Unified Coverage Report :: Module :: pattgen

Module : pattgen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pattgen_0.1/rtl/pattgen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pattgen	90.00			90.00

---

Module Instance : tb.dut.top_earlgrey.u_pattgen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.02	90.65		91.41			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : pattgen

	Total	Covered	Percent
Totals	35	27	77.14
Total Bits	300	270	90.00
Total Bits 0->1	150	135	90.00
Total Bits 1->0	150	135	90.00

Ports	35	27	77.14
Port Bits	300	270	90.00
Port Bits 0->1	150	135	90.00
Port Bits 1->0	150	135	90.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T98,T52,T180	Yes	T98,T52,T180	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T98,T52,T180	Yes	T98,T52,T180	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19:17]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T70,*T52,*T44	Yes	T70,T52,T44	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T98,T54,T52	Yes	T98,T54,T52	INPUT
tl_o.a_ready	Yes	Yes	T98,T54,T52	Yes	T98,T54,T52	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T98,T52,T180	Yes	T98,T52,T180	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T98,T52,T180	Yes	T98,T54,T52	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T52,T53,*T98	Yes	T98,T54,T52	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T98,T52,T180	Yes	T98,T54,T52	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T52,*T53,*T312	Yes	T52,T53,T98	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T52,T53	Yes	T98,T54,T52	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T98,*T52,*T180	Yes	T98,T52,T180	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T98,T54,T52	Yes	T98,T54,T52	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T318,T212,T319	Yes	T318,T212,T319	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T212,T78,T79	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T80	Yes	T212,T78,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T318,T212,T319	Yes	T318,T212,T319	OUTPUT
cio_pda0_tx_o	Yes	Yes	T320,T321	Yes	T320,T321	OUTPUT
cio_pcl0_tx_o	Yes	Yes	T52,T320,T321	Yes	T52,T320,T321	OUTPUT
cio_pda1_tx_o	Yes	Yes	T312,T320,T321	Yes	T312,T320,T321	OUTPUT
cio_pcl1_tx_o	Yes	Yes	T312,T320,T321	Yes	T312,T320,T321	OUTPUT
cio_pda0_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pcl0_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pda1_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pcl1_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_done_ch0_o	Yes	Yes	T98,T180,T320	Yes	T98,T180,T320	OUTPUT
intr_done_ch1_o	Yes	Yes	T98,T180,T312	Yes	T98,T180,T312	OUTPUT

*Tests covering at least one bit in the range