Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.89			80.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	80.89			80.89

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.89			80.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.89			80.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.02	90.65		91.41			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	299	54.36
Total Bits	6824	5520	80.89
Total Bits 0->1	3412	2761	80.92
Total Bits 1->0	3412	2759	80.86

Ports	550	299	54.36
Port Bits	6824	5520	80.89
Port Bits 0->1	3412	2761	80.92
Port Bits 1->0	3412	2759	80.86

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[5:3]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T77,T69,T106	Yes	T77,T69,T106	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0]	Yes	Yes	*T77,*T69,*T106	Yes	T77,T69,T106	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T70,T52,T44	Yes	T70,T52,T44	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T107,T108,T31	Yes	T107,T108,T31	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T107,T108,T30	Yes	T107,T108,T30	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_opcode[1]	No	No		No		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T62,T77,T69	Yes	T62,T77,T69	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T3,T4,T20	Yes	T2,T3,T4	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T20	Yes	T2,T3,T4	INPUT
tl_rv_dm__sba_i.a_user.instr_type[0]	Yes	Yes	*T3,*T4,*T20	Yes	T2,T3,T4	INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_rv_dm__sba_i.a_user.instr_type[3]	Yes	Yes	T3,T4,T20	Yes	T2,T3,T4	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T3,T4,T20	Yes	T2,T3,T4	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_size[1]	Yes	Yes	T3,T4,T20	Yes	T2,T3,T4	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[1:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_opcode[2]	Yes	Yes	T3,T4,T20	Yes	T2,T3,T4	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0]	Yes	Yes	T70,T71,T109	Yes	T70,T71,T109	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3]	Yes	Yes	*T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__sba_o.d_sink	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_size[1]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[1:0]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[2]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[3]	Yes	Yes	*T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[4]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:5]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[4:2]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[5]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[0]	Yes	Yes	*T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[0]	Yes	Yes	*T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_data[3:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[6:4]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_data[7]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[8]	Yes	Yes	*T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_data[9]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[11:10]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_data[12]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[13]	Yes	Yes	*T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_data[15:14]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[19:16]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_data[21:20]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[23:22]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_data[25:24]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[26]	Yes	Yes	*T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_data[27]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[28]	Yes	Yes	*T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_data[30:29]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[31]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[0]	Yes	Yes	*T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_source[5:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_size[1]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_opcode[2]	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T44	Yes	T44	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T44	Yes	T44	INPUT
tl_rv_dm__regs_i.d_error	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T44	Yes	T44	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T44	Yes	T44	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T44	Yes	T44	INPUT
tl_rv_dm__regs_i.d_sink	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[0]	Yes	Yes	*T44	Yes	T44	INPUT
tl_rv_dm__regs_i.d_source[5:1]	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_size[1]	Yes	Yes	T44	Yes	T44	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T44	Yes	T44	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T44	Yes	T44	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T69,T76,T44	Yes	T69,T76,T44	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T76,T44	Yes	T69,T76,T44	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T69,T76,T44	Yes	T69,T76,T44	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T69,T76,T44	Yes	T69,T76,T44	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T69,T76,T44	Yes	T69,T76,T44	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[4:0]	Yes	Yes	*T69,*T76,*T110	Yes	T69,T76,T110	OUTPUT
tl_rv_dm__mem_o.a_source[5]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_size[1]	Yes	Yes	T69,T76,T44	Yes	T69,T76,T44	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_opcode[2]	Yes	Yes	T69,T76,T44	Yes	T69,T76,T44	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T69,T76,T44	Yes	T69,T76,T44	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T2,T3,T4	Yes	T3,T4,T20	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T69,T76,T110	Yes	T69,T76,T110	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	*T69,*T76,*T44	Yes	T69,T76,T44	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4]	Yes	Yes	*T69,*T76,*T44	Yes	T69,T76,T44	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T3,T4,T20	INPUT
tl_rv_dm__mem_i.d_sink	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[4:0]	Yes	Yes	*T69,*T76,*T110	Yes	T69,T76,T110	INPUT
tl_rv_dm__mem_i.d_source[5]	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__mem_i.d_size[1]	Yes	Yes	T69,T76,T44	Yes	T69,T76,T44	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T3,T4,T20	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T69,T76,T44	Yes	T69,T76,T44	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T6,T38	Yes	T1,T6,T38	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T111,T70,T112	Yes	T111,T70,T112	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[5]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T54,T55,T44	Yes	T54,T55,T44	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T113,T55	Yes	T54,T113,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0]	Yes	Yes	*T54,*T113,*T55	Yes	T54,T113,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3]	Yes	Yes	T54,T113,T55	Yes	T54,T113,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T54,T55,T44	Yes	T54,T55,T44	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T54,T113,T55	Yes	T54,T113,T55	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[1:0]	Yes	Yes	*T44,*T113,*T114	Yes	T44,T113,T114	OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_size[1]	Yes	Yes	T54,T113,T55	Yes	T54,T113,T55	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2]	Yes	Yes	T113,T114,T44	Yes	T113,T114,T44	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T54,T113,T55	Yes	T54,T113,T55	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T54,T113,T55	Yes	T54,T113,T55	INPUT
tl_rom_ctrl__regs_i.d_error	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T113,T114,T115	Yes	T113,T114,T115	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T44,*T54,*T55	Yes	T54,T55,T44	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T114,T44,T116	Yes	T54,T113,T55	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T113,T114,T44	Yes	T54,T113,T55	INPUT
tl_rom_ctrl__regs_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[1:0]	Yes	Yes	*T44,*T113,*T114	Yes	T44,T113,T114	INPUT
tl_rom_ctrl__regs_i.d_source[5:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_size[1]	Yes	Yes	T114,T44,T116	Yes	T54,T113,T55	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T114,*T44,*T116	Yes	T113,T114,T44	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T54,T113,T55	Yes	T54,T113,T55	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_peri_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[0]	Yes	Yes	*T70,*T52,*T44	Yes	T70,T52,T44	OUTPUT
tl_peri_o.a_opcode[1]	No	No		No		OUTPUT
tl_peri_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T63,T117,T118	Yes	T63,T117,T118	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	No	No		No		INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0]	Yes	Yes	*T10,*T98,*T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2]	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_o.a_user.instr_type[0]	Yes	Yes	*T10,*T98,*T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.instr_type[3]	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[1:0]	Yes	Yes	*T53,*T10,*T119	Yes	T53,T10,T119	OUTPUT
tl_spi_host0_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host0_o.a_size[1]	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[0]	Yes	Yes	*T120,*T121,*T122	Yes	T120,T121,T122	OUTPUT
tl_spi_host0_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_opcode[2]	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	INPUT
tl_spi_host0_i.d_error	No	No		No		INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0]	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4]	Yes	Yes	T10,T119,*T123	Yes	T10,T98,T119	INPUT
tl_spi_host0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	INPUT
tl_spi_host0_i.d_sink	No	No		No		INPUT
tl_spi_host0_i.d_source[1:0]	Yes	Yes	*T53,*T10,*T119	Yes	T53,T10,T119	INPUT
tl_spi_host0_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[0]	No	No		No		INPUT
tl_spi_host0_i.d_size[1]	Yes	Yes	T10,T119,T123	Yes	T10,T98,T119	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T98,*T119	Yes	T10,T98,T119	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T10,T98,T119	Yes	T10,T98,T119	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	OUTPUT
tl_spi_host1_o.a_user.instr_type[0]	Yes	Yes	*T98,*T119,*T124	Yes	T98,T119,T124	OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host1_o.a_user.instr_type[3]	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[1:0]	Yes	Yes	*T53,*T98,*T119	Yes	T53,T98,T119	OUTPUT
tl_spi_host1_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host1_o.a_size[1]	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_opcode[2]	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	INPUT
tl_spi_host1_i.d_error	No	No		No		INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0]	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4]	Yes	Yes	T119,T124,T125	Yes	T98,T119,T124	INPUT
tl_spi_host1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	INPUT
tl_spi_host1_i.d_sink	No	No		No		INPUT
tl_spi_host1_i.d_source[1:0]	Yes	Yes	*T53,*T98,*T119	Yes	T53,T98,T119	INPUT
tl_spi_host1_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[0]	No	No		No		INPUT
tl_spi_host1_i.d_size[1]	Yes	Yes	T119,T124,T125	Yes	T98,T119,T124	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T98,*T119,*T124	Yes	T98,T119,T124	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T98,T119,T124	Yes	T98,T119,T124	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_o.a_user.instr_type[0]	Yes	Yes	*T126,*T119,*T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_usbdev_o.a_user.instr_type[3]	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[0]	No	No		No		OUTPUT
tl_usbdev_o.a_source[1]	Yes	Yes	*T126,*T119,*T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_o.a_source[5:2]	No	No		No		OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[0]	No	No		No		OUTPUT
tl_usbdev_o.a_size[1]	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_usbdev_o.a_opcode[2]	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	INPUT
tl_usbdev_i.d_error	No	No		No		INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	INPUT
tl_usbdev_i.d_user.rsp_intg[1:0]	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	INPUT
tl_usbdev_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_usbdev_i.d_user.rsp_intg[5:4]	Yes	Yes	T119,T16,T124	Yes	T126,T119,T16	INPUT
tl_usbdev_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	INPUT
tl_usbdev_i.d_sink	No	No		No		INPUT
tl_usbdev_i.d_source[0]	No	No		No		INPUT
tl_usbdev_i.d_source[1]	Yes	Yes	*T126,*T119,*T16	Yes	T126,T119,T16	INPUT
tl_usbdev_i.d_source[5:2]	No	No		No		INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[0]	No	No		No		INPUT
tl_usbdev_i.d_size[1]	Yes	Yes	T119,T16,T124	Yes	T126,T119,T16	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T126,*T119,*T16	Yes	T126,T119,T16	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T126,T119,T16	Yes	T126,T119,T16	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_source[1]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_source[5:2]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_size[1]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T20	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[1]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_size[1]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_valid	No	No		No		OUTPUT
tl_flash_ctrl__prim_i.a_ready	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_error	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	No	No		No		INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[1]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[5]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_size[1]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T20	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[1]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[4:2]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_size[1]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_hmac_o.a_user.instr_type[0]	Yes	Yes	*T6,*T38,*T40	Yes	T6,T38,T40	OUTPUT
tl_hmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_hmac_o.a_user.instr_type[3]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[0]	No	No		No		OUTPUT
tl_hmac_o.a_source[1]	Yes	Yes	*T6,*T38,*T40	Yes	T6,T38,T40	OUTPUT
tl_hmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[0]	No	No		No		OUTPUT
tl_hmac_o.a_size[1]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[0]	Yes	Yes	*T104,*T127,*T128	Yes	T104,T127,T128	OUTPUT
tl_hmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_hmac_o.a_opcode[2]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	INPUT
tl_hmac_i.d_error	No	No		No		INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	INPUT
tl_hmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	INPUT
tl_hmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_hmac_i.d_user.rsp_intg[5:4]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	INPUT
tl_hmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	INPUT
tl_hmac_i.d_sink	No	No		No		INPUT
tl_hmac_i.d_source[0]	No	No		No		INPUT
tl_hmac_i.d_source[1]	Yes	Yes	*T6,*T38,*T40	Yes	T6,T38,T40	INPUT
tl_hmac_i.d_source[5:2]	No	No		No		INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[0]	No	No		No		INPUT
tl_hmac_i.d_size[1]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T6,*T38,*T40	Yes	T6,T38,T40	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	INPUT
tl_kmac_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T81,T129,T98	Yes	T81,T129,T98	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T81,T5,T130	Yes	T81,T5,T130	OUTPUT
tl_kmac_o.a_user.instr_type[0]	Yes	Yes	*T81,*T5,*T130	Yes	T81,T5,T130	OUTPUT
tl_kmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_kmac_o.a_user.instr_type[3]	Yes	Yes	T81,T5,T130	Yes	T81,T5,T130	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T81,T129,T98	Yes	T81,T129,T98	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T81,T5,T130	Yes	T81,T5,T130	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[1:0]	Yes	Yes	*T52,*T53,*T81	Yes	T52,T53,T81	OUTPUT
tl_kmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[0]	No	No		No		OUTPUT
tl_kmac_o.a_size[1]	Yes	Yes	T81,T5,T130	Yes	T81,T5,T130	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[0]	Yes	Yes	*T81,*T92,*T131	Yes	T81,T92,T131	OUTPUT
tl_kmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_kmac_o.a_opcode[2]	Yes	Yes	T81,T5,T130	Yes	T81,T5,T130	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T81,T5,T130	Yes	T81,T5,T130	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T81,T5,T130	Yes	T81,T5,T130	INPUT
tl_kmac_i.d_error	No	No		No		INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T81,T5,T130	Yes	T81,T5,T130	INPUT
tl_kmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T81,T5,T130	Yes	T81,T5,T130	INPUT
tl_kmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_kmac_i.d_user.rsp_intg[5:4]	Yes	Yes	T81,T5,T132	Yes	T81,T5,T130	INPUT
tl_kmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T81,T5,T130	Yes	T81,T5,T129	INPUT
tl_kmac_i.d_sink	No	No		No		INPUT
tl_kmac_i.d_source[1:0]	Yes	Yes	*T52,*T53,*T81	Yes	T52,T53,T81	INPUT
tl_kmac_i.d_source[5:2]	No	No		No		INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[0]	No	No		No		INPUT
tl_kmac_i.d_size[1]	Yes	Yes	T81,T5,T132	Yes	T81,T5,T130	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T81,*T5,*T130	Yes	T81,T5,T132	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T81,T5,T130	Yes	T81,T5,T130	INPUT
tl_aes_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	OUTPUT
tl_aes_o.a_user.cmd_intg[0]	Yes	Yes	*T105,*T95,*T133	Yes	T105,T95,T133	OUTPUT
tl_aes_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_aes_o.a_user.cmd_intg[6:2]	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	OUTPUT
tl_aes_o.a_user.instr_type[0]	Yes	Yes	*T105,*T95,*T133	Yes	T105,T95,T133	OUTPUT
tl_aes_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aes_o.a_user.instr_type[3]	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[0]	No	No		No		OUTPUT
tl_aes_o.a_source[1]	Yes	Yes	*T105,*T95,*T133	Yes	T105,T95,T133	OUTPUT
tl_aes_o.a_source[5:2]	No	No		No		OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[0]	No	No		No		OUTPUT
tl_aes_o.a_size[1]	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_aes_o.a_opcode[2]	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	INPUT
tl_aes_i.d_error	No	No		No		INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	INPUT
tl_aes_i.d_user.rsp_intg[1:0]	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	INPUT
tl_aes_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aes_i.d_user.rsp_intg[5:4]	Yes	Yes	T134,T135,T136	Yes	T105,T95,T133	INPUT
tl_aes_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	INPUT
tl_aes_i.d_sink	No	No		No		INPUT
tl_aes_i.d_source[0]	No	No		No		INPUT
tl_aes_i.d_source[1]	Yes	Yes	*T105,*T95,*T133	Yes	T105,T95,T133	INPUT
tl_aes_i.d_source[5:2]	No	No		No		INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[0]	No	No		No		INPUT
tl_aes_i.d_size[1]	Yes	Yes	T134,T135,T136	Yes	T105,T95,T133	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T105,*T95,*T133	Yes	T105,T95,T133	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T105,T95,T133	Yes	T105,T95,T133	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_entropy_src_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[0]	No	No		No		OUTPUT
tl_entropy_src_o.a_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_source[5:2]	No	No		No		OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[0]	No	No		No		OUTPUT
tl_entropy_src_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_opcode[2]	Yes	Yes	T137,T40,T138	Yes	T137,T40,T138	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	No	No		No		INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4]	Yes	Yes	*T3,*T4,*T20	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	No	No		No		INPUT
tl_entropy_src_i.d_source[0]	No	No		No		INPUT
tl_entropy_src_i.d_source[1]	Yes	Yes	*T3,*T4,*T20	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_source[5:2]	No	No		No		INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[0]	No	No		No		INPUT
tl_entropy_src_i.d_size[1]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T137,*T138,*T95	Yes	T137,T40,T138	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_csrng_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T139,T137,T138	Yes	T139,T137,T138	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[0]	No	No		No		OUTPUT
tl_csrng_o.a_source[1]	Yes	Yes	*T6,*T38,*T139	Yes	T6,T38,T139	OUTPUT
tl_csrng_o.a_source[5:2]	No	No		No		OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[0]	No	No		No		OUTPUT
tl_csrng_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_csrng_o.a_opcode[2]	Yes	Yes	T139,T137,T138	Yes	T139,T137,T138	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	No	No		No		INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T139,T137,T138	Yes	T139,T137,T138	INPUT
tl_csrng_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_csrng_i.d_user.rsp_intg[5:4]	Yes	Yes	*T3,*T4,*T20	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	No	No		No		INPUT
tl_csrng_i.d_source[0]	No	No		No		INPUT
tl_csrng_i.d_source[1]	Yes	Yes	*T6,*T38,*T139	Yes	T6,T38,T139	INPUT
tl_csrng_i.d_source[5:2]	No	No		No		INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[0]	No	No		No		INPUT
tl_csrng_i.d_size[1]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T139,*T137,*T138	Yes	T139,T137,T138	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn0_o.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[0]	No	No		No		OUTPUT
tl_edn0_o.a_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[0]	No	No		No		OUTPUT
tl_edn0_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn0_o.a_opcode[2]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	No	No		No		INPUT
tl_edn0_i.d_user.data_intg[0]	Yes	Yes	*T137,*T138,*T95	Yes	T137,T138,T95	INPUT
tl_edn0_i.d_user.data_intg[1]	No	No		No		INPUT
tl_edn0_i.d_user.data_intg[6:2]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	INPUT
tl_edn0_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn0_i.d_user.rsp_intg[5:4]	Yes	Yes	*T3,*T4,*T20	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	No	No		No		INPUT
tl_edn0_i.d_source[0]	No	No		No		INPUT
tl_edn0_i.d_source[1]	Yes	Yes	*T3,*T4,*T20	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_source[5:2]	No	No		No		INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[0]	No	No		No		INPUT
tl_edn0_i.d_size[1]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T137,*T138,*T95	Yes	T137,T138,T95	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_o.a_user.cmd_intg[0]	Yes	Yes	*T137,*T138,*T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_o.a_user.instr_type[0]	Yes	Yes	*T137,*T138,*T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn1_o.a_user.instr_type[3]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[0]	No	No		No		OUTPUT
tl_edn1_o.a_source[1]	Yes	Yes	*T137,*T138,*T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[0]	No	No		No		OUTPUT
tl_edn1_o.a_size[1]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn1_o.a_opcode[2]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	INPUT
tl_edn1_i.d_error	No	No		No		INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	INPUT
tl_edn1_i.d_user.rsp_intg[1:0]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	INPUT
tl_edn1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn1_i.d_user.rsp_intg[4]	No	No		Yes	T137,T138,T95	INPUT
tl_edn1_i.d_user.rsp_intg[5]	Yes	Yes	*T137,*T138,*T95	Yes	T137,T138,T95	INPUT
tl_edn1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	INPUT
tl_edn1_i.d_sink	No	No		No		INPUT
tl_edn1_i.d_source[0]	No	No		No		INPUT
tl_edn1_i.d_source[1]	Yes	Yes	*T137,*T138,*T95	Yes	T137,T138,T95	INPUT
tl_edn1_i.d_source[5:2]	No	No		No		INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[0]	No	No		No		INPUT
tl_edn1_i.d_size[1]	No	No		Yes	T137,T138,T95	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T137,*T138,*T95	Yes	T137,T138,T95	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T137,T138,T95	Yes	T137,T138,T95	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T3,T4,T50	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	OUTPUT
tl_rv_plic_o.a_user.instr_type[0]	Yes	Yes	*T50,*T51,*T140	Yes	T50,T51,T140	OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_plic_o.a_user.instr_type[3]	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[1:0]	Yes	Yes	*T53,*T50,*T51	Yes	T53,T50,T51	OUTPUT
tl_rv_plic_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[0]	No	No		No		OUTPUT
tl_rv_plic_o.a_size[1]	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_opcode[2]	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	INPUT
tl_rv_plic_i.d_error	No	No		No		INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0]	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4]	Yes	Yes	T68,T141,*T62	Yes	T50,T51,T140	INPUT
tl_rv_plic_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	INPUT
tl_rv_plic_i.d_sink	No	No		No		INPUT
tl_rv_plic_i.d_source[1:0]	Yes	Yes	*T53,*T50,*T51	Yes	T53,T50,T51	INPUT
tl_rv_plic_i.d_source[5:2]	No	No		No		INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[0]	No	No		No		INPUT
tl_rv_plic_i.d_size[1]	Yes	Yes	T68,T141,T62	Yes	T50,T51,T140	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T50,*T51,*T140	Yes	T50,T51,T140	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T50,T51,T140	Yes	T50,T51,T140	INPUT
tl_otbn_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	OUTPUT
tl_otbn_o.a_user.instr_type[0]	Yes	Yes	*T6,*T38,*T137	Yes	T6,T38,T137	OUTPUT
tl_otbn_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otbn_o.a_user.instr_type[3]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[1:0]	Yes	Yes	*T70,*T52,*T107	Yes	T70,T52,T107	OUTPUT
tl_otbn_o.a_source[5:2]	No	No		No		OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[0]	No	No		No		OUTPUT
tl_otbn_o.a_size[1]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_otbn_o.a_opcode[2]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	INPUT
tl_otbn_i.d_error	No	No		No		INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	INPUT
tl_otbn_i.d_user.rsp_intg[1:0]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	INPUT
tl_otbn_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otbn_i.d_user.rsp_intg[5:4]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	INPUT
tl_otbn_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	INPUT
tl_otbn_i.d_sink	No	No		No		INPUT
tl_otbn_i.d_source[1:0]	Yes	Yes	*T70,*T52,*T107	Yes	T70,T52,T107	INPUT
tl_otbn_i.d_source[5:2]	No	No		No		INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[0]	No	No		No		INPUT
tl_otbn_i.d_size[1]	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T6,*T38,*T137	Yes	T6,T38,T137	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T6,T38,T137	Yes	T6,T38,T137	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_o.a_user.cmd_intg[0]	Yes	Yes	*T33,*T5,*T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2]	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_o.a_user.instr_type[0]	Yes	Yes	*T33,*T5,*T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.instr_type[3]	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[0]	No	No		No		OUTPUT
tl_keymgr_o.a_source[1]	Yes	Yes	*T33,*T5,*T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_o.a_source[5:2]	No	No		No		OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[0]	No	No		No		OUTPUT
tl_keymgr_o.a_size[1]	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_keymgr_o.a_opcode[2]	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	INPUT
tl_keymgr_i.d_error	No	No		No		INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	INPUT
tl_keymgr_i.d_user.rsp_intg[1:0]	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	INPUT
tl_keymgr_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_keymgr_i.d_user.rsp_intg[5:4]	Yes	Yes	T33,T5,T132	Yes	T33,T5,T130	INPUT
tl_keymgr_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	INPUT
tl_keymgr_i.d_sink	No	No		No		INPUT
tl_keymgr_i.d_source[0]	No	No		No		INPUT
tl_keymgr_i.d_source[1]	Yes	Yes	*T33,*T5,*T130	Yes	T33,T5,T130	INPUT
tl_keymgr_i.d_source[5:2]	No	No		No		INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[0]	No	No		No		INPUT
tl_keymgr_i.d_size[1]	Yes	Yes	T33,T5,T132	Yes	T33,T5,T130	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T33,*T5,*T130	Yes	T33,T5,T130	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T33,T5,T130	Yes	T33,T5,T130	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1:0]	Yes	Yes	*T44,*T1,*T2	Yes	T44,T1,T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T44	Yes	T44	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T51,T142,T143	Yes	T51,T142,T143	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[2:0]	Yes	Yes	*T2,*T3,*T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T51,T142,T143	Yes	T51,T142,T143	INPUT
tl_rv_core_ibex__cfg_i.d_sink	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[1:0]	Yes	Yes	*T44,*T1,*T2	Yes	T44,T1,T2	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[0]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_size[1]	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T6,*T38,*T40	Yes	T6,T38,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2]	Yes	Yes	T144,T145,T146	Yes	T144,T145,T146	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0]	Yes	Yes	*T6,*T38,*T40	Yes	T6,T38,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0]	Yes	Yes	*T53,*T144,*T145	Yes	T53,T144,T145	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1]	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2]	Yes	Yes	T144,T145,T146	Yes	T144,T145,T146	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	INPUT
tl_sram_ctrl_main__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[3:0]	Yes	Yes	*T53,*T144,*T146	Yes	T53,T144,T146	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[4]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5]	Yes	Yes	*T144,*T146,*T147	Yes	T144,T146,T147	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T6,T38,T144	Yes	T6,T38,T40	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	*T6,*T38,T144	Yes	T6,T38,T40	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T6,T38,T144	Yes	T6,T38,T40	INPUT
tl_sram_ctrl_main__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[1:0]	Yes	Yes	*T53,*T144,*T146	Yes	T53,T144,T145	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_size[1]	Yes	Yes	T6,T38,T144	Yes	T6,T38,T40	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T144,*T146,*T147	Yes	T144,T145,T146	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T6,T38,T40	Yes	T6,T38,T40	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T20	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[5]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range