Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.61 95.61

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 92.54 92.54
tb.dut.top_earlgrey.u_edn0 95.35 95.35


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.54 92.54


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.54 92.54


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.02 90.65 91.41 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.35 95.35


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.35 95.35


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.02 90.65 91.41 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 63 80.77
Total Bits 1206 1153 95.61
Total Bits 0->1 603 578 95.85
Total Bits 1->0 603 575 95.36

Ports 78 63 80.77
Port Bits 1206 1153 95.61
Port Bits 0->1 603 578 95.85
Port Bits 1->0 603 575 95.36

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T20 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T3,T4,T20 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T3,*T4,*T20 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T3,T4,T20 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T3,*T4,*T20 Yes T1,T2,T3 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T3,T4,T20 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T33,T5,T130 Yes T33,T5,T130 INPUT
edn_i[1].edn_req Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
edn_i[2].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T302,T303,T384 Yes T302,T303,T384 INPUT
edn_i[4].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T33,T5,T130 Yes T33,T5,T130 OUTPUT
edn_o[0].edn_fips Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
edn_o[0].edn_ack Yes Yes T33,T5,T130 Yes T33,T5,T130 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[1].edn_fips No No Yes T164,T165,T182 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T4,T50 Yes T2,T4,T50 OUTPUT
edn_o[2].edn_fips Yes Yes T161,T162,T163 Yes T164,T165,T166 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T302,T303,T384 Yes T302,T303,T384 OUTPUT
edn_o[3].edn_fips No No Yes T302,T303,T385 OUTPUT
edn_o[3].edn_ack Yes Yes T302,T303,T384 Yes T302,T303,T384 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T20,T33,T5 Yes T50,T20,T81 OUTPUT
edn_o[4].edn_fips No No Yes T165,T386,T387 OUTPUT
edn_o[4].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_fips Yes Yes T95,T133,T388 Yes T95,T133,T302 OUTPUT
edn_o[5].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_fips Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
edn_o[6].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T50,T140 OUTPUT
edn_o[7].edn_fips Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
edn_o[7].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T3,T4,T20 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.genbits_fips Yes Yes T208,T209,T210 Yes T137,T138,T95 INPUT
csrng_cmd_i.genbits_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T141,T389,T78 Yes T141,T389,T78 INPUT
alert_rx_i[0].ping_n Yes Yes T141,T78,T79 Yes T141,T78,T79 INPUT
alert_rx_i[0].ping_p Yes Yes T141,T78,T79 Yes T141,T78,T79 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T317,T276,T78 Yes T317,T276,T78 INPUT
alert_rx_i[1].ping_n Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[1].ping_p Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T141,T389,T78 Yes T141,T389,T78 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T317,T276,T78 Yes T317,T276,T78 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T340,T341,T213 Yes T340,T341,T213 OUTPUT
intr_edn_fatal_err_o Yes Yes T213,T214,T215 Yes T213,T214,T215 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 37 74.00
Total Bits 710 657 92.54
Total Bits 0->1 355 330 92.96
Total Bits 1->0 355 327 92.11

Ports 50 37 74.00
Port Bits 710 657 92.54
Port Bits 0->1 355 330 92.96
Port Bits 1->0 355 327 92.11

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T20 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T3,T4,T20 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_mask[3:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_valid Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_o.a_ready Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[4] No No Yes T137,T138,T95 OUTPUT
tl_o.d_user.rsp_intg[5] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] No No Yes T137,T138,T95 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
edn_i[0].edn_req Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
edn_o[0].edn_fips Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
edn_o[0].edn_ack Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
csrng_cmd_i.genbits_fips No No Yes T208,T209,T210 INPUT
csrng_cmd_i.genbits_valid Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T78,T54,T79 Yes T78,T54,T79 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T78,T54,T79 Yes T78,T54,T79 INPUT
alert_rx_i[1].ping_n Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[1].ping_p Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T78,T54,T79 Yes T78,T54,T79 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T78,T54,T79 Yes T78,T54,T79 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T340,T341,T213 Yes T340,T341,T213 OUTPUT
intr_edn_fatal_err_o Yes Yes T213,T214,T215 Yes T213,T214,T215 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 61 78.21
Total Bits 1204 1148 95.35
Total Bits 0->1 602 576 95.68
Total Bits 1->0 602 572 95.02

Ports 78 61 78.21
Port Bits 1204 1148 95.35
Port Bits 0->1 602 576 95.68
Port Bits 1->0 602 572 95.02

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T20 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[0] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 OUTPUT
tl_o.d_user.data_intg[1] No No No OUTPUT
tl_o.d_user.data_intg[6:2] Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T3,T4,T20 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T3,*T4,*T20 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T3,T4,T20 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T3,*T4,*T20 Yes T1,T2,T3 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T3,T4,T20 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T137,*T138,*T95 Yes T137,T138,T95 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T33,T5,T130 Yes T33,T5,T130 INPUT
edn_i[1].edn_req Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
edn_i[2].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T302,T303,T384 Yes T302,T303,T384 INPUT
edn_i[4].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T33,T5,T130 Yes T33,T5,T130 OUTPUT
edn_o[0].edn_fips No No Yes T302,T303,T292 OUTPUT
edn_o[0].edn_ack Yes Yes T33,T5,T130 Yes T33,T5,T130 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[1].edn_fips No No Yes T164,T165,T182 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T4,T50 Yes T2,T4,T50 OUTPUT
edn_o[2].edn_fips Yes Yes T161,T162,T163 Yes T164,T165,T166 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T302,T303,T384 Yes T302,T303,T384 OUTPUT
edn_o[3].edn_fips No No Yes T302,T303,T385 OUTPUT
edn_o[3].edn_ack Yes Yes T302,T303,T384 Yes T302,T303,T384 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T20,T33,T5 Yes T50,T20,T81 OUTPUT
edn_o[4].edn_fips No No Yes T165,T386,T387 OUTPUT
edn_o[4].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[5].edn_fips Yes Yes T95,T133,T388 Yes T95,T133,T302 OUTPUT
edn_o[5].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[6].edn_fips Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
edn_o[6].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T50,T140 OUTPUT
edn_o[7].edn_fips Yes Yes T137,T138,T95 Yes T137,T138,T95 OUTPUT
edn_o[7].edn_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T3,T4,T20 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.genbits_fips Yes Yes T208,T209,T210 Yes T137,T138,T95 INPUT
csrng_cmd_i.genbits_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T137,T138,T95 Yes T137,T138,T95 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T141,T389,T78 Yes T141,T389,T78 INPUT
alert_rx_i[0].ping_n Yes Yes T141,T78,T79 Yes T141,T78,T79 INPUT
alert_rx_i[0].ping_p Yes Yes T141,T78,T79 Yes T141,T78,T79 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T317,T276,T78 Yes T317,T276,T78 INPUT
alert_rx_i[1].ping_n Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[1].ping_p Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T141,T389,T78 Yes T141,T389,T78 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T317,T276,T78 Yes T317,T276,T78 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T340,T341,T213 Yes T340,T341,T213 OUTPUT
intr_edn_fatal_err_o Yes Yes T213,T214,T215 Yes T213,T214,T215 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%