Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=10,ResetVal=0,BitMask=769,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=1,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T13,T25,T43 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T25,T43 |
1 | 1 | Covered | T13,T25,T43 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T25,T42 |
1 | 0 | Covered | T13,T25,T43 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T13,T25,T43 |
1 | 1 | Covered | T13,T25,T43 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T13,T25,T42 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T13,T25,T42 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T25,T42 |
1 | 1 | Covered | T13,T25,T42 |
LINE 112
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T13,T25,T42 |
1 | - | Covered | T13,T25,T42 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T13,T25,T42 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T13,T25,T42 |
1 | 1 | Covered | T13,T25,T42 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T13,T25,T43 |
0 |
0 |
1 |
Covered |
T13,T25,T43 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T13,T25,T43 |
0 |
0 |
1 |
Covered |
T13,T25,T43 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
22128 |
0 |
0 |
T13 |
92672 |
4145 |
0 |
0 |
T14 |
540414 |
0 |
0 |
0 |
T25 |
0 |
2666 |
0 |
0 |
T42 |
38692 |
1344 |
0 |
0 |
T43 |
0 |
295 |
0 |
0 |
T44 |
240934 |
7405 |
0 |
0 |
T45 |
0 |
332 |
0 |
0 |
T46 |
0 |
1278 |
0 |
0 |
T47 |
0 |
1120 |
0 |
0 |
T48 |
0 |
3288 |
0 |
0 |
T49 |
0 |
255 |
0 |
0 |
T78 |
35233 |
0 |
0 |
0 |
T98 |
88204 |
0 |
0 |
0 |
T99 |
79468 |
0 |
0 |
0 |
T100 |
178592 |
0 |
0 |
0 |
T101 |
69560 |
0 |
0 |
0 |
T102 |
73388 |
0 |
0 |
0 |
T103 |
1015258 |
0 |
0 |
0 |
T104 |
51200 |
0 |
0 |
0 |
T105 |
45972 |
0 |
0 |
0 |
T124 |
21468 |
0 |
0 |
0 |
T203 |
35312 |
0 |
0 |
0 |
T222 |
223264 |
0 |
0 |
0 |
T319 |
41605 |
0 |
0 |
0 |
T340 |
111049 |
0 |
0 |
0 |
T400 |
118994 |
0 |
0 |
0 |
T401 |
59082 |
0 |
0 |
0 |
T402 |
40248 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
33395700 |
29049100 |
0 |
0 |
T1 |
9100 |
5000 |
0 |
0 |
T2 |
24975 |
20925 |
0 |
0 |
T3 |
30600 |
26500 |
0 |
0 |
T4 |
133000 |
105950 |
0 |
0 |
T20 |
98375 |
94300 |
0 |
0 |
T33 |
23975 |
19850 |
0 |
0 |
T50 |
23175 |
19075 |
0 |
0 |
T51 |
24750 |
20675 |
0 |
0 |
T67 |
18625 |
14550 |
0 |
0 |
T81 |
7975 |
3875 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
60 |
0 |
0 |
T13 |
92672 |
9 |
0 |
0 |
T14 |
540414 |
0 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T42 |
38692 |
3 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
240934 |
25 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
0 |
3 |
0 |
0 |
T48 |
0 |
8 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T78 |
35233 |
0 |
0 |
0 |
T98 |
88204 |
0 |
0 |
0 |
T99 |
79468 |
0 |
0 |
0 |
T100 |
178592 |
0 |
0 |
0 |
T101 |
69560 |
0 |
0 |
0 |
T102 |
73388 |
0 |
0 |
0 |
T103 |
1015258 |
0 |
0 |
0 |
T104 |
51200 |
0 |
0 |
0 |
T105 |
45972 |
0 |
0 |
0 |
T124 |
21468 |
0 |
0 |
0 |
T203 |
35312 |
0 |
0 |
0 |
T222 |
223264 |
0 |
0 |
0 |
T319 |
41605 |
0 |
0 |
0 |
T340 |
111049 |
0 |
0 |
0 |
T400 |
118994 |
0 |
0 |
0 |
T401 |
59082 |
0 |
0 |
0 |
T402 |
40248 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
340225 |
329450 |
0 |
0 |
T2 |
2397775 |
2383050 |
0 |
0 |
T3 |
1272375 |
1259350 |
0 |
0 |
T4 |
6722275 |
6576225 |
0 |
0 |
T20 |
10578450 |
10568400 |
0 |
0 |
T33 |
1703375 |
1692400 |
0 |
0 |
T50 |
2077025 |
2065275 |
0 |
0 |
T51 |
2195950 |
2186925 |
0 |
0 |
T67 |
1546400 |
1536075 |
0 |
0 |
T81 |
470300 |
449225 |
0 |
0 |