SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
67.66 | 92.41 | 50.91 | 50.85 | 76.47 | u_pinmux_strap_sampling |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
prim_buf_tdi | 0.00 | 0.00 | |||||
prim_buf_tdo | 0.00 | 0.00 | |||||
prim_buf_tdo_oe | 0.00 | 0.00 | |||||
prim_buf_tms | 0.00 | 0.00 | |||||
prim_buf_trst_n | 0.00 | 0.00 | |||||
prim_clock_buf_tck | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
67.66 | 92.41 | 50.91 | 50.85 | 76.47 | u_pinmux_strap_sampling |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
prim_buf_tdi | 0.00 | 0.00 | |||||
prim_buf_tdo | 0.00 | 0.00 | |||||
prim_buf_tdo_oe | 0.00 | 0.00 | |||||
prim_buf_tms | 0.00 | 0.00 | |||||
prim_buf_trst_n | 0.00 | 0.00 | |||||
prim_clock_buf_tck | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
67.66 | 92.41 | 50.91 | 50.85 | 76.47 | u_pinmux_strap_sampling |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
prim_buf_tdi | 0.00 | 0.00 | |||||
prim_buf_tdo | 0.00 | 0.00 | |||||
prim_buf_tdo_oe | 0.00 | 0.00 | |||||
prim_buf_tms | 0.00 | 0.00 | |||||
prim_buf_trst_n | 0.00 | 0.00 | |||||
prim_clock_buf_tck | 0.00 | 0.00 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |