Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	16104470	126335	0	0
DepthKnown_A	16104470	16087600	0	0
RvalidKnown_A	16104470	16087600	0	0
WreadyKnown_A	16104470	16087600	0	0
gen_passthru_fifo.paramCheckPass	100	100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16104470	126335	0	0
T1	312808	14703	0	0
T2	317570	14981	0	0
T3	403770	21329	0	0
T4	328152	7735	0	0
T5	235924	6482	0	0
T6	436280	23495	0	0
T7	242518	5639	0	0
T8	342520	9687	0	0
T9	252550	5371	0	0
T10	348802	16913	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16104470	16087600	0	0
T1	1564040	1562330	0	0
T2	1587850	1586250	0	0
T3	2018850	2017250	0	0
T4	1640760	1639050	0	0
T5	1179620	1177940	0	0
T6	2181400	2179580	0	0
T7	1212590	1210840	0	0
T8	1712600	1710960	0	0
T9	1262750	1261140	0	0
T10	1744010	1742260	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16104470	16087600	0	0
T1	1564040	1562330	0	0
T2	1587850	1586250	0	0
T3	2018850	2017250	0	0
T4	1640760	1639050	0	0
T5	1179620	1177940	0	0
T6	2181400	2179580	0	0
T7	1212590	1210840	0	0
T8	1712600	1710960	0	0
T9	1262750	1261140	0	0
T10	1744010	1742260	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16104470	16087600	0	0
T1	1564040	1562330	0	0
T2	1587850	1586250	0	0
T3	2018850	2017250	0	0
T4	1640760	1639050	0	0
T5	1179620	1177940	0	0
T6	2181400	2179580	0	0
T7	1212590	1210840	0	0
T8	1712600	1710960	0	0
T9	1262750	1261140	0	0
T10	1744010	1742260	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	100	100	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T5	10	10	0	0
T6	10	10	0	0
T7	10	10	0	0
T8	10	10	0	0
T9	10	10	0	0
T10	10	10	0	0