Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1610447	0	0	0
DepthKnown_A	1610447	1608760	0	0
RvalidKnown_A	1610447	1608760	0	0
WreadyKnown_A	1610447	1608760	0	0
gen_passthru_fifo.paramCheckPass	10	10	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1610447	0	0	0
DepthKnown_A	1610447	1608760	0	0
RvalidKnown_A	1610447	1608760	0	0
WreadyKnown_A	1610447	1608760	0	0
gen_passthru_fifo.paramCheckPass	10	10	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1610447	40377	0	0
DepthKnown_A	1610447	1608760	0	0
RvalidKnown_A	1610447	1608760	0	0
WreadyKnown_A	1610447	1608760	0	0
gen_passthru_fifo.paramCheckPass	10	10	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	40377	0	0
T1	156404	3237	0	0
T2	158785	3341	0	0
T3	201885	4297	0	0
T4	164076	4219	0	0
T5	117962	4500	0	0
T6	218140	4633	0	0
T7	121259	3617	0	0
T8	171260	5831	0	0
T9	126275	3191	0	0
T10	174401	3511	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1610447	85958	0	0
DepthKnown_A	1610447	1608760	0	0
RvalidKnown_A	1610447	1608760	0	0
WreadyKnown_A	1610447	1608760	0	0
gen_passthru_fifo.paramCheckPass	10	10	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	85958	0	0
T1	156404	11466	0	0
T2	158785	11640	0	0
T3	201885	17032	0	0
T4	164076	3516	0	0
T5	117962	1982	0	0
T6	218140	18862	0	0
T7	121259	2022	0	0
T8	171260	3856	0	0
T9	126275	2180	0	0
T10	174401	13402	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1610447	0	0	0
DepthKnown_A	1610447	1608760	0	0
RvalidKnown_A	1610447	1608760	0	0
WreadyKnown_A	1610447	1608760	0	0
gen_passthru_fifo.paramCheckPass	10	10	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1610447	0	0	0
DepthKnown_A	1610447	1608760	0	0
RvalidKnown_A	1610447	1608760	0	0
WreadyKnown_A	1610447	1608760	0	0
gen_passthru_fifo.paramCheckPass	10	10	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1610447	0	0	0
DepthKnown_A	1610447	1608760	0	0
RvalidKnown_A	1610447	1608760	0	0
WreadyKnown_A	1610447	1608760	0	0
gen_passthru_fifo.paramCheckPass	10	10	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1610447	0	0	0
DepthKnown_A	1610447	1608760	0	0
RvalidKnown_A	1610447	1608760	0	0
WreadyKnown_A	1610447	1608760	0	0
gen_passthru_fifo.paramCheckPass	10	10	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1610447	0	0	0
DepthKnown_A	1610447	1608760	0	0
RvalidKnown_A	1610447	1608760	0	0
WreadyKnown_A	1610447	1608760	0	0
gen_passthru_fifo.paramCheckPass	10	10	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1610447	0	0	0
DepthKnown_A	1610447	1608760	0	0
RvalidKnown_A	1610447	1608760	0	0
WreadyKnown_A	1610447	1608760	0	0
gen_passthru_fifo.paramCheckPass	10	10	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610447	1608760	0	0
T1	156404	156233	0	0
T2	158785	158625	0	0
T3	201885	201725	0	0
T4	164076	163905	0	0
T5	117962	117794	0	0
T6	218140	217958	0	0
T7	121259	121084	0	0
T8	171260	171096	0	0
T9	126275	126114	0	0
T10	174401	174226	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0