Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.52 0.26 0.35 1.47 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 0.52 0.26 0.35 1.47 0.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL152840.26
ALWAYS684375.00
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WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 0 1
MISSING_ELSE
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18699 0 1
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18701 0 1
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18710 0 1
18711 0 1
18712 0 1
18713 0 1
18714 0 1
18715 0 1
18716 0 1
18717 0 1
18718 0 1
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18722 0 1
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18725 0 1
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18727 0 1
18728 0 1
18729 0 1
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18731 0 1
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18780 0 1
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18788 0 1
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18790 0 1
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18799 0 1
18803 0 1
18804 0 1
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18806 0 1
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18810 0 1
18811 0 1
18812 0 1
18813 0 1
18814 0 1
18815 0 1
18816 0 1
18817 0 1
18818 0 1
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18820 0 1
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18822 0 1
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18825 0 1
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18828 0 1
18829 0 1
18830 0 1
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18832 0 1
18833 0 1
18834 0 1
18838 0 1
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18844 0 1
18845 0 1
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18847 0 1
18848 0 1
18849 0 1
18850 0 1
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18852 0 1
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18854 0 1
18855 0 1
18856 0 1
18857 0 1
18858 0 1
18859 0 1
18860 0 1
18861 0 1
18862 0 1
18863 0 1
18864 0 1
18865 0 1
18866 0 1
18867 0 1
18868 0 1
18869 0 1
18873 0 1
18874 0 1
18875 0 1
18876 0 1
18877 0 1
18878 0 1
18879 0 1
18880 0 1
18881 0 1
18882 0 1
18883 0 1
18884 0 1
18885 0 1
18886 0 1
18887 0 1
18888 0 1
18889 0 1
18890 0 1
18891 0 1
18892 0 1
18893 0 1
18894 0 1
18895 0 1
18896 0 1
18897 0 1
18898 0 1
18899 0 1
18900 0 1
18901 0 1
18902 0 1
18903 0 1
18904 0 1
18908 0 1
18909 0 1
18910 0 1
18911 0 1
18912 0 1
18913 0 1
18914 0 1
18915 0 1
18916 0 1
18917 0 1
18918 0 1
18919 0 1
18920 0 1
18921 0 1
18922 0 1
18923 0 1
18924 0 1
18925 0 1
18926 0 1
18927 0 1
18928 0 1
18929 0 1
18930 0 1
18931 0 1
18932 0 1
18933 0 1
18934 0 1
18935 0 1
18936 0 1
18937 0 1
18938 0 1
18939 0 1
18943 0 1
18944 0 1
18945 0 1
18946 0 1
18947 0 1
18948 0 1
18949 0 1
18950 0 1
18951 0 1
18952 0 1
18953 0 1
18954 0 1
18955 0 1
18956 0 1
18957 0 1
18958 0 1
18959 0 1
18960 0 1
18961 0 1
18962 0 1
18963 0 1
18964 0 1
18968 0 1
18972 0 1
18976 0 1
18980 0 1
18994 unreachable
19002 0 1
19003 0 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions198370.35
Logical198370.35
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-165000.73
16500-171820.10
17185-176280.00

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 204 3 1.47
TERNARY 16496 2 1 50.00
IF 68 3 2 66.67
CASE 17838 199 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16496 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 17838 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Not Covered
addr_hit[1] Not Covered
addr_hit[2] Not Covered
addr_hit[3] Not Covered
addr_hit[4] Not Covered
addr_hit[5] Not Covered
addr_hit[6] Not Covered
addr_hit[7] Not Covered
addr_hit[8] Not Covered
addr_hit[9] Not Covered
addr_hit[10] Not Covered
addr_hit[11] Not Covered
addr_hit[12] Not Covered
addr_hit[13] Not Covered
addr_hit[14] Not Covered
addr_hit[15] Not Covered
addr_hit[16] Not Covered
addr_hit[17] Not Covered
addr_hit[18] Not Covered
addr_hit[19] Not Covered
addr_hit[20] Not Covered
addr_hit[21] Not Covered
addr_hit[22] Not Covered
addr_hit[23] Not Covered
addr_hit[24] Not Covered
addr_hit[25] Not Covered
addr_hit[26] Not Covered
addr_hit[27] Not Covered
addr_hit[28] Not Covered
addr_hit[29] Not Covered
addr_hit[30] Not Covered
addr_hit[31] Not Covered
addr_hit[32] Not Covered
addr_hit[33] Not Covered
addr_hit[34] Not Covered
addr_hit[35] Not Covered
addr_hit[36] Not Covered
addr_hit[37] Not Covered
addr_hit[38] Not Covered
addr_hit[39] Not Covered
addr_hit[40] Not Covered
addr_hit[41] Not Covered
addr_hit[42] Not Covered
addr_hit[43] Not Covered
addr_hit[44] Not Covered
addr_hit[45] Not Covered
addr_hit[46] Not Covered
addr_hit[47] Not Covered
addr_hit[48] Not Covered
addr_hit[49] Not Covered
addr_hit[50] Not Covered
addr_hit[51] Not Covered
addr_hit[52] Not Covered
addr_hit[53] Not Covered
addr_hit[54] Not Covered
addr_hit[55] Not Covered
addr_hit[56] Not Covered
addr_hit[57] Not Covered
addr_hit[58] Not Covered
addr_hit[59] Not Covered
addr_hit[60] Not Covered
addr_hit[61] Not Covered
addr_hit[62] Not Covered
addr_hit[63] Not Covered
addr_hit[64] Not Covered
addr_hit[65] Not Covered
addr_hit[66] Not Covered
addr_hit[67] Not Covered
addr_hit[68] Not Covered
addr_hit[69] Not Covered
addr_hit[70] Not Covered
addr_hit[71] Not Covered
addr_hit[72] Not Covered
addr_hit[73] Not Covered
addr_hit[74] Not Covered
addr_hit[75] Not Covered
addr_hit[76] Not Covered
addr_hit[77] Not Covered
addr_hit[78] Not Covered
addr_hit[79] Not Covered
addr_hit[80] Not Covered
addr_hit[81] Not Covered
addr_hit[82] Not Covered
addr_hit[83] Not Covered
addr_hit[84] Not Covered
addr_hit[85] Not Covered
addr_hit[86] Not Covered
addr_hit[87] Not Covered
addr_hit[88] Not Covered
addr_hit[89] Not Covered
addr_hit[90] Not Covered
addr_hit[91] Not Covered
addr_hit[92] Not Covered
addr_hit[93] Not Covered
addr_hit[94] Not Covered
addr_hit[95] Not Covered
addr_hit[96] Not Covered
addr_hit[97] Not Covered
addr_hit[98] Not Covered
addr_hit[99] Not Covered
addr_hit[100] Not Covered
addr_hit[101] Not Covered
addr_hit[102] Not Covered
addr_hit[103] Not Covered
addr_hit[104] Not Covered
addr_hit[105] Not Covered
addr_hit[106] Not Covered
addr_hit[107] Not Covered
addr_hit[108] Not Covered
addr_hit[109] Not Covered
addr_hit[110] Not Covered
addr_hit[111] Not Covered
addr_hit[112] Not Covered
addr_hit[113] Not Covered
addr_hit[114] Not Covered
addr_hit[115] Not Covered
addr_hit[116] Not Covered
addr_hit[117] Not Covered
addr_hit[118] Not Covered
addr_hit[119] Not Covered
addr_hit[120] Not Covered
addr_hit[121] Not Covered
addr_hit[122] Not Covered
addr_hit[123] Not Covered
addr_hit[124] Not Covered
addr_hit[125] Not Covered
addr_hit[126] Not Covered
addr_hit[127] Not Covered
addr_hit[128] Not Covered
addr_hit[129] Not Covered
addr_hit[130] Not Covered
addr_hit[131] Not Covered
addr_hit[132] Not Covered
addr_hit[133] Not Covered
addr_hit[134] Not Covered
addr_hit[135] Not Covered
addr_hit[136] Not Covered
addr_hit[137] Not Covered
addr_hit[138] Not Covered
addr_hit[139] Not Covered
addr_hit[140] Not Covered
addr_hit[141] Not Covered
addr_hit[142] Not Covered
addr_hit[143] Not Covered
addr_hit[144] Not Covered
addr_hit[145] Not Covered
addr_hit[146] Not Covered
addr_hit[147] Not Covered
addr_hit[148] Not Covered
addr_hit[149] Not Covered
addr_hit[150] Not Covered
addr_hit[151] Not Covered
addr_hit[152] Not Covered
addr_hit[153] Not Covered
addr_hit[154] Not Covered
addr_hit[155] Not Covered
addr_hit[156] Not Covered
addr_hit[157] Not Covered
addr_hit[158] Not Covered
addr_hit[159] Not Covered
addr_hit[160] Not Covered
addr_hit[161] Not Covered
addr_hit[162] Not Covered
addr_hit[163] Not Covered
addr_hit[164] Not Covered
addr_hit[165] Not Covered
addr_hit[166] Not Covered
addr_hit[167] Not Covered
addr_hit[168] Not Covered
addr_hit[169] Not Covered
addr_hit[170] Not Covered
addr_hit[171] Not Covered
addr_hit[172] Not Covered
addr_hit[173] Not Covered
addr_hit[174] Not Covered
addr_hit[175] Not Covered
addr_hit[176] Not Covered
addr_hit[177] Not Covered
addr_hit[178] Not Covered
addr_hit[179] Not Covered
addr_hit[180] Not Covered
addr_hit[181] Not Covered
addr_hit[182] Not Covered
addr_hit[183] Not Covered
addr_hit[184] Not Covered
addr_hit[185] Not Covered
addr_hit[186] Not Covered
addr_hit[187] Not Covered
addr_hit[188] Not Covered
addr_hit[189] Not Covered
addr_hit[190] Not Covered
addr_hit[191] Not Covered
addr_hit[192] Not Covered
addr_hit[193] Not Covered
addr_hit[194] Not Covered
addr_hit[195] Not Covered
addr_hit[196] Not Covered
addr_hit[197] Not Covered
default Not Covered


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 1610447 0 0 0
reAfterRv 1610447 0 0 0
rePulse 1610447 0 0 0
wePulse 1610447 0 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 1610447 0 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 1610447 0 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 1610447 0 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 1610447 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%