Unified Coverage Report :: Module :: tlul_rsp_intg_chk

Module : tlul_rsp_intg_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	80.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk	46.67	0.00	40.00				100.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk	93.33	100.00	80.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.67	0.00	40.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.67	0.00	40.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
28.40	27.27	30.77			55.56	0.00	tl_adapter_host_i_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	80.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	80.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
37.57	60.87	29.41			60.00	0.00	tl_adapter_host_d_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_rsp_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	23	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	50	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1
47	1	1
50	1	1

---

Cond Coverage for Module : tlul_rsp_intg_chk

	Total	Covered	Percent
Conditions	5	4	80.00
Logical	5	4	80.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_rsp_intg_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	20	20	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	20	20	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
CONT_ASSIGN	23	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	50	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	0	1
47	0	1
50	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk

	Total	Covered	Percent
Conditions	5	2	40.00
Logical	5	2	40.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	10	10	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	23	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	50	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1
47	1	1
50	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk

	Total	Covered	Percent
Conditions	5	4	80.00
Logical	5	4	80.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	10	10	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	10	10	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0