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NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
fifo_d 75.00 100.00 50.00 50.00 100.00
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00
fifo_i 45.00 0.00 50.00 50.00 80.00
reqfifo 40.00 0.00 80.00
rspfifo 40.00 0.00 80.00
gen_alert_senders[0].u_alert_sender 33.33 33.33
gen_alert_senders[1].u_alert_sender 33.33 33.33
gen_alert_senders[2].u_alert_sender 33.33 33.33
gen_alert_senders[3].u_alert_sender 33.33 33.33
tl_adapter_host_d_ibex 61.66 79.07 40.91 60.00 66.67
u_cmd_intg_gen 100.00 100.00 100.00
u_cmd_gen 100.00 100.00
u_rsp_chk 93.33 100.00 80.00 100.00
tl_adapter_host_i_ibex 42.46 14.29 33.33 55.56 66.67
u_cmd_intg_gen 50.00 0.00 100.00
u_cmd_gen 0.00 0.00
u_rsp_chk 46.67 0.00 40.00 100.00
u_alert_nmi_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_core 2.49 2.49
u_core_sleeping_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_dbus_trans 11.80 1.15 22.22 16.67 7.14
u_sel_region 3.45 0.00 6.67 0.00 7.14
u_edn_if 48.85 75.32 50.85 69.23 0.00
u_prim_packer_fifo 53.31 81.82 60.00 71.43 0.00
u_prim_sync_reqack_data 44.71 75.51 33.33 70.00 0.00
u_prim_sync_reqack 45.10 77.08 33.33 70.00 0.00
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_ibus_trans 9.94 1.15 14.81 16.67 7.14
u_sel_region 3.45 0.00 6.67 0.00 7.14
u_intr_timer_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_lc_sync 100.00 100.00 100.00 100.00
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_buf_irq 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_esc_receiver 28.57 28.57
u_prim_lc_sender 80.00 60.00 100.00
gen_flops.u_prim_flop 100.00 100.00 100.00
u_secure_anchor_flop 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_prim_sync_reqack_data 26.22 44.90 0.00 60.00 0.00
u_prim_sync_reqack 26.46 45.83 0.00 60.00 0.00
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_pwrmgr_sync 100.00 100.00 100.00 100.00
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_reg_cfg 41.77 19.34 24.67 45.80 77.27
u_alert_test_fatal_hw_err 0.00 0.00
u_alert_test_fatal_sw_err 0.00 0.00
u_alert_test_recov_hw_err 0.00 0.00
u_alert_test_recov_sw_err 0.00 0.00
u_chk 83.33 66.67 100.00
u_tlul_data_integ_dec 0.00 0.00
u_dbus_addr_en_0 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_dbus_addr_en_1 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_dbus_addr_matching_0 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_dbus_addr_matching_1 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_dbus_regwen_0 47.78 33.33 50.00 60.00
wr_en_data_arb 25.00 0.00 50.00
u_dbus_regwen_1 47.78 33.33 50.00 60.00
wr_en_data_arb 25.00 0.00 50.00
u_dbus_remap_addr_0 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_dbus_remap_addr_1 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_err_status_fatal_core_err 45.00 33.33 41.67 60.00
wr_en_data_arb 20.00 0.00 40.00
u_err_status_fatal_intg_err 59.81 77.78 41.67 60.00
wr_en_data_arb 70.00 100.00 40.00
u_err_status_recov_core_err 45.00 33.33 41.67 60.00
wr_en_data_arb 20.00 0.00 40.00
u_err_status_reg_intg_err 45.00 33.33 41.67 60.00
wr_en_data_arb 20.00 0.00 40.00
u_fpga_info 0.00 0.00
u_ibus_addr_en_0 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_ibus_addr_en_1 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_ibus_addr_matching_0 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_ibus_addr_matching_1 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_ibus_regwen_0 47.78 33.33 50.00 60.00
wr_en_data_arb 25.00 0.00 50.00
u_ibus_regwen_1 47.78 33.33 50.00 60.00
wr_en_data_arb 25.00 0.00 50.00
u_ibus_remap_addr_0 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_ibus_remap_addr_1 46.83 33.33 50.00 57.14
wr_en_data_arb 33.33 0.00 50.00 50.00
u_nmi_enable_alert_en 47.78 33.33 50.00 60.00
wr_en_data_arb 25.00 0.00 50.00
u_nmi_enable_wdog_en 47.78 33.33 50.00 60.00
wr_en_data_arb 25.00 0.00 50.00
u_nmi_state_alert 45.00 33.33 41.67 60.00
wr_en_data_arb 20.00 0.00 40.00
u_nmi_state_wdog 45.00 33.33 41.67 60.00
wr_en_data_arb 20.00 0.00 40.00
u_prim_reg_we_check 0.00 0.00
u_prim_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_reg_if 42.07 20.00 20.99 27.27 100.00
u_err 31.43 0.00 25.71 0.00 100.00
u_rsp_intg_gen 50.00 0.00 100.00
u_rnd_data 0.00 0.00
u_rnd_status_rnd_data_fips 0.00 0.00
u_rnd_status_rnd_data_valid 0.00 0.00
u_rsp_intg_gen 50.00 0.00 100.00
gen_data_intg.u_tlul_data_integ_enc 0.00 0.00
u_data_gen 0.00 0.00
gen_rsp_intg.u_rsp_gen 0.00 0.00
u_socket 42.93 18.75 35.71 36.00 81.25
fifo_h 51.25 25.00 50.00 50.00 80.00
reqfifo 40.00 0.00 80.00
rspfifo 65.00 50.00 80.00
gen_dfifo[0].fifo_d 51.25 25.00 50.00 50.00 80.00
reqfifo 40.00 0.00 80.00
rspfifo 65.00 50.00 80.00
gen_dfifo[1].fifo_d 51.25 25.00 50.00 50.00 80.00
reqfifo 40.00 0.00 80.00
rspfifo 65.00 50.00 80.00
u_sw_fatal_err 47.78 33.33 50.00 60.00
wr_en_data_arb 25.00 0.00 50.00
u_sw_recov_err 44.97 33.33 44.44 57.14
wr_en_data_arb 30.95 0.00 42.86 50.00
u_sim_win_rsp 55.63 30.61 36.36 55.56 100.00
u_intg_gen 50.00 0.00 100.00
gen_data_intg.u_tlul_data_integ_enc 0.00 0.00
u_data_gen 0.00 0.00
gen_rsp_intg.u_rsp_gen 0.00 0.00
u_tlul_req_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_tlul_rsp_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_wdog_nmi_sync 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
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