Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1037019	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23174339

1

T1

18976

T2

26909

T3

5593

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15532139	1			T1	11859		T2	10454		T3	2361
values[0x0]	7641212	1			T1	7117		T2	16455		T3	3232
values[0x1]	1038007	1			T1	2344		T2	1464		T3	419

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7776	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24203582

1

T1

21320

T2

28373

T3

6012

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12093264	1			T1	10660		T2	14188		T3	3006
valid_sources[0x01]	12092306	1			T1	10660		T2	14185		T3	3006
valid_sources[0x02]	311	1			T57	1		T79	2		T28	47
valid_sources[0x03]	245	1			T56	1		T79	1		T28	40
valid_sources[0x04]	349	1			T79	1		T28	51		T29	49
valid_sources[0x05]	2128	1			T56	2		T28	50		T29	41
valid_sources[0x06]	305	1			T28	43		T29	51		T444	47
valid_sources[0x07]	320	1			T56	1		T79	3		T28	36
valid_sources[0x08]	2864	1			T27	2555		T28	33		T29	53
valid_sources[0x09]	418	1			T56	1		T65	39		T66	21
valid_sources[0x0a]	353	1			T56	2		T28	40		T29	42
valid_sources[0x0b]	327	1			T56	4		T28	49		T29	50
valid_sources[0x0c]	323	1			T56	1		T28	51		T29	55
valid_sources[0x0d]	431	1			T79	1		T28	43		T29	44
valid_sources[0x0e]	323	1			T56	1		T79	1		T28	38
valid_sources[0x0f]	356	1			T57	2		T28	21		T29	44
valid_sources[0x10]	333	1			T28	46		T29	47		T444	53
valid_sources[0x11]	397	1			T56	1		T79	1		T66	3
valid_sources[0x12]	345	1			T56	1		T28	46		T29	52
valid_sources[0x13]	341	1			T56	1		T79	1		T28	33
valid_sources[0x14]	352	1			T79	1		T28	47		T29	46
valid_sources[0x15]	304	1			T56	2		T27	16		T28	44
valid_sources[0x16]	307	1			T79	3		T28	25		T29	64
valid_sources[0x17]	385	1			T79	1		T28	58		T29	54
valid_sources[0x18]	465	1			T56	1		T79	1		T27	16
valid_sources[0x19]	282	1			T57	3		T28	43		T29	42
valid_sources[0x1a]	265	1			T79	1		T28	43		T29	55
valid_sources[0x1b]	290	1			T56	1		T79	1		T28	48
valid_sources[0x1c]	364	1			T56	1		T59	39		T28	39
valid_sources[0x1d]	438	1			T27	16		T28	39		T29	59
valid_sources[0x1e]	472	1			T79	2		T28	46		T29	49
valid_sources[0x1f]	286	1			T79	1		T28	35		T29	43
valid_sources[0x20]	267	1			T79	1		T28	45		T29	55

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15532139

1

T1

11859

T2

10454

T3

2361

values[0x0]

all_enables

biggest_size

7637236

1

T1

7117

T2

16455

T3

3232

values[0x1]

all_enables

biggest_size

4964

1

T56

22

T57

17

T79

18