| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 41.70 |
41.70 |
45.67 |
45.67 |
43.08 |
43.08 |
33.03 |
33.03 |
|
|
58.32 |
58.32 |
62.85 |
62.85 |
7.24 |
7.24 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.345051639 |
| 49.24 |
7.55 |
45.75 |
0.08 |
43.16 |
0.08 |
35.60 |
2.57 |
|
|
58.33 |
0.01 |
62.85 |
0.00 |
49.78 |
42.54 |
/workspace/coverage/default/0.chip_sw_alert_test.916912125 |
| 54.31 |
5.07 |
57.13 |
11.38 |
50.38 |
7.22 |
37.48 |
1.88 |
|
|
68.25 |
9.92 |
62.85 |
0.00 |
49.78 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2451063019 |
| 59.15 |
4.84 |
66.67 |
9.54 |
55.68 |
5.30 |
41.87 |
4.39 |
|
|
70.81 |
2.56 |
62.85 |
0.00 |
57.02 |
7.24 |
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3362505506 |
| 62.84 |
3.69 |
73.11 |
6.43 |
63.09 |
7.41 |
42.37 |
0.50 |
|
|
78.45 |
7.64 |
63.03 |
0.18 |
57.02 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.970484483 |
| 65.99 |
3.15 |
76.89 |
3.79 |
67.26 |
4.17 |
48.54 |
6.17 |
|
|
81.91 |
3.47 |
63.03 |
0.00 |
58.33 |
1.32 |
/workspace/coverage/default/2.chip_jtag_csr_rw.375627572 |
| 68.16 |
2.16 |
78.82 |
1.93 |
69.57 |
2.32 |
55.34 |
6.80 |
|
|
83.47 |
1.56 |
63.40 |
0.37 |
58.33 |
0.00 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.945188533 |
| 69.84 |
1.69 |
78.82 |
0.00 |
69.57 |
0.00 |
65.45 |
10.11 |
|
|
83.47 |
0.00 |
63.40 |
0.00 |
58.33 |
0.00 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3368030077 |
| 71.46 |
1.62 |
78.83 |
0.01 |
69.58 |
0.01 |
66.36 |
0.91 |
|
|
83.47 |
0.00 |
63.40 |
0.00 |
67.11 |
8.77 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2192013517 |
| 73.03 |
1.57 |
78.96 |
0.13 |
69.66 |
0.08 |
75.21 |
8.85 |
|
|
83.65 |
0.17 |
63.59 |
0.18 |
67.11 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.177433503 |
| 74.56 |
1.53 |
80.61 |
1.64 |
70.97 |
1.31 |
76.02 |
0.80 |
|
|
85.01 |
1.37 |
67.65 |
4.07 |
67.11 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1504101008 |
| 75.80 |
1.23 |
82.94 |
2.34 |
73.01 |
2.04 |
76.60 |
0.58 |
|
|
87.46 |
2.45 |
67.65 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.3532356974 |
| 76.84 |
1.04 |
83.98 |
1.04 |
73.55 |
0.54 |
76.62 |
0.02 |
|
|
88.04 |
0.58 |
71.72 |
4.07 |
67.11 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3135236265 |
| 77.53 |
0.70 |
84.54 |
0.55 |
74.19 |
0.64 |
76.80 |
0.18 |
|
|
88.61 |
0.58 |
73.94 |
2.22 |
67.11 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3163607383 |
| 78.20 |
0.67 |
84.55 |
0.01 |
74.19 |
0.01 |
80.79 |
3.98 |
|
|
88.61 |
0.00 |
73.94 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.3943052676 |
| 78.85 |
0.66 |
85.62 |
1.07 |
75.27 |
1.07 |
82.08 |
1.30 |
|
|
89.12 |
0.50 |
73.94 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2593503511 |
| 79.36 |
0.50 |
85.92 |
0.30 |
75.54 |
0.27 |
82.08 |
0.00 |
|
|
89.34 |
0.22 |
76.16 |
2.22 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1211061246 |
| 79.86 |
0.50 |
86.88 |
0.96 |
76.45 |
0.92 |
82.12 |
0.03 |
|
|
90.02 |
0.68 |
76.34 |
0.18 |
67.32 |
0.22 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3688560300 |
| 80.25 |
0.39 |
87.93 |
1.04 |
76.68 |
0.23 |
83.01 |
0.90 |
|
|
90.20 |
0.18 |
76.34 |
0.00 |
67.32 |
0.00 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.423275451 |
| 80.60 |
0.35 |
87.96 |
0.04 |
76.71 |
0.03 |
83.29 |
0.27 |
|
|
90.24 |
0.03 |
76.52 |
0.18 |
68.86 |
1.54 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.414936029 |
| 80.88 |
0.29 |
88.13 |
0.17 |
76.79 |
0.09 |
83.74 |
0.46 |
|
|
90.32 |
0.08 |
77.45 |
0.92 |
68.86 |
0.00 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3253499543 |
| 81.16 |
0.27 |
88.59 |
0.46 |
77.30 |
0.50 |
84.05 |
0.31 |
|
|
90.69 |
0.37 |
77.45 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.3891286190 |
| 81.42 |
0.26 |
89.06 |
0.47 |
77.72 |
0.43 |
84.34 |
0.29 |
|
|
91.09 |
0.40 |
77.45 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.423137928 |
| 81.65 |
0.23 |
89.06 |
0.00 |
77.72 |
0.00 |
85.72 |
1.38 |
|
|
91.09 |
0.00 |
77.45 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.968510189 |
| 81.81 |
0.16 |
89.12 |
0.06 |
78.12 |
0.40 |
85.76 |
0.04 |
|
|
91.52 |
0.44 |
77.45 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3439761757 |
| 81.96 |
0.15 |
89.33 |
0.22 |
78.45 |
0.33 |
86.12 |
0.36 |
|
|
91.52 |
0.00 |
77.45 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2958361448 |
| 82.10 |
0.14 |
89.35 |
0.01 |
78.50 |
0.05 |
86.88 |
0.76 |
|
|
91.55 |
0.02 |
77.45 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3171073558 |
| 82.23 |
0.13 |
89.59 |
0.25 |
78.98 |
0.49 |
86.89 |
0.01 |
|
|
91.60 |
0.05 |
77.45 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/1.chip_jtag_csr_rw.3956344616 |
| 82.32 |
0.09 |
89.65 |
0.06 |
79.04 |
0.05 |
86.89 |
0.00 |
|
|
91.64 |
0.04 |
77.63 |
0.18 |
69.08 |
0.22 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3500449383 |
| 82.41 |
0.09 |
89.66 |
0.01 |
79.09 |
0.05 |
87.16 |
0.27 |
|
|
91.65 |
0.02 |
77.82 |
0.18 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.883327394 |
| 82.49 |
0.08 |
89.66 |
0.00 |
79.09 |
0.00 |
87.63 |
0.47 |
|
|
91.65 |
0.00 |
77.82 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2986547672 |
| 82.57 |
0.08 |
89.81 |
0.15 |
79.13 |
0.04 |
87.65 |
0.02 |
|
|
91.68 |
0.02 |
77.82 |
0.00 |
69.30 |
0.22 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2592072060 |
| 82.64 |
0.08 |
89.82 |
0.01 |
79.15 |
0.02 |
87.65 |
0.00 |
|
|
91.70 |
0.02 |
78.00 |
0.18 |
69.52 |
0.22 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.230716736 |
| 82.71 |
0.07 |
89.83 |
0.01 |
79.16 |
0.01 |
87.66 |
0.01 |
|
|
91.71 |
0.01 |
78.19 |
0.18 |
69.74 |
0.22 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.860788750 |
| 82.78 |
0.07 |
89.83 |
0.00 |
79.16 |
0.00 |
88.07 |
0.41 |
|
|
91.71 |
0.00 |
78.19 |
0.00 |
69.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.508757314 |
| 82.85 |
0.06 |
89.85 |
0.02 |
79.34 |
0.17 |
88.07 |
0.00 |
|
|
91.91 |
0.20 |
78.19 |
0.00 |
69.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3754485911 |
| 82.91 |
0.06 |
89.85 |
0.00 |
79.34 |
0.00 |
88.43 |
0.36 |
|
|
91.91 |
0.00 |
78.19 |
0.00 |
69.74 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3134232908 |
| 82.95 |
0.05 |
89.85 |
0.00 |
79.34 |
0.00 |
88.49 |
0.05 |
|
|
91.91 |
0.00 |
78.19 |
0.00 |
69.96 |
0.22 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.4037880747 |
| 83.00 |
0.04 |
89.85 |
0.00 |
79.34 |
0.00 |
88.52 |
0.04 |
|
|
91.91 |
0.00 |
78.19 |
0.00 |
70.18 |
0.22 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3152801838 |
| 83.04 |
0.04 |
90.07 |
0.23 |
79.36 |
0.03 |
88.52 |
0.00 |
|
|
91.91 |
0.00 |
78.19 |
0.00 |
70.18 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3744588450 |
| 83.08 |
0.04 |
90.07 |
0.00 |
79.36 |
0.00 |
88.76 |
0.24 |
|
|
91.91 |
0.00 |
78.19 |
0.00 |
70.18 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3007525751 |
| 83.12 |
0.04 |
90.08 |
0.01 |
79.36 |
0.00 |
88.76 |
0.01 |
|
|
91.91 |
0.00 |
78.19 |
0.00 |
70.39 |
0.22 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4137575530 |
| 83.15 |
0.04 |
90.08 |
0.00 |
79.37 |
0.01 |
88.76 |
0.01 |
|
|
91.91 |
0.00 |
78.19 |
0.00 |
70.61 |
0.22 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2107241777 |
| 83.19 |
0.04 |
90.08 |
0.00 |
79.37 |
0.00 |
88.77 |
0.01 |
|
|
91.91 |
0.00 |
78.19 |
0.00 |
70.83 |
0.22 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.64951345 |
| 83.23 |
0.04 |
90.08 |
0.00 |
79.37 |
0.00 |
88.77 |
0.01 |
|
|
91.91 |
0.00 |
78.19 |
0.00 |
71.05 |
0.22 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1199495187 |
| 83.26 |
0.04 |
90.08 |
0.00 |
79.37 |
0.01 |
88.77 |
0.00 |
|
|
91.91 |
0.00 |
78.19 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.1057894926 |
| 83.30 |
0.04 |
90.15 |
0.08 |
79.37 |
0.00 |
88.91 |
0.14 |
|
|
91.92 |
0.01 |
78.19 |
0.00 |
71.27 |
0.00 |
/workspace/coverage/default/2.chip_tap_straps_rma.2342330413 |
| 83.34 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.01 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3386767850 |
| 83.38 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.847720577 |
| 83.41 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
71.93 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4039449596 |
| 83.45 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
72.15 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.4241041132 |
| 83.49 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
72.37 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.48157369 |
| 83.52 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
72.59 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.3477644248 |
| 83.56 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
72.81 |
0.22 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1227900412 |
| 83.59 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
73.03 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.2233117767 |
| 83.63 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
73.25 |
0.22 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.878086706 |
| 83.67 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
73.46 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.4001731433 |
| 83.70 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
73.68 |
0.22 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1602987015 |
| 83.74 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
73.90 |
0.22 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.321962714 |
| 83.78 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
74.12 |
0.22 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3643646643 |
| 83.81 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
74.34 |
0.22 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.3089115253 |
| 83.85 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
74.56 |
0.22 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771787768 |
| 83.89 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
74.78 |
0.22 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4223691653 |
| 83.92 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
75.00 |
0.22 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.606394229 |
| 83.96 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
75.22 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.778336264 |
| 84.00 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
75.44 |
0.22 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.751955505 |
| 84.03 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
75.66 |
0.22 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.2226962556 |
| 84.07 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
75.88 |
0.22 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2013326551 |
| 84.11 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
76.10 |
0.22 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1661005306 |
| 84.14 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
76.32 |
0.22 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3061312445 |
| 84.18 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
76.54 |
0.22 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.828317116 |
| 84.22 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
76.75 |
0.22 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3811703323 |
| 84.25 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
76.97 |
0.22 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.3771455526 |
| 84.29 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
77.19 |
0.22 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3783611232 |
| 84.33 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
77.41 |
0.22 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.887112992 |
| 84.36 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
77.63 |
0.22 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3810909497 |
| 84.40 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
77.85 |
0.22 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2024316232 |
| 84.44 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
78.07 |
0.22 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1119234249 |
| 84.47 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
78.29 |
0.22 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2765284791 |
| 84.51 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
78.51 |
0.22 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1820718331 |
| 84.54 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
78.73 |
0.22 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.15415145 |
| 84.58 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
78.95 |
0.22 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1875677962 |
| 84.62 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
79.17 |
0.22 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335294066 |
| 84.65 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
79.39 |
0.22 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2011184028 |
| 84.69 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
79.61 |
0.22 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1823135910 |
| 84.73 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
79.82 |
0.22 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2916915865 |
| 84.76 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
80.04 |
0.22 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3310536545 |
| 84.80 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
80.26 |
0.22 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2779165125 |
| 84.84 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
80.48 |
0.22 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3350300530 |
| 84.87 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
80.70 |
0.22 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.578280257 |
| 84.91 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
80.92 |
0.22 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1970959985 |
| 84.95 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
81.14 |
0.22 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4187037840 |
| 84.98 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
81.36 |
0.22 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3870289929 |
| 85.02 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
81.58 |
0.22 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031582160 |
| 85.06 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
81.80 |
0.22 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2336644580 |
| 85.09 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
82.02 |
0.22 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2725995941 |
| 85.13 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
82.24 |
0.22 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1800857155 |
| 85.17 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
82.46 |
0.22 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040002287 |
| 85.20 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
82.68 |
0.22 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3256001930 |
| 85.24 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
82.89 |
0.22 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.654562808 |
| 85.28 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
83.11 |
0.22 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.800316007 |
| 85.31 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
83.33 |
0.22 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2939833412 |
| 85.35 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
83.55 |
0.22 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3342823729 |
| 85.39 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
83.77 |
0.22 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538357824 |
| 85.42 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
83.99 |
0.22 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1916957733 |
| 85.46 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
84.21 |
0.22 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1262530746 |
| 85.50 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.91 |
0.00 |
|
|
91.92 |
0.00 |
78.19 |
0.00 |
84.43 |
0.22 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1419930959 |
| 85.53 |
0.04 |
90.15 |
0.00 |
79.37 |
0.00 |
88.94 |
0.03 |
|
|
91.92 |
0.00 |
78.37 |
0.18 |
84.43 |
0.00 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3195613718 |
| 85.57 |
0.04 |
90.18 |
0.02 |
79.39 |
0.02 |
89.12 |
0.17 |
|
|
91.92 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_power_idle_load.1657929962 |
| 85.60 |
0.03 |
90.18 |
0.00 |
79.57 |
0.18 |
89.12 |
0.00 |
|
|
91.92 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3303735090 |
| 85.62 |
0.03 |
90.18 |
0.00 |
79.57 |
0.00 |
89.28 |
0.16 |
|
|
91.92 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2574180500 |
| 85.65 |
0.03 |
90.21 |
0.03 |
79.63 |
0.06 |
89.33 |
0.05 |
|
|
91.94 |
0.02 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2661701837 |
| 85.68 |
0.03 |
90.27 |
0.06 |
79.66 |
0.03 |
89.34 |
0.02 |
|
|
91.99 |
0.05 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.967550285 |
| 85.70 |
0.02 |
90.28 |
0.01 |
79.68 |
0.02 |
89.46 |
0.11 |
|
|
91.99 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2628172412 |
| 85.72 |
0.02 |
90.30 |
0.02 |
79.70 |
0.02 |
89.53 |
0.07 |
|
|
92.01 |
0.02 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2215800893 |
| 85.74 |
0.02 |
90.30 |
0.00 |
79.70 |
0.00 |
89.64 |
0.11 |
|
|
92.01 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_init.3666030636 |
| 85.76 |
0.02 |
90.30 |
0.00 |
79.70 |
0.00 |
89.74 |
0.10 |
|
|
92.01 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.1943045118 |
| 85.78 |
0.02 |
90.30 |
0.00 |
79.70 |
0.00 |
89.84 |
0.10 |
|
|
92.01 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1468042768 |
| 85.79 |
0.02 |
90.30 |
0.00 |
79.79 |
0.09 |
89.84 |
0.00 |
|
|
92.01 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.4201777049 |
| 85.81 |
0.01 |
90.32 |
0.01 |
79.82 |
0.03 |
89.89 |
0.05 |
|
|
92.01 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1506033150 |
| 85.82 |
0.01 |
90.32 |
0.00 |
79.82 |
0.00 |
89.97 |
0.08 |
|
|
92.01 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3426532870 |
| 85.83 |
0.01 |
90.34 |
0.03 |
79.83 |
0.02 |
89.97 |
0.01 |
|
|
92.03 |
0.02 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.86195947 |
| 85.84 |
0.01 |
90.34 |
0.01 |
79.85 |
0.02 |
90.02 |
0.04 |
|
|
92.04 |
0.01 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1018465493 |
| 85.86 |
0.01 |
90.34 |
0.00 |
79.93 |
0.07 |
90.02 |
0.00 |
|
|
92.04 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.622800373 |
| 85.87 |
0.01 |
90.35 |
0.01 |
79.96 |
0.04 |
90.05 |
0.03 |
|
|
92.04 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.192877527 |
| 85.88 |
0.01 |
90.35 |
0.00 |
79.96 |
0.00 |
90.12 |
0.07 |
|
|
92.04 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3709709607 |
| 85.89 |
0.01 |
90.38 |
0.03 |
79.98 |
0.01 |
90.12 |
0.00 |
|
|
92.06 |
0.02 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2033063375 |
| 85.90 |
0.01 |
90.41 |
0.03 |
79.98 |
0.01 |
90.12 |
0.01 |
|
|
92.07 |
0.02 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1941136968 |
| 85.91 |
0.01 |
90.41 |
0.00 |
79.99 |
0.01 |
90.17 |
0.04 |
|
|
92.08 |
0.01 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3328620704 |
| 85.92 |
0.01 |
90.43 |
0.02 |
79.99 |
0.01 |
90.17 |
0.01 |
|
|
92.10 |
0.02 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2343497404 |
| 85.92 |
0.01 |
90.43 |
0.00 |
80.00 |
0.01 |
90.22 |
0.05 |
|
|
92.10 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.4149624955 |
| 85.93 |
0.01 |
90.44 |
0.02 |
80.00 |
0.00 |
90.25 |
0.03 |
|
|
92.10 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2920626356 |
| 85.94 |
0.01 |
90.44 |
0.00 |
80.00 |
0.00 |
90.30 |
0.05 |
|
|
92.10 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.293621450 |
| 85.95 |
0.01 |
90.48 |
0.03 |
80.00 |
0.01 |
90.30 |
0.00 |
|
|
92.10 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.1021056690 |
| 85.95 |
0.01 |
90.48 |
0.00 |
80.00 |
0.00 |
90.33 |
0.04 |
|
|
92.10 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4099273706 |
| 85.96 |
0.01 |
90.48 |
0.00 |
80.00 |
0.00 |
90.37 |
0.03 |
|
|
92.10 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.1247107192 |
| 85.96 |
0.01 |
90.48 |
0.00 |
80.00 |
0.00 |
90.40 |
0.03 |
|
|
92.10 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3666837687 |
| 85.97 |
0.01 |
90.48 |
0.00 |
80.03 |
0.03 |
90.40 |
0.00 |
|
|
92.10 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1869100585 |
| 85.97 |
0.01 |
90.48 |
0.00 |
80.05 |
0.01 |
90.40 |
0.00 |
|
|
92.12 |
0.02 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3283415324 |
| 85.98 |
0.01 |
90.48 |
0.01 |
80.06 |
0.01 |
90.40 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2557448387 |
| 85.98 |
0.01 |
90.48 |
0.01 |
80.08 |
0.01 |
90.41 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.905634893 |
| 85.98 |
0.01 |
90.48 |
0.00 |
80.09 |
0.01 |
90.41 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.3134693219 |
| 85.99 |
0.01 |
90.48 |
0.00 |
80.09 |
0.00 |
90.43 |
0.02 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.496644275 |
| 85.99 |
0.01 |
90.48 |
0.00 |
80.11 |
0.02 |
90.43 |
0.00 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3450627746 |
| 85.99 |
0.01 |
90.48 |
0.00 |
80.12 |
0.02 |
90.43 |
0.00 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.434637235 |
| 86.00 |
0.01 |
90.48 |
0.00 |
80.13 |
0.01 |
90.44 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3336279384 |
| 86.00 |
0.01 |
90.48 |
0.00 |
80.14 |
0.01 |
90.44 |
0.00 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.393334641 |
| 86.00 |
0.01 |
90.48 |
0.00 |
80.16 |
0.01 |
90.44 |
0.00 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2902501430 |
| 86.00 |
0.01 |
90.48 |
0.00 |
80.17 |
0.01 |
90.44 |
0.00 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio.475414757 |
| 86.01 |
0.01 |
90.48 |
0.00 |
80.17 |
0.00 |
90.46 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1977552732 |
| 86.01 |
0.01 |
90.49 |
0.01 |
80.18 |
0.01 |
90.46 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1222623978 |
| 86.01 |
0.01 |
90.49 |
0.01 |
80.18 |
0.00 |
90.46 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.580943609 |
| 86.01 |
0.01 |
90.49 |
0.00 |
80.19 |
0.01 |
90.46 |
0.00 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4288990429 |
| 86.01 |
0.01 |
90.49 |
0.00 |
80.19 |
0.00 |
90.47 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1047622041 |
| 86.01 |
0.01 |
90.49 |
0.00 |
80.19 |
0.00 |
90.48 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2944677870 |
| 86.02 |
0.01 |
90.49 |
0.00 |
80.19 |
0.00 |
90.49 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2802751248 |
| 86.02 |
0.01 |
90.49 |
0.00 |
80.19 |
0.00 |
90.50 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1323289117 |
| 86.02 |
0.01 |
90.49 |
0.00 |
80.19 |
0.00 |
90.51 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.4269334325 |
| 86.02 |
0.01 |
90.49 |
0.00 |
80.20 |
0.01 |
90.52 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_hmac_enc.3809642702 |
| 86.02 |
0.01 |
90.49 |
0.00 |
80.20 |
0.00 |
90.52 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.832244851 |
| 86.02 |
0.01 |
90.49 |
0.00 |
80.20 |
0.00 |
90.52 |
0.00 |
|
|
92.12 |
0.01 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_tap_straps_dev.408485744 |
| 86.02 |
0.01 |
90.49 |
0.00 |
80.20 |
0.01 |
90.52 |
0.00 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.711415655 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.20 |
0.00 |
90.53 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.4000939768 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.20 |
0.00 |
90.54 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2786862774 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.20 |
0.00 |
90.54 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2455121837 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.20 |
0.00 |
90.55 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1976040762 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.20 |
0.00 |
90.55 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.622689112 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.20 |
0.00 |
90.56 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.843479664 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.21 |
0.01 |
90.56 |
0.00 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio.3019100535 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.21 |
0.00 |
90.56 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.1353637189 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.21 |
0.00 |
90.56 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.969603521 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.21 |
0.00 |
90.56 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.327486796 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.21 |
0.00 |
90.57 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1658019296 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.21 |
0.00 |
90.57 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/0.rom_raw_unlock.1491670226 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.21 |
0.00 |
90.57 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.720572408 |
| 86.03 |
0.01 |
90.49 |
0.00 |
80.21 |
0.00 |
90.57 |
0.01 |
|
|
92.12 |
0.00 |
78.37 |
0.00 |
84.43 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1900670833 |
| Name |
| /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2452867735 |
| /workspace/coverage/default/0.chip_sival_flash_info_access.1134972222 |
| /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2117123161 |
| /workspace/coverage/default/0.chip_sw_aes_enc.3246892931 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.68990759 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1960007902 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.1492116857 |
| /workspace/coverage/default/0.chip_sw_aes_idle.2105472383 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.837193023 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.1252718633 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1981270351 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1371050476 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2862504021 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3437133989 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3520342970 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3796658115 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3723919531 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.661432532 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.4146991664 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1146867341 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2687114123 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3761204649 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3852680315 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.497869178 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.140799203 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.566422063 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.284690285 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2672493963 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2511025074 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.4132623156 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2946174993 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3930055974 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3314910739 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3946752667 |
| /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3137926789 |
| /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1899597769 |
| /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3477891888 |
| /workspace/coverage/default/0.chip_sw_coremark.3141889727 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1987695954 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2287546619 |
| /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.740279239 |
| /workspace/coverage/default/0.chip_sw_csrng_kat_test.2464881065 |
| /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.626003042 |
| /workspace/coverage/default/0.chip_sw_csrng_smoketest.1188304050 |
| /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3399451628 |
| /workspace/coverage/default/0.chip_sw_edn_auto_mode.2046477502 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1333641691 |
| /workspace/coverage/default/0.chip_sw_edn_kat.3905908516 |
| /workspace/coverage/default/0.chip_sw_edn_sw_mode.1872855819 |
| /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.123134642 |
| /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.505113428 |
| /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4202512831 |
| /workspace/coverage/default/0.chip_sw_example_concurrency.1529224671 |
| /workspace/coverage/default/0.chip_sw_example_flash.3057139179 |
| /workspace/coverage/default/0.chip_sw_example_manufacturer.606409851 |
| /workspace/coverage/default/0.chip_sw_example_rom.1635671704 |
| /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3901179314 |
| /workspace/coverage/default/0.chip_sw_flash_crash_alert.5540209 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3594746485 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1621274095 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1183133743 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3779760706 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2206344614 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3717282719 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2268546459 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2528383197 |
| /workspace/coverage/default/0.chip_sw_flash_init.2111478586 |
| /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3539105519 |
| /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.4273230506 |
| /workspace/coverage/default/0.chip_sw_gpio_smoketest.2956376746 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_idle.4097077794 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2508467857 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3756725256 |
| /workspace/coverage/default/0.chip_sw_hmac_smoketest.2464590442 |
| /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2416912632 |
| /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3100761528 |
| /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2313705410 |
| /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2726507007 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3870043745 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3524040862 |
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| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2814602283 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.525444533 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.500428101 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2933212333 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3141503702 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2354834258 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4032282844 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3417478202 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3430010886 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3829792865 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1630441769 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2981044955 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.227658880 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.11624412 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3427839473 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3638468156 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.559431939 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.4004100718 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1582579971 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3643768124 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.830650813 |
| /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1009176087 |
| /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2224967510 |
| /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1335941715 |
| /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3090194732 |
| /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2370266572 |
| /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3760725299 |
| /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.689579698 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1670841373 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1616577245 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3134433796 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.250030501 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3196792125 |
| /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4045332926 |
| /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2468802790 |
| /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.292063898 |
| /workspace/coverage/default/2.chip_sw_rv_timer_irq.1265638540 |
| /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.777663914 |
| /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1053455420 |
| /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2832413763 |
| /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2121584965 |
| /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1160556837 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3662699567 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2733932136 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2555295095 |
| /workspace/coverage/default/2.chip_sw_spi_device_tpm.1493697390 |
| /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1912126504 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1053715502 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2542362116 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.917472184 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1091445932 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2088622939 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1249855604 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1291185791 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1493894901 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3557248261 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4143800033 |
| /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2119257510 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest.2057507680 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest_signed.1343053866 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx.1754012225 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1635230536 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4207870290 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1103423649 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2083611091 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.791823981 |
| /workspace/coverage/default/2.chip_tap_straps_dev.986654632 |
| /workspace/coverage/default/2.chip_tap_straps_prod.21391956 |
| /workspace/coverage/default/2.chip_tap_straps_testunlock0.3117847319 |
| /workspace/coverage/default/2.rom_e2e_asm_init_dev.2805530238 |
| /workspace/coverage/default/2.rom_e2e_asm_init_prod.3145196404 |
| /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2773010553 |
| /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3601181078 |
| /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2347812329 |
| /workspace/coverage/default/2.rom_e2e_shutdown_output.668277701 |
| /workspace/coverage/default/2.rom_e2e_smoke.154242202 |
| /workspace/coverage/default/2.rom_e2e_static_critical.3439266305 |
| /workspace/coverage/default/2.rom_keymgr_functest.403691354 |
| /workspace/coverage/default/2.rom_raw_unlock.3601719121 |
| /workspace/coverage/default/2.rom_volatile_raw_unlock.2950729000 |
| /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3768468754 |
| /workspace/coverage/default/22.chip_sw_all_escalation_resets.1797034479 |
| /workspace/coverage/default/23.chip_sw_all_escalation_resets.3931174121 |
| /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.724743618 |
| /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2784428662 |
| /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1973885103 |
| /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1888763059 |
| /workspace/coverage/default/3.chip_sw_all_escalation_resets.1967429154 |
| /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4284920321 |
| /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3972426697 |
| /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2764076445 |
| /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.65020481 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx.1304751553 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4099598849 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2321353569 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2714934042 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3491301402 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2876379634 |
| /workspace/coverage/default/3.chip_tap_straps_dev.1033594564 |
| /workspace/coverage/default/3.chip_tap_straps_prod.4036414897 |
| /workspace/coverage/default/3.chip_tap_straps_rma.2709162668 |
| /workspace/coverage/default/3.chip_tap_straps_testunlock0.4024449050 |
| /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3625278036 |
| /workspace/coverage/default/31.chip_sw_all_escalation_resets.2490947436 |
| /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.694430052 |
| /workspace/coverage/default/33.chip_sw_all_escalation_resets.1709795090 |
| /workspace/coverage/default/34.chip_sw_all_escalation_resets.3612229064 |
| /workspace/coverage/default/35.chip_sw_all_escalation_resets.728377208 |
| /workspace/coverage/default/36.chip_sw_all_escalation_resets.405551667 |
| /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2777061285 |
| /workspace/coverage/default/38.chip_sw_all_escalation_resets.2241395455 |
| /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1093529375 |
| /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3341073169 |
| /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3586588687 |
| /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1222926137 |
| /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3454768044 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx.2332215439 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3505710279 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.704090296 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3934227335 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2586132737 |
| /workspace/coverage/default/4.chip_tap_straps_dev.576160641 |
| /workspace/coverage/default/4.chip_tap_straps_prod.2754992782 |
| /workspace/coverage/default/4.chip_tap_straps_rma.795721295 |
| /workspace/coverage/default/4.chip_tap_straps_testunlock0.928815382 |
| /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1128726663 |
| /workspace/coverage/default/40.chip_sw_all_escalation_resets.2184112917 |
| /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3762887617 |
| /workspace/coverage/default/41.chip_sw_all_escalation_resets.238290191 |
| /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3020370061 |
| /workspace/coverage/default/45.chip_sw_all_escalation_resets.591103756 |
| /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2461464913 |
| /workspace/coverage/default/47.chip_sw_all_escalation_resets.3148297388 |
| /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2294290760 |
| /workspace/coverage/default/48.chip_sw_all_escalation_resets.574859087 |
| /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161786496 |
| /workspace/coverage/default/49.chip_sw_all_escalation_resets.2678298041 |
| /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2128301558 |
| /workspace/coverage/default/5.chip_sw_all_escalation_resets.3790398266 |
| /workspace/coverage/default/5.chip_sw_data_integrity_escalation.4148359435 |
| /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3803093776 |
| /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1708913572 |
| /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1420915315 |
| /workspace/coverage/default/50.chip_sw_all_escalation_resets.763899546 |
| /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1053265526 |
| /workspace/coverage/default/51.chip_sw_all_escalation_resets.3983238699 |
| /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.869718477 |
| /workspace/coverage/default/52.chip_sw_all_escalation_resets.2824088537 |
| /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.404608532 |
| /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878832921 |
| /workspace/coverage/default/54.chip_sw_all_escalation_resets.2006480322 |
| /workspace/coverage/default/56.chip_sw_all_escalation_resets.3554881552 |
| /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.925491985 |
| /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3210053940 |
| /workspace/coverage/default/59.chip_sw_all_escalation_resets.1349803486 |
| /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1807769714 |
| /workspace/coverage/default/6.chip_sw_all_escalation_resets.2007161144 |
| /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.745079225 |
| /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1126356061 |
| /workspace/coverage/default/60.chip_sw_all_escalation_resets.3252131951 |
| /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1664485243 |
| /workspace/coverage/default/62.chip_sw_all_escalation_resets.2570980999 |
| /workspace/coverage/default/63.chip_sw_all_escalation_resets.1264179278 |
| /workspace/coverage/default/64.chip_sw_all_escalation_resets.2682905354 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.353454548 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2887974723 |
| /workspace/coverage/default/66.chip_sw_all_escalation_resets.352689622 |
| /workspace/coverage/default/67.chip_sw_all_escalation_resets.1011746248 |
| /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.515164696 |
| /workspace/coverage/default/68.chip_sw_all_escalation_resets.4027727825 |
| /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2075386586 |
| /workspace/coverage/default/69.chip_sw_all_escalation_resets.2809005124 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1271447063 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1584198478 |
| /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.178470585 |
| /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1949802731 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.354941293 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4058520061 |
| /workspace/coverage/default/72.chip_sw_all_escalation_resets.1818824279 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2735306808 |
| /workspace/coverage/default/73.chip_sw_all_escalation_resets.2901249305 |
| /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1507518859 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.1632684373 |
| /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2140493000 |
| /workspace/coverage/default/75.chip_sw_all_escalation_resets.1035143082 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1335196406 |
| /workspace/coverage/default/76.chip_sw_all_escalation_resets.335596220 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3156081598 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.1240903009 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3207196992 |
| /workspace/coverage/default/78.chip_sw_all_escalation_resets.1643483633 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.3905271727 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2275028903 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1736313352 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2809267548 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.834958565 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.3328298322 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.3169273973 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.647632281 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.975532686 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1585796636 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.3677342717 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2838228996 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.4187064119 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3619971678 |
| /workspace/coverage/default/86.chip_sw_all_escalation_resets.1560116210 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4212093831 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.692960134 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1339709815 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.265461991 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3608485307 |
| /workspace/coverage/default/90.chip_sw_all_escalation_resets.2388463841 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.811435888 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.3569499214 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.44563627 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.553103547 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.1496796707 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.1060279673 |
| /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2887853518 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3239000554 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4011387299 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1806587066 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3542077178 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2486178327 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2789984112 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1687216998 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2606338210 |
|
|
Mar 28 03:59:51 PM PDT 24 |
Mar 28 04:12:04 PM PDT 24 |
3894493736 ps |
| T2 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.345051639 |
|
|
Mar 28 03:49:22 PM PDT 24 |
Mar 28 04:11:33 PM PDT 24 |
13023027370 ps |
| T3 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3798701535 |
|
|
Mar 28 04:09:31 PM PDT 24 |
Mar 28 04:13:53 PM PDT 24 |
2490104490 ps |
| T30 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3841914998 |
|
|
Mar 28 03:43:47 PM PDT 24 |
Mar 28 03:52:58 PM PDT 24 |
7551349802 ps |
| T80 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1816871272 |
|
|
Mar 28 04:05:21 PM PDT 24 |
Mar 28 04:14:02 PM PDT 24 |
3780363250 ps |
| T81 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.162665183 |
|
|
Mar 28 04:01:07 PM PDT 24 |
Mar 28 04:29:08 PM PDT 24 |
7318998530 ps |
| T4 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.177433503 |
|
|
Mar 28 03:50:19 PM PDT 24 |
Mar 28 05:15:13 PM PDT 24 |
44703061648 ps |
| T82 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.589993579 |
|
|
Mar 28 04:02:32 PM PDT 24 |
Mar 28 04:06:20 PM PDT 24 |
2680588136 ps |
| T83 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161786496 |
|
|
Mar 28 04:12:15 PM PDT 24 |
Mar 28 04:17:53 PM PDT 24 |
3704855552 ps |
| T39 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.945188533 |
|
|
Mar 28 04:10:18 PM PDT 24 |
Mar 28 04:38:08 PM PDT 24 |
8244451279 ps |
| T5 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3007525751 |
|
|
Mar 28 04:03:19 PM PDT 24 |
Mar 28 04:06:25 PM PDT 24 |
3910361702 ps |
| T40 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.1343053866 |
|
|
Mar 28 04:10:11 PM PDT 24 |
Mar 28 04:37:45 PM PDT 24 |
8884913500 ps |
| T178 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.832244851 |
|
|
Mar 28 04:02:06 PM PDT 24 |
Mar 28 04:09:43 PM PDT 24 |
3964937680 ps |
| T195 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4212093831 |
|
|
Mar 28 04:14:12 PM PDT 24 |
Mar 28 04:19:28 PM PDT 24 |
3562305480 ps |
| T43 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3328620704 |
|
|
Mar 28 03:51:50 PM PDT 24 |
Mar 28 04:00:53 PM PDT 24 |
5001141430 ps |
| T177 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1529782033 |
|
|
Mar 28 03:48:03 PM PDT 24 |
Mar 28 04:04:17 PM PDT 24 |
5141714934 ps |
| T206 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3760725299 |
|
|
Mar 28 04:00:38 PM PDT 24 |
Mar 28 04:10:48 PM PDT 24 |
5040078746 ps |
| T73 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3171073558 |
|
|
Mar 28 04:14:28 PM PDT 24 |
Mar 28 04:23:26 PM PDT 24 |
5392932568 ps |
| T139 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1192644941 |
|
|
Mar 28 04:07:23 PM PDT 24 |
Mar 28 04:16:20 PM PDT 24 |
4139864884 ps |
| T46 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3253499543 |
|
|
Mar 28 03:50:21 PM PDT 24 |
Mar 28 03:55:26 PM PDT 24 |
4252695266 ps |
| T74 |
/workspace/coverage/default/2.chip_tap_straps_rma.2342330413 |
|
|
Mar 28 04:04:40 PM PDT 24 |
Mar 28 04:11:17 PM PDT 24 |
4102546911 ps |
| T6 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3709709607 |
|
|
Mar 28 04:11:04 PM PDT 24 |
Mar 28 04:17:31 PM PDT 24 |
5168902661 ps |
| T115 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1960007902 |
|
|
Mar 28 03:47:25 PM PDT 24 |
Mar 28 03:51:26 PM PDT 24 |
2805426379 ps |
| T173 |
/workspace/coverage/default/1.chip_sw_aes_idle.1559434886 |
|
|
Mar 28 03:48:13 PM PDT 24 |
Mar 28 03:52:28 PM PDT 24 |
2422787014 ps |
| T109 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2628172412 |
|
|
Mar 28 03:47:46 PM PDT 24 |
Mar 28 07:31:03 PM PDT 24 |
77753580690 ps |
| T222 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.453822475 |
|
|
Mar 28 03:49:55 PM PDT 24 |
Mar 28 04:03:46 PM PDT 24 |
7275316248 ps |
| T113 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2655814795 |
|
|
Mar 28 03:48:44 PM PDT 24 |
Mar 28 04:01:51 PM PDT 24 |
6465595730 ps |
| T10 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.62421644 |
|
|
Mar 28 03:45:13 PM PDT 24 |
Mar 28 03:58:10 PM PDT 24 |
7188162065 ps |
| T163 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1644500599 |
|
|
Mar 28 04:03:22 PM PDT 24 |
Mar 28 04:14:05 PM PDT 24 |
5035584104 ps |
| T152 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.281256987 |
|
|
Mar 28 03:50:55 PM PDT 24 |
Mar 28 04:14:42 PM PDT 24 |
11051000016 ps |
| T116 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.508757314 |
|
|
Mar 28 03:47:06 PM PDT 24 |
Mar 28 04:03:35 PM PDT 24 |
5174369977 ps |
| T117 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4099273706 |
|
|
Mar 28 03:46:50 PM PDT 24 |
Mar 28 03:55:15 PM PDT 24 |
5926406121 ps |
| T114 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.559431939 |
|
|
Mar 28 04:05:25 PM PDT 24 |
Mar 28 04:11:03 PM PDT 24 |
5158151362 ps |
| T341 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4137575530 |
|
|
Mar 28 04:10:37 PM PDT 24 |
Mar 28 04:17:32 PM PDT 24 |
3463150390 ps |
| T333 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.515164696 |
|
|
Mar 28 04:11:46 PM PDT 24 |
Mar 28 04:17:59 PM PDT 24 |
3827449156 ps |
| T41 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.3145196404 |
|
|
Mar 28 04:08:55 PM PDT 24 |
Mar 28 04:37:44 PM PDT 24 |
8975609613 ps |
| T508 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1661005306 |
|
|
Mar 28 04:08:47 PM PDT 24 |
Mar 28 04:16:06 PM PDT 24 |
3955557210 ps |
| T260 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1729844776 |
|
|
Mar 28 03:47:43 PM PDT 24 |
Mar 28 03:58:52 PM PDT 24 |
5272275920 ps |
| T544 |
/workspace/coverage/default/0.chip_sw_aes_idle.2105472383 |
|
|
Mar 28 03:46:05 PM PDT 24 |
Mar 28 03:49:59 PM PDT 24 |
2633681320 ps |
| T258 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1140618206 |
|
|
Mar 28 03:56:18 PM PDT 24 |
Mar 28 04:00:44 PM PDT 24 |
3198934068 ps |
| T378 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3688560300 |
|
|
Mar 28 04:12:35 PM PDT 24 |
Mar 28 04:18:16 PM PDT 24 |
3694199158 ps |
| T167 |
/workspace/coverage/default/1.rom_keymgr_functest.3835811410 |
|
|
Mar 28 03:55:11 PM PDT 24 |
Mar 28 04:03:36 PM PDT 24 |
3284741520 ps |
| T385 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.222118730 |
|
|
Mar 28 03:49:02 PM PDT 24 |
Mar 28 03:57:49 PM PDT 24 |
4614968908 ps |
| T42 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2289924592 |
|
|
Mar 28 03:53:18 PM PDT 24 |
Mar 28 04:29:16 PM PDT 24 |
9241244232 ps |
| T145 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.414936029 |
|
|
Mar 28 03:46:56 PM PDT 24 |
Mar 28 03:56:10 PM PDT 24 |
4788008392 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.650920968 |
|
|
Mar 28 03:46:28 PM PDT 24 |
Mar 28 04:52:29 PM PDT 24 |
18516019946 ps |
| T168 |
/workspace/coverage/default/0.rom_keymgr_functest.79349590 |
|
|
Mar 28 03:47:57 PM PDT 24 |
Mar 28 03:54:38 PM PDT 24 |
5040350856 ps |
| T111 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2802751248 |
|
|
Mar 28 03:45:22 PM PDT 24 |
Mar 28 03:57:45 PM PDT 24 |
9596858272 ps |
| T265 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3152801838 |
|
|
Mar 28 04:07:58 PM PDT 24 |
Mar 28 04:18:14 PM PDT 24 |
4554866932 ps |
| T110 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2726507007 |
|
|
Mar 28 03:44:31 PM PDT 24 |
Mar 28 06:55:18 PM PDT 24 |
65344729348 ps |
| T266 |
/workspace/coverage/default/2.rom_e2e_static_critical.3439266305 |
|
|
Mar 28 04:10:27 PM PDT 24 |
Mar 28 04:43:49 PM PDT 24 |
10761165006 ps |
| T131 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.967550285 |
|
|
Mar 28 03:47:17 PM PDT 24 |
Mar 28 04:01:40 PM PDT 24 |
7576531968 ps |
| T215 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.887112992 |
|
|
Mar 28 04:08:50 PM PDT 24 |
Mar 28 04:14:44 PM PDT 24 |
3874172904 ps |
| T62 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.3524589084 |
|
|
Mar 28 04:02:00 PM PDT 24 |
Mar 28 04:08:00 PM PDT 24 |
2822577172 ps |
| T205 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3920396684 |
|
|
Mar 28 03:49:28 PM PDT 24 |
Mar 28 04:09:56 PM PDT 24 |
10966961675 ps |
| T123 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.943672428 |
|
|
Mar 28 04:03:00 PM PDT 24 |
Mar 28 04:53:18 PM PDT 24 |
12726737316 ps |
| T172 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1813351329 |
|
|
Mar 28 04:03:23 PM PDT 24 |
Mar 28 04:27:33 PM PDT 24 |
8999792904 ps |
| T124 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1077229797 |
|
|
Mar 28 04:02:06 PM PDT 24 |
Mar 28 04:29:29 PM PDT 24 |
7370120514 ps |
| T190 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4187545152 |
|
|
Mar 28 04:09:57 PM PDT 24 |
Mar 28 04:17:14 PM PDT 24 |
3761821312 ps |
| T143 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2592072060 |
|
|
Mar 28 04:06:40 PM PDT 24 |
Mar 28 04:17:43 PM PDT 24 |
6206503340 ps |
| T221 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.745079225 |
|
|
Mar 28 04:07:52 PM PDT 24 |
Mar 28 04:15:05 PM PDT 24 |
7123860268 ps |
| T120 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3586888881 |
|
|
Mar 28 03:43:25 PM PDT 24 |
Mar 28 03:50:26 PM PDT 24 |
4007582470 ps |
| T169 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3618685675 |
|
|
Mar 28 03:47:52 PM PDT 24 |
Mar 28 03:54:26 PM PDT 24 |
3213087114 ps |
| T307 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3573957573 |
|
|
Mar 28 03:53:32 PM PDT 24 |
Mar 28 04:30:19 PM PDT 24 |
8262325800 ps |
| T226 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4187037840 |
|
|
Mar 28 04:11:14 PM PDT 24 |
Mar 28 04:17:14 PM PDT 24 |
3641737870 ps |
| T186 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2862504021 |
|
|
Mar 28 03:46:54 PM PDT 24 |
Mar 28 04:25:57 PM PDT 24 |
9433520064 ps |
| T223 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3100761528 |
|
|
Mar 28 03:47:23 PM PDT 24 |
Mar 28 04:03:01 PM PDT 24 |
5554337632 ps |
| T144 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.3089115253 |
|
|
Mar 28 04:09:09 PM PDT 24 |
Mar 28 04:19:33 PM PDT 24 |
5182067144 ps |
| T261 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.1902248891 |
|
|
Mar 28 03:52:28 PM PDT 24 |
Mar 28 03:59:18 PM PDT 24 |
3859675902 ps |
| T164 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.4097077794 |
|
|
Mar 28 03:47:32 PM PDT 24 |
Mar 28 03:51:47 PM PDT 24 |
2881934504 ps |
| T63 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1981270351 |
|
|
Mar 28 03:46:58 PM PDT 24 |
Mar 28 03:52:31 PM PDT 24 |
3046515981 ps |
| T392 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4158994420 |
|
|
Mar 28 04:02:12 PM PDT 24 |
Mar 28 04:09:18 PM PDT 24 |
3939336366 ps |
| T335 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4223691653 |
|
|
Mar 28 04:04:10 PM PDT 24 |
Mar 28 04:11:34 PM PDT 24 |
4260432282 ps |
| T19 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2920626356 |
|
|
Mar 28 03:47:24 PM PDT 24 |
Mar 28 04:21:14 PM PDT 24 |
24630946456 ps |
| T54 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.799107692 |
|
|
Mar 28 03:51:11 PM PDT 24 |
Mar 28 04:01:34 PM PDT 24 |
4204820400 ps |
| T332 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.64951345 |
|
|
Mar 28 04:13:10 PM PDT 24 |
Mar 28 04:22:14 PM PDT 24 |
5377515500 ps |
| T7 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.970484483 |
|
|
Mar 28 03:56:30 PM PDT 24 |
Mar 28 04:01:45 PM PDT 24 |
3110727192 ps |
| T13 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.752142480 |
|
|
Mar 28 03:55:09 PM PDT 24 |
Mar 28 03:58:41 PM PDT 24 |
2530031963 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_power_idle_load.1657929962 |
|
|
Mar 28 03:51:25 PM PDT 24 |
Mar 28 04:01:12 PM PDT 24 |
4137980566 ps |
| T369 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3386767850 |
|
|
Mar 28 04:10:07 PM PDT 24 |
Mar 28 04:21:17 PM PDT 24 |
4844658268 ps |
| T487 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.585365802 |
|
|
Mar 28 04:07:58 PM PDT 24 |
Mar 28 04:18:19 PM PDT 24 |
5644388684 ps |
| T472 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.622689112 |
|
|
Mar 28 03:47:38 PM PDT 24 |
Mar 28 03:56:56 PM PDT 24 |
7478281064 ps |
| T305 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4288990429 |
|
|
Mar 28 03:48:06 PM PDT 24 |
Mar 28 04:03:27 PM PDT 24 |
4921320344 ps |
| T545 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1087025497 |
|
|
Mar 28 03:48:04 PM PDT 24 |
Mar 28 03:52:35 PM PDT 24 |
2446149466 ps |
| T473 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2944677870 |
|
|
Mar 28 03:47:05 PM PDT 24 |
Mar 28 04:06:42 PM PDT 24 |
6317832180 ps |
| T384 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.619152937 |
|
|
Mar 28 03:43:47 PM PDT 24 |
Mar 28 03:53:47 PM PDT 24 |
5883036848 ps |
| T200 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2885980528 |
|
|
Mar 28 03:56:02 PM PDT 24 |
Mar 28 04:25:38 PM PDT 24 |
6411486300 ps |
| T347 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.352689622 |
|
|
Mar 28 04:11:51 PM PDT 24 |
Mar 28 04:21:18 PM PDT 24 |
5683959972 ps |
| T199 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1188661522 |
|
|
Mar 28 03:58:40 PM PDT 24 |
Mar 28 05:27:31 PM PDT 24 |
49288738348 ps |
| T370 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3796658115 |
|
|
Mar 28 03:46:59 PM PDT 24 |
Mar 28 03:56:56 PM PDT 24 |
4872264720 ps |
| T121 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3666837687 |
|
|
Mar 28 03:45:34 PM PDT 24 |
Mar 28 03:55:11 PM PDT 24 |
3794148586 ps |
| T161 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1033929482 |
|
|
Mar 28 03:49:03 PM PDT 24 |
Mar 28 03:55:37 PM PDT 24 |
4734725888 ps |
| T204 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3507492420 |
|
|
Mar 28 03:46:55 PM PDT 24 |
Mar 28 03:49:15 PM PDT 24 |
2780426995 ps |
| T11 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1912126504 |
|
|
Mar 28 03:57:49 PM PDT 24 |
Mar 28 04:01:09 PM PDT 24 |
2852654174 ps |
| T17 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1630441769 |
|
|
Mar 28 04:05:48 PM PDT 24 |
Mar 28 04:20:50 PM PDT 24 |
16343680440 ps |
| T102 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1014133487 |
|
|
Mar 28 03:48:37 PM PDT 24 |
Mar 28 03:51:37 PM PDT 24 |
2763984126 ps |
| T103 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3367193297 |
|
|
Mar 28 04:01:35 PM PDT 24 |
Mar 28 04:10:53 PM PDT 24 |
4088822028 ps |
| T14 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2269065018 |
|
|
Mar 28 03:47:59 PM PDT 24 |
Mar 28 04:15:25 PM PDT 24 |
8076695656 ps |
| T104 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.870497759 |
|
|
Mar 28 03:53:39 PM PDT 24 |
Mar 28 03:59:12 PM PDT 24 |
2551632344 ps |
| T105 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.1943045118 |
|
|
Mar 28 03:51:02 PM PDT 24 |
Mar 28 03:54:09 PM PDT 24 |
2338873764 ps |
| T106 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.2746850904 |
|
|
Mar 28 03:48:36 PM PDT 24 |
Mar 28 03:50:37 PM PDT 24 |
2290398866 ps |
| T20 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3570473211 |
|
|
Mar 28 03:51:42 PM PDT 24 |
Mar 28 04:44:48 PM PDT 24 |
20227099274 ps |
| T107 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3141503702 |
|
|
Mar 28 03:59:38 PM PDT 24 |
Mar 28 04:06:40 PM PDT 24 |
6666500772 ps |
| T108 |
/workspace/coverage/default/2.chip_sw_aes_entropy.2420367630 |
|
|
Mar 28 04:01:54 PM PDT 24 |
Mar 28 04:05:32 PM PDT 24 |
3000091088 ps |
| T129 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3716518466 |
|
|
Mar 28 03:57:43 PM PDT 24 |
Mar 28 05:01:53 PM PDT 24 |
25425858284 ps |
| T196 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.496644275 |
|
|
Mar 28 03:45:33 PM PDT 24 |
Mar 28 03:47:14 PM PDT 24 |
2357855379 ps |
| T351 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.711415655 |
|
|
Mar 28 03:46:47 PM PDT 24 |
Mar 28 03:57:22 PM PDT 24 |
4039379872 ps |
| T170 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3280342564 |
|
|
Mar 28 04:02:08 PM PDT 24 |
Mar 28 04:07:07 PM PDT 24 |
3010443432 ps |
| T245 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1339709815 |
|
|
Mar 28 04:13:20 PM PDT 24 |
Mar 28 04:22:40 PM PDT 24 |
3955486424 ps |
| T285 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3207196992 |
|
|
Mar 28 04:13:00 PM PDT 24 |
Mar 28 04:18:34 PM PDT 24 |
2977287520 ps |
| T64 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2192013517 |
|
|
Mar 28 03:47:33 PM PDT 24 |
Mar 28 04:14:13 PM PDT 24 |
11397573040 ps |
| T286 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4003016715 |
|
|
Mar 28 03:47:11 PM PDT 24 |
Mar 28 04:06:53 PM PDT 24 |
8388354488 ps |
| T287 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1053265526 |
|
|
Mar 28 04:11:43 PM PDT 24 |
Mar 28 04:16:34 PM PDT 24 |
3372067224 ps |
| T288 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3554881552 |
|
|
Mar 28 04:11:52 PM PDT 24 |
Mar 28 04:23:42 PM PDT 24 |
5517830680 ps |
| T234 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1865315965 |
|
|
Mar 28 03:51:47 PM PDT 24 |
Mar 28 03:57:05 PM PDT 24 |
3490263147 ps |
| T15 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.4278829254 |
|
|
Mar 28 03:45:10 PM PDT 24 |
Mar 28 03:53:12 PM PDT 24 |
4621012294 ps |
| T289 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2753016039 |
|
|
Mar 28 03:56:35 PM PDT 24 |
Mar 28 03:59:17 PM PDT 24 |
1823430350 ps |
| T290 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2013326551 |
|
|
Mar 28 04:10:33 PM PDT 24 |
Mar 28 04:16:55 PM PDT 24 |
3471472776 ps |
| T348 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2140650375 |
|
|
Mar 28 03:49:27 PM PDT 24 |
Mar 28 04:01:58 PM PDT 24 |
6962680460 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3349407249 |
|
|
Mar 28 03:59:02 PM PDT 24 |
Mar 28 05:29:35 PM PDT 24 |
47735700588 ps |
| T474 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3713609252 |
|
|
Mar 28 03:52:32 PM PDT 24 |
Mar 28 03:58:35 PM PDT 24 |
3400771736 ps |
| T141 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.497869178 |
|
|
Mar 28 03:47:28 PM PDT 24 |
Mar 28 03:56:47 PM PDT 24 |
4610675984 ps |
| T244 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.482318741 |
|
|
Mar 28 04:02:32 PM PDT 24 |
Mar 28 04:12:43 PM PDT 24 |
5572037266 ps |
| T162 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2451063019 |
|
|
Mar 28 03:45:48 PM PDT 24 |
Mar 28 04:02:50 PM PDT 24 |
4175982484 ps |
| T150 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2018700017 |
|
|
Mar 28 03:56:29 PM PDT 24 |
Mar 28 04:09:50 PM PDT 24 |
6167243640 ps |
| T509 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1420915315 |
|
|
Mar 28 04:12:01 PM PDT 24 |
Mar 28 04:17:22 PM PDT 24 |
3756171074 ps |
| T153 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.423137928 |
|
|
Mar 28 04:02:46 PM PDT 24 |
Mar 28 04:12:00 PM PDT 24 |
3307664178 ps |
| T246 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3500449383 |
|
|
Mar 28 04:10:06 PM PDT 24 |
Mar 28 04:23:19 PM PDT 24 |
4346465670 ps |
| T469 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.751955505 |
|
|
Mar 28 04:08:20 PM PDT 24 |
Mar 28 04:15:00 PM PDT 24 |
4000607064 ps |
| T352 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.454324695 |
|
|
Mar 28 03:50:25 PM PDT 24 |
Mar 28 04:02:23 PM PDT 24 |
4398232310 ps |
| T546 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4202512831 |
|
|
Mar 28 03:47:33 PM PDT 24 |
Mar 28 03:55:01 PM PDT 24 |
3774614986 ps |
| T547 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.3931645566 |
|
|
Mar 28 03:56:30 PM PDT 24 |
Mar 28 04:00:13 PM PDT 24 |
2780708860 ps |
| T191 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1426329453 |
|
|
Mar 28 03:56:01 PM PDT 24 |
Mar 28 04:34:20 PM PDT 24 |
9686386720 ps |
| T338 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4143800033 |
|
|
Mar 28 04:03:19 PM PDT 24 |
Mar 28 04:12:00 PM PDT 24 |
5380913032 ps |
| T235 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1103423649 |
|
|
Mar 28 03:56:48 PM PDT 24 |
Mar 28 04:08:52 PM PDT 24 |
4563489160 ps |
| T548 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.4146991664 |
|
|
Mar 28 03:47:27 PM PDT 24 |
Mar 28 03:52:36 PM PDT 24 |
2675784144 ps |
| T171 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3368030077 |
|
|
Mar 28 03:51:26 PM PDT 24 |
Mar 28 04:01:23 PM PDT 24 |
5323707880 ps |
| T451 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1227900412 |
|
|
Mar 28 04:07:56 PM PDT 24 |
Mar 28 04:14:55 PM PDT 24 |
3817581664 ps |
| T224 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2639181932 |
|
|
Mar 28 03:48:13 PM PDT 24 |
Mar 28 04:01:35 PM PDT 24 |
5744511928 ps |
| T248 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3547025913 |
|
|
Mar 28 03:53:58 PM PDT 24 |
Mar 28 04:45:02 PM PDT 24 |
11722750704 ps |
| T454 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3020370061 |
|
|
Mar 28 04:11:24 PM PDT 24 |
Mar 28 04:17:26 PM PDT 24 |
3789200216 ps |
| T12 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3277185494 |
|
|
Mar 28 03:47:49 PM PDT 24 |
Mar 28 03:58:41 PM PDT 24 |
6830436495 ps |
| T125 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.3943052676 |
|
|
Mar 28 04:03:29 PM PDT 24 |
Mar 28 04:20:52 PM PDT 24 |
4568022320 ps |
| T452 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2735306808 |
|
|
Mar 28 04:14:22 PM PDT 24 |
Mar 28 04:20:29 PM PDT 24 |
3848520082 ps |
| T339 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.245098841 |
|
|
Mar 28 03:46:37 PM PDT 24 |
Mar 28 04:09:19 PM PDT 24 |
13765985446 ps |
| T336 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1708913572 |
|
|
Mar 28 04:08:12 PM PDT 24 |
Mar 28 04:16:31 PM PDT 24 |
3595350210 ps |
| T448 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2779165125 |
|
|
Mar 28 04:09:49 PM PDT 24 |
Mar 28 04:20:02 PM PDT 24 |
4447575056 ps |
| T165 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1806027603 |
|
|
Mar 28 03:53:39 PM PDT 24 |
Mar 28 03:57:51 PM PDT 24 |
2846598400 ps |
| T24 |
/workspace/coverage/default/1.chip_sw_gpio.475414757 |
|
|
Mar 28 03:48:21 PM PDT 24 |
Mar 28 03:56:19 PM PDT 24 |
4015923428 ps |
| T549 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4277920394 |
|
|
Mar 28 03:45:12 PM PDT 24 |
Mar 28 04:05:32 PM PDT 24 |
6186387656 ps |
| T550 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.2805530238 |
|
|
Mar 28 04:08:45 PM PDT 24 |
Mar 28 04:40:31 PM PDT 24 |
8740136648 ps |
| T308 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1160556837 |
|
|
Mar 28 03:58:34 PM PDT 24 |
Mar 28 04:18:01 PM PDT 24 |
7259185998 ps |
| T551 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.120605671 |
|
|
Mar 28 03:51:41 PM PDT 24 |
Mar 28 04:25:32 PM PDT 24 |
8592597130 ps |
| T470 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1128726663 |
|
|
Mar 28 04:09:52 PM PDT 24 |
Mar 28 04:17:08 PM PDT 24 |
3663227704 ps |
| T481 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2809267548 |
|
|
Mar 28 04:13:28 PM PDT 24 |
Mar 28 04:19:02 PM PDT 24 |
3644274652 ps |
| T462 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.404608532 |
|
|
Mar 28 04:12:00 PM PDT 24 |
Mar 28 04:17:36 PM PDT 24 |
3927170376 ps |
| T485 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3350300530 |
|
|
Mar 28 04:10:45 PM PDT 24 |
Mar 28 04:18:03 PM PDT 24 |
4144988470 ps |
| T346 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1967429154 |
|
|
Mar 28 04:06:17 PM PDT 24 |
Mar 28 04:14:39 PM PDT 24 |
4476202308 ps |
| T236 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2714934042 |
|
|
Mar 28 04:06:38 PM PDT 24 |
Mar 28 04:16:07 PM PDT 24 |
3525861380 ps |
| T227 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2158489670 |
|
|
Mar 28 03:47:27 PM PDT 24 |
Mar 28 03:58:06 PM PDT 24 |
4248895988 ps |
| T8 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3439761757 |
|
|
Mar 28 03:45:44 PM PDT 24 |
Mar 28 03:52:25 PM PDT 24 |
3171510100 ps |
| T238 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4207870290 |
|
|
Mar 28 04:01:00 PM PDT 24 |
Mar 28 04:09:44 PM PDT 24 |
4014091417 ps |
| T475 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2916915865 |
|
|
Mar 28 04:09:45 PM PDT 24 |
Mar 28 04:17:00 PM PDT 24 |
3843692600 ps |
| T194 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.469949271 |
|
|
Mar 28 04:02:39 PM PDT 24 |
Mar 28 04:25:47 PM PDT 24 |
10401890400 ps |
| T157 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1909522206 |
|
|
Mar 28 04:02:24 PM PDT 24 |
Mar 28 04:26:00 PM PDT 24 |
13430315778 ps |
| T334 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1372391757 |
|
|
Mar 28 03:51:04 PM PDT 24 |
Mar 28 04:01:16 PM PDT 24 |
3509951586 ps |
| T174 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1199495187 |
|
|
Mar 28 04:11:03 PM PDT 24 |
Mar 28 04:21:16 PM PDT 24 |
5083696310 ps |
| T209 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1368462016 |
|
|
Mar 28 03:59:28 PM PDT 24 |
Mar 28 04:20:02 PM PDT 24 |
8465856852 ps |
| T371 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2580148533 |
|
|
Mar 28 03:58:05 PM PDT 24 |
Mar 28 04:05:11 PM PDT 24 |
3848185228 ps |
| T552 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.4007826240 |
|
|
Mar 28 03:48:22 PM PDT 24 |
Mar 28 03:52:17 PM PDT 24 |
2606201734 ps |
| T553 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.11624412 |
|
|
Mar 28 04:00:00 PM PDT 24 |
Mar 28 04:09:07 PM PDT 24 |
6383698024 ps |
| T309 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2824217679 |
|
|
Mar 28 03:47:38 PM PDT 24 |
Mar 28 03:55:42 PM PDT 24 |
4154066608 ps |
| T327 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3430010886 |
|
|
Mar 28 03:59:39 PM PDT 24 |
Mar 28 04:11:53 PM PDT 24 |
7193222592 ps |
| T554 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2981225236 |
|
|
Mar 28 03:58:44 PM PDT 24 |
Mar 28 04:08:59 PM PDT 24 |
4859531848 ps |
| T267 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.2950729000 |
|
|
Mar 28 04:05:39 PM PDT 24 |
Mar 28 04:07:33 PM PDT 24 |
2221843223 ps |
| T501 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.975532686 |
|
|
Mar 28 04:13:38 PM PDT 24 |
Mar 28 04:19:53 PM PDT 24 |
4205683580 ps |
| T555 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.499881918 |
|
|
Mar 28 03:46:45 PM PDT 24 |
Mar 28 03:57:58 PM PDT 24 |
4711312016 ps |
| T192 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.2508346450 |
|
|
Mar 28 04:04:14 PM PDT 24 |
Mar 28 04:30:17 PM PDT 24 |
7730877650 ps |
| T344 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1131905892 |
|
|
Mar 28 03:59:24 PM PDT 24 |
Mar 28 04:24:34 PM PDT 24 |
10368448745 ps |
| T479 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3520342970 |
|
|
Mar 28 03:46:13 PM PDT 24 |
Mar 28 03:53:33 PM PDT 24 |
3880515340 ps |
| T360 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1264179278 |
|
|
Mar 28 04:10:49 PM PDT 24 |
Mar 28 04:20:20 PM PDT 24 |
5711700784 ps |
| T420 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3169273973 |
|
|
Mar 28 04:14:46 PM PDT 24 |
Mar 28 04:22:35 PM PDT 24 |
6004008486 ps |
| T230 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2997914207 |
|
|
Mar 28 03:58:12 PM PDT 24 |
Mar 28 04:14:38 PM PDT 24 |
5565893732 ps |
| T310 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2336644580 |
|
|
Mar 28 04:14:37 PM PDT 24 |
Mar 28 04:20:07 PM PDT 24 |
3420671120 ps |
| T556 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.606409851 |
|
|
Mar 28 03:44:47 PM PDT 24 |
Mar 28 03:48:02 PM PDT 24 |
2823016266 ps |
| T445 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.3931174121 |
|
|
Mar 28 04:08:12 PM PDT 24 |
Mar 28 04:15:58 PM PDT 24 |
5192702700 ps |
| T557 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.774599634 |
|
|
Mar 28 03:57:45 PM PDT 24 |
Mar 28 04:34:53 PM PDT 24 |
9221780385 ps |
| T210 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1658019296 |
|
|
Mar 28 03:47:52 PM PDT 24 |
Mar 28 04:01:05 PM PDT 24 |
7381533496 ps |
| T558 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.924280885 |
|
|
Mar 28 03:58:27 PM PDT 24 |
Mar 28 04:08:41 PM PDT 24 |
5439080957 ps |
| T559 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1543838400 |
|
|
Mar 28 03:56:33 PM PDT 24 |
Mar 28 04:00:24 PM PDT 24 |
2168711270 ps |
| T560 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.426732230 |
|
|
Mar 28 03:50:47 PM PDT 24 |
Mar 28 04:21:45 PM PDT 24 |
7285839460 ps |
| T460 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.238290191 |
|
|
Mar 28 04:09:44 PM PDT 24 |
Mar 28 04:18:29 PM PDT 24 |
4813335256 ps |
| T183 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2555295095 |
|
|
Mar 28 03:59:37 PM PDT 24 |
Mar 28 04:12:38 PM PDT 24 |
6590375827 ps |
| T356 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2876379634 |
|
|
Mar 28 04:05:16 PM PDT 24 |
Mar 28 04:17:18 PM PDT 24 |
4018763500 ps |
| T160 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3946752667 |
|
|
Mar 28 03:45:19 PM PDT 24 |
Mar 28 04:04:01 PM PDT 24 |
8348387650 ps |
| T175 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2946174993 |
|
|
Mar 28 03:46:26 PM PDT 24 |
Mar 28 03:55:46 PM PDT 24 |
4595053744 ps |
| T561 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2929901983 |
|
|
Mar 28 03:55:36 PM PDT 24 |
Mar 28 04:30:52 PM PDT 24 |
9118950184 ps |
| T463 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.574859087 |
|
|
Mar 28 04:12:34 PM PDT 24 |
Mar 28 04:24:15 PM PDT 24 |
4690424764 ps |
| T453 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2725995941 |
|
|
Mar 28 04:13:42 PM PDT 24 |
Mar 28 04:20:41 PM PDT 24 |
3742383912 ps |
| T562 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3662699567 |
|
|
Mar 28 04:04:02 PM PDT 24 |
Mar 28 04:14:04 PM PDT 24 |
6245797800 ps |
| T489 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2765284791 |
|
|
Mar 28 04:10:29 PM PDT 24 |
Mar 28 04:17:20 PM PDT 24 |
3199554776 ps |
| T112 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3036480654 |
|
|
Mar 28 03:49:57 PM PDT 24 |
Mar 28 03:56:38 PM PDT 24 |
6102625372 ps |
| T18 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.2283491706 |
|
|
Mar 28 03:46:39 PM PDT 24 |
Mar 28 03:51:25 PM PDT 24 |
2964704752 ps |
| T130 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.829107776 |
|
|
Mar 28 04:02:24 PM PDT 24 |
Mar 28 04:15:34 PM PDT 24 |
4860876092 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1266707958 |
|
|
Mar 28 03:49:50 PM PDT 24 |
Mar 28 03:56:16 PM PDT 24 |
4358895970 ps |
| T21 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1641866829 |
|
|
Mar 28 03:50:33 PM PDT 24 |
Mar 28 04:39:59 PM PDT 24 |
20217480384 ps |
| T563 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3477891888 |
|
|
Mar 28 03:47:23 PM PDT 24 |
Mar 28 03:51:11 PM PDT 24 |
2809687404 ps |
| T60 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.3117847319 |
|
|
Mar 28 04:05:04 PM PDT 24 |
Mar 28 04:14:38 PM PDT 24 |
5809709456 ps |
| T446 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.763899546 |
|
|
Mar 28 04:10:49 PM PDT 24 |
Mar 28 04:20:03 PM PDT 24 |
4757433376 ps |
| T44 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1504101008 |
|
|
Mar 28 03:49:49 PM PDT 24 |
Mar 28 04:19:34 PM PDT 24 |
24693786258 ps |
| T361 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.728377208 |
|
|
Mar 28 04:11:43 PM PDT 24 |
Mar 28 04:22:01 PM PDT 24 |
4806667568 ps |
| T154 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.423275451 |
|
|
Mar 28 03:59:44 PM PDT 24 |
Mar 28 04:09:12 PM PDT 24 |
4025457701 ps |
| T84 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2784428662 |
|
|
Mar 28 04:08:36 PM PDT 24 |
Mar 28 04:15:20 PM PDT 24 |
3949629536 ps |
| T91 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3762887617 |
|
|
Mar 28 04:12:11 PM PDT 24 |
Mar 28 04:17:35 PM PDT 24 |
3286071980 ps |
| T92 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3336279384 |
|
|
Mar 28 03:45:41 PM PDT 24 |
Mar 28 04:18:17 PM PDT 24 |
14159824536 ps |
| T93 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.968510189 |
|
|
Mar 28 03:52:40 PM PDT 24 |
Mar 28 05:21:52 PM PDT 24 |
50242211720 ps |
| T94 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3688507919 |
|
|
Mar 28 04:02:17 PM PDT 24 |
Mar 28 04:09:51 PM PDT 24 |
3637180578 ps |
| T95 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4054449542 |
|
|
Mar 28 03:48:33 PM PDT 24 |
Mar 28 04:09:32 PM PDT 24 |
8305293856 ps |
| T96 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.899231690 |
|
|
Mar 28 04:02:12 PM PDT 24 |
Mar 28 04:53:49 PM PDT 24 |
18653022929 ps |
| T33 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.1021056690 |
|
|
Mar 28 03:47:00 PM PDT 24 |
Mar 28 03:52:20 PM PDT 24 |
2936563686 ps |
| T97 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1371829967 |
|
|
Mar 28 03:48:42 PM PDT 24 |
Mar 28 03:57:24 PM PDT 24 |
3944634914 ps |
| T98 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3134232908 |
|
|
Mar 28 03:58:43 PM PDT 24 |
Mar 28 05:19:18 PM PDT 24 |
47933707861 ps |
| T464 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.321962714 |
|
|
Mar 28 04:09:42 PM PDT 24 |
Mar 28 04:21:21 PM PDT 24 |
4712709240 ps |
| T486 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2011184028 |
|
|
Mar 28 04:11:27 PM PDT 24 |
Mar 28 04:17:00 PM PDT 24 |
3282149800 ps |
| T415 |
/workspace/coverage/default/0.chip_sw_edn_kat.3905908516 |
|
|
Mar 28 03:47:40 PM PDT 24 |
Mar 28 03:58:25 PM PDT 24 |
3666191322 ps |
| T457 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040002287 |
|
|
Mar 28 04:14:22 PM PDT 24 |
Mar 28 04:19:32 PM PDT 24 |
3384115640 ps |
| T449 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2887974723 |
|
|
Mar 28 04:11:23 PM PDT 24 |
Mar 28 04:16:45 PM PDT 24 |
3646856368 ps |
| T36 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2347812329 |
|
|
Mar 28 04:09:24 PM PDT 24 |
Mar 28 04:35:40 PM PDT 24 |
8962444964 ps |
| T484 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3983238699 |
|
|
Mar 28 04:10:46 PM PDT 24 |
Mar 28 04:18:49 PM PDT 24 |
4818410432 ps |
| T564 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3601181078 |
|
|
Mar 28 04:08:14 PM PDT 24 |
Mar 28 04:28:48 PM PDT 24 |
7122662600 ps |
| T232 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.603451536 |
|
|
Mar 28 04:01:33 PM PDT 24 |
Mar 28 04:13:12 PM PDT 24 |
4422230410 ps |
| T37 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.668277701 |
|
|
Mar 28 04:12:31 PM PDT 24 |
Mar 28 04:59:44 PM PDT 24 |
22767326135 ps |
| T242 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3810909497 |
|
|
Mar 28 04:09:10 PM PDT 24 |
Mar 28 04:17:06 PM PDT 24 |
5143178490 ps |
| T461 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1949802731 |
|
|
Mar 28 04:14:56 PM PDT 24 |
Mar 28 04:21:23 PM PDT 24 |
3684711456 ps |
| T323 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1333641691 |
|
|
Mar 28 03:48:07 PM PDT 24 |
Mar 28 04:01:40 PM PDT 24 |
3816849450 ps |
| T565 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2370266572 |
|
|
Mar 28 04:04:58 PM PDT 24 |
Mar 28 04:08:28 PM PDT 24 |
2368715062 ps |
| T38 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2407945773 |
|
|
Mar 28 03:54:25 PM PDT 24 |
Mar 28 04:24:00 PM PDT 24 |
8123347784 ps |
| T326 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.1266405248 |
|
|
Mar 28 03:47:01 PM PDT 24 |
Mar 28 03:50:35 PM PDT 24 |
2398918584 ps |
| T566 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.72900674 |
|
|
Mar 28 04:05:20 PM PDT 24 |
Mar 28 04:10:56 PM PDT 24 |
3804390306 ps |
| T567 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1271447063 |
|
|
Mar 28 04:06:51 PM PDT 24 |
Mar 28 04:23:31 PM PDT 24 |
11340501084 ps |
| T478 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.778336264 |
|
|
Mar 28 04:07:58 PM PDT 24 |
Mar 28 04:17:21 PM PDT 24 |
5370722880 ps |
| T568 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2661701837 |
|
|
Mar 28 04:06:45 PM PDT 24 |
Mar 28 04:33:17 PM PDT 24 |
8441649556 ps |
| T458 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2777061285 |
|
|
Mar 28 04:09:48 PM PDT 24 |
Mar 28 04:16:04 PM PDT 24 |
3924600000 ps |
| T569 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2223983177 |
|
|
Mar 28 03:43:09 PM PDT 24 |
Mar 28 03:51:06 PM PDT 24 |
6502006384 ps |
| T237 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3362129740 |
|
|
Mar 28 04:08:03 PM PDT 24 |
Mar 28 04:49:23 PM PDT 24 |
13289474974 ps |
| T520 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3061312445 |
|
|
Mar 28 04:10:05 PM PDT 24 |
Mar 28 04:16:42 PM PDT 24 |
3391489070 ps |
| T570 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3818651824 |
|
|
Mar 28 04:03:59 PM PDT 24 |
Mar 28 04:07:49 PM PDT 24 |
2416971731 ps |
| T207 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3827598139 |
|
|
Mar 28 03:49:17 PM PDT 24 |
Mar 28 04:26:45 PM PDT 24 |
35709813440 ps |
| T187 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2585851281 |
|
|
Mar 28 03:48:55 PM PDT 24 |
Mar 28 03:55:25 PM PDT 24 |
3259243066 ps |
| T571 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.4239268171 |
|
|
Mar 28 03:55:34 PM PDT 24 |
Mar 28 04:02:12 PM PDT 24 |
2573083844 ps |