Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.64 94.97 72.06 86.48 92.87 91.82


Total modules in report: 108
modlist.html | modlist1.html
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
prim_mubi4_dec 0.00 0.00
padring 50.59 50.59
pinmux_wkup 64.07 68.42 69.23 54.55
rv_dm 64.39 64.39
prim_packer_fifo 68.93 100.00 90.00 85.71 0.00
rv_plic_gateway 69.17 100.00 20.00 87.50
pinmux 77.32 77.07 79.44 64.65 73.45 92.00
tlul_err_resp 79.42 92.31 68.18 77.78
ast 80.10 80.10
xbar_main 80.98 80.98
spi_device 81.13 81.13
top_earlgrey 82.88 90.32 58.30 100.00
usbdev 83.17 83.17
tlul_err 83.23 96.15 74.29 62.50 100.00
spi_host 84.36 84.36
otp_ctrl 84.55 84.55
hmac 84.81 84.81
entropy_src 85.08 85.08
prim_generic_clock_mux2 85.19 100.00 55.56 100.00
i2c 85.63 85.63
chip_earlgrey_asic 87.01 66.67 100.00 94.37
rv_core_ibex 87.55 94.12 89.29 86.15 100.00 68.18
  prim_reg_cdc_arb 88.49 94.00 86.05 73.91 100.00
rv_core_ibex_cfg_reg_top 88.80 98.88 62.06 94.29 100.00
pwm 88.89 88.89
  tlul_adapter_host 89.09 91.11 75.79 89.44 100.00
keymgr 89.29 89.29
rv_timer 89.73 89.73
xbar_peri 89.73 89.73
aon_timer 89.81 89.81
pattgen 90.00 90.00
adc_ctrl 90.12 90.12
uart 90.20 90.20
sysrst_ctrl 91.02 91.02
pinmux_reg_top 91.18 98.28 66.46 100.00 100.00
lc_ctrl 91.29 91.29
prim_max_tree 91.52 88.49 77.58 100.00 100.00
  tlul_rsp_intg_gen 91.67 83.33 100.00
prim_sync_reqack 91.67 100.00 66.67 100.00 100.00
rom_ctrl 92.13 92.13
rv_plic_reg_top 92.38 100.00 69.99 99.51 100.00
rstmgr 92.42 92.42
tlul_socket_1n 92.60 89.29 86.36 94.74 100.00
pwrmgr 93.04 93.04
sensor_ctrl_reg_top 93.30 100.00 73.18 100.00 100.00
tlul_rsp_intg_chk 93.33 100.00 80.00 100.00
tlul_adapter_reg 94.24 97.37 79.59 100.00 100.00
ibex_top 94.28 94.28
sram_ctrl 94.30 94.30
gpio 94.44 94.44
flash_ctrl 94.49 94.49
sensor_ctrl 94.50 92.86 88.00 91.67 100.00 100.00
prim_arbiter_fixed 94.88 100.00 86.67 100.00 92.86
clkmgr 94.93 94.93
edn 95.94 95.94
rv_plic 96.10 99.82 100.00 90.68 100.00 90.00
prim_edn_req 96.15 100.00 84.62 100.00 100.00
prim_generic_usb_diff_rx 96.30 100.00 88.89 100.00
aes 96.62 96.62
usbdev_aon_wake 96.98 100.00 93.18 94.74 100.00
alert_handler 97.21 97.21
  prim_reg_cdc 97.25 100.00 89.01 100.00 100.00
csrng 97.36 97.36
otbn 97.39 97.39
kmac 98.28 98.28
  prim_subreg_arb 99.60 100.00 98.81 100.00
pinmux_strap_sampling 99.83 99.34 100.00 100.00 100.00
  prim_lc_sync 100.00 100.00 100.00
prim_lc_sender 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
tlul_cmd_intg_gen 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
prim_edge_detector 100.00 100.00 100.00 100.00
clk_ctrl_and_main_pd_sva_if 100.00 100.00
  prim_subreg 100.00 100.00 100.00 100.00
prim_filter 100.00 100.00 100.00 100.00
pinmux_jtag_breakout 100.00 100.00 100.00
prim_lc_or_hardened 100.00 100.00 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00 100.00 100.00
prim_pulse_sync 100.00 100.00 100.00 100.00 100.00
prim_fifo_sync 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
prim_esc_receiver 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
  prim_generic_pad_wrapper 100.00 100.00 100.00 100.00 100.00
prim_sync_reqack_data 100.00 100.00 100.00
rv_core_addr_trans 100.00 100.00 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
rv_plic_target 100.00 100.00 100.00 100.00
prim_mubi4_sync 100.00 100.00
prim_generic_clock_buf 100.00 100.00
pinmux_jtag_buf
prim_usb_diff_rx
prim_clock_buf
tlul_data_integ_enc
prim_reg_we_check