Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409546678	44985618	0	0
DepthKnown_A	409546678	409443158	0	0
RvalidKnown_A	409546678	409443158	0	0
WreadyKnown_A	409546678	409443158	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	44985618	0	0
T1	192840	38307	0	0
T2	569599	66797	0	0
T3	91140	9748	0	0
T4	412300	159519	0	0
T30	221923	22999	0	0
T39	683935	85464	0	0
T80	169046	20598	0	0
T81	572297	80513	0	0
T82	73912	8342	0	0
T83	135218	17949	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T30	1	1	0	0
T39	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409546678	33888114	0	0
DepthKnown_A	409546678	409443158	0	0
RvalidKnown_A	409546678	409443158	0	0
WreadyKnown_A	409546678	409443158	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	33888114	0	0
T1	192840	28220	0	0
T2	569599	49180	0	0
T3	91140	7874	0	0
T4	412300	80004	0	0
T30	221923	15447	0	0
T39	683935	67781	0	0
T80	169046	18651	0	0
T81	572297	77313	0	0
T82	73912	6048	0	0
T83	135218	12828	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T30	1	1	0	0
T39	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409546678	29774475	0	0
DepthKnown_A	409546678	409443158	0	0
RvalidKnown_A	409546678	409443158	0	0
WreadyKnown_A	409546678	409443158	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	29774475	0	0
T1	192840	21854	0	0
T2	569599	29220	0	0
T3	91140	6137	0	0
T4	412300	12927	0	0
T30	221923	11513	0	0
T39	683935	132903	0	0
T80	169046	13895	0	0
T81	572297	5588	0	0
T82	73912	4710	0	0
T83	135218	7295	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T30	1	1	0	0
T39	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409546678	24273210	0	0
DepthKnown_A	409546678	409443158	0	0
RvalidKnown_A	409546678	409443158	0	0
WreadyKnown_A	409546678	409443158	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	24273210	0	0
T1	192840	21320	0	0
T2	569599	28373	0	0
T3	91140	6012	0	0
T4	412300	11962	0	0
T30	221923	11070	0	0
T39	683935	59438	0	0
T80	169046	13780	0	0
T81	572297	5412	0	0
T82	73912	4585	0	0
T83	135218	7018	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T30	1	1	0	0
T39	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409546678	61811	0	0
DepthKnown_A	409546678	409443158	0	0
RvalidKnown_A	409546678	409443158	0	0
WreadyKnown_A	409546678	409443158	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	61811	0	0
T1	192840	15	0	0
T2	569599	112	0	0
T3	91140	13	0	0
T4	412300	73	0	0
T30	221923	64	0	0
T39	683935	26	0	0
T80	169046	13	0	0
T81	572297	23	0	0
T82	73912	13	0	0
T83	135218	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T30	1	1	0	0
T39	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409546678	61811	0	0
DepthKnown_A	409546678	409443158	0	0
RvalidKnown_A	409546678	409443158	0	0
WreadyKnown_A	409546678	409443158	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	61811	0	0
T1	192840	15	0	0
T2	569599	112	0	0
T3	91140	13	0	0
T4	412300	73	0	0
T30	221923	64	0	0
T39	683935	26	0	0
T80	169046	13	0	0
T81	572297	23	0	0
T82	73912	13	0	0
T83	135218	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T30	1	1	0	0
T39	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409546678	49565	0	0
DepthKnown_A	409546678	409443158	0	0
RvalidKnown_A	409546678	409443158	0	0
WreadyKnown_A	409546678	409443158	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	49565	0	0
T1	192840	12	0	0
T2	569599	97	0	0
T3	91140	12	0	0
T4	412300	69	0	0
T30	221923	59	0	0
T39	683935	5	0	0
T80	169046	12	0	0
T81	572297	20	0	0
T82	73912	12	0	0
T83	135218	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T30	1	1	0	0
T39	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409546678	49565	0	0
DepthKnown_A	409546678	409443158	0	0
RvalidKnown_A	409546678	409443158	0	0
WreadyKnown_A	409546678	409443158	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	49565	0	0
T1	192840	12	0	0
T2	569599	97	0	0
T3	91140	12	0	0
T4	412300	69	0	0
T30	221923	59	0	0
T39	683935	5	0	0
T80	169046	12	0	0
T81	572297	20	0	0
T82	73912	12	0	0
T83	135218	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T30	1	1	0	0
T39	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409546678	12246	0	0
DepthKnown_A	409546678	409443158	0	0
RvalidKnown_A	409546678	409443158	0	0
WreadyKnown_A	409546678	409443158	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	12246	0	0
T1	192840	3	0	0
T2	569599	15	0	0
T3	91140	1	0	0
T4	412300	4	0	0
T30	221923	5	0	0
T39	683935	21	0	0
T80	169046	1	0	0
T81	572297	3	0	0
T82	73912	1	0	0
T83	135218	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T30	1	1	0	0
T39	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409546678	12246	0	0
DepthKnown_A	409546678	409443158	0	0
RvalidKnown_A	409546678	409443158	0	0
WreadyKnown_A	409546678	409443158	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	12246	0	0
T1	192840	3	0	0
T2	569599	15	0	0
T3	91140	1	0	0
T4	412300	4	0	0
T30	221923	5	0	0
T39	683935	21	0	0
T80	169046	1	0	0
T81	572297	3	0	0
T82	73912	1	0	0
T83	135218	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409546678	409443158	0	0
T1	192840	192789	0	0
T2	569599	569315	0	0
T3	91140	91078	0	0
T4	412300	412272	0	0
T30	221923	221763	0	0
T39	683935	683880	0	0
T80	169046	168991	0	0
T81	572297	572235	0	0
T82	73912	73861	0	0
T83	135218	135156	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T30	1	1	0	0
T39	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0