Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.38 100.00 69.99 99.51 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 92.38 100.00 69.99 99.51 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15281528100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
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CONT_ASSIGN11911100.00
CONT_ASSIGN1622711100.00
CONT_ASSIGN1624111100.00
CONT_ASSIGN1627511100.00
CONT_ASSIGN1628911100.00
ALWAYS16295199199100.00
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ALWAYS1650011100.00
CONT_ASSIGN1670211100.00
CONT_ASSIGN1670411100.00
CONT_ASSIGN1670511100.00
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CONT_ASSIGN1731711100.00
CONT_ASSIGN1731911100.00
CONT_ASSIGN1732111100.00
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CONT_ASSIGN1732511100.00
CONT_ASSIGN1732711100.00
CONT_ASSIGN1732911100.00
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ALWAYS17634199199100.00
ALWAYS17837552552100.00
CONT_ASSIGN1899400
CONT_ASSIGN1900211100.00
CONT_ASSIGN1900311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16227 1 1
16241 1 1
16275 1 1
16289 1 1
16295 1 1
16296 1 1
16297 1 1
16298 1 1
16299 1 1
16300 1 1
16301 1 1
16302 1 1
16303 1 1
16304 1 1
16305 1 1
16306 1 1
16307 1 1
16308 1 1
16309 1 1
16310 1 1
16311 1 1
16312 1 1
16313 1 1
16314 1 1
16315 1 1
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16317 1 1
16318 1 1
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16326 1 1
16327 1 1
16328 1 1
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16330 1 1
16331 1 1
16332 1 1
16333 1 1
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16335 1 1
16336 1 1
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18964 1 1
18968 1 1
18972 1 1
18976 1 1
18980 1 1
18994 unreachable
19002 1 1
19003 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions1983138869.99
Logical1983138869.99
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1647998.43
16480-1650044.79
16500-1688570.57
16888-1762875.00

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 204 203 99.51
TERNARY 16496 2 2 100.00
IF 68 3 3 100.00
CASE 17838 199 198 99.50

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16496 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T378,T368,T379
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 17838 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T30
addr_hit[1] Covered T120,T162,T153
addr_hit[2] Covered T120,T162,T153
addr_hit[3] Covered T120,T102,T162
addr_hit[4] Covered T120,T102,T162
addr_hit[5] Covered T120,T162,T153
addr_hit[6] Covered T120,T162,T153
addr_hit[7] Covered T120,T162,T153
addr_hit[8] Covered T120,T162,T153
addr_hit[9] Covered T162,T153,T235
addr_hit[10] Covered T162,T153,T235
addr_hit[11] Covered T162,T153,T235
addr_hit[12] Covered T162,T153,T235
addr_hit[13] Covered T162,T153,T235
addr_hit[14] Covered T162,T153,T235
addr_hit[15] Covered T162,T153,T235
addr_hit[16] Covered T162,T153,T235
addr_hit[17] Covered T139,T109,T162
addr_hit[18] Covered T139,T109,T162
addr_hit[19] Covered T139,T109,T162
addr_hit[20] Covered T139,T109,T162
addr_hit[21] Covered T139,T109,T162
addr_hit[22] Covered T139,T109,T162
addr_hit[23] Covered T139,T109,T162
addr_hit[24] Covered T139,T109,T162
addr_hit[25] Covered T14,T15,T162
addr_hit[26] Covered T14,T15,T162
addr_hit[27] Covered T14,T15,T162
addr_hit[28] Covered T14,T15,T162
addr_hit[29] Covered T14,T15,T162
addr_hit[30] Covered T14,T15,T162
addr_hit[31] Covered T14,T15,T162
addr_hit[32] Covered T14,T15,T162
addr_hit[33] Covered T162,T153,T24
addr_hit[34] Covered T162,T153,T24
addr_hit[35] Covered T162,T153,T24
addr_hit[36] Covered T162,T153,T24
addr_hit[37] Covered T162,T153,T24
addr_hit[38] Covered T162,T153,T24
addr_hit[39] Covered T162,T153,T24
addr_hit[40] Covered T162,T153,T24
addr_hit[41] Covered T162,T153,T24
addr_hit[42] Covered T162,T153,T24
addr_hit[43] Covered T162,T153,T24
addr_hit[44] Covered T162,T153,T24
addr_hit[45] Covered T162,T153,T24
addr_hit[46] Covered T162,T153,T24
addr_hit[47] Covered T162,T153,T24
addr_hit[48] Covered T162,T153,T24
addr_hit[49] Covered T162,T153,T24
addr_hit[50] Covered T162,T153,T24
addr_hit[51] Covered T162,T153,T24
addr_hit[52] Covered T162,T153,T24
addr_hit[53] Covered T162,T153,T24
addr_hit[54] Covered T162,T153,T24
addr_hit[55] Covered T162,T153,T24
addr_hit[56] Covered T162,T153,T24
addr_hit[57] Covered T162,T153,T24
addr_hit[58] Covered T162,T153,T24
addr_hit[59] Covered T162,T153,T24
addr_hit[60] Covered T162,T153,T24
addr_hit[61] Covered T162,T153,T24
addr_hit[62] Covered T162,T153,T24
addr_hit[63] Covered T162,T153,T24
addr_hit[64] Covered T162,T153,T24
addr_hit[65] Covered T10,T162,T153
addr_hit[66] Covered T162,T153,T33
addr_hit[67] Covered T162,T153,T33
addr_hit[68] Covered T10,T162,T153
addr_hit[69] Covered T10,T162,T153
addr_hit[70] Covered T162,T153,T33
addr_hit[71] Covered T162,T153,T216
addr_hit[72] Covered T162,T153,T216
addr_hit[73] Covered T223,T162,T153
addr_hit[74] Covered T223,T162,T153
addr_hit[75] Covered T162,T153,T216
addr_hit[76] Covered T223,T162,T153
addr_hit[77] Covered T223,T162,T153
addr_hit[78] Covered T223,T162,T153
addr_hit[79] Covered T223,T162,T153
addr_hit[80] Covered T223,T162,T153
addr_hit[81] Covered T162,T153,T216
addr_hit[82] Covered T223,T162,T153
addr_hit[83] Covered T162,T153,T227
addr_hit[84] Covered T162,T153,T216
addr_hit[85] Covered T162,T153,T227
addr_hit[86] Covered T162,T153,T227
addr_hit[87] Covered T162,T153,T227
addr_hit[88] Covered T177,T162,T153
addr_hit[89] Covered T177,T162,T153
addr_hit[90] Covered T162,T153,T216
addr_hit[91] Covered T177,T162,T153
addr_hit[92] Covered T177,T162,T153
addr_hit[93] Covered T177,T162,T153
addr_hit[94] Covered T177,T162,T153
addr_hit[95] Covered T177,T162,T153
addr_hit[96] Covered T162,T153,T216
addr_hit[97] Covered T177,T162,T153
addr_hit[98] Covered T162,T153,T216
addr_hit[99] Covered T162,T153,T216
addr_hit[100] Covered T162,T153,T216
addr_hit[101] Covered T162,T153,T216
addr_hit[102] Covered T162,T153,T216
addr_hit[103] Covered T162,T153,T224
addr_hit[104] Covered T162,T153,T224
addr_hit[105] Covered T162,T153,T216
addr_hit[106] Covered T162,T153,T224
addr_hit[107] Covered T162,T153,T224
addr_hit[108] Covered T162,T153,T224
addr_hit[109] Covered T162,T153,T224
addr_hit[110] Covered T162,T153,T224
addr_hit[111] Covered T162,T153,T216
addr_hit[112] Covered T162,T153,T224
addr_hit[113] Covered T162,T153,T216
addr_hit[114] Covered T162,T153,T216
addr_hit[115] Covered T162,T153,T216
addr_hit[116] Covered T162,T153,T216
addr_hit[117] Covered T162,T153,T216
addr_hit[118] Covered T162,T153,T326
addr_hit[119] Covered T162,T153,T326
addr_hit[120] Covered T162,T153,T216
addr_hit[121] Covered T162,T153,T216
addr_hit[122] Covered T162,T153,T216
addr_hit[123] Covered T2,T73,T265
addr_hit[124] Covered T2,T73,T265
addr_hit[125] Covered T2,T73,T265
addr_hit[126] Covered T2,T73,T265
addr_hit[127] Covered T10,T162,T153
addr_hit[128] Covered T10,T162,T153
addr_hit[129] Covered T162,T153,T216
addr_hit[130] Covered T162,T153,T216
addr_hit[131] Covered T162,T153,T216
addr_hit[132] Covered T162,T153,T216
addr_hit[133] Covered T162,T153,T216
addr_hit[134] Covered T162,T153,T216
addr_hit[135] Covered T162,T153,T216
addr_hit[136] Covered T162,T153,T216
addr_hit[137] Covered T162,T153,T216
addr_hit[138] Covered T162,T153,T216
addr_hit[139] Covered T162,T153,T216
addr_hit[140] Covered T162,T153,T216
addr_hit[141] Covered T162,T153,T216
addr_hit[142] Covered T162,T153,T216
addr_hit[143] Covered T162,T153,T216
addr_hit[144] Covered T162,T153,T216
addr_hit[145] Covered T162,T153,T216
addr_hit[146] Covered T162,T153,T216
addr_hit[147] Covered T162,T153,T216
addr_hit[148] Covered T162,T153,T216
addr_hit[149] Covered T30,T83,T195
addr_hit[150] Covered T162,T153,T216
addr_hit[151] Covered T162,T153,T122
addr_hit[152] Covered T2,T73,T265
addr_hit[153] Covered T2,T73,T265
addr_hit[154] Covered T162,T153,T216
addr_hit[155] Covered T162,T153,T216
addr_hit[156] Covered T1,T351,T162
addr_hit[157] Covered T1,T351,T162
addr_hit[158] Covered T1,T351,T162
addr_hit[159] Covered T1,T351,T162
addr_hit[160] Covered T1,T351,T162
addr_hit[161] Covered T162,T153,T216
addr_hit[162] Covered T162,T153,T165
addr_hit[163] Covered T162,T153,T165
addr_hit[164] Covered T162,T153,T216
addr_hit[165] Covered T162,T153,T216
addr_hit[166] Covered T162,T153,T216
addr_hit[167] Covered T162,T153,T216
addr_hit[168] Covered T129,T162,T153
addr_hit[169] Covered T162,T153,T216
addr_hit[170] Covered T162,T153,T216
addr_hit[171] Covered T124,T162,T153
addr_hit[172] Covered T162,T153,T216
addr_hit[173] Covered T162,T153,T216
addr_hit[174] Covered T162,T153,T216
addr_hit[175] Covered T162,T153,T216
addr_hit[176] Covered T162,T153,T216
addr_hit[177] Covered T162,T153,T216
addr_hit[178] Covered T124,T162,T153
addr_hit[179] Covered T162,T153,T216
addr_hit[180] Covered T124,T162,T153
addr_hit[181] Covered T162,T153,T216
addr_hit[182] Covered T59
addr_hit[183] Covered T59
addr_hit[184] Covered T59
addr_hit[185] Covered T59
addr_hit[186] Covered T380,T381,T59
addr_hit[187] Covered T59
addr_hit[188] Covered T139,T109,T120
addr_hit[189] Covered T14,T15,T162
addr_hit[190] Covered T177,T10,T223
addr_hit[191] Covered T2,T177,T73
addr_hit[192] Covered T1,T2,T30
addr_hit[193] Covered T1,T124,T129
addr_hit[194] Covered T1,T2,T30
addr_hit[195] Covered T1,T2,T30
addr_hit[196] Covered T255,T256,T257
addr_hit[197] Covered T67,T68,T59
default Not Covered


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 409546678 33421 0 0
reAfterRv 409546678 33421 0 0
rePulse 409546678 13568 0 0
wePulse 409546678 19853 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 409546678 33421 0 0
T1 192840 110 0 0
T2 569599 102 0 0
T3 91140 0 0 0
T4 412300 0 0 0
T10 0 15 0 0
T30 221923 6 0 0
T39 683935 0 0 0
T73 0 40 0 0
T80 169046 0 0 0
T81 572297 0 0 0
T82 73912 0 0 0
T83 135218 8 0 0
T109 0 41 0 0
T139 0 41 0 0
T177 0 48 0 0
T195 0 8 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 409546678 33421 0 0
T1 192840 110 0 0
T2 569599 102 0 0
T3 91140 0 0 0
T4 412300 0 0 0
T10 0 15 0 0
T30 221923 6 0 0
T39 683935 0 0 0
T73 0 40 0 0
T80 169046 0 0 0
T81 572297 0 0 0
T82 73912 0 0 0
T83 135218 8 0 0
T109 0 41 0 0
T139 0 41 0 0
T177 0 48 0 0
T195 0 8 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 409546678 13568 0 0
T1 192840 52 0 0
T2 569599 31 0 0
T3 91140 0 0 0
T4 412300 0 0 0
T10 0 5 0 0
T30 221923 2 0 0
T39 683935 0 0 0
T73 0 12 0 0
T80 169046 0 0 0
T81 572297 0 0 0
T82 73912 0 0 0
T83 135218 3 0 0
T109 0 16 0 0
T139 0 16 0 0
T177 0 20 0 0
T195 0 3 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 409546678 19853 0 0
T1 192840 58 0 0
T2 569599 71 0 0
T3 91140 0 0 0
T4 412300 0 0 0
T10 0 10 0 0
T30 221923 4 0 0
T39 683935 0 0 0
T73 0 28 0 0
T80 169046 0 0 0
T81 572297 0 0 0
T82 73912 0 0 0
T83 135218 5 0 0
T109 0 25 0 0
T139 0 25 0 0
T177 0 28 0 0
T195 0 5 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%