| T410 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.4000939768 |
|
|
Mar 28 03:45:18 PM PDT 24 |
Mar 28 03:48:45 PM PDT 24 |
2571015144 ps |
| T572 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.207116672 |
|
|
Mar 28 04:02:58 PM PDT 24 |
Mar 28 04:26:47 PM PDT 24 |
7138015762 ps |
| T219 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.405809153 |
|
|
Mar 28 04:02:53 PM PDT 24 |
Mar 28 04:12:39 PM PDT 24 |
3312849250 ps |
| T573 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.111897770 |
|
|
Mar 28 03:49:14 PM PDT 24 |
Mar 28 03:53:58 PM PDT 24 |
2773643514 ps |
| T118 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1833610663 |
|
|
Mar 28 04:02:34 PM PDT 24 |
Mar 28 04:11:27 PM PDT 24 |
4163645093 ps |
| T240 |
/workspace/coverage/default/1.chip_tap_straps_prod.1430653601 |
|
|
Mar 28 03:52:45 PM PDT 24 |
Mar 28 03:55:21 PM PDT 24 |
3028134341 ps |
| T574 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1405251939 |
|
|
Mar 28 03:46:47 PM PDT 24 |
Mar 28 03:56:40 PM PDT 24 |
4393213523 ps |
| T575 |
/workspace/coverage/default/0.chip_sw_example_rom.1635671704 |
|
|
Mar 28 03:42:56 PM PDT 24 |
Mar 28 03:45:08 PM PDT 24 |
2525757464 ps |
| T390 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3134433796 |
|
|
Mar 28 04:03:33 PM PDT 24 |
Mar 28 04:06:04 PM PDT 24 |
2531505536 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.635111720 |
|
|
Mar 28 03:47:49 PM PDT 24 |
Mar 28 04:37:26 PM PDT 24 |
11649738772 ps |
| T576 |
/workspace/coverage/default/2.chip_sw_aes_idle.924233268 |
|
|
Mar 28 04:02:03 PM PDT 24 |
Mar 28 04:06:21 PM PDT 24 |
3000484720 ps |
| T577 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.2241395455 |
|
|
Mar 28 04:09:38 PM PDT 24 |
Mar 28 04:21:06 PM PDT 24 |
5005454776 ps |
| T578 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.893208542 |
|
|
Mar 28 03:54:27 PM PDT 24 |
Mar 28 03:57:52 PM PDT 24 |
3042500656 ps |
| T166 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1042226142 |
|
|
Mar 28 03:52:46 PM PDT 24 |
Mar 28 03:57:15 PM PDT 24 |
3091140007 ps |
| T579 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1471565770 |
|
|
Mar 28 03:59:32 PM PDT 24 |
Mar 28 04:29:41 PM PDT 24 |
21666972048 ps |
| T318 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.86958152 |
|
|
Mar 28 03:45:35 PM PDT 24 |
Mar 28 05:14:43 PM PDT 24 |
50432724974 ps |
| T488 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2006480322 |
|
|
Mar 28 04:11:57 PM PDT 24 |
Mar 28 04:20:32 PM PDT 24 |
4537808604 ps |
| T34 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.2742683377 |
|
|
Mar 28 03:45:37 PM PDT 24 |
Mar 28 03:52:00 PM PDT 24 |
3391961615 ps |
| T320 |
/workspace/coverage/default/0.chip_sw_flash_init.2111478586 |
|
|
Mar 28 03:46:16 PM PDT 24 |
Mar 28 04:26:03 PM PDT 24 |
19135895741 ps |
| T496 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.553103547 |
|
|
Mar 28 04:15:25 PM PDT 24 |
Mar 28 04:25:23 PM PDT 24 |
4719913670 ps |
| T540 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.3771455526 |
|
|
Mar 28 04:11:04 PM PDT 24 |
Mar 28 04:21:25 PM PDT 24 |
5321922660 ps |
| T122 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2117123161 |
|
|
Mar 28 03:47:04 PM PDT 24 |
Mar 28 03:57:31 PM PDT 24 |
19353713652 ps |
| T477 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.193703253 |
|
|
Mar 28 04:02:33 PM PDT 24 |
Mar 28 07:42:14 PM PDT 24 |
255399938628 ps |
| T580 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1093529375 |
|
|
Mar 28 04:12:25 PM PDT 24 |
Mar 28 04:18:01 PM PDT 24 |
3330010692 ps |
| T142 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1677185979 |
|
|
Mar 28 04:02:34 PM PDT 24 |
Mar 28 04:13:31 PM PDT 24 |
4864804240 ps |
| T179 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2024755061 |
|
|
Mar 28 03:46:37 PM PDT 24 |
Mar 28 03:58:14 PM PDT 24 |
4086832840 ps |
| T216 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.3532356974 |
|
|
Mar 28 03:51:18 PM PDT 24 |
Mar 28 04:14:24 PM PDT 24 |
6280179252 ps |
| T581 |
/workspace/coverage/default/3.chip_tap_straps_prod.4036414897 |
|
|
Mar 28 04:06:22 PM PDT 24 |
Mar 28 04:09:07 PM PDT 24 |
2835947623 ps |
| T76 |
/workspace/coverage/default/4.chip_tap_straps_dev.576160641 |
|
|
Mar 28 04:05:59 PM PDT 24 |
Mar 28 04:22:17 PM PDT 24 |
11506007362 ps |
| T319 |
/workspace/coverage/default/1.chip_sw_flash_init.3666030636 |
|
|
Mar 28 03:50:54 PM PDT 24 |
Mar 28 04:20:18 PM PDT 24 |
21118171078 ps |
| T61 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.4024449050 |
|
|
Mar 28 04:05:37 PM PDT 24 |
Mar 28 04:10:59 PM PDT 24 |
3843023705 ps |
| T582 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3657766762 |
|
|
Mar 28 03:50:05 PM PDT 24 |
Mar 28 03:56:44 PM PDT 24 |
4028071440 ps |
| T583 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3717282719 |
|
|
Mar 28 03:50:48 PM PDT 24 |
Mar 28 04:14:24 PM PDT 24 |
5774362360 ps |
| T465 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3612229064 |
|
|
Mar 28 04:09:19 PM PDT 24 |
Mar 28 04:21:45 PM PDT 24 |
6386315200 ps |
| T220 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.2438247807 |
|
|
Mar 28 03:51:27 PM PDT 24 |
Mar 28 04:00:31 PM PDT 24 |
2886984048 ps |
| T25 |
/workspace/coverage/default/2.chip_sw_gpio.3891286190 |
|
|
Mar 28 03:58:35 PM PDT 24 |
Mar 28 04:08:29 PM PDT 24 |
3625003802 ps |
| T584 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.292063898 |
|
|
Mar 28 04:05:06 PM PDT 24 |
Mar 28 04:09:15 PM PDT 24 |
2897881390 ps |
| T367 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3790398266 |
|
|
Mar 28 04:07:18 PM PDT 24 |
Mar 28 04:16:00 PM PDT 24 |
5521690070 ps |
| T531 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.847720577 |
|
|
Mar 28 03:44:35 PM PDT 24 |
Mar 28 03:57:21 PM PDT 24 |
5726512852 ps |
| T311 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3243982008 |
|
|
Mar 28 04:02:55 PM PDT 24 |
Mar 28 04:12:55 PM PDT 24 |
4680189316 ps |
| T251 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3586588687 |
|
|
Mar 28 04:07:56 PM PDT 24 |
Mar 28 04:17:49 PM PDT 24 |
5910700152 ps |
| T56 |
/workspace/coverage/default/1.chip_jtag_mem_access.348234035 |
|
|
Mar 28 03:42:54 PM PDT 24 |
Mar 28 04:07:32 PM PDT 24 |
14034488132 ps |
| T492 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878832921 |
|
|
Mar 28 04:10:34 PM PDT 24 |
Mar 28 04:16:19 PM PDT 24 |
3221000622 ps |
| T585 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.4119454131 |
|
|
Mar 28 03:50:16 PM PDT 24 |
Mar 28 03:58:47 PM PDT 24 |
4411628300 ps |
| T57 |
/workspace/coverage/default/0.chip_jtag_mem_access.1247107192 |
|
|
Mar 28 03:36:33 PM PDT 24 |
Mar 28 04:00:57 PM PDT 24 |
12838825228 ps |
| T321 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1711906949 |
|
|
Mar 28 03:46:46 PM PDT 24 |
Mar 28 05:16:54 PM PDT 24 |
47653816671 ps |
| T586 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3852680315 |
|
|
Mar 28 03:47:08 PM PDT 24 |
Mar 28 03:58:23 PM PDT 24 |
3729900920 ps |
| T587 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.4273230506 |
|
|
Mar 28 03:54:24 PM PDT 24 |
Mar 28 03:57:04 PM PDT 24 |
2964145236 ps |
| T119 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.339109754 |
|
|
Mar 28 03:48:25 PM PDT 24 |
Mar 28 03:56:02 PM PDT 24 |
4644513703 ps |
| T268 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1018465493 |
|
|
Mar 28 03:53:00 PM PDT 24 |
Mar 28 04:34:07 PM PDT 24 |
8560763208 ps |
| T588 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1736313352 |
|
|
Mar 28 04:07:01 PM PDT 24 |
Mar 28 04:14:28 PM PDT 24 |
4151863532 ps |
| T85 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.405551667 |
|
|
Mar 28 04:09:21 PM PDT 24 |
Mar 28 04:18:54 PM PDT 24 |
4792318796 ps |
| T79 |
/workspace/coverage/default/2.chip_jtag_mem_access.68203494 |
|
|
Mar 28 03:55:55 PM PDT 24 |
Mar 28 04:21:04 PM PDT 24 |
13385294523 ps |
| T589 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.830650813 |
|
|
Mar 28 04:03:53 PM PDT 24 |
Mar 28 04:12:31 PM PDT 24 |
3354021916 ps |
| T590 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3437133989 |
|
|
Mar 28 03:46:21 PM PDT 24 |
Mar 28 04:19:36 PM PDT 24 |
8420707640 ps |
| T459 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3328298322 |
|
|
Mar 28 04:13:26 PM PDT 24 |
Mar 28 04:22:57 PM PDT 24 |
4636846536 ps |
| T126 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.4149624955 |
|
|
Mar 28 03:52:26 PM PDT 24 |
Mar 28 04:26:47 PM PDT 24 |
16038579764 ps |
| T591 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.3905327952 |
|
|
Mar 28 04:01:18 PM PDT 24 |
Mar 28 04:05:14 PM PDT 24 |
2936122134 ps |
| T132 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.806831403 |
|
|
Mar 28 03:48:09 PM PDT 24 |
Mar 28 03:57:00 PM PDT 24 |
6008846840 ps |
| T592 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2687114123 |
|
|
Mar 28 03:50:22 PM PDT 24 |
Mar 28 04:01:34 PM PDT 24 |
5680011470 ps |
| T593 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1864295015 |
|
|
Mar 28 03:51:01 PM PDT 24 |
Mar 28 03:57:36 PM PDT 24 |
3661170722 ps |
| T594 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.68990759 |
|
|
Mar 28 03:48:18 PM PDT 24 |
Mar 28 03:54:31 PM PDT 24 |
3312127728 ps |
| T595 |
/workspace/coverage/default/0.chip_sival_flash_info_access.1134972222 |
|
|
Mar 28 03:47:31 PM PDT 24 |
Mar 28 03:52:35 PM PDT 24 |
2973074496 ps |
| T511 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.647632281 |
|
|
Mar 28 04:16:11 PM PDT 24 |
Mar 28 04:22:20 PM PDT 24 |
4367783832 ps |
| T180 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.883327394 |
|
|
Mar 28 03:43:38 PM PDT 24 |
Mar 28 03:50:52 PM PDT 24 |
4788628511 ps |
| T450 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.15415145 |
|
|
Mar 28 04:10:19 PM PDT 24 |
Mar 28 04:15:53 PM PDT 24 |
4108850892 ps |
| T391 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1900670833 |
|
|
Mar 28 03:50:59 PM PDT 24 |
Mar 28 03:53:50 PM PDT 24 |
2627797168 ps |
| T198 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.293621450 |
|
|
Mar 28 03:58:18 PM PDT 24 |
Mar 28 04:00:21 PM PDT 24 |
2541768965 ps |
| T136 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2343497404 |
|
|
Mar 28 04:06:47 PM PDT 24 |
Mar 28 04:18:35 PM PDT 24 |
6759322424 ps |
| T322 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2534846168 |
|
|
Mar 28 03:44:57 PM PDT 24 |
Mar 28 05:10:22 PM PDT 24 |
50572085431 ps |
| T596 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2402670103 |
|
|
Mar 28 03:56:15 PM PDT 24 |
Mar 28 04:22:19 PM PDT 24 |
8415576336 ps |
| T597 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3196792125 |
|
|
Mar 28 04:03:19 PM PDT 24 |
Mar 28 04:22:16 PM PDT 24 |
5962890856 ps |
| T181 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2574180500 |
|
|
Mar 28 03:46:53 PM PDT 24 |
Mar 28 03:57:29 PM PDT 24 |
7951907099 ps |
| T269 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2293154769 |
|
|
Mar 28 03:52:53 PM PDT 24 |
Mar 28 04:30:44 PM PDT 24 |
8180346923 ps |
| T298 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2586132737 |
|
|
Mar 28 04:07:00 PM PDT 24 |
Mar 28 04:15:52 PM PDT 24 |
4348341356 ps |
| T151 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.4269334325 |
|
|
Mar 28 03:47:34 PM PDT 24 |
Mar 28 04:02:48 PM PDT 24 |
6396109240 ps |
| T299 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.1789910484 |
|
|
Mar 28 03:57:13 PM PDT 24 |
Mar 28 04:02:27 PM PDT 24 |
2786894444 ps |
| T300 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2075386586 |
|
|
Mar 28 04:13:06 PM PDT 24 |
Mar 28 04:19:27 PM PDT 24 |
4292052212 ps |
| T301 |
/workspace/coverage/default/2.chip_sw_flash_init.3690902043 |
|
|
Mar 28 03:59:29 PM PDT 24 |
Mar 28 04:33:52 PM PDT 24 |
19667799530 ps |
| T127 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.399398716 |
|
|
Mar 28 04:05:16 PM PDT 24 |
Mar 28 04:36:44 PM PDT 24 |
12898784884 ps |
| T302 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2598626736 |
|
|
Mar 28 03:50:33 PM PDT 24 |
Mar 28 03:54:06 PM PDT 24 |
2331443580 ps |
| T303 |
/workspace/coverage/default/0.chip_tap_straps_prod.3849562838 |
|
|
Mar 28 03:46:56 PM PDT 24 |
Mar 28 04:04:01 PM PDT 24 |
9433841100 ps |
| T389 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2481003637 |
|
|
Mar 28 03:50:25 PM PDT 24 |
Mar 28 03:58:29 PM PDT 24 |
5730950710 ps |
| T45 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.198957219 |
|
|
Mar 28 03:51:56 PM PDT 24 |
Mar 28 04:22:30 PM PDT 24 |
21202636026 ps |
| T598 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3333864516 |
|
|
Mar 28 03:52:42 PM PDT 24 |
Mar 28 04:11:48 PM PDT 24 |
8258720360 ps |
| T471 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1632684373 |
|
|
Mar 28 04:12:25 PM PDT 24 |
Mar 28 04:22:59 PM PDT 24 |
5905670316 ps |
| T436 |
/workspace/coverage/default/0.chip_tap_straps_dev.408485744 |
|
|
Mar 28 03:45:38 PM PDT 24 |
Mar 28 04:03:03 PM PDT 24 |
10134506352 ps |
| T599 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3054409345 |
|
|
Mar 28 03:49:07 PM PDT 24 |
Mar 28 03:53:03 PM PDT 24 |
2572084620 ps |
| T99 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.73815347 |
|
|
Mar 28 03:45:05 PM PDT 24 |
Mar 28 03:54:12 PM PDT 24 |
7477614872 ps |
| T600 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.82111720 |
|
|
Mar 28 03:55:38 PM PDT 24 |
Mar 28 03:59:47 PM PDT 24 |
2980732840 ps |
| T211 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3319620951 |
|
|
Mar 28 03:48:14 PM PDT 24 |
Mar 28 03:52:50 PM PDT 24 |
2966116608 ps |
| T291 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3930055974 |
|
|
Mar 28 03:46:31 PM PDT 24 |
Mar 28 03:53:36 PM PDT 24 |
5207364472 ps |
| T292 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.654562808 |
|
|
Mar 28 04:06:05 PM PDT 24 |
Mar 28 04:15:38 PM PDT 24 |
5735630904 ps |
| T293 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2020782519 |
|
|
Mar 28 03:49:18 PM PDT 24 |
Mar 28 04:18:06 PM PDT 24 |
5999474940 ps |
| T241 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1132273190 |
|
|
Mar 28 03:50:13 PM PDT 24 |
Mar 28 04:19:01 PM PDT 24 |
21875384900 ps |
| T281 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2996656772 |
|
|
Mar 28 03:53:41 PM PDT 24 |
Mar 28 04:00:15 PM PDT 24 |
3144444756 ps |
| T128 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2791017155 |
|
|
Mar 28 03:53:46 PM PDT 24 |
Mar 28 04:22:28 PM PDT 24 |
9845906891 ps |
| T294 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2613843639 |
|
|
Mar 28 03:46:25 PM PDT 24 |
Mar 28 04:07:23 PM PDT 24 |
7633555000 ps |
| T295 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1823135910 |
|
|
Mar 28 04:10:41 PM PDT 24 |
Mar 28 04:22:14 PM PDT 24 |
5526127504 ps |
| T296 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3038414854 |
|
|
Mar 28 03:53:23 PM PDT 24 |
Mar 28 04:27:26 PM PDT 24 |
9055107770 ps |
| T601 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3341073169 |
|
|
Mar 28 04:07:54 PM PDT 24 |
Mar 28 04:15:46 PM PDT 24 |
6928610060 ps |
| T212 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3062161318 |
|
|
Mar 28 03:51:17 PM PDT 24 |
Mar 28 03:56:44 PM PDT 24 |
3200688233 ps |
| T602 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.319437105 |
|
|
Mar 28 03:55:59 PM PDT 24 |
Mar 28 04:21:37 PM PDT 24 |
7276787514 ps |
| T603 |
/workspace/coverage/default/2.chip_sw_example_flash.4127238248 |
|
|
Mar 28 03:56:14 PM PDT 24 |
Mar 28 04:00:10 PM PDT 24 |
2601390870 ps |
| T368 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2107241777 |
|
|
Mar 28 04:08:35 PM PDT 24 |
Mar 28 04:22:12 PM PDT 24 |
5400189594 ps |
| T604 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.1457874167 |
|
|
Mar 28 03:59:38 PM PDT 24 |
Mar 28 04:05:09 PM PDT 24 |
2112579444 ps |
| T605 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.2956376746 |
|
|
Mar 28 03:47:51 PM PDT 24 |
Mar 28 03:51:52 PM PDT 24 |
2249375574 ps |
| T534 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3870289929 |
|
|
Mar 28 04:12:52 PM PDT 24 |
Mar 28 04:19:49 PM PDT 24 |
3506396920 ps |
| T466 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1973885103 |
|
|
Mar 28 04:12:58 PM PDT 24 |
Mar 28 04:22:06 PM PDT 24 |
3947606524 ps |
| T363 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2571305668 |
|
|
Mar 28 03:50:21 PM PDT 24 |
Mar 28 03:53:59 PM PDT 24 |
2125362220 ps |
| T606 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.3315153838 |
|
|
Mar 28 03:58:57 PM PDT 24 |
Mar 28 04:29:05 PM PDT 24 |
8558654370 ps |
| T374 |
/workspace/coverage/default/1.chip_sival_flash_info_access.2389126586 |
|
|
Mar 28 03:49:42 PM PDT 24 |
Mar 28 03:54:34 PM PDT 24 |
2904452896 ps |
| T607 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3701754970 |
|
|
Mar 28 03:55:22 PM PDT 24 |
Mar 28 03:59:52 PM PDT 24 |
4241132150 ps |
| T514 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.329569970 |
|
|
Mar 28 04:08:16 PM PDT 24 |
Mar 28 04:14:05 PM PDT 24 |
3514666520 ps |
| T282 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.917472184 |
|
|
Mar 28 04:02:22 PM PDT 24 |
Mar 28 04:10:51 PM PDT 24 |
4186004974 ps |
| T608 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1228018059 |
|
|
Mar 28 04:07:25 PM PDT 24 |
Mar 28 04:27:55 PM PDT 24 |
7821522128 ps |
| T609 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1189395392 |
|
|
Mar 28 03:49:29 PM PDT 24 |
Mar 28 04:00:54 PM PDT 24 |
3792021108 ps |
| T239 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.1754012225 |
|
|
Mar 28 03:58:34 PM PDT 24 |
Mar 28 04:08:31 PM PDT 24 |
4522986154 ps |
| T86 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.860788750 |
|
|
Mar 28 04:11:37 PM PDT 24 |
Mar 28 04:20:04 PM PDT 24 |
4499747352 ps |
| T467 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1602987015 |
|
|
Mar 28 04:07:34 PM PDT 24 |
Mar 28 04:17:48 PM PDT 24 |
4928705304 ps |
| T610 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.9351524 |
|
|
Mar 28 03:50:06 PM PDT 24 |
Mar 28 04:02:27 PM PDT 24 |
4995746974 ps |
| T611 |
/workspace/coverage/default/1.chip_sw_aes_entropy.976592069 |
|
|
Mar 28 03:51:02 PM PDT 24 |
Mar 28 03:54:21 PM PDT 24 |
2748002692 ps |
| T476 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1496796707 |
|
|
Mar 28 04:15:33 PM PDT 24 |
Mar 28 04:24:27 PM PDT 24 |
5867800150 ps |
| T612 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2733932136 |
|
|
Mar 28 04:03:52 PM PDT 24 |
Mar 28 04:16:06 PM PDT 24 |
8643402480 ps |
| T613 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3134706896 |
|
|
Mar 28 03:47:09 PM PDT 24 |
Mar 28 04:06:20 PM PDT 24 |
8339584306 ps |
| T355 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.3134693219 |
|
|
Mar 28 03:47:06 PM PDT 24 |
Mar 28 03:58:14 PM PDT 24 |
4329861000 ps |
| T614 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.4087231066 |
|
|
Mar 28 03:47:32 PM PDT 24 |
Mar 28 03:58:41 PM PDT 24 |
6703603901 ps |
| T498 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2682905354 |
|
|
Mar 28 04:12:45 PM PDT 24 |
Mar 28 04:21:51 PM PDT 24 |
5687116560 ps |
| T499 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4058520061 |
|
|
Mar 28 04:13:38 PM PDT 24 |
Mar 28 04:20:12 PM PDT 24 |
4352363422 ps |
| T615 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1596939053 |
|
|
Mar 28 03:52:38 PM PDT 24 |
Mar 28 04:12:46 PM PDT 24 |
5634955384 ps |
| T532 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.353454548 |
|
|
Mar 28 04:14:16 PM PDT 24 |
Mar 28 04:20:49 PM PDT 24 |
4796676400 ps |
| T35 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1493697390 |
|
|
Mar 28 03:58:15 PM PDT 24 |
Mar 28 04:04:38 PM PDT 24 |
3310873551 ps |
| T616 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1826097737 |
|
|
Mar 28 03:51:43 PM PDT 24 |
Mar 28 04:03:34 PM PDT 24 |
4895175634 ps |
| T617 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2872848520 |
|
|
Mar 28 03:51:19 PM PDT 24 |
Mar 28 04:50:43 PM PDT 24 |
17455795360 ps |
| T353 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.393334641 |
|
|
Mar 28 03:47:22 PM PDT 24 |
Mar 28 04:16:16 PM PDT 24 |
6885621072 ps |
| T618 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2287546619 |
|
|
Mar 28 03:47:45 PM PDT 24 |
Mar 28 04:36:50 PM PDT 24 |
16203659403 ps |
| T619 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3454768044 |
|
|
Mar 28 04:07:00 PM PDT 24 |
Mar 28 04:14:50 PM PDT 24 |
3363829054 ps |
| T372 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2206344614 |
|
|
Mar 28 03:44:59 PM PDT 24 |
Mar 28 03:50:52 PM PDT 24 |
2940363300 ps |
| T500 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3643646643 |
|
|
Mar 28 04:08:46 PM PDT 24 |
Mar 28 04:17:37 PM PDT 24 |
3910786008 ps |
| T620 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.114456887 |
|
|
Mar 28 03:55:27 PM PDT 24 |
Mar 28 03:59:18 PM PDT 24 |
2971042250 ps |
| T621 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3239329438 |
|
|
Mar 28 03:47:04 PM PDT 24 |
Mar 28 04:04:23 PM PDT 24 |
12989846018 ps |
| T622 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3314910739 |
|
|
Mar 28 03:45:55 PM PDT 24 |
Mar 28 03:56:58 PM PDT 24 |
4671487338 ps |
| T55 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1468042768 |
|
|
Mar 28 03:48:46 PM PDT 24 |
Mar 28 03:59:37 PM PDT 24 |
4675639880 ps |
| T504 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.578280257 |
|
|
Mar 28 04:15:12 PM PDT 24 |
Mar 28 04:22:02 PM PDT 24 |
4218140998 ps |
| T623 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3027353562 |
|
|
Mar 28 03:52:32 PM PDT 24 |
Mar 28 04:29:22 PM PDT 24 |
9194050630 ps |
| T366 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2508467857 |
|
|
Mar 28 03:48:14 PM PDT 24 |
Mar 28 03:51:54 PM PDT 24 |
3304364163 ps |
| T624 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.4190375670 |
|
|
Mar 28 03:52:52 PM PDT 24 |
Mar 28 04:38:14 PM PDT 24 |
11899375836 ps |
| T625 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1311060759 |
|
|
Mar 28 04:08:18 PM PDT 24 |
Mar 28 04:16:33 PM PDT 24 |
3563314220 ps |
| T626 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.500428101 |
|
|
Mar 28 04:01:04 PM PDT 24 |
Mar 28 04:16:28 PM PDT 24 |
8820559644 ps |
| T627 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2885206675 |
|
|
Mar 28 03:47:25 PM PDT 24 |
Mar 28 04:04:03 PM PDT 24 |
4837579808 ps |
| T480 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1875677962 |
|
|
Mar 28 04:09:34 PM PDT 24 |
Mar 28 04:18:25 PM PDT 24 |
4639669856 ps |
| T628 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.333175628 |
|
|
Mar 28 04:04:18 PM PDT 24 |
Mar 28 04:13:55 PM PDT 24 |
3997308380 ps |
| T629 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3092666467 |
|
|
Mar 28 04:02:23 PM PDT 24 |
Mar 28 04:15:31 PM PDT 24 |
4475245352 ps |
| T630 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1585796636 |
|
|
Mar 28 04:13:46 PM PDT 24 |
Mar 28 04:19:50 PM PDT 24 |
3466676648 ps |
| T439 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.81168136 |
|
|
Mar 28 03:55:12 PM PDT 24 |
Mar 28 03:57:10 PM PDT 24 |
2401330992 ps |
| T631 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.192877527 |
|
|
Mar 28 03:47:40 PM PDT 24 |
Mar 28 03:57:13 PM PDT 24 |
3592986584 ps |
| T315 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.576777975 |
|
|
Mar 28 03:48:52 PM PDT 24 |
Mar 28 03:56:28 PM PDT 24 |
5771739083 ps |
| T632 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.2997007065 |
|
|
Mar 28 04:05:27 PM PDT 24 |
Mar 28 04:10:25 PM PDT 24 |
3480635624 ps |
| T633 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2455121837 |
|
|
Mar 28 03:46:04 PM PDT 24 |
Mar 28 04:02:48 PM PDT 24 |
10314785070 ps |
| T634 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2833504112 |
|
|
Mar 28 04:02:27 PM PDT 24 |
Mar 28 04:07:14 PM PDT 24 |
3409649560 ps |
| T635 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.1051855731 |
|
|
Mar 28 03:58:08 PM PDT 24 |
Mar 28 04:02:32 PM PDT 24 |
2713016880 ps |
| T636 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2901249305 |
|
|
Mar 28 04:13:21 PM PDT 24 |
Mar 28 04:23:18 PM PDT 24 |
6394829120 ps |
| T637 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1183133743 |
|
|
Mar 28 03:47:52 PM PDT 24 |
Mar 28 04:03:12 PM PDT 24 |
7004195924 ps |
| T411 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1976040762 |
|
|
Mar 28 03:47:57 PM PDT 24 |
Mar 28 04:52:23 PM PDT 24 |
24786603415 ps |
| T304 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.86195947 |
|
|
Mar 28 04:14:56 PM PDT 24 |
Mar 28 04:25:59 PM PDT 24 |
4475888632 ps |
| T638 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.745269275 |
|
|
Mar 28 03:52:21 PM PDT 24 |
Mar 28 04:26:05 PM PDT 24 |
9379113015 ps |
| T639 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.845662274 |
|
|
Mar 28 03:50:34 PM PDT 24 |
Mar 28 03:56:08 PM PDT 24 |
3261935382 ps |
| T640 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2899052803 |
|
|
Mar 28 04:03:11 PM PDT 24 |
Mar 28 04:15:34 PM PDT 24 |
4349542200 ps |
| T641 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2122928850 |
|
|
Mar 28 03:57:34 PM PDT 24 |
Mar 28 04:35:20 PM PDT 24 |
8806711000 ps |
| T642 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.196484370 |
|
|
Mar 28 03:48:29 PM PDT 24 |
Mar 28 05:27:00 PM PDT 24 |
50541506432 ps |
| T643 |
/workspace/coverage/default/0.rom_e2e_static_critical.3825219110 |
|
|
Mar 28 03:50:53 PM PDT 24 |
Mar 28 04:36:14 PM PDT 24 |
11413193752 ps |
| T468 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2570980999 |
|
|
Mar 28 04:12:45 PM PDT 24 |
Mar 28 04:21:06 PM PDT 24 |
5380728336 ps |
| T644 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.65020481 |
|
|
Mar 28 04:06:01 PM PDT 24 |
Mar 28 04:26:13 PM PDT 24 |
7460537908 ps |
| T645 |
/workspace/coverage/default/0.chip_sw_coremark.3141889727 |
|
|
Mar 28 03:46:54 PM PDT 24 |
Mar 28 06:32:34 PM PDT 24 |
51285791032 ps |
| T259 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.1265638540 |
|
|
Mar 28 04:00:21 PM PDT 24 |
Mar 28 04:04:02 PM PDT 24 |
2468493982 ps |
| T646 |
/workspace/coverage/default/1.chip_sw_example_concurrency.3882016481 |
|
|
Mar 28 03:49:06 PM PDT 24 |
Mar 28 03:54:13 PM PDT 24 |
2960176800 ps |
| T47 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2026235148 |
|
|
Mar 28 04:02:59 PM PDT 24 |
Mar 28 04:09:14 PM PDT 24 |
4115967850 ps |
| T255 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.3348480977 |
|
|
Mar 28 04:05:33 PM PDT 24 |
Mar 28 04:09:14 PM PDT 24 |
2497604680 ps |
| T647 |
/workspace/coverage/default/1.rom_e2e_smoke.3065249247 |
|
|
Mar 28 03:54:03 PM PDT 24 |
Mar 28 04:34:19 PM PDT 24 |
8636990526 ps |
| T648 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2647505440 |
|
|
Mar 28 04:01:41 PM PDT 24 |
Mar 28 04:06:40 PM PDT 24 |
2717169320 ps |
| T214 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2986547672 |
|
|
Mar 28 03:44:43 PM PDT 24 |
Mar 28 05:06:11 PM PDT 24 |
43446689424 ps |
| T649 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2954988072 |
|
|
Mar 28 03:49:42 PM PDT 24 |
Mar 28 04:01:01 PM PDT 24 |
5316549706 ps |
| T650 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.265461991 |
|
|
Mar 28 04:11:54 PM PDT 24 |
Mar 28 04:17:52 PM PDT 24 |
3162850244 ps |
| T651 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3661163600 |
|
|
Mar 28 03:55:16 PM PDT 24 |
Mar 28 04:22:40 PM PDT 24 |
7542930828 ps |
| T188 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.434637235 |
|
|
Mar 28 04:03:53 PM PDT 24 |
Mar 28 04:15:57 PM PDT 24 |
4197400682 ps |
| T490 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.99097367 |
|
|
Mar 28 04:08:09 PM PDT 24 |
Mar 28 04:14:55 PM PDT 24 |
3577224096 ps |
| T652 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.664758019 |
|
|
Mar 28 04:01:03 PM PDT 24 |
Mar 28 04:08:57 PM PDT 24 |
6786125432 ps |
| T364 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.4281672584 |
|
|
Mar 28 03:47:05 PM PDT 24 |
Mar 28 03:52:05 PM PDT 24 |
2851177711 ps |
| T653 |
/workspace/coverage/default/2.rom_e2e_smoke.154242202 |
|
|
Mar 28 04:06:17 PM PDT 24 |
Mar 28 04:34:31 PM PDT 24 |
8532282144 ps |
| T65 |
/workspace/coverage/default/2.chip_jtag_csr_rw.375627572 |
|
|
Mar 28 03:56:04 PM PDT 24 |
Mar 28 04:30:52 PM PDT 24 |
16536127048 ps |
| T654 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3539202064 |
|
|
Mar 28 03:49:10 PM PDT 24 |
Mar 28 03:56:31 PM PDT 24 |
3064604000 ps |
| T283 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3399451628 |
|
|
Mar 28 03:45:38 PM PDT 24 |
Mar 28 03:56:31 PM PDT 24 |
5789667776 ps |
| T655 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1006764315 |
|
|
Mar 28 04:04:34 PM PDT 24 |
Mar 28 04:08:59 PM PDT 24 |
2585508495 ps |
| T656 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.993770389 |
|
|
Mar 28 03:50:23 PM PDT 24 |
Mar 28 03:58:52 PM PDT 24 |
4471270566 ps |
| T657 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.843479664 |
|
|
Mar 28 03:50:06 PM PDT 24 |
Mar 28 05:16:30 PM PDT 24 |
44742715282 ps |
| T658 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2654069023 |
|
|
Mar 28 03:52:24 PM PDT 24 |
Mar 28 03:57:58 PM PDT 24 |
3325577806 ps |
| T659 |
/workspace/coverage/default/1.chip_sw_example_rom.1878720761 |
|
|
Mar 28 03:47:49 PM PDT 24 |
Mar 28 03:50:06 PM PDT 24 |
2741854010 ps |
| T660 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2194233899 |
|
|
Mar 28 03:45:46 PM PDT 24 |
Mar 28 04:21:18 PM PDT 24 |
28077269026 ps |
| T661 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.813032068 |
|
|
Mar 28 03:45:42 PM PDT 24 |
Mar 28 03:49:18 PM PDT 24 |
3067377870 ps |
| T662 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3764860775 |
|
|
Mar 28 03:49:56 PM PDT 24 |
Mar 28 04:07:57 PM PDT 24 |
5685455888 ps |
| T663 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.4027727825 |
|
|
Mar 28 04:11:36 PM PDT 24 |
Mar 28 04:23:40 PM PDT 24 |
5269694300 ps |
| T386 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.335596220 |
|
|
Mar 28 04:12:37 PM PDT 24 |
Mar 28 04:23:51 PM PDT 24 |
5922834226 ps |
| T396 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.3926061035 |
|
|
Mar 28 03:49:24 PM PDT 24 |
Mar 28 03:53:16 PM PDT 24 |
2552234058 ps |
| T397 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.4082267918 |
|
|
Mar 28 04:02:28 PM PDT 24 |
Mar 28 04:35:38 PM PDT 24 |
10603920040 ps |
| T398 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1977552732 |
|
|
Mar 28 03:45:45 PM PDT 24 |
Mar 28 03:53:46 PM PDT 24 |
3944308400 ps |
| T87 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.925491985 |
|
|
Mar 28 04:12:03 PM PDT 24 |
Mar 28 04:19:05 PM PDT 24 |
3900994952 ps |
| T399 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1662800094 |
|
|
Mar 28 03:51:19 PM PDT 24 |
Mar 28 03:54:40 PM PDT 24 |
2990796236 ps |
| T400 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3256001930 |
|
|
Mar 28 04:09:04 PM PDT 24 |
Mar 28 04:15:08 PM PDT 24 |
3653622390 ps |
| T401 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2482721428 |
|
|
Mar 28 04:03:45 PM PDT 24 |
Mar 28 04:12:01 PM PDT 24 |
4041209354 ps |
| T402 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.869718477 |
|
|
Mar 28 04:10:56 PM PDT 24 |
Mar 28 04:16:12 PM PDT 24 |
3153665584 ps |
| T217 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3303735090 |
|
|
Mar 28 04:02:39 PM PDT 24 |
Mar 28 04:19:35 PM PDT 24 |
6215848616 ps |
| T387 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.230716736 |
|
|
Mar 28 04:08:34 PM PDT 24 |
Mar 28 04:19:06 PM PDT 24 |
5086804762 ps |
| T664 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.150115536 |
|
|
Mar 28 04:06:27 PM PDT 24 |
Mar 28 04:10:17 PM PDT 24 |
2866102680 ps |
| T665 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1423108169 |
|
|
Mar 28 03:46:41 PM PDT 24 |
Mar 28 03:52:06 PM PDT 24 |
3824046210 ps |
| T437 |
/workspace/coverage/default/2.chip_tap_straps_dev.986654632 |
|
|
Mar 28 04:03:03 PM PDT 24 |
Mar 28 04:14:23 PM PDT 24 |
7005352884 ps |
| T666 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.3594746485 |
|
|
Mar 28 03:44:48 PM PDT 24 |
Mar 28 04:02:16 PM PDT 24 |
6020541178 ps |
| T667 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2713556876 |
|
|
Mar 28 03:47:18 PM PDT 24 |
Mar 28 04:00:33 PM PDT 24 |
7335088172 ps |
| T482 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1419930959 |
|
|
Mar 28 04:15:18 PM PDT 24 |
Mar 28 04:25:57 PM PDT 24 |
5035387400 ps |
| T668 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3129736975 |
|
|
Mar 28 04:07:27 PM PDT 24 |
Mar 28 04:18:29 PM PDT 24 |
6608717339 ps |
| T669 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2511025074 |
|
|
Mar 28 03:47:26 PM PDT 24 |
Mar 28 03:50:20 PM PDT 24 |
2881559732 ps |
| T670 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2814602283 |
|
|
Mar 28 04:00:48 PM PDT 24 |
Mar 28 04:17:26 PM PDT 24 |
13009089989 ps |
| T671 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.620814663 |
|
|
Mar 28 04:00:52 PM PDT 24 |
Mar 28 04:17:37 PM PDT 24 |
6899710340 ps |
| T208 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.4079649737 |
|
|
Mar 28 03:47:21 PM PDT 24 |
Mar 28 03:51:13 PM PDT 24 |
2889851296 ps |
| T672 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2951338708 |
|
|
Mar 28 03:46:01 PM PDT 24 |
Mar 28 04:02:08 PM PDT 24 |
11418703976 ps |
| T88 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.606394229 |
|
|
Mar 28 03:56:48 PM PDT 24 |
Mar 28 04:07:13 PM PDT 24 |
4749698276 ps |
| T673 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3805701075 |
|
|
Mar 28 03:48:40 PM PDT 24 |
Mar 28 04:19:09 PM PDT 24 |
13116788315 ps |
| T362 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1323289117 |
|
|
Mar 28 03:45:37 PM PDT 24 |
Mar 28 03:56:42 PM PDT 24 |
19604247752 ps |
| T674 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3602671196 |
|
|
Mar 28 04:05:05 PM PDT 24 |
Mar 28 04:11:15 PM PDT 24 |
3480784418 ps |
| T675 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.918180444 |
|
|
Mar 28 03:58:42 PM PDT 24 |
Mar 28 04:16:20 PM PDT 24 |
5830439641 ps |
| T440 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1912555661 |
|
|
Mar 28 04:00:52 PM PDT 24 |
Mar 28 04:02:39 PM PDT 24 |
2322435934 ps |
| T75 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.928815382 |
|
|
Mar 28 04:05:48 PM PDT 24 |
Mar 28 04:09:01 PM PDT 24 |
3125892188 ps |
| T676 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.2464590442 |
|
|
Mar 28 03:47:28 PM PDT 24 |
Mar 28 03:52:56 PM PDT 24 |
3446318004 ps |
| T202 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1560116210 |
|
|
Mar 28 04:13:35 PM PDT 24 |
Mar 28 04:20:49 PM PDT 24 |
4771153576 ps |
| T677 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.724743618 |
|
|
Mar 28 04:07:52 PM PDT 24 |
Mar 28 04:15:13 PM PDT 24 |
4349588450 ps |
| T678 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.999556954 |
|
|
Mar 28 03:51:06 PM PDT 24 |
Mar 28 04:04:31 PM PDT 24 |
6890763624 ps |
| T197 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.720572408 |
|
|
Mar 28 03:52:41 PM PDT 24 |
Mar 28 03:54:44 PM PDT 24 |
2676670499 ps |
| T483 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.4175933493 |
|
|
Mar 28 04:02:57 PM PDT 24 |
Mar 28 04:08:02 PM PDT 24 |
3189644491 ps |
| T133 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3427839473 |
|
|
Mar 28 04:02:05 PM PDT 24 |
Mar 28 04:09:22 PM PDT 24 |
4835015036 ps |
| T337 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2866585983 |
|
|
Mar 28 03:47:37 PM PDT 24 |
Mar 28 03:59:56 PM PDT 24 |
4580479004 ps |
| T89 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3252131951 |
|
|
Mar 28 04:11:40 PM PDT 24 |
Mar 28 04:19:26 PM PDT 24 |
4106935184 ps |
| T49 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3163607383 |
|
|
Mar 28 03:43:23 PM PDT 24 |
Mar 28 03:48:28 PM PDT 24 |
3960305928 ps |
| T422 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335294066 |
|
|
Mar 28 04:12:11 PM PDT 24 |
Mar 28 04:19:19 PM PDT 24 |
3335840012 ps |
| T423 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2192202929 |
|
|
Mar 28 03:48:18 PM PDT 24 |
Mar 28 03:51:59 PM PDT 24 |
2208575316 ps |
| T306 |
/workspace/coverage/default/2.chip_sw_power_idle_load.3044001895 |
|
|
Mar 28 04:06:04 PM PDT 24 |
Mar 28 04:16:58 PM PDT 24 |
3702304672 ps |
| T379 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3156081598 |
|
|
Mar 28 04:12:59 PM PDT 24 |
Mar 28 04:21:33 PM PDT 24 |
3689644150 ps |
| T424 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2749604778 |
|
|
Mar 28 03:52:51 PM PDT 24 |
Mar 28 04:01:26 PM PDT 24 |
4559478432 ps |
| T425 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.1065855991 |
|
|
Mar 28 03:48:56 PM PDT 24 |
Mar 28 04:07:04 PM PDT 24 |
5699379260 ps |
| T426 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3031555171 |
|
|
Mar 28 04:07:44 PM PDT 24 |
Mar 28 04:44:31 PM PDT 24 |
12716606734 ps |
| T231 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2416912632 |
|
|
Mar 28 03:44:55 PM PDT 24 |
Mar 28 03:51:54 PM PDT 24 |
3908444064 ps |
| T427 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3870043745 |
|
|
Mar 28 03:48:11 PM PDT 24 |
Mar 28 03:57:50 PM PDT 24 |
4139952592 ps |