| T679 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1845528841 |
|
|
Mar 28 04:04:12 PM PDT 24 |
Mar 28 04:11:05 PM PDT 24 |
3924087086 ps |
| T680 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.546655054 |
|
|
Mar 28 03:46:42 PM PDT 24 |
Mar 28 03:55:14 PM PDT 24 |
5126571470 ps |
| T681 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1956057042 |
|
|
Mar 28 03:45:34 PM PDT 24 |
Mar 28 03:52:13 PM PDT 24 |
3313578032 ps |
| T682 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3744206764 |
|
|
Mar 28 03:49:17 PM PDT 24 |
Mar 28 03:55:09 PM PDT 24 |
5204208840 ps |
| T324 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.3248251482 |
|
|
Mar 28 04:04:04 PM PDT 24 |
Mar 28 04:15:33 PM PDT 24 |
11232911404 ps |
| T683 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.4187064119 |
|
|
Mar 28 04:13:55 PM PDT 24 |
Mar 28 04:24:10 PM PDT 24 |
4703009576 ps |
| T176 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.626003042 |
|
|
Mar 28 03:46:59 PM PDT 24 |
Mar 28 03:56:50 PM PDT 24 |
6167782226 ps |
| T684 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1584198478 |
|
|
Mar 28 04:07:04 PM PDT 24 |
Mar 28 04:28:19 PM PDT 24 |
7985160544 ps |
| T685 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3211170340 |
|
|
Mar 28 04:00:51 PM PDT 24 |
Mar 28 04:09:26 PM PDT 24 |
4277614710 ps |
| T686 |
/workspace/coverage/default/1.chip_sw_kmac_idle.1786784075 |
|
|
Mar 28 03:50:14 PM PDT 24 |
Mar 28 03:54:39 PM PDT 24 |
2592870440 ps |
| T687 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1354620744 |
|
|
Mar 28 03:48:27 PM PDT 24 |
Mar 28 03:57:15 PM PDT 24 |
5158894274 ps |
| T688 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1371050476 |
|
|
Mar 28 03:45:21 PM PDT 24 |
Mar 28 03:54:14 PM PDT 24 |
5701433016 ps |
| T67 |
/workspace/coverage/default/0.chip_sw_alert_test.916912125 |
|
|
Mar 28 03:46:59 PM PDT 24 |
Mar 28 03:52:32 PM PDT 24 |
3344961974 ps |
| T689 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2119257510 |
|
|
Mar 28 04:00:13 PM PDT 24 |
Mar 28 04:11:25 PM PDT 24 |
4648774400 ps |
| T690 |
/workspace/coverage/default/1.chip_sw_aes_enc.3106621715 |
|
|
Mar 28 03:47:51 PM PDT 24 |
Mar 28 03:52:40 PM PDT 24 |
2756122388 ps |
| T542 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4039449596 |
|
|
Mar 28 03:56:09 PM PDT 24 |
Mar 28 04:03:15 PM PDT 24 |
3899619392 ps |
| T377 |
/workspace/coverage/default/0.chip_sw_hmac_enc.3809642702 |
|
|
Mar 28 03:48:15 PM PDT 24 |
Mar 28 03:52:20 PM PDT 24 |
2970900464 ps |
| T413 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.2046477502 |
|
|
Mar 28 03:46:40 PM PDT 24 |
Mar 28 04:04:42 PM PDT 24 |
4469062360 ps |
| T493 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1011746248 |
|
|
Mar 28 04:13:34 PM PDT 24 |
Mar 28 04:24:16 PM PDT 24 |
5626019480 ps |
| T225 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2224967510 |
|
|
Mar 28 04:00:12 PM PDT 24 |
Mar 28 04:25:31 PM PDT 24 |
11963794624 ps |
| T691 |
/workspace/coverage/default/0.chip_sw_example_flash.3057139179 |
|
|
Mar 28 03:43:48 PM PDT 24 |
Mar 28 03:47:37 PM PDT 24 |
2865242328 ps |
| T134 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1941136968 |
|
|
Mar 28 03:48:24 PM PDT 24 |
Mar 28 04:00:16 PM PDT 24 |
4612701280 ps |
| T345 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2433594753 |
|
|
Mar 28 03:47:01 PM PDT 24 |
Mar 28 04:13:39 PM PDT 24 |
9679426091 ps |
| T692 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1692985188 |
|
|
Mar 28 03:46:25 PM PDT 24 |
Mar 28 04:12:29 PM PDT 24 |
8326010860 ps |
| T693 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3608485307 |
|
|
Mar 28 04:08:01 PM PDT 24 |
Mar 28 04:36:05 PM PDT 24 |
8506087114 ps |
| T694 |
/workspace/coverage/default/4.chip_tap_straps_rma.795721295 |
|
|
Mar 28 04:06:09 PM PDT 24 |
Mar 28 04:10:32 PM PDT 24 |
3389294642 ps |
| T312 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3444504795 |
|
|
Mar 28 03:50:34 PM PDT 24 |
Mar 28 03:59:32 PM PDT 24 |
5121394912 ps |
| T695 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1224762179 |
|
|
Mar 28 04:07:13 PM PDT 24 |
Mar 28 04:16:00 PM PDT 24 |
3612677756 ps |
| T696 |
/workspace/coverage/default/1.chip_sw_hmac_enc.902754612 |
|
|
Mar 28 03:52:47 PM PDT 24 |
Mar 28 03:58:15 PM PDT 24 |
2982632232 ps |
| T417 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1807769714 |
|
|
Mar 28 04:07:54 PM PDT 24 |
Mar 28 04:13:55 PM PDT 24 |
3235488400 ps |
| T506 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.48157369 |
|
|
Mar 28 04:06:44 PM PDT 24 |
Mar 28 04:13:04 PM PDT 24 |
3516603338 ps |
| T697 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2905039445 |
|
|
Mar 28 04:07:31 PM PDT 24 |
Mar 28 04:27:59 PM PDT 24 |
7769325280 ps |
| T698 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2584967497 |
|
|
Mar 28 03:51:56 PM PDT 24 |
Mar 28 04:03:53 PM PDT 24 |
5006273829 ps |
| T193 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.760291290 |
|
|
Mar 28 03:56:45 PM PDT 24 |
Mar 28 06:45:21 PM PDT 24 |
58446948361 ps |
| T699 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.637691651 |
|
|
Mar 28 03:58:31 PM PDT 24 |
Mar 28 04:07:50 PM PDT 24 |
4289454236 ps |
| T416 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.1353637189 |
|
|
Mar 28 03:45:25 PM PDT 24 |
Mar 28 03:53:07 PM PDT 24 |
3255984574 ps |
| T700 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2102751517 |
|
|
Mar 28 03:47:43 PM PDT 24 |
Mar 28 03:54:26 PM PDT 24 |
2826282704 ps |
| T434 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1728580380 |
|
|
Mar 28 04:02:40 PM PDT 24 |
Mar 28 04:33:10 PM PDT 24 |
28067695974 ps |
| T66 |
/workspace/coverage/default/1.chip_jtag_csr_rw.3956344616 |
|
|
Mar 28 03:41:54 PM PDT 24 |
Mar 28 04:20:28 PM PDT 24 |
17401953638 ps |
| T701 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1113414649 |
|
|
Mar 28 03:47:48 PM PDT 24 |
Mar 28 04:09:36 PM PDT 24 |
11630119980 ps |
| T702 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1507518859 |
|
|
Mar 28 04:12:46 PM PDT 24 |
Mar 28 04:19:29 PM PDT 24 |
4060445026 ps |
| T703 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1917136505 |
|
|
Mar 28 04:02:14 PM PDT 24 |
Mar 28 04:06:14 PM PDT 24 |
2528292324 ps |
| T53 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2902501430 |
|
|
Mar 28 03:48:57 PM PDT 24 |
Mar 28 04:22:54 PM PDT 24 |
22000070708 ps |
| T704 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3779760706 |
|
|
Mar 28 03:46:48 PM PDT 24 |
Mar 28 04:05:42 PM PDT 24 |
6010604125 ps |
| T705 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.5540209 |
|
|
Mar 28 03:47:36 PM PDT 24 |
Mar 28 03:57:46 PM PDT 24 |
4866129792 ps |
| T247 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1818824279 |
|
|
Mar 28 04:13:05 PM PDT 24 |
Mar 28 04:25:17 PM PDT 24 |
6285870272 ps |
| T706 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.887728863 |
|
|
Mar 28 04:04:39 PM PDT 24 |
Mar 28 04:08:48 PM PDT 24 |
2415042168 ps |
| T707 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.4004100718 |
|
|
Mar 28 04:01:13 PM PDT 24 |
Mar 28 04:19:15 PM PDT 24 |
7253027880 ps |
| T708 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.566422063 |
|
|
Mar 28 03:46:44 PM PDT 24 |
Mar 28 03:57:35 PM PDT 24 |
4248619276 ps |
| T243 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2824088537 |
|
|
Mar 28 04:11:46 PM PDT 24 |
Mar 28 04:22:18 PM PDT 24 |
4286273256 ps |
| T270 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3195613718 |
|
|
Mar 28 04:06:24 PM PDT 24 |
Mar 28 04:16:25 PM PDT 24 |
5873210948 ps |
| T272 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3389937143 |
|
|
Mar 28 03:45:03 PM PDT 24 |
Mar 28 06:24:36 PM PDT 24 |
58896297875 ps |
| T273 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.1188304050 |
|
|
Mar 28 03:50:00 PM PDT 24 |
Mar 28 03:54:19 PM PDT 24 |
2713511256 ps |
| T274 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2540150158 |
|
|
Mar 28 03:46:41 PM PDT 24 |
Mar 28 03:55:35 PM PDT 24 |
4756074149 ps |
| T275 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3699376715 |
|
|
Mar 28 03:47:49 PM PDT 24 |
Mar 28 04:42:40 PM PDT 24 |
12115243150 ps |
| T276 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.811435888 |
|
|
Mar 28 04:14:54 PM PDT 24 |
Mar 28 04:24:13 PM PDT 24 |
5700429664 ps |
| T277 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.69477438 |
|
|
Mar 28 03:48:47 PM PDT 24 |
Mar 28 04:05:46 PM PDT 24 |
5159629128 ps |
| T278 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1823110971 |
|
|
Mar 28 03:55:28 PM PDT 24 |
Mar 28 04:27:53 PM PDT 24 |
8540942168 ps |
| T279 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.354941293 |
|
|
Mar 28 04:11:54 PM PDT 24 |
Mar 28 04:23:43 PM PDT 24 |
5256022448 ps |
| T280 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2528383197 |
|
|
Mar 28 03:47:47 PM PDT 24 |
Mar 28 03:58:29 PM PDT 24 |
5281400647 ps |
| T709 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3131268552 |
|
|
Mar 28 03:56:27 PM PDT 24 |
Mar 28 04:35:54 PM PDT 24 |
8590473690 ps |
| T710 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1825571102 |
|
|
Mar 28 04:04:10 PM PDT 24 |
Mar 28 04:16:50 PM PDT 24 |
4900652306 ps |
| T711 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2388463841 |
|
|
Mar 28 04:15:46 PM PDT 24 |
Mar 28 04:25:25 PM PDT 24 |
4685027332 ps |
| T712 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.734984013 |
|
|
Mar 28 03:54:53 PM PDT 24 |
Mar 28 03:59:21 PM PDT 24 |
2707786160 ps |
| T713 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2643879767 |
|
|
Mar 28 03:47:24 PM PDT 24 |
Mar 28 03:58:21 PM PDT 24 |
7504668520 ps |
| T218 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.622800373 |
|
|
Mar 28 03:46:45 PM PDT 24 |
Mar 28 04:07:12 PM PDT 24 |
6336589160 ps |
| T714 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3030147735 |
|
|
Mar 28 03:55:56 PM PDT 24 |
Mar 28 04:27:36 PM PDT 24 |
8340058836 ps |
| T158 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1495727254 |
|
|
Mar 28 03:44:19 PM PDT 24 |
Mar 28 03:47:40 PM PDT 24 |
3076979312 ps |
| T715 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.13320770 |
|
|
Mar 28 03:50:05 PM PDT 24 |
Mar 28 03:57:37 PM PDT 24 |
5468903514 ps |
| T716 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3290759689 |
|
|
Mar 28 04:02:18 PM PDT 24 |
Mar 28 05:02:51 PM PDT 24 |
16801756476 ps |
| T455 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3148297388 |
|
|
Mar 28 04:10:41 PM PDT 24 |
Mar 28 04:21:58 PM PDT 24 |
5751152816 ps |
| T717 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2537735187 |
|
|
Mar 28 04:03:23 PM PDT 24 |
Mar 28 04:14:09 PM PDT 24 |
7067367368 ps |
| T718 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.470215024 |
|
|
Mar 28 03:49:49 PM PDT 24 |
Mar 28 03:54:01 PM PDT 24 |
2915808808 ps |
| T719 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2109442035 |
|
|
Mar 28 03:53:53 PM PDT 24 |
Mar 28 04:06:46 PM PDT 24 |
4552589238 ps |
| T720 |
/workspace/coverage/default/2.chip_sw_example_concurrency.2615407896 |
|
|
Mar 28 03:56:35 PM PDT 24 |
Mar 28 04:01:31 PM PDT 24 |
2965806544 ps |
| T146 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1281594069 |
|
|
Mar 28 03:50:25 PM PDT 24 |
Mar 28 04:02:28 PM PDT 24 |
8901861146 ps |
| T521 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1119234249 |
|
|
Mar 28 04:09:32 PM PDT 24 |
Mar 28 04:14:35 PM PDT 24 |
4060324152 ps |
| T721 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3068144041 |
|
|
Mar 28 03:49:58 PM PDT 24 |
Mar 28 04:38:39 PM PDT 24 |
32601443680 ps |
| T722 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.2986605963 |
|
|
Mar 28 03:49:54 PM PDT 24 |
Mar 28 04:09:06 PM PDT 24 |
6105192376 ps |
| T354 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3669917288 |
|
|
Mar 28 03:45:30 PM PDT 24 |
Mar 28 04:09:11 PM PDT 24 |
6382755752 ps |
| T418 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1664485243 |
|
|
Mar 28 04:12:57 PM PDT 24 |
Mar 28 04:18:18 PM PDT 24 |
3795753450 ps |
| T723 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.113659354 |
|
|
Mar 28 03:51:57 PM PDT 24 |
Mar 28 04:00:30 PM PDT 24 |
6503203412 ps |
| T724 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.188369713 |
|
|
Mar 28 04:01:48 PM PDT 24 |
Mar 28 04:30:45 PM PDT 24 |
8425520800 ps |
| T725 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.777663914 |
|
|
Mar 28 04:05:03 PM PDT 24 |
Mar 28 04:09:49 PM PDT 24 |
2638567322 ps |
| T726 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2559895072 |
|
|
Mar 28 03:49:15 PM PDT 24 |
Mar 28 03:52:57 PM PDT 24 |
2380483720 ps |
| T727 |
/workspace/coverage/default/0.chip_sw_aes_entropy.1492116857 |
|
|
Mar 28 03:46:50 PM PDT 24 |
Mar 28 03:52:07 PM PDT 24 |
2715828064 ps |
| T68 |
/workspace/coverage/default/2.chip_sw_alert_test.3662559058 |
|
|
Mar 28 04:00:27 PM PDT 24 |
Mar 28 04:05:44 PM PDT 24 |
2802037204 ps |
| T316 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.398063349 |
|
|
Mar 28 04:00:42 PM PDT 24 |
Mar 28 04:59:58 PM PDT 24 |
17290527000 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4286701649 |
|
|
Mar 28 03:48:30 PM PDT 24 |
Mar 28 03:57:15 PM PDT 24 |
5095446112 ps |
| T502 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1262530746 |
|
|
Mar 28 04:07:26 PM PDT 24 |
Mar 28 04:17:02 PM PDT 24 |
4116956200 ps |
| T147 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.2954831628 |
|
|
Mar 28 04:02:29 PM PDT 24 |
Mar 28 04:05:44 PM PDT 24 |
2935445656 ps |
| T728 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1742973660 |
|
|
Mar 28 04:04:31 PM PDT 24 |
Mar 28 04:13:51 PM PDT 24 |
3935724660 ps |
| T375 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2648252482 |
|
|
Mar 28 03:51:28 PM PDT 24 |
Mar 28 04:03:13 PM PDT 24 |
3552115650 ps |
| T729 |
/workspace/coverage/default/1.rom_e2e_static_critical.1618320241 |
|
|
Mar 28 03:58:35 PM PDT 24 |
Mar 28 04:39:26 PM PDT 24 |
10528940000 ps |
| T730 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.140523505 |
|
|
Mar 28 03:57:07 PM PDT 24 |
Mar 28 04:00:51 PM PDT 24 |
2152271384 ps |
| T340 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3557248261 |
|
|
Mar 28 04:00:23 PM PDT 24 |
Mar 28 04:26:38 PM PDT 24 |
24398466652 ps |
| T731 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2332215439 |
|
|
Mar 28 04:06:40 PM PDT 24 |
Mar 28 04:19:22 PM PDT 24 |
4190250840 ps |
| T535 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1820718331 |
|
|
Mar 28 04:10:55 PM PDT 24 |
Mar 28 04:20:09 PM PDT 24 |
4693822244 ps |
| T328 |
/workspace/coverage/default/1.rom_raw_unlock.908726008 |
|
|
Mar 28 03:55:42 PM PDT 24 |
Mar 28 04:29:33 PM PDT 24 |
13909166428 ps |
| T732 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3328836235 |
|
|
Mar 28 03:50:17 PM PDT 24 |
Mar 28 04:47:58 PM PDT 24 |
17736834740 ps |
| T733 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3901179314 |
|
|
Mar 28 03:44:24 PM PDT 24 |
Mar 28 06:35:30 PM PDT 24 |
57436949208 ps |
| T734 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3216297148 |
|
|
Mar 28 03:55:33 PM PDT 24 |
Mar 28 04:25:10 PM PDT 24 |
7783505972 ps |
| T203 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1522862087 |
|
|
Mar 28 03:45:08 PM PDT 24 |
Mar 28 03:55:18 PM PDT 24 |
4460245210 ps |
| T438 |
/workspace/coverage/default/1.chip_tap_straps_dev.932978160 |
|
|
Mar 28 03:51:55 PM PDT 24 |
Mar 28 04:18:25 PM PDT 24 |
14042859012 ps |
| T735 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2413700159 |
|
|
Mar 28 03:48:23 PM PDT 24 |
Mar 28 03:57:13 PM PDT 24 |
5269831598 ps |
| T736 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3858426348 |
|
|
Mar 28 04:06:18 PM PDT 24 |
Mar 28 04:27:11 PM PDT 24 |
7191498445 ps |
| T313 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.969603521 |
|
|
Mar 28 03:50:12 PM PDT 24 |
Mar 28 03:56:39 PM PDT 24 |
5289559480 ps |
| T737 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2275028903 |
|
|
Mar 28 04:08:54 PM PDT 24 |
Mar 28 04:21:09 PM PDT 24 |
12532788172 ps |
| T738 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.308167706 |
|
|
Mar 28 04:07:50 PM PDT 24 |
Mar 28 04:15:00 PM PDT 24 |
4200673710 ps |
| T739 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2629424769 |
|
|
Mar 28 03:44:50 PM PDT 24 |
Mar 28 04:08:03 PM PDT 24 |
7731444852 ps |
| T740 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2542362116 |
|
|
Mar 28 04:02:48 PM PDT 24 |
Mar 28 04:10:31 PM PDT 24 |
3925710238 ps |
| T741 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2083611091 |
|
|
Mar 28 03:58:26 PM PDT 24 |
Mar 28 04:07:45 PM PDT 24 |
3961663074 ps |
| T742 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.860864768 |
|
|
Mar 28 03:56:00 PM PDT 24 |
Mar 28 04:00:42 PM PDT 24 |
2670526540 ps |
| T743 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3972426697 |
|
|
Mar 28 04:06:18 PM PDT 24 |
Mar 28 04:16:03 PM PDT 24 |
5736336012 ps |
| T744 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3022150322 |
|
|
Mar 28 03:49:30 PM PDT 24 |
Mar 28 04:00:12 PM PDT 24 |
4942867815 ps |
| T388 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3310536545 |
|
|
Mar 28 04:11:46 PM PDT 24 |
Mar 28 04:21:58 PM PDT 24 |
5884128120 ps |
| T745 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3455739140 |
|
|
Mar 28 03:45:12 PM PDT 24 |
Mar 28 06:54:52 PM PDT 24 |
64499025038 ps |
| T746 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2767087103 |
|
|
Mar 28 04:09:34 PM PDT 24 |
Mar 28 04:17:30 PM PDT 24 |
3821057230 ps |
| T329 |
/workspace/coverage/default/0.rom_raw_unlock.1491670226 |
|
|
Mar 28 03:48:26 PM PDT 24 |
Mar 28 04:26:17 PM PDT 24 |
15963055462 ps |
| T747 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2304266575 |
|
|
Mar 28 03:52:22 PM PDT 24 |
Mar 28 04:27:55 PM PDT 24 |
8764257783 ps |
| T748 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.164123178 |
|
|
Mar 28 03:52:42 PM PDT 24 |
Mar 28 04:03:44 PM PDT 24 |
3864066950 ps |
| T749 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1530756945 |
|
|
Mar 28 03:59:04 PM PDT 24 |
Mar 28 04:04:44 PM PDT 24 |
2804027590 ps |
| T750 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.1559577895 |
|
|
Mar 28 03:49:59 PM PDT 24 |
Mar 28 03:54:23 PM PDT 24 |
3007171900 ps |
| T380 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.227658880 |
|
|
Mar 28 04:00:21 PM PDT 24 |
Mar 28 04:04:20 PM PDT 24 |
2904461096 ps |
| T751 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1056647542 |
|
|
Mar 28 03:49:36 PM PDT 24 |
Mar 28 03:58:39 PM PDT 24 |
4915507082 ps |
| T752 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.791823981 |
|
|
Mar 28 03:56:49 PM PDT 24 |
Mar 28 04:09:17 PM PDT 24 |
3888038680 ps |
| T342 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.250030501 |
|
|
Mar 28 04:01:06 PM PDT 24 |
Mar 28 04:14:05 PM PDT 24 |
4296047940 ps |
| T753 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1493894901 |
|
|
Mar 28 03:59:49 PM PDT 24 |
Mar 28 04:04:35 PM PDT 24 |
2874485356 ps |
| T754 |
/workspace/coverage/default/3.chip_tap_straps_rma.2709162668 |
|
|
Mar 28 04:05:14 PM PDT 24 |
Mar 28 04:07:51 PM PDT 24 |
2012350762 ps |
| T755 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1614246765 |
|
|
Mar 28 03:50:33 PM PDT 24 |
Mar 28 03:55:01 PM PDT 24 |
2761423851 ps |
| T325 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3008686480 |
|
|
Mar 28 03:47:24 PM PDT 24 |
Mar 28 04:18:40 PM PDT 24 |
10743910520 ps |
| T756 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.454387288 |
|
|
Mar 28 03:50:19 PM PDT 24 |
Mar 28 03:57:26 PM PDT 24 |
3754835720 ps |
| T523 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3783611232 |
|
|
Mar 28 04:07:00 PM PDT 24 |
Mar 28 04:12:57 PM PDT 24 |
3281805684 ps |
| T757 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1147251843 |
|
|
Mar 28 03:46:32 PM PDT 24 |
Mar 28 03:51:33 PM PDT 24 |
3590547870 ps |
| T758 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3802207360 |
|
|
Mar 28 03:48:12 PM PDT 24 |
Mar 28 04:46:28 PM PDT 24 |
38128653342 ps |
| T759 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2374795652 |
|
|
Mar 28 03:50:00 PM PDT 24 |
Mar 28 04:04:56 PM PDT 24 |
7390757842 ps |
| T760 |
/workspace/coverage/default/0.chip_tap_straps_rma.3656159420 |
|
|
Mar 28 03:47:24 PM PDT 24 |
Mar 28 03:49:56 PM PDT 24 |
2865805130 ps |
| T761 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.611282230 |
|
|
Mar 28 03:58:33 PM PDT 24 |
Mar 28 04:17:01 PM PDT 24 |
5007924680 ps |
| T762 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3723919531 |
|
|
Mar 28 03:47:36 PM PDT 24 |
Mar 28 07:25:01 PM PDT 24 |
254353073504 ps |
| T763 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2304236183 |
|
|
Mar 28 03:47:40 PM PDT 24 |
Mar 28 04:22:29 PM PDT 24 |
20798431677 ps |
| T764 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.4004496597 |
|
|
Mar 28 03:57:36 PM PDT 24 |
Mar 28 04:34:17 PM PDT 24 |
8389196762 ps |
| T765 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1489942992 |
|
|
Mar 28 04:02:34 PM PDT 24 |
Mar 28 04:07:10 PM PDT 24 |
3315963172 ps |
| T256 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.2518525188 |
|
|
Mar 28 03:45:41 PM PDT 24 |
Mar 28 03:49:35 PM PDT 24 |
2305973272 ps |
| T365 |
/workspace/coverage/default/2.chip_sival_flash_info_access.25391955 |
|
|
Mar 28 03:56:38 PM PDT 24 |
Mar 28 04:01:53 PM PDT 24 |
3168938964 ps |
| T766 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3090194732 |
|
|
Mar 28 03:56:24 PM PDT 24 |
Mar 28 04:06:47 PM PDT 24 |
4324699070 ps |
| T767 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.521490068 |
|
|
Mar 28 03:49:15 PM PDT 24 |
Mar 28 03:57:32 PM PDT 24 |
4309347104 ps |
| T412 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1181500848 |
|
|
Mar 28 04:05:53 PM PDT 24 |
Mar 28 05:13:56 PM PDT 24 |
24921088311 ps |
| T257 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.969920411 |
|
|
Mar 28 03:51:23 PM PDT 24 |
Mar 28 03:56:39 PM PDT 24 |
3286016726 ps |
| T349 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1869100585 |
|
|
Mar 28 04:07:04 PM PDT 24 |
Mar 28 04:18:23 PM PDT 24 |
4717714654 ps |
| T768 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.740279239 |
|
|
Mar 28 03:47:15 PM PDT 24 |
Mar 28 03:54:51 PM PDT 24 |
4659913250 ps |
| T769 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3457745160 |
|
|
Mar 28 03:45:29 PM PDT 24 |
Mar 28 03:50:56 PM PDT 24 |
2966860812 ps |
| T519 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2678298041 |
|
|
Mar 28 04:11:41 PM PDT 24 |
Mar 28 04:23:48 PM PDT 24 |
4806063160 ps |
| T159 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3534515330 |
|
|
Mar 28 03:45:15 PM PDT 24 |
Mar 28 03:48:51 PM PDT 24 |
2955260250 ps |
| T284 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.694430052 |
|
|
Mar 28 04:14:17 PM PDT 24 |
Mar 28 04:20:49 PM PDT 24 |
4320773660 ps |
| T184 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3450627746 |
|
|
Mar 28 03:45:20 PM PDT 24 |
Mar 28 03:54:30 PM PDT 24 |
3596932708 ps |
| T770 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1852508751 |
|
|
Mar 28 03:47:21 PM PDT 24 |
Mar 28 03:56:20 PM PDT 24 |
4380757690 ps |
| T771 |
/workspace/coverage/default/1.chip_tap_straps_rma.2786882035 |
|
|
Mar 28 03:48:15 PM PDT 24 |
Mar 28 03:54:24 PM PDT 24 |
4593006965 ps |
| T772 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.908964284 |
|
|
Mar 28 03:47:08 PM PDT 24 |
Mar 28 03:58:01 PM PDT 24 |
4125688588 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1211061246 |
|
|
Mar 28 03:56:52 PM PDT 24 |
Mar 28 04:00:25 PM PDT 24 |
3296945936 ps |
| T77 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2557448387 |
|
|
Mar 28 03:44:46 PM PDT 24 |
Mar 28 03:53:45 PM PDT 24 |
3921330850 ps |
| T428 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.24264196 |
|
|
Mar 28 03:44:59 PM PDT 24 |
Mar 28 03:49:29 PM PDT 24 |
3179632136 ps |
| T138 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2764076445 |
|
|
Mar 28 04:05:41 PM PDT 24 |
Mar 28 04:20:54 PM PDT 24 |
6953534000 ps |
| T429 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.1872855819 |
|
|
Mar 28 03:45:34 PM PDT 24 |
Mar 28 04:34:17 PM PDT 24 |
11252421830 ps |
| T430 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2434616371 |
|
|
Mar 28 03:52:37 PM PDT 24 |
Mar 28 03:56:27 PM PDT 24 |
2980739244 ps |
| T431 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1070803260 |
|
|
Mar 28 03:52:42 PM PDT 24 |
Mar 28 04:10:46 PM PDT 24 |
5536752989 ps |
| T343 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1091445932 |
|
|
Mar 28 04:04:08 PM PDT 24 |
Mar 28 04:14:51 PM PDT 24 |
5476389149 ps |
| T432 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.689579698 |
|
|
Mar 28 04:01:24 PM PDT 24 |
Mar 28 04:05:05 PM PDT 24 |
2159184904 ps |
| T213 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1616577245 |
|
|
Mar 28 04:04:29 PM PDT 24 |
Mar 28 04:10:04 PM PDT 24 |
3016220410 ps |
| T773 |
/workspace/coverage/default/2.chip_sw_edn_kat.2639461622 |
|
|
Mar 28 04:02:49 PM PDT 24 |
Mar 28 04:14:23 PM PDT 24 |
3239702490 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1222623978 |
|
|
Mar 28 03:46:48 PM PDT 24 |
Mar 28 03:59:30 PM PDT 24 |
4719847684 ps |
| T538 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1240903009 |
|
|
Mar 28 04:13:20 PM PDT 24 |
Mar 28 04:23:29 PM PDT 24 |
5434340432 ps |
| T314 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2690626612 |
|
|
Mar 28 04:03:13 PM PDT 24 |
Mar 28 04:14:45 PM PDT 24 |
5242889472 ps |
| T774 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.35504235 |
|
|
Mar 28 03:58:21 PM PDT 24 |
Mar 28 04:17:12 PM PDT 24 |
6257016322 ps |
| T497 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1035143082 |
|
|
Mar 28 04:16:30 PM PDT 24 |
Mar 28 04:25:14 PM PDT 24 |
5033660650 ps |
| T381 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2475944000 |
|
|
Mar 28 03:46:41 PM PDT 24 |
Mar 28 03:49:42 PM PDT 24 |
2238695500 ps |
| T376 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2268546459 |
|
|
Mar 28 03:47:01 PM PDT 24 |
Mar 28 03:58:45 PM PDT 24 |
4768717990 ps |
| T775 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1261717693 |
|
|
Mar 28 04:04:05 PM PDT 24 |
Mar 28 04:11:33 PM PDT 24 |
5310665940 ps |
| T776 |
/workspace/coverage/default/3.chip_tap_straps_dev.1033594564 |
|
|
Mar 28 04:05:05 PM PDT 24 |
Mar 28 04:33:43 PM PDT 24 |
14432785441 ps |
| T777 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.140799203 |
|
|
Mar 28 03:46:48 PM PDT 24 |
Mar 28 03:56:23 PM PDT 24 |
4538000064 ps |
| T778 |
/workspace/coverage/default/0.chip_sw_example_concurrency.1529224671 |
|
|
Mar 28 03:46:02 PM PDT 24 |
Mar 28 03:49:52 PM PDT 24 |
3200422912 ps |
| T373 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.661432532 |
|
|
Mar 28 03:47:42 PM PDT 24 |
Mar 28 03:54:58 PM PDT 24 |
3733704728 ps |
| T779 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.253847438 |
|
|
Mar 28 04:05:14 PM PDT 24 |
Mar 28 04:09:35 PM PDT 24 |
3032422933 ps |
| T780 |
/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.1422611140 |
|
|
Mar 28 03:51:28 PM PDT 24 |
Mar 28 04:26:55 PM PDT 24 |
9120850942 ps |
| T781 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1725882161 |
|
|
Mar 28 04:01:46 PM PDT 24 |
Mar 28 04:11:31 PM PDT 24 |
4697915130 ps |
| T782 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1635230536 |
|
|
Mar 28 03:57:47 PM PDT 24 |
Mar 28 04:19:00 PM PDT 24 |
8215811239 ps |
| T783 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3539105519 |
|
|
Mar 28 03:47:24 PM PDT 24 |
Mar 28 04:18:29 PM PDT 24 |
20778579918 ps |
| T784 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3368803791 |
|
|
Mar 28 03:47:59 PM PDT 24 |
Mar 28 03:52:37 PM PDT 24 |
2754445570 ps |
| T785 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2321353569 |
|
|
Mar 28 04:05:58 PM PDT 24 |
Mar 28 04:16:55 PM PDT 24 |
4075876904 ps |
| T441 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.278707541 |
|
|
Mar 28 03:47:47 PM PDT 24 |
Mar 28 03:49:33 PM PDT 24 |
2876538965 ps |
| T786 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.123134642 |
|
|
Mar 28 03:47:43 PM PDT 24 |
Mar 28 03:51:08 PM PDT 24 |
2620307920 ps |
| T148 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4025239928 |
|
|
Mar 28 03:51:05 PM PDT 24 |
Mar 28 04:00:42 PM PDT 24 |
8627197231 ps |
| T787 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3631351422 |
|
|
Mar 28 03:49:08 PM PDT 24 |
Mar 28 04:09:33 PM PDT 24 |
9400599948 ps |
| T788 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.667316880 |
|
|
Mar 28 03:45:16 PM PDT 24 |
Mar 28 03:51:29 PM PDT 24 |
4433366446 ps |
| T789 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.704090296 |
|
|
Mar 28 04:05:26 PM PDT 24 |
Mar 28 04:18:02 PM PDT 24 |
4418600000 ps |
| T790 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2354834258 |
|
|
Mar 28 04:00:02 PM PDT 24 |
Mar 28 04:05:47 PM PDT 24 |
3419601971 ps |
| T518 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.800316007 |
|
|
Mar 28 04:13:07 PM PDT 24 |
Mar 28 04:23:35 PM PDT 24 |
5830889684 ps |
| T515 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.4241041132 |
|
|
Mar 28 03:49:17 PM PDT 24 |
Mar 28 04:02:11 PM PDT 24 |
4681637500 ps |
| T791 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.976688879 |
|
|
Mar 28 03:55:53 PM PDT 24 |
Mar 28 04:47:18 PM PDT 24 |
10891850692 ps |
| T792 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.440556074 |
|
|
Mar 28 03:52:48 PM PDT 24 |
Mar 28 04:26:29 PM PDT 24 |
8598222726 ps |
| T793 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1487350949 |
|
|
Mar 28 03:46:49 PM PDT 24 |
Mar 28 03:55:38 PM PDT 24 |
4468890752 ps |
| T794 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1222926137 |
|
|
Mar 28 04:07:42 PM PDT 24 |
Mar 28 04:26:34 PM PDT 24 |
13638817972 ps |
| T795 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3676966132 |
|
|
Mar 28 03:54:40 PM PDT 24 |
Mar 28 04:47:09 PM PDT 24 |
12096002360 ps |
| T249 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3230908223 |
|
|
Mar 28 03:57:42 PM PDT 24 |
Mar 28 04:53:01 PM PDT 24 |
11629405360 ps |
| T796 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2366564532 |
|
|
Mar 28 04:05:04 PM PDT 24 |
Mar 28 04:15:05 PM PDT 24 |
4493423556 ps |
| T797 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2664577241 |
|
|
Mar 28 04:04:11 PM PDT 24 |
Mar 28 04:10:15 PM PDT 24 |
3306511716 ps |
| T798 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1483447708 |
|
|
Mar 28 03:54:39 PM PDT 24 |
Mar 28 04:10:56 PM PDT 24 |
4287119622 ps |
| T252 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3135236265 |
|
|
Mar 28 03:48:35 PM PDT 24 |
Mar 28 03:53:51 PM PDT 24 |
2875411554 ps |
| T403 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1888763059 |
|
|
Mar 28 04:09:41 PM PDT 24 |
Mar 28 04:15:36 PM PDT 24 |
2937488548 ps |
| T404 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.1939903637 |
|
|
Mar 28 03:49:49 PM PDT 24 |
Mar 28 03:54:24 PM PDT 24 |
2747178928 ps |
| T405 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1051901775 |
|
|
Mar 28 03:47:53 PM PDT 24 |
Mar 28 03:56:19 PM PDT 24 |
5039475636 ps |
| T406 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.3910122833 |
|
|
Mar 28 03:51:00 PM PDT 24 |
Mar 28 03:55:56 PM PDT 24 |
2927781889 ps |
| T407 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.2464881065 |
|
|
Mar 28 03:45:33 PM PDT 24 |
Mar 28 03:48:43 PM PDT 24 |
2596918712 ps |
| T408 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1800857155 |
|
|
Mar 28 04:12:58 PM PDT 24 |
Mar 28 04:25:04 PM PDT 24 |
6548551964 ps |
| T409 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.3367665494 |
|
|
Mar 28 03:47:54 PM PDT 24 |
Mar 28 03:51:48 PM PDT 24 |
2726889020 ps |
| T137 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2958361448 |
|
|
Mar 28 03:47:47 PM PDT 24 |
Mar 28 03:53:54 PM PDT 24 |
5013607480 ps |
| T48 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2452867735 |
|
|
Mar 28 03:49:55 PM PDT 24 |
Mar 28 03:56:11 PM PDT 24 |
4568857192 ps |
| T799 |
/workspace/coverage/default/0.rom_e2e_smoke.3228584814 |
|
|
Mar 28 03:47:07 PM PDT 24 |
Mar 28 04:22:16 PM PDT 24 |
8447691256 ps |
| T800 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2939631060 |
|
|
Mar 28 04:08:59 PM PDT 24 |
Mar 28 04:21:46 PM PDT 24 |
13160307653 ps |
| T801 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.2332675825 |
|
|
Mar 28 04:06:27 PM PDT 24 |
Mar 28 04:12:07 PM PDT 24 |
3311467640 ps |
| T802 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3724810640 |
|
|
Mar 28 03:46:56 PM PDT 24 |
Mar 28 04:00:22 PM PDT 24 |
9282994808 ps |
| T803 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.446650892 |
|
|
Mar 28 03:48:57 PM PDT 24 |
Mar 28 04:12:54 PM PDT 24 |
8766353070 ps |
| T804 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.305899645 |
|
|
Mar 28 03:52:42 PM PDT 24 |
Mar 28 04:13:06 PM PDT 24 |
5939059340 ps |
| T805 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2044007935 |
|
|
Mar 28 03:50:06 PM PDT 24 |
Mar 28 03:57:30 PM PDT 24 |
6396683292 ps |
| T433 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3328145871 |
|
|
Mar 28 03:48:18 PM PDT 24 |
Mar 28 04:03:05 PM PDT 24 |
4822529416 ps |
| T806 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.2498992059 |
|
|
Mar 28 04:00:36 PM PDT 24 |
Mar 28 04:08:18 PM PDT 24 |
3912781128 ps |
| T59 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2593503511 |
|
|
Mar 28 03:36:34 PM PDT 24 |
Mar 28 04:23:25 PM PDT 24 |
21595720710 ps |
| T807 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3145135215 |
|
|
Mar 28 03:50:29 PM PDT 24 |
Mar 28 04:02:04 PM PDT 24 |
7638638648 ps |
| T50 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3283415324 |
|
|
Mar 28 03:46:02 PM PDT 24 |
Mar 28 03:50:24 PM PDT 24 |
3509937512 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.3065918463 |
|
|
Mar 28 03:46:34 PM PDT 24 |
Mar 28 04:18:20 PM PDT 24 |
8018746296 ps |
| T808 |
/workspace/coverage/default/0.chip_sw_aes_enc.3246892931 |
|
|
Mar 28 03:48:24 PM PDT 24 |
Mar 28 03:52:57 PM PDT 24 |
2206730456 ps |
| T809 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2738841228 |
|
|
Mar 28 03:45:16 PM PDT 24 |
Mar 28 03:54:04 PM PDT 24 |
5308714909 ps |
| T810 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3840887206 |
|
|
Mar 28 04:03:57 PM PDT 24 |
Mar 28 04:37:39 PM PDT 24 |
23815559193 ps |
| T317 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.327486796 |
|
|
Mar 28 03:47:26 PM PDT 24 |
Mar 28 04:47:56 PM PDT 24 |
12879494940 ps |
| T811 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2088622939 |
|
|
Mar 28 04:06:11 PM PDT 24 |
Mar 28 04:10:47 PM PDT 24 |
3421029568 ps |
| T812 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3104534266 |
|
|
Mar 28 04:06:50 PM PDT 24 |
Mar 28 04:18:07 PM PDT 24 |
7590281232 ps |
| T813 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2773010553 |
|
|
Mar 28 04:10:16 PM PDT 24 |
Mar 28 04:35:50 PM PDT 24 |
9500738304 ps |
| T814 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3948296836 |
|
|
Mar 28 04:06:51 PM PDT 24 |
Mar 28 04:14:04 PM PDT 24 |
5631733198 ps |
| T815 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.448601154 |
|
|
Mar 28 03:50:26 PM PDT 24 |
Mar 28 04:20:34 PM PDT 24 |
8932530304 ps |
| T447 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.878086706 |
|
|
Mar 28 04:07:18 PM PDT 24 |
Mar 28 04:16:43 PM PDT 24 |
5300811432 ps |
| T527 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2461464913 |
|
|
Mar 28 04:09:42 PM PDT 24 |
Mar 28 04:15:11 PM PDT 24 |
3197094480 ps |
| T510 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3342823729 |
|
|
Mar 28 04:14:16 PM PDT 24 |
Mar 28 04:25:21 PM PDT 24 |
5968077256 ps |
| T816 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.430798090 |
|
|
Mar 28 03:54:32 PM PDT 24 |
Mar 28 04:52:13 PM PDT 24 |
23477046585 ps |
| T817 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2966564834 |
|
|
Mar 28 04:03:47 PM PDT 24 |
Mar 28 04:12:10 PM PDT 24 |
5086096032 ps |
| T818 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2933212333 |
|
|
Mar 28 04:00:29 PM PDT 24 |
Mar 28 04:07:31 PM PDT 24 |
6643025158 ps |
| T528 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1970959985 |
|
|
Mar 28 04:12:51 PM PDT 24 |
Mar 28 04:19:10 PM PDT 24 |
3440922594 ps |
| T819 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1668296753 |
|
|
Mar 28 03:50:53 PM PDT 24 |
Mar 28 06:56:20 PM PDT 24 |
254200086580 ps |
| T820 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.2184112917 |
|
|
Mar 28 04:10:45 PM PDT 24 |
Mar 28 04:18:26 PM PDT 24 |
5171072534 ps |
| T821 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1309050272 |
|
|
Mar 28 03:45:59 PM PDT 24 |
Mar 28 04:13:46 PM PDT 24 |
7964727263 ps |
| T822 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1243922134 |
|
|
Mar 28 04:03:45 PM PDT 24 |
Mar 28 04:14:27 PM PDT 24 |
3464867400 ps |
| T516 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3565488537 |
|
|
Mar 28 04:08:20 PM PDT 24 |
Mar 28 04:13:29 PM PDT 24 |
3114169968 ps |