CHIP Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: `9f4903e77a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	3.689m	3.198ms	3	3	100.00
		chip_sw_example_rom	2.070m	2.311ms	3	3	100.00
		chip_sw_example_manufacturer	4.164m	2.904ms	3	3	100.00
		chip_sw_example_concurrency	4.142m	2.855ms	3	3	100.00
		chip_sw_uart_smoketest_signed			0	3	0.00
V1	csr_hw_reset	chip_csr_hw_reset			0	5	0.00
V1	csr_rw	chip_csr_rw			0	20	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	5	0.00
V1	csr_aliasing	chip_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	5	0.00
		chip_csr_rw			0	20	0.00
V1	xbar_smoke	xbar_smoke			0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.546m	3.479ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.546m	3.479ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.546m	3.479ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.752m	4.812ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.752m	4.812ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	11.740m	4.076ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.419m	4.343ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.465m	4.989ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	47.944m	13.446ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	29.818m	8.150ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	29.057m	13.974ms	5	5	100.00
V1		TOTAL			65	223	29.15
V2	chip_pin_mux	chip_padctrl_attributes	6.369m	5.715ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	6.369m	5.715ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.037m	3.267ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.571m	5.643ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.795m	4.215ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	22.667m	12.865ms	5	5	100.00
		chip_tap_straps_testunlock0	9.056m	5.737ms	5	5	100.00
		chip_tap_straps_rma	12.613m	7.178ms	5	5	100.00
		chip_tap_straps_prod	37.374m	17.856ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	6.029m	2.692ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	26.263m	9.086ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	12.514m	5.282ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	12.514m	5.282ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.158m	6.489ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	42.609m	18.081ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	10.132m	3.332ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.378m	6.390ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.061h	18.831ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.169m	2.274ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	21.093m	6.001ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.095m	3.238ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.509m	4.189ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.554m	3.021ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.464m	5.582ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.819m	3.143ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.427m	2.858ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	17.789m	7.898ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.732m	5.451ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.573m	3.393ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.732m	5.451ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	5.271m	3.227ms	3	3	100.00
		chip_sw_aes_smoketest	5.233m	2.731ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.008m	3.056ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.448m	3.413ms	3	3	100.00
		chip_sw_csrng_smoketest	3.958m	2.126ms	3	3	100.00
		chip_sw_entropy_src_smoketest	8.755m	3.225ms	3	3	100.00
		chip_sw_gpio_smoketest	5.429m	2.984ms	3	3	100.00
		chip_sw_hmac_smoketest	6.165m	3.321ms	3	3	100.00
		chip_sw_kmac_smoketest	5.605m	3.225ms	3	3	100.00
		chip_sw_otbn_smoketest	29.636m	8.300ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.235m	2.736ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.476m	4.804ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	7.042m	6.204ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.672m	2.812ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.301m	3.067ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.343m	2.716ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.730m	2.789ms	3	3	100.00
		chip_sw_uart_smoketest	5.044m	2.921ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.058m	5.432ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed			0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.772h	77.308ms	2	3	66.67
V2	chip_sw_secure_boot	rom_e2e_smoke			0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	5.013h	204.129ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	15.207m	4.301ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	9.877m	10.145ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.168h	59.088ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.342h	63.387ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	xbar_base_random_sequence	xbar_random			0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	100	0.00
		xbar_smoke_large_delays			0	100	0.00
		xbar_smoke_slow_rsp			0	100	0.00
		xbar_random_zero_delays			0	100	0.00
		xbar_random_large_delays			0	100	0.00
		xbar_random_slow_rsp			0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_error_cases	xbar_error_random			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	100	0.00
		xbar_access_same_device_slow_rsp			0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	100	0.00
V2	xbar_stress_all	xbar_stress_all			0	100	0.00
		xbar_stress_all_with_error			0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	100	0.00
		xbar_stress_all_with_reset_error			0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	57.108m	14.669ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	35.726m	9.076ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	49.282m	12.676ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	59.898m	11.917ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	58.113m	12.517ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	47.958m	12.428ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	36.444m	8.670ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	50.189m	12.386ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	51.901m	12.374ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	49.035m	12.185ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	49.120m	12.545ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	53.237m	13.372ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.206h	19.152ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.259h	18.924ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.345h	18.551ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.129h	19.186ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	53.805m	13.424ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.080h	17.402ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.125h	17.571ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.157h	17.796ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.080h	17.535ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	47.466m	10.248ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	1.086h	15.180ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.036h	14.474ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	57.715m	14.445ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	53.404m	14.713ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	37.752m	10.591ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.095h	14.583ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	55.772m	14.465ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	58.149m	15.282ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	47.435m	15.147ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	48.961m	10.550ms	3	3	100.00
		rom_e2e_asm_init_dev	1.076h	15.419ms	3	3	100.00
		rom_e2e_asm_init_prod	1.026h	15.496ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.090h	15.107ms	3	3	100.00
		rom_e2e_asm_init_rma	1.083h	15.138ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.106h	20.024ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.205m	3.231ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.169m	2.274ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.866m	2.746ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.535m	2.984ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	9.576m	5.000ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.375m	18.732ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.375m	18.732ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.204m	3.880ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.476m	4.804ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.204m	3.880ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.834m	7.338ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.834m	7.338ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.666m	6.737ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	9.573m	4.972ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.634m	5.893ms	3	3	100.00
		chip_sw_aes_idle	5.535m	2.984ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.908m	3.204ms	3	3	100.00
		chip_sw_kmac_idle	4.737m	3.570ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	8.906m	4.477ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.934m	5.761ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	9.092m	4.745ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.342m	5.571ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	17.416m	11.407ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.878m	4.447ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.841m	5.343ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.440m	3.951ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.873m	4.644ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.696m	3.579ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.363m	4.683ms	3	3	100.00
		chip_sw_ast_clk_outputs	16.158m	6.489ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.595m	9.716ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.440m	3.951ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.873m	4.644ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	10.132m	3.332ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.378m	6.390ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.061h	18.831ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.169m	2.274ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	21.093m	6.001ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.095m	3.238ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.509m	4.189ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.554m	3.021ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.464m	5.582ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.819m	3.143ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.521m	2.969ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.500m	5.226ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.111m	6.780ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.124h	25.063ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.495m	2.403ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.031m	3.435ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.996m	5.540ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	4.894m	3.758ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.092m	4.877ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	41.298m	26.713ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	51.455m	15.548ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.158m	6.489ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.521m	4.270ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	9.311m	3.415ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.788m	4.758ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	26.152m	7.614ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	30.275m	6.764ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.518m	4.062ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	13.518m	7.328ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.659m	3.592ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.556m	7.380ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	34.787m	23.055ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.433m	3.762ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	45.920s	10.140us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.196m	4.669ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	34.787m	23.055ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	34.787m	23.055ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	59.960m	20.688ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	59.960m	20.688ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	10.998m	5.810ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.375m	18.732ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	55.524m	14.417ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.460m	3.531ms	3	3	100.00
		chip_sw_edn_entropy_reqs	18.193m	4.790ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.460m	3.531ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	30.275m	6.764ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	3.805m	3.201ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	37.948m	21.498ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.844m	5.724ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.378m	6.390ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.087m	4.652ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	10.132m	3.332ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.443h	44.029ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	37.948m	21.498ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.099m	3.245ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	9.224m	4.402ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.056m	5.554ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.443h	44.029ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.056m	5.554ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.056m	5.554ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	10.056m	5.554ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.056m	5.554ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.788m	4.758ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	17.530m	6.057ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.352m	5.290ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.352m	5.290ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.399m	2.856ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.095m	3.238ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.908m	3.204ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.667m	4.949ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	14.696m	5.762ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.185m	5.287ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.778m	4.103ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	9.224m	4.402ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.509m	4.189ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	8.022m	5.059ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	9.576m	5.000ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.004h	13.336ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	6.734m	2.575ms	3	3	100.00
		chip_sw_kmac_mode_kmac	7.380m	3.247ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.554m	3.021ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	9.224m	4.402ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	17.868m	13.755ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.963m	2.782ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.079m	2.593ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.737m	3.570ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.073m	4.496ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	22.667m	12.865ms	5	5	100.00
		chip_tap_straps_rma	12.613m	7.178ms	5	5	100.00
		chip_tap_straps_prod	37.374m	17.856ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.308m	2.311ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	17.868m	13.755ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	17.868m	13.755ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	17.868m	13.755ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.110m	5.556ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	10.056m	5.554ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.443h	44.029ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.219m	4.479ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.663m	8.278ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	20.261m	8.450ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.448m	9.776ms	3	3	100.00
		chip_sw_lc_ctrl_transition	17.868m	13.755ms	15	15	100.00
		chip_sw_keymgr_key_derivation	9.224m	4.402ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.459m	8.989ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	15.332m	9.221ms	3	3	100.00
		chip_prim_tl_access			0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.595m	9.716ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.878m	4.447ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.841m	5.343ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.440m	3.951ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.873m	4.644ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.696m	3.579ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.363m	4.683ms	3	3	100.00
		chip_tap_straps_dev	22.667m	12.865ms	5	5	100.00
		chip_tap_straps_rma	12.613m	7.178ms	5	5	100.00
		chip_tap_straps_prod	37.374m	17.856ms	5	5	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.767m	2.466ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.973m	3.759ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.722m	3.485ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.486m	3.833ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	38.972m	33.571ms	2	3	66.67
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.638h	49.882ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.755h	48.259ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	22.126m	10.793ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.526h	45.278ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	38.972m	33.571ms	2	3	66.67
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.256m	2.253ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.131m	2.341ms	3	3	100.00
		rom_volatile_raw_unlock	1.992m	1.930ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	17.868m	13.755ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	37.948m	21.498ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.122m	4.132ms	3	3	100.00
		chip_sw_keymgr_key_derivation	9.224m	4.402ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.953m	5.340ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.267m	2.494ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	37.948m	21.498ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.122m	4.132ms	3	3	100.00
		chip_sw_keymgr_key_derivation	9.224m	4.402ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.953m	5.340ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.267m	2.494ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	17.868m	13.755ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	21.904m	14.555ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.308m	2.311ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.219m	4.479ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.663m	8.278ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	20.261m	8.450ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.448m	9.776ms	3	3	100.00
		chip_sw_lc_ctrl_transition	17.868m	13.755ms	15	15	100.00
		chip_prim_tl_access			0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.885m	9.677ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	27.960m	22.048ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.708m	7.487ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	15.692m	9.029ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	10.759m	8.045ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	31.437m	22.386ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	28.675m	16.087ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	14.834m	7.338ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	27.933m	10.499ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.877m	5.070ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.885m	9.677ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	7.125m	4.577ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.007h	31.525ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.647m	7.119ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	8.712m	6.595ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	34.596m	19.354ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.556m	7.380ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	27.624m	11.809ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	46.687m	29.628ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.908m	3.050ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.788m	4.758ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.459m	8.989ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.459m	8.989ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	27.624m	11.809ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	34.596m	19.354ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	10.877m	5.070ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.476m	4.804ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	9.379m	5.228ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	10.825m	5.594ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.862m	3.384ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.878m	13.900ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.443m	2.765ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.788m	4.758ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	29.015m	8.527ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	23.472m	6.136ms	3	3	100.00
		chip_plic_all_irqs_10	10.701m	3.818ms	3	3	100.00
		chip_plic_all_irqs_20	14.034m	4.160ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.173m	2.235ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.900m	2.445ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.461m	7.184ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.117m	4.073ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.287m	3.028ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.713m	2.999ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.953m	5.340ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.464m	5.582ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	10.330m	8.386ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	11.936m	8.183ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	15.332m	9.221ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.788m	4.758ms	97	100	97.00
		chip_sw_data_integrity_escalation	12.514m	5.282ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.234m	2.341ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.156m	3.267ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.341m	3.459ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	8.105m	3.866ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	30.283m	8.468ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.920h	31.612ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	50.616m	12.241ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	4.979m	2.879ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.073m	4.496ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.788m	4.758ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.718m	2.939ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.878m	13.900ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.048m	5.226ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.544m	3.775ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	26.201m	12.202ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	26.152m	7.614ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	29.015m	8.527ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.598h	254.835ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	28.837m	12.251ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	25.774m	13.575ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	9.379m	5.228ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.785m	5.380ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.887m	3.785ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	12.613m	7.178ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			832	2657	31.31
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.136m	3.149ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.776h	51.192ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.957m	5.319ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.228m	2.839ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.569m	2.355ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.147m	2.416ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.100h	41.386ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.218h	40.365ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.120h	50.532ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.944m	3.582ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.818m	3.178ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	21.420m	4.269ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	42.814m	10.664ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.848m	3.460ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	20.391m	5.551ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.201m	2.595ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.811m	6.157ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.079m	23.367ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	6.994m	5.027ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	27.624m	11.809ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.788m	4.758ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.752m	4.812ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.222h	19.103ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.228m	2.839ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.569m	2.355ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.147m	2.416ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.739m	5.954ms	3	3	100.00
V3		TOTAL			30	45	66.67
	Unmapped tests	chip_sival_flash_info_access	5.689m	3.386ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	10.662m	5.411ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	58.217m	16.882ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	18.725m	5.558ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	17.329m	4.131ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.131m	6.761ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.058m	2.773ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.500m	2.804ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			954	2955	32.28

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	12	63.16
V2	290	276	229	78.97
V2S	1	1	1	100.00
V3	91	21	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.96	89.80	79.30	90.01	--	91.93	97.38	85.31

Failure Buckets

launch_task.returncode != *, err: Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.85957409100876790363106251249829587212658581458086738809279024944872954450432
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
  - 2.chip_csr_bit_bash.14807588749659774709581797776492272467318138444950656185368945088389826763915
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.60016006289156336060890986966901979513051300284642815939040388222456468778011
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
  - 2.chip_same_csr_outstanding.40651407968075583666812936702857247405742927143808090896423604714077653044826
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
  - ... and 1 more failures.
- Test chip_prim_tl_access has 2 failures.
  - 0.chip_prim_tl_access.94550259947751364846116264563193859828489917159061421214007614117919952689719
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
  - 2.chip_prim_tl_access.115247481232755320539243573007547321455898490372578548671118794007149341839726
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
- Test xbar_smoke has 8 failures.
  - 0.xbar_smoke.13375858131018375817524209304295432882165129812345964126763363399088172195007
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
  - 2.xbar_smoke.20984795797797235765107450212795151431676794360351555969066351778298319297469
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
  - ... and 6 more failures.
- Test xbar_smoke_large_delays has 8 failures.
  - 0.xbar_smoke_large_delays.97472499758531291851407307762939305538566929850495785766185027393894150196742
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
  - 2.xbar_smoke_large_delays.67978511835864928209431787198876714971182144854657160221160990016603947035162
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
  - ... and 6 more failures.
- ... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.41823748737945680296634658674219596435844125999089397909905650302661382112241
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
  - 2.chip_csr_aliasing.3680292609742928601608132175265046015639808020711295635385647708216601079268
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
  - ... and 1 more failures.
- Test chip_tl_errors has 8 failures.
  - 0.chip_tl_errors.82058032382621175905954590930090594506773125709026416625362443692530832611298
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
  - 2.chip_tl_errors.94726850133704917467261535661345196659097408402018273163678239208376835500079
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
  - ... and 6 more failures.
- Test chip_rv_dm_lc_disabled has 2 failures.
  - 0.chip_rv_dm_lc_disabled.107201948156464727446133378123494175886269936738096763449272250828873080498762
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
  - 2.chip_rv_dm_lc_disabled.37160782060841806375945284863478705601041440931599755050960421015839822809121
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
- Test xbar_smoke_zero_delays has 8 failures.
  - 0.xbar_smoke_zero_delays.59147701862105855063746621039423836139528558948117723159349942420260573788258
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
  - 2.xbar_smoke_zero_delays.96971570449956805115784119702935945266771171507717394444416682345681225423931
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
  - ... and 6 more failures.
- Test xbar_smoke_slow_rsp has 8 failures.
  - 0.xbar_smoke_slow_rsp.7895650894209876393084913966772966936866691171692452821631106932665114335710
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
  - 2.xbar_smoke_slow_rsp.72709422969479580663348022511799737775666082322234727327452031183699222254602
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
  - ... and 6 more failures.
- ... and 22 more tests.

Exit reason: Error: User command failed Job returned non-zero exit code has 45 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.62135836239488769233127184236770932960867831348748988563741545122624284843951
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:37:01) Loading:
  (15:37:02) Loading:
  (15:37:02) Loading: 4 packages loaded
  (15:37:02) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:37:02) WARNING: Target pattern parsing failed.
  (15:37:02) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:37:02) INFO: Elapsed time: 20.364s
  (15:37:02) INFO: 0 processes.
  (15:37:02) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.109713161074362836614664045807643090340399371363019570956475498547689816029259
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:51:32) Loading:
  (15:51:33) Loading:
  (15:51:33) Loading: 4 packages loaded
  (15:51:33) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:51:33) WARNING: Target pattern parsing failed.
  (15:51:33) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:51:33) INFO: Elapsed time: 18.132s
  (15:51:33) INFO: 0 processes.
  (15:51:33) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.20702279462006950258339990406780877453779621527031933414280943901815305903730
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:39:09) Loading:
  (15:39:10) Loading:
  (15:39:10) Loading: 4 packages loaded
  (15:39:10) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:39:10) WARNING: Target pattern parsing failed.
  (15:39:10) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:39:10) INFO: Elapsed time: 66.663s
  (15:39:10) INFO: 0 processes.
  (15:39:10) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.92694784717421446032775280905758539272172289393005404296214004678641626038881
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:53:52) Loading:
  (15:53:53) Loading:
  (15:53:53) Loading: 4 packages loaded
  (15:53:53) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:53:53) WARNING: Target pattern parsing failed.
  (15:53:53) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:53:53) INFO: Elapsed time: 40.634s
  (15:53:53) INFO: 0 processes.
  (15:53:53) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.95018443160114369331378418743237031414495751742467233727668853422717992880160
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:38:36) Loading:
  (15:38:37) Loading:
  (15:38:37) Loading: 4 packages loaded
  (15:38:37) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:38:37) WARNING: Target pattern parsing failed.
  (15:38:37) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:38:37) INFO: Elapsed time: 31.209s
  (15:38:37) INFO: 0 processes.
  (15:38:37) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.86103722263492285825227205999292447418451515946002378401768966395893268529331
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:52:30) Loading:
  (15:52:31) Loading:
  (15:52:31) Loading: 4 packages loaded
  (15:52:31) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:52:31) WARNING: Target pattern parsing failed.
  (15:52:31) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:52:31) INFO: Elapsed time: 19.204s
  (15:52:31) INFO: 0 processes.
  (15:52:31) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.61229424441696491369240450774749027376358910314826245655253263060493758786744
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:39:10) Loading:
  (15:39:11) Loading:
  (15:39:11) Loading: 4 packages loaded
  (15:39:11) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:39:11) WARNING: Target pattern parsing failed.
  (15:39:11) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:39:11) INFO: Elapsed time: 59.961s
  (15:39:11) INFO: 0 processes.
  (15:39:11) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.7174838057142285956025064100499749203109103404765026975083335629851484625762
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:52:31) Loading:
  (15:52:32) Loading:
  (15:52:32) Loading: 4 packages loaded
  (15:52:32) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:52:32) WARNING: Target pattern parsing failed.
  (15:52:32) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:52:32) INFO: Elapsed time: 19.633s
  (15:52:32) INFO: 0 processes.
  (15:52:32) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.42990198428404939089645246352064512159958911076638838219791793125955976991611
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:38:51) Loading:
  (15:38:52) Loading:
  (15:38:52) Loading: 4 packages loaded
  (15:38:53) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:38:53) WARNING: Target pattern parsing failed.
  (15:38:53) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:38:53) INFO: Elapsed time: 36.642s
  (15:38:53) INFO: 0 processes.
  (15:38:53) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.79397078633962906225212193313887821773069495993277594727772331979227749871584
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:52:33) Loading:
  (15:52:33) Loading:
  (15:52:33) Loading: 4 packages loaded
  (15:52:33) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:52:33) WARNING: Target pattern parsing failed.
  (15:52:33) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:52:33) INFO: Elapsed time: 17.400s
  (15:52:33) INFO: 0 processes.
  (15:52:33) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 10 more tests.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test chip_sw_lc_walkthrough_testunlocks has 1 failures.
  - 0.chip_sw_lc_walkthrough_testunlocks.75811128845547206353305453346261072584228782608374952911793732077927920745344
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  Job ID: smart:8496bfdf-fbec-4484-9f5e-43bc68c1d658
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.62702826881527653250463210437154054671966093889555435752777084440085599120047
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:cf00ee36-0dde-4315-ada9-94706cb54bbe
```
  - 1.chip_sw_rv_timer_systick_test.69697787598786976682981322925576792382274667680549930650731579018140233976609
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:d19dd10d-e3ee-4eaf-8082-ec49db315382
```
  - ... and 1 more failures.
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.115195108248568050380345528480718766586764763768361961144495142503220433056517
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:5d91f7cd-098b-4cdf-bd22-4c7401ed45fa
```
- Test rom_e2e_smoke has 3 failures.
  - 0.rom_e2e_smoke.18553348403328026296558420841405057145283358123393971110568276536208465726405
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log
```
  Job ID: smart:4747bc64-2ca9-4af5-ac5e-bfc6a03a749c
```
  - 1.rom_e2e_smoke.102051789007751090272169911074244929623807695085862195595382732612750356190558
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log
```
  Job ID: smart:4dd7180a-0f59-4106-ab73-5f6954a24cb7
```
  - ... and 1 more failures.
- Test rom_e2e_shutdown_output has 3 failures.
  - 0.rom_e2e_shutdown_output.30317066150649212702578196459297285860254789902386070979084714042213941234937
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
  Job ID: smart:4ba2a294-4d0c-4e5d-91c2-58bfb0ecc103
```
  - 1.rom_e2e_shutdown_output.83148078360455375577889053956654041601241534802437012556943093321331723104304
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
```
  Job ID: smart:8549653f-a459-4114-877d-de8f91ed1561
```
  - ... and 1 more failures.
- ... and 2 more tests.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.84845775887561080572273567587116029298137090412200954323282150448360852323579
    Line 783, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.28509501038012838150062634176493757293408977503849506786252293776845278537632
    Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.81919917520677517388314322535167357148233910844761834094546625341553559030613
    Line 837, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15248.113824 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15248.113824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.83931044319246224637959830139255508692869472310822525900361498557935056414925
    Line 817, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14554.744112 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14554.744112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.73282175538515280251346949832884596165411952840664111634506453977070431452040
    Line 799, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 22888.671504 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 22888.671504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.93031667617979302399871118758500939236755240820679431402134967034752765156693
    Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23367.439728 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23367.439728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.12371677143688263039434463660668053981037576482246309807348158813153272213061
    Line 884, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 4207.238347 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 4207.238347 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.57570067183965826172005732104866372576022699783698479881312996542866536594431
    Line 760, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3785.417360 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3785.417360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.9253768041923401660779194148326450310691265942430856208574931368537206197713
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2839.097500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2839.097500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.108543665776109706753301602158269918651253454128402813880795683693510886783437
    Line 728, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2354.605500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2354.605500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.60473589526204511379956804193896479061372897492870350572126123874062718276733
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2416.405500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2416.405500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.23010681565162542046588172466694891134518243616560818629057599069416534530291
    Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 41386.456912 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 41386.456912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.51378673171709684816312050062462209018362963113615377438504112025142934288423
    Line 830, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 40365.249509 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40365.249509 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.4435932714807432278000016658209155360092785056067179368877753659293693701006
    Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 50531.808639 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50531.808639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.85723714315242408909608278142099758816180208390672697233971627859853470875465
    Line 976, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20024.383073 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20024.383073 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.rom_e2e_static_critical.74596153181034004388693370960732909875276601385542445622723756137055163020516
    Line 979, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20014.959313 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20014.959313 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.94230829890600359213387510773015498680338542480979552675219199460585156850011
Line 810, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 204129.078156 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 204129.078156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.38423121160507805586119555343100369173360828717728784525965995583646760257749
Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 206233.313703 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 206233.313703 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 43.chip_sw_all_escalation_resets.90804938026958381513094523824333761635266889136347607758698945250772724765102
    Line 869, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3498.236584 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3498.236584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.chip_sw_all_escalation_resets.4667384835320368602415135039892497557255738943811552667194066538254982887536
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2537.135738 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2537.135738 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 54.chip_sw_alert_handler_lpg_sleep_mode_alerts.110109746824148461555455567838264005678401068003644348177910269224229859215616
    Line 822, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3245.925484 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3245.925484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 87.chip_sw_alert_handler_lpg_sleep_mode_alerts.69310326684593452786765851991177836245190694362832904616829202065646328769096
    Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3777.121120 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3777.121120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.112044669743192237273646721276159767064097558486669111284595579507512135265771
    Line 1063, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5318.873813 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 5318.873813 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.11077153835618728497561275567521005170255627243339929570573760217544960113596
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 5997.576000 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 5997.576000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```