CHIP Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.686m	2.844ms	3	3	100.00
		chip_sw_example_rom	2.542m	2.417ms	3	3	100.00
		chip_sw_example_manufacturer	5.307m	2.801ms	3	3	100.00
		chip_sw_example_concurrency	5.088m	2.352ms	3	3	100.00
		chip_sw_uart_smoketest_signed	38.341m	9.445ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	8.594m	7.507ms	5	5	100.00
V1	csr_rw	chip_csr_rw	12.271m	5.327ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	23.885m	13.059ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.507h	56.574ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.483m	2.632ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.507h	56.574ms	5	5	100.00
		chip_csr_rw	12.271m	5.327ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.390s	251.914us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.317m	3.829ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.317m	3.829ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.317m	3.829ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	16.191m	5.754ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	16.191m	5.754ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	14.744m	5.504ms	4	5	80.00
		chip_sw_uart_tx_rx_idx2	14.553m	5.442ms	4	5	80.00
		chip_sw_uart_tx_rx_idx3	17.771m	5.415ms	4	5	80.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.114h	23.171ms	14	20	70.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	38.563m	14.245ms	4	5	80.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	43.192m	22.768ms	3	5	60.00
V1		TOTAL			191	223	85.65
V2	chip_pin_mux	chip_padctrl_attributes	5.200m	4.868ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.200m	4.868ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	7.049m	2.860ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	8.831m	6.296ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.649m	4.512ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	20.892m	11.286ms	5	5	100.00
		chip_tap_straps_testunlock0	19.121m	10.100ms	5	5	100.00
		chip_tap_straps_rma	11.908m	6.921ms	5	5	100.00
		chip_tap_straps_prod	33.687m	16.342ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.316m	3.351ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	27.011m	8.267ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	12.616m	5.207ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	12.616m	5.207ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.663m	6.795ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	31.781m	15.080ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.794m	4.328ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.541m	5.920ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.036h	18.988ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.889m	3.011ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	22.929m	5.771ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.228m	2.172ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.979m	4.959ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.007m	3.184ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.995m	4.303ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.683m	2.794ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.968m	2.667ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	16.986m	8.443ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.119m	5.534ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	6.458m	3.262ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.119m	5.534ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	5.522m	3.108ms	3	3	100.00
		chip_sw_aes_smoketest	4.280m	2.619ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.116m	3.253ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.197m	3.179ms	3	3	100.00
		chip_sw_csrng_smoketest	4.858m	3.267ms	3	3	100.00
		chip_sw_entropy_src_smoketest	9.466m	3.555ms	3	3	100.00
		chip_sw_gpio_smoketest	5.065m	2.128ms	3	3	100.00
		chip_sw_hmac_smoketest	7.897m	3.329ms	3	3	100.00
		chip_sw_kmac_smoketest	6.808m	3.262ms	3	3	100.00
		chip_sw_otbn_smoketest	38.610m	11.826ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.662m	2.930ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.758m	5.459ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	7.402m	5.959ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.923m	2.329ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.777m	2.822ms	3	3	100.00
		chip_sw_rstmgr_smoketest	6.037m	2.527ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.253m	2.862ms	3	3	100.00
		chip_sw_uart_smoketest	5.774m	2.808ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	10.119m	5.442ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	38.341m	9.445ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.781h	79.301ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke	38.549m	8.656ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	38.830m	16.925ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	10.979m	4.234ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.507m	10.761ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.225h	58.455ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.538h	64.243ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	10.693m	5.396ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	10.693m	5.396ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.507h	56.574ms	5	5	100.00
		chip_same_csr_outstanding	1.059h	31.556ms	20	20	100.00
		chip_csr_hw_reset	8.594m	7.507ms	5	5	100.00
		chip_csr_rw	12.271m	5.327ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.507h	56.574ms	5	5	100.00
		chip_same_csr_outstanding	1.059h	31.556ms	20	20	100.00
		chip_csr_hw_reset	8.594m	7.507ms	5	5	100.00
		chip_csr_rw	12.271m	5.327ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.933m	2.667ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.000s	56.157us	100	100	100.00
		xbar_smoke_large_delays	2.046m	10.377ms	100	100	100.00
		xbar_smoke_slow_rsp	2.154m	6.933ms	100	100	100.00
		xbar_random_zero_delays	1.047m	660.830us	100	100	100.00
		xbar_random_large_delays	21.210m	109.542ms	100	100	100.00
		xbar_random_slow_rsp	21.367m	67.097ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.129m	1.406ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.010m	1.315ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.784m	2.459ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.010m	1.315ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.758m	3.660ms	100	100	100.00
		xbar_access_same_device_slow_rsp	50.539m	173.225ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.663m	2.739ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.276m	17.669ms	100	100	100.00
		xbar_stress_all_with_error	12.231m	21.258ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	18.604m	10.068ms	100	100	100.00
		xbar_stress_all_with_reset_error	16.577m	21.538ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.549m	8.656ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	52.344m	23.906ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.468m	8.039ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	27.412m	7.262ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	33.912m	8.151ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	34.355m	8.897ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	36.453m	8.979ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	28.836m	8.532ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	30.109m	6.797ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	37.951m	8.971ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	37.324m	8.992ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	37.137m	8.271ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	43.342m	8.906ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	46.858m	9.867ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	55.386m	11.624ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	51.298m	11.938ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	56.746m	11.929ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	47.803m	11.525ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	49.742m	10.021ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	57.287m	11.417ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	56.210m	11.975ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	49.037m	11.593ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	52.106m	12.085ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.700m	7.660ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	41.581m	9.171ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	33.805m	8.477ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	37.544m	8.610ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	39.098m	9.405ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	30.498m	6.737ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	32.002m	8.939ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	36.304m	8.767ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	33.910m	8.358ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	31.610m	8.880ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	25.948m	7.044ms	3	3	100.00
		rom_e2e_asm_init_dev	34.640m	8.870ms	3	3	100.00
		rom_e2e_asm_init_prod	38.414m	8.781ms	3	3	100.00
		rom_e2e_asm_init_prod_end	35.262m	8.616ms	3	3	100.00
		rom_e2e_asm_init_rma	37.790m	8.489ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	45.332m	11.306ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.183m	2.535ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.889m	3.011ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.555m	2.870ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.741m	3.316ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	9.650m	4.089ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.968m	19.170ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.968m	19.170ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.350m	3.830ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.758m	5.459ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.350m	3.830ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.172m	7.832ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.172m	7.832ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.562m	6.740ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.479m	5.491ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.583m	5.890ms	3	3	100.00
		chip_sw_aes_idle	4.741m	3.316ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.556m	3.210ms	3	3	100.00
		chip_sw_kmac_idle	5.227m	2.777ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.636m	5.291ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.691m	4.368ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.845m	4.178ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.673m	5.287ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	29.111m	12.164ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.288m	3.745ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.049m	4.908ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.376m	4.022ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.089m	4.447ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.598m	4.139ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	8.875m	4.103ms	3	3	100.00
		chip_sw_ast_clk_outputs	16.663m	6.795ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.987m	10.970ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.376m	4.022ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.089m	4.447ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.794m	4.328ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.541m	5.920ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.036h	18.988ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.889m	3.011ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	22.929m	5.771ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.228m	2.172ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.979m	4.959ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.007m	3.184ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.995m	4.303ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.683m	2.794ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.792m	2.811ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.381m	4.647ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.767m	7.084ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.247h	24.386ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.351m	3.476ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.790m	3.596ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.098m	4.710ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.728m	3.669ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	14.304m	5.961ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	34.034m	27.511ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.361h	29.961ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.663m	6.795ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.249m	4.922ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.906m	3.855ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.195m	5.771ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	32.212m	8.356ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	24.782m	6.753ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	9.446m	4.199ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	12.040m	6.350ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.041m	3.286ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.349m	7.544ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	27.197m	22.686ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.092m	2.868ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	43.880s	10.120us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.508m	4.362ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	27.197m	22.686ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	27.197m	22.686ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	57.992m	19.972ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	57.992m	19.972ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	7.265m	4.475ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.968m	19.170ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	54.578m	14.027ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.241m	2.684ms	3	3	100.00
		chip_sw_edn_entropy_reqs	19.911m	5.919ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.241m	2.684ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	24.782m	6.753ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.670m	2.275ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	34.230m	24.615ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	19.028m	5.989ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.541m	5.920ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.921m	4.565ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.794m	4.328ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.573h	44.286ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	34.230m	24.615ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.636m	3.852ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	10.960m	5.263ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.687m	3.831ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.573h	44.286ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.687m	3.831ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.687m	3.831ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	9.687m	3.831ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.687m	3.831ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.195m	5.771ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	7.109m	10.843ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	18.917m	5.269ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	11.942m	5.610ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	11.942m	5.610ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.390m	2.927ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.228m	2.172ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.556m	3.210ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.012m	5.757ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	13.627m	5.740ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.326m	4.734ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.584m	3.518ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	10.960m	5.263ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.979m	4.959ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	9.588m	4.968ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	9.650m	4.089ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.166h	17.327ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.628m	2.720ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.337m	3.574ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.007m	3.184ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	10.960m	5.263ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.874m	13.646ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.409m	2.981ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.660m	3.585ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.227m	2.777ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	8.873m	4.786ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	20.892m	11.286ms	5	5	100.00
		chip_tap_straps_rma	11.908m	6.921ms	5	5	100.00
		chip_tap_straps_prod	33.687m	16.342ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.059m	3.063ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.874m	13.646ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.874m	13.646ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.874m	13.646ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.409m	4.843ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	9.687m	3.831ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.573h	44.286ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.473m	4.398ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.252m	9.819ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.515m	9.467ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.254m	7.581ms	3	3	100.00
		chip_sw_lc_ctrl_transition	21.874m	13.646ms	15	15	100.00
		chip_sw_keymgr_key_derivation	10.960m	5.263ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	8.091m	9.904ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	15.400m	9.020ms	3	3	100.00
		chip_prim_tl_access	7.109m	10.843ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.987m	10.970ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.288m	3.745ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.049m	4.908ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.376m	4.022ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.089m	4.447ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.598m	4.139ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	8.875m	4.103ms	3	3	100.00
		chip_tap_straps_dev	20.892m	11.286ms	5	5	100.00
		chip_tap_straps_rma	11.908m	6.921ms	5	5	100.00
		chip_tap_straps_prod	33.687m	16.342ms	5	5	100.00
		chip_rv_dm_lc_disabled	7.022m	7.677ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.746m	3.193ms	0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	2.310m	2.673ms	0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.218m	3.751ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.828m	3.543ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	33.160m	34.253ms	2	3	66.67
		chip_rv_dm_lc_disabled	7.022m	7.677ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.656h	49.409ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.755h	48.451ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	18.844m	9.901ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.458h	49.417ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	33.160m	34.253ms	2	3	66.67
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.332m	3.009ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.997m	2.601ms	3	3	100.00
		rom_volatile_raw_unlock	2.101m	2.367ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.874m	13.646ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	34.230m	24.615ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.365m	3.481ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.960m	5.263ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.578m	5.099ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.135m	3.235ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	34.230m	24.615ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.365m	3.481ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.960m	5.263ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.578m	5.099ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.135m	3.235ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.874m	13.646ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	16.134m	14.627ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.059m	3.063ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.473m	4.398ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.252m	9.819ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.515m	9.467ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.254m	7.581ms	3	3	100.00
		chip_sw_lc_ctrl_transition	21.874m	13.646ms	15	15	100.00
		chip_prim_tl_access	7.109m	10.843ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.109m	10.843ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.946m	7.682ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	32.343m	21.449ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.458m	6.407ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.954m	7.707ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	10.099m	5.306ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	34.021m	24.343ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	29.190m	14.122ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	15.172m	7.832ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	25.441m	13.152ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.241m	3.983ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.946m	7.682ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.335m	3.918ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	53.180m	37.197ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.310m	6.767ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	8.625m	5.273ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	39.432m	19.944ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.349m	7.544ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	29.491m	9.992ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	42.721m	28.144ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.568m	3.187ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.195m	5.771ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.091m	9.904ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.091m	9.904ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	29.491m	9.992ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	39.432m	19.944ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	10.241m	3.983ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.758m	5.459ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.971m	3.816ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	13.675m	5.062ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.774m	4.026ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	30.390m	13.341ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.466m	2.383ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.195m	5.771ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	32.739m	7.782ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.856m	6.642ms	3	3	100.00
		chip_plic_all_irqs_10	12.158m	3.480ms	3	3	100.00
		chip_plic_all_irqs_20	13.896m	4.474ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.367m	2.930ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.150m	3.247ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	38.549m	8.656ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.004m	7.367ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.687m	4.868ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.692m	3.674ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.544m	3.346ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.578m	5.099ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.995m	4.303ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	15.323m	9.193ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.020m	7.629ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	15.400m	9.020ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.195m	5.771ms	97	100	97.00
		chip_sw_data_integrity_escalation	12.616m	5.207ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.178m	2.720ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.829m	3.573ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.596m	3.360ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	7.610m	4.232ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	32.310m	8.423ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.969h	31.350ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	50.526m	11.997ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.141m	3.181ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	8.873m	4.786ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.195m	5.771ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.970m	3.260ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	30.390m	13.341ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.690m	4.745ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.480m	3.581ms	86	90	95.56
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	26.205m	11.033ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	32.212m	8.356ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	32.739m	7.782ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.690h	255.226ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	30.193m	11.804ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	26.544m	13.624ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.971m	3.816ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	8.996m	5.783ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.433m	3.354ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	11.908m	6.921ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	7.022m	7.677ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2592	2657	97.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.208m	3.423ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.949m	4.592ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.644m	2.348ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.728m	2.829ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.869m	2.416ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.141h	38.162ms	0	1	0.00
		rom_e2e_jtag_inject_dev	51.511m	51.061ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.145h	42.362ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	6.634m	2.946ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.567m	3.277ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	24.749m	4.659ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	33.582m	8.442ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.982m	3.563ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.367m	5.319ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.295m	2.837ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.298m	5.692ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.530m	23.302ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.503m	4.245ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	29.491m	9.992ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.195m	5.771ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	16.191m	5.754ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.236h	19.188ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.644m	2.348ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.728m	2.829ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.869m	2.416ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.817m	5.766ms	3	3	100.00
V3		TOTAL			29	45	64.44
	Unmapped tests	chip_sival_flash_info_access	5.258m	2.771ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	14.268m	5.174ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.014h	16.754ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	18.560m	6.188ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	14.919m	5.216ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.813m	6.243ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	6.168m	3.327ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.290m	2.416ms	2	3	66.67
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2838	2955	96.04

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	7	77.78
V1	19	19	12	63.16
V2	290	276	252	86.90
V2S	1	1	1	100.00
V3	91	21	11	12.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.19	95.38	94.18	95.66	--	94.94	97.38	99.58

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.113773099639032936737813088411780889501181612614827300073442068727649582598507
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:37:13) Loading:
  (15:37:14) Loading:
  (15:37:14) Loading: 4 packages loaded
  (15:37:14) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:37:14) WARNING: Target pattern parsing failed.
  (15:37:14) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:37:14) INFO: Elapsed time: 24.458s
  (15:37:14) INFO: 0 processes.
  (15:37:14) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.16798909314132035018208169403519745179630724451097577030585989254063466200882
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:43:57) Loading:
  (15:43:58) Loading:
  (15:43:58) Loading: 4 packages loaded
  (15:43:58) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:43:58) WARNING: Target pattern parsing failed.
  (15:43:58) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:43:58) INFO: Elapsed time: 77.764s
  (15:43:58) INFO: 0 processes.
  (15:43:58) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.57911725188653720433194065796365011161076955891472171936592101669008771976030
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:37:15) Loading:
  (15:37:16) Loading:
  (15:37:16) Loading: 4 packages loaded
  (15:37:16) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:16) WARNING: Target pattern parsing failed.
  (15:37:16) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:16) INFO: Elapsed time: 22.636s
  (15:37:16) INFO: 0 processes.
  (15:37:16) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.26300994285466600549403509943053956263527517557722554333540628243139615002561
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:46:38) Loading:
  (15:46:38) Loading:
  (15:46:38) Loading: 4 packages loaded
  (15:46:39) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:46:39) WARNING: Target pattern parsing failed.
  (15:46:39) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:46:39) INFO: Elapsed time: 88.331s
  (15:46:39) INFO: 0 processes.
  (15:46:39) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.48471064114067864167721578327333064341221432880939246610980416148413419073625
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:37:13) Loading:
  (15:37:14) Loading:
  (15:37:14) Loading: 4 packages loaded
  (15:37:14) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:14) WARNING: Target pattern parsing failed.
  (15:37:14) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:14) INFO: Elapsed time: 21.498s
  (15:37:14) INFO: 0 processes.
  (15:37:14) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.14555402028225843314661188923276961268356754887691147075486688679662487307384
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:44:54) Loading:
  (15:44:54) Loading:
  (15:44:55) Loading: 4 packages loaded
  (15:44:55) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:44:55) WARNING: Target pattern parsing failed.
  (15:44:55) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:44:55) INFO: Elapsed time: 52.911s
  (15:44:55) INFO: 0 processes.
  (15:44:55) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.92670095570886405110775837978895041930476079750648048821367293720446620750148
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:37:12) Loading:
  (15:37:13) Loading:
  (15:37:13) Loading: 4 packages loaded
  (15:37:13) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:13) WARNING: Target pattern parsing failed.
  (15:37:13) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:37:13) INFO: Elapsed time: 19.414s
  (15:37:13) INFO: 0 processes.
  (15:37:13) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.695841427250163982488822556130852979028253792157008067077407916557254883544
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:46:45) Loading:
  (15:46:46) Loading:
  (15:46:46) Loading: 4 packages loaded
  (15:46:46) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:46:46) WARNING: Target pattern parsing failed.
  (15:46:46) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:46:46) INFO: Elapsed time: 86.543s
  (15:46:46) INFO: 0 processes.
  (15:46:46) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.18447917698144188561468874517597882614203912685853677349474368199106847053446
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:37:14) Loading:
  (15:37:15) Loading:
  (15:37:15) Loading: 4 packages loaded
  (15:37:15) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:37:15) WARNING: Target pattern parsing failed.
  (15:37:15) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:37:15) INFO: Elapsed time: 19.239s
  (15:37:15) INFO: 0 processes.
  (15:37:15) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.86022266898989632019176267483804921816069988180773006915719085337473923277491
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:45:24) Loading:
  (15:45:25) Loading:
  (15:45:25) Loading: 4 packages loaded
  (15:45:25) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:45:25) WARNING: Target pattern parsing failed.
  (15:45:25) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:45:25) INFO: Elapsed time: 33.419s
  (15:45:25) INFO: 0 processes.
  (15:45:25) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.97378934061249320092344666664430965703699874823458052960213632045143671549392
    Line 395, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2523.600025 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2523.600025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.56271553726187873864569290873769936158076792951170911745292724141517602239609
    Line 368, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2631.872040 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2631.872040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt has 12 failures:
- Test chip_sw_uart_tx_rx_idx1 has 1 failures.
  - 0.chip_sw_uart_tx_rx_idx1.3842306693337039069421004279483487391146715646990534054559571190139812924701
    Line 942, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx1/latest/run.log
```
  UVM_ERROR @ 4500.517864 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4500.517864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_rand_baudrate has 6 failures.
  - 0.chip_sw_uart_rand_baudrate.53018891319307935658934499809552805448405306325905088410037968380295148523316
    Line 878, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_ERROR @ 10948.558260 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 10948.558260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.chip_sw_uart_rand_baudrate.99761647193420130040190197183858576391600087620593844362794490932713042116135
    Line 810, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_ERROR @ 11355.501800 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 11355.501800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
- Test chip_sw_uart_tx_rx_alt_clk_freq has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq.81618972190630495443782711548794033834554078189580101103029266666686228106615
    Line 1004, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log
```
  UVM_ERROR @ 5188.761225 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 5188.761225 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_idx2 has 1 failures.
  - 1.chip_sw_uart_tx_rx_idx2.64071957164729870916557390527014099436085681857805038448389236587186819757546
    Line 901, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx2/latest/run.log
```
  UVM_ERROR @ 4870.657590 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4870.657590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_idx3 has 1 failures.
  - 1.chip_sw_uart_tx_rx_idx3.52595074342283351904885193781402982363574795921575822070987021498814232234252
    Line 886, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx3/latest/run.log
```
  UVM_ERROR @ 4757.537564 us: (sw_logger_if.sv:526) [uart_tx_rx_test_sim_dv(sw/device/tests/uart_tx_rx_test.c:243)] CHECK-fail: Unexpected RX overflow interrupt
  UVM_INFO @ 4757.537564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 2 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.106437421160410924861581048511974913447388218782357257288252849329608082369019
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:3255c1d3-c2f0-4be4-acf9-6422e6968ad4
```
  - 2.chip_sw_uart_tx_rx_bootstrap.25745699396862177741222909558458964291427541904415703533816750666613675895263
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:406d2dbf-9bea-4fba-af64-49d3aa5e2215
```
- Test chip_sw_lc_walkthrough_testunlocks has 1 failures.
  - 0.chip_sw_lc_walkthrough_testunlocks.100991571297391241725231242479152528299052124470416091366184273023490150898684
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  Job ID: smart:d532584b-e457-4d46-ae95-b2ca12700091
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.107519737866000888760489955179229402851190963939528179334780966595028596659634
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:ae5336c3-bc87-4d2a-97fa-600c20eb92a7
```
  - 1.chip_sw_rv_timer_systick_test.29946278547765348094547722892668404230158559678352742948362796053170259227877
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:d682461c-792f-490f-87e2-7ab6e8ad1c44
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.94611266226144045081194785240563465376203340290498357009367847794856691382028
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:f1337385-60dc-4c9a-9c9b-6534d4d584f3
```
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 0.chip_sw_ast_clk_rst_inputs.66902895254362605060323232171534454169856632948079186350930167281597677336250
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:5130eeb3-a9e8-4d28-aacf-d08976652b35
```
  - 1.chip_sw_ast_clk_rst_inputs.66557575952853704467904998897396595178244464499792348135306936629055083247099
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:a1947858-99b0-4c10-a412-be19f09a3207
```
- ... and 1 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 4 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 4 failures.
  - 17.chip_sw_alert_handler_lpg_sleep_mode_alerts.7213860023336496653915143680249143699492292908795935128292164648701981286729
    Line 841, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3921.700782 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3921.700782 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.chip_sw_alert_handler_lpg_sleep_mode_alerts.109860095202590279742489319922603548662922713641450604801937939440157598562113
    Line 880, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3396.132246 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3396.132246 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.28009351917872061137922106027403177215655732284117536691274552138887863356320
    Line 883, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.55620545918079059561644417259931271246887991684671431897162434509015458490494
    Line 851, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.15081159929348832801906390267339333069474784427361878977467820972600267331868
    Line 883, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14586.734166 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14586.734166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.37054189794414651588926106567776988598442498902582928920350357649318186079850
    Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15216.372900 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15216.372900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 3 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 3 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.29411596945909211793740295404393657409028446484205770927764588356660419230033
    Line 1022, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 5499.549128 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 5499.549128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.82847497354711175995440847765247792416585081913962669801878466775884274357792
    Line 836, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6040.586500 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6040.586500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.91151009754730534517212061650112566637788713315328695998736376473901289597212
    Line 908, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 22847.371600 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 22847.371600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.5334725828687377064871195813517097980888987324464207501308795793458379697375
    Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23302.457600 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23302.457600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.69102711977836435782641943365115547290331419873725341411669604868543073091237
    Line 873, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3383.534313 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3383.534313 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.59198106924617501663104620642777678631070539616081763300814488090710550556806
    Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3921.059972 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3921.059972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.15661741800895826281050588523043947182933806811639486889928232415622841056363
    Line 858, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2348.090000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2348.090000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.34482405350289026572202477485992344173650179529697147550164951388851403996783
    Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2828.697000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2828.697000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.64848500547382724766088944443137226738316612195498024255377973584183534853867
    Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2415.869000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2415.869000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.82052604415344218383520565001133119848653182738850111852224789015678190574142
    Line 820, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 38162.140229 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 38162.140229 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.93555565816442634944295945498550929161601702687880605203557701302360705499554
    Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 51061.021756 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51061.021756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.45637890708529018405262591381583231746514502592085405494659899551366189719418
    Line 821, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 42362.133730 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 42362.133730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 10.chip_sw_all_escalation_resets.109843946770973200946413333018907623641260114397010000949872213512737871231668
    Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2674.585280 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2674.585280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.chip_sw_all_escalation_resets.64073556552763597329589308916574873637043651155532752343307252569835149826495
    Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2730.971464 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2730.971464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:767) [chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error *f* has 1 failures:
- Test chip_sw_lc_ctrl_rma_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_rma_to_scrap.89263835144924499156220577853415114485293408304322408157136451900368366793052
    Line 846, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log
```
  UVM_ERROR @ 3192.525457 us: (chip_sw_base_vseq.sv:767) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == 0 (5743 [0x166f] vs 0 [0x0]) Unexpected status error 166f800
  UVM_INFO @ 3192.525457 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:767) [chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error f* has 1 failures:
- Test chip_sw_lc_ctrl_raw_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_raw_to_scrap.23655023193309090689132523933486376786822930913071127168223343509626348715061
    Line 808, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log
```
  UVM_ERROR @ 2672.980390 us: (chip_sw_base_vseq.sv:767) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == 0 (983040 [0xf0000] vs 0 [0x0]) Unexpected status error f0000000
  UVM_INFO @ 2672.980390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(outstanding_load_resp | outstanding_store_resp)' has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 1.chip_sw_rv_core_ibex_lockstep_glitch.42780606378062651453595869545188162532108810784641347077058795718284621677459
    Line 805, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
      Offending '(outstanding_load_resp | outstanding_store_resp)'
  UVM_ERROR @ 2415.572584 us: (ibex_core.sv:967) [ASSERT FAILED] NoMemResponseWithoutPendingAccess
  UVM_INFO @ 2415.572584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 1.chip_sw_power_virus.73120748882772000989068524830833381203409990940088874529243751220900784217353
    Line 983, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4591.727106 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 4591.727106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```