1fbe1ece8d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 0 | 3 | 0.00 | ||
| chip_sw_example_rom | 0 | 3 | 0.00 | ||||
| chip_sw_example_manufacturer | 0 | 3 | 0.00 | ||||
| chip_sw_example_concurrency | 0 | 3 | 0.00 | ||||
| chip_sw_uart_smoketest_signed | 0 | 3 | 0.00 | ||||
| V1 | csr_hw_reset | chip_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | chip_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V1 | xbar_smoke | xbar_smoke | 0 | 100 | 0.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 0 | 3 | 0.00 | ||
| V1 | chip_sw_gpio_in | chip_sw_gpio | 0 | 3 | 0.00 | ||
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 0 | 3 | 0.00 | ||
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 0 | 5 | 0.00 | ||
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 0 | 5 | 0.00 | ||
| chip_sw_uart_tx_rx_idx1 | 0 | 5 | 0.00 | ||||
| chip_sw_uart_tx_rx_idx2 | 0 | 5 | 0.00 | ||||
| chip_sw_uart_tx_rx_idx3 | 0 | 5 | 0.00 | ||||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 0 | 20 | 0.00 | ||
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 0 | 5 | 0.00 | ||
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 223 | 0.00 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.511m | 5.805ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.511m | 5.805ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 0 | 3 | 0.00 | ||
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 0 | 5 | 0.00 | ||
| chip_tap_straps_testunlock0 | 0 | 5 | 0.00 | ||||
| chip_tap_straps_rma | 0 | 5 | 0.00 | ||||
| chip_tap_straps_prod | 0 | 5 | 0.00 | ||||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 0 | 3 | 0.00 | ||
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 0 | 6 | 0.00 | ||
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 0 | 6 | 0.00 | ||
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 0 | 3 | 0.00 | ||
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 0 | 3 | 0.00 | ||
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 0 | 3 | 0.00 | ||
| chip_sw_flash_ctrl_access_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_aes_enc_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_edn_entropy_reqs_jitter | 0 | 3 | 0.00 | ||||
| chip_sw_hmac_enc_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_keymgr_key_derivation_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_kmac_mode_kmac_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_jitter | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 0 | 1 | 0.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 0 | 5 | 0.00 | ||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 3 | 0.00 | ||
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 0 | 3 | 0.00 | ||
| chip_sw_aes_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_aon_timer_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_csrng_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_entropy_src_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_gpio_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_hmac_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_kmac_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_otbn_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_otp_ctrl_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_pwrmgr_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_pwrmgr_usbdev_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_rv_plic_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_rv_timer_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_rstmgr_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_sram_ctrl_smoketest | 0 | 3 | 0.00 | ||||
| chip_sw_uart_smoketest | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 0 | 3 | 0.00 | ||
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 0 | 3 | 0.00 | ||
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 0 | 3 | 0.00 | ||
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 0 | 3 | 0.00 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 0 | 3 | 0.00 | ||
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 0 | 3 | 0.00 | ||
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 0 | 3 | 0.00 | ||
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 0 | 3 | 0.00 | ||
| V2 | tl_d_oob_addr_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_illegal_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | xbar_base_random_sequence | xbar_random | 0 | 100 | 0.00 | ||
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 0 | 100 | 0.00 | ||
| xbar_smoke_large_delays | 0 | 100 | 0.00 | ||||
| xbar_smoke_slow_rsp | 0 | 100 | 0.00 | ||||
| xbar_random_zero_delays | 0 | 100 | 0.00 | ||||
| xbar_random_large_delays | 0 | 100 | 0.00 | ||||
| xbar_random_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_error_cases | xbar_error_random | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 0 | 100 | 0.00 | ||
| xbar_access_same_device_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 0 | 100 | 0.00 | ||
| V2 | xbar_stress_all | xbar_stress_all | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_error | 0 | 100 | 0.00 | ||||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_reset_error | 0 | 100 | 0.00 | ||||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 0 | 1 | 0.00 | ||||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 0 | 1 | 0.00 | ||||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_dev_otbn | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_dev_sw | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_prod_otbn | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_prod_sw | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_rma_otbn | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_rma_sw | 0 | 3 | 0.00 | ||||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_dev | 0 | 3 | 0.00 | ||||
| rom_e2e_asm_init_prod | 0 | 3 | 0.00 | ||||
| rom_e2e_asm_init_prod_end | 0 | 3 | 0.00 | ||||
| rom_e2e_asm_init_rma | 0 | 3 | 0.00 | ||||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 0 | 3 | 0.00 | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 0 | 3 | 0.00 | ||||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0 | 3 | 0.00 | ||||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 0 | 3 | 0.00 | ||
| chip_sw_aes_enc_jitter_en | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 0 | 3 | 0.00 | ||
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 3 | 0.00 | ||
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 0 | 5 | 0.00 | ||
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 0 | 3 | 0.00 | ||
| chip_sw_aes_idle | 0 | 3 | 0.00 | ||||
| chip_sw_hmac_enc_idle | 0 | 3 | 0.00 | ||||
| chip_sw_kmac_idle | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_hmac_trans | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_off_kmac_trans | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_off_otbn_trans | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 0 | 3 | 0.00 | ||||
| chip_sw_ast_clk_outputs | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 0 | 3 | 0.00 | ||
| chip_sw_flash_ctrl_access_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_aes_enc_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_edn_entropy_reqs_jitter | 0 | 3 | 0.00 | ||||
| chip_sw_hmac_enc_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_keymgr_key_derivation_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_kmac_mode_kmac_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_jitter | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 0 | 3 | 0.00 | ||
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 0 | 3 | 0.00 | ||||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 0 | 3 | 0.00 | ||||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 0 | 3 | 0.00 | ||||
| chip_sw_aes_enc_jitter_en_reduced_freq | 0 | 3 | 0.00 | ||||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 0 | 3 | 0.00 | ||||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 0 | 3 | 0.00 | ||||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 0 | 3 | 0.00 | ||||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 0 | 3 | 0.00 | ||||
| chip_sw_flash_init_reduced_freq | 0 | 3 | 0.00 | ||||
| chip_sw_csrng_edn_concurrency_reduced_freq | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 0 | 100 | 0.00 | ||
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 0 | 3 | 0.00 | ||
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 0 | 3 | 0.00 | ||
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 0 | 3 | 0.00 | ||
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 0 | 3 | 0.00 | ||
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 0 | 3 | 0.00 | ||
| chip_sw_sysrst_ctrl_reset | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 0 | 3 | 0.00 | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 0 | 3 | 0.00 | ||
| chip_sw_entropy_src_ast_rng_req | 0 | 3 | 0.00 | ||||
| chip_sw_edn_entropy_reqs | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 0 | 3 | 0.00 | ||
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 0 | 3 | 0.00 | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 0 | 3 | 0.00 | ||
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 0 | 3 | 0.00 | ||
| chip_sw_flash_ctrl_access_jitter_en | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 0 | 3 | 0.00 | ||
| chip_sw_flash_ctrl_ops_jitter_en | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 0 | 100 | 0.00 | ||
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 0 | 3 | 0.00 | ||
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 0 | 3 | 0.00 | ||
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 0 | 3 | 0.00 | ||
| chip_sw_i2c_host_tx_rx_idx1 | 0 | 3 | 0.00 | ||||
| chip_sw_i2c_host_tx_rx_idx2 | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 0 | 3 | 0.00 | ||
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 0 | 3 | 0.00 | ||
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 0 | 3 | 0.00 | ||
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 0 | 3 | 0.00 | ||
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac | 0 | 3 | 0.00 | ||||
| chip_sw_kmac_mode_kmac_jitter_en | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 0 | 3 | 0.00 | ||
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 0 | 15 | 0.00 | ||
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 0 | 3 | 0.00 | ||
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 0 | 3 | 0.00 | ||
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 0 | 5 | 0.00 | ||
| chip_tap_straps_rma | 0 | 5 | 0.00 | ||||
| chip_tap_straps_prod | 0 | 5 | 0.00 | ||||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 0 | 15 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 0 | 15 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 0 | 15 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 0 | 3 | 0.00 | ||
| chip_sw_flash_rma_unlocked | 0 | 3 | 0.00 | ||||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0 | 3 | 0.00 | ||||
| chip_sw_otp_ctrl_lc_signals_dev | 0 | 3 | 0.00 | ||||
| chip_sw_otp_ctrl_lc_signals_prod | 0 | 3 | 0.00 | ||||
| chip_sw_otp_ctrl_lc_signals_rma | 0 | 3 | 0.00 | ||||
| chip_sw_lc_ctrl_transition | 0 | 15 | 0.00 | ||||
| chip_sw_keymgr_key_derivation | 0 | 3 | 0.00 | ||||
| chip_sw_rom_ctrl_integrity_check | 0 | 3 | 0.00 | ||||
| chip_sw_sram_ctrl_execution_main | 0 | 3 | 0.00 | ||||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_lc | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 0 | 3 | 0.00 | ||||
| chip_tap_straps_dev | 0 | 5 | 0.00 | ||||
| chip_tap_straps_rma | 0 | 5 | 0.00 | ||||
| chip_tap_straps_prod | 0 | 5 | 0.00 | ||||
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 0 | 1 | 0.00 | ||
| chip_sw_lc_ctrl_raw_to_scrap | 0 | 1 | 0.00 | ||||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 0 | 1 | 0.00 | ||||
| chip_sw_lc_ctrl_rand_to_scrap | 0 | 3 | 0.00 | ||||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 0 | 3 | 0.00 | ||
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_prod | 0 | 3 | 0.00 | ||||
| chip_sw_lc_walkthrough_prodend | 0 | 3 | 0.00 | ||||
| chip_sw_lc_walkthrough_rma | 0 | 3 | 0.00 | ||||
| chip_sw_lc_walkthrough_testunlocks | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 0 | 3 | 0.00 | ||||
| rom_volatile_raw_unlock | 0 | 3 | 0.00 | ||||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 0 | 15 | 0.00 | ||
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 0 | 3 | 0.00 | ||
| chip_sw_otbn_mem_scramble | 0 | 3 | 0.00 | ||||
| chip_sw_keymgr_key_derivation | 0 | 3 | 0.00 | ||||
| chip_sw_sram_ctrl_scrambled_access | 0 | 3 | 0.00 | ||||
| chip_sw_rv_core_ibex_icache_invalidate | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 0 | 3 | 0.00 | ||
| chip_sw_otbn_mem_scramble | 0 | 3 | 0.00 | ||||
| chip_sw_keymgr_key_derivation | 0 | 3 | 0.00 | ||||
| chip_sw_sram_ctrl_scrambled_access | 0 | 3 | 0.00 | ||||
| chip_sw_rv_core_ibex_icache_invalidate | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 0 | 15 | 0.00 | ||
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 0 | 3 | 0.00 | ||||
| chip_sw_otp_ctrl_lc_signals_prod | 0 | 3 | 0.00 | ||||
| chip_sw_otp_ctrl_lc_signals_rma | 0 | 3 | 0.00 | ||||
| chip_sw_lc_ctrl_transition | 0 | 15 | 0.00 | ||||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 0 | 3 | 0.00 | ||
| chip_sw_aon_timer_wdog_bite_reset | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 0 | 3 | 0.00 | ||
| chip_sw_pwrmgr_all_reset_reqs | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 0 | 3 | 0.00 | ||
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 0 | 100 | 0.00 | ||
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 0 | 3 | 0.00 | ||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 3 | 0.00 | ||||
| chip_sw_pwrmgr_wdog_reset | 0 | 3 | 0.00 | ||||
| chip_sw_pwrmgr_smoketest | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 0 | 100 | 0.00 | ||
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 0 | 3 | 0.00 | ||
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 0 | 3 | 0.00 | ||
| chip_plic_all_irqs_10 | 0 | 3 | 0.00 | ||||
| chip_plic_all_irqs_20 | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 0 | 3 | 0.00 | ||
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 0 | 3 | 0.00 | ||
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 0 | 3 | 0.00 | ||
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 0 | 3 | 0.00 | ||
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 0 | 3 | 0.00 | ||
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 0 | 3 | 0.00 | ||
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 0 | 3 | 0.00 | ||
| chip_sw_sleep_sram_ret_contents_scramble | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 0 | 100 | 0.00 | ||
| chip_sw_data_integrity_escalation | 0 | 6 | 0.00 | ||||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 0 | 1 | 0.00 | ||
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 0 | 1 | 0.00 | ||
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 0 | 1 | 0.00 | ||
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 0 | 1 | 0.00 | ||
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 0 | 1 | 0.00 | ||
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 0 | 1 | 0.00 | ||
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 0 | 1 | 0.00 | ||
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 0 | 3 | 0.00 | ||
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 0 | 3 | 0.00 | ||
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 0 | 100 | 0.00 | ||
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 0 | 3 | 0.00 | ||
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 0 | 3 | 0.00 | ||
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 0 | 3 | 0.00 | ||
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 90 | 0.00 | ||
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 3 | 0.00 | ||
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 0 | 3 | 0.00 | ||
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 0 | 3 | 0.00 | ||
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 3 | 0.00 | ||
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 28.772m | 18.674ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 19.748m | 13.059ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 3 | 0.00 | ||
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 0 | 5 | 0.00 | ||
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 16 | 2657 | 0.60 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 0 | 3 | 0.00 | ||
| V2S | TOTAL | 0 | 3 | 0.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 3 | 0.00 | ||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_jtag_debug_rma | 0 | 1 | 0.00 | ||||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_inject_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_jtag_inject_rma | 0 | 1 | 0.00 | ||||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 0 | 0 | -- | ||
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 0 | 3 | 0.00 | ||
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 0 | 3 | 0.00 | ||
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 0 | 3 | 0.00 | ||
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 0 | 3 | 0.00 | ||
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 0 | 3 | 0.00 | ||
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 0 | 3 | 0.00 | ||
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 3 | 0.00 | ||
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | ||
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 0 | 3 | 0.00 | ||
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 0 | 3 | 0.00 | ||
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 0 | 3 | 0.00 | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 0 | 100 | 0.00 | ||
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | chip_sw_spi_host_pass_through | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | chip_sw_spi_host_configuration | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 0 | 5 | 0.00 | ||
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 0 | 1 | 0.00 | ||
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_jtag_debug_rma | 0 | 1 | 0.00 | ||||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 0 | 3 | 0.00 | ||
| V3 | TOTAL | 0 | 45 | 0.00 | |||
| Unmapped tests | chip_sival_flash_info_access | 0 | 3 | 0.00 | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 0 | 3 | 0.00 | ||||
| chip_sw_otbn_ecdsa_op_irq | 0 | 3 | 0.00 | ||||
| chip_sw_rv_core_ibex_rnd | 0 | 3 | 0.00 | ||||
| chip_sw_rv_core_ibex_nmi_irq | 0 | 3 | 0.00 | ||||
| chip_sw_pwrmgr_sleep_wake_5_bug | 0 | 3 | 0.00 | ||||
| chip_sw_rv_core_ibex_address_translation | 0 | 3 | 0.00 | ||||
| chip_sw_rv_core_ibex_lockstep_glitch | 0 | 3 | 0.00 | ||||
| chip_sw_flash_ctrl_write_clear | 0 | 3 | 0.00 | ||||
| TOTAL | 16 | 2955 | 0.54 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 9 | 9 | 0 | 0.00 |
| V1 | 19 | 19 | 0 | 0.00 |
| V2 | 290 | 276 | 3 | 1.03 |
| V2S | 1 | 1 | 0 | 0.00 |
| V3 | 91 | 21 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 59.38 | 67.31 | 64.84 | 36.65 | -- | 75.78 | 85.61 | 26.10 |
Exit reason: Error: User command failed Job returned non-zero exit code has 1028 failures:
0.chip_sw_example_flash.77169867747364542329679051755322047548008137925194668601369942569280029539147
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log
(15:42:55) ERROR: /workspace/mnt/repo_top/WORKSPACE:64:11: fetching http_archive rule //external:lowrisc_serde_annotate: Traceback (most recent call last):
File "/root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/bazel_tools/tools/build_defs/repo/http.bzl", line 132, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp17971324005592787954/v0.0.11.tar.gz: connect timed out
(15:42:55) ERROR: /workspace/mnt/repo_top/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @lowrisc_serde_annotate//serde_annotate:serde_annotate in repository @lowrisc_serde_annotate which failed to fetch. no such package '@lowrisc_serde_annotate//serde_annotate': java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp17971324005592787954/v0.0.11.tar.gz: connect timed out
(15:42:55) ERROR: Analysis of target '//sw/device/tests:example_test_from_flash_sim_dv' failed; build aborted:
(15:42:55) INFO: Elapsed time: 82.882s
(15:42:55) INFO: 0 processes.
(15:42:55) FAILED: Build did NOT complete successfully (185 packages loaded, 10708 targets configured)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_example_flash.114039381179060693995927908061547610495031473674661458505449669668675346149705
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_flash/latest/run.log
(15:45:01) ERROR: /workspace/mnt/repo_top/WORKSPACE:64:11: fetching http_archive rule //external:lowrisc_serde_annotate: Traceback (most recent call last):
File "/root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/bazel_tools/tools/build_defs/repo/http.bzl", line 132, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp17321635342968431927/v0.0.11.tar.gz: connect timed out
(15:45:01) ERROR: /workspace/mnt/repo_top/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @lowrisc_serde_annotate//serde_annotate:serde_annotate in repository @lowrisc_serde_annotate which failed to fetch. no such package '@lowrisc_serde_annotate//serde_annotate': java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp17321635342968431927/v0.0.11.tar.gz: connect timed out
(15:45:01) ERROR: Analysis of target '//sw/device/tests:example_test_from_flash_sim_dv' failed; build aborted:
(15:45:01) INFO: Elapsed time: 83.914s
(15:45:01) INFO: 0 processes.
(15:45:01) FAILED: Build did NOT complete successfully (185 packages loaded, 10708 targets configured)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_example_rom.25015874270598642551226901045023489209096889746931147895685501427997503793207
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
(15:42:55) ERROR: /workspace/mnt/repo_top/WORKSPACE:64:11: fetching http_archive rule //external:lowrisc_serde_annotate: Traceback (most recent call last):
File "/root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/bazel_tools/tools/build_defs/repo/http.bzl", line 132, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp13031604497324402527/v0.0.11.tar.gz: connect timed out
(15:42:55) ERROR: /workspace/mnt/repo_top/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @lowrisc_serde_annotate//serde_annotate:serde_annotate in repository @lowrisc_serde_annotate which failed to fetch. no such package '@lowrisc_serde_annotate//serde_annotate': java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp13031604497324402527/v0.0.11.tar.gz: connect timed out
(15:42:55) ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted:
(15:42:55) INFO: Elapsed time: 82.296s
(15:42:55) INFO: 0 processes.
(15:42:55) FAILED: Build did NOT complete successfully (181 packages loaded, 10625 targets configured)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_example_rom.28916652563814963274324289302223255498157168346638779061891191275345475876954
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
(15:45:03) ERROR: /workspace/mnt/repo_top/WORKSPACE:64:11: fetching http_archive rule //external:lowrisc_serde_annotate: Traceback (most recent call last):
File "/root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/bazel_tools/tools/build_defs/repo/http.bzl", line 132, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp14101671617672958562/v0.0.11.tar.gz: connect timed out
(15:45:03) ERROR: /workspace/mnt/repo_top/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @lowrisc_serde_annotate//serde_annotate:serde_annotate in repository @lowrisc_serde_annotate which failed to fetch. no such package '@lowrisc_serde_annotate//serde_annotate': java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp14101671617672958562/v0.0.11.tar.gz: connect timed out
(15:45:03) ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted:
(15:45:03) INFO: Elapsed time: 82.259s
(15:45:03) INFO: 0 processes.
(15:45:03) FAILED: Build did NOT complete successfully (181 packages loaded, 10625 targets configured)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_example_manufacturer.10478984821973081526169797441099907989776051040613813176265987344878208277356
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log
(15:42:50) ERROR: /workspace/mnt/repo_top/WORKSPACE:64:11: fetching http_archive rule //external:lowrisc_serde_annotate: Traceback (most recent call last):
File "/root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/bazel_tools/tools/build_defs/repo/http.bzl", line 132, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp6398293533330791757/v0.0.11.tar.gz: connect timed out
(15:42:50) ERROR: /workspace/mnt/repo_top/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @lowrisc_serde_annotate//serde_annotate:serde_annotate in repository @lowrisc_serde_annotate which failed to fetch. no such package '@lowrisc_serde_annotate//serde_annotate': java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp6398293533330791757/v0.0.11.tar.gz: connect timed out
(15:42:50) ERROR: Analysis of target '@manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted:
(15:42:50) INFO: Elapsed time: 82.990s
(15:42:50) INFO: 0 processes.
(15:42:50) FAILED: Build did NOT complete successfully (197 packages loaded, 10893 targets configured)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_example_manufacturer.31494760288504270691334310679601551408925650734333656893530506611668511427347
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log
(15:45:02) ERROR: /workspace/mnt/repo_top/WORKSPACE:64:11: fetching http_archive rule //external:lowrisc_serde_annotate: Traceback (most recent call last):
File "/root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/bazel_tools/tools/build_defs/repo/http.bzl", line 132, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp4627348104995789444/v0.0.11.tar.gz: connect timed out
(15:45:02) ERROR: /workspace/mnt/repo_top/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @lowrisc_serde_annotate//serde_annotate:serde_annotate in repository @lowrisc_serde_annotate which failed to fetch. no such package '@lowrisc_serde_annotate//serde_annotate': java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp4627348104995789444/v0.0.11.tar.gz: connect timed out
(15:45:02) ERROR: Analysis of target '@manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted:
(15:45:02) INFO: Elapsed time: 80.649s
(15:45:02) INFO: 0 processes.
(15:45:02) FAILED: Build did NOT complete successfully (197 packages loaded, 10893 targets configured)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_example_concurrency.21451699181843564259356703494091831534385946969500645987501735932504934635357
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log
(15:42:53) ERROR: /workspace/mnt/repo_top/WORKSPACE:64:11: fetching http_archive rule //external:lowrisc_serde_annotate: Traceback (most recent call last):
File "/root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/bazel_tools/tools/build_defs/repo/http.bzl", line 132, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp5781129411495039254/v0.0.11.tar.gz: connect timed out
(15:42:53) ERROR: /workspace/mnt/repo_top/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @lowrisc_serde_annotate//serde_annotate:serde_annotate in repository @lowrisc_serde_annotate which failed to fetch. no such package '@lowrisc_serde_annotate//serde_annotate': java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp5781129411495039254/v0.0.11.tar.gz: connect timed out
(15:42:53) ERROR: Analysis of target '//sw/device/tests:example_concurrency_test_sim_dv' failed; build aborted:
(15:42:53) INFO: Elapsed time: 83.096s
(15:42:53) INFO: 0 processes.
(15:42:53) FAILED: Build did NOT complete successfully (185 packages loaded, 10708 targets configured)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_example_concurrency.63034665066075246257960325767290186763237648197523182571749902684356838793586
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_concurrency/latest/run.log
(15:45:04) ERROR: /workspace/mnt/repo_top/WORKSPACE:64:11: fetching http_archive rule //external:lowrisc_serde_annotate: Traceback (most recent call last):
File "/root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/bazel_tools/tools/build_defs/repo/http.bzl", line 132, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp4839604484916951609/v0.0.11.tar.gz: connect timed out
(15:45:04) ERROR: /workspace/mnt/repo_top/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @lowrisc_serde_annotate//serde_annotate:serde_annotate in repository @lowrisc_serde_annotate which failed to fetch. no such package '@lowrisc_serde_annotate//serde_annotate': java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp4839604484916951609/v0.0.11.tar.gz: connect timed out
(15:45:04) ERROR: Analysis of target '//sw/device/tests:example_concurrency_test_sim_dv' failed; build aborted:
(15:45:04) INFO: Elapsed time: 81.741s
(15:45:04) INFO: 0 processes.
(15:45:04) FAILED: Build did NOT complete successfully (185 packages loaded, 10708 targets configured)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sival_flash_info_access.49088464863670140315815560951188769731521098797455982962746552128078114293432
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest/run.log
(15:42:59) ERROR: /workspace/mnt/repo_top/WORKSPACE:64:11: fetching http_archive rule //external:lowrisc_serde_annotate: Traceback (most recent call last):
File "/root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/bazel_tools/tools/build_defs/repo/http.bzl", line 132, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp11879975488210288732/v0.0.11.tar.gz: connect timed out
(15:42:59) ERROR: /workspace/mnt/repo_top/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @lowrisc_serde_annotate//serde_annotate:serde_annotate in repository @lowrisc_serde_annotate which failed to fetch. no such package '@lowrisc_serde_annotate//serde_annotate': java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp11879975488210288732/v0.0.11.tar.gz: connect timed out
(15:42:59) ERROR: Analysis of target '//sw/device/tests:flash_ctrl_info_access_lc_sim_dv' failed; build aborted:
(15:42:59) INFO: Elapsed time: 82.872s
(15:42:59) INFO: 0 processes.
(15:42:59) FAILED: Build did NOT complete successfully (196 packages loaded, 10836 targets configured)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sival_flash_info_access.95981056563553134776389968659230091112277219232118186059784531504962136431133
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sival_flash_info_access/latest/run.log
(15:45:08) ERROR: /workspace/mnt/repo_top/WORKSPACE:64:11: fetching http_archive rule //external:lowrisc_serde_annotate: Traceback (most recent call last):
File "/root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/bazel_tools/tools/build_defs/repo/http.bzl", line 132, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp6103916194945273740/v0.0.11.tar.gz: connect timed out
(15:45:08) ERROR: /workspace/mnt/repo_top/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @lowrisc_serde_annotate//serde_annotate:serde_annotate in repository @lowrisc_serde_annotate which failed to fetch. no such package '@lowrisc_serde_annotate//serde_annotate': java.io.IOException: Error downloading [https://github.com/lowRISC/serde-annotate/archive/refs/tags/v0.0.11.tar.gz] to /root/.cache/bazel/_bazel_default/96f40d218badc03ed33c48f246ec2aa1/external/lowrisc_serde_annotate/temp6103916194945273740/v0.0.11.tar.gz: connect timed out
(15:45:08) ERROR: Analysis of target '//sw/device/tests:flash_ctrl_info_access_lc_sim_dv' failed; build aborted:
(15:45:08) INFO: Elapsed time: 85.326s
(15:45:08) INFO: 0 processes.
(15:45:08) FAILED: Build did NOT complete successfully (196 packages loaded, 10836 targets configured)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
Test chip_csr_bit_bash has 3 failures.
0.chip_csr_bit_bash.72099360198261853915471656599621408112074431053063524694008641491059875760772
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
2.chip_csr_bit_bash.31918731745228213589780753156751692874574155392202545376411041472746343580958
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
... and 1 more failures.
Test chip_same_csr_outstanding has 3 failures.
0.chip_same_csr_outstanding.58783599097367118633970917675446047228816566922012391604356294061527954641720
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
2.chip_same_csr_outstanding.109422699247176385283079176240480786266847049325632186223510623982249818216536
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
... and 1 more failures.
Test chip_prim_tl_access has 2 failures.
0.chip_prim_tl_access.56867621431716765528137455460984691543447522786222190622390769293571727453168
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
2.chip_prim_tl_access.104596531664488773358139535373865013670934421411128107176535585529553405305613
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
Test xbar_smoke has 8 failures.
0.xbar_smoke.62418225207524483575282626077640423853135835281933259667633033989005195863196
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
2.xbar_smoke.67088774973673249213244950229780476065624340191415260356383492153921077069193
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
... and 6 more failures.
Test xbar_smoke_large_delays has 8 failures.
0.xbar_smoke_large_delays.17499168402589139743799581365680514771159461491715357505082307742696498995913
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
2.xbar_smoke_large_delays.51928122283315229328330538273106741765104071073545633240358601662216047638347
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
... and 6 more failures.
... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
Test chip_csr_aliasing has 3 failures.
0.chip_csr_aliasing.74998153200676003119072209047679376963038341128288174950589410737644453368785
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
2.chip_csr_aliasing.43718495392371873597484549053050356974051227665219196544912849755732014799582
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
... and 1 more failures.
Test chip_tl_errors has 8 failures.
0.chip_tl_errors.1391540120999189063052551290265873543430666836085064157330098148902874074938
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
2.chip_tl_errors.109722820543521230959570596351716763125444384718663383254007800511291796725725
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
... and 6 more failures.
Test chip_rv_dm_lc_disabled has 2 failures.
0.chip_rv_dm_lc_disabled.31763123170283811554193895738981180113332967325691455332902160474661117930945
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
2.chip_rv_dm_lc_disabled.36471990636621820691772286359941010446735969270354607932115815861277766033219
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
Test xbar_smoke_zero_delays has 8 failures.
0.xbar_smoke_zero_delays.82073611339417747549592714162833610260842669872234798706240895407552012405893
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
2.xbar_smoke_zero_delays.93584465852012305162998185772924839642714905162071115017491701018460860771996
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
... and 6 more failures.
Test xbar_smoke_slow_rsp has 8 failures.
0.xbar_smoke_slow_rsp.36985271297866591660526522883791062704950586487516458320010237116650435016624
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
2.xbar_smoke_slow_rsp.71033576369414155993393869826353195175012818600871180366444654495848109593959
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
... and 6 more failures.
... and 22 more tests.