CHIP Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.732m	3.046ms	3	3	100.00
		chip_sw_example_rom	2.131m	2.293ms	3	3	100.00
		chip_sw_example_manufacturer	4.299m	2.333ms	3	3	100.00
		chip_sw_example_concurrency	5.064m	3.414ms	3	3	100.00
		chip_sw_uart_smoketest_signed	32.450m	8.378ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset			0	5	0.00
V1	csr_rw	chip_csr_rw			0	20	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	5	0.00
V1	csr_aliasing	chip_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	5	0.00
		chip_csr_rw			0	20	0.00
V1	xbar_smoke	xbar_smoke			0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.623m	4.241ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.623m	4.241ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.623m	4.241ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.238m	5.105ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.238m	5.105ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	11.849m	4.175ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	13.477m	3.689ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	11.910m	5.085ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	34.348m	13.526ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	46.621m	12.840ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	20.210m	8.462ms	5	5	100.00
V1		TOTAL			68	223	30.49
V2	chip_pin_mux	chip_padctrl_attributes	4.955m	5.740ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.955m	5.740ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.165m	3.430ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.047m	3.098ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.741m	4.338ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	30.154m	17.598ms	5	5	100.00
		chip_tap_straps_testunlock0	16.536m	7.476ms	5	5	100.00
		chip_tap_straps_rma	6.493m	4.869ms	5	5	100.00
		chip_tap_straps_prod	18.198m	11.669ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	7.244m	3.189ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.204m	9.237ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	11.875m	4.924ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	11.875m	4.924ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	21.115m	7.906ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	33.484m	15.966ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.785m	4.718ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	23.601m	6.106ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.020h	18.663ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.161m	2.783ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.234m	5.956ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.499m	2.885ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.250m	5.704ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.149m	3.182ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.597m	4.889ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.161m	2.089ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.599m	3.500ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	17.109m	5.844ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.768m	4.901ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	6.468m	2.902ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.768m	4.901ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.260m	3.036ms	3	3	100.00
		chip_sw_aes_smoketest	4.589m	3.381ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.100m	2.562ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.395m	2.640ms	3	3	100.00
		chip_sw_csrng_smoketest	4.527m	2.605ms	3	3	100.00
		chip_sw_entropy_src_smoketest	9.625m	4.079ms	3	3	100.00
		chip_sw_gpio_smoketest	5.376m	3.333ms	3	3	100.00
		chip_sw_hmac_smoketest	6.056m	2.822ms	3	3	100.00
		chip_sw_kmac_smoketest	4.920m	2.570ms	3	3	100.00
		chip_sw_otbn_smoketest	29.828m	7.564ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	6.250m	3.194ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.415m	5.639ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.094m	4.423ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.214m	2.247ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.317m	2.906ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.770m	2.590ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.204m	2.995ms	3	3	100.00
		chip_sw_uart_smoketest	4.294m	2.576ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.743m	4.147ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	32.450m	8.378ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap			0	3	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	33.021m	8.402ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	40.127m	16.420ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	11.475m	4.178ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	9.859m	10.360ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.904h	59.652ms	2	3	66.67
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.309h	65.107ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	xbar_base_random_sequence	xbar_random			0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	100	0.00
		xbar_smoke_large_delays			0	100	0.00
		xbar_smoke_slow_rsp			0	100	0.00
		xbar_random_zero_delays			0	100	0.00
		xbar_random_large_delays			0	100	0.00
		xbar_random_slow_rsp			0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_error_cases	xbar_error_random			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	100	0.00
		xbar_access_same_device_slow_rsp			0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	100	0.00
V2	xbar_stress_all	xbar_stress_all			0	100	0.00
		xbar_stress_all_with_error			0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	100	0.00
		xbar_stress_all_with_reset_error			0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	33.021m	8.402ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	50.664m	22.626ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	35.109m	8.094ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	25.756m	7.033ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	32.529m	8.535ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	29.707m	8.646ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	36.104m	8.710ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	29.893m	8.330ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	25.208m	6.404ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	35.228m	8.884ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	33.208m	8.807ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	34.538m	9.324ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	32.232m	8.077ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	39.012m	9.585ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	44.585m	11.327ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	49.545m	12.085ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	49.437m	12.460ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	50.383m	12.432ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	42.407m	10.201ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	48.939m	10.736ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	43.186m	11.550ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	40.888m	12.263ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	40.649m	11.320ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	23.742m	6.826ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	35.052m	8.633ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	33.518m	8.748ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	35.609m	8.350ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	32.883m	8.264ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.217m	6.831ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	30.313m	8.011ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	29.964m	8.739ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	35.056m	8.649ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	31.712m	8.090ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.276m	6.854ms	3	3	100.00
		rom_e2e_asm_init_dev	35.322m	8.970ms	3	3	100.00
		rom_e2e_asm_init_prod	36.093m	9.044ms	3	3	100.00
		rom_e2e_asm_init_prod_end	37.049m	9.219ms	3	3	100.00
		rom_e2e_asm_init_rma	41.032m	8.312ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.942m	10.455ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.455m	3.115ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.161m	2.783ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.516m	2.604ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.868m	3.279ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	9.500m	5.085ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.097m	18.282ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.097m	18.282ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.369m	4.306ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.415m	5.639ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.369m	4.306ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	12.600m	8.832ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	12.600m	8.832ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.427m	7.206ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.359m	5.875ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.997m	6.254ms	3	3	100.00
		chip_sw_aes_idle	4.868m	3.279ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.983m	3.220ms	3	3	100.00
		chip_sw_kmac_idle	4.090m	2.620ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.220m	5.377ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.210m	5.122ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.811m	4.628ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.561m	4.822ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	18.931m	10.301ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.022m	4.274ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.048m	5.252ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.493m	3.483ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.988m	4.124ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.435m	4.299ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.148m	4.887ms	3	3	100.00
		chip_sw_ast_clk_outputs	21.115m	7.906ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.515m	13.661ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.493m	3.483ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.988m	4.124ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.785m	4.718ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	23.601m	6.106ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.020h	18.663ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.161m	2.783ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.234m	5.956ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.499m	2.885ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.250m	5.704ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.149m	3.182ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.597m	4.889ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.161m	2.089ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.014m	2.884ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	11.810m	4.985ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.485m	7.817ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.090h	24.693ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.162m	3.622ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.058m	2.732ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	11.144m	4.646ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	4.908m	3.522ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	9.985m	5.722ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	31.442m	17.832ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	46.375m	14.851ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	21.115m	7.906ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.315m	4.410ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	9.238m	3.412ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.594m	6.133ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	33.368m	8.151ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	28.658m	7.231ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.299m	5.319ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	13.610m	7.449ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.920m	3.444ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	25.097m	7.248ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	30.178m	22.675ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	4.943m	3.396ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	40.310s	10.380us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.711m	5.194ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	30.178m	22.675ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	30.178m	22.675ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	56.232m	20.620ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	56.232m	20.620ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.567m	5.748ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.097m	18.282ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.121h	19.040ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.019m	2.809ms	3	3	100.00
		chip_sw_edn_entropy_reqs	13.542m	3.941ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.019m	2.809ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	28.658m	7.231ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.973m	3.288ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	39.045m	24.013ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	21.584m	5.573ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	23.601m	6.106ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.481m	3.371ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.785m	4.718ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.508h	43.151ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	39.045m	24.013ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	5.864m	3.670ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	7.654m	5.181ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.794m	4.974ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.508h	43.151ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.794m	4.974ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.794m	4.974ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	11.794m	4.974ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.794m	4.974ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.594m	6.133ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.180m	5.349ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.964m	5.507ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.964m	5.507ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.721m	2.835ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.499m	2.885ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.983m	3.220ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.180m	5.236ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	14.597m	5.341ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	16.767m	5.402ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.889m	4.453ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	7.654m	5.181ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.250m	5.704ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.527m	5.628ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	9.500m	5.085ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.132h	20.016ms	2	3	66.67
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.757m	2.903ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.147m	2.952ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.149m	3.182ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	7.654m	5.181ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	20.162m	14.111ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.504m	2.557ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.312m	2.982ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.090m	2.620ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.661m	4.637ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	30.154m	17.598ms	5	5	100.00
		chip_tap_straps_rma	6.493m	4.869ms	5	5	100.00
		chip_tap_straps_prod	18.198m	11.669ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	7.019m	3.521ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	20.162m	14.111ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	20.162m	14.111ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	20.162m	14.111ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.095m	4.164ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	11.794m	4.974ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.508h	43.151ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.424m	4.371ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.628m	8.733ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	20.812m	8.348ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.677m	8.779ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.162m	14.111ms	15	15	100.00
		chip_sw_keymgr_key_derivation	7.654m	5.181ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	11.046m	9.218ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	16.680m	8.165ms	3	3	100.00
		chip_prim_tl_access			0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.515m	13.661ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.022m	4.274ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.048m	5.252ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.493m	3.483ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.988m	4.124ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.435m	4.299ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.148m	4.887ms	3	3	100.00
		chip_tap_straps_dev	30.154m	17.598ms	5	5	100.00
		chip_tap_straps_rma	6.493m	4.869ms	5	5	100.00
		chip_tap_straps_prod	18.198m	11.669ms	5	5	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.011m	3.139ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.157m	3.057ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.130m	3.810ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.014m	3.033ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	34.840m	23.588ms	3	3	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.542h	48.621ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.629h	48.117ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	19.400m	7.802ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.470h	45.235ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	34.840m	23.588ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.355m	2.887ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.123m	2.652ms	3	3	100.00
		rom_volatile_raw_unlock	1.861m	2.047ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	20.162m	14.111ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	39.045m	24.013ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.799m	4.174ms	3	3	100.00
		chip_sw_keymgr_key_derivation	7.654m	5.181ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.483m	5.052ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.849m	3.316ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	39.045m	24.013ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.799m	4.174ms	3	3	100.00
		chip_sw_keymgr_key_derivation	7.654m	5.181ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.483m	5.052ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.849m	3.316ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	20.162m	14.111ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	16.206m	15.582ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	7.019m	3.521ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.424m	4.371ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.628m	8.733ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	20.812m	8.348ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.677m	8.779ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.162m	14.111ms	15	15	100.00
		chip_prim_tl_access			0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.630m	9.573ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	28.645m	21.209ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.209m	7.203ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	11.882m	6.975ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.963m	7.517ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	31.433m	21.176ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	28.392m	16.705ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	12.600m	8.832ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	27.726m	11.004ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	9.193m	4.583ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.630m	9.573ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.224m	4.366ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	45.992m	28.952ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.032m	6.616ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.169m	4.955ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	43.156m	20.837ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	25.097m	7.248ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	25.789m	9.279ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	41.153m	26.812ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.555m	3.220ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.594m	6.133ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.046m	9.218ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.046m	9.218ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	25.789m	9.279ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	43.156m	20.837ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	9.193m	4.583ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.415m	5.639ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.284m	4.717ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	13.480m	7.056ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.064m	4.778ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.848m	12.891ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.550m	2.585ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.594m	6.133ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	34.050m	8.486ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.893m	5.399ms	3	3	100.00
		chip_plic_all_irqs_10	9.569m	4.064ms	3	3	100.00
		chip_plic_all_irqs_20	14.141m	5.196ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.471m	2.903ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.174m	3.658ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	33.021m	8.402ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.193m	7.039ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	8.399m	4.614ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.086m	3.172ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.939m	3.100ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.483m	5.052ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.597m	4.889ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	12.808m	7.182ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.768m	6.317ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.680m	8.165ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.594m	6.133ms	97	100	97.00
		chip_sw_data_integrity_escalation	11.875m	4.924ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.377m	2.754ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	6.048m	3.008ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	6.977m	3.504ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.626m	3.976ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	31.498m	7.643ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.749h	31.546ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	45.382m	12.620ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.873m	3.322ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.661m	4.637ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.594m	6.133ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	7.183m	3.653ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.848m	12.891ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.022m	4.863ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.169m	3.606ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	20.350m	10.664ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	33.368m	8.151ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	34.050m	8.486ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.300h	254.385ms	1	3	33.33
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	34.002m	20.610ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	24.397m	12.971ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.284m	4.717ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.772m	5.187ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.445m	4.100ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.493m	4.869ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			839	2657	31.58
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.512m	2.796ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.737h	50.582ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.763m	4.754ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.721m	2.142ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.966m	2.504ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.254m	2.711ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.178h	48.366ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.093h	39.767ms	0	1	0.00
		rom_e2e_jtag_inject_rma	49.952m	40.519ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.394m	3.775ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.932m	2.963ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	22.021m	5.588ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	39.553m	10.703ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.040m	3.687ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	18.481m	5.788ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.452m	2.580ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	12.107m	4.754ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.188m	23.358ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.983m	5.669ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	25.789m	9.279ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.594m	6.133ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.857h	37.811ms	1	3	33.33
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.857h	37.811ms	1	3	33.33
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.238m	5.105ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.160h	18.946ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.721m	2.142ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.966m	2.504ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.254m	2.711ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.730m	6.220ms	3	3	100.00
V3		TOTAL			31	45	68.89
	Unmapped tests	chip_sival_flash_info_access	5.350m	3.406ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.266m	5.905ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.070h	17.023ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	18.810m	5.966ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	18.046m	4.529ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.310m	4.628ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.590m	2.830ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.239m	3.215ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			965	2955	32.66

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	13	68.42
V2	290	276	232	80.00
V2S	1	1	1	100.00
V3	91	21	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.05	91.14	80.55	90.56	--	92.62	82.80	84.65

Failure Buckets

launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.20234088913926638160749916066453753310864470655430178450921901721269291193650
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
  - 2.chip_csr_bit_bash.71387865009889364586050583845234074557935638972613050440437963897820848015108
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.38207748860218663176784324193256972060487884745886544243896598000925640044915
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
  - 2.chip_same_csr_outstanding.99284892852053326283227478141046940014068305646219496503213751065353978419878
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
  - ... and 1 more failures.
- Test chip_prim_tl_access has 2 failures.
  - 0.chip_prim_tl_access.2186138129003845118967704887003206344808198041749492789759673292044839026998
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
  - 2.chip_prim_tl_access.77967119245689402392548153919477258922060568039197415237095193290846355676207
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
- Test xbar_smoke has 8 failures.
  - 0.xbar_smoke.18322997113309852318310613315067852064734110624507180668381747317547288372209
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
  - 2.xbar_smoke.107835601445206155510410716430866506578875980240433898299875440243909070825196
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
  - ... and 6 more failures.
- Test xbar_smoke_large_delays has 8 failures.
  - 0.xbar_smoke_large_delays.10652232359823642279777319373015812519442290393832114591091060436178836799659
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
  - 2.xbar_smoke_large_delays.77528101926506392016633757788901592112527670413472165635168654690433474050508
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
  - ... and 6 more failures.
- ... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.37500938231910599180824817841275744020509762968069168098296358388323585910012
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
  - 2.chip_csr_aliasing.25962447440583563466021728181743775593927246965306327456522967332981481034264
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
  - ... and 1 more failures.
- Test chip_tl_errors has 8 failures.
  - 0.chip_tl_errors.81034474775612138816364414078135415775019993645116935412581267719121625223349
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
  - 2.chip_tl_errors.78412416282338264007531015557144123857673796147064788719198017089576373948619
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
  - ... and 6 more failures.
- Test chip_rv_dm_lc_disabled has 2 failures.
  - 0.chip_rv_dm_lc_disabled.99761543600887669867455038559118473707014707291002148956277832240349695916787
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
  - 2.chip_rv_dm_lc_disabled.75610331299066807654380558214586368181201593409771913521316481359940808228831
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
- Test xbar_smoke_zero_delays has 8 failures.
  - 0.xbar_smoke_zero_delays.76768395985094754451315620633502374631290998870788675954275156873466720695807
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
  - 2.xbar_smoke_zero_delays.6600548061002979933622780895284179807402101796042616801611090279160627635096
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
  - ... and 6 more failures.
- Test xbar_smoke_slow_rsp has 8 failures.
  - 0.xbar_smoke_slow_rsp.9809395577351085764792450467814953257468504180155479200997255685196599733444
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
  - 2.xbar_smoke_slow_rsp.43044141340706010088293902594545028945264501325098557866509566621363205759711
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
  - ... and 6 more failures.
- ... and 22 more tests.

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.4509273645169933254073399540092349494149555937625337019854951651908119672295
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:57:34) Loading:
  (15:57:34) Loading:
  (15:57:34) Loading: 4 packages loaded
  (15:57:35) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:57:35) WARNING: Target pattern parsing failed.
  (15:57:35) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:57:35) INFO: Elapsed time: 28.397s
  (15:57:35) INFO: 0 processes.
  (15:57:35) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.115649110202777469323071111496224112246585208296217909233986213166152118304783
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (16:02:37) Loading:
  (16:02:38) Loading:
  (16:02:38) Loading: 4 packages loaded
  (16:02:38) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:02:38) WARNING: Target pattern parsing failed.
  (16:02:38) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:02:38) INFO: Elapsed time: 56.714s
  (16:02:38) INFO: 0 processes.
  (16:02:38) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.76167977652822270940822927075231308083857461292370108965589383887275269180908
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:57:25) Loading:
  (15:57:25) Loading:
  (15:57:26) Loading: 4 packages loaded
  (15:57:26) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:26) WARNING: Target pattern parsing failed.
  (15:57:26) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:26) INFO: Elapsed time: 18.550s
  (15:57:26) INFO: 0 processes.
  (15:57:26) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.72008787579563564624751283426232921705301195814727773206865485220353266330621
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (16:05:55) Loading:
  (16:05:56) Loading:
  (16:05:56) Loading: 4 packages loaded
  (16:05:57) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:05:57) WARNING: Target pattern parsing failed.
  (16:05:57) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:05:57) INFO: Elapsed time: 49.290s
  (16:05:57) INFO: 0 processes.
  (16:05:57) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.72224516430508911333045461862458194041469381901864989663893130824840937976013
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:57:33) Loading:
  (15:57:34) Loading:
  (15:57:34) Loading: 4 packages loaded
  (15:57:34) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:34) WARNING: Target pattern parsing failed.
  (15:57:34) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:34) INFO: Elapsed time: 24.411s
  (15:57:34) INFO: 0 processes.
  (15:57:34) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.93768953326882438387985944239306599094153043976228778747830781631339059188129
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:04:33) Loading:
  (16:04:34) Loading:
  (16:04:34) Loading: 4 packages loaded
  (16:04:34) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:04:34) WARNING: Target pattern parsing failed.
  (16:04:34) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:04:34) INFO: Elapsed time: 36.962s
  (16:04:34) INFO: 0 processes.
  (16:04:34) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.61578995975315478089057094239010432008782481006770018536722958030769716351333
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:57:32) Loading:
  (15:57:33) Loading:
  (15:57:33) Loading: 4 packages loaded
  (15:57:33) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:33) WARNING: Target pattern parsing failed.
  (15:57:33) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:33) INFO: Elapsed time: 18.644s
  (15:57:33) INFO: 0 processes.
  (15:57:33) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.27026858547320521287889592959209355587135862180433778859087764999538027440120
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (16:04:38) Loading:
  (16:04:39) Loading:
  (16:04:39) Loading: 4 packages loaded
  (16:04:39) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:04:39) WARNING: Target pattern parsing failed.
  (16:04:39) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:04:39) INFO: Elapsed time: 29.721s
  (16:04:39) INFO: 0 processes.
  (16:04:39) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.2254404366238144833335892205094937744994239582194464692180314197230954609316
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:57:29) Loading:
  (15:57:30) Loading:
  (15:57:30) Loading: 4 packages loaded
  (15:57:30) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:57:30) WARNING: Target pattern parsing failed.
  (15:57:30) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:57:30) INFO: Elapsed time: 20.329s
  (15:57:30) INFO: 0 processes.
  (15:57:30) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.88418277034778061124231211299109248397082443314458883308422763382515495116595
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (16:06:35) Loading:
  (16:06:36) Loading:
  (16:06:36) Loading: 4 packages loaded
  (16:06:37) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:06:37) WARNING: Target pattern parsing failed.
  (16:06:37) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:06:37) INFO: Elapsed time: 48.498s
  (16:06:37) INFO: 0 processes.
  (16:06:37) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 3 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.98087433551394307509887011097531024214835598091798792990488927934310630975580
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:6af6d9da-d3dc-47da-9168-f6744c1142d5
```
  - 1.chip_sw_uart_tx_rx_bootstrap.78083551194157517298176059671197730337361560370502389775159085902081139387954
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:d0afa360-a4ce-43de-bc95-3c0c5bfd7758
```
  - ... and 1 more failures.
- Test chip_sw_rv_timer_systick_test has 2 failures.
  - 0.chip_sw_rv_timer_systick_test.33215791514383758010462145712010371327885006874309703011361081672094193904407
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:927b25e2-cbcf-4f07-aa3b-8c73d4ee0036
```
  - 1.chip_sw_rv_timer_systick_test.92262203558488941239029363344026101887513834644119713566607452955473711287011
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:8890170a-6946-4f53-8bc9-c2fd02e24c6f
```
- Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 2 failures.
  - 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.55476584712719345265721383922809703525768167530467566564946656105260251869223
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
```
  Job ID: smart:3ae47ab5-b0e9-4d39-90c6-afeb2f5b2751
```
  - 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.78041529270824389633899841996801136998785670603295563583429905352101484029340
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
```
  Job ID: smart:cc8be779-e7fe-4ffb-ab5b-29d844f3c94d
```
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 1.chip_sw_ast_clk_rst_inputs.39588520253352498295901473964467950065915119391704627736900090774737208263731
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:5016c7a3-63e5-4ce4-8a2d-140356496907
```
  - 2.chip_sw_ast_clk_rst_inputs.87230200831511037124126004792041981885118401600202579432209049322413535545199
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:70cc0a4c-79a3-4218-a531-1519d84f0c25
```
- Test chip_sw_power_virus has 2 failures.
  - 1.chip_sw_power_virus.68626931735240444095485172507254784370468054004341205833904814353868777225781
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:b191cee6-9c12-4622-912d-388e2fbaebb0
```
  - 2.chip_sw_power_virus.36524821254567576763409235511448934508865422450785802963790379267292595377210
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:56396bc0-ad88-4327-862a-43a1416be2be
```
- ... and 1 more tests.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.44946738495727104013832658933234900960947917144084287146643948917189798463235
    Line 865, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.63613351209808830297880026962038444297506720572973496370912195309726116627753
    Line 872, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.60827327788593944048297634903321589744063798101363484000982660040533283940738
    Line 964, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14894.121184 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14894.121184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.8860466254249757124958793318028165947536132445738972615237320897366901248233
    Line 849, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15582.236810 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15582.236810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.97439093538763442565965467418312464406355715496882192426067820637259655742702
    Line 966, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 22735.243928 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 22735.243928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.115156417486070944632513541441591531001174662788794679009581509543172625025478
    Line 835, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 22894.320236 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 22894.320236 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.44775273904344134020942216411168815077430942178418404653027095323905405861673
    Line 912, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3342.969008 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3342.969008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.56497284864845074624068125938792365306290134146639420171157680980733522554754
    Line 839, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 4100.304370 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 4100.304370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.85333292236563526933094183890338637291163977052719421511102749990476253969016
    Line 745, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2141.860000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2141.860000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.11611425620307699620417076814614628522584793314513559182468747963687434408611
    Line 843, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2504.020000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2504.020000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.30979393394003265677855319166848507959816553590878071191483990775592699055575
    Line 827, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2710.523000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2710.523000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.96018756305908789691778025802236891991411131695240581181236168838052770004634
    Line 809, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 48365.649521 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 48365.649521 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.73925759920095459528984554310710747072720318998660301607495926071411576786385
    Line 838, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 39767.302600 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 39767.302600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.29786629849244006818719277320181698473828431020650779346408643594425267520111
    Line 822, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 40519.092294 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40519.092294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 25.chip_sw_all_escalation_resets.3165049036775713708343721804373203144504646014094676357617638591677627645156
    Line 830, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3498.077480 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3498.077480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.chip_sw_all_escalation_resets.78431941827431304093201690512495626228589469202985535071982167501179347270268
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3220.177496 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3220.177496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 36.chip_sw_alert_handler_lpg_sleep_mode_alerts.74041802854170544683591485084140109902586157512122935691450009233373653133938
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3933.579600 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3933.579600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 75.chip_sw_alert_handler_lpg_sleep_mode_alerts.51403967244213517290592067333562143629005662266622310258570278958711418944285
    Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3189.541904 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3189.541904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_keymgr_sideload_otbn has 1 failures.
  - 0.chip_sw_keymgr_sideload_otbn.54259289363000655529352784419338977350887377988574682917408063069182516942554
    Line 856, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest/run.log
```
  UVM_ERROR @ 20016.093590 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20016.093590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.16654702780708787119214970628925263564223629769071170289115224393994765441668
    Line 1246, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4754.163550 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 4754.163550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```