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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.25 95.38 94.39 95.68 95.08 97.38 99.58


Total test records in report: 2839
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T222 /workspace/coverage/default/0.chip_sw_flash_init.2548676854 Apr 16 04:16:21 PM PDT 24 Apr 16 04:55:05 PM PDT 24 17243606048 ps
T764 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1737535997 Apr 16 04:47:33 PM PDT 24 Apr 16 04:54:27 PM PDT 24 3654777320 ps
T722 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1751673823 Apr 16 04:46:50 PM PDT 24 Apr 16 04:54:36 PM PDT 24 4126772536 ps
T908 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2470490035 Apr 16 04:25:30 PM PDT 24 Apr 16 04:32:53 PM PDT 24 6170960504 ps
T909 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2148182789 Apr 16 04:43:53 PM PDT 24 Apr 16 05:03:14 PM PDT 24 7895802472 ps
T361 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2051887651 Apr 16 04:31:44 PM PDT 24 Apr 16 04:35:34 PM PDT 24 2698954246 ps
T142 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3278367300 Apr 16 04:37:33 PM PDT 24 Apr 16 04:41:51 PM PDT 24 2300230407 ps
T301 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3633269176 Apr 16 04:18:03 PM PDT 24 Apr 16 04:32:14 PM PDT 24 5378762284 ps
T910 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2334616791 Apr 16 04:50:24 PM PDT 24 Apr 16 04:56:11 PM PDT 24 3821025400 ps
T911 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1727134070 Apr 16 04:20:20 PM PDT 24 Apr 16 04:27:30 PM PDT 24 4075464424 ps
T912 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3270928456 Apr 16 04:29:28 PM PDT 24 Apr 16 04:40:11 PM PDT 24 4029281900 ps
T95 /workspace/coverage/default/43.chip_sw_all_escalation_resets.631528444 Apr 16 04:51:13 PM PDT 24 Apr 16 04:57:49 PM PDT 24 4648319572 ps
T913 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2412526282 Apr 16 04:15:11 PM PDT 24 Apr 16 04:33:54 PM PDT 24 6145490795 ps
T914 /workspace/coverage/default/1.chip_tap_straps_prod.1825304714 Apr 16 04:30:36 PM PDT 24 Apr 16 05:08:35 PM PDT 24 17956706875 ps
T789 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2120058561 Apr 16 04:22:28 PM PDT 24 Apr 16 04:32:52 PM PDT 24 5102619776 ps
T57 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.4173300272 Apr 16 04:22:04 PM PDT 24 Apr 16 04:27:21 PM PDT 24 5452709064 ps
T763 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.416009260 Apr 16 04:50:03 PM PDT 24 Apr 16 04:56:52 PM PDT 24 4550038500 ps
T761 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3684168979 Apr 16 04:52:53 PM PDT 24 Apr 16 05:02:25 PM PDT 24 5123438612 ps
T915 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.751855318 Apr 16 04:16:38 PM PDT 24 Apr 16 04:42:48 PM PDT 24 8027709560 ps
T916 /workspace/coverage/default/0.chip_sw_kmac_idle.2143056619 Apr 16 04:18:50 PM PDT 24 Apr 16 04:22:43 PM PDT 24 2451107186 ps
T762 /workspace/coverage/default/29.chip_sw_all_escalation_resets.1017403215 Apr 16 04:48:05 PM PDT 24 Apr 16 04:56:34 PM PDT 24 4463885620 ps
T917 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3125327802 Apr 16 04:26:56 PM PDT 24 Apr 16 04:30:09 PM PDT 24 2605580240 ps
T918 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1066166481 Apr 16 04:21:33 PM PDT 24 Apr 16 04:27:51 PM PDT 24 3448025481 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2435678536 Apr 16 04:15:51 PM PDT 24 Apr 16 06:06:03 PM PDT 24 31691719080 ps
T919 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4240364458 Apr 16 04:46:59 PM PDT 24 Apr 16 04:52:35 PM PDT 24 3474765624 ps
T325 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3961278547 Apr 16 04:34:04 PM PDT 24 Apr 16 04:47:53 PM PDT 24 3950951544 ps
T143 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1575766834 Apr 16 04:39:13 PM PDT 24 Apr 16 04:46:27 PM PDT 24 8399993008 ps
T226 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1009821538 Apr 16 04:39:13 PM PDT 24 Apr 16 05:12:27 PM PDT 24 19942028765 ps
T96 /workspace/coverage/default/0.chip_sw_all_escalation_resets.606677641 Apr 16 04:16:59 PM PDT 24 Apr 16 04:28:52 PM PDT 24 4576926040 ps
T210 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3958899940 Apr 16 04:31:16 PM PDT 24 Apr 16 04:39:30 PM PDT 24 4325629320 ps
T920 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3735568811 Apr 16 04:32:41 PM PDT 24 Apr 16 04:42:33 PM PDT 24 4394277892 ps
T252 /workspace/coverage/default/0.rom_volatile_raw_unlock.20841313 Apr 16 04:23:17 PM PDT 24 Apr 16 04:25:02 PM PDT 24 2190001010 ps
T921 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2404859178 Apr 16 04:33:46 PM PDT 24 Apr 16 04:52:38 PM PDT 24 6463670508 ps
T331 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3556016420 Apr 16 04:49:17 PM PDT 24 Apr 16 04:58:12 PM PDT 24 5304395864 ps
T922 /workspace/coverage/default/2.chip_sw_example_flash.680539115 Apr 16 04:32:37 PM PDT 24 Apr 16 04:36:55 PM PDT 24 2786669656 ps
T212 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1373705346 Apr 16 04:18:07 PM PDT 24 Apr 16 04:27:21 PM PDT 24 4906355896 ps
T201 /workspace/coverage/default/2.chip_sw_power_sleep_load.3868890977 Apr 16 04:40:39 PM PDT 24 Apr 16 04:46:51 PM PDT 24 4415146044 ps
T923 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3371301904 Apr 16 04:50:38 PM PDT 24 Apr 16 04:58:13 PM PDT 24 4177491620 ps
T786 /workspace/coverage/default/62.chip_sw_all_escalation_resets.1611525352 Apr 16 04:49:28 PM PDT 24 Apr 16 04:59:16 PM PDT 24 4328236488 ps
T692 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1609392423 Apr 16 04:34:15 PM PDT 24 Apr 16 04:37:39 PM PDT 24 2758629720 ps
T771 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1754620777 Apr 16 04:49:34 PM PDT 24 Apr 16 04:54:48 PM PDT 24 3330349240 ps
T924 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3700456862 Apr 16 04:23:59 PM PDT 24 Apr 16 05:00:34 PM PDT 24 9259019200 ps
T410 /workspace/coverage/default/82.chip_sw_all_escalation_resets.2231204411 Apr 16 04:51:47 PM PDT 24 Apr 16 04:58:35 PM PDT 24 4329983208 ps
T155 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2050967333 Apr 16 04:17:09 PM PDT 24 Apr 16 04:26:29 PM PDT 24 6265900520 ps
T42 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1066659671 Apr 16 04:33:28 PM PDT 24 Apr 16 04:39:13 PM PDT 24 2830909384 ps
T47 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4221836591 Apr 16 04:26:18 PM PDT 24 Apr 16 05:31:56 PM PDT 24 17396267926 ps
T415 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2127263313 Apr 16 04:38:22 PM PDT 24 Apr 16 04:51:57 PM PDT 24 7203309854 ps
T416 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3689257503 Apr 16 04:25:15 PM PDT 24 Apr 16 04:40:55 PM PDT 24 4443911694 ps
T417 /workspace/coverage/default/2.chip_sival_flash_info_access.4061613568 Apr 16 04:32:56 PM PDT 24 Apr 16 04:38:36 PM PDT 24 3124249176 ps
T418 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600362853 Apr 16 04:49:57 PM PDT 24 Apr 16 04:58:16 PM PDT 24 4171989496 ps
T419 /workspace/coverage/default/57.chip_sw_all_escalation_resets.3349825859 Apr 16 04:50:23 PM PDT 24 Apr 16 05:03:06 PM PDT 24 6255467456 ps
T177 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.865240408 Apr 16 04:39:09 PM PDT 24 Apr 16 04:44:38 PM PDT 24 2932425238 ps
T215 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.889653288 Apr 16 04:47:34 PM PDT 24 Apr 16 04:56:07 PM PDT 24 3486381950 ps
T370 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.729110173 Apr 16 04:43:54 PM PDT 24 Apr 16 04:53:23 PM PDT 24 4366612260 ps
T371 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2561570428 Apr 16 04:25:39 PM PDT 24 Apr 16 05:11:27 PM PDT 24 11747713232 ps
T372 /workspace/coverage/default/2.chip_sw_all_escalation_resets.2574833264 Apr 16 04:32:56 PM PDT 24 Apr 16 04:45:01 PM PDT 24 5552349300 ps
T373 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2870387467 Apr 16 04:26:11 PM PDT 24 Apr 16 04:30:42 PM PDT 24 3212449510 ps
T374 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1185574697 Apr 16 04:33:46 PM PDT 24 Apr 16 04:44:53 PM PDT 24 4350978327 ps
T375 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2508120716 Apr 16 04:47:00 PM PDT 24 Apr 16 04:53:37 PM PDT 24 3699285220 ps
T376 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3626791506 Apr 16 04:29:10 PM PDT 24 Apr 16 04:35:58 PM PDT 24 3471540926 ps
T377 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2723493869 Apr 16 04:19:42 PM PDT 24 Apr 16 04:24:49 PM PDT 24 2726846822 ps
T925 /workspace/coverage/default/1.chip_sw_example_manufacturer.2291777178 Apr 16 04:21:24 PM PDT 24 Apr 16 04:25:52 PM PDT 24 2321183300 ps
T21 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3693031837 Apr 16 04:16:59 PM PDT 24 Apr 16 05:17:13 PM PDT 24 20911275487 ps
T926 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1008087657 Apr 16 04:37:49 PM PDT 24 Apr 16 04:48:17 PM PDT 24 3901985160 ps
T693 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3913989787 Apr 16 04:17:31 PM PDT 24 Apr 16 04:23:09 PM PDT 24 3097740640 ps
T55 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3483617098 Apr 16 04:29:49 PM PDT 24 Apr 16 04:36:59 PM PDT 24 3196080160 ps
T26 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1221105158 Apr 16 04:32:32 PM PDT 24 Apr 16 04:36:56 PM PDT 24 3270875510 ps
T927 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2518076663 Apr 16 04:18:10 PM PDT 24 Apr 16 04:24:03 PM PDT 24 3005124646 ps
T253 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2708770988 Apr 16 04:38:55 PM PDT 24 Apr 16 05:36:39 PM PDT 24 14833275377 ps
T316 /workspace/coverage/default/16.chip_sw_all_escalation_resets.1076431007 Apr 16 04:45:35 PM PDT 24 Apr 16 04:56:49 PM PDT 24 5066174912 ps
T928 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.4017411467 Apr 16 04:26:10 PM PDT 24 Apr 16 05:29:09 PM PDT 24 15121391874 ps
T929 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1433232218 Apr 16 04:16:15 PM PDT 24 Apr 16 04:34:49 PM PDT 24 7587512280 ps
T321 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4017310554 Apr 16 04:17:40 PM PDT 24 Apr 16 04:29:12 PM PDT 24 4236405222 ps
T930 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2971338571 Apr 16 04:18:54 PM PDT 24 Apr 16 04:25:01 PM PDT 24 4448796804 ps
T931 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1977346138 Apr 16 04:32:27 PM PDT 24 Apr 16 04:42:22 PM PDT 24 4007252926 ps
T180 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.248767380 Apr 16 04:15:33 PM PDT 24 Apr 16 05:41:50 PM PDT 24 43158133790 ps
T932 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2604510537 Apr 16 04:38:08 PM PDT 24 Apr 16 05:32:36 PM PDT 24 15266482065 ps
T429 /workspace/coverage/default/1.chip_sw_otbn_randomness.2563936358 Apr 16 04:26:04 PM PDT 24 Apr 16 04:44:52 PM PDT 24 6151811416 ps
T933 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3444520369 Apr 16 04:44:17 PM PDT 24 Apr 16 04:59:40 PM PDT 24 11412041959 ps
T742 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3171705770 Apr 16 04:49:15 PM PDT 24 Apr 16 05:00:34 PM PDT 24 6098753868 ps
T213 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1946674159 Apr 16 04:46:30 PM PDT 24 Apr 16 04:52:17 PM PDT 24 3011045624 ps
T934 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2198170954 Apr 16 04:32:37 PM PDT 24 Apr 16 04:44:52 PM PDT 24 4351793612 ps
T935 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.106841797 Apr 16 04:36:27 PM PDT 24 Apr 16 04:42:51 PM PDT 24 6890485904 ps
T12 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3803940557 Apr 16 04:34:14 PM PDT 24 Apr 16 04:47:01 PM PDT 24 6690300674 ps
T24 /workspace/coverage/default/0.chip_sw_usbdev_config_host.4017948324 Apr 16 04:17:28 PM PDT 24 Apr 16 04:51:32 PM PDT 24 8238191272 ps
T73 /workspace/coverage/default/3.chip_tap_straps_testunlock0.367493902 Apr 16 04:42:32 PM PDT 24 Apr 16 04:52:08 PM PDT 24 5349832432 ps
T688 /workspace/coverage/default/25.chip_sw_all_escalation_resets.2923217858 Apr 16 04:47:29 PM PDT 24 Apr 16 04:57:58 PM PDT 24 4604082350 ps
T382 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1992397741 Apr 16 04:27:31 PM PDT 24 Apr 16 04:43:52 PM PDT 24 8610726180 ps
T936 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.606107259 Apr 16 04:23:03 PM PDT 24 Apr 16 04:43:12 PM PDT 24 7717825910 ps
T937 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3607003961 Apr 16 04:30:27 PM PDT 24 Apr 16 04:45:00 PM PDT 24 4348949448 ps
T238 /workspace/coverage/default/73.chip_sw_all_escalation_resets.2359758194 Apr 16 04:51:25 PM PDT 24 Apr 16 04:59:49 PM PDT 24 5612097516 ps
T790 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4246185581 Apr 16 04:51:24 PM PDT 24 Apr 16 04:57:46 PM PDT 24 3779468472 ps
T780 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2792233972 Apr 16 04:48:16 PM PDT 24 Apr 16 04:55:44 PM PDT 24 3517082140 ps
T938 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.708342724 Apr 16 04:20:51 PM PDT 24 Apr 16 04:28:59 PM PDT 24 4561867802 ps
T211 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.874364955 Apr 16 04:18:18 PM PDT 24 Apr 16 04:24:03 PM PDT 24 3994709260 ps
T241 /workspace/coverage/default/1.chip_sw_plic_sw_irq.1087381400 Apr 16 04:28:28 PM PDT 24 Apr 16 04:34:42 PM PDT 24 3126529840 ps
T939 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.665474079 Apr 16 04:22:40 PM PDT 24 Apr 16 05:06:27 PM PDT 24 27235840539 ps
T254 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3323230527 Apr 16 04:25:42 PM PDT 24 Apr 16 05:06:11 PM PDT 24 10840670260 ps
T940 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.756059433 Apr 16 04:46:31 PM PDT 24 Apr 16 04:57:35 PM PDT 24 7487463916 ps
T673 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.617327004 Apr 16 04:24:01 PM PDT 24 Apr 16 04:26:00 PM PDT 24 2329879107 ps
T941 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1270989850 Apr 16 04:39:02 PM PDT 24 Apr 16 04:47:03 PM PDT 24 2834310328 ps
T182 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2743996480 Apr 16 04:40:02 PM PDT 24 Apr 16 04:46:50 PM PDT 24 3925999580 ps
T364 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3869963972 Apr 16 04:49:06 PM PDT 24 Apr 16 04:55:38 PM PDT 24 3225333120 ps
T942 /workspace/coverage/default/0.chip_sw_uart_tx_rx.2508859906 Apr 16 04:17:00 PM PDT 24 Apr 16 04:28:27 PM PDT 24 4203114592 ps
T943 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3878362142 Apr 16 04:28:20 PM PDT 24 Apr 16 05:13:13 PM PDT 24 24023535064 ps
T944 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.670938526 Apr 16 04:21:19 PM PDT 24 Apr 16 04:25:14 PM PDT 24 3177868370 ps
T84 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.853767722 Apr 16 04:20:37 PM PDT 24 Apr 16 04:30:12 PM PDT 24 5859619350 ps
T687 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1813344200 Apr 16 04:44:02 PM PDT 24 Apr 16 04:51:04 PM PDT 24 4448793972 ps
T945 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.697432693 Apr 16 04:39:25 PM PDT 24 Apr 16 04:51:31 PM PDT 24 7805485808 ps
T946 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2011372508 Apr 16 04:37:28 PM PDT 24 Apr 16 05:25:18 PM PDT 24 29903695896 ps
T947 /workspace/coverage/default/2.chip_sw_csrng_kat_test.466508179 Apr 16 04:36:53 PM PDT 24 Apr 16 04:40:37 PM PDT 24 1986040240 ps
T22 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2806895223 Apr 16 04:25:03 PM PDT 24 Apr 16 04:53:07 PM PDT 24 22257740132 ps
T272 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3345705053 Apr 16 04:29:52 PM PDT 24 Apr 16 04:40:30 PM PDT 24 4758923271 ps
T329 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.192352116 Apr 16 04:15:37 PM PDT 24 Apr 16 04:26:56 PM PDT 24 4093562384 ps
T948 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.526943376 Apr 16 04:46:56 PM PDT 24 Apr 16 05:34:16 PM PDT 24 14876629321 ps
T214 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1311819905 Apr 16 04:36:31 PM PDT 24 Apr 16 04:44:45 PM PDT 24 5487806352 ps
T949 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2368281093 Apr 16 04:16:31 PM PDT 24 Apr 16 04:26:16 PM PDT 24 5044857720 ps
T950 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1195023877 Apr 16 04:41:25 PM PDT 24 Apr 16 04:48:30 PM PDT 24 4816118214 ps
T951 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3222460355 Apr 16 04:18:00 PM PDT 24 Apr 16 04:39:53 PM PDT 24 8539649360 ps
T952 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.163690968 Apr 16 04:18:14 PM PDT 24 Apr 16 04:22:48 PM PDT 24 2191537736 ps
T953 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2646061869 Apr 16 04:32:45 PM PDT 24 Apr 16 04:46:26 PM PDT 24 4326036390 ps
T954 /workspace/coverage/default/2.chip_sw_kmac_idle.3581771540 Apr 16 04:38:01 PM PDT 24 Apr 16 04:42:14 PM PDT 24 2368090808 ps
T955 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.4099497652 Apr 16 04:17:12 PM PDT 24 Apr 16 04:29:09 PM PDT 24 4360511508 ps
T183 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2871307689 Apr 16 04:37:52 PM PDT 24 Apr 16 04:50:59 PM PDT 24 9178301319 ps
T427 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.281257205 Apr 16 04:47:31 PM PDT 24 Apr 16 04:54:20 PM PDT 24 3538797520 ps
T131 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1344885600 Apr 16 04:19:41 PM PDT 24 Apr 16 04:27:42 PM PDT 24 5148651122 ps
T956 /workspace/coverage/default/2.chip_sw_uart_tx_rx.2349010972 Apr 16 04:33:51 PM PDT 24 Apr 16 04:44:48 PM PDT 24 4722706814 ps
T957 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1534616666 Apr 16 04:20:55 PM PDT 24 Apr 16 04:43:16 PM PDT 24 8486055080 ps
T317 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3078019678 Apr 16 04:48:10 PM PDT 24 Apr 16 04:57:16 PM PDT 24 4693290184 ps
T360 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4024851085 Apr 16 04:24:05 PM PDT 24 Apr 16 05:36:35 PM PDT 24 18365454280 ps
T729 /workspace/coverage/default/67.chip_sw_all_escalation_resets.2536376892 Apr 16 04:55:16 PM PDT 24 Apr 16 05:02:39 PM PDT 24 4154241352 ps
T958 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1105780515 Apr 16 04:34:37 PM PDT 24 Apr 16 04:47:49 PM PDT 24 8121664940 ps
T224 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1082795878 Apr 16 04:30:14 PM PDT 24 Apr 16 05:09:49 PM PDT 24 21455813316 ps
T781 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.15247721 Apr 16 04:48:43 PM PDT 24 Apr 16 04:53:46 PM PDT 24 3192432768 ps
T959 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1397878035 Apr 16 04:24:20 PM PDT 24 Apr 16 05:13:56 PM PDT 24 12342799160 ps
T88 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3674936502 Apr 16 04:26:09 PM PDT 24 Apr 16 04:31:18 PM PDT 24 3397242385 ps
T257 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.831169392 Apr 16 04:25:07 PM PDT 24 Apr 16 05:26:26 PM PDT 24 14356759920 ps
T960 /workspace/coverage/default/1.rom_keymgr_functest.4054987383 Apr 16 04:31:11 PM PDT 24 Apr 16 04:42:52 PM PDT 24 5084002096 ps
T961 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1634931034 Apr 16 04:44:14 PM PDT 24 Apr 16 05:28:27 PM PDT 24 12740086412 ps
T85 /workspace/coverage/default/1.chip_jtag_mem_access.661057288 Apr 16 04:22:14 PM PDT 24 Apr 16 04:46:39 PM PDT 24 13075556458 ps
T280 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1809346264 Apr 16 04:20:51 PM PDT 24 Apr 16 04:26:15 PM PDT 24 3094266620 ps
T962 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2435345040 Apr 16 04:42:16 PM PDT 24 Apr 16 04:46:11 PM PDT 24 2674155960 ps
T963 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.713801950 Apr 16 04:15:03 PM PDT 24 Apr 16 04:23:57 PM PDT 24 4315793230 ps
T205 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.484344644 Apr 16 04:37:40 PM PDT 24 Apr 16 05:00:41 PM PDT 24 6494101640 ps
T964 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1565398418 Apr 16 04:45:33 PM PDT 24 Apr 16 05:21:40 PM PDT 24 10063494008 ps
T749 /workspace/coverage/default/35.chip_sw_all_escalation_resets.884530945 Apr 16 04:46:55 PM PDT 24 Apr 16 04:58:20 PM PDT 24 4665315886 ps
T719 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3661138090 Apr 16 04:48:10 PM PDT 24 Apr 16 04:56:37 PM PDT 24 3853899210 ps
T223 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3162226130 Apr 16 04:19:59 PM PDT 24 Apr 16 05:07:04 PM PDT 24 22975013128 ps
T56 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1083901415 Apr 16 04:38:12 PM PDT 24 Apr 16 04:42:47 PM PDT 24 3960412942 ps
T43 /workspace/coverage/default/1.chip_sw_spi_device_tpm.4270502072 Apr 16 04:21:21 PM PDT 24 Apr 16 04:28:45 PM PDT 24 4059569900 ps
T965 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1984190870 Apr 16 04:38:07 PM PDT 24 Apr 16 05:06:07 PM PDT 24 12753655042 ps
T966 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.587044181 Apr 16 04:36:58 PM PDT 24 Apr 16 04:40:43 PM PDT 24 2892680460 ps
T739 /workspace/coverage/default/28.chip_sw_all_escalation_resets.411393624 Apr 16 04:47:05 PM PDT 24 Apr 16 04:55:20 PM PDT 24 4864837380 ps
T706 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3077284381 Apr 16 04:16:12 PM PDT 24 Apr 16 04:44:29 PM PDT 24 21404058810 ps
T967 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2158941994 Apr 16 04:32:41 PM PDT 24 Apr 16 04:36:45 PM PDT 24 2338291808 ps
T968 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2091892335 Apr 16 04:36:28 PM PDT 24 Apr 16 05:09:26 PM PDT 24 9887657548 ps
T969 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1630546162 Apr 16 04:30:04 PM PDT 24 Apr 16 04:37:10 PM PDT 24 5684888456 ps
T970 /workspace/coverage/default/1.chip_sw_example_flash.160055876 Apr 16 04:20:54 PM PDT 24 Apr 16 04:25:29 PM PDT 24 2523861422 ps
T58 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2899938156 Apr 16 04:18:26 PM PDT 24 Apr 16 04:23:38 PM PDT 24 4632567288 ps
T347 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2485361521 Apr 16 04:16:21 PM PDT 24 Apr 16 04:25:03 PM PDT 24 2739568452 ps
T9 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3860755275 Apr 16 04:33:42 PM PDT 24 Apr 16 04:39:24 PM PDT 24 2525814614 ps
T148 /workspace/coverage/default/2.chip_sw_otbn_smoketest.3233772420 Apr 16 04:43:51 PM PDT 24 Apr 16 04:59:44 PM PDT 24 5102118920 ps
T971 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4024568611 Apr 16 04:39:48 PM PDT 24 Apr 16 04:45:36 PM PDT 24 3049414849 ps
T747 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.63532767 Apr 16 04:48:08 PM PDT 24 Apr 16 04:54:07 PM PDT 24 3077756648 ps
T674 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.242978087 Apr 16 04:22:14 PM PDT 24 Apr 16 04:24:02 PM PDT 24 2031459675 ps
T89 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.17607665 Apr 16 04:35:53 PM PDT 24 Apr 16 04:41:19 PM PDT 24 3811455017 ps
T746 /workspace/coverage/default/45.chip_sw_all_escalation_resets.648099108 Apr 16 04:49:22 PM PDT 24 Apr 16 05:00:38 PM PDT 24 6010294336 ps
T670 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.415180425 Apr 16 04:31:44 PM PDT 24 Apr 16 04:39:15 PM PDT 24 5297743300 ps
T132 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2791764971 Apr 16 04:19:41 PM PDT 24 Apr 16 04:28:09 PM PDT 24 6608573422 ps
T972 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2261086954 Apr 16 04:19:45 PM PDT 24 Apr 16 04:23:46 PM PDT 24 2645147278 ps
T338 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4088816869 Apr 16 04:18:31 PM PDT 24 Apr 16 04:31:26 PM PDT 24 5003790138 ps
T973 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1048929873 Apr 16 04:18:03 PM PDT 24 Apr 16 04:38:04 PM PDT 24 4998305400 ps
T974 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.814777242 Apr 16 04:38:49 PM PDT 24 Apr 16 04:44:44 PM PDT 24 3755878165 ps
T975 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.163011450 Apr 16 04:15:51 PM PDT 24 Apr 16 04:19:57 PM PDT 24 2608198152 ps
T274 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.912951905 Apr 16 04:50:30 PM PDT 24 Apr 16 04:55:14 PM PDT 24 3208384528 ps
T62 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.176263005 Apr 16 04:17:23 PM PDT 24 Apr 16 04:21:25 PM PDT 24 3491605244 ps
T356 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.737971108 Apr 16 04:22:49 PM PDT 24 Apr 16 04:35:05 PM PDT 24 4328355400 ps
T976 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.646475146 Apr 16 04:32:24 PM PDT 24 Apr 16 04:40:05 PM PDT 24 3747610040 ps
T977 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.4053420606 Apr 16 04:34:51 PM PDT 24 Apr 16 04:41:34 PM PDT 24 6125093980 ps
T978 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2610738413 Apr 16 04:30:29 PM PDT 24 Apr 16 04:40:54 PM PDT 24 4700464007 ps
T979 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2438721172 Apr 16 04:46:37 PM PDT 24 Apr 16 05:14:37 PM PDT 24 8762734160 ps
T225 /workspace/coverage/default/1.chip_sw_flash_init.1796995815 Apr 16 04:20:07 PM PDT 24 Apr 16 04:59:35 PM PDT 24 25511087770 ps
T153 /workspace/coverage/default/1.chip_plic_all_irqs_10.547221889 Apr 16 04:27:54 PM PDT 24 Apr 16 04:37:40 PM PDT 24 3808941240 ps
T980 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1070826715 Apr 16 04:22:35 PM PDT 24 Apr 16 04:26:31 PM PDT 24 2409373390 ps
T981 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2049143714 Apr 16 04:20:38 PM PDT 24 Apr 16 04:31:07 PM PDT 24 5083366024 ps
T135 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2211229534 Apr 16 04:38:09 PM PDT 24 Apr 16 04:51:06 PM PDT 24 7066637314 ps
T737 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2912859399 Apr 16 04:44:54 PM PDT 24 Apr 16 04:50:35 PM PDT 24 3069153740 ps
T982 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2884393611 Apr 16 04:35:34 PM PDT 24 Apr 16 04:52:54 PM PDT 24 6985899750 ps
T983 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2016384858 Apr 16 04:17:46 PM PDT 24 Apr 16 04:41:07 PM PDT 24 12856795365 ps
T984 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1611289973 Apr 16 04:29:39 PM PDT 24 Apr 16 04:37:16 PM PDT 24 4735242843 ps
T218 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.160190243 Apr 16 04:36:42 PM PDT 24 Apr 16 04:48:14 PM PDT 24 4740051864 ps
T985 /workspace/coverage/default/3.chip_tap_straps_dev.3652074408 Apr 16 04:42:14 PM PDT 24 Apr 16 04:45:02 PM PDT 24 2586409828 ps
T322 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1138221797 Apr 16 04:25:45 PM PDT 24 Apr 16 04:35:56 PM PDT 24 5040493468 ps
T675 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3268109080 Apr 16 04:36:12 PM PDT 24 Apr 16 04:37:57 PM PDT 24 2752449146 ps
T74 /workspace/coverage/default/0.chip_tap_straps_rma.2373910960 Apr 16 04:22:37 PM PDT 24 Apr 16 04:32:36 PM PDT 24 6477793963 ps
T230 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3013301277 Apr 16 04:33:47 PM PDT 24 Apr 16 06:08:49 PM PDT 24 47799080780 ps
T244 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2869562131 Apr 16 04:40:04 PM PDT 24 Apr 16 04:49:40 PM PDT 24 5010157880 ps
T986 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1430594583 Apr 16 04:35:00 PM PDT 24 Apr 16 07:52:06 PM PDT 24 65472281675 ps
T987 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4263110653 Apr 16 04:25:29 PM PDT 24 Apr 16 05:10:45 PM PDT 24 14854769051 ps
T988 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.851230086 Apr 16 04:45:55 PM PDT 24 Apr 16 04:54:40 PM PDT 24 6973576248 ps
T108 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2667515203 Apr 16 04:30:07 PM PDT 24 Apr 16 04:56:47 PM PDT 24 20009154430 ps
T989 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4190015024 Apr 16 04:22:12 PM PDT 24 Apr 16 04:27:58 PM PDT 24 3750880672 ps
T323 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3039547293 Apr 16 04:34:48 PM PDT 24 Apr 16 04:45:55 PM PDT 24 4594240248 ps
T990 /workspace/coverage/default/4.chip_tap_straps_prod.2375272643 Apr 16 04:42:22 PM PDT 24 Apr 16 04:54:02 PM PDT 24 7185303624 ps
T159 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1706043216 Apr 16 04:25:13 PM PDT 24 Apr 16 07:56:33 PM PDT 24 254978408110 ps
T991 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4229911134 Apr 16 04:37:17 PM PDT 24 Apr 16 04:45:04 PM PDT 24 5165263853 ps
T992 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.990677130 Apr 16 04:18:40 PM PDT 24 Apr 16 04:29:10 PM PDT 24 8610413483 ps
T189 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2228234769 Apr 16 04:15:14 PM PDT 24 Apr 16 04:26:31 PM PDT 24 5824959830 ps
T993 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3493223906 Apr 16 04:42:46 PM PDT 24 Apr 16 05:03:54 PM PDT 24 8648208302 ps
T228 /workspace/coverage/default/2.chip_sw_flash_init.2964786721 Apr 16 04:33:41 PM PDT 24 Apr 16 05:08:17 PM PDT 24 22400457720 ps
T994 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.231854605 Apr 16 04:21:46 PM PDT 24 Apr 16 04:31:41 PM PDT 24 4047711504 ps
T995 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.425112352 Apr 16 04:31:27 PM PDT 24 Apr 16 04:50:50 PM PDT 24 5499347920 ps
T184 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.206544843 Apr 16 04:28:16 PM PDT 24 Apr 16 04:42:57 PM PDT 24 7439559012 ps
T411 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3124133638 Apr 16 04:48:37 PM PDT 24 Apr 16 04:59:01 PM PDT 24 5921795404 ps
T996 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.867207525 Apr 16 04:24:09 PM PDT 24 Apr 16 05:52:05 PM PDT 24 46678526392 ps
T997 /workspace/coverage/default/2.chip_sw_example_rom.738609072 Apr 16 04:31:54 PM PDT 24 Apr 16 04:34:05 PM PDT 24 1902261820 ps
T676 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1847715195 Apr 16 04:18:24 PM PDT 24 Apr 16 04:20:20 PM PDT 24 2179353162 ps
T351 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1554072620 Apr 16 04:38:50 PM PDT 24 Apr 16 04:41:34 PM PDT 24 1878099590 ps
T998 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.981411190 Apr 16 04:29:52 PM PDT 24 Apr 16 04:36:29 PM PDT 24 5123519960 ps
T999 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.4255697052 Apr 16 04:27:13 PM PDT 24 Apr 16 04:35:41 PM PDT 24 3964135244 ps
T672 /workspace/coverage/default/2.chip_tap_straps_dev.735033018 Apr 16 04:40:11 PM PDT 24 Apr 16 04:50:52 PM PDT 24 6290541584 ps
T1000 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3024824662 Apr 16 04:23:40 PM PDT 24 Apr 16 05:56:12 PM PDT 24 49608640439 ps
T519 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1543989600 Apr 16 04:35:41 PM PDT 24 Apr 16 04:48:51 PM PDT 24 4262853280 ps
T1001 /workspace/coverage/default/4.chip_sw_all_escalation_resets.1305346915 Apr 16 04:44:31 PM PDT 24 Apr 16 04:56:11 PM PDT 24 4517070008 ps
T294 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1260420912 Apr 16 04:16:32 PM PDT 24 Apr 16 04:47:52 PM PDT 24 11768336658 ps
T1002 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3627213373 Apr 16 04:26:34 PM PDT 24 Apr 16 05:15:31 PM PDT 24 12230903540 ps
T117 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3519747524 Apr 16 04:31:09 PM PDT 24 Apr 16 05:18:39 PM PDT 24 16508297480 ps
T1003 /workspace/coverage/default/2.chip_tap_straps_prod.1299726598 Apr 16 04:38:40 PM PDT 24 Apr 16 05:08:42 PM PDT 24 14306070966 ps
T1004 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3545829139 Apr 16 04:44:51 PM PDT 24 Apr 16 04:52:18 PM PDT 24 4732672870 ps
T1005 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.4003139459 Apr 16 04:36:02 PM PDT 24 Apr 16 06:03:04 PM PDT 24 47322881814 ps
T1006 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.493212249 Apr 16 04:26:11 PM PDT 24 Apr 16 04:45:55 PM PDT 24 7313373264 ps
T745 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3614514602 Apr 16 04:50:30 PM PDT 24 Apr 16 05:00:53 PM PDT 24 5247608712 ps
T721 /workspace/coverage/default/51.chip_sw_all_escalation_resets.310415538 Apr 16 04:50:32 PM PDT 24 Apr 16 05:02:01 PM PDT 24 5323900740 ps
T778 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2249526311 Apr 16 04:45:51 PM PDT 24 Apr 16 04:52:02 PM PDT 24 3459501224 ps
T1007 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.543793504 Apr 16 04:26:45 PM PDT 24 Apr 16 05:22:48 PM PDT 24 13669196040 ps
T1008 /workspace/coverage/default/1.chip_sw_example_rom.437813294 Apr 16 04:20:07 PM PDT 24 Apr 16 04:22:09 PM PDT 24 2168817008 ps
T219 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3247864338 Apr 16 04:17:47 PM PDT 24 Apr 16 05:32:32 PM PDT 24 19752324528 ps
T1009 /workspace/coverage/default/0.chip_sw_power_idle_load.130736883 Apr 16 04:22:08 PM PDT 24 Apr 16 04:35:57 PM PDT 24 4551320408 ps
T782 /workspace/coverage/default/40.chip_sw_all_escalation_resets.411240544 Apr 16 04:47:11 PM PDT 24 Apr 16 04:58:11 PM PDT 24 5547935162 ps
T66 /workspace/coverage/default/1.chip_sw_alert_test.1112763372 Apr 16 04:25:15 PM PDT 24 Apr 16 04:31:13 PM PDT 24 2634049000 ps
T723 /workspace/coverage/default/84.chip_sw_all_escalation_resets.573270841 Apr 16 04:52:08 PM PDT 24 Apr 16 05:02:12 PM PDT 24 5632806076 ps
T1010 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3031973063 Apr 16 04:24:08 PM PDT 24 Apr 16 04:41:43 PM PDT 24 7989511200 ps
T1011 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3843513020 Apr 16 04:27:41 PM PDT 24 Apr 16 04:32:21 PM PDT 24 2510495954 ps
T136 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4231617117 Apr 16 04:43:03 PM PDT 24 Apr 16 04:58:19 PM PDT 24 8700283540 ps
T1012 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.168840343 Apr 16 04:29:29 PM PDT 24 Apr 16 04:48:31 PM PDT 24 7806788518 ps
T1013 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1371382870 Apr 16 04:19:59 PM PDT 24 Apr 16 04:46:25 PM PDT 24 7242503808 ps
T776 /workspace/coverage/default/53.chip_sw_all_escalation_resets.3158766882 Apr 16 04:48:19 PM PDT 24 Apr 16 04:58:18 PM PDT 24 5129986300 ps
T1014 /workspace/coverage/default/2.chip_sw_otbn_randomness.3824804297 Apr 16 04:35:40 PM PDT 24 Apr 16 04:57:22 PM PDT 24 6395190694 ps
T720 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.974768151 Apr 16 04:52:33 PM PDT 24 Apr 16 04:59:50 PM PDT 24 3197206584 ps
T1015 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.54915255 Apr 16 04:21:05 PM PDT 24 Apr 16 04:32:09 PM PDT 24 4421674564 ps
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