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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.25 95.38 94.39 95.68 95.08 97.38 99.58


Total test records in report: 2839
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T1170 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.387305913 Apr 16 04:27:11 PM PDT 24 Apr 16 04:35:35 PM PDT 24 4120671160 ps
T1171 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2710445251 Apr 16 04:23:39 PM PDT 24 Apr 16 04:36:42 PM PDT 24 4810926636 ps
T1172 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2833631909 Apr 16 04:21:55 PM PDT 24 Apr 16 04:40:04 PM PDT 24 5723802460 ps
T1173 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1148504821 Apr 16 04:16:19 PM PDT 24 Apr 16 04:25:06 PM PDT 24 4665319256 ps
T634 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.322360014 Apr 16 04:41:33 PM PDT 24 Apr 16 04:50:46 PM PDT 24 5273928068 ps
T353 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3651104139 Apr 16 04:15:39 PM PDT 24 Apr 16 04:27:03 PM PDT 24 4934133108 ps
T1174 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.4037553554 Apr 16 04:20:48 PM PDT 24 Apr 16 04:25:21 PM PDT 24 2579999598 ps
T1175 /workspace/coverage/default/1.chip_sw_kmac_entropy.2387205569 Apr 16 04:22:24 PM PDT 24 Apr 16 04:27:17 PM PDT 24 3072666568 ps
T303 /workspace/coverage/default/0.chip_plic_all_irqs_20.1730905031 Apr 16 04:19:33 PM PDT 24 Apr 16 04:32:59 PM PDT 24 4824667080 ps
T1176 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3159870392 Apr 16 04:24:42 PM PDT 24 Apr 16 05:14:13 PM PDT 24 12706061994 ps
T1177 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2854657553 Apr 16 04:41:53 PM PDT 24 Apr 16 04:47:27 PM PDT 24 3055078872 ps
T79 /workspace/coverage/default/0.chip_sw_usbdev_pullup.4254466824 Apr 16 04:15:45 PM PDT 24 Apr 16 04:21:05 PM PDT 24 3254031664 ps
T249 /workspace/coverage/default/20.chip_sw_all_escalation_resets.3432930679 Apr 16 04:45:52 PM PDT 24 Apr 16 04:53:58 PM PDT 24 4060542996 ps
T671 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1494361575 Apr 16 04:16:59 PM PDT 24 Apr 16 04:25:46 PM PDT 24 5929533963 ps
T1178 /workspace/coverage/default/0.chip_sw_aes_idle.853574587 Apr 16 04:18:03 PM PDT 24 Apr 16 04:23:20 PM PDT 24 2723485654 ps
T412 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3714601061 Apr 16 04:45:50 PM PDT 24 Apr 16 04:53:08 PM PDT 24 4188308520 ps
T1179 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2547153884 Apr 16 04:21:02 PM PDT 24 Apr 16 04:27:58 PM PDT 24 4224876364 ps
T1180 /workspace/coverage/default/0.chip_sw_uart_smoketest.2011449608 Apr 16 04:22:55 PM PDT 24 Apr 16 04:27:51 PM PDT 24 2813337000 ps
T1181 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.779781633 Apr 16 04:49:34 PM PDT 24 Apr 16 04:55:26 PM PDT 24 3739460490 ps
T1182 /workspace/coverage/default/2.chip_sw_aes_idle.239241899 Apr 16 04:35:23 PM PDT 24 Apr 16 04:39:50 PM PDT 24 2604552426 ps
T1183 /workspace/coverage/default/1.chip_sw_rv_timer_irq.3280406216 Apr 16 04:24:21 PM PDT 24 Apr 16 04:28:35 PM PDT 24 2957805746 ps
T1184 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1021373826 Apr 16 04:16:47 PM PDT 24 Apr 16 04:19:51 PM PDT 24 2217699742 ps
T363 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.4096563060 Apr 16 04:21:42 PM PDT 24 Apr 16 04:26:48 PM PDT 24 2979919578 ps
T1185 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1232036489 Apr 16 04:24:35 PM PDT 24 Apr 16 05:23:06 PM PDT 24 15034463498 ps
T1186 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3212907056 Apr 16 04:26:18 PM PDT 24 Apr 16 05:15:32 PM PDT 24 13755122732 ps
T98 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2216707533 Apr 16 04:52:12 PM PDT 24 Apr 16 04:56:52 PM PDT 24 3287366122 ps
T1187 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.4178876830 Apr 16 04:50:30 PM PDT 24 Apr 16 05:10:19 PM PDT 24 7849659800 ps
T1188 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.411454780 Apr 16 04:35:58 PM PDT 24 Apr 16 05:42:13 PM PDT 24 17076595380 ps
T1189 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2040059872 Apr 16 04:17:39 PM PDT 24 Apr 16 04:43:50 PM PDT 24 12562829003 ps
T1190 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.727802441 Apr 16 04:23:42 PM PDT 24 Apr 16 04:58:16 PM PDT 24 26063561248 ps
T1191 /workspace/coverage/default/1.chip_sw_aon_timer_irq.1667516207 Apr 16 04:25:08 PM PDT 24 Apr 16 04:31:54 PM PDT 24 4012088812 ps
T1192 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2137607526 Apr 16 04:35:19 PM PDT 24 Apr 16 05:29:27 PM PDT 24 29091632920 ps
T1193 /workspace/coverage/default/2.chip_sw_hmac_enc.2246694600 Apr 16 04:38:20 PM PDT 24 Apr 16 04:43:47 PM PDT 24 3504175966 ps
T1194 /workspace/coverage/default/15.chip_sw_all_escalation_resets.202268005 Apr 16 04:45:28 PM PDT 24 Apr 16 04:53:33 PM PDT 24 5058383528 ps
T1195 /workspace/coverage/default/0.chip_sw_otbn_smoketest.3049726634 Apr 16 04:22:43 PM PDT 24 Apr 16 04:49:24 PM PDT 24 6087492914 ps
T740 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1789592931 Apr 16 04:44:57 PM PDT 24 Apr 16 04:51:26 PM PDT 24 3949632296 ps
T151 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.542892896 Apr 16 04:32:47 PM PDT 24 Apr 16 07:22:40 PM PDT 24 59573798216 ps
T728 /workspace/coverage/default/68.chip_sw_all_escalation_resets.1174738167 Apr 16 04:50:18 PM PDT 24 Apr 16 05:00:35 PM PDT 24 5843454680 ps
T1196 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3566666313 Apr 16 04:35:36 PM PDT 24 Apr 16 04:42:35 PM PDT 24 6456044045 ps
T37 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.863619097 Apr 16 04:15:34 PM PDT 24 Apr 16 04:21:45 PM PDT 24 3461970620 ps
T1197 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2118794432 Apr 16 04:51:32 PM PDT 24 Apr 16 05:02:11 PM PDT 24 5234649734 ps
T1198 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.352307974 Apr 16 04:23:56 PM PDT 24 Apr 16 05:18:24 PM PDT 24 14891729028 ps
T1199 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4016509491 Apr 16 04:29:08 PM PDT 24 Apr 16 04:32:01 PM PDT 24 2771029718 ps
T413 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2936297109 Apr 16 04:45:04 PM PDT 24 Apr 16 04:51:32 PM PDT 24 3762555050 ps
T1200 /workspace/coverage/default/1.chip_sw_csrng_smoketest.1710755697 Apr 16 04:33:09 PM PDT 24 Apr 16 04:38:21 PM PDT 24 2800381616 ps
T1201 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1638469902 Apr 16 04:45:37 PM PDT 24 Apr 16 05:08:04 PM PDT 24 7815798764 ps
T1202 /workspace/coverage/default/1.chip_tap_straps_testunlock0.1313208351 Apr 16 04:29:52 PM PDT 24 Apr 16 04:33:03 PM PDT 24 2611501260 ps
T1203 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3766429710 Apr 16 04:26:29 PM PDT 24 Apr 16 05:20:32 PM PDT 24 14484929946 ps
T99 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.820695544 Apr 16 04:50:27 PM PDT 24 Apr 16 04:57:47 PM PDT 24 3233172010 ps
T258 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.689691721 Apr 16 04:21:32 PM PDT 24 Apr 16 04:32:51 PM PDT 24 5091863542 ps
T259 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4252856210 Apr 16 04:35:20 PM PDT 24 Apr 16 05:00:55 PM PDT 24 12781731008 ps
T260 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.486076403 Apr 16 04:48:01 PM PDT 24 Apr 16 04:54:54 PM PDT 24 3731608944 ps
T261 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3261334139 Apr 16 04:45:11 PM PDT 24 Apr 16 04:50:12 PM PDT 24 2508922504 ps
T262 /workspace/coverage/default/0.chip_sw_example_rom.1088442400 Apr 16 04:14:58 PM PDT 24 Apr 16 04:17:12 PM PDT 24 2820901500 ps
T263 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2872449943 Apr 16 04:19:11 PM PDT 24 Apr 16 04:34:59 PM PDT 24 10530702733 ps
T264 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3766225090 Apr 16 04:26:40 PM PDT 24 Apr 16 04:41:56 PM PDT 24 5268157304 ps
T265 /workspace/coverage/default/2.chip_tap_straps_testunlock0.474035038 Apr 16 04:38:47 PM PDT 24 Apr 16 04:48:36 PM PDT 24 5925023994 ps
T266 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2946560367 Apr 16 04:17:31 PM PDT 24 Apr 16 05:46:34 PM PDT 24 50108143548 ps
T267 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2526570535 Apr 16 04:28:33 PM PDT 24 Apr 16 04:39:41 PM PDT 24 4532618874 ps
T1204 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1184492913 Apr 16 04:33:31 PM PDT 24 Apr 16 04:53:46 PM PDT 24 8810949552 ps
T1205 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.4047786491 Apr 16 04:44:48 PM PDT 24 Apr 16 04:59:31 PM PDT 24 12086299640 ps
T1206 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1021045170 Apr 16 04:24:02 PM PDT 24 Apr 16 04:38:55 PM PDT 24 9289411060 ps
T1207 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1236716725 Apr 16 04:44:34 PM PDT 24 Apr 16 05:11:01 PM PDT 24 7566389736 ps
T1208 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1028046761 Apr 16 04:25:20 PM PDT 24 Apr 16 05:18:38 PM PDT 24 14777678920 ps
T1209 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1359292861 Apr 16 04:19:57 PM PDT 24 Apr 16 04:28:06 PM PDT 24 3192176586 ps
T1210 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3921691417 Apr 16 04:45:46 PM PDT 24 Apr 16 05:38:53 PM PDT 24 15769774280 ps
T1211 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2297287454 Apr 16 04:39:38 PM PDT 24 Apr 16 04:43:11 PM PDT 24 3176502072 ps
T1212 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2113288279 Apr 16 04:31:11 PM PDT 24 Apr 16 04:34:49 PM PDT 24 2244296950 ps
T1213 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.695634150 Apr 16 04:37:50 PM PDT 24 Apr 16 04:43:49 PM PDT 24 4668045048 ps
T1214 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2658906704 Apr 16 04:23:47 PM PDT 24 Apr 16 05:02:02 PM PDT 24 10356075477 ps
T730 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3078564589 Apr 16 04:51:11 PM PDT 24 Apr 16 04:58:21 PM PDT 24 4959212092 ps
T1215 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4048393091 Apr 16 04:22:52 PM PDT 24 Apr 16 04:28:21 PM PDT 24 3231871452 ps
T1216 /workspace/coverage/default/2.chip_tap_straps_rma.145681425 Apr 16 04:39:10 PM PDT 24 Apr 16 04:47:40 PM PDT 24 5471288904 ps
T1217 /workspace/coverage/default/2.chip_sw_kmac_entropy.4074427974 Apr 16 04:33:04 PM PDT 24 Apr 16 04:37:10 PM PDT 24 3058908600 ps
T1218 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3182232067 Apr 16 04:17:37 PM PDT 24 Apr 16 04:24:42 PM PDT 24 3967969840 ps
T656 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1955881698 Apr 16 04:36:18 PM PDT 24 Apr 16 05:06:12 PM PDT 24 7022839106 ps
T1219 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.377396765 Apr 16 04:44:56 PM PDT 24 Apr 16 05:11:21 PM PDT 24 8834109358 ps
T1220 /workspace/coverage/default/2.chip_sw_gpio_smoketest.3591156543 Apr 16 04:44:50 PM PDT 24 Apr 16 04:49:54 PM PDT 24 3424027709 ps
T1221 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.872458071 Apr 16 04:27:50 PM PDT 24 Apr 16 04:32:01 PM PDT 24 3028218751 ps
T41 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.502869614 Apr 16 04:23:33 PM PDT 24 Apr 16 04:32:26 PM PDT 24 5506694064 ps
T1222 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3755073062 Apr 16 04:38:36 PM PDT 24 Apr 16 04:43:26 PM PDT 24 3144540852 ps
T1223 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2263846530 Apr 16 04:18:11 PM PDT 24 Apr 16 04:37:41 PM PDT 24 8545488056 ps
T1224 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.910600811 Apr 16 04:41:44 PM PDT 24 Apr 16 04:47:34 PM PDT 24 2704870920 ps
T1225 /workspace/coverage/default/2.chip_sw_flash_crash_alert.1077419473 Apr 16 04:39:36 PM PDT 24 Apr 16 04:48:23 PM PDT 24 4737580120 ps
T1226 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2132029697 Apr 16 04:44:18 PM PDT 24 Apr 16 04:54:35 PM PDT 24 7633546700 ps
T1227 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2779417631 Apr 16 04:24:34 PM PDT 24 Apr 16 04:34:23 PM PDT 24 6352523906 ps
T738 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2284823901 Apr 16 04:53:45 PM PDT 24 Apr 16 04:58:45 PM PDT 24 3471098020 ps
T677 /workspace/coverage/default/9.chip_sw_all_escalation_resets.1105588222 Apr 16 04:45:50 PM PDT 24 Apr 16 04:54:52 PM PDT 24 4594758692 ps
T1228 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.974046730 Apr 16 04:17:42 PM PDT 24 Apr 16 04:27:41 PM PDT 24 4689126926 ps
T779 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1055988847 Apr 16 04:55:18 PM PDT 24 Apr 16 05:01:24 PM PDT 24 3884064446 ps
T770 /workspace/coverage/default/6.chip_sw_all_escalation_resets.569493240 Apr 16 04:45:03 PM PDT 24 Apr 16 04:53:42 PM PDT 24 5020030524 ps
T1229 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3578365461 Apr 16 04:31:20 PM PDT 24 Apr 16 04:38:54 PM PDT 24 4507470554 ps
T1230 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3490970932 Apr 16 04:44:34 PM PDT 24 Apr 16 04:58:06 PM PDT 24 4371606550 ps
T1231 /workspace/coverage/default/0.rom_keymgr_functest.1365075154 Apr 16 04:20:53 PM PDT 24 Apr 16 04:28:21 PM PDT 24 4234061218 ps
T334 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1869953447 Apr 16 04:35:10 PM PDT 24 Apr 16 04:46:05 PM PDT 24 17929241800 ps
T1232 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2442726708 Apr 16 04:17:39 PM PDT 24 Apr 16 04:48:07 PM PDT 24 7027346250 ps
T775 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.4191208584 Apr 16 04:48:55 PM PDT 24 Apr 16 04:57:37 PM PDT 24 3899319388 ps
T1233 /workspace/coverage/default/0.chip_sw_example_flash.2478525785 Apr 16 04:16:15 PM PDT 24 Apr 16 04:20:17 PM PDT 24 2930258366 ps
T1234 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2925261920 Apr 16 04:27:52 PM PDT 24 Apr 16 05:39:39 PM PDT 24 18743157208 ps
T754 /workspace/coverage/default/11.chip_sw_all_escalation_resets.2416451353 Apr 16 04:46:01 PM PDT 24 Apr 16 04:56:13 PM PDT 24 6218767024 ps
T1235 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3314850321 Apr 16 04:23:17 PM PDT 24 Apr 16 04:33:41 PM PDT 24 4072476190 ps
T282 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2029215718 Apr 16 04:31:24 PM PDT 24 Apr 16 04:34:50 PM PDT 24 2381326196 ps
T141 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3829709005 Apr 16 04:28:34 PM PDT 24 Apr 16 04:41:31 PM PDT 24 5984803580 ps
T1236 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4124199294 Apr 16 04:38:16 PM PDT 24 Apr 16 04:48:07 PM PDT 24 4549298904 ps
T1237 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3945768759 Apr 16 04:37:07 PM PDT 24 Apr 16 04:42:52 PM PDT 24 3270579211 ps
T777 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.653609777 Apr 16 04:44:30 PM PDT 24 Apr 16 04:50:57 PM PDT 24 3823263352 ps
T1238 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3579155159 Apr 16 04:20:02 PM PDT 24 Apr 16 04:27:10 PM PDT 24 4993144169 ps
T1239 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3056555246 Apr 16 04:54:33 PM PDT 24 Apr 16 05:01:12 PM PDT 24 4362096108 ps
T1240 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.950776605 Apr 16 04:18:16 PM PDT 24 Apr 16 04:42:48 PM PDT 24 9930767384 ps
T1241 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1636154180 Apr 16 04:33:51 PM PDT 24 Apr 16 05:56:22 PM PDT 24 45985428897 ps
T1242 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2351857554 Apr 16 04:30:12 PM PDT 24 Apr 16 04:44:01 PM PDT 24 5841471608 ps
T765 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1813871725 Apr 16 04:50:49 PM PDT 24 Apr 16 04:57:34 PM PDT 24 3598260940 ps
T1243 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2306896452 Apr 16 04:24:16 PM PDT 24 Apr 16 05:49:47 PM PDT 24 18130270200 ps
T1244 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1085352740 Apr 16 04:39:56 PM PDT 24 Apr 16 04:44:56 PM PDT 24 3348777729 ps
T1245 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3213461698 Apr 16 04:33:15 PM PDT 24 Apr 16 04:50:16 PM PDT 24 6258398690 ps
T335 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.617268470 Apr 16 04:26:01 PM PDT 24 Apr 16 04:35:52 PM PDT 24 19160498816 ps
T1246 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2432020145 Apr 16 04:50:28 PM PDT 24 Apr 16 05:00:28 PM PDT 24 5223368648 ps
T1247 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1051791692 Apr 16 04:22:34 PM PDT 24 Apr 16 04:33:59 PM PDT 24 3672004232 ps
T1248 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3501972439 Apr 16 04:18:40 PM PDT 24 Apr 16 04:23:17 PM PDT 24 2792252968 ps
T1249 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1153647187 Apr 16 04:16:05 PM PDT 24 Apr 16 04:21:00 PM PDT 24 4058175544 ps
T1250 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2629870540 Apr 16 04:22:49 PM PDT 24 Apr 16 04:46:56 PM PDT 24 9365702708 ps
T1251 /workspace/coverage/default/2.rom_keymgr_functest.3882431069 Apr 16 04:41:29 PM PDT 24 Apr 16 04:49:11 PM PDT 24 3732421492 ps
T1252 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3538586327 Apr 16 04:16:37 PM PDT 24 Apr 16 04:25:26 PM PDT 24 6703873696 ps
T1253 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1357728322 Apr 16 04:29:34 PM PDT 24 Apr 16 05:39:09 PM PDT 24 18056651862 ps
T1254 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.494333246 Apr 16 04:26:23 PM PDT 24 Apr 16 04:33:28 PM PDT 24 3004831096 ps
T1255 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1208416316 Apr 16 04:51:39 PM PDT 24 Apr 16 04:57:26 PM PDT 24 3869966420 ps
T1256 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2576214052 Apr 16 04:31:01 PM PDT 24 Apr 16 04:35:47 PM PDT 24 2981992500 ps
T725 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3955169885 Apr 16 04:44:06 PM PDT 24 Apr 16 04:50:49 PM PDT 24 3587519662 ps
T1257 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3970541805 Apr 16 04:52:13 PM PDT 24 Apr 16 04:58:38 PM PDT 24 4154552236 ps
T767 /workspace/coverage/default/26.chip_sw_all_escalation_resets.297063343 Apr 16 04:52:35 PM PDT 24 Apr 16 05:03:23 PM PDT 24 5518523086 ps
T414 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.21111286 Apr 16 04:18:36 PM PDT 24 Apr 16 04:26:19 PM PDT 24 3448642100 ps
T750 /workspace/coverage/default/49.chip_sw_all_escalation_resets.204020070 Apr 16 04:51:25 PM PDT 24 Apr 16 05:03:38 PM PDT 24 5360331392 ps
T1258 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3343486492 Apr 16 04:27:39 PM PDT 24 Apr 16 04:36:33 PM PDT 24 4870394604 ps
T309 /workspace/coverage/default/1.chip_plic_all_irqs_20.3817556112 Apr 16 04:30:19 PM PDT 24 Apr 16 04:44:20 PM PDT 24 4826404880 ps
T732 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3343698844 Apr 16 04:48:49 PM PDT 24 Apr 16 04:54:20 PM PDT 24 3478005706 ps
T1259 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3966852393 Apr 16 04:35:53 PM PDT 24 Apr 16 04:43:01 PM PDT 24 3587638168 ps
T220 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3135497986 Apr 16 04:37:33 PM PDT 24 Apr 16 05:56:18 PM PDT 24 18161660654 ps
T1260 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3242451275 Apr 16 04:44:02 PM PDT 24 Apr 16 04:55:40 PM PDT 24 4110860432 ps
T1261 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1105767188 Apr 16 04:23:46 PM PDT 24 Apr 16 04:31:45 PM PDT 24 5633794094 ps
T1262 /workspace/coverage/default/23.chip_sw_all_escalation_resets.2860504970 Apr 16 04:45:33 PM PDT 24 Apr 16 04:58:34 PM PDT 24 4548761244 ps
T1263 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2099176700 Apr 16 04:32:48 PM PDT 24 Apr 16 04:37:14 PM PDT 24 3407029707 ps
T1264 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.525752789 Apr 16 04:23:28 PM PDT 24 Apr 16 04:26:56 PM PDT 24 3031202880 ps
T1265 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2470877932 Apr 16 04:16:32 PM PDT 24 Apr 16 04:27:09 PM PDT 24 5825275040 ps
T250 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3120917581 Apr 16 04:36:22 PM PDT 24 Apr 16 04:44:42 PM PDT 24 6598749312 ps
T167 /workspace/coverage/default/61.chip_sw_all_escalation_resets.3332758940 Apr 16 04:49:07 PM PDT 24 Apr 16 04:57:13 PM PDT 24 4944567048 ps
T1266 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.298253299 Apr 16 04:17:53 PM PDT 24 Apr 16 04:22:45 PM PDT 24 3269438376 ps
T731 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.515537306 Apr 16 04:49:16 PM PDT 24 Apr 16 04:55:00 PM PDT 24 4206007136 ps
T1267 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1382878570 Apr 16 04:25:23 PM PDT 24 Apr 16 04:46:16 PM PDT 24 6074491185 ps
T302 /workspace/coverage/default/0.chip_plic_all_irqs_0.1673572281 Apr 16 04:19:04 PM PDT 24 Apr 16 04:42:01 PM PDT 24 6230686670 ps
T1268 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.341550532 Apr 16 04:42:31 PM PDT 24 Apr 16 04:51:06 PM PDT 24 5667893360 ps
T1269 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3461384137 Apr 16 04:16:09 PM PDT 24 Apr 16 04:20:48 PM PDT 24 2717172816 ps
T1270 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3248688778 Apr 16 04:17:37 PM PDT 24 Apr 16 04:23:02 PM PDT 24 2852935864 ps
T221 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1542990419 Apr 16 04:26:43 PM PDT 24 Apr 16 05:38:46 PM PDT 24 16018746120 ps
T1271 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1158726411 Apr 16 04:23:27 PM PDT 24 Apr 16 04:36:48 PM PDT 24 10360006819 ps
T1272 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3729506156 Apr 16 04:17:11 PM PDT 24 Apr 16 05:02:58 PM PDT 24 22104389636 ps
T1273 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3505610025 Apr 16 04:23:55 PM PDT 24 Apr 16 04:27:50 PM PDT 24 2171748622 ps
T1274 /workspace/coverage/default/2.chip_sw_example_concurrency.2409419644 Apr 16 04:32:49 PM PDT 24 Apr 16 04:38:25 PM PDT 24 2752549512 ps
T736 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3703873923 Apr 16 04:53:55 PM PDT 24 Apr 16 05:03:10 PM PDT 24 4978707928 ps
T44 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1487743529 Apr 16 04:18:33 PM PDT 24 Apr 16 04:25:35 PM PDT 24 3686917626 ps
T1275 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3192885521 Apr 16 04:15:08 PM PDT 24 Apr 16 04:39:12 PM PDT 24 7430148472 ps
T339 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2267052273 Apr 16 04:30:21 PM PDT 24 Apr 16 04:42:55 PM PDT 24 4886662370 ps
T733 /workspace/coverage/default/17.chip_sw_all_escalation_resets.731727076 Apr 16 04:50:33 PM PDT 24 Apr 16 05:03:56 PM PDT 24 5572085010 ps
T1276 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3026463215 Apr 16 04:23:42 PM PDT 24 Apr 16 04:46:32 PM PDT 24 7732790776 ps
T1277 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.4126311805 Apr 16 04:18:50 PM PDT 24 Apr 16 04:37:33 PM PDT 24 5011639208 ps
T1278 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3050721751 Apr 16 04:44:56 PM PDT 24 Apr 16 04:52:40 PM PDT 24 6645005086 ps
T726 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4225972811 Apr 16 04:48:34 PM PDT 24 Apr 16 04:56:07 PM PDT 24 3439180792 ps
T1279 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3984424607 Apr 16 04:36:00 PM PDT 24 Apr 16 04:40:50 PM PDT 24 2949796250 ps
T1280 /workspace/coverage/default/1.chip_sw_aes_idle.1958106054 Apr 16 04:25:36 PM PDT 24 Apr 16 04:29:07 PM PDT 24 3076158180 ps
T1281 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.936801415 Apr 16 04:39:45 PM PDT 24 Apr 16 04:48:59 PM PDT 24 3752852280 ps
T768 /workspace/coverage/default/97.chip_sw_all_escalation_resets.441793509 Apr 16 04:53:22 PM PDT 24 Apr 16 05:00:54 PM PDT 24 4927524280 ps
T1282 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2624607761 Apr 16 04:17:07 PM PDT 24 Apr 16 04:31:25 PM PDT 24 7083668496 ps
T1283 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.552020871 Apr 16 04:19:21 PM PDT 24 Apr 16 04:31:38 PM PDT 24 6604915174 ps
T1284 /workspace/coverage/default/1.rom_e2e_asm_init_prod.4135378327 Apr 16 04:36:34 PM PDT 24 Apr 16 05:40:22 PM PDT 24 14528048112 ps
T1285 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.282492975 Apr 16 04:29:13 PM PDT 24 Apr 16 04:39:17 PM PDT 24 4170526532 ps
T1286 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2220351983 Apr 16 04:27:33 PM PDT 24 Apr 16 04:43:01 PM PDT 24 5700407325 ps
T1287 /workspace/coverage/default/2.chip_sw_aes_smoketest.1779759791 Apr 16 04:41:39 PM PDT 24 Apr 16 04:46:18 PM PDT 24 3111062752 ps
T741 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1786979180 Apr 16 04:51:49 PM PDT 24 Apr 16 05:02:13 PM PDT 24 5975126004 ps
T354 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1873865227 Apr 16 04:34:08 PM PDT 24 Apr 16 04:49:18 PM PDT 24 5037003320 ps
T1288 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2395408336 Apr 16 04:24:18 PM PDT 24 Apr 16 05:21:00 PM PDT 24 14508114560 ps
T1289 /workspace/coverage/default/2.chip_sw_rv_timer_irq.1542455872 Apr 16 04:35:32 PM PDT 24 Apr 16 04:39:42 PM PDT 24 2541425030 ps
T1290 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3882096304 Apr 16 04:44:30 PM PDT 24 Apr 16 05:09:49 PM PDT 24 9110739476 ps
T1291 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.373607410 Apr 16 04:18:27 PM PDT 24 Apr 16 04:29:23 PM PDT 24 4329957854 ps
T1292 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.727334082 Apr 16 04:43:38 PM PDT 24 Apr 16 04:59:00 PM PDT 24 9622333904 ps
T735 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2989088422 Apr 16 04:51:38 PM PDT 24 Apr 16 04:58:28 PM PDT 24 3713519990 ps
T394 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3722331391 Apr 16 04:18:17 PM PDT 24 Apr 16 04:50:22 PM PDT 24 21231654040 ps
T1293 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1355020404 Apr 16 04:41:02 PM PDT 24 Apr 16 04:50:45 PM PDT 24 4125888250 ps
T1294 /workspace/coverage/default/0.chip_sw_otbn_randomness.2578461191 Apr 16 04:17:58 PM PDT 24 Apr 16 04:30:11 PM PDT 24 5828497660 ps
T1295 /workspace/coverage/default/2.chip_sw_power_idle_load.4175617052 Apr 16 04:41:30 PM PDT 24 Apr 16 04:52:44 PM PDT 24 3860878280 ps
T420 /workspace/coverage/default/0.chip_jtag_mem_access.214725261 Apr 16 04:10:08 PM PDT 24 Apr 16 04:37:10 PM PDT 24 13429350532 ps
T80 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1441462930 Apr 16 03:50:57 PM PDT 24 Apr 16 04:07:27 PM PDT 24 19665450988 ps
T81 /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.794278451 Apr 16 03:54:41 PM PDT 24 Apr 16 03:59:35 PM PDT 24 17880075168 ps
T82 /workspace/coverage/cover_reg_top/74.xbar_error_random.3775953027 Apr 16 04:03:47 PM PDT 24 Apr 16 04:04:26 PM PDT 24 479419870 ps
T239 /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.2596179582 Apr 16 03:57:02 PM PDT 24 Apr 16 03:57:09 PM PDT 24 81524768 ps
T352 /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.4291833546 Apr 16 03:52:10 PM PDT 24 Apr 16 03:57:37 PM PDT 24 2556659400 ps
T523 /workspace/coverage/cover_reg_top/52.xbar_access_same_device.1957852330 Apr 16 03:59:58 PM PDT 24 Apr 16 04:01:30 PM PDT 24 2148958681 ps
T430 /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1563885004 Apr 16 03:48:55 PM PDT 24 Apr 16 03:50:40 PM PDT 24 6350117498 ps
T431 /workspace/coverage/cover_reg_top/15.xbar_smoke.2908415893 Apr 16 03:53:55 PM PDT 24 Apr 16 03:54:05 PM PDT 24 195307520 ps
T397 /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3749983559 Apr 16 04:07:03 PM PDT 24 Apr 16 04:08:21 PM PDT 24 204279200 ps
T399 /workspace/coverage/cover_reg_top/41.xbar_stress_all.80326316 Apr 16 03:58:16 PM PDT 24 Apr 16 04:03:43 PM PDT 24 8363564434 ps
T405 /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2374846460 Apr 16 03:56:40 PM PDT 24 Apr 16 04:04:37 PM PDT 24 26931239183 ps
T396 /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3681583400 Apr 16 04:00:43 PM PDT 24 Apr 16 04:23:18 PM PDT 24 75352767693 ps
T807 /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2654990742 Apr 16 04:03:46 PM PDT 24 Apr 16 04:12:26 PM PDT 24 32747822467 ps
T526 /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3006374218 Apr 16 03:54:48 PM PDT 24 Apr 16 03:55:17 PM PDT 24 290207720 ps
T527 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.2927581921 Apr 16 03:55:56 PM PDT 24 Apr 16 03:57:00 PM PDT 24 840967984 ps
T524 /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2832690483 Apr 16 03:49:14 PM PDT 24 Apr 16 03:51:25 PM PDT 24 1647347614 ps
T616 /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2702190661 Apr 16 03:54:16 PM PDT 24 Apr 16 03:55:48 PM PDT 24 8844290334 ps
T525 /workspace/coverage/cover_reg_top/88.xbar_access_same_device.472285061 Apr 16 04:06:09 PM PDT 24 Apr 16 04:07:34 PM PDT 24 1230051402 ps
T834 /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.431733774 Apr 16 04:04:59 PM PDT 24 Apr 16 04:06:00 PM PDT 24 144878582 ps
T862 /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.1046291359 Apr 16 04:02:36 PM PDT 24 Apr 16 04:03:35 PM PDT 24 5712306080 ps
T863 /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3067452155 Apr 16 04:04:36 PM PDT 24 Apr 16 04:07:04 PM PDT 24 13160242424 ps
T579 /workspace/coverage/cover_reg_top/95.xbar_same_source.389376982 Apr 16 04:07:21 PM PDT 24 Apr 16 04:07:40 PM PDT 24 635042715 ps
T797 /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.539839006 Apr 16 04:03:24 PM PDT 24 Apr 16 04:11:57 PM PDT 24 30971406723 ps
T607 /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.834952843 Apr 16 03:58:19 PM PDT 24 Apr 16 03:59:50 PM PDT 24 5113994125 ps
T678 /workspace/coverage/cover_reg_top/48.xbar_access_same_device.3084578996 Apr 16 03:59:20 PM PDT 24 Apr 16 04:00:44 PM PDT 24 1265967148 ps
T499 /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.1966780746 Apr 16 04:01:37 PM PDT 24 Apr 16 04:15:36 PM PDT 24 77294764078 ps
T528 /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.3192499029 Apr 16 04:01:22 PM PDT 24 Apr 16 04:06:31 PM PDT 24 3816161416 ps
T813 /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.2071703331 Apr 16 03:57:05 PM PDT 24 Apr 16 03:58:53 PM PDT 24 5892349538 ps
T529 /workspace/coverage/cover_reg_top/33.xbar_same_source.3832722363 Apr 16 03:56:51 PM PDT 24 Apr 16 03:57:32 PM PDT 24 529272529 ps
T432 /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2453074191 Apr 16 03:59:21 PM PDT 24 Apr 16 04:14:16 PM PDT 24 49284496121 ps
T618 /workspace/coverage/cover_reg_top/66.xbar_same_source.2025206592 Apr 16 04:02:20 PM PDT 24 Apr 16 04:02:34 PM PDT 24 323546525 ps
T1296 /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.749662978 Apr 16 04:06:35 PM PDT 24 Apr 16 04:06:42 PM PDT 24 51611398 ps
T402 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.992368734 Apr 16 04:05:34 PM PDT 24 Apr 16 04:14:31 PM PDT 24 4569204571 ps
T613 /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.572556916 Apr 16 03:53:11 PM PDT 24 Apr 16 03:57:17 PM PDT 24 13460340627 ps
T1297 /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1939771918 Apr 16 04:04:18 PM PDT 24 Apr 16 04:05:58 PM PDT 24 5465651503 ps
T594 /workspace/coverage/cover_reg_top/92.xbar_random.3345833829 Apr 16 04:06:48 PM PDT 24 Apr 16 04:07:21 PM PDT 24 770133499 ps
T578 /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2102118717 Apr 16 03:53:41 PM PDT 24 Apr 16 03:55:10 PM PDT 24 8482911288 ps
T544 /workspace/coverage/cover_reg_top/94.xbar_stress_all.3885787857 Apr 16 04:07:09 PM PDT 24 Apr 16 04:08:17 PM PDT 24 1627804858 ps
T805 /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2186402892 Apr 16 04:00:57 PM PDT 24 Apr 16 04:20:53 PM PDT 24 69930061401 ps
T443 /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3926410073 Apr 16 03:54:56 PM PDT 24 Apr 16 03:55:15 PM PDT 24 172594002 ps
T586 /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.2235444604 Apr 16 03:59:25 PM PDT 24 Apr 16 03:59:45 PM PDT 24 453947813 ps
T404 /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.326737915 Apr 16 03:58:37 PM PDT 24 Apr 16 04:05:10 PM PDT 24 21314718728 ps
T1298 /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.374425481 Apr 16 04:07:43 PM PDT 24 Apr 16 04:07:51 PM PDT 24 48377506 ps
T391 /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1425611248 Apr 16 03:55:30 PM PDT 24 Apr 16 04:06:41 PM PDT 24 6088717565 ps
T549 /workspace/coverage/cover_reg_top/40.xbar_same_source.1891232732 Apr 16 03:57:58 PM PDT 24 Apr 16 03:58:55 PM PDT 24 1926450552 ps
T587 /workspace/coverage/cover_reg_top/58.xbar_random.924030441 Apr 16 04:00:53 PM PDT 24 Apr 16 04:01:07 PM PDT 24 127024145 ps
T610 /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.815877451 Apr 16 04:07:51 PM PDT 24 Apr 16 04:07:58 PM PDT 24 49915806 ps
T488 /workspace/coverage/cover_reg_top/78.xbar_stress_all.448800349 Apr 16 04:04:37 PM PDT 24 Apr 16 04:05:46 PM PDT 24 2028069140 ps
T1299 /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2105186155 Apr 16 03:54:03 PM PDT 24 Apr 16 03:54:10 PM PDT 24 46293357 ps
T393 /workspace/coverage/cover_reg_top/5.xbar_stress_all.224183340 Apr 16 03:50:19 PM PDT 24 Apr 16 03:53:09 PM PDT 24 1655919979 ps
T1300 /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.254681950 Apr 16 04:06:20 PM PDT 24 Apr 16 04:07:38 PM PDT 24 7172789344 ps
T1301 /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1670986122 Apr 16 03:52:18 PM PDT 24 Apr 16 03:53:26 PM PDT 24 3792595605 ps
T401 /workspace/coverage/cover_reg_top/82.xbar_random.2222673387 Apr 16 04:05:02 PM PDT 24 Apr 16 04:05:24 PM PDT 24 511791917 ps
T830 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3077504646 Apr 16 04:03:15 PM PDT 24 Apr 16 04:04:46 PM PDT 24 309140338 ps
T533 /workspace/coverage/cover_reg_top/23.chip_tl_errors.123525907 Apr 16 03:55:12 PM PDT 24 Apr 16 03:57:35 PM PDT 24 2965050766 ps
T836 /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1977431940 Apr 16 03:59:53 PM PDT 24 Apr 16 04:03:30 PM PDT 24 726593418 ps
T489 /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.1840624456 Apr 16 04:00:43 PM PDT 24 Apr 16 04:06:53 PM PDT 24 21603543203 ps
T546 /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3057520046 Apr 16 03:54:31 PM PDT 24 Apr 16 03:55:00 PM PDT 24 324826837 ps
T515 /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.1607582112 Apr 16 04:08:03 PM PDT 24 Apr 16 04:23:18 PM PDT 24 44269524055 ps
T1302 /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2050948113 Apr 16 03:58:46 PM PDT 24 Apr 16 03:59:27 PM PDT 24 1037722875 ps
T604 /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2709925649 Apr 16 04:05:53 PM PDT 24 Apr 16 04:06:00 PM PDT 24 46554117 ps
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