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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.25 95.38 94.39 95.68 95.08 97.38 99.58


Total test records in report: 2839
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T748 /workspace/coverage/default/71.chip_sw_all_escalation_resets.3106382074 Apr 16 04:54:05 PM PDT 24 Apr 16 05:04:42 PM PDT 24 5557578860 ps
T1016 /workspace/coverage/default/0.chip_sw_hmac_smoketest.193511644 Apr 16 04:21:24 PM PDT 24 Apr 16 04:26:11 PM PDT 24 3762711488 ps
T1017 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.778467138 Apr 16 04:44:45 PM PDT 24 Apr 16 04:53:18 PM PDT 24 5558712360 ps
T1018 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2054329179 Apr 16 04:19:41 PM PDT 24 Apr 16 04:29:30 PM PDT 24 3501362824 ps
T1019 /workspace/coverage/default/3.chip_tap_straps_prod.2078229937 Apr 16 04:42:54 PM PDT 24 Apr 16 05:08:16 PM PDT 24 12502507849 ps
T715 /workspace/coverage/default/52.chip_sw_all_escalation_resets.2571417331 Apr 16 04:51:56 PM PDT 24 Apr 16 05:02:59 PM PDT 24 6050636948 ps
T1020 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2818096043 Apr 16 04:29:15 PM PDT 24 Apr 16 04:40:55 PM PDT 24 4203218352 ps
T791 /workspace/coverage/default/91.chip_sw_all_escalation_resets.112329960 Apr 16 04:52:14 PM PDT 24 Apr 16 05:02:10 PM PDT 24 4517905828 ps
T1021 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.785722003 Apr 16 04:17:51 PM PDT 24 Apr 16 04:26:21 PM PDT 24 5530732836 ps
T1022 /workspace/coverage/default/1.chip_sw_aes_enc.2886644713 Apr 16 04:25:11 PM PDT 24 Apr 16 04:31:20 PM PDT 24 2786484096 ps
T774 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2309347530 Apr 16 04:46:48 PM PDT 24 Apr 16 04:51:49 PM PDT 24 3409113040 ps
T1023 /workspace/coverage/default/0.chip_sw_csrng_kat_test.2907514858 Apr 16 04:17:21 PM PDT 24 Apr 16 04:21:38 PM PDT 24 2789817776 ps
T1024 /workspace/coverage/default/1.chip_sw_csrng_kat_test.1879402950 Apr 16 04:27:14 PM PDT 24 Apr 16 04:31:27 PM PDT 24 3022248530 ps
T520 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3115154270 Apr 16 04:16:04 PM PDT 24 Apr 16 04:31:14 PM PDT 24 4770858016 ps
T164 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3902521930 Apr 16 04:34:21 PM PDT 24 Apr 16 04:36:07 PM PDT 24 2175816342 ps
T1025 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3284931015 Apr 16 04:33:59 PM PDT 24 Apr 16 04:43:55 PM PDT 24 4358357464 ps
T1026 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.4245720024 Apr 16 04:37:15 PM PDT 24 Apr 16 04:45:45 PM PDT 24 5115512950 ps
T1027 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3645196998 Apr 16 04:37:01 PM PDT 24 Apr 16 04:40:40 PM PDT 24 2974045865 ps
T783 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4217960307 Apr 16 04:49:12 PM PDT 24 Apr 16 04:55:13 PM PDT 24 4028192680 ps
T660 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1538880264 Apr 16 04:20:00 PM PDT 24 Apr 16 04:28:34 PM PDT 24 4062565684 ps
T785 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1398917267 Apr 16 04:53:32 PM PDT 24 Apr 16 04:59:51 PM PDT 24 3424929368 ps
T1028 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1262133181 Apr 16 04:35:06 PM PDT 24 Apr 16 04:47:09 PM PDT 24 4635827707 ps
T40 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1777937601 Apr 16 04:17:04 PM PDT 24 Apr 16 04:28:15 PM PDT 24 5550540792 ps
T172 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3338776529 Apr 16 04:17:37 PM PDT 24 Apr 16 04:20:26 PM PDT 24 3130754904 ps
T149 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1545156793 Apr 16 04:23:04 PM PDT 24 Apr 16 07:19:31 PM PDT 24 58607650392 ps
T231 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2195312025 Apr 16 04:19:18 PM PDT 24 Apr 16 04:35:06 PM PDT 24 5047584864 ps
T1029 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2160974747 Apr 16 04:17:34 PM PDT 24 Apr 16 04:54:29 PM PDT 24 21631439406 ps
T25 /workspace/coverage/default/0.chip_sw_usbdev_dpi.28683220 Apr 16 04:18:07 PM PDT 24 Apr 16 05:05:43 PM PDT 24 11753211120 ps
T1030 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1070258482 Apr 16 04:19:46 PM PDT 24 Apr 16 04:29:55 PM PDT 24 4927357680 ps
T1031 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3408035236 Apr 16 04:45:42 PM PDT 24 Apr 16 04:49:49 PM PDT 24 3499829500 ps
T1032 /workspace/coverage/default/0.chip_sw_aes_entropy.3773414323 Apr 16 04:17:03 PM PDT 24 Apr 16 04:21:16 PM PDT 24 2740545640 ps
T1033 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1129328432 Apr 16 04:33:43 PM PDT 24 Apr 16 04:50:46 PM PDT 24 6006098869 ps
T1034 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.638327119 Apr 16 04:44:04 PM PDT 24 Apr 16 05:24:52 PM PDT 24 13125080410 ps
T1035 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2949425270 Apr 16 04:45:03 PM PDT 24 Apr 16 04:53:37 PM PDT 24 6977260726 ps
T714 /workspace/coverage/default/27.chip_sw_all_escalation_resets.1935208611 Apr 16 04:46:13 PM PDT 24 Apr 16 04:56:22 PM PDT 24 6130995862 ps
T760 /workspace/coverage/default/31.chip_sw_all_escalation_resets.1488902496 Apr 16 04:53:32 PM PDT 24 Apr 16 05:01:38 PM PDT 24 6013842024 ps
T1036 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1593499584 Apr 16 04:19:07 PM PDT 24 Apr 16 05:22:19 PM PDT 24 16758556360 ps
T1037 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1392186564 Apr 16 04:36:17 PM PDT 24 Apr 16 04:54:48 PM PDT 24 5787332664 ps
T1038 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.574909509 Apr 16 04:19:29 PM PDT 24 Apr 16 05:54:22 PM PDT 24 50023329832 ps
T1039 /workspace/coverage/default/0.chip_sw_csrng_smoketest.1544322250 Apr 16 04:20:50 PM PDT 24 Apr 16 04:25:14 PM PDT 24 3002952900 ps
T1040 /workspace/coverage/default/1.chip_sw_edn_kat.1656558912 Apr 16 04:26:40 PM PDT 24 Apr 16 04:38:43 PM PDT 24 3501437274 ps
T232 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1322678638 Apr 16 04:35:45 PM PDT 24 Apr 16 04:55:21 PM PDT 24 5195744960 ps
T156 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2002387177 Apr 16 04:51:50 PM PDT 24 Apr 16 05:00:17 PM PDT 24 4108293358 ps
T1041 /workspace/coverage/default/2.chip_sw_aes_masking_off.2430933449 Apr 16 04:36:35 PM PDT 24 Apr 16 04:41:44 PM PDT 24 2898082411 ps
T246 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3419404268 Apr 16 04:22:15 PM PDT 24 Apr 16 04:31:49 PM PDT 24 5974120202 ps
T1042 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1667012648 Apr 16 04:16:27 PM PDT 24 Apr 16 05:17:48 PM PDT 24 18381909759 ps
T295 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1361778495 Apr 16 04:39:38 PM PDT 24 Apr 16 05:06:45 PM PDT 24 13692648640 ps
T1043 /workspace/coverage/default/3.chip_sw_uart_tx_rx.3329292376 Apr 16 04:42:39 PM PDT 24 Apr 16 04:51:24 PM PDT 24 3565204538 ps
T716 /workspace/coverage/default/95.chip_sw_all_escalation_resets.433053468 Apr 16 04:51:56 PM PDT 24 Apr 16 04:58:52 PM PDT 24 5712744430 ps
T109 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.576167511 Apr 16 04:38:30 PM PDT 24 Apr 16 04:45:11 PM PDT 24 7124995196 ps
T97 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793845075 Apr 16 04:54:13 PM PDT 24 Apr 16 04:59:09 PM PDT 24 2878434000 ps
T1044 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.520751571 Apr 16 04:24:47 PM PDT 24 Apr 16 04:54:31 PM PDT 24 13128513773 ps
T1045 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3009685854 Apr 16 04:16:15 PM PDT 24 Apr 16 04:27:20 PM PDT 24 4181755264 ps
T27 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3860007208 Apr 16 04:23:15 PM PDT 24 Apr 16 04:28:26 PM PDT 24 3625904120 ps
T1046 /workspace/coverage/default/0.chip_sw_power_sleep_load.2953351088 Apr 16 04:18:12 PM PDT 24 Apr 16 04:26:43 PM PDT 24 10176885320 ps
T357 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3162856691 Apr 16 04:33:41 PM PDT 24 Apr 16 04:43:20 PM PDT 24 4287051476 ps
T1047 /workspace/coverage/default/0.chip_sw_aon_timer_irq.4023719030 Apr 16 04:18:40 PM PDT 24 Apr 16 04:26:16 PM PDT 24 3825000842 ps
T1048 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.268675254 Apr 16 04:23:26 PM PDT 24 Apr 16 04:42:37 PM PDT 24 5595110868 ps
T772 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3442468705 Apr 16 04:47:42 PM PDT 24 Apr 16 04:56:18 PM PDT 24 4014547340 ps
T348 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.4174237266 Apr 16 04:36:55 PM PDT 24 Apr 16 04:49:46 PM PDT 24 7671676599 ps
T1049 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.36701508 Apr 16 04:18:10 PM PDT 24 Apr 16 04:30:51 PM PDT 24 4390811344 ps
T1050 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1456852144 Apr 16 04:34:20 PM PDT 24 Apr 16 04:50:16 PM PDT 24 5948206960 ps
T28 /workspace/coverage/default/0.chip_sw_gpio.4259267002 Apr 16 04:18:20 PM PDT 24 Apr 16 04:26:35 PM PDT 24 4189365300 ps
T1051 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3231376894 Apr 16 04:37:55 PM PDT 24 Apr 16 04:46:44 PM PDT 24 4623465608 ps
T1052 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1094191150 Apr 16 04:23:45 PM PDT 24 Apr 16 05:31:28 PM PDT 24 14435524176 ps
T1053 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3566630493 Apr 16 04:23:22 PM PDT 24 Apr 16 04:29:27 PM PDT 24 3569574170 ps
T1054 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2975064278 Apr 16 04:33:10 PM PDT 24 Apr 16 04:38:57 PM PDT 24 2678227190 ps
T1055 /workspace/coverage/default/0.chip_sival_flash_info_access.2611704147 Apr 16 04:15:59 PM PDT 24 Apr 16 04:22:02 PM PDT 24 3157854218 ps
T1056 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3130075959 Apr 16 04:14:54 PM PDT 24 Apr 16 04:22:42 PM PDT 24 4270755646 ps
T1057 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.720947567 Apr 16 04:45:47 PM PDT 24 Apr 16 04:51:59 PM PDT 24 3821388588 ps
T1058 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1527060152 Apr 16 04:46:38 PM PDT 24 Apr 16 04:56:02 PM PDT 24 4203707730 ps
T1059 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.895074744 Apr 16 04:35:01 PM PDT 24 Apr 16 05:14:44 PM PDT 24 21489142810 ps
T653 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1556480500 Apr 16 04:20:37 PM PDT 24 Apr 16 05:16:55 PM PDT 24 24079188733 ps
T86 /workspace/coverage/default/1.chip_jtag_csr_rw.1576584539 Apr 16 04:22:42 PM PDT 24 Apr 16 05:08:10 PM PDT 24 21047580302 ps
T1060 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3123865909 Apr 16 04:17:54 PM PDT 24 Apr 16 04:26:06 PM PDT 24 5146215812 ps
T349 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1716793741 Apr 16 04:45:42 PM PDT 24 Apr 16 04:50:46 PM PDT 24 4034898080 ps
T36 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3651157043 Apr 16 04:22:32 PM PDT 24 Apr 16 04:26:47 PM PDT 24 2793511940 ps
T1061 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1077549291 Apr 16 04:38:27 PM PDT 24 Apr 16 05:11:57 PM PDT 24 10356975836 ps
T305 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2650466316 Apr 16 04:27:16 PM PDT 24 Apr 16 04:50:41 PM PDT 24 5685893962 ps
T428 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2047241994 Apr 16 04:19:24 PM PDT 24 Apr 16 04:31:48 PM PDT 24 4727778876 ps
T1062 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2652361974 Apr 16 04:16:56 PM PDT 24 Apr 16 04:48:56 PM PDT 24 8512788262 ps
T61 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2507380839 Apr 16 04:18:30 PM PDT 24 Apr 16 04:26:24 PM PDT 24 4522860424 ps
T298 /workspace/coverage/default/2.chip_plic_all_irqs_20.3176231670 Apr 16 04:37:11 PM PDT 24 Apr 16 04:50:53 PM PDT 24 4453581350 ps
T163 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.580194243 Apr 16 04:22:28 PM PDT 24 Apr 16 04:24:01 PM PDT 24 2188626456 ps
T1063 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2395524934 Apr 16 04:29:46 PM PDT 24 Apr 16 04:49:50 PM PDT 24 6710969277 ps
T1064 /workspace/coverage/default/1.rom_e2e_asm_init_rma.2234291297 Apr 16 04:37:38 PM PDT 24 Apr 16 05:29:45 PM PDT 24 14990574977 ps
T166 /workspace/coverage/default/98.chip_sw_all_escalation_resets.337301093 Apr 16 04:52:08 PM PDT 24 Apr 16 05:01:04 PM PDT 24 5196225280 ps
T1065 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.499942579 Apr 16 04:17:11 PM PDT 24 Apr 16 04:27:54 PM PDT 24 4484331000 ps
T1066 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1000716228 Apr 16 04:20:09 PM PDT 24 Apr 16 04:24:48 PM PDT 24 2560393064 ps
T1067 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2410850537 Apr 16 04:34:29 PM PDT 24 Apr 16 04:38:17 PM PDT 24 2294642044 ps
T1068 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.201060864 Apr 16 04:42:45 PM PDT 24 Apr 16 04:52:57 PM PDT 24 4566163480 ps
T247 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3754902396 Apr 16 04:46:34 PM PDT 24 Apr 16 04:53:52 PM PDT 24 4375678592 ps
T1069 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2512177649 Apr 16 04:43:27 PM PDT 24 Apr 16 04:47:57 PM PDT 24 2531264494 ps
T758 /workspace/coverage/default/47.chip_sw_all_escalation_resets.830126765 Apr 16 04:49:27 PM PDT 24 Apr 16 04:59:13 PM PDT 24 4869265080 ps
T1070 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1684077104 Apr 16 04:20:55 PM PDT 24 Apr 16 04:25:16 PM PDT 24 3290099544 ps
T90 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3532570234 Apr 16 04:17:15 PM PDT 24 Apr 16 04:21:16 PM PDT 24 3393212347 ps
T1071 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3793010508 Apr 16 04:43:06 PM PDT 24 Apr 16 04:55:33 PM PDT 24 5751418252 ps
T1072 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2470327150 Apr 16 04:33:45 PM PDT 24 Apr 16 04:55:52 PM PDT 24 8537678914 ps
T307 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2153190834 Apr 16 04:22:22 PM PDT 24 Apr 16 04:38:37 PM PDT 24 4856203668 ps
T173 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2610357283 Apr 16 04:15:21 PM PDT 24 Apr 16 04:20:15 PM PDT 24 3346240867 ps
T1073 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2440226614 Apr 16 04:23:49 PM PDT 24 Apr 16 04:36:22 PM PDT 24 4386750060 ps
T1074 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3743471437 Apr 16 04:19:58 PM PDT 24 Apr 16 04:29:23 PM PDT 24 4736141082 ps
T63 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2001444153 Apr 16 04:33:25 PM PDT 24 Apr 16 04:38:36 PM PDT 24 3132762520 ps
T1075 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1635293420 Apr 16 04:19:53 PM PDT 24 Apr 16 04:30:18 PM PDT 24 6150517764 ps
T1076 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3695111968 Apr 16 04:46:13 PM PDT 24 Apr 16 04:56:18 PM PDT 24 4547779384 ps
T154 /workspace/coverage/default/2.chip_plic_all_irqs_10.1598069629 Apr 16 04:37:46 PM PDT 24 Apr 16 04:49:20 PM PDT 24 4413849082 ps
T1077 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3661727951 Apr 16 04:45:43 PM PDT 24 Apr 16 04:49:38 PM PDT 24 2527945520 ps
T1078 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064817713 Apr 16 04:48:19 PM PDT 24 Apr 16 04:55:48 PM PDT 24 4025926376 ps
T1079 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.56948982 Apr 16 04:24:16 PM PDT 24 Apr 16 04:30:09 PM PDT 24 4809790680 ps
T724 /workspace/coverage/default/79.chip_sw_all_escalation_resets.3966223306 Apr 16 04:51:33 PM PDT 24 Apr 16 05:00:20 PM PDT 24 5984153544 ps
T773 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4220421280 Apr 16 04:44:07 PM PDT 24 Apr 16 04:49:49 PM PDT 24 3461975064 ps
T1080 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2545246926 Apr 16 04:37:42 PM PDT 24 Apr 16 04:49:34 PM PDT 24 5468320020 ps
T144 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3430109519 Apr 16 04:23:40 PM PDT 24 Apr 16 04:33:58 PM PDT 24 8837939707 ps
T78 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.4158491302 Apr 16 04:17:39 PM PDT 24 Apr 16 04:26:09 PM PDT 24 3464760004 ps
T1081 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2124275200 Apr 16 04:23:29 PM PDT 24 Apr 16 04:30:10 PM PDT 24 5991971260 ps
T150 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1325618973 Apr 16 04:17:54 PM PDT 24 Apr 16 07:17:07 PM PDT 24 57950795740 ps
T1082 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3461561886 Apr 16 04:45:32 PM PDT 24 Apr 16 05:12:37 PM PDT 24 8202833796 ps
T1083 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.696580331 Apr 16 04:43:55 PM PDT 24 Apr 16 05:06:53 PM PDT 24 13150644240 ps
T522 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.118155064 Apr 16 04:19:01 PM PDT 24 Apr 16 04:29:37 PM PDT 24 3846544040 ps
T1084 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2033380203 Apr 16 04:35:54 PM PDT 24 Apr 16 04:38:08 PM PDT 24 3038511940 ps
T315 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2384647955 Apr 16 04:22:02 PM PDT 24 Apr 16 04:37:06 PM PDT 24 4693056860 ps
T1085 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.4024662161 Apr 16 04:21:24 PM PDT 24 Apr 16 04:33:24 PM PDT 24 6535415520 ps
T1086 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3069493020 Apr 16 04:23:35 PM PDT 24 Apr 16 04:35:08 PM PDT 24 4169596776 ps
T1087 /workspace/coverage/default/4.chip_tap_straps_dev.990367116 Apr 16 04:44:05 PM PDT 24 Apr 16 04:47:20 PM PDT 24 3168523657 ps
T787 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3920306465 Apr 16 04:46:49 PM PDT 24 Apr 16 04:57:58 PM PDT 24 6064085752 ps
T1088 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1371109968 Apr 16 04:29:56 PM PDT 24 Apr 16 04:33:28 PM PDT 24 2344237875 ps
T60 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.80106547 Apr 16 04:29:35 PM PDT 24 Apr 16 04:55:43 PM PDT 24 19820497502 ps
T1089 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3259161138 Apr 16 04:36:40 PM PDT 24 Apr 16 04:40:36 PM PDT 24 2212509448 ps
T1090 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.663641016 Apr 16 04:34:53 PM PDT 24 Apr 16 04:44:26 PM PDT 24 5321963448 ps
T1091 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.707729337 Apr 16 04:19:48 PM PDT 24 Apr 16 04:30:33 PM PDT 24 7845736720 ps
T240 /workspace/coverage/default/2.chip_jtag_mem_access.3056088936 Apr 16 04:31:28 PM PDT 24 Apr 16 04:55:27 PM PDT 24 13150109795 ps
T157 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1076033550 Apr 16 04:25:37 PM PDT 24 Apr 16 04:49:40 PM PDT 24 10858910040 ps
T216 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.492677625 Apr 16 04:36:48 PM PDT 24 Apr 16 04:48:55 PM PDT 24 5065264760 ps
T1092 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.536390753 Apr 16 04:33:11 PM PDT 24 Apr 16 04:54:00 PM PDT 24 8067207908 ps
T29 /workspace/coverage/default/1.chip_sw_gpio.1212034808 Apr 16 04:21:29 PM PDT 24 Apr 16 04:29:01 PM PDT 24 3884897040 ps
T1093 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2677933097 Apr 16 04:40:16 PM PDT 24 Apr 16 05:04:45 PM PDT 24 7710610713 ps
T308 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1714987223 Apr 16 04:17:52 PM PDT 24 Apr 16 04:33:50 PM PDT 24 4955326078 ps
T1094 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4095574138 Apr 16 04:24:20 PM PDT 24 Apr 16 05:05:40 PM PDT 24 10521358870 ps
T1095 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1810638745 Apr 16 04:27:27 PM PDT 24 Apr 16 04:32:12 PM PDT 24 2739716166 ps
T1096 /workspace/coverage/default/0.chip_sw_gpio_smoketest.613346764 Apr 16 04:23:22 PM PDT 24 Apr 16 04:27:17 PM PDT 24 3002105473 ps
T709 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2762596132 Apr 16 04:37:48 PM PDT 24 Apr 16 05:35:13 PM PDT 24 20301358316 ps
T658 /workspace/coverage/default/1.chip_sw_edn_boot_mode.1828368414 Apr 16 04:25:57 PM PDT 24 Apr 16 04:35:20 PM PDT 24 3009331000 ps
T248 /workspace/coverage/default/5.chip_sw_all_escalation_resets.567859187 Apr 16 04:43:55 PM PDT 24 Apr 16 04:54:18 PM PDT 24 6120912550 ps
T1097 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.471825440 Apr 16 04:26:45 PM PDT 24 Apr 16 04:35:46 PM PDT 24 5194032232 ps
T179 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1985920654 Apr 16 04:35:44 PM PDT 24 Apr 16 05:56:19 PM PDT 24 43410882689 ps
T1098 /workspace/coverage/default/0.chip_sw_usbdev_vbus.1523356034 Apr 16 04:16:51 PM PDT 24 Apr 16 04:21:18 PM PDT 24 3247565308 ps
T350 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2392778799 Apr 16 04:47:58 PM PDT 24 Apr 16 04:55:26 PM PDT 24 3871870216 ps
T1099 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.877077166 Apr 16 04:32:21 PM PDT 24 Apr 16 04:37:40 PM PDT 24 3203583062 ps
T1100 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3541492815 Apr 16 04:26:56 PM PDT 24 Apr 16 04:34:11 PM PDT 24 3307336934 ps
T1101 /workspace/coverage/default/4.chip_tap_straps_testunlock0.1601068165 Apr 16 04:43:03 PM PDT 24 Apr 16 05:07:48 PM PDT 24 11812655213 ps
T118 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1605233841 Apr 16 04:41:18 PM PDT 24 Apr 16 05:19:30 PM PDT 24 14531629079 ps
T355 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1086578314 Apr 16 04:21:39 PM PDT 24 Apr 16 04:34:18 PM PDT 24 4918455736 ps
T705 /workspace/coverage/default/1.chip_sw_pattgen_ios.2443314731 Apr 16 04:23:08 PM PDT 24 Apr 16 04:26:36 PM PDT 24 2655422072 ps
T769 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3983357060 Apr 16 04:52:05 PM PDT 24 Apr 16 05:02:46 PM PDT 24 4738604798 ps
T324 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1842214579 Apr 16 04:17:14 PM PDT 24 Apr 16 04:21:12 PM PDT 24 2935574584 ps
T1102 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1232300284 Apr 16 04:17:47 PM PDT 24 Apr 16 04:37:27 PM PDT 24 7750832104 ps
T1103 /workspace/coverage/default/1.chip_sw_kmac_idle.943003726 Apr 16 04:27:27 PM PDT 24 Apr 16 04:30:43 PM PDT 24 2852537156 ps
T1104 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2422849588 Apr 16 04:37:37 PM PDT 24 Apr 16 04:47:15 PM PDT 24 4667702652 ps
T30 /workspace/coverage/default/2.chip_sw_gpio.292790417 Apr 16 04:34:28 PM PDT 24 Apr 16 04:44:15 PM PDT 24 3533050136 ps
T654 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3958772403 Apr 16 04:30:49 PM PDT 24 Apr 16 05:39:41 PM PDT 24 25293227757 ps
T1105 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3060473207 Apr 16 04:43:17 PM PDT 24 Apr 16 05:09:17 PM PDT 24 7931165336 ps
T713 /workspace/coverage/default/32.chip_sw_all_escalation_resets.493797973 Apr 16 04:53:20 PM PDT 24 Apr 16 05:04:17 PM PDT 24 5788852284 ps
T1106 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2654313426 Apr 16 04:38:08 PM PDT 24 Apr 16 04:42:02 PM PDT 24 2224244758 ps
T1107 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1202037451 Apr 16 04:23:53 PM PDT 24 Apr 16 05:31:25 PM PDT 24 17078548912 ps
T1108 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.360910785 Apr 16 04:34:41 PM PDT 24 Apr 16 04:38:25 PM PDT 24 3256044628 ps
T275 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.304591324 Apr 16 04:48:21 PM PDT 24 Apr 16 04:56:24 PM PDT 24 4169882110 ps
T1109 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.4081180821 Apr 16 04:18:25 PM PDT 24 Apr 16 04:40:15 PM PDT 24 6474896056 ps
T1110 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3041091848 Apr 16 04:22:58 PM PDT 24 Apr 16 04:27:03 PM PDT 24 2764573318 ps
T1111 /workspace/coverage/default/36.chip_sw_all_escalation_resets.2920310298 Apr 16 04:49:09 PM PDT 24 Apr 16 05:01:35 PM PDT 24 4850551142 ps
T1112 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.4059212727 Apr 16 04:36:11 PM PDT 24 Apr 16 04:55:31 PM PDT 24 9763450625 ps
T1113 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.658066437 Apr 16 04:34:12 PM PDT 24 Apr 16 04:40:50 PM PDT 24 3010755812 ps
T1114 /workspace/coverage/default/0.chip_sw_aes_enc.4086465441 Apr 16 04:17:59 PM PDT 24 Apr 16 04:22:56 PM PDT 24 2657444200 ps
T759 /workspace/coverage/default/60.chip_sw_all_escalation_resets.1082495281 Apr 16 04:51:28 PM PDT 24 Apr 16 05:02:10 PM PDT 24 4506572720 ps
T1115 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.135725211 Apr 16 04:45:10 PM PDT 24 Apr 16 05:22:20 PM PDT 24 12944472904 ps
T1116 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1754312447 Apr 16 04:31:38 PM PDT 24 Apr 16 04:38:32 PM PDT 24 5476439760 ps
T310 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1799652018 Apr 16 04:33:54 PM PDT 24 Apr 16 04:49:12 PM PDT 24 4571766324 ps
T1117 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1261202511 Apr 16 04:36:00 PM PDT 24 Apr 16 05:02:23 PM PDT 24 7693740020 ps
T333 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2620625471 Apr 16 04:17:58 PM PDT 24 Apr 16 04:25:17 PM PDT 24 18874962544 ps
T362 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1461715655 Apr 16 04:41:06 PM PDT 24 Apr 16 04:45:50 PM PDT 24 2396885440 ps
T694 /workspace/coverage/default/0.chip_sw_plic_sw_irq.681522636 Apr 16 04:20:14 PM PDT 24 Apr 16 04:24:20 PM PDT 24 3157145372 ps
T1118 /workspace/coverage/default/1.chip_sw_uart_tx_rx.1586336438 Apr 16 04:23:12 PM PDT 24 Apr 16 04:34:29 PM PDT 24 3909055644 ps
T751 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3289054479 Apr 16 04:49:45 PM PDT 24 Apr 16 04:56:20 PM PDT 24 3224630992 ps
T1119 /workspace/coverage/default/39.chip_sw_all_escalation_resets.3274156491 Apr 16 04:48:47 PM PDT 24 Apr 16 04:57:26 PM PDT 24 5359453280 ps
T217 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2485690689 Apr 16 04:19:11 PM PDT 24 Apr 16 04:30:30 PM PDT 24 5201713160 ps
T1120 /workspace/coverage/default/1.chip_sw_aes_entropy.2732650038 Apr 16 04:25:38 PM PDT 24 Apr 16 04:30:58 PM PDT 24 2461900676 ps
T1121 /workspace/coverage/default/2.rom_volatile_raw_unlock.1472452564 Apr 16 04:42:06 PM PDT 24 Apr 16 04:43:46 PM PDT 24 2285906112 ps
T1122 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.305581192 Apr 16 04:25:26 PM PDT 24 Apr 16 04:33:38 PM PDT 24 5414776444 ps
T1123 /workspace/coverage/default/2.chip_sw_aon_timer_irq.2335060656 Apr 16 04:35:27 PM PDT 24 Apr 16 04:43:21 PM PDT 24 4127784952 ps
T276 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1427286086 Apr 16 04:44:42 PM PDT 24 Apr 16 04:50:14 PM PDT 24 3537566452 ps
T1124 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.401224528 Apr 16 04:45:45 PM PDT 24 Apr 16 04:55:58 PM PDT 24 5450170759 ps
T1125 /workspace/coverage/default/2.chip_sw_edn_kat.337763803 Apr 16 04:37:57 PM PDT 24 Apr 16 04:47:47 PM PDT 24 2976143254 ps
T1126 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2670232865 Apr 16 04:28:32 PM PDT 24 Apr 16 04:45:52 PM PDT 24 8716190500 ps
T1127 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2901174513 Apr 16 04:35:20 PM PDT 24 Apr 16 07:32:44 PM PDT 24 254867465148 ps
T766 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.472169292 Apr 16 04:50:53 PM PDT 24 Apr 16 04:57:31 PM PDT 24 3641970680 ps
T1128 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3516885102 Apr 16 04:45:09 PM PDT 24 Apr 16 04:53:05 PM PDT 24 4539567200 ps
T1129 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1481256115 Apr 16 04:35:00 PM PDT 24 Apr 16 05:29:05 PM PDT 24 18562751086 ps
T202 /workspace/coverage/default/0.chip_jtag_csr_rw.650388845 Apr 16 04:10:04 PM PDT 24 Apr 16 04:51:01 PM PDT 24 20074280600 ps
T1130 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4003521130 Apr 16 04:32:33 PM PDT 24 Apr 16 04:44:02 PM PDT 24 4030285764 ps
T717 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.777991275 Apr 16 04:51:56 PM PDT 24 Apr 16 04:56:32 PM PDT 24 3310026036 ps
T1131 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.425824673 Apr 16 04:16:01 PM PDT 24 Apr 16 04:24:18 PM PDT 24 3949984720 ps
T1132 /workspace/coverage/default/2.chip_sw_uart_smoketest.2173304378 Apr 16 04:42:07 PM PDT 24 Apr 16 04:45:45 PM PDT 24 2945247204 ps
T1133 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4071751711 Apr 16 04:29:20 PM PDT 24 Apr 16 04:40:48 PM PDT 24 5016789864 ps
T1134 /workspace/coverage/default/0.chip_sw_kmac_entropy.1062684685 Apr 16 04:18:20 PM PDT 24 Apr 16 04:23:02 PM PDT 24 2263085692 ps
T185 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3800786456 Apr 16 04:17:51 PM PDT 24 Apr 16 04:36:42 PM PDT 24 9377107812 ps
T1135 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3638607965 Apr 16 04:44:09 PM PDT 24 Apr 16 04:53:29 PM PDT 24 6906442387 ps
T753 /workspace/coverage/default/76.chip_sw_all_escalation_resets.4156389585 Apr 16 04:52:23 PM PDT 24 Apr 16 05:00:36 PM PDT 24 5257311000 ps
T1136 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.53402679 Apr 16 04:24:44 PM PDT 24 Apr 16 04:44:15 PM PDT 24 5247969658 ps
T1137 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2898752003 Apr 16 04:16:41 PM PDT 24 Apr 16 04:38:06 PM PDT 24 8652889784 ps
T784 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2796574581 Apr 16 04:52:39 PM PDT 24 Apr 16 04:59:55 PM PDT 24 3727446188 ps
T1138 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2334557056 Apr 16 04:18:29 PM PDT 24 Apr 16 04:24:58 PM PDT 24 3751244391 ps
T1139 /workspace/coverage/default/1.chip_sw_uart_smoketest.1020620227 Apr 16 04:32:25 PM PDT 24 Apr 16 04:35:47 PM PDT 24 2276892168 ps
T1140 /workspace/coverage/default/65.chip_sw_all_escalation_resets.2217041703 Apr 16 04:50:55 PM PDT 24 Apr 16 05:03:09 PM PDT 24 6116769240 ps
T1141 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2448890055 Apr 16 04:36:44 PM PDT 24 Apr 16 04:51:15 PM PDT 24 4418161166 ps
T1142 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1351693618 Apr 16 04:24:32 PM PDT 24 Apr 16 04:57:20 PM PDT 24 9610880566 ps
T1143 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1788665270 Apr 16 04:28:56 PM PDT 24 Apr 16 04:34:01 PM PDT 24 2490837647 ps
T1144 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1619097158 Apr 16 04:23:39 PM PDT 24 Apr 16 05:13:28 PM PDT 24 12047761820 ps
T1145 /workspace/coverage/default/2.chip_sw_aes_enc.3241673396 Apr 16 04:36:03 PM PDT 24 Apr 16 04:41:21 PM PDT 24 3071502080 ps
T727 /workspace/coverage/default/48.chip_sw_all_escalation_resets.2338587319 Apr 16 04:48:16 PM PDT 24 Apr 16 05:01:32 PM PDT 24 6148079286 ps
T1146 /workspace/coverage/default/0.rom_e2e_asm_init_dev.2485510243 Apr 16 04:24:14 PM PDT 24 Apr 16 05:19:06 PM PDT 24 14782470215 ps
T1147 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1459973724 Apr 16 04:20:53 PM PDT 24 Apr 16 07:50:40 PM PDT 24 255934455544 ps
T1148 /workspace/coverage/default/2.chip_sw_plic_sw_irq.1493720083 Apr 16 04:37:39 PM PDT 24 Apr 16 04:42:54 PM PDT 24 2839211670 ps
T744 /workspace/coverage/default/12.chip_sw_all_escalation_resets.4161358670 Apr 16 04:44:35 PM PDT 24 Apr 16 04:55:53 PM PDT 24 6098305648 ps
T710 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2736193519 Apr 16 04:24:24 PM PDT 24 Apr 16 05:21:44 PM PDT 24 20812591713 ps
T1149 /workspace/coverage/default/1.chip_sw_edn_sw_mode.1483800613 Apr 16 04:25:58 PM PDT 24 Apr 16 04:51:37 PM PDT 24 6693822456 ps
T1150 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.867324560 Apr 16 04:14:53 PM PDT 24 Apr 16 04:23:41 PM PDT 24 3806045820 ps
T1151 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1510994574 Apr 16 04:19:07 PM PDT 24 Apr 16 04:31:28 PM PDT 24 5983441412 ps
T1152 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2732160291 Apr 16 04:33:39 PM PDT 24 Apr 16 04:55:20 PM PDT 24 8621032995 ps
T1153 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2004051792 Apr 16 04:22:59 PM PDT 24 Apr 16 04:25:38 PM PDT 24 3492257722 ps
T1154 /workspace/coverage/default/94.chip_sw_all_escalation_resets.4249863915 Apr 16 04:55:56 PM PDT 24 Apr 16 05:04:54 PM PDT 24 4918190280 ps
T1155 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3691355042 Apr 16 04:21:38 PM PDT 24 Apr 16 04:37:46 PM PDT 24 8097170224 ps
T1156 /workspace/coverage/default/0.chip_sw_usbdev_stream.1951053875 Apr 16 04:17:25 PM PDT 24 Apr 16 05:32:36 PM PDT 24 18181573476 ps
T1157 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.26562491 Apr 16 04:41:56 PM PDT 24 Apr 16 04:46:14 PM PDT 24 2312864490 ps
T1158 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3404012612 Apr 16 04:43:23 PM PDT 24 Apr 16 04:57:55 PM PDT 24 5288149980 ps
T365 /workspace/coverage/default/13.chip_sw_all_escalation_resets.2032392873 Apr 16 04:45:19 PM PDT 24 Apr 16 04:53:38 PM PDT 24 5608025936 ps
T755 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227089480 Apr 16 04:51:27 PM PDT 24 Apr 16 04:56:10 PM PDT 24 3645823000 ps
T229 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3798491110 Apr 16 04:16:02 PM PDT 24 Apr 16 04:25:29 PM PDT 24 4322730424 ps
T1159 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2221524251 Apr 16 04:36:25 PM PDT 24 Apr 16 04:49:20 PM PDT 24 9996181240 ps
T1160 /workspace/coverage/default/1.chip_sw_example_concurrency.3522870042 Apr 16 04:20:47 PM PDT 24 Apr 16 04:24:17 PM PDT 24 2790898944 ps
T1161 /workspace/coverage/default/0.rom_e2e_asm_init_rma.677210076 Apr 16 04:26:10 PM PDT 24 Apr 16 05:27:56 PM PDT 24 15635582914 ps
T1162 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3882343493 Apr 16 04:15:57 PM PDT 24 Apr 16 04:18:09 PM PDT 24 2769408739 ps
T137 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1249288828 Apr 16 04:42:05 PM PDT 24 Apr 16 04:53:32 PM PDT 24 6108206280 ps
T1163 /workspace/coverage/default/22.chip_sw_all_escalation_resets.3235049542 Apr 16 04:46:40 PM PDT 24 Apr 16 04:58:39 PM PDT 24 6038753000 ps
T734 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483902439 Apr 16 04:51:57 PM PDT 24 Apr 16 04:57:44 PM PDT 24 4074095280 ps
T1164 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1103087312 Apr 16 04:28:57 PM PDT 24 Apr 16 04:36:27 PM PDT 24 3941652556 ps
T1165 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.493681688 Apr 16 04:20:56 PM PDT 24 Apr 16 04:24:43 PM PDT 24 2680475496 ps
T1166 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2942877844 Apr 16 04:34:22 PM PDT 24 Apr 16 04:37:39 PM PDT 24 3250664055 ps
T281 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3734468381 Apr 16 04:40:08 PM PDT 24 Apr 16 04:44:05 PM PDT 24 2779026792 ps
T1167 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1711792438 Apr 16 04:30:27 PM PDT 24 Apr 16 04:38:33 PM PDT 24 5457780020 ps
T1168 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3383612647 Apr 16 04:16:33 PM PDT 24 Apr 16 04:33:43 PM PDT 24 5170493117 ps
T1169 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2433859344 Apr 16 04:23:19 PM PDT 24 Apr 16 04:45:34 PM PDT 24 5663648771 ps
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