CHIP Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.570m	2.524ms	3	3	100.00
		chip_sw_example_rom	2.207m	2.821ms	3	3	100.00
		chip_sw_example_manufacturer	4.456m	2.321ms	3	3	100.00
		chip_sw_example_concurrency	5.582m	2.753ms	3	3	100.00
		chip_sw_uart_smoketest_signed			0	3	0.00
V1	csr_hw_reset	chip_csr_hw_reset	7.808m	5.744ms	5	5	100.00
V1	csr_rw	chip_csr_rw	12.463m	5.614ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	29.537m	15.154ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.931h	52.773ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.946m	1.833ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.931h	52.773ms	4	5	80.00
		chip_csr_rw	12.463m	5.614ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.010s	256.865us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.769m	3.533ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.769m	3.533ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.769m	3.533ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	11.481m	4.842ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	11.481m	4.842ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	11.614m	4.111ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	11.936m	4.361ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.676m	4.326ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	50.495m	13.559ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	44.196m	12.740ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	31.778m	13.185ms	5	5	100.00
V1		TOTAL			199	223	89.24
V2	chip_pin_mux	chip_padctrl_attributes	6.550m	4.302ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	6.550m	4.302ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.683m	2.526ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.275m	5.453ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	7.869m	4.523ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	14.247m	8.562ms	5	5	100.00
		chip_tap_straps_testunlock0	24.742m	11.813ms	5	5	100.00
		chip_tap_straps_rma	15.865m	8.668ms	5	5	100.00
		chip_tap_straps_prod	37.965m	17.957ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.931m	3.603ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.051m	7.430ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.533m	5.288ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.533m	5.288ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.009m	7.807ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.037m	4.636ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.703m	6.145ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.136h	33.024ms	2	3	66.67
		chip_sw_aes_enc_jitter_en	5.854m	3.005ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.874m	6.074ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.815m	3.145ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	7.781m	5.165ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.745m	3.271ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.092m	4.437ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.080m	2.491ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	6.571m	3.661ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	15.251m	8.700ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.284m	5.137ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.274m	2.300ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.284m	5.137ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.474m	2.531ms	3	3	100.00
		chip_sw_aes_smoketest	6.397m	2.753ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.564m	3.055ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.825m	2.705ms	3	3	100.00
		chip_sw_csrng_smoketest	5.190m	2.800ms	3	3	100.00
		chip_sw_entropy_src_smoketest	7.675m	3.748ms	3	3	100.00
		chip_sw_gpio_smoketest	5.037m	3.424ms	3	3	100.00
		chip_sw_hmac_smoketest	6.799m	3.328ms	3	3	100.00
		chip_sw_kmac_smoketest	6.768m	3.209ms	3	3	100.00
		chip_sw_otbn_smoketest	26.668m	6.087ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.944m	3.050ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.117m	4.562ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.571m	5.668ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.007m	2.509ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.550m	2.580ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.589m	2.358ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	3.773m	2.295ms	3	3	100.00
		chip_sw_uart_smoketest	4.910m	2.813ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.666m	5.084ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed			0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.774h	77.543ms	2	3	66.67
V2	chip_sw_secure_boot	rom_e2e_smoke			0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	5.448h	204.570ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.804m	4.551ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.504m	10.177ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.986h	57.951ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.284h	65.472ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.840m	6.196ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.840m	6.196ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.931h	52.773ms	4	5	80.00
		chip_same_csr_outstanding	1.287h	28.473ms	20	20	100.00
		chip_csr_hw_reset	7.808m	5.744ms	5	5	100.00
		chip_csr_rw	12.463m	5.614ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.931h	52.773ms	4	5	80.00
		chip_same_csr_outstanding	1.287h	28.473ms	20	20	100.00
		chip_csr_hw_reset	7.808m	5.744ms	5	5	100.00
		chip_csr_rw	12.463m	5.614ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.692m	2.579ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.330s	55.073us	100	100	100.00
		xbar_smoke_large_delays	1.977m	10.124ms	100	100	100.00
		xbar_smoke_slow_rsp	2.074m	6.773ms	100	100	100.00
		xbar_random_zero_delays	55.010s	619.400us	100	100	100.00
		xbar_random_large_delays	23.233m	113.326ms	100	100	100.00
		xbar_random_slow_rsp	20.345m	69.087ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	57.770s	1.334ms	100	100	100.00
		xbar_error_and_unmapped_addr	59.160s	1.366ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.729m	2.655ms	100	100	100.00
		xbar_error_and_unmapped_addr	59.160s	1.366ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.510m	3.090ms	100	100	100.00
		xbar_access_same_device_slow_rsp	51.010m	166.389ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.436m	2.630ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	12.974m	18.816ms	100	100	100.00
		xbar_stress_all_with_error	13.584m	18.014ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	24.537m	26.456ms	100	100	100.00
		xbar_stress_all_with_reset_error	21.714m	24.392ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	57.727m	14.833ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	36.565m	9.259ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	58.160m	12.509ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	48.945m	12.231ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	48.792m	12.211ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	50.335m	12.407ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	38.789m	8.623ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	49.805m	12.048ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	49.486m	12.706ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	45.790m	11.748ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	49.588m	12.343ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	56.034m	13.669ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.196h	18.743ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.276h	18.969ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.208h	18.365ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.202h	18.565ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	49.221m	13.755ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.057h	18.658ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.425h	18.130ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.159h	18.057ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.094h	17.396ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	38.240m	10.356ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	51.402m	14.582ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.128h	14.436ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	54.460m	14.892ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	53.272m	14.778ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	40.478m	10.841ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	56.676m	14.508ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	1.022h	14.357ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	58.480m	15.034ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	45.261m	14.855ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	41.309m	10.521ms	3	3	100.00
		rom_e2e_asm_init_dev	1.030h	14.760ms	3	3	100.00
		rom_e2e_asm_init_prod	1.075h	15.011ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.049h	15.121ms	3	3	100.00
		rom_e2e_asm_init_rma	1.029h	15.636ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.272h	20.018ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.137m	2.786ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.854m	3.005ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	6.082m	3.278ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.286m	2.723ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	12.100m	5.065ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.890m	17.929ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.890m	17.929ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.893m	4.128ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.117m	4.562ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.893m	4.128ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.564m	7.990ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.564m	7.990ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.762m	7.223ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	8.770m	4.665ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	21.696m	6.395ms	3	3	100.00
		chip_sw_aes_idle	5.286m	2.723ms	3	3	100.00
		chip_sw_hmac_enc_idle	7.237m	3.307ms	3	3	100.00
		chip_sw_kmac_idle	4.201m	2.368ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.706m	4.126ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.048m	4.171ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	9.843m	4.549ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.810m	4.623ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	27.984m	12.754ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.660m	4.391ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.459m	5.017ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.641m	4.203ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.532m	4.349ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.938m	4.102ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.083m	4.878ms	3	3	100.00
		chip_sw_ast_clk_outputs	19.009m	7.807ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.782m	10.531ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.641m	4.203ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.532m	4.349ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.037m	4.636ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.703m	6.145ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.136h	33.024ms	2	3	66.67
		chip_sw_aes_enc_jitter_en	5.854m	3.005ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.874m	6.074ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.815m	3.145ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	7.781m	5.165ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.745m	3.271ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.092m	4.437ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.080m	2.491ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.624m	2.580ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.907m	5.004ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	24.487m	7.711ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.147h	25.293ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.990m	3.349ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.347m	2.878ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	7.058m	4.816ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.291m	3.448ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.394m	4.700ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	47.063m	22.975ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	54.329m	17.950ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.009m	7.807ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.861m	4.926ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.134m	3.192ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.361m	5.572ms	98	100	98.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	29.860m	8.628ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	23.649m	6.481ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.396m	4.121ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	15.457m	5.700ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.278m	2.790ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	21.398m	8.653ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	28.277m	21.404ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.772m	3.049ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	43.750s	10.340us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.470m	4.236ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	28.277m	21.404ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	28.277m	21.404ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.004h	20.911ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.004h	20.911ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	11.155m	5.551ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.890m	17.929ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	51.060m	13.267ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.748m	2.740ms	3	3	100.00
		chip_sw_edn_entropy_reqs	19.586m	5.196ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.748m	2.740ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	23.649m	6.481ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.957m	3.418ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	39.450m	25.511ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	19.163m	5.595ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.703m	6.145ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.796m	3.951ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.037m	4.636ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.438h	43.158ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	39.450m	25.511ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.087m	3.461ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	9.009m	5.194ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.400m	4.072ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.438h	43.158ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.400m	4.072ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.400m	4.072ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	10.400m	4.072ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.400m	4.072ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.361m	5.572ms	98	100	98.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	6.332m	9.683ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	22.242m	5.664ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.806m	5.841ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.806m	5.841ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.451m	3.504ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.815m	3.145ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	7.237m	3.307ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.157m	5.037ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	14.170m	5.379ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	16.234m	4.856ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.256m	4.328ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	9.009m	5.194ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	7.781m	5.165ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	11.510m	4.740ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	12.100m	5.065ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.312h	18.162ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.665m	2.510ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.600m	2.965ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.745m	3.271ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	9.009m	5.194ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	16.723m	10.582ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.125m	2.945ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.870m	3.073ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.201m	2.368ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.220m	4.906ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	14.247m	8.562ms	5	5	100.00
		chip_tap_straps_rma	15.865m	8.668ms	5	5	100.00
		chip_tap_straps_prod	37.965m	17.957ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.772m	2.678ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	16.723m	10.582ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	16.723m	10.582ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	16.723m	10.582ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.405m	4.736ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	10.400m	4.072ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.438h	43.158ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.530m	4.387ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.143m	8.028ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.098m	9.289ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.105m	9.366ms	3	3	100.00
		chip_sw_lc_ctrl_transition	16.723m	10.582ms	15	15	100.00
		chip_sw_keymgr_key_derivation	9.009m	5.194ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	10.489m	8.610ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	18.835m	9.377ms	3	3	100.00
		chip_prim_tl_access	6.332m	9.683ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.782m	10.531ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.660m	4.391ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.459m	5.017ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.641m	4.203ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.532m	4.349ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.938m	4.102ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.083m	4.878ms	3	3	100.00
		chip_tap_straps_dev	14.247m	8.562ms	5	5	100.00
		chip_tap_straps_rma	15.865m	8.668ms	5	5	100.00
		chip_tap_straps_prod	37.965m	17.957ms	5	5	100.00
		chip_rv_dm_lc_disabled	9.417m	14.192ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.383m	3.466ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.810m	3.131ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.178m	2.769ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.905m	3.346ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	35.559m	23.250ms	3	3	100.00
		chip_rv_dm_lc_disabled	9.417m	14.192ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.667h	46.976ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.697h	50.199ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	19.319m	9.763ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.483h	50.108ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	35.559m	23.250ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.223m	3.039ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.968m	2.330ms	3	3	100.00
		rom_volatile_raw_unlock	1.826m	2.889ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	16.723m	10.582ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	39.450m	25.511ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.162m	3.790ms	3	3	100.00
		chip_sw_keymgr_key_derivation	9.009m	5.194ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.565m	3.847ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.682m	2.747ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	39.450m	25.511ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.162m	3.790ms	3	3	100.00
		chip_sw_keymgr_key_derivation	9.009m	5.194ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.565m	3.847ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.682m	2.747ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	16.723m	10.582ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.368m	14.905ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.772m	2.678ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.530m	4.387ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.143m	8.028ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.098m	9.289ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.105m	9.366ms	3	3	100.00
		chip_sw_lc_ctrl_transition	16.723m	10.582ms	15	15	100.00
		chip_prim_tl_access	6.332m	9.683ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.332m	9.683ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.279m	8.838ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	32.072m	21.232ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.674m	7.125ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	14.874m	9.289ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.985m	6.456ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	37.480m	20.527ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	29.721m	13.129ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	17.564m	7.990ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	28.827m	11.561ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.036m	4.811ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.279m	8.838ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	5.915m	3.756ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.003h	44.330ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.602m	5.825ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.728m	5.045ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.757m	22.104ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	21.398m	8.653ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	32.783m	9.611ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	47.824m	29.904ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.611m	3.098ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.361m	5.572ms	98	100	98.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.489m	8.610ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.489m	8.610ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	32.783m	9.611ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.757m	22.104ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	13.036m	4.811ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.117m	4.562ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.143m	3.196ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	11.472m	4.763ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.096m	4.719ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.307m	11.768ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.080m	2.765ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.361m	5.572ms	98	100	98.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	33.860m	8.006ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.927m	6.231ms	3	3	100.00
		chip_plic_all_irqs_10	11.533m	4.414ms	3	3	100.00
		chip_plic_all_irqs_20	14.005m	4.826ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.216m	3.127ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.865m	2.921ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	16.113m	8.097ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	45.548m	14.008ms	2	3	66.67
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.390m	4.060ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.174m	3.462ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.565m	3.847ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.092m	4.437ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	17.324m	8.716ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	12.287m	6.605ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.835m	9.377ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.361m	5.572ms	98	100	98.00
		chip_sw_data_integrity_escalation	14.533m	5.288ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.439m	3.248ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.311m	3.254ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.488m	3.465ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	8.280m	3.950ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	34.053m	8.238ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.836h	31.692ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	47.583m	11.753ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.490m	2.979ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.220m	4.906ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.361m	5.572ms	98	100	98.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.420m	3.811ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.307m	11.768ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.559m	4.063ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.698m	3.899ms	86	90	95.56
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	24.521m	9.931ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	29.860m	8.628ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	33.860m	8.006ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.522h	254.978ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	45.439m	21.048ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.031m	13.429ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.143m	3.196ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.591m	5.010ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.874m	3.932ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	15.865m	8.668ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.417m	14.192ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2584	2657	97.25
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.496m	2.955ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.322m	5.527ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.635m	1.984ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.883m	2.324ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.803m	2.329ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	49.142m	40.903ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.044h	39.702ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.166h	45.845ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.008m	2.834ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.364m	3.009ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	29.897m	7.023ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	33.797m	9.877ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.040m	3.501ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.816m	6.475ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.759m	2.176ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.312m	6.266ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	6.891m	23.408ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.417m	3.998ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	32.783m	9.611ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.361m	5.572ms	98	100	98.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	11.481m	4.842ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.253h	18.182ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.635m	1.984ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.883m	2.324ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.803m	2.329ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	9.113m	5.203ms	3	3	100.00
V3		TOTAL			29	45	64.44
	Unmapped tests	chip_sival_flash_info_access	6.031m	3.158ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.231m	4.352ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.125h	17.079ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	20.002m	4.998ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.650m	4.444ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.398m	6.151ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.470m	2.932ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	5.078m	2.980ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2839	2955	96.07

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	16	84.21
V2	290	276	249	85.86
V2S	1	1	1	100.00
V3	91	21	11	12.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.25	95.38	94.39	95.68	--	95.08	97.38	99.58

Failure Buckets

• Exit reason: Error: User command failed Job returned non-zero exit code has 45 failures:

  • Test chip_sw_flash_ctrl_write_clear has 3 failures.

    • 0.chip_sw_flash_ctrl_write_clear.8953266948951162049273684580107893755264518291031962936478424432033657095801
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

        (16:11:09) Loading:
        (16:11:10) Loading:
        (16:11:10) Loading: 4 packages loaded
        (16:11:10) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (16:11:10) WARNING: Target pattern parsing failed.
        (16:11:10) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (16:11:10) INFO: Elapsed time: 43.249s
        (16:11:10) INFO: 0 processes.
        (16:11:10) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_flash_ctrl_write_clear.39548149318080310457807769127251279066197944560137473196413372466730146277923
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

        (16:23:11) Loading:
        (16:23:12) Loading:
        (16:23:12) Loading: 4 packages loaded
        (16:23:12) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (16:23:12) WARNING: Target pattern parsing failed.
        (16:23:12) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (16:23:12) INFO: Elapsed time: 19.265s
        (16:23:12) INFO: 0 processes.
        (16:23:12) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_meas.110397944193421656133361534709109240152208617880421102327965152426966116849681
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (16:12:38) Loading:
        (16:12:38) Loading:
        (16:12:38) Loading: 4 packages loaded
        (16:12:38) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:12:38) WARNING: Target pattern parsing failed.
        (16:12:38) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:12:39) INFO: Elapsed time: 20.862s
        (16:12:39) INFO: 0 processes.
        (16:12:39) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_meas.86555925167099340891863869337094667582427795952632825873802494937759055731159
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (16:24:37) Loading:
        (16:24:38) Loading:
        (16:24:38) Loading: 4 packages loaded
        (16:24:38) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:24:38) WARNING: Target pattern parsing failed.
        (16:24:38) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:24:38) INFO: Elapsed time: 19.672s
        (16:24:38) INFO: 0 processes.
        (16:24:38) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_no_meas.32419472219447857966079759742324584210875591762799900288568887723791140352901
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (16:13:32) Loading:
        (16:13:33) Loading:
        (16:13:33) Loading: 4 packages loaded
        (16:13:33) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:13:33) WARNING: Target pattern parsing failed.
        (16:13:33) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:13:33) INFO: Elapsed time: 50.024s
        (16:13:33) INFO: 0 processes.
        (16:13:33) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_no_meas.55366572756324027802999690575166354537243860384054055695450347071011130682000
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (16:24:38) Loading:
        (16:24:39) Loading:
        (16:24:39) Loading: 4 packages loaded
        (16:24:39) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:24:39) WARNING: Target pattern parsing failed.
        (16:24:39) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:24:39) INFO: Elapsed time: 25.896s
        (16:24:39) INFO: 0 processes.
        (16:24:39) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.9628013131846872669219840528922695182237386993454850430652568979486260576326
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (16:13:04) Loading:
        (16:13:05) Loading:
        (16:13:05) Loading: 4 packages loaded
        (16:13:05) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:13:05) WARNING: Target pattern parsing failed.
        (16:13:05) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:13:05) INFO: Elapsed time: 43.323s
        (16:13:05) INFO: 0 processes.
        (16:13:05) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.53165704774929066041883780712099336493052708329497594156802002338792324538144
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (16:24:30) Loading:
        (16:24:31) Loading:
        (16:24:31) Loading: 4 packages loaded
        (16:24:31) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:24:31) WARNING: Target pattern parsing failed.
        (16:24:31) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (16:24:31) INFO: Elapsed time: 18.669s
        (16:24:31) INFO: 0 processes.
        (16:24:31) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

    • 0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.108065539775609783039514338144532155472104580202853153841816696616724811706708
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

        (16:12:38) Loading:
        (16:12:39) Loading:
        (16:12:39) Loading: 4 packages loaded
        (16:12:39) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (16:12:39) WARNING: Target pattern parsing failed.
        (16:12:39) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (16:12:39) INFO: Elapsed time: 24.419s
        (16:12:39) INFO: 0 processes.
        (16:12:39) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.17003276511240174016697271795342126973125223961678700856710164643711904768430
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

        (16:24:42) Loading:
        (16:24:42) Loading:
        (16:24:42) Loading: 4 packages loaded
        (16:24:43) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (16:24:43) WARNING: Target pattern parsing failed.
        (16:24:43) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (16:24:43) INFO: Elapsed time: 22.400s
        (16:24:43) INFO: 0 processes.
        (16:24:43) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • ... and 10 more tests.

• UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test chip_csr_mem_rw_with_rand_reset has 20 failures.

    • 0.chip_csr_mem_rw_with_rand_reset.93818212121270682115339947302227215301989289663601112384136287193075447392246
      Line 378, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2687.721038 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2687.721038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_csr_mem_rw_with_rand_reset.53903187388525937903237472332182023498758262587562681443266497796381564007951
      Line 383, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2360.625621 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2360.625621 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:

  • Test chip_sw_rv_timer_systick_test has 3 failures.

    • 0.chip_sw_rv_timer_systick_test.2456231191520983023902837066710367015129057422014958079054721702979760660042
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:c386c11e-3bf4-450c-b720-16db1353d234
      

    • 1.chip_sw_rv_timer_systick_test.23973011305376256880533820179980843986162143022852101813351476610023560632490
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:b3ef82bb-4b12-4d26-9f3b-f1848224bdd4
      

    • ... and 1 more failures.

  • Test chip_sw_coremark has 1 failures.

    • 0.chip_sw_coremark.10443166268612581312457372226136296296358287357958434080076754016214364726201
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log

        Job ID: smart:73779536-f433-4046-ac93-84f53641cf66
      

  • Test chip_sw_ast_clk_rst_inputs has 3 failures.

    • 0.chip_sw_ast_clk_rst_inputs.70812691485152952902163612372689176202294767256050886273611906588872550202535
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:aa7284c2-6c2e-4c94-ab77-4380d95dae89
      

    • 1.chip_sw_ast_clk_rst_inputs.22242321522413593781246852525685257388563610311654936017348222940311988350709
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:353145f3-6efe-421a-a67a-4e839206e7f7
      

    • ... and 1 more failures.

  • Test rom_e2e_smoke has 3 failures.

    • 0.rom_e2e_smoke.61187759888958142769933268008794957650461365857146435208032499195353247859761
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log

        Job ID: smart:ac576939-e9b0-4f9f-b8a8-15f7f0941deb
      

    • 1.rom_e2e_smoke.23225736465947547623424826428125622250017228154033600568954169159752137432074
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log

        Job ID: smart:88811dfd-f628-4147-8123-8a90aecf3561
      

    • ... and 1 more failures.

  • Test rom_e2e_shutdown_output has 3 failures.

    • 0.rom_e2e_shutdown_output.109666558583859749655333265109858311737511884189519449062267494900714750397020
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

        Job ID: smart:5797e4b0-ef76-410c-9a30-e20a0cd7cdb7
      

    • 1.rom_e2e_shutdown_output.110568336195342516661455409354654693815312096104609846538473762757278484930070
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log

        Job ID: smart:3279792b-74e7-40fd-bb17-94e8ed9c56d8
      

    • ... and 1 more failures.

  • ... and 1 more tests.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 4 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 4 failures.

    • 41.chip_sw_alert_handler_lpg_sleep_mode_alerts.113279488080449281361475847006834395628144103590850462045927369799523381988583
      Line 797, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 4361.141896 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
        UVM_INFO @ 4361.141896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 50.chip_sw_alert_handler_lpg_sleep_mode_alerts.6447841976003913992768203167394451420063568822634023662821332590881680399775
      Line 838, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3264.820716 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
        UVM_INFO @ 3264.820716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:

  • Test chip_sw_sysrst_ctrl_outputs has 3 failures.

    • 0.chip_sw_sysrst_ctrl_outputs.83093777349208120224511237741746298017228755417399097802523169143487316756435
      Line 808, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_sysrst_ctrl_outputs.46978529159778173799416293334979699235822160025686409413091872875954646653315
      Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

  • Test chip_sw_lc_ctrl_program_error has 3 failures.

    • 0.chip_sw_lc_ctrl_program_error.95135632416626994654665082455016951075961924370047487895096744830451606910978
      Line 782, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 14886.020824 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 14886.020824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.chip_sw_lc_ctrl_program_error.84257089765894586823385533823834286724096017743433770076781967271318454504096
      Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 14904.997832 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 14904.997832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:

  • Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.

    • 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.88217719774229962223616121258750198549930992929093420679697209662008454825786
      Line 809, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_FATAL @ 23407.538250 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
        UVM_INFO @ 23407.538250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.101762261036776722659819067394778475753137689696712215415536809340589202682191
      Line 753, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_FATAL @ 22892.746542 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
        UVM_INFO @ 22892.746542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:

  • Test chip_sw_rv_dm_access_after_wakeup has 3 failures.

    • 0.chip_sw_rv_dm_access_after_wakeup.44473120990969671678874997578495556577752543912996385459282259840489535280241
      Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log

        UVM_FATAL @ 4434.185453 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
        UVM_INFO @ 4434.185453 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_rv_dm_access_after_wakeup.89764787728565596290132945888518267289462297336816763394124615892409896855890
      Line 745, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log

        UVM_FATAL @ 3773.418239 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
        UVM_INFO @ 3773.418239 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 3 failures:

  • Test chip_sw_power_virus has 3 failures.

    • 0.chip_sw_power_virus.46055153910507960821099176568739393441537553570100971217851620691029026727269
      Line 1000, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 5526.990398 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 5526.990398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_power_virus.74682392533763761368561324766376821588569067535425509143336220178681935602702
      Line 1058, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 4878.123959 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 4878.123959 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:

  • Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_debug_test_unlocked0.20815485357576889592614866822084764434930859983610755395630999021378243028072
      Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log

        UVM_FATAL @ 1984.173500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 1984.173500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_dev has 1 failures.

    • 0.rom_e2e_jtag_debug_dev.45340937928089604213001539306312323997499305572379341175041258491551734389589
      Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log

        UVM_FATAL @ 2323.696000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2323.696000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_rma has 1 failures.

    • 0.rom_e2e_jtag_debug_rma.2977708962450090921826698105108733748975611043960832224430227059590772714328
      Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log

        UVM_FATAL @ 2329.421000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2329.421000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:

  • Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_inject_test_unlocked0.94106551085426249384797105128533575030953911489841330628058493650597930270830
      Line 797, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log

        UVM_FATAL @ 40902.582570 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 40902.582570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_dev has 1 failures.

    • 0.rom_e2e_jtag_inject_dev.106373391885924664193982039567745169342595446332663887250298832881597100839626
      Line 803, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log

        UVM_FATAL @ 39701.924415 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 39701.924415 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_rma has 1 failures.

    • 0.rom_e2e_jtag_inject_rma.2164140274923470668602821734872067013588740525401855369257227616960273428672
      Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log

        UVM_FATAL @ 45844.866253 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 45844.866253 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:

  • Test rom_e2e_static_critical has 2 failures.

    • 0.rom_e2e_static_critical.25759525431582065904601331390489635743538673408328303954540492248104479259116
      Line 977, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log

        UVM_ERROR @ 20016.567651 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
        
        UVM_INFO @ 20016.567651 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.rom_e2e_static_critical.86797635648695096301192435744311246374257780283240225883179529461861206219685
      Line 954, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log

        UVM_ERROR @ 20017.710520 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
        
        UVM_INFO @ 20017.710520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:

  • Test rom_raw_unlock has 2 failures.

    • 0.rom_raw_unlock.113639605393286574040603829714587221248985439629865647605250946668101590366404
      Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

        UVM_ERROR @ 204570.313484 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
        
        UVM_INFO @ 204570.313484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.rom_raw_unlock.27509272173419210385606502638629108181729483986362870822759121750759095223785
      Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

        UVM_ERROR @ 206941.999816 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
        
        UVM_INFO @ 206941.999816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:

  • Test chip_sw_all_escalation_resets has 2 failures.

    • 3.chip_sw_all_escalation_resets.66661675369086650375348587926819682647739119983142803523660902695095102339917
      Line 820, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 2867.999112 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 2867.999112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 64.chip_sw_all_escalation_resets.95396694177726089624776910201773507782907335639517926903720598366714789670013
      Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 2931.636984 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 2931.636984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:457) [chip_sw_spi_passthrough_collision_vseq] timeout occurred! has 1 failures:

  • Test chip_sw_spi_device_pass_through_collision has 1 failures.

    • 0.chip_sw_spi_device_pass_through_collision.51477205366597638676277010673270725411199614853284548119135992700012684508749
      Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_FATAL @ 14007.927540 us: (chip_sw_base_vseq.sv:457) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] timeout occurred!
        UVM_INFO @ 14007.927540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test chip_csr_aliasing has 1 failures.

    • 1.chip_csr_aliasing.44639159161180617062050610489256709854309685577524298569887005527804722839093
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log

        Job ID: smart:522fc6a5-5bf5-4edb-aca8-1dec630f3656
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:

  • Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 1 failures.

    • 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.22811041405604373784716404388198185249216165589372605900972186192442605857202
      Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log

        UVM_ERROR @ 33023.855635 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 33000000 ns
        
        UVM_INFO @ 33023.855635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:

  • Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.

    • 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.59628632070544527280562864407379258442704305730003419146671783360474734347818
      Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 5948.941600 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
        UVM_INFO @ 5948.941600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:

  • Test rom_e2e_static_critical has 1 failures.

    • 2.rom_e2e_static_critical.36382820529361411906973057188773718209978761512690594645385026038771363869432
      Line 1012, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_e2e_static_critical/latest/run.log

        UVM_ERROR @ 20018.509610 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 20000000 ns
        
        UVM_INFO @ 20018.509610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:770) [chip_sw_lc_raw_unlock_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error e* has 1 failures:

  • Test rom_raw_unlock has 1 failures.

    • 2.rom_raw_unlock.33982969795682248138257005150624183903055888161106653861807928117722346772025
      Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log

        UVM_ERROR @ 2920.118799 us: (chip_sw_base_vseq.sv:770) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Check failed (status_val) >> dummy.num() == 0 (917504 [0xe0000] vs 0 [0x0]) Unexpected status error e0000000
        UVM_INFO @ 2920.118799 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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