Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.00	95.29	93.69	95.62		94.41	97.38	99.59

Total test records in report: 2800

T2757	/workspace/coverage/cover_reg_top/72.xbar_random.3139408328	Apr 23 04:46:29 PM PDT 24	Apr 23 04:47:17 PM PDT 24	533489588 ps
T2758	/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.449143573	Apr 23 04:35:10 PM PDT 24	Apr 23 04:36:13 PM PDT 24	5976229152 ps
T2759	/workspace/coverage/cover_reg_top/85.xbar_stress_all.4141110964	Apr 23 04:48:41 PM PDT 24	Apr 23 04:57:32 PM PDT 24	14184134631 ps
T2760	/workspace/coverage/cover_reg_top/69.xbar_error_random.3157972239	Apr 23 04:46:05 PM PDT 24	Apr 23 04:46:23 PM PDT 24	189066962 ps
T2761	/workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3671090493	Apr 23 04:45:58 PM PDT 24	Apr 23 04:46:17 PM PDT 24	178915989 ps
T2762	/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1280790267	Apr 23 04:36:26 PM PDT 24	Apr 23 04:36:52 PM PDT 24	190790530 ps
T2763	/workspace/coverage/cover_reg_top/65.xbar_access_same_device.1295941050	Apr 23 04:45:25 PM PDT 24	Apr 23 04:46:47 PM PDT 24	985257000 ps
T2764	/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1694494861	Apr 23 04:34:01 PM PDT 24	Apr 23 04:34:38 PM PDT 24	718394995 ps
T2765	/workspace/coverage/cover_reg_top/51.xbar_same_source.2463194009	Apr 23 04:43:17 PM PDT 24	Apr 23 04:44:15 PM PDT 24	1876000710 ps
T2766	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.946194980	Apr 23 04:49:11 PM PDT 24	Apr 23 04:53:53 PM PDT 24	3218638853 ps
T2767	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3908453610	Apr 23 04:44:46 PM PDT 24	Apr 23 04:45:55 PM PDT 24	101845085 ps
T2768	/workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.2278507317	Apr 23 04:37:20 PM PDT 24	Apr 23 04:38:22 PM PDT 24	1278766351 ps
T2769	/workspace/coverage/cover_reg_top/96.xbar_same_source.922797335	Apr 23 04:50:26 PM PDT 24	Apr 23 04:50:45 PM PDT 24	502300053 ps
T2770	/workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3927206808	Apr 23 04:41:24 PM PDT 24	Apr 23 04:45:54 PM PDT 24	25262807344 ps
T2771	/workspace/coverage/cover_reg_top/51.xbar_error_random.1269386398	Apr 23 04:43:17 PM PDT 24	Apr 23 04:44:19 PM PDT 24	1698531227 ps
T2772	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.779907442	Apr 23 04:46:01 PM PDT 24	Apr 23 04:46:27 PM PDT 24	95506553 ps
T2773	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.210243798	Apr 23 04:38:09 PM PDT 24	Apr 23 04:39:44 PM PDT 24	216698364 ps
T2774	/workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1112707081	Apr 23 04:43:58 PM PDT 24	Apr 23 04:45:29 PM PDT 24	5647001611 ps
T2775	/workspace/coverage/cover_reg_top/12.xbar_random.2500521086	Apr 23 04:34:37 PM PDT 24	Apr 23 04:36:10 PM PDT 24	2272003032 ps
T2776	/workspace/coverage/cover_reg_top/29.xbar_random_large_delays.433757234	Apr 23 04:39:36 PM PDT 24	Apr 23 04:42:30 PM PDT 24	15404547641 ps
T2777	/workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3971792272	Apr 23 04:30:47 PM PDT 24	Apr 23 04:39:52 PM PDT 24	29156283454 ps
T2778	/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.13456924	Apr 23 04:28:04 PM PDT 24	Apr 23 04:42:29 PM PDT 24	69690748446 ps
T2779	/workspace/coverage/cover_reg_top/37.xbar_same_source.4130076286	Apr 23 04:41:05 PM PDT 24	Apr 23 04:41:25 PM PDT 24	502148689 ps
T2780	/workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.4183743327	Apr 23 04:37:42 PM PDT 24	Apr 23 04:40:57 PM PDT 24	9639531913 ps
T2781	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.1146128055	Apr 23 04:43:09 PM PDT 24	Apr 23 04:44:55 PM PDT 24	1299335499 ps
T2782	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1498103445	Apr 23 04:31:34 PM PDT 24	Apr 23 04:32:40 PM PDT 24	135398529 ps
T2783	/workspace/coverage/cover_reg_top/16.chip_csr_rw.1673996745	Apr 23 04:36:36 PM PDT 24	Apr 23 04:42:28 PM PDT 24	4608376632 ps
T2784	/workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.1599806047	Apr 23 04:49:04 PM PDT 24	Apr 23 05:09:58 PM PDT 24	73912743395 ps
T2785	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.410234028	Apr 23 04:37:05 PM PDT 24	Apr 23 04:42:57 PM PDT 24	8260346215 ps
T2786	/workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.1186658295	Apr 23 04:50:07 PM PDT 24	Apr 23 04:50:46 PM PDT 24	375227544 ps
T2787	/workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3287604196	Apr 23 04:47:03 PM PDT 24	Apr 23 04:51:39 PM PDT 24	14431088436 ps
T2788	/workspace/coverage/cover_reg_top/64.xbar_error_random.611592358	Apr 23 04:45:15 PM PDT 24	Apr 23 04:45:39 PM PDT 24	581763383 ps
T2789	/workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.115749866	Apr 23 04:44:49 PM PDT 24	Apr 23 04:45:46 PM PDT 24	1204611785 ps
T2790	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1908899161	Apr 23 04:33:13 PM PDT 24	Apr 23 04:36:34 PM PDT 24	1299170717 ps
T2791	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1196541590	Apr 23 04:40:36 PM PDT 24	Apr 23 04:41:30 PM PDT 24	74591575 ps
T2792	/workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2039713600	Apr 23 04:44:10 PM PDT 24	Apr 23 04:44:51 PM PDT 24	507522245 ps
T2793	/workspace/coverage/cover_reg_top/15.xbar_smoke.3988847046	Apr 23 04:35:53 PM PDT 24	Apr 23 04:36:03 PM PDT 24	175682636 ps
T2794	/workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.448025257	Apr 23 04:37:11 PM PDT 24	Apr 23 04:37:39 PM PDT 24	290387723 ps
T2795	/workspace/coverage/cover_reg_top/82.xbar_smoke.16345577	Apr 23 04:48:06 PM PDT 24	Apr 23 04:48:16 PM PDT 24	218090770 ps
T2796	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1078419266	Apr 23 04:44:34 PM PDT 24	Apr 23 04:46:46 PM PDT 24	484631671 ps
T28	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2648900379	Apr 23 04:25:55 PM PDT 24	Apr 23 04:30:22 PM PDT 24	4966829100 ps
T29	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2432755227	Apr 23 04:26:07 PM PDT 24	Apr 23 04:32:12 PM PDT 24	4448985670 ps
T30	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.858610949	Apr 23 04:25:50 PM PDT 24	Apr 23 04:30:31 PM PDT 24	5405453488 ps
T36	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3030938053	Apr 23 04:25:54 PM PDT 24	Apr 23 04:30:29 PM PDT 24	4698994216 ps
T644	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2074662544	Apr 23 04:25:42 PM PDT 24	Apr 23 04:30:05 PM PDT 24	4189662075 ps
T645	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2789086550	Apr 23 04:25:38 PM PDT 24	Apr 23 04:30:10 PM PDT 24	4322308015 ps
T2797	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3312009108	Apr 23 04:25:45 PM PDT 24	Apr 23 04:31:23 PM PDT 24	5117607558 ps
T2798	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2455481997	Apr 23 04:25:50 PM PDT 24	Apr 23 04:30:38 PM PDT 24	4077940004 ps
T2799	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.35651055	Apr 23 04:25:59 PM PDT 24	Apr 23 04:30:40 PM PDT 24	5069688040 ps
T2800	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3183999799	Apr 23 04:25:47 PM PDT 24	Apr 23 04:31:36 PM PDT 24	4748290343 ps

Test location	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1063558036
Short name	T32
Test name
Test status
Simulation time	5108334968 ps
CPU time	575.85 seconds
Started	Apr 23 04:28:17 PM PDT 24
Finished	Apr 23 04:37:53 PM PDT 24
Peak memory	635872 kb
Host	smart-b2b317a8-20f8-4817-8b38-7aaf0efb0efc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1063558036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.1063558036
Directory	/workspace/18.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_rw.3133491307
Short name	T151
Test name
Test status
Simulation time	5736468258 ps
CPU time	623.44 seconds
Started	Apr 23 04:31:05 PM PDT 24
Finished	Apr 23 04:41:29 PM PDT 24
Peak memory	589740 kb
Host	smart-a41706c2-aeb8-4445-a067-f4deb5672e8f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133491307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3133491307
Directory	/workspace/4.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.294875808
Short name	T501
Test name
Test status
Simulation time	103052451956 ps
CPU time	1785.5 seconds
Started	Apr 23 04:44:06 PM PDT 24
Finished	Apr 23 05:13:52 PM PDT 24
Peak memory	562900 kb
Host	smart-effc3bf4-2855-4e9e-822b-a1a04d28ece8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294875808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_d evice_slow_rsp.294875808
Directory	/workspace/57.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_0.3144776940
Short name	T299
Test name
Test status
Simulation time	6222728798 ps
CPU time	1081.61 seconds
Started	Apr 23 04:11:05 PM PDT 24
Finished	Apr 23 04:29:07 PM PDT 24
Peak memory	600212 kb
Host	smart-49ad9bcd-6a16-4e81-8523-bfdfc0b62a6b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144776940 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.3144776940
Directory	/workspace/1.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.4291846188
Short name	T756
Test name
Test status
Simulation time	137335826271 ps
CPU time	2335.19 seconds
Started	Apr 23 04:31:25 PM PDT 24
Finished	Apr 23 05:10:21 PM PDT 24
Peak memory	562840 kb
Host	smart-1a099a73-ff93-4e93-be17-37281608757b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291846188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.4291846188
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/2.chip_jtag_csr_rw.1777613864
Short name	T63
Test name
Test status
Simulation time	16839078985 ps
CPU time	1934.91 seconds
Started	Apr 23 04:16:33 PM PDT 24
Finished	Apr 23 04:48:48 PM PDT 24
Peak memory	599900 kb
Host	smart-f91a95ba-7fb2-4f1e-a8bf-197a50011ae3
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777613864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.1777613864
Directory	/workspace/2.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3854141005
Short name	T504
Test name
Test status
Simulation time	6633198630 ps
CPU time	441.86 seconds
Started	Apr 23 04:34:56 PM PDT 24
Finished	Apr 23 04:42:18 PM PDT 24
Peak memory	572172 kb
Host	smart-3d59c751-9b44-4a46-8d0b-550349a251b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854141005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.3854141005
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2648900379
Short name	T28
Test name
Test status
Simulation time	4966829100 ps
CPU time	265.9 seconds
Started	Apr 23 04:25:55 PM PDT 24
Finished	Apr 23 04:30:22 PM PDT 24
Peak memory	630892 kb
Host	smart-13f4bffe-d2fe-4758-a98d-5a721b3a2c44
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648900379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.2648900379
Directory	/workspace/9.chip_padctrl_attributes/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1164460542
Short name	T87
Test name
Test status
Simulation time	10181733248 ps
CPU time	1333.8 seconds
Started	Apr 23 04:09:23 PM PDT 24
Finished	Apr 23 04:31:38 PM PDT 24
Peak memory	601700 kb
Host	smart-7160ae9e-ae5e-4809-ae69-c36d4a3f2a72
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164460542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1164460542
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1230291626
Short name	T492
Test name
Test status
Simulation time	66730665784 ps
CPU time	1159.06 seconds
Started	Apr 23 04:32:35 PM PDT 24
Finished	Apr 23 04:51:54 PM PDT 24
Peak memory	562924 kb
Host	smart-c22a02d7-2dcb-427e-b6c0-5c217ddebb69
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230291626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.1230291626
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2089418735
Short name	T7
Test name
Test status
Simulation time	3386249252 ps
CPU time	246.71 seconds
Started	Apr 23 04:15:57 PM PDT 24
Finished	Apr 23 04:20:04 PM PDT 24
Peak memory	600280 kb
Host	smart-28190b4b-9db4-4eb1-bed7-7c7e6a675d22
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089 418735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.2089418735
Directory	/workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4214517602
Short name	T167
Test name
Test status
Simulation time	48938807334 ps
CPU time	5912.17 seconds
Started	Apr 23 04:16:16 PM PDT 24
Finished	Apr 23 05:54:49 PM PDT 24
Peak memory	607748 kb
Host	smart-df62c754-9857-4f58-a6ee-b1dd56de7855
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214517602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.4214517602
Directory	/workspace/2.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2203995242
Short name	T785
Test name
Test status
Simulation time	114512330977 ps
CPU time	2018.8 seconds
Started	Apr 23 04:40:47 PM PDT 24
Finished	Apr 23 05:14:27 PM PDT 24
Peak memory	562948 kb
Host	smart-e109517e-3ea4-4f9c-8141-c1d2faaae863
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203995242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.2203995242
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.608900024
Short name	T1
Test name
Test status
Simulation time	4280879650 ps
CPU time	448.71 seconds
Started	Apr 23 04:23:01 PM PDT 24
Finished	Apr 23 04:30:31 PM PDT 24
Peak memory	601160 kb
Host	smart-cccbb04f-1016-4450-b2a6-069f68304cd6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608900 024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.608900024
Directory	/workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2865215774
Short name	T774
Test name
Test status
Simulation time	97352338474 ps
CPU time	1797.35 seconds
Started	Apr 23 04:33:10 PM PDT 24
Finished	Apr 23 05:03:08 PM PDT 24
Peak memory	562820 kb
Host	smart-0cef147a-9e4f-4df9-98c7-60f7d2fe68c2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865215774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.2865215774
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4167087056
Short name	T105
Test name
Test status
Simulation time	21067703080 ps
CPU time	1376.91 seconds
Started	Apr 23 04:11:52 PM PDT 24
Finished	Apr 23 04:34:50 PM PDT 24
Peak memory	601328 kb
Host	smart-a40d3025-9bee-4d74-9b64-2802354b17a3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4167087056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4167087056
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3517706305
Short name	T113
Test name
Test status
Simulation time	2797519974 ps
CPU time	244.38 seconds
Started	Apr 23 03:54:51 PM PDT 24
Finished	Apr 23 03:58:56 PM PDT 24
Peak memory	599992 kb
Host	smart-16962d4c-9953-41c3-ba13-fe388c325676
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3517706305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.3517706305
Directory	/workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_test.3532814995
Short name	T62
Test name
Test status
Simulation time	2558040768 ps
CPU time	263.96 seconds
Started	Apr 23 04:07:57 PM PDT 24
Finished	Apr 23 04:12:21 PM PDT 24
Peak memory	599872 kb
Host	smart-41fa82a0-eab1-4bb4-b83d-b1471c11442e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532814995 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.3532814995
Directory	/workspace/1.chip_sw_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1652464892
Short name	T771
Test name
Test status
Simulation time	78308867041 ps
CPU time	1355.25 seconds
Started	Apr 23 04:47:09 PM PDT 24
Finished	Apr 23 05:09:45 PM PDT 24
Peak memory	562812 kb
Host	smart-ca8a4e90-e13b-4264-9635-8214fcd8113d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652464892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.1652464892
Directory	/workspace/76.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_20.195628479
Short name	T309
Test name
Test status
Simulation time	4264211848 ps
CPU time	515.36 seconds
Started	Apr 23 03:52:37 PM PDT 24
Finished	Apr 23 04:01:13 PM PDT 24
Peak memory	599860 kb
Host	smart-cb309093-1db9-4310-9d73-57aa22c22ef4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195628479 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_20.195628479
Directory	/workspace/0.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all.132261605
Short name	T445
Test name
Test status
Simulation time	8777427578 ps
CPU time	343.02 seconds
Started	Apr 23 04:47:14 PM PDT 24
Finished	Apr 23 04:52:57 PM PDT 24
Peak memory	563072 kb
Host	smart-1b26bfc7-5fa2-4ea1-92f7-2b90b934f72c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132261605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.132261605
Directory	/workspace/76.xbar_stress_all/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4233279492
Short name	T61
Test name
Test status
Simulation time	24164430833 ps
CPU time	3644.28 seconds
Started	Apr 23 04:11:34 PM PDT 24
Finished	Apr 23 05:12:19 PM PDT 24
Peak memory	600292 kb
Host	smart-8f41092d-1c9e-4953-885d-1c7a89924840
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233279492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.4233279492
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_gpio.326860761
Short name	T24
Test name
Test status
Simulation time	3549082554 ps
CPU time	363.51 seconds
Started	Apr 23 03:52:02 PM PDT 24
Finished	Apr 23 03:58:06 PM PDT 24
Peak memory	600328 kb
Host	smart-794c5221-3882-4ff1-8895-78b02dd62d42
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326860761 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_gpio.326860761
Directory	/workspace/0.chip_sw_gpio/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.866574257
Short name	T5
Test name
Test status
Simulation time	77836926444 ps
CPU time	13579 seconds
Started	Apr 23 04:05:18 PM PDT 24
Finished	Apr 23 07:51:38 PM PDT 24
Peak memory	621944 kb
Host	smart-1d7bc0ad-1e98-4ad0-9067-4d0c502f357f
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=866574257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.866574257
Directory	/workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3647584853
Short name	T1666
Test name
Test status
Simulation time	145025938620 ps
CPU time	2416.46 seconds
Started	Apr 23 04:42:45 PM PDT 24
Finished	Apr 23 05:23:02 PM PDT 24
Peak memory	563016 kb
Host	smart-b1556d29-c1ef-49d8-857e-31f4bebeb639
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647584853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.3647584853
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1270084001
Short name	T508
Test name
Test status
Simulation time	4113812297 ps
CPU time	480.85 seconds
Started	Apr 23 04:44:51 PM PDT 24
Finished	Apr 23 04:52:52 PM PDT 24
Peak memory	572232 kb
Host	smart-ec711c91-7bfd-4b07-bb21-c90b4baa0148
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270084001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.1270084001
Directory	/workspace/60.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/18.chip_tl_errors.563358748
Short name	T513
Test name
Test status
Simulation time	4482808412 ps
CPU time	263.41 seconds
Started	Apr 23 04:36:51 PM PDT 24
Finished	Apr 23 04:41:15 PM PDT 24
Peak memory	585064 kb
Host	smart-1e05552a-264b-41e6-9d6e-32cc8af7bcf8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563358748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.563358748
Directory	/workspace/18.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3466599599
Short name	T81
Test name
Test status
Simulation time	828468636 ps
CPU time	44.76 seconds
Started	Apr 23 04:32:10 PM PDT 24
Finished	Apr 23 04:32:55 PM PDT 24
Peak memory	562816 kb
Host	smart-a43f64cd-7c83-4963-8b6c-53a511a01768
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466599599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3466599599
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_10.4121995055
Short name	T162
Test name
Test status
Simulation time	3638260460 ps
CPU time	466.2 seconds
Started	Apr 23 03:52:31 PM PDT 24
Finished	Apr 23 04:00:17 PM PDT 24
Peak memory	600200 kb
Host	smart-27cd4766-650e-41fe-85e5-5fcb6d8185e2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121995055 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.4121995055
Directory	/workspace/0.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2498550004
Short name	T152
Test name
Test status
Simulation time	31224966179 ps
CPU time	3502.15 seconds
Started	Apr 23 04:32:51 PM PDT 24
Finished	Apr 23 05:31:14 PM PDT 24
Peak memory	585236 kb
Host	smart-89c6195e-69a3-45dd-bb04-25b28b317524
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498550004 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.2498550004
Directory	/workspace/8.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_access_same_device.3382567657
Short name	T763
Test name
Test status
Simulation time	1316285150 ps
CPU time	107.04 seconds
Started	Apr 23 04:36:40 PM PDT 24
Finished	Apr 23 04:38:27 PM PDT 24
Peak memory	562700 kb
Host	smart-625baa68-7155-49d8-961f-000319042ddd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382567657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .3382567657
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.863258327
Short name	T48
Test name
Test status
Simulation time	12261382017 ps
CPU time	880.14 seconds
Started	Apr 23 04:29:22 PM PDT 24
Finished	Apr 23 04:44:03 PM PDT 24
Peak memory	610720 kb
Host	smart-9b903203-c19e-448e-9aa6-c3a22fa24dc3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863258327 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.863258327
Directory	/workspace/8.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.977259933
Short name	T456
Test name
Test status
Simulation time	7628931796 ps
CPU time	548.32 seconds
Started	Apr 23 04:50:31 PM PDT 24
Finished	Apr 23 04:59:40 PM PDT 24
Peak memory	572240 kb
Host	smart-471c7b37-a44c-4b9c-b257-c4dfeb80243b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977259933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_ with_rand_reset.977259933
Directory	/workspace/96.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.86848616
Short name	T46
Test name
Test status
Simulation time	77863136698 ps
CPU time	16113.1 seconds
Started	Apr 23 04:02:49 PM PDT 24
Finished	Apr 23 08:31:24 PM PDT 24
Peak memory	600372 kb
Host	smart-63566b27-daf4-4e6d-8fb0-7bd81ae655d6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_b inary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,rom_wit h_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=86848616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.86848616
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1201286475
Short name	T135
Test name
Test status
Simulation time	7572897300 ps
CPU time	639.48 seconds
Started	Apr 23 03:55:27 PM PDT 24
Finished	Apr 23 04:06:07 PM PDT 24
Peak memory	600372 kb
Host	smart-29f81018-4f0a-4b0c-bd7b-39fc7da5dea2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12012864 75 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1201286475
Directory	/workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2145704406
Short name	T8
Test name
Test status
Simulation time	2806200321 ps
CPU time	291.66 seconds
Started	Apr 23 04:03:33 PM PDT 24
Finished	Apr 23 04:08:26 PM PDT 24
Peak memory	599948 kb
Host	smart-5cce8c8f-1b72-4f32-ba35-62cfe4d8bef2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145 704406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.2145704406
Directory	/workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_random_large_delays.609677492
Short name	T86
Test name
Test status
Simulation time	101072235910 ps
CPU time	1135.42 seconds
Started	Apr 23 04:49:02 PM PDT 24
Finished	Apr 23 05:07:58 PM PDT 24
Peak memory	562792 kb
Host	smart-cc5a6c12-2aac-4166-bdcb-3b1418f722b5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609677492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.609677492
Directory	/workspace/88.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/21.chip_tl_errors.2973768505
Short name	T549
Test name
Test status
Simulation time	4156378720 ps
CPU time	387.43 seconds
Started	Apr 23 04:37:46 PM PDT 24
Finished	Apr 23 04:44:14 PM PDT 24
Peak memory	593316 kb
Host	smart-5dfd3287-b6be-47dd-9b7d-fa3e0d84f8f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973768505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.2973768505
Directory	/workspace/21.chip_tl_errors/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1890421765
Short name	T136
Test name
Test status
Simulation time	4896527224 ps
CPU time	365.54 seconds
Started	Apr 23 03:52:14 PM PDT 24
Finished	Apr 23 03:58:20 PM PDT 24
Peak memory	599944 kb
Host	smart-0d4054ab-132f-4a90-b9ae-28f66fe215dd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18904217 65 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1890421765
Directory	/workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/1.chip_jtag_csr_rw.2790899281
Short name	T17
Test name
Test status
Simulation time	11132375786 ps
CPU time	1290.6 seconds
Started	Apr 23 04:03:29 PM PDT 24
Finished	Apr 23 04:25:01 PM PDT 24
Peak memory	593812 kb
Host	smart-524e7fe8-f44f-4271-9e6d-eb68d9768987
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790899281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.2790899281
Directory	/workspace/1.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1637571178
Short name	T160
Test name
Test status
Simulation time	5357333220 ps
CPU time	822.39 seconds
Started	Apr 23 03:53:01 PM PDT 24
Finished	Apr 23 04:06:44 PM PDT 24
Peak memory	600964 kb
Host	smart-e9366846-8a07-49fc-87b8-af5193b57094
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1637571178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1637571178
Directory	/workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1244685670
Short name	T124
Test name
Test status
Simulation time	3795899352 ps
CPU time	413.74 seconds
Started	Apr 23 04:08:52 PM PDT 24
Finished	Apr 23 04:15:46 PM PDT 24
Peak memory	600496 kb
Host	smart-1f9ed421-bf97-4e04-8f10-218478620fca
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244685670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1244685670
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1342482314
Short name	T9
Test name
Test status
Simulation time	2829352713 ps
CPU time	219.52 seconds
Started	Apr 23 03:50:17 PM PDT 24
Finished	Apr 23 03:53:57 PM PDT 24
Peak memory	600288 kb
Host	smart-fc4b123d-01b4-4f10-9240-38657667dffa
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342 482314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1342482314
Directory	/workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3294553716
Short name	T129
Test name
Test status
Simulation time	4264930988 ps
CPU time	835.4 seconds
Started	Apr 23 04:09:01 PM PDT 24
Finished	Apr 23 04:22:57 PM PDT 24
Peak memory	600344 kb
Host	smart-a578f655-f733-4f5c-b3a8-f2e2ff6dce57
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294553716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.3294553716
Directory	/workspace/1.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.408940100
Short name	T175
Test name
Test status
Simulation time	43352889406 ps
CPU time	4797.01 seconds
Started	Apr 23 04:03:35 PM PDT 24
Finished	Apr 23 05:23:33 PM PDT 24
Peak memory	615720 kb
Host	smart-18c61da1-363e-4388-bef6-69bbf84e2266
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=408940100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.408940100
Directory	/workspace/1.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2559199685
Short name	T845
Test name
Test status
Simulation time	3978209720 ps
CPU time	583.32 seconds
Started	Apr 23 04:28:25 PM PDT 24
Finished	Apr 23 04:38:09 PM PDT 24
Peak memory	607524 kb
Host	smart-e0a45f24-06e5-4833-b60f-87b793729d36
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2559199685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.2559199685
Directory	/workspace/13.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3484456918
Short name	T10
Test name
Test status
Simulation time	7739287396 ps
CPU time	762.09 seconds
Started	Apr 23 04:16:56 PM PDT 24
Finished	Apr 23 04:29:39 PM PDT 24
Peak memory	617760 kb
Host	smart-9fa71d07-0e7c-45fe-b709-878b7f6bbf31
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484456918 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3484456918
Directory	/workspace/2.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2122979195
Short name	T191
Test name
Test status
Simulation time	3233242264 ps
CPU time	360.68 seconds
Started	Apr 23 04:18:50 PM PDT 24
Finished	Apr 23 04:24:53 PM PDT 24
Peak memory	603472 kb
Host	smart-00aa41cf-fd98-44c2-b1ea-f78d4e41c699
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122979195 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2122979195
Directory	/workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.4222207965
Short name	T377
Test name
Test status
Simulation time	27886083264 ps
CPU time	3054.87 seconds
Started	Apr 23 04:29:42 PM PDT 24
Finished	Apr 23 05:20:38 PM PDT 24
Peak memory	585092 kb
Host	smart-896ca83a-1192-4e27-9f84-c6d8d51a5f37
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222207965 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.4222207965
Directory	/workspace/3.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.107221561
Short name	T56
Test name
Test status
Simulation time	4143059146 ps
CPU time	263.78 seconds
Started	Apr 23 03:50:46 PM PDT 24
Finished	Apr 23 03:55:10 PM PDT 24
Peak memory	599896 kb
Host	smart-13471054-4027-4b89-8c77-2febfdd40b87
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107221561 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.107221561
Directory	/workspace/0.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2948706096
Short name	T179
Test name
Test status
Simulation time	6499326632 ps
CPU time	379.97 seconds
Started	Apr 23 03:50:54 PM PDT 24
Finished	Apr 23 03:57:15 PM PDT 24
Peak memory	600240 kb
Host	smart-9ffb2093-1903-4865-87db-f27df8c3396a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948706096 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.2948706096
Directory	/workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all.385470893
Short name	T478
Test name
Test status
Simulation time	24015464441 ps
CPU time	975.03 seconds
Started	Apr 23 04:43:14 PM PDT 24
Finished	Apr 23 04:59:29 PM PDT 24
Peak memory	563444 kb
Host	smart-b5591338-1390-4544-9e13-046e92d0e97e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385470893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.385470893
Directory	/workspace/50.xbar_stress_all/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.712962036
Short name	T176
Test name
Test status
Simulation time	3897544472 ps
CPU time	388.1 seconds
Started	Apr 23 03:53:56 PM PDT 24
Finished	Apr 23 04:00:25 PM PDT 24
Peak memory	600284 kb
Host	smart-92d8317f-7450-4e9b-8185-5544a42a0ce6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71 2962036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.712962036
Directory	/workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_access_same_device.3173278164
Short name	T83
Test name
Test status
Simulation time	2270867007 ps
CPU time	113.89 seconds
Started	Apr 23 04:49:28 PM PDT 24
Finished	Apr 23 04:51:23 PM PDT 24
Peak memory	562868 kb
Host	smart-2cabb94e-5d2f-4c7e-a57f-5d166735050e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173278164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .3173278164
Directory	/workspace/90.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/5.chip_tl_errors.2156044350
Short name	T519
Test name
Test status
Simulation time	4125406650 ps
CPU time	329.93 seconds
Started	Apr 23 04:31:12 PM PDT 24
Finished	Apr 23 04:36:42 PM PDT 24
Peak memory	585120 kb
Host	smart-d18a0fe2-e80c-42a5-b2ab-a6c53e35355b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156044350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.2156044350
Directory	/workspace/5.chip_tl_errors/latest

Test location	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1952422390
Short name	T230
Test name
Test status
Simulation time	4696324950 ps
CPU time	673.57 seconds
Started	Apr 23 04:26:17 PM PDT 24
Finished	Apr 23 04:37:32 PM PDT 24
Peak memory	635740 kb
Host	smart-99803355-bf4f-4eee-9154-be0de08334d3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1952422390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.1952422390
Directory	/workspace/3.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1917235610
Short name	T350
Test name
Test status
Simulation time	3834481282 ps
CPU time	300.14 seconds
Started	Apr 23 04:32:21 PM PDT 24
Finished	Apr 23 04:37:22 PM PDT 24
Peak memory	635560 kb
Host	smart-e765e7a1-14bb-49f8-9a88-7d11596a404c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917235610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1917235610
Directory	/workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2587284742
Short name	T286
Test name
Test status
Simulation time	5123921528 ps
CPU time	502.6 seconds
Started	Apr 23 04:28:19 PM PDT 24
Finished	Apr 23 04:36:42 PM PDT 24
Peak memory	635376 kb
Host	smart-9ad79e6e-4046-4ffd-9f98-a9e3ef48884a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2587284742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2587284742
Directory	/workspace/13.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1743624511
Short name	T92
Test name
Test status
Simulation time	4133863788 ps
CPU time	530.34 seconds
Started	Apr 23 04:27:38 PM PDT 24
Finished	Apr 23 04:36:29 PM PDT 24
Peak memory	636608 kb
Host	smart-cdd6f6f6-b673-403b-a5f4-2208d7da0a63
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1743624511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1743624511
Directory	/workspace/17.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_stream.1157956132
Short name	T16
Test name
Test status
Simulation time	19674274200 ps
CPU time	4809.1 seconds
Started	Apr 23 03:51:01 PM PDT 24
Finished	Apr 23 05:11:12 PM PDT 24
Peak memory	600376 kb
Host	smart-f02d83ab-8f0b-422f-9c4e-fbf8ba1fa356
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1157956132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.1157956132
Directory	/workspace/0.chip_sw_usbdev_stream/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3963860435
Short name	T67
Test name
Test status
Simulation time	2251405423 ps
CPU time	119.65 seconds
Started	Apr 23 03:53:34 PM PDT 24
Finished	Apr 23 03:55:36 PM PDT 24
Peak memory	611064 kb
Host	smart-95d84e19-458f-44be-9d83-58fb856ebc14
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39638604 35 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3963860435
Directory	/workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.414046825
Short name	T252
Test name
Test status
Simulation time	6135302454 ps
CPU time	694.35 seconds
Started	Apr 23 03:51:45 PM PDT 24
Finished	Apr 23 04:03:20 PM PDT 24
Peak memory	600816 kb
Host	smart-c89e0a86-41a5-4711-b0ff-8870018e2086
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=414046825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.414046825
Directory	/workspace/0.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1585186275
Short name	T754
Test name
Test status
Simulation time	12279971514 ps
CPU time	679.92 seconds
Started	Apr 23 04:47:08 PM PDT 24
Finished	Apr 23 04:58:28 PM PDT 24
Peak memory	572212 kb
Host	smart-ea1a750d-5fe2-4b81-8d66-9684707fddd8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585186275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.1585186275
Directory	/workspace/75.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_0.3713998389
Short name	T307
Test name
Test status
Simulation time	6699391424 ps
CPU time	1324.99 seconds
Started	Apr 23 04:24:28 PM PDT 24
Finished	Apr 23 04:46:33 PM PDT 24
Peak memory	600192 kb
Host	smart-9f705baf-b218-4656-90c6-48760d8328e9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713998389 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.3713998389
Directory	/workspace/2.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_entropy.1492665793
Short name	T413
Test name
Test status
Simulation time	2818260344 ps
CPU time	228.5 seconds
Started	Apr 23 04:06:36 PM PDT 24
Finished	Apr 23 04:10:25 PM PDT 24
Peak memory	600216 kb
Host	smart-152b0eb4-e1fa-4284-b15d-fd4a446d7166
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492665793 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.1492665793
Directory	/workspace/1.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_rma.232408917
Short name	T71
Test name
Test status
Simulation time	2896539615 ps
CPU time	159.58 seconds
Started	Apr 23 04:10:30 PM PDT 24
Finished	Apr 23 04:13:10 PM PDT 24
Peak memory	610832 kb
Host	smart-3e410115-e884-41f9-99b6-0a63a7553f80
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232408917 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.232408917
Directory	/workspace/1.chip_tap_straps_rma/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all.1243998699
Short name	T428
Test name
Test status
Simulation time	16680020176 ps
CPU time	711.64 seconds
Started	Apr 23 04:27:02 PM PDT 24
Finished	Apr 23 04:38:54 PM PDT 24
Peak memory	564016 kb
Host	smart-115f50fb-d477-4e7c-8ddf-f58dea260b07
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243998699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1243998699
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2403204736
Short name	T58
Test name
Test status
Simulation time	4491625032 ps
CPU time	288.64 seconds
Started	Apr 23 03:50:50 PM PDT 24
Finished	Apr 23 03:55:39 PM PDT 24
Peak memory	600408 kb
Host	smart-e7f7cde0-9dac-44b1-bcc1-5dc061f0200e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403204736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.2403204736
Directory	/workspace/0.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3644032216
Short name	T59
Test name
Test status
Simulation time	3056998072 ps
CPU time	166.27 seconds
Started	Apr 23 04:05:40 PM PDT 24
Finished	Apr 23 04:08:27 PM PDT 24
Peak memory	600316 kb
Host	smart-2f644bc5-d069-4528-b9f7-eab3983e64e5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644032216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.3644032216
Directory	/workspace/1.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3372695076
Short name	T37
Test name
Test status
Simulation time	5505230140 ps
CPU time	494.34 seconds
Started	Apr 23 04:18:46 PM PDT 24
Finished	Apr 23 04:27:01 PM PDT 24
Peak memory	600732 kb
Host	smart-93430f01-dd78-43ca-b620-2e4eb2ad778d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372695076 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3372695076
Directory	/workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.486895711
Short name	T1085
Test name
Test status
Simulation time	44131516963 ps
CPU time	5327.78 seconds
Started	Apr 23 03:50:06 PM PDT 24
Finished	Apr 23 05:18:55 PM PDT 24
Peak memory	607608 kb
Host	smart-d6637a9c-daf9-43dc-ad9b-d166a1b6d26b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=486895711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.486895711
Directory	/workspace/0.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/cover_reg_top/27.chip_tl_errors.3278281831
Short name	T521
Test name
Test status
Simulation time	3442711130 ps
CPU time	227.67 seconds
Started	Apr 23 04:39:07 PM PDT 24
Finished	Apr 23 04:42:55 PM PDT 24
Peak memory	593296 kb
Host	smart-aeb7efdf-5dd3-4834-b47b-528aae35085f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278281831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.3278281831
Directory	/workspace/27.chip_tl_errors/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1650891229
Short name	T201
Test name
Test status
Simulation time	8552898049 ps
CPU time	1581.18 seconds
Started	Apr 23 04:27:37 PM PDT 24
Finished	Apr 23 04:53:59 PM PDT 24
Peak memory	609528 kb
Host	smart-401ea9b6-9c35-4f64-8781-198231465bbe
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650891229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.1650891229
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1552317933
Short name	T143
Test name
Test status
Simulation time	4066681313 ps
CPU time	281.11 seconds
Started	Apr 23 04:29:18 PM PDT 24
Finished	Apr 23 04:33:59 PM PDT 24
Peak memory	651644 kb
Host	smart-e1cf32bf-8e38-4611-9886-61ac8f32adc7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552317933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.1552317933
Directory	/workspace/2.chip_csr_hw_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3791769866
Short name	T34
Test name
Test status
Simulation time	2484437090 ps
CPU time	282.99 seconds
Started	Apr 23 03:51:22 PM PDT 24
Finished	Apr 23 03:56:06 PM PDT 24
Peak memory	600352 kb
Host	smart-6a3322d0-9ab6-449d-bdee-439073c8d869
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791769866 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.3791769866
Directory	/workspace/0.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2260704687
Short name	T184
Test name
Test status
Simulation time	5570558369 ps
CPU time	520.47 seconds
Started	Apr 23 04:08:48 PM PDT 24
Finished	Apr 23 04:17:29 PM PDT 24
Peak memory	601052 kb
Host	smart-afbe7372-18cf-4305-b1cf-c374d65d8849
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260704687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.2260704687
Directory	/workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2455481997
Short name	T2798
Test name
Test status
Simulation time	4077940004 ps
CPU time	286.94 seconds
Started	Apr 23 04:25:50 PM PDT 24
Finished	Apr 23 04:30:38 PM PDT 24
Peak memory	637732 kb
Host	smart-fd9024b0-f244-4c63-ac9e-90d23d4f1cef
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455481997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.2455481997
Directory	/workspace/3.chip_padctrl_attributes/latest

Test location	/workspace/coverage/default/46.chip_sw_all_escalation_resets.747638373
Short name	T173
Test name
Test status
Simulation time	5123284938 ps
CPU time	559.12 seconds
Started	Apr 23 04:29:49 PM PDT 24
Finished	Apr 23 04:39:09 PM PDT 24
Peak memory	635676 kb
Host	smart-74a21cdb-a4b5-45c9-84b6-04649a2fe41f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 747638373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.747638373
Directory	/workspace/46.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all.2773821179
Short name	T418
Test name
Test status
Simulation time	7706749592 ps
CPU time	317.34 seconds
Started	Apr 23 04:49:13 PM PDT 24
Finished	Apr 23 04:54:30 PM PDT 24
Peak memory	563936 kb
Host	smart-0e418ce1-9af2-40ff-810e-6464683c0175
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773821179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.2773821179
Directory	/workspace/88.xbar_stress_all/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2842537246
Short name	T13
Test name
Test status
Simulation time	3724334620 ps
CPU time	748.35 seconds
Started	Apr 23 03:52:56 PM PDT 24
Finished	Apr 23 04:05:25 PM PDT 24
Peak memory	608564 kb
Host	smart-b01dc9bf-831b-4d28-9bac-20752ae52a9e
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842537246 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2842537246
Directory	/workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.3275931999
Short name	T481
Test name
Test status
Simulation time	7771495758 ps
CPU time	555.44 seconds
Started	Apr 23 04:48:32 PM PDT 24
Finished	Apr 23 04:57:48 PM PDT 24
Peak memory	572132 kb
Host	smart-4c7e3e73-d962-4a1c-babd-84c09633b18b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275931999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.3275931999
Directory	/workspace/84.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/25.chip_tl_errors.1845510749
Short name	T601
Test name
Test status
Simulation time	4253121402 ps
CPU time	219.4 seconds
Started	Apr 23 04:38:49 PM PDT 24
Finished	Apr 23 04:42:28 PM PDT 24
Peak memory	593416 kb
Host	smart-3fb25ef9-21e0-4d08-97a8-e72b2aa6b577
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845510749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1845510749
Directory	/workspace/25.chip_tl_errors/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_20.4261781258
Short name	T300
Test name
Test status
Simulation time	4656811104 ps
CPU time	763.33 seconds
Started	Apr 23 04:28:12 PM PDT 24
Finished	Apr 23 04:40:56 PM PDT 24
Peak memory	600228 kb
Host	smart-89bbd9e4-daeb-42a8-bb4a-2a1a2548907b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261781258 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.4261781258
Directory	/workspace/2.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1227169991
Short name	T139
Test name
Test status
Simulation time	5548915420 ps
CPU time	568.31 seconds
Started	Apr 23 04:10:04 PM PDT 24
Finished	Apr 23 04:19:33 PM PDT 24
Peak memory	600228 kb
Host	smart-a73fa7a6-e1f1-4ab6-9f4d-7ef78fe71f8b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12271699 91 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1227169991
Directory	/workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2642504340
Short name	T54
Test name
Test status
Simulation time	3483163360 ps
CPU time	354.67 seconds
Started	Apr 23 03:57:51 PM PDT 24
Finished	Apr 23 04:03:47 PM PDT 24
Peak memory	609432 kb
Host	smart-7818a9ba-bc88-4459-a388-1256394eeaa7
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 642504340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.2642504340
Directory	/workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_0.4054021963
Short name	T308
Test name
Test status
Simulation time	6365622126 ps
CPU time	820.46 seconds
Started	Apr 23 03:55:58 PM PDT 24
Finished	Apr 23 04:09:39 PM PDT 24
Peak memory	600240 kb
Host	smart-7f397463-112f-432b-9d9c-7eb4ccbd9ce8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054021963 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.4054021963
Directory	/workspace/0.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1862573591
Short name	T215
Test name
Test status
Simulation time	25771743043 ps
CPU time	2130.29 seconds
Started	Apr 23 04:11:07 PM PDT 24
Finished	Apr 23 04:46:38 PM PDT 24
Peak memory	607312 kb
Host	smart-3013754c-540b-4ca7-af67-66d1d492073b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1862573591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.1862573591
Directory	/workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_power_sleep_load.3382275973
Short name	T115
Test name
Test status
Simulation time	4333472120 ps
CPU time	386.63 seconds
Started	Apr 23 04:13:10 PM PDT 24
Finished	Apr 23 04:19:38 PM PDT 24
Peak memory	600640 kb
Host	smart-3a6832f1-ef26-48a5-9f2a-3d3fb94c2a9b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382275973 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.3382275973
Directory	/workspace/1.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2700582113
Short name	T65
Test name
Test status
Simulation time	3406777836 ps
CPU time	458.06 seconds
Started	Apr 23 03:50:14 PM PDT 24
Finished	Apr 23 03:57:53 PM PDT 24
Peak memory	599976 kb
Host	smart-dbfd5196-c5ca-4a4e-8b0d-826d8d5f2a7c
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270058 2113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.2700582113
Directory	/workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.275277338
Short name	T819
Test name
Test status
Simulation time	1848898674 ps
CPU time	203.66 seconds
Started	Apr 23 04:45:59 PM PDT 24
Finished	Apr 23 04:49:23 PM PDT 24
Peak memory	563888 kb
Host	smart-d2faf198-9113-4759-91aa-a9fbe67b80ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275277338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_ with_rand_reset.275277338
Directory	/workspace/68.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3623789652
Short name	T19
Test name
Test status
Simulation time	20496309958 ps
CPU time	1342.74 seconds
Started	Apr 23 04:06:15 PM PDT 24
Finished	Apr 23 04:28:38 PM PDT 24
Peak memory	604656 kb
Host	smart-f49d4e08-1077-4d9f-adeb-8b427493d394
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237896 52 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.3623789652
Directory	/workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.63708455
Short name	T806
Test name
Test status
Simulation time	2129287449 ps
CPU time	390.59 seconds
Started	Apr 23 04:36:45 PM PDT 24
Finished	Apr 23 04:43:15 PM PDT 24
Peak memory	572128 kb
Host	smart-734fd1eb-70a3-482c-85fd-d1269de85b81
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63708455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_w ith_rand_reset.63708455
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.782230585
Short name	T145
Test name
Test status
Simulation time	6310191399 ps
CPU time	406.86 seconds
Started	Apr 23 04:28:27 PM PDT 24
Finished	Apr 23 04:35:14 PM PDT 24
Peak memory	652728 kb
Host	smart-4546b245-4f80-4648-bad7-9a08704165a7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782230585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_re set.782230585
Directory	/workspace/1.chip_csr_hw_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.192753282
Short name	T165
Test name
Test status
Simulation time	3563973352 ps
CPU time	292.52 seconds
Started	Apr 23 04:07:49 PM PDT 24
Finished	Apr 23 04:12:42 PM PDT 24
Peak memory	608440 kb
Host	smart-e141fdd6-d7c7-442d-8dd2-19a54ed5a597
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192753282 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.192753282
Directory	/workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1935845119
Short name	T185
Test name
Test status
Simulation time	43000363399 ps
CPU time	4919.26 seconds
Started	Apr 23 04:20:45 PM PDT 24
Finished	Apr 23 05:42:45 PM PDT 24
Peak memory	615912 kb
Host	smart-31bcfc57-14b4-4900-8524-258d8eb72b27
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1935845119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.1935845119
Directory	/workspace/2.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/cover_reg_top/19.chip_tl_errors.2803731710
Short name	T517
Test name
Test status
Simulation time	4663709632 ps
CPU time	388.75 seconds
Started	Apr 23 04:37:08 PM PDT 24
Finished	Apr 23 04:43:37 PM PDT 24
Peak memory	593308 kb
Host	smart-51ffec4d-468d-4578-9a81-ced08a66528b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803731710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.2803731710
Directory	/workspace/19.chip_tl_errors/latest

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4122417386
Short name	T116
Test name
Test status
Simulation time	19583630432 ps
CPU time	2702.9 seconds
Started	Apr 23 04:25:45 PM PDT 24
Finished	Apr 23 05:10:49 PM PDT 24
Peak memory	600528 kb
Host	smart-ce48d1a8-418e-472f-b681-43c87923f77c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122417386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.4122417386
Directory	/workspace/2.chip_sw_ast_clk_rst_inputs/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3014217012
Short name	T344
Test name
Test status
Simulation time	4450022549 ps
CPU time	555.13 seconds
Started	Apr 23 03:51:01 PM PDT 24
Finished	Apr 23 04:00:17 PM PDT 24
Peak memory	600164 kb
Host	smart-022ba980-ed9c-4663-807a-47e3c9f0c89e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3014217012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.3014217012
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all.1377980203
Short name	T586
Test name
Test status
Simulation time	4354820038 ps
CPU time	370.55 seconds
Started	Apr 23 04:39:54 PM PDT 24
Finished	Apr 23 04:46:05 PM PDT 24
Peak memory	563928 kb
Host	smart-75569bfc-1346-4cb6-bd45-e30afb570db7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377980203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1377980203
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2744067773
Short name	T918
Test name
Test status
Simulation time	4018031960 ps
CPU time	585.83 seconds
Started	Apr 23 03:52:32 PM PDT 24
Finished	Apr 23 04:02:19 PM PDT 24
Peak memory	604232 kb
Host	smart-25dbb14f-c629-45fb-b018-8ec167fb3903
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744067773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2744067773
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1668148070
Short name	T461
Test name
Test status
Simulation time	9003255232 ps
CPU time	813.66 seconds
Started	Apr 23 04:45:09 PM PDT 24
Finished	Apr 23 04:58:43 PM PDT 24
Peak memory	572160 kb
Host	smart-df35ef1b-dea4-4263-a449-cf5fe256a963
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668148070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.1668148070
Directory	/workspace/63.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_gpio.3701166659
Short name	T27
Test name
Test status
Simulation time	3653701340 ps
CPU time	532.14 seconds
Started	Apr 23 04:04:29 PM PDT 24
Finished	Apr 23 04:13:21 PM PDT 24
Peak memory	600520 kb
Host	smart-c4a743c7-aad9-4362-9bed-a6bb95b514e7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701166659 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.3701166659
Directory	/workspace/1.chip_sw_gpio/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1895262695
Short name	T148
Test name
Test status
Simulation time	7355063196 ps
CPU time	296.72 seconds
Started	Apr 23 04:06:37 PM PDT 24
Finished	Apr 23 04:11:35 PM PDT 24
Peak memory	600272 kb
Host	smart-16f8df5e-a6bf-4b7f-993b-170e2b820a70
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895262695 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.1895262695
Directory	/workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2081172145
Short name	T212
Test name
Test status
Simulation time	48372306261 ps
CPU time	5584.04 seconds
Started	Apr 23 03:51:14 PM PDT 24
Finished	Apr 23 05:24:20 PM PDT 24
Peak memory	608636 kb
Host	smart-422bea09-3165-4ed8-9f82-f2558620e22e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081172145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.2081172145
Directory	/workspace/0.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.79643689
Short name	T820
Test name
Test status
Simulation time	10226418225 ps
CPU time	536.13 seconds
Started	Apr 23 04:36:49 PM PDT 24
Finished	Apr 23 04:45:46 PM PDT 24
Peak memory	572212 kb
Host	smart-b4812120-b49b-454b-9ddb-13267a843b97
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79643689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_ with_reset_error.79643689
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2447904343
Short name	T824
Test name
Test status
Simulation time	350916750 ps
CPU time	166.98 seconds
Started	Apr 23 04:42:06 PM PDT 24
Finished	Apr 23 04:44:53 PM PDT 24
Peak memory	563916 kb
Host	smart-b835d2ed-83c9-4401-b9da-834880a4c870
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447904343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.2447904343
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/23.chip_tl_errors.433429078
Short name	T1961
Test name
Test status
Simulation time	4441428928 ps
CPU time	263.18 seconds
Started	Apr 23 04:38:11 PM PDT 24
Finished	Apr 23 04:42:34 PM PDT 24
Peak memory	593260 kb
Host	smart-5dc1cc26-bd62-4c9e-b45c-e38696127da5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433429078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.433429078
Directory	/workspace/23.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all.2448770863
Short name	T2120
Test name
Test status
Simulation time	3068581356 ps
CPU time	232.41 seconds
Started	Apr 23 04:31:32 PM PDT 24
Finished	Apr 23 04:35:25 PM PDT 24
Peak memory	563116 kb
Host	smart-5778e606-fa11-4efb-8f35-1f2c4e508905
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448770863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2448770863
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_10.3190926885
Short name	T163
Test name
Test status
Simulation time	4197508980 ps
CPU time	598.64 seconds
Started	Apr 23 04:28:01 PM PDT 24
Finished	Apr 23 04:38:00 PM PDT 24
Peak memory	599924 kb
Host	smart-414bbe59-16ef-4d29-9dc0-b9c6b7752efa
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190926885 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.3190926885
Directory	/workspace/2.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/24.chip_sw_all_escalation_resets.269926408
Short name	T31
Test name
Test status
Simulation time	4143029660 ps
CPU time	575 seconds
Started	Apr 23 04:29:17 PM PDT 24
Finished	Apr 23 04:38:52 PM PDT 24
Peak memory	635588 kb
Host	smart-57f74dd2-a03f-45b8-8616-1c26a9cc41d4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 269926408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.269926408
Directory	/workspace/24.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2673299448
Short name	T281
Test name
Test status
Simulation time	5979052175 ps
CPU time	470.84 seconds
Started	Apr 23 03:54:53 PM PDT 24
Finished	Apr 23 04:02:44 PM PDT 24
Peak memory	600588 kb
Host	smart-547fef3b-2688-4352-98c7-8c4f764a1f08
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673299448 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2673299448
Directory	/workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2783334357
Short name	T816
Test name
Test status
Simulation time	8151776323 ps
CPU time	533.01 seconds
Started	Apr 23 04:37:25 PM PDT 24
Finished	Apr 23 04:46:18 PM PDT 24
Peak memory	572172 kb
Host	smart-bbdc7759-36a7-4f06-ba2b-32966261b9c1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783334357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2783334357
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2915005254
Short name	T131
Test name
Test status
Simulation time	8010137908 ps
CPU time	1523.87 seconds
Started	Apr 23 03:53:58 PM PDT 24
Finished	Apr 23 04:19:22 PM PDT 24
Peak memory	600308 kb
Host	smart-55b117c6-2dc2-48e2-9c30-4080e84fc807
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2915005254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2915005254
Directory	/workspace/0.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/1.chip_sw_pattgen_ios.3910939357
Short name	T320
Test name
Test status
Simulation time	2616245630 ps
CPU time	209.81 seconds
Started	Apr 23 04:05:05 PM PDT 24
Finished	Apr 23 04:08:36 PM PDT 24
Peak memory	600404 kb
Host	smart-b084db1d-563b-4f5d-9bbe-3933555bd24b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910939357 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.3910939357
Directory	/workspace/1.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1222072209
Short name	T102
Test name
Test status
Simulation time	2658934139 ps
CPU time	254.26 seconds
Started	Apr 23 03:52:01 PM PDT 24
Finished	Apr 23 03:56:16 PM PDT 24
Peak memory	607480 kb
Host	smart-d238a51b-1d74-4e87-bf2b-526018e552bb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222072209 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1222072209
Directory	/workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/68.chip_sw_all_escalation_resets.2194946617
Short name	T685
Test name
Test status
Simulation time	4911815000 ps
CPU time	763.05 seconds
Started	Apr 23 04:31:02 PM PDT 24
Finished	Apr 23 04:43:46 PM PDT 24
Peak memory	635632 kb
Host	smart-c08ad6b6-0f36-4d2a-9b29-b150a5349502
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2194946617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2194946617
Directory	/workspace/68.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/85.chip_sw_all_escalation_resets.1447894073
Short name	T70
Test name
Test status
Simulation time	4758254534 ps
CPU time	479.78 seconds
Started	Apr 23 04:32:27 PM PDT 24
Finished	Apr 23 04:40:27 PM PDT 24
Peak memory	635636 kb
Host	smart-8e785c47-6338-4b5a-85d9-b86fe7cc5601
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1447894073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.1447894073
Directory	/workspace/85.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3042763639
Short name	T342
Test name
Test status
Simulation time	17873821675 ps
CPU time	2200.42 seconds
Started	Apr 23 04:06:31 PM PDT 24
Finished	Apr 23 04:43:13 PM PDT 24
Peak memory	602264 kb
Host	smart-7773fe19-d021-431a-9b06-d94078f9c071
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3042763639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3042763639
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.651945476
Short name	T204
Test name
Test status
Simulation time	4366415787 ps
CPU time	386.76 seconds
Started	Apr 23 03:49:42 PM PDT 24
Finished	Apr 23 03:56:10 PM PDT 24
Peak memory	616992 kb
Host	smart-c045bd6b-95c7-4bc8-9d94-4122a5441e9a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651945476 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.651945476
Directory	/workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all.856987073
Short name	T1828
Test name
Test status
Simulation time	9139604541 ps
CPU time	383.48 seconds
Started	Apr 23 04:28:12 PM PDT 24
Finished	Apr 23 04:34:36 PM PDT 24
Peak memory	563992 kb
Host	smart-1ecdcf12-9aa1-415c-b4c1-8c50312a99ec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856987073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.856987073
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc.3079473409
Short name	T334
Test name
Test status
Simulation time	2796453000 ps
CPU time	270.64 seconds
Started	Apr 23 04:09:19 PM PDT 24
Finished	Apr 23 04:13:50 PM PDT 24
Peak memory	600172 kb
Host	smart-de16aec6-0abb-468a-9c1e-7aa2ed51148d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079473409 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.3079473409
Directory	/workspace/1.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3402009026
Short name	T144
Test name
Test status
Simulation time	4893469454 ps
CPU time	267.92 seconds
Started	Apr 23 04:31:08 PM PDT 24
Finished	Apr 23 04:35:37 PM PDT 24
Peak memory	650420 kb
Host	smart-378a7241-580e-49c2-aeb2-022418eda303
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402009026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.3402009026
Directory	/workspace/4.chip_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.chip_tl_errors.3434922893
Short name	T518
Test name
Test status
Simulation time	3428332000 ps
CPU time	178.61 seconds
Started	Apr 23 04:33:16 PM PDT 24
Finished	Apr 23 04:36:15 PM PDT 24
Peak memory	593684 kb
Host	smart-4f65a5c0-d71e-4343-84ee-b0e799a26486
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434922893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3434922893
Directory	/workspace/9.chip_tl_errors/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3559812675
Short name	T285
Test name
Test status
Simulation time	3299463984 ps
CPU time	316.91 seconds
Started	Apr 23 03:52:54 PM PDT 24
Finished	Apr 23 03:58:11 PM PDT 24
Peak memory	634208 kb
Host	smart-e3a61453-b8f4-4e61-aafb-959e5bd070c9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559812675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.3559812675
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/0.chip_sw_all_escalation_resets.171299084
Short name	T379
Test name
Test status
Simulation time	5227223592 ps
CPU time	527.36 seconds
Started	Apr 23 03:51:30 PM PDT 24
Finished	Apr 23 04:00:17 PM PDT 24
Peak memory	635636 kb
Host	smart-c095880f-dac1-40e6-bdb0-5100dbe4f7fe
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 171299084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.171299084
Directory	/workspace/0.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1443562046
Short name	T1151
Test name
Test status
Simulation time	3663773608 ps
CPU time	501.43 seconds
Started	Apr 23 04:08:52 PM PDT 24
Finished	Apr 23 04:17:14 PM PDT 24
Peak memory	633400 kb
Host	smart-8a9b8ffb-74bd-4e23-a5de-adb0b36f086e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443562046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.1443562046
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/1.chip_sw_all_escalation_resets.944371116
Short name	T745
Test name
Test status
Simulation time	4753778604 ps
CPU time	728.98 seconds
Started	Apr 23 04:03:32 PM PDT 24
Finished	Apr 23 04:15:42 PM PDT 24
Peak memory	635656 kb
Host	smart-4287eac5-301a-462f-90ce-cb578971ccf1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 944371116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.944371116
Directory	/workspace/1.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/11.chip_sw_all_escalation_resets.661241937
Short name	T244
Test name
Test status
Simulation time	5505077982 ps
CPU time	693.72 seconds
Started	Apr 23 04:28:57 PM PDT 24
Finished	Apr 23 04:40:32 PM PDT 24
Peak memory	637580 kb
Host	smart-74a9528a-71a8-4f12-a28f-6bd0bfa6e6b0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 661241937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.661241937
Directory	/workspace/11.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3043989000
Short name	T266
Test name
Test status
Simulation time	3181764552 ps
CPU time	366.39 seconds
Started	Apr 23 04:30:18 PM PDT 24
Finished	Apr 23 04:36:25 PM PDT 24
Peak memory	633632 kb
Host	smart-c3285b03-79fe-4876-bfae-b89870077226
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043989000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3043989000
Directory	/workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3916846455
Short name	T1219
Test name
Test status
Simulation time	5483205660 ps
CPU time	654.71 seconds
Started	Apr 23 04:28:59 PM PDT 24
Finished	Apr 23 04:39:54 PM PDT 24
Peak memory	634476 kb
Host	smart-b0e02cbf-de29-4a61-85cb-329d624816a0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3916846455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3916846455
Directory	/workspace/12.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614186391
Short name	T652
Test name
Test status
Simulation time	2970690340 ps
CPU time	361.83 seconds
Started	Apr 23 04:30:13 PM PDT 24
Finished	Apr 23 04:36:15 PM PDT 24
Peak memory	633404 kb
Host	smart-30aa09b5-1070-4134-b7bd-edaa458aba36
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614186391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1614186391
Directory	/workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3910494045
Short name	T712
Test name
Test status
Simulation time	3735622496 ps
CPU time	450.24 seconds
Started	Apr 23 04:29:20 PM PDT 24
Finished	Apr 23 04:36:51 PM PDT 24
Peak memory	635372 kb
Host	smart-5d9d828e-1158-4c68-94ce-9dfec3efbfa8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910494045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3910494045
Directory	/workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1906487897
Short name	T223
Test name
Test status
Simulation time	5057231128 ps
CPU time	697.46 seconds
Started	Apr 23 04:28:35 PM PDT 24
Finished	Apr 23 04:40:13 PM PDT 24
Peak memory	637664 kb
Host	smart-99cb1458-ea9e-45a7-88a7-8e34d14afdfa
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1906487897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1906487897
Directory	/workspace/14.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.4240992434
Short name	T1158
Test name
Test status
Simulation time	3900463784 ps
CPU time	442.23 seconds
Started	Apr 23 04:28:22 PM PDT 24
Finished	Apr 23 04:35:45 PM PDT 24
Peak memory	633396 kb
Host	smart-3796a46d-f58c-4380-a618-dac02acef5da
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240992434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4240992434
Directory	/workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/16.chip_sw_all_escalation_resets.4146440032
Short name	T290
Test name
Test status
Simulation time	6123868992 ps
CPU time	605.22 seconds
Started	Apr 23 04:27:55 PM PDT 24
Finished	Apr 23 04:38:00 PM PDT 24
Peak memory	635496 kb
Host	smart-ff8bf8c0-a409-43c2-9ae1-c24be55609fc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4146440032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.4146440032
Directory	/workspace/16.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770713062
Short name	T95
Test name
Test status
Simulation time	2823955400 ps
CPU time	336.78 seconds
Started	Apr 23 04:30:23 PM PDT 24
Finished	Apr 23 04:36:00 PM PDT 24
Peak memory	634576 kb
Host	smart-38ca9f88-5f7e-4704-b257-76b0c9053b67
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770713062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2770713062
Directory	/workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3743727240
Short name	T272
Test name
Test status
Simulation time	3453515832 ps
CPU time	347.24 seconds
Started	Apr 23 04:28:44 PM PDT 24
Finished	Apr 23 04:34:32 PM PDT 24
Peak memory	633556 kb
Host	smart-8c8d3278-fbdf-49c9-aac3-379ca8aec0cb
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743727240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3743727240
Directory	/workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.767670101
Short name	T676
Test name
Test status
Simulation time	3875222152 ps
CPU time	466.44 seconds
Started	Apr 23 04:30:15 PM PDT 24
Finished	Apr 23 04:38:02 PM PDT 24
Peak memory	633320 kb
Host	smart-3722aad5-8426-44f9-b74a-e1a0d92e94ba
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767670101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_s w_alert_handler_lpg_sleep_mode_alerts.767670101
Directory	/workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2608207430
Short name	T66
Test name
Test status
Simulation time	3843456680 ps
CPU time	460.84 seconds
Started	Apr 23 04:21:53 PM PDT 24
Finished	Apr 23 04:29:34 PM PDT 24
Peak memory	635728 kb
Host	smart-87564842-045e-4e3b-beed-ac8737d34326
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608207430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.2608207430
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/2.chip_sw_all_escalation_resets.2764823654
Short name	T1168
Test name
Test status
Simulation time	5901136148 ps
CPU time	671.4 seconds
Started	Apr 23 04:14:56 PM PDT 24
Finished	Apr 23 04:26:08 PM PDT 24
Peak memory	637584 kb
Host	smart-eb80feed-9c31-461c-b71e-2d33ede6f18b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2764823654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.2764823654
Directory	/workspace/2.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1812983731
Short name	T730
Test name
Test status
Simulation time	3794361000 ps
CPU time	401.4 seconds
Started	Apr 23 04:29:27 PM PDT 24
Finished	Apr 23 04:36:09 PM PDT 24
Peak memory	633656 kb
Host	smart-9bb91d0d-e5b2-4dc3-aa69-c1bae388fa98
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812983731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1812983731
Directory	/workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/20.chip_sw_all_escalation_resets.138820280
Short name	T749
Test name
Test status
Simulation time	5091108040 ps
CPU time	754.48 seconds
Started	Apr 23 04:28:36 PM PDT 24
Finished	Apr 23 04:41:11 PM PDT 24
Peak memory	634608 kb
Host	smart-910a3430-f8cd-40c3-b62b-318fad37977f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 138820280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.138820280
Directory	/workspace/20.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4282789989
Short name	T714
Test name
Test status
Simulation time	3485062144 ps
CPU time	399.98 seconds
Started	Apr 23 04:28:12 PM PDT 24
Finished	Apr 23 04:34:52 PM PDT 24
Peak memory	633424 kb
Host	smart-d954daca-1cab-4b2a-bc61-18d0ab8d9b03
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282789989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4282789989
Directory	/workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/21.chip_sw_all_escalation_resets.1584227785
Short name	T177
Test name
Test status
Simulation time	4159135500 ps
CPU time	548.39 seconds
Started	Apr 23 04:29:05 PM PDT 24
Finished	Apr 23 04:38:13 PM PDT 24
Peak memory	635516 kb
Host	smart-eb24e781-a1c3-4d4c-a6ca-ce7b4e16e6b5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1584227785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1584227785
Directory	/workspace/21.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1783970961
Short name	T698
Test name
Test status
Simulation time	4173557700 ps
CPU time	316.55 seconds
Started	Apr 23 04:28:17 PM PDT 24
Finished	Apr 23 04:33:35 PM PDT 24
Peak memory	633768 kb
Host	smart-66688cb9-d738-4684-a208-e1398de2fa00
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783970961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1783970961
Directory	/workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452451143
Short name	T667
Test name
Test status
Simulation time	3575812040 ps
CPU time	390.06 seconds
Started	Apr 23 04:30:28 PM PDT 24
Finished	Apr 23 04:36:58 PM PDT 24
Peak memory	633328 kb
Host	smart-5248d963-92bc-4892-b38d-aff4279c311b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452451143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2452451143
Directory	/workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1959927969
Short name	T616
Test name
Test status
Simulation time	3727557080 ps
CPU time	301.67 seconds
Started	Apr 23 04:30:21 PM PDT 24
Finished	Apr 23 04:35:24 PM PDT 24
Peak memory	633668 kb
Host	smart-644649e3-17ea-4031-9d08-1a6bc681c06c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959927969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1959927969
Directory	/workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/25.chip_sw_all_escalation_resets.722401691
Short name	T660
Test name
Test status
Simulation time	3995522940 ps
CPU time	706.41 seconds
Started	Apr 23 04:32:16 PM PDT 24
Finished	Apr 23 04:44:03 PM PDT 24
Peak memory	635416 kb
Host	smart-091ccb57-158b-43bb-b430-4ee8c9919b09
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 722401691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.722401691
Directory	/workspace/25.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3978933851
Short name	T657
Test name
Test status
Simulation time	3443716428 ps
CPU time	356.98 seconds
Started	Apr 23 04:30:32 PM PDT 24
Finished	Apr 23 04:36:30 PM PDT 24
Peak memory	633420 kb
Host	smart-8f2419f8-a688-48d5-9983-e2598dfbba01
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978933851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3978933851
Directory	/workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2591903153
Short name	T721
Test name
Test status
Simulation time	4131986392 ps
CPU time	379.83 seconds
Started	Apr 23 04:28:34 PM PDT 24
Finished	Apr 23 04:34:54 PM PDT 24
Peak memory	633640 kb
Host	smart-828743e3-f34a-4afd-9193-35a914e31c63
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591903153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2591903153
Directory	/workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3048587514
Short name	T683
Test name
Test status
Simulation time	4134595532 ps
CPU time	705.84 seconds
Started	Apr 23 04:29:06 PM PDT 24
Finished	Apr 23 04:40:52 PM PDT 24
Peak memory	634308 kb
Host	smart-f449d560-988f-4098-925f-71549fb14722
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3048587514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.3048587514
Directory	/workspace/28.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2476251623
Short name	T692
Test name
Test status
Simulation time	4014556564 ps
CPU time	283.05 seconds
Started	Apr 23 04:28:46 PM PDT 24
Finished	Apr 23 04:33:29 PM PDT 24
Peak memory	633564 kb
Host	smart-18fb13a0-74b7-4de9-9267-5d9ecec8b94e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476251623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2476251623
Directory	/workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607150158
Short name	T707
Test name
Test status
Simulation time	4234662528 ps
CPU time	572.19 seconds
Started	Apr 23 04:29:59 PM PDT 24
Finished	Apr 23 04:39:32 PM PDT 24
Peak memory	634520 kb
Host	smart-c3fe282c-f9e7-45aa-972d-146aadefa6a4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607150158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2607150158
Directory	/workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.161987209
Short name	T715
Test name
Test status
Simulation time	3673607800 ps
CPU time	498.22 seconds
Started	Apr 23 04:31:12 PM PDT 24
Finished	Apr 23 04:39:31 PM PDT 24
Peak memory	633484 kb
Host	smart-7991c10b-87b7-4a77-95d1-3fefa58435b0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161987209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s w_alert_handler_lpg_sleep_mode_alerts.161987209
Directory	/workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/31.chip_sw_all_escalation_resets.3173614761
Short name	T224
Test name
Test status
Simulation time	4855080328 ps
CPU time	609.33 seconds
Started	Apr 23 04:31:16 PM PDT 24
Finished	Apr 23 04:41:26 PM PDT 24
Peak memory	637824 kb
Host	smart-4096c945-b1d3-4b8c-9428-bec9d8eccf49
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3173614761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.3173614761
Directory	/workspace/31.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.311712474
Short name	T705
Test name
Test status
Simulation time	4256958422 ps
CPU time	429.05 seconds
Started	Apr 23 04:31:42 PM PDT 24
Finished	Apr 23 04:38:52 PM PDT 24
Peak memory	635388 kb
Host	smart-ae25959f-bc04-4cd7-8fcb-e0943bdb9683
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311712474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_s w_alert_handler_lpg_sleep_mode_alerts.311712474
Directory	/workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1976943208
Short name	T673
Test name
Test status
Simulation time	3186773036 ps
CPU time	328.33 seconds
Started	Apr 23 04:31:01 PM PDT 24
Finished	Apr 23 04:36:30 PM PDT 24
Peak memory	635388 kb
Host	smart-56a251f6-03f2-4165-b986-153a24cdc706
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976943208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1976943208
Directory	/workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/35.chip_sw_all_escalation_resets.2965762992
Short name	T656
Test name
Test status
Simulation time	5240261800 ps
CPU time	606.64 seconds
Started	Apr 23 04:30:19 PM PDT 24
Finished	Apr 23 04:40:26 PM PDT 24
Peak memory	635576 kb
Host	smart-efadb477-dd3a-46c4-8c18-9282bd6fe0fe
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2965762992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2965762992
Directory	/workspace/35.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3869306139
Short name	T689
Test name
Test status
Simulation time	3652218550 ps
CPU time	404.97 seconds
Started	Apr 23 04:30:57 PM PDT 24
Finished	Apr 23 04:37:42 PM PDT 24
Peak memory	633288 kb
Host	smart-fe2c879b-aa2c-4b05-8a00-1d3f7390a595
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869306139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3869306139
Directory	/workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2084558570
Short name	T339
Test name
Test status
Simulation time	6225507710 ps
CPU time	659.34 seconds
Started	Apr 23 04:30:52 PM PDT 24
Finished	Apr 23 04:41:52 PM PDT 24
Peak memory	637568 kb
Host	smart-a3aa1165-986e-49a3-8cfe-480c8dd9b9a6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2084558570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.2084558570
Directory	/workspace/36.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4223094493
Short name	T371
Test name
Test status
Simulation time	4562831980 ps
CPU time	399.57 seconds
Started	Apr 23 04:31:36 PM PDT 24
Finished	Apr 23 04:38:16 PM PDT 24
Peak memory	633976 kb
Host	smart-5477f8ba-b86e-44da-a57b-6f43bb3e86ce
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223094493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4223094493
Directory	/workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.134735882
Short name	T265
Test name
Test status
Simulation time	3749631630 ps
CPU time	334.48 seconds
Started	Apr 23 04:31:17 PM PDT 24
Finished	Apr 23 04:36:52 PM PDT 24
Peak memory	635652 kb
Host	smart-607b0d65-ce02-4e6c-baae-84448c953b18
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134735882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_s w_alert_handler_lpg_sleep_mode_alerts.134735882
Directory	/workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4052214153
Short name	T708
Test name
Test status
Simulation time	4392211750 ps
CPU time	438.33 seconds
Started	Apr 23 04:32:35 PM PDT 24
Finished	Apr 23 04:39:54 PM PDT 24
Peak memory	633904 kb
Host	smart-7ac0f749-5fba-4bda-a5c7-c45a1b7a26cc
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052214153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4052214153
Directory	/workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/44.chip_sw_all_escalation_resets.2123625269
Short name	T399
Test name
Test status
Simulation time	4949901254 ps
CPU time	518.24 seconds
Started	Apr 23 04:32:28 PM PDT 24
Finished	Apr 23 04:41:07 PM PDT 24
Peak memory	635584 kb
Host	smart-e67cc9d2-5288-46b5-b3c8-1526764dcdd4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2123625269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.2123625269
Directory	/workspace/44.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/45.chip_sw_all_escalation_resets.565530088
Short name	T752
Test name
Test status
Simulation time	5300262148 ps
CPU time	746.34 seconds
Started	Apr 23 04:29:14 PM PDT 24
Finished	Apr 23 04:41:41 PM PDT 24
Peak memory	634660 kb
Host	smart-b77acccf-fe53-483e-9186-a06b918fef0b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 565530088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.565530088
Directory	/workspace/45.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.906431928
Short name	T650
Test name
Test status
Simulation time	4009156088 ps
CPU time	446.51 seconds
Started	Apr 23 04:31:58 PM PDT 24
Finished	Apr 23 04:39:25 PM PDT 24
Peak memory	633384 kb
Host	smart-ffa85e2a-9137-4b4d-ace4-fb4f2de064e9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906431928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_s w_alert_handler_lpg_sleep_mode_alerts.906431928
Directory	/workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050403671
Short name	T626
Test name
Test status
Simulation time	3858881820 ps
CPU time	455.58 seconds
Started	Apr 23 04:27:58 PM PDT 24
Finished	Apr 23 04:35:34 PM PDT 24
Peak memory	633388 kb
Host	smart-19c74913-23cb-48a1-b6fe-cfcbeaf4fb0b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050403671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.4050403671
Directory	/workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416455129
Short name	T2
Test name
Test status
Simulation time	4293165780 ps
CPU time	480.7 seconds
Started	Apr 23 04:32:43 PM PDT 24
Finished	Apr 23 04:40:44 PM PDT 24
Peak memory	633388 kb
Host	smart-62bb5c39-64e4-474b-8b6a-76164caa64fe
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416455129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1416455129
Directory	/workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3689427018
Short name	T734
Test name
Test status
Simulation time	5261566686 ps
CPU time	716.7 seconds
Started	Apr 23 04:30:48 PM PDT 24
Finished	Apr 23 04:42:45 PM PDT 24
Peak memory	636568 kb
Host	smart-4d280c79-e2b1-491e-9fc1-84b18f169a89
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3689427018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3689427018
Directory	/workspace/51.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2309657935
Short name	T733
Test name
Test status
Simulation time	3706027500 ps
CPU time	436.88 seconds
Started	Apr 23 04:30:37 PM PDT 24
Finished	Apr 23 04:37:54 PM PDT 24
Peak memory	633492 kb
Host	smart-0b3a57b4-e377-4560-b8a4-efe9bf25c5a2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309657935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2309657935
Directory	/workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3967450380
Short name	T728
Test name
Test status
Simulation time	4255262936 ps
CPU time	359.16 seconds
Started	Apr 23 04:31:34 PM PDT 24
Finished	Apr 23 04:37:34 PM PDT 24
Peak memory	633352 kb
Host	smart-44e59ec6-99a7-415f-90c6-fb6136993506
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967450380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3967450380
Directory	/workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/6.chip_sw_all_escalation_resets.2558135743
Short name	T687
Test name
Test status
Simulation time	5936901660 ps
CPU time	571.2 seconds
Started	Apr 23 04:29:23 PM PDT 24
Finished	Apr 23 04:38:54 PM PDT 24
Peak memory	635656 kb
Host	smart-be6d22c7-9be1-4400-9bd4-dd105179962e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2558135743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.2558135743
Directory	/workspace/6.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.445782987
Short name	T655
Test name
Test status
Simulation time	4324460280 ps
CPU time	378.54 seconds
Started	Apr 23 04:32:57 PM PDT 24
Finished	Apr 23 04:39:16 PM PDT 24
Peak memory	635740 kb
Host	smart-47831d2a-9b7a-43e2-aaad-2e1ccd9acba6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445782987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_s w_alert_handler_lpg_sleep_mode_alerts.445782987
Directory	/workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/61.chip_sw_all_escalation_resets.3287223778
Short name	T353
Test name
Test status
Simulation time	5238821882 ps
CPU time	502.07 seconds
Started	Apr 23 04:35:10 PM PDT 24
Finished	Apr 23 04:43:33 PM PDT 24
Peak memory	635712 kb
Host	smart-be49c5c9-1a60-42ee-a542-40bbad1559aa
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3287223778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.3287223778
Directory	/workspace/61.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/62.chip_sw_all_escalation_resets.3205375078
Short name	T111
Test name
Test status
Simulation time	5749538978 ps
CPU time	644.91 seconds
Started	Apr 23 04:31:25 PM PDT 24
Finished	Apr 23 04:42:11 PM PDT 24
Peak memory	634608 kb
Host	smart-973fe41c-f5aa-48d3-874d-2a8c204b893e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3205375078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.3205375078
Directory	/workspace/62.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.171249716
Short name	T385
Test name
Test status
Simulation time	3396029210 ps
CPU time	376.06 seconds
Started	Apr 23 04:35:16 PM PDT 24
Finished	Apr 23 04:41:33 PM PDT 24
Peak memory	634568 kb
Host	smart-326f220a-0d21-4b31-a90e-d947e2b280c9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171249716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s w_alert_handler_lpg_sleep_mode_alerts.171249716
Directory	/workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3450270123
Short name	T742
Test name
Test status
Simulation time	3133048612 ps
CPU time	417.79 seconds
Started	Apr 23 04:31:51 PM PDT 24
Finished	Apr 23 04:38:49 PM PDT 24
Peak memory	634344 kb
Host	smart-3cf311bf-fd65-4918-8f06-5d5c79e8a8c3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450270123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3450270123
Directory	/workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/65.chip_sw_all_escalation_resets.109346453
Short name	T702
Test name
Test status
Simulation time	5439134040 ps
CPU time	545.18 seconds
Started	Apr 23 04:32:01 PM PDT 24
Finished	Apr 23 04:41:06 PM PDT 24
Peak memory	635792 kb
Host	smart-e2a8bc38-8e53-417f-b4da-fc98cd92f987
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 109346453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.109346453
Directory	/workspace/65.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.752773173
Short name	T668
Test name
Test status
Simulation time	4133078404 ps
CPU time	402.06 seconds
Started	Apr 23 04:31:16 PM PDT 24
Finished	Apr 23 04:37:59 PM PDT 24
Peak memory	633428 kb
Host	smart-9d116540-77c1-4176-8828-b183a341e2c2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752773173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_s w_alert_handler_lpg_sleep_mode_alerts.752773173
Directory	/workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020330562
Short name	T741
Test name
Test status
Simulation time	3676717560 ps
CPU time	496.76 seconds
Started	Apr 23 04:36:43 PM PDT 24
Finished	Apr 23 04:45:00 PM PDT 24
Peak memory	633288 kb
Host	smart-e76ba224-429b-4f12-a899-a5143b333e59
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020330562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1020330562
Directory	/workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4195054137
Short name	T718
Test name
Test status
Simulation time	3481773168 ps
CPU time	347.15 seconds
Started	Apr 23 04:31:50 PM PDT 24
Finished	Apr 23 04:37:37 PM PDT 24
Peak memory	633516 kb
Host	smart-d52ea568-14c1-419e-9afa-50d85ac361b3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195054137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4195054137
Directory	/workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/73.chip_sw_all_escalation_resets.880397519
Short name	T664
Test name
Test status
Simulation time	6138924544 ps
CPU time	624.29 seconds
Started	Apr 23 04:31:57 PM PDT 24
Finished	Apr 23 04:42:21 PM PDT 24
Peak memory	637604 kb
Host	smart-57a079f9-9c53-4b16-9151-97369137b60c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 880397519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.880397519
Directory	/workspace/73.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4208958706
Short name	T696
Test name
Test status
Simulation time	4112120430 ps
CPU time	406.46 seconds
Started	Apr 23 04:32:31 PM PDT 24
Finished	Apr 23 04:39:17 PM PDT 24
Peak memory	633648 kb
Host	smart-5fb59eb3-9557-4500-ab2d-e9b32f250c19
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208958706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4208958706
Directory	/workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2157433369
Short name	T710
Test name
Test status
Simulation time	4369683264 ps
CPU time	473.83 seconds
Started	Apr 23 04:31:19 PM PDT 24
Finished	Apr 23 04:39:13 PM PDT 24
Peak memory	633784 kb
Host	smart-49df3dc1-792e-4766-9539-ae2f9330eeaa
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157433369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2157433369
Directory	/workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/8.chip_sw_all_escalation_resets.258138258
Short name	T661
Test name
Test status
Simulation time	4457732836 ps
CPU time	494.69 seconds
Started	Apr 23 04:29:29 PM PDT 24
Finished	Apr 23 04:37:44 PM PDT 24
Peak memory	635716 kb
Host	smart-f4ea2d00-bd9a-4e77-8cfd-819690c8c0c8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 258138258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.258138258
Directory	/workspace/8.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3316705975
Short name	T351
Test name
Test status
Simulation time	4148078170 ps
CPU time	548.38 seconds
Started	Apr 23 04:32:01 PM PDT 24
Finished	Apr 23 04:41:10 PM PDT 24
Peak memory	637312 kb
Host	smart-f77a0102-ea12-4f7a-9519-b37ad25c0755
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3316705975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3316705975
Directory	/workspace/82.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119868347
Short name	T739
Test name
Test status
Simulation time	4160900372 ps
CPU time	398.31 seconds
Started	Apr 23 04:31:43 PM PDT 24
Finished	Apr 23 04:38:21 PM PDT 24
Peak memory	633320 kb
Host	smart-30f8d9b4-7fb9-46b9-a148-4325a8fc67f7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119868347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2119868347
Directory	/workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/98.chip_sw_all_escalation_resets.4200403812
Short name	T740
Test name
Test status
Simulation time	5522031174 ps
CPU time	504.36 seconds
Started	Apr 23 04:32:47 PM PDT 24
Finished	Apr 23 04:41:12 PM PDT 24
Peak memory	635488 kb
Host	smart-60d84802-b533-423d-8487-a44ccd95b760
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4200403812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.4200403812
Directory	/workspace/98.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_tl_errors.4168817990
Short name	T632
Test name
Test status
Simulation time	4558652235 ps
CPU time	542.28 seconds
Started	Apr 23 04:26:09 PM PDT 24
Finished	Apr 23 04:35:12 PM PDT 24
Peak memory	585320 kb
Host	smart-e022b2e6-44fe-465a-b654-0f621933a8c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168817990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.4168817990
Directory	/workspace/0.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all.1403065191
Short name	T1855
Test name
Test status
Simulation time	2038854269 ps
CPU time	188.52 seconds
Started	Apr 23 04:42:33 PM PDT 24
Finished	Apr 23 04:45:42 PM PDT 24
Peak memory	562900 kb
Host	smart-e7a2fe49-0d2c-4b84-a2cd-648f62f6b098
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403065191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1403065191
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.757048340
Short name	T296
Test name
Test status
Simulation time	12909797200 ps
CPU time	1742.04 seconds
Started	Apr 23 03:52:22 PM PDT 24
Finished	Apr 23 04:21:24 PM PDT 24
Peak memory	601368 kb
Host	smart-e378c9ba-35ba-4b61-b9a1-29900a2e4df0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=757048340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.757048340
Directory	/workspace/0.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3125464508
Short name	T234
Test name
Test status
Simulation time	3052569912 ps
CPU time	214.81 seconds
Started	Apr 23 03:54:23 PM PDT 24
Finished	Apr 23 03:57:58 PM PDT 24
Peak memory	599860 kb
Host	smart-8161692c-1cd8-4990-8438-e0c340af5bfd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125464508 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.3125464508
Directory	/workspace/0.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/10.chip_sw_all_escalation_resets.406620571
Short name	T323
Test name
Test status
Simulation time	4936341922 ps
CPU time	541.23 seconds
Started	Apr 23 04:28:34 PM PDT 24
Finished	Apr 23 04:37:36 PM PDT 24
Peak memory	600812 kb
Host	smart-63c2b82a-9832-47e8-a69d-47a929973161
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 406620571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.406620571
Directory	/workspace/10.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4156302757
Short name	T341
Test name
Test status
Simulation time	36110690518 ps
CPU time	3415.28 seconds
Started	Apr 23 03:52:38 PM PDT 24
Finished	Apr 23 04:49:34 PM PDT 24
Peak memory	602604 kb
Host	smart-62734d2f-e8e6-4b64-b77c-5572a379f945
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156302757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.4156302757
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2209664971
Short name	T236
Test name
Test status
Simulation time	4004548054 ps
CPU time	468.89 seconds
Started	Apr 23 03:57:46 PM PDT 24
Finished	Apr 23 04:05:36 PM PDT 24
Peak memory	608468 kb
Host	smart-8586f5fc-2219-470f-9b9c-3706928813c4
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220966 4971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2209664971
Directory	/workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1215731891
Short name	T52
Test name
Test status
Simulation time	20234423480 ps
CPU time	1585.65 seconds
Started	Apr 23 03:55:46 PM PDT 24
Finished	Apr 23 04:22:12 PM PDT 24
Peak memory	601880 kb
Host	smart-12c7d1be-89c4-473f-be9d-e2bac21022dd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1215731891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1215731891
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3892632968
Short name	T99
Test name
Test status
Simulation time	5520194881 ps
CPU time	460.68 seconds
Started	Apr 23 03:53:19 PM PDT 24
Finished	Apr 23 04:01:00 PM PDT 24
Peak memory	609460 kb
Host	smart-6a463f0f-1748-42bd-9108-ced358c787eb
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892632968 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.3892632968
Directory	/workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_random.2230963226
Short name	T1754
Test name
Test status
Simulation time	2282143569 ps
CPU time	104.33 seconds
Started	Apr 23 04:33:51 PM PDT 24
Finished	Apr 23 04:35:35 PM PDT 24
Peak memory	562756 kb
Host	smart-1ef19520-d8ba-4ab7-876e-19808ac1d454
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230963226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2230963226
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1776622213
Short name	T270
Test name
Test status
Simulation time	4114427916 ps
CPU time	543.17 seconds
Started	Apr 23 03:52:39 PM PDT 24
Finished	Apr 23 04:01:42 PM PDT 24
Peak memory	599908 kb
Host	smart-5090b62b-eb1c-41f5-8c41-d46253b084b3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776622213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.1776622213
Directory	/workspace/0.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.310847810
Short name	T1117
Test name
Test status
Simulation time	18181719120 ps
CPU time	468.15 seconds
Started	Apr 23 03:51:45 PM PDT 24
Finished	Apr 23 03:59:34 PM PDT 24
Peak memory	607544 kb
Host	smart-61bee1de-6365-464b-b8fc-076d4494f68f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=310847810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.310847810
Directory	/workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2199662721
Short name	T122
Test name
Test status
Simulation time	5358720038 ps
CPU time	389.94 seconds
Started	Apr 23 03:54:49 PM PDT 24
Finished	Apr 23 04:01:20 PM PDT 24
Peak memory	607260 kb
Host	smart-e3334971-d71a-470e-9085-ca61b660621b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2199662721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2199662721
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1257687648
Short name	T356
Test name
Test status
Simulation time	6946343330 ps
CPU time	944.05 seconds
Started	Apr 23 03:53:30 PM PDT 24
Finished	Apr 23 04:09:17 PM PDT 24
Peak memory	601220 kb
Host	smart-cfd48de2-a5d8-4c3d-9e20-b2545a9bbfc1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1257687648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1257687648
Directory	/workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.981121596
Short name	T1091
Test name
Test status
Simulation time	6104070620 ps
CPU time	908.57 seconds
Started	Apr 23 03:51:35 PM PDT 24
Finished	Apr 23 04:06:45 PM PDT 24
Peak memory	600432 kb
Host	smart-56491903-1bb8-41be-96a3-51c25c15ad86
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=981121596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.981121596
Directory	/workspace/0.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all.3243093415
Short name	T442
Test name
Test status
Simulation time	9942028442 ps
CPU time	332.78 seconds
Started	Apr 23 04:37:06 PM PDT 24
Finished	Apr 23 04:42:40 PM PDT 24
Peak memory	563900 kb
Host	smart-6deb9aeb-674e-48db-aeb6-03dd93652bb5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243093415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3243093415
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.4178726594
Short name	T623
Test name
Test status
Simulation time	3942773044 ps
CPU time	368.06 seconds
Started	Apr 23 04:40:44 PM PDT 24
Finished	Apr 23 04:46:52 PM PDT 24
Peak memory	564016 kb
Host	smart-d3caa7eb-a4d3-485f-a0f2-39abf9f7a54c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178726594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.4178726594
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.324950341
Short name	T581
Test name
Test status
Simulation time	11474382861 ps
CPU time	397.83 seconds
Started	Apr 23 04:41:07 PM PDT 24
Finished	Apr 23 04:47:45 PM PDT 24
Peak memory	564028 kb
Host	smart-d662f1a3-eacb-44b3-a2e6-247a136cf55d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324950341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.324950341
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1004391827
Short name	T622
Test name
Test status
Simulation time	9417930806 ps
CPU time	379.51 seconds
Started	Apr 23 04:41:57 PM PDT 24
Finished	Apr 23 04:48:17 PM PDT 24
Peak memory	562880 kb
Host	smart-be7c1650-7b04-48ff-8dc8-0dec44e4bc84
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004391827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1004391827
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3510105686
Short name	T579
Test name
Test status
Simulation time	3755361371 ps
CPU time	305.16 seconds
Started	Apr 23 04:46:26 PM PDT 24
Finished	Apr 23 04:51:32 PM PDT 24
Peak memory	563972 kb
Host	smart-3450702c-dc6e-422e-bcd8-ac88a6b920d1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510105686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.3510105686
Directory	/workspace/71.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2825388256
Short name	T571
Test name
Test status
Simulation time	15959209349 ps
CPU time	730.89 seconds
Started	Apr 23 04:46:27 PM PDT 24
Finished	Apr 23 04:58:38 PM PDT 24
Peak memory	564028 kb
Host	smart-294b3dfc-70a8-4963-9ff7-b7260fc854f6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825388256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.2825388256
Directory	/workspace/71.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.2061664343
Short name	T567
Test name
Test status
Simulation time	12279605995 ps
CPU time	453.79 seconds
Started	Apr 23 04:46:39 PM PDT 24
Finished	Apr 23 04:54:13 PM PDT 24
Peak memory	564004 kb
Host	smart-97dd5863-eb6e-4ce7-a446-55fe4523d914
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061664343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2061664343
Directory	/workspace/72.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.662258549
Short name	T556
Test name
Test status
Simulation time	7873353042 ps
CPU time	281.45 seconds
Started	Apr 23 04:49:15 PM PDT 24
Finished	Apr 23 04:53:57 PM PDT 24
Peak memory	563912 kb
Host	smart-f141fa79-74b6-43ef-b73b-422d4af92d0e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662258549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.662258549
Directory	/workspace/88.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1753427776
Short name	T235
Test name
Test status
Simulation time	3788579720 ps
CPU time	511.76 seconds
Started	Apr 23 03:52:35 PM PDT 24
Finished	Apr 23 04:01:07 PM PDT 24
Peak memory	599860 kb
Host	smart-897c78ef-b2ea-49c8-a9bc-8c214c6c74c0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753427776 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1753427776
Directory	/workspace/0.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.548806150
Short name	T316
Test name
Test status
Simulation time	5694533862 ps
CPU time	853.11 seconds
Started	Apr 23 03:51:10 PM PDT 24
Finished	Apr 23 04:05:23 PM PDT 24
Peak memory	600280 kb
Host	smart-832420b3-dc8d-4f39-be71-83733356427a
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548806150 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.548806150
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1405813216
Short name	T640
Test name
Test status
Simulation time	4661816840 ps
CPU time	662.02 seconds
Started	Apr 23 03:52:34 PM PDT 24
Finished	Apr 23 04:03:37 PM PDT 24
Peak memory	600204 kb
Host	smart-4adef0ad-46ef-47ef-a39d-d3f1fd9227b5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14058 13216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1405813216
Directory	/workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_20.3729043734
Short name	T318
Test name
Test status
Simulation time	4909458960 ps
CPU time	643.73 seconds
Started	Apr 23 04:10:40 PM PDT 24
Finished	Apr 23 04:21:25 PM PDT 24
Peak memory	600200 kb
Host	smart-db607a82-86fe-40b3-99a3-cdf6e4e67c52
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729043734 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.3729043734
Directory	/workspace/1.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.167668277
Short name	T298
Test name
Test status
Simulation time	13464684200 ps
CPU time	1890.04 seconds
Started	Apr 23 04:05:37 PM PDT 24
Finished	Apr 23 04:37:07 PM PDT 24
Peak memory	600688 kb
Host	smart-27a8febf-7c23-43f4-8cc6-e8e1748b1a1b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=167668277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.167668277
Directory	/workspace/1.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/2.chip_sw_gpio.682214575
Short name	T26
Test name
Test status
Simulation time	4216498343 ps
CPU time	477.02 seconds
Started	Apr 23 04:16:11 PM PDT 24
Finished	Apr 23 04:24:08 PM PDT 24
Peak memory	600144 kb
Host	smart-ebe4551c-4e65-4018-b01c-08167a79eb52
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682214575 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.682214575
Directory	/workspace/2.chip_sw_gpio/latest

Test location	/workspace/coverage/default/0.chip_jtag_csr_rw.4104504628
Short name	T205
Test name
Test status
Simulation time	10604464711 ps
CPU time	984.39 seconds
Started	Apr 23 03:46:00 PM PDT 24
Finished	Apr 23 04:02:25 PM PDT 24
Peak memory	593400 kb
Host	smart-61010c70-9a85-44c4-841d-469454ff78bf
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104504628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.4104504628
Directory	/workspace/0.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/0.chip_sw_pattgen_ios.2728117955
Short name	T319
Test name
Test status
Simulation time	2587776216 ps
CPU time	233.47 seconds
Started	Apr 23 03:50:31 PM PDT 24
Finished	Apr 23 03:54:26 PM PDT 24
Peak memory	600316 kb
Host	smart-b10236a4-2b91-4368-b1fe-626bb19b3e30
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728117955 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.2728117955
Directory	/workspace/0.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3442712233
Short name	T363
Test name
Test status
Simulation time	2367262330 ps
CPU time	110.59 seconds
Started	Apr 23 03:53:35 PM PDT 24
Finished	Apr 23 03:55:28 PM PDT 24
Peak memory	631720 kb
Host	smart-8948c4b3-abb1-440a-958b-3cff540606cf
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442712233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.3442712233
Directory	/workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1721525604
Short name	T154
Test name
Test status
Simulation time	7301458410 ps
CPU time	1609.2 seconds
Started	Apr 23 03:51:13 PM PDT 24
Finished	Apr 23 04:18:04 PM PDT 24
Peak memory	600180 kb
Host	smart-46c744f9-3332-493e-9510-e82c3414230e
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17215 25604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1721525604
Directory	/workspace/0.chip_sw_usbdev_config_host/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.485798662
Short name	T141
Test name
Test status
Simulation time	4919616610 ps
CPU time	257.09 seconds
Started	Apr 23 04:27:22 PM PDT 24
Finished	Apr 23 04:31:39 PM PDT 24
Peak memory	653456 kb
Host	smart-22d7595e-0d67-432d-8e78-3c03806015a5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485798662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_re set.485798662
Directory	/workspace/0.chip_csr_hw_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1796165560
Short name	T186
Test name
Test status
Simulation time	3742653530 ps
CPU time	595.8 seconds
Started	Apr 23 03:52:55 PM PDT 24
Finished	Apr 23 04:02:51 PM PDT 24
Peak memory	600392 kb
Host	smart-3769aa4c-8d56-4133-a678-3150e83cbd05
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17961 65560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1796165560
Directory	/workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3780442541
Short name	T615
Test name
Test status
Simulation time	2739391220 ps
CPU time	488.16 seconds
Started	Apr 23 03:53:08 PM PDT 24
Finished	Apr 23 04:01:17 PM PDT 24
Peak memory	600200 kb
Host	smart-5e734297-b379-4108-a9fb-d4e9eb1151c4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780442541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.3780442541
Directory	/workspace/0.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1693135089
Short name	T209
Test name
Test status
Simulation time	17793016408 ps
CPU time	4358.46 seconds
Started	Apr 23 03:55:16 PM PDT 24
Finished	Apr 23 05:07:55 PM PDT 24
Peak memory	600676 kb
Host	smart-9c091a96-1506-4920-aba4-550717570c43
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16931 35089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.1693135089
Directory	/workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.175171024
Short name	T166
Test name
Test status
Simulation time	1745923166 ps
CPU time	99.03 seconds
Started	Apr 23 04:18:30 PM PDT 24
Finished	Apr 23 04:20:10 PM PDT 24
Peak memory	606828 kb
Host	smart-18543ae0-cef4-40ab-99e0-38e652e79c8e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175171024 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.175171024
Directory	/workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.147967084
Short name	T44
Test name
Test status
Simulation time	152751739624 ps
CPU time	30557 seconds
Started	Apr 23 04:05:22 PM PDT 24
Finished	Apr 24 12:34:42 AM PDT 24
Peak memory	601336 kb
Host	smart-bcfac919-cd02-434e-b531-0131f468ac11
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_si gverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147967084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e _sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.147967084
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2620942729
Short name	T364
Test name
Test status
Simulation time	2506050700 ps
CPU time	154.51 seconds
Started	Apr 23 04:29:01 PM PDT 24
Finished	Apr 23 04:31:36 PM PDT 24
Peak memory	606212 kb
Host	smart-9c0f8954-d420-4fb8-b72b-162b2fbb4128
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620942729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.2620942729
Directory	/workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.198076743
Short name	T2603
Test name
Test status
Simulation time	40104854105 ps
CPU time	5626.3 seconds
Started	Apr 23 04:25:53 PM PDT 24
Finished	Apr 23 05:59:40 PM PDT 24
Peak memory	585188 kb
Host	smart-6f04630d-0cd6-4795-85f4-e352e4b8e02b
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198076743 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.chip_csr_aliasing.198076743
Directory	/workspace/0.chip_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.427532414
Short name	T2135
Test name
Test status
Simulation time	44670800459 ps
CPU time	4205.06 seconds
Started	Apr 23 04:25:46 PM PDT 24
Finished	Apr 23 05:35:51 PM PDT 24
Peak memory	585016 kb
Host	smart-9cf47385-f9d0-47a8-a317-b6318ea43cfe
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427532414 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.427532414
Directory	/workspace/0.chip_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_rw.2734536016
Short name	T410
Test name
Test status
Simulation time	3427057586 ps
CPU time	302.83 seconds
Started	Apr 23 04:27:39 PM PDT 24
Finished	Apr 23 04:32:43 PM PDT 24
Peak memory	589300 kb
Host	smart-59a502d2-f307-41b3-a478-50a83c9e700c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734536016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.2734536016
Directory	/workspace/0.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2749091267
Short name	T1579
Test name
Test status
Simulation time	2492108995 ps
CPU time	76.65 seconds
Started	Apr 23 04:25:57 PM PDT 24
Finished	Apr 23 04:27:14 PM PDT 24
Peak memory	579880 kb
Host	smart-fa77af39-8f53-47b7-bd2f-76d1c9fc0752
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749091267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.2749091267
Directory	/workspace/0.chip_prim_tl_access/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.159135512
Short name	T2014
Test name
Test status
Simulation time	15204759714 ps
CPU time	559.51 seconds
Started	Apr 23 04:26:20 PM PDT 24
Finished	Apr 23 04:35:41 PM PDT 24
Peak memory	582476 kb
Host	smart-038147e6-b13e-41b0-b3e9-f5581bddf8be
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159135512 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.chip_rv_dm_lc_disabled.159135512
Directory	/workspace/0.chip_rv_dm_lc_disabled/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1271472194
Short name	T408
Test name
Test status
Simulation time	28221183220 ps
CPU time	3368.15 seconds
Started	Apr 23 04:26:04 PM PDT 24
Finished	Apr 23 05:22:13 PM PDT 24
Peak memory	585260 kb
Host	smart-5be48df0-c699-4338-87be-95d540962b0e
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271472194 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1271472194
Directory	/workspace/0.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3316259599
Short name	T1443
Test name
Test status
Simulation time	1435051214 ps
CPU time	69.25 seconds
Started	Apr 23 04:26:48 PM PDT 24
Finished	Apr 23 04:27:57 PM PDT 24
Peak memory	562760 kb
Host	smart-111ad612-2ac7-4dd1-b937-40faa4bd2649
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316259599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 3316259599
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3115310823
Short name	T2187
Test name
Test status
Simulation time	108510389663 ps
CPU time	1913.42 seconds
Started	Apr 23 04:26:35 PM PDT 24
Finished	Apr 23 04:58:29 PM PDT 24
Peak memory	562964 kb
Host	smart-428e5d80-e039-4435-81c1-c287efea5e84
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115310823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.3115310823
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3706171790
Short name	T1357
Test name
Test status
Simulation time	1452222818 ps
CPU time	57.03 seconds
Started	Apr 23 04:27:11 PM PDT 24
Finished	Apr 23 04:28:08 PM PDT 24
Peak memory	562676 kb
Host	smart-ece95adb-1c18-4bb4-be6b-59533ba97cad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706171790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .3706171790
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_error_random.382404633
Short name	T1817
Test name
Test status
Simulation time	363070444 ps
CPU time	34.12 seconds
Started	Apr 23 04:27:06 PM PDT 24
Finished	Apr 23 04:27:40 PM PDT 24
Peak memory	562724 kb
Host	smart-273b6a35-d797-4e4d-9faf-853352268633
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382404633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.382404633
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_random.1282974268
Short name	T1503
Test name
Test status
Simulation time	1329461088 ps
CPU time	51.08 seconds
Started	Apr 23 04:26:30 PM PDT 24
Finished	Apr 23 04:27:21 PM PDT 24
Peak memory	562748 kb
Host	smart-ad0199ff-431d-41fd-8952-05f801b3eb5e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282974268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.1282974268
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1821680943
Short name	T1977
Test name
Test status
Simulation time	70023191540 ps
CPU time	808.31 seconds
Started	Apr 23 04:26:51 PM PDT 24
Finished	Apr 23 04:40:20 PM PDT 24
Peak memory	562824 kb
Host	smart-89cb4158-92aa-4f95-b9e2-baea798f8b42
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821680943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1821680943
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.737208325
Short name	T1950
Test name
Test status
Simulation time	3561254068 ps
CPU time	72.35 seconds
Started	Apr 23 04:27:02 PM PDT 24
Finished	Apr 23 04:28:15 PM PDT 24
Peak memory	562792 kb
Host	smart-6dc4b3aa-7caf-4222-8a04-7443b24b9bb3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737208325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.737208325
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3734550272
Short name	T2209
Test name
Test status
Simulation time	332651312 ps
CPU time	33.55 seconds
Started	Apr 23 04:26:27 PM PDT 24
Finished	Apr 23 04:27:00 PM PDT 24
Peak memory	562664 kb
Host	smart-3a3bbdd4-17c4-4899-a98f-ea0474fd83e9
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734550272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.3734550272
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_same_source.2515914515
Short name	T603
Test name
Test status
Simulation time	894947004 ps
CPU time	34.67 seconds
Started	Apr 23 04:27:19 PM PDT 24
Finished	Apr 23 04:27:55 PM PDT 24
Peak memory	562708 kb
Host	smart-7bf7e6aa-1b0e-44c1-b8de-777ab35b0fe9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515914515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2515914515
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke.2895320944
Short name	T2170
Test name
Test status
Simulation time	48101732 ps
CPU time	6.74 seconds
Started	Apr 23 04:26:18 PM PDT 24
Finished	Apr 23 04:26:26 PM PDT 24
Peak memory	562728 kb
Host	smart-1d6194fe-7d24-4e27-bb90-e88ab2fdcaa2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895320944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2895320944
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2438712087
Short name	T1928
Test name
Test status
Simulation time	9856712129 ps
CPU time	114.7 seconds
Started	Apr 23 04:26:29 PM PDT 24
Finished	Apr 23 04:28:24 PM PDT 24
Peak memory	562776 kb
Host	smart-374cf9bb-a39c-46f8-aa1b-98e10235d74f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438712087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2438712087
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3849454605
Short name	T1726
Test name
Test status
Simulation time	5079023152 ps
CPU time	92.21 seconds
Started	Apr 23 04:26:52 PM PDT 24
Finished	Apr 23 04:28:25 PM PDT 24
Peak memory	562808 kb
Host	smart-c92a6956-8266-4222-923d-de5ccd57bda4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849454605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3849454605
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.4135082483
Short name	T2068
Test name
Test status
Simulation time	46307191 ps
CPU time	7.52 seconds
Started	Apr 23 04:26:47 PM PDT 24
Finished	Apr 23 04:26:55 PM PDT 24
Peak memory	562692 kb
Host	smart-64cd73ca-c7cd-4791-9b67-0197f18a7a55
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135082483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .4135082483
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.210051087
Short name	T643
Test name
Test status
Simulation time	5801114720 ps
CPU time	230.98 seconds
Started	Apr 23 04:27:05 PM PDT 24
Finished	Apr 23 04:30:56 PM PDT 24
Peak memory	562728 kb
Host	smart-6f52bcb9-064c-4b48-b2b1-bec0410b5521
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210051087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.210051087
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.590491685
Short name	T2652
Test name
Test status
Simulation time	34492909 ps
CPU time	17.1 seconds
Started	Apr 23 04:27:10 PM PDT 24
Finished	Apr 23 04:27:28 PM PDT 24
Peak memory	562840 kb
Host	smart-5564f9e6-68bf-42ca-a375-e7e6e18ec855
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590491685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_w ith_rand_reset.590491685
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3167378389
Short name	T1404
Test name
Test status
Simulation time	246162102 ps
CPU time	71.99 seconds
Started	Apr 23 04:27:04 PM PDT 24
Finished	Apr 23 04:28:16 PM PDT 24
Peak memory	563964 kb
Host	smart-882d050e-e204-48e0-831d-882180c15de4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167378389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.3167378389
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3726774480
Short name	T1472
Test name
Test status
Simulation time	724035551 ps
CPU time	33.73 seconds
Started	Apr 23 04:26:54 PM PDT 24
Finished	Apr 23 04:27:28 PM PDT 24
Peak memory	562708 kb
Host	smart-a60d12c4-b1c1-45ac-9e6d-739b8cae9168
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726774480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3726774480
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.372328237
Short name	T349
Test name
Test status
Simulation time	29778915024 ps
CPU time	4983.37 seconds
Started	Apr 23 04:27:33 PM PDT 24
Finished	Apr 23 05:50:37 PM PDT 24
Peak memory	585876 kb
Host	smart-698164ae-c6a1-4f6a-99ff-8a1a9783ffe3
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372328237 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.chip_csr_aliasing.372328237
Directory	/workspace/1.chip_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1889508459
Short name	T1338
Test name
Test status
Simulation time	14905717914 ps
CPU time	1898.25 seconds
Started	Apr 23 04:27:28 PM PDT 24
Finished	Apr 23 04:59:07 PM PDT 24
Peak memory	585080 kb
Host	smart-6db8c266-a383-4585-afaa-ba5eac7b2dab
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889508459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.1889508459
Directory	/workspace/1.chip_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_rw.3562846426
Short name	T2622
Test name
Test status
Simulation time	5901582628 ps
CPU time	646.45 seconds
Started	Apr 23 04:28:38 PM PDT 24
Finished	Apr 23 04:39:25 PM PDT 24
Peak memory	589140 kb
Host	smart-df472e73-4e98-476a-8190-2096a257e205
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562846426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.3562846426
Directory	/workspace/1.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.52897348
Short name	T2640
Test name
Test status
Simulation time	6961574707 ps
CPU time	291.36 seconds
Started	Apr 23 04:27:50 PM PDT 24
Finished	Apr 23 04:32:42 PM PDT 24
Peak memory	580472 kb
Host	smart-1434abfa-827d-460f-abf9-f8f572dfce32
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52897348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. chip_prim_tl_access.52897348
Directory	/workspace/1.chip_prim_tl_access/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.422747033
Short name	T2577
Test name
Test status
Simulation time	6552774836 ps
CPU time	219.01 seconds
Started	Apr 23 04:27:34 PM PDT 24
Finished	Apr 23 04:31:13 PM PDT 24
Peak memory	581716 kb
Host	smart-e9d47734-f274-4c09-9d0c-f1dbfe8a947e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422747033 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.chip_rv_dm_lc_disabled.422747033
Directory	/workspace/1.chip_rv_dm_lc_disabled/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1835618817
Short name	T346
Test name
Test status
Simulation time	14160629398 ps
CPU time	1746.79 seconds
Started	Apr 23 04:27:26 PM PDT 24
Finished	Apr 23 04:56:33 PM PDT 24
Peak memory	585052 kb
Host	smart-54c81d9e-4739-47de-9a3d-5963152c15c4
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835618817 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.1835618817
Directory	/workspace/1.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_tl_errors.1121650732
Short name	T1589
Test name
Test status
Simulation time	2472663282 ps
CPU time	77.83 seconds
Started	Apr 23 04:27:31 PM PDT 24
Finished	Apr 23 04:28:50 PM PDT 24
Peak memory	585780 kb
Host	smart-e6cfd89d-be28-4c51-b6d0-27d707e45c2c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121650732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.1121650732
Directory	/workspace/1.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1513877975
Short name	T1461
Test name
Test status
Simulation time	422563911 ps
CPU time	35.95 seconds
Started	Apr 23 04:28:08 PM PDT 24
Finished	Apr 23 04:28:45 PM PDT 24
Peak memory	562736 kb
Host	smart-8e4a5a7e-fbfe-4525-9f9e-8344b14618a2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513877975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 1513877975
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3096473777
Short name	T1888
Test name
Test status
Simulation time	130037497479 ps
CPU time	2318.01 seconds
Started	Apr 23 04:27:57 PM PDT 24
Finished	Apr 23 05:06:36 PM PDT 24
Peak memory	562868 kb
Host	smart-0d2ff494-371e-4ffd-8bba-caabb7e19ffb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096473777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.3096473777
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4156990901
Short name	T2238
Test name
Test status
Simulation time	42617172 ps
CPU time	9.33 seconds
Started	Apr 23 04:28:27 PM PDT 24
Finished	Apr 23 04:28:37 PM PDT 24
Peak memory	562732 kb
Host	smart-02ed4153-370c-4203-b1b4-5906674c10b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156990901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .4156990901
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_error_random.2908256370
Short name	T1947
Test name
Test status
Simulation time	296583356 ps
CPU time	32.27 seconds
Started	Apr 23 04:28:08 PM PDT 24
Finished	Apr 23 04:28:41 PM PDT 24
Peak memory	562672 kb
Host	smart-974ec365-b26a-41f7-a3e3-72bc01995c8c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908256370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2908256370
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_random.1318612951
Short name	T2384
Test name
Test status
Simulation time	1779949367 ps
CPU time	74.69 seconds
Started	Apr 23 04:27:59 PM PDT 24
Finished	Apr 23 04:29:14 PM PDT 24
Peak memory	562740 kb
Host	smart-dd74175e-26e1-41a1-8b8b-df3059bb6a0a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318612951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1318612951
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.13456924
Short name	T2778
Test name
Test status
Simulation time	69690748446 ps
CPU time	863.94 seconds
Started	Apr 23 04:28:04 PM PDT 24
Finished	Apr 23 04:42:29 PM PDT 24
Peak memory	562828 kb
Host	smart-44605377-f51c-4ed3-a8c0-f6d58dff8f52
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13456924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.13456924
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3737847294
Short name	T2591
Test name
Test status
Simulation time	28936745901 ps
CPU time	517.9 seconds
Started	Apr 23 04:27:55 PM PDT 24
Finished	Apr 23 04:36:34 PM PDT 24
Peak memory	562784 kb
Host	smart-da94d150-0242-48fd-ba1e-333c4ac94563
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737847294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3737847294
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1453568709
Short name	T427
Test name
Test status
Simulation time	421000904 ps
CPU time	38.24 seconds
Started	Apr 23 04:27:50 PM PDT 24
Finished	Apr 23 04:28:29 PM PDT 24
Peak memory	562752 kb
Host	smart-abd7bba0-a9fe-40a8-a80a-6743ce314b42
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453568709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.1453568709
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_same_source.4027916335
Short name	T1263
Test name
Test status
Simulation time	68605914 ps
CPU time	8.61 seconds
Started	Apr 23 04:28:08 PM PDT 24
Finished	Apr 23 04:28:17 PM PDT 24
Peak memory	562712 kb
Host	smart-a98693d9-7efc-43d7-b239-14a17076335d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027916335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4027916335
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke.3247842966
Short name	T2475
Test name
Test status
Simulation time	232688695 ps
CPU time	11.28 seconds
Started	Apr 23 04:27:35 PM PDT 24
Finished	Apr 23 04:27:46 PM PDT 24
Peak memory	562728 kb
Host	smart-a26a7b27-88ca-47f5-854d-c0aeb0f891af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247842966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3247842966
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1976593673
Short name	T2376
Test name
Test status
Simulation time	8254282491 ps
CPU time	86.89 seconds
Started	Apr 23 04:27:40 PM PDT 24
Finished	Apr 23 04:29:08 PM PDT 24
Peak memory	562724 kb
Host	smart-95f65fe6-35f4-434c-9c5f-baf343fdc27f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976593673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1976593673
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3775365273
Short name	T2272
Test name
Test status
Simulation time	4073548560 ps
CPU time	75.75 seconds
Started	Apr 23 04:27:44 PM PDT 24
Finished	Apr 23 04:29:00 PM PDT 24
Peak memory	562804 kb
Host	smart-f9930a70-dcb1-4bf1-adac-3ea63b2da689
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775365273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3775365273
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1253712239
Short name	T2430
Test name
Test status
Simulation time	42657886 ps
CPU time	6.59 seconds
Started	Apr 23 04:27:37 PM PDT 24
Finished	Apr 23 04:27:44 PM PDT 24
Peak memory	562648 kb
Host	smart-d5c406c3-1d63-4cba-a74a-42a36e64b706
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253712239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .1253712239
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1149253298
Short name	T1667
Test name
Test status
Simulation time	3215395510 ps
CPU time	223.59 seconds
Started	Apr 23 04:28:18 PM PDT 24
Finished	Apr 23 04:32:02 PM PDT 24
Peak memory	572164 kb
Host	smart-b1827087-c0f6-4a90-ac8e-b7d4da7a5ea8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149253298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1149253298
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2927994189
Short name	T1725
Test name
Test status
Simulation time	2862323913 ps
CPU time	307.36 seconds
Started	Apr 23 04:28:16 PM PDT 24
Finished	Apr 23 04:33:24 PM PDT 24
Peak memory	572160 kb
Host	smart-913fb0a6-75a4-4bbb-a1e9-8350fcfbf023
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927994189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.2927994189
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2579679409
Short name	T2541
Test name
Test status
Simulation time	744226722 ps
CPU time	214.56 seconds
Started	Apr 23 04:28:20 PM PDT 24
Finished	Apr 23 04:31:55 PM PDT 24
Peak memory	572140 kb
Host	smart-d57e7a76-d79b-4e52-8f66-0bb73d69c531
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579679409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.2579679409
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2753118123
Short name	T2261
Test name
Test status
Simulation time	1272787525 ps
CPU time	59.97 seconds
Started	Apr 23 04:28:02 PM PDT 24
Finished	Apr 23 04:29:03 PM PDT 24
Peak memory	562780 kb
Host	smart-85b40eff-2757-4b79-8298-e3656f93bcb5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753118123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2753118123
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/10.chip_csr_rw.592470922
Short name	T2072
Test name
Test status
Simulation time	4638698200 ps
CPU time	369.25 seconds
Started	Apr 23 04:34:06 PM PDT 24
Finished	Apr 23 04:40:16 PM PDT 24
Peak memory	587896 kb
Host	smart-0f79f69b-7c7c-43a6-8c4e-0ff86bc5116a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592470922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.592470922
Directory	/workspace/10.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2465651986
Short name	T1494
Test name
Test status
Simulation time	15082517932 ps
CPU time	1988.33 seconds
Started	Apr 23 04:33:49 PM PDT 24
Finished	Apr 23 05:06:58 PM PDT 24
Peak memory	585052 kb
Host	smart-cb70699d-e82d-45d2-be02-0761ba1d3c2f
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465651986 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.2465651986
Directory	/workspace/10.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.chip_tl_errors.3012310973
Short name	T2348
Test name
Test status
Simulation time	3505534798 ps
CPU time	190.08 seconds
Started	Apr 23 04:33:50 PM PDT 24
Finished	Apr 23 04:37:00 PM PDT 24
Peak memory	586256 kb
Host	smart-2f6f9099-f42b-4388-b378-9aaf1e12cb40
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012310973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3012310973
Directory	/workspace/10.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2025551116
Short name	T2123
Test name
Test status
Simulation time	811419034 ps
CPU time	68.77 seconds
Started	Apr 23 04:33:55 PM PDT 24
Finished	Apr 23 04:35:04 PM PDT 24
Peak memory	562768 kb
Host	smart-3d2f3221-8bdc-4ce1-93b1-61f1cb22e059
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025551116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .2025551116
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.411035289
Short name	T2157
Test name
Test status
Simulation time	36534509024 ps
CPU time	662.11 seconds
Started	Apr 23 04:33:53 PM PDT 24
Finished	Apr 23 04:44:56 PM PDT 24
Peak memory	562780 kb
Host	smart-a13258d6-ef9f-4653-8f67-d500157b4eef
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411035289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_d evice_slow_rsp.411035289
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.402828360
Short name	T1705
Test name
Test status
Simulation time	767026804 ps
CPU time	34.64 seconds
Started	Apr 23 04:34:01 PM PDT 24
Finished	Apr 23 04:34:35 PM PDT 24
Peak memory	562664 kb
Host	smart-fb0592d4-0dde-445b-baef-00503f8ca6b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402828360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr .402828360
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_error_random.581902216
Short name	T1328
Test name
Test status
Simulation time	2469938388 ps
CPU time	104.23 seconds
Started	Apr 23 04:33:57 PM PDT 24
Finished	Apr 23 04:35:41 PM PDT 24
Peak memory	562804 kb
Host	smart-00e3ca32-2169-4a7c-a7a9-2e7c30622fc5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581902216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.581902216
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.884749579
Short name	T1769
Test name
Test status
Simulation time	15698883325 ps
CPU time	180.7 seconds
Started	Apr 23 04:33:55 PM PDT 24
Finished	Apr 23 04:36:57 PM PDT 24
Peak memory	562772 kb
Host	smart-08925389-cbe7-4751-8eb6-fc1cbc438007
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884749579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.884749579
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2232436772
Short name	T535
Test name
Test status
Simulation time	45864450064 ps
CPU time	827.77 seconds
Started	Apr 23 04:33:54 PM PDT 24
Finished	Apr 23 04:47:42 PM PDT 24
Peak memory	562844 kb
Host	smart-b3f85de0-3637-4419-b6f7-ad2f2deb7f2f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232436772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2232436772
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2034111928
Short name	T2325
Test name
Test status
Simulation time	353805452 ps
CPU time	34.52 seconds
Started	Apr 23 04:33:51 PM PDT 24
Finished	Apr 23 04:34:26 PM PDT 24
Peak memory	562756 kb
Host	smart-e41835a4-014a-4e59-9405-47e8aa0b97d3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034111928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.2034111928
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_same_source.3181435508
Short name	T592
Test name
Test status
Simulation time	363741124 ps
CPU time	30.95 seconds
Started	Apr 23 04:33:54 PM PDT 24
Finished	Apr 23 04:34:25 PM PDT 24
Peak memory	562680 kb
Host	smart-bed28343-59f9-480b-b8d7-2322877b971c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181435508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3181435508
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke.3555389754
Short name	T2343
Test name
Test status
Simulation time	220801372 ps
CPU time	9.04 seconds
Started	Apr 23 04:33:48 PM PDT 24
Finished	Apr 23 04:33:57 PM PDT 24
Peak memory	562672 kb
Host	smart-f1d1f6ee-a1d5-495d-a2f4-98b1128554e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555389754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3555389754
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3810198994
Short name	T1757
Test name
Test status
Simulation time	10048171010 ps
CPU time	112.32 seconds
Started	Apr 23 04:33:58 PM PDT 24
Finished	Apr 23 04:35:50 PM PDT 24
Peak memory	562784 kb
Host	smart-d6150162-b24a-40a7-a0f3-85a566ca19fb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810198994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3810198994
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1786241868
Short name	T1250
Test name
Test status
Simulation time	2891478963 ps
CPU time	51.29 seconds
Started	Apr 23 04:33:48 PM PDT 24
Finished	Apr 23 04:34:39 PM PDT 24
Peak memory	562748 kb
Host	smart-0c891766-3dc4-4547-993c-bfb75775dacf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786241868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1786241868
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.57737954
Short name	T2552
Test name
Test status
Simulation time	51754587 ps
CPU time	6.6 seconds
Started	Apr 23 04:33:53 PM PDT 24
Finished	Apr 23 04:33:59 PM PDT 24
Peak memory	562692 kb
Host	smart-2886d725-4653-41c5-93f7-9802604ea37a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57737954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.57737954
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all.3633712074
Short name	T485
Test name
Test status
Simulation time	1750154709 ps
CPU time	84.83 seconds
Started	Apr 23 04:34:02 PM PDT 24
Finished	Apr 23 04:35:27 PM PDT 24
Peak memory	562844 kb
Host	smart-14b3918b-de61-4be0-8a0b-8074d2da9904
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633712074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3633712074
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3027871952
Short name	T2383
Test name
Test status
Simulation time	8510273281 ps
CPU time	291.33 seconds
Started	Apr 23 04:34:07 PM PDT 24
Finished	Apr 23 04:38:59 PM PDT 24
Peak memory	562952 kb
Host	smart-7f02e305-877c-4788-ba9c-9c9788168319
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027871952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3027871952
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2959716526
Short name	T1895
Test name
Test status
Simulation time	3793640473 ps
CPU time	522.86 seconds
Started	Apr 23 04:34:08 PM PDT 24
Finished	Apr 23 04:42:51 PM PDT 24
Peak memory	572208 kb
Host	smart-1ac26ec8-419e-4c63-9f6c-0bddc0182678
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959716526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.2959716526
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1833298580
Short name	T2007
Test name
Test status
Simulation time	7955255212 ps
CPU time	499.69 seconds
Started	Apr 23 04:34:08 PM PDT 24
Finished	Apr 23 04:42:28 PM PDT 24
Peak memory	572212 kb
Host	smart-57d1c441-bc50-44d6-be1c-76bfc64d3389
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833298580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.1833298580
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1694494861
Short name	T2764
Test name
Test status
Simulation time	718394995 ps
CPU time	37.15 seconds
Started	Apr 23 04:34:01 PM PDT 24
Finished	Apr 23 04:34:38 PM PDT 24
Peak memory	562764 kb
Host	smart-21893b1f-eafa-4f55-9379-0d87d16dd941
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694494861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1694494861
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/11.chip_csr_rw.2643171159
Short name	T378
Test name
Test status
Simulation time	5938949915 ps
CPU time	691.11 seconds
Started	Apr 23 04:34:31 PM PDT 24
Finished	Apr 23 04:46:03 PM PDT 24
Peak memory	589544 kb
Host	smart-9d136768-ec23-4aa1-9640-6806eee605b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643171159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.2643171159
Directory	/workspace/11.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3732717675
Short name	T1899
Test name
Test status
Simulation time	13958155689 ps
CPU time	1394.91 seconds
Started	Apr 23 04:34:06 PM PDT 24
Finished	Apr 23 04:57:21 PM PDT 24
Peak memory	585052 kb
Host	smart-46216432-fb92-40d3-9193-b547e6f9de0e
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732717675 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3732717675
Directory	/workspace/11.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.chip_tl_errors.168295439
Short name	T525
Test name
Test status
Simulation time	3410506997 ps
CPU time	221.52 seconds
Started	Apr 23 04:34:07 PM PDT 24
Finished	Apr 23 04:37:48 PM PDT 24
Peak memory	585148 kb
Host	smart-2bf92134-c957-4910-9785-a4fd44cd9d65
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168295439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.168295439
Directory	/workspace/11.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3823157319
Short name	T2322
Test name
Test status
Simulation time	1534150616 ps
CPU time	75.93 seconds
Started	Apr 23 04:34:20 PM PDT 24
Finished	Apr 23 04:35:36 PM PDT 24
Peak memory	562740 kb
Host	smart-cf6915b1-9577-4b1b-ba01-3da302c17b3e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823157319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .3823157319
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1299979791
Short name	T2130
Test name
Test status
Simulation time	17571601642 ps
CPU time	316.44 seconds
Started	Apr 23 04:34:19 PM PDT 24
Finished	Apr 23 04:39:35 PM PDT 24
Peak memory	562856 kb
Host	smart-753f4446-3d3e-4074-879e-ab5ac20f2701
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299979791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.1299979791
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4230793865
Short name	T2252
Test name
Test status
Simulation time	1119093539 ps
CPU time	43.98 seconds
Started	Apr 23 04:34:27 PM PDT 24
Finished	Apr 23 04:35:11 PM PDT 24
Peak memory	562692 kb
Host	smart-bdb6ba3d-43a8-4dcc-9045-4101eb1c8fdc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230793865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.4230793865
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_error_random.3669870760
Short name	T1850
Test name
Test status
Simulation time	1414957715 ps
CPU time	57.83 seconds
Started	Apr 23 04:34:19 PM PDT 24
Finished	Apr 23 04:35:17 PM PDT 24
Peak memory	562740 kb
Host	smart-e18d6e6c-1e10-489e-8c75-302e26a979a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669870760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3669870760
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_random.4013711726
Short name	T1931
Test name
Test status
Simulation time	2137777100 ps
CPU time	78.87 seconds
Started	Apr 23 04:34:08 PM PDT 24
Finished	Apr 23 04:35:28 PM PDT 24
Peak memory	562736 kb
Host	smart-0922ee73-6f87-426d-970c-7041d59d2c11
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013711726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.4013711726
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4017114032
Short name	T2302
Test name
Test status
Simulation time	31082892534 ps
CPU time	329.81 seconds
Started	Apr 23 04:34:15 PM PDT 24
Finished	Apr 23 04:39:46 PM PDT 24
Peak memory	562836 kb
Host	smart-720ceb12-8186-4e16-8535-6bb89faa0bad
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017114032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.4017114032
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2830222454
Short name	T1848
Test name
Test status
Simulation time	32588495835 ps
CPU time	599.08 seconds
Started	Apr 23 04:34:21 PM PDT 24
Finished	Apr 23 04:44:20 PM PDT 24
Peak memory	562820 kb
Host	smart-466e2a43-b956-4695-a5d5-92467769ee01
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830222454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2830222454
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1530705574
Short name	T544
Test name
Test status
Simulation time	178870323 ps
CPU time	19.5 seconds
Started	Apr 23 04:34:12 PM PDT 24
Finished	Apr 23 04:34:32 PM PDT 24
Peak memory	562696 kb
Host	smart-2ae72f1f-7db2-460c-8ef8-a2de512de43f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530705574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.1530705574
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_same_source.48623160
Short name	T1925
Test name
Test status
Simulation time	144836266 ps
CPU time	12.94 seconds
Started	Apr 23 04:34:21 PM PDT 24
Finished	Apr 23 04:34:34 PM PDT 24
Peak memory	562700 kb
Host	smart-be1a1b11-69bb-469c-ae60-674d14f3ebda
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48623160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.48623160
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke.3088840608
Short name	T1625
Test name
Test status
Simulation time	50923000 ps
CPU time	6.43 seconds
Started	Apr 23 04:34:08 PM PDT 24
Finished	Apr 23 04:34:15 PM PDT 24
Peak memory	562692 kb
Host	smart-5caa1632-5430-4bc9-812f-e7eac56167ab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088840608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3088840608
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.886140915
Short name	T1296
Test name
Test status
Simulation time	9104660841 ps
CPU time	110.55 seconds
Started	Apr 23 04:34:12 PM PDT 24
Finished	Apr 23 04:36:03 PM PDT 24
Peak memory	562788 kb
Host	smart-321c9609-778c-4e7c-a8ca-1b264a78d2d1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886140915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.886140915
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3604638626
Short name	T1738
Test name
Test status
Simulation time	4282269087 ps
CPU time	79.08 seconds
Started	Apr 23 04:34:11 PM PDT 24
Finished	Apr 23 04:35:30 PM PDT 24
Peak memory	562740 kb
Host	smart-7e437505-b8e6-4342-b842-5ad1f40778bb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604638626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3604638626
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2511865903
Short name	T2587
Test name
Test status
Simulation time	52290650 ps
CPU time	6.92 seconds
Started	Apr 23 04:34:10 PM PDT 24
Finished	Apr 23 04:34:17 PM PDT 24
Peak memory	562712 kb
Host	smart-4da77c48-032a-4a95-aade-00a88f0e1662
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511865903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.2511865903
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all.3657788796
Short name	T1939
Test name
Test status
Simulation time	735214744 ps
CPU time	70.23 seconds
Started	Apr 23 04:34:26 PM PDT 24
Finished	Apr 23 04:35:37 PM PDT 24
Peak memory	563356 kb
Host	smart-0134e8f2-4bc6-4ffc-9786-b959ad955eed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657788796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3657788796
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.447738092
Short name	T2540
Test name
Test status
Simulation time	2640063261 ps
CPU time	265.42 seconds
Started	Apr 23 04:34:32 PM PDT 24
Finished	Apr 23 04:38:57 PM PDT 24
Peak memory	563952 kb
Host	smart-849e8680-08ac-44a9-9346-34ca3e6c7a25
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447738092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.447738092
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1095198286
Short name	T1814
Test name
Test status
Simulation time	3779343920 ps
CPU time	441.62 seconds
Started	Apr 23 04:34:32 PM PDT 24
Finished	Apr 23 04:41:54 PM PDT 24
Peak memory	572224 kb
Host	smart-f1077c3f-26b6-4145-9e70-036b1fbcf056
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095198286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.1095198286
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.97737655
Short name	T1893
Test name
Test status
Simulation time	4187482857 ps
CPU time	485.24 seconds
Started	Apr 23 04:34:31 PM PDT 24
Finished	Apr 23 04:42:37 PM PDT 24
Peak memory	579980 kb
Host	smart-c5c1403d-4552-40fb-a3c6-88f33673142d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97737655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_ with_reset_error.97737655
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1735246514
Short name	T2081
Test name
Test status
Simulation time	1027264310 ps
CPU time	51.48 seconds
Started	Apr 23 04:34:25 PM PDT 24
Finished	Apr 23 04:35:16 PM PDT 24
Peak memory	562796 kb
Host	smart-6301b9ce-b71e-40f7-8c8b-9bc5019be85c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735246514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1735246514
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/12.chip_csr_rw.3752065720
Short name	T2748
Test name
Test status
Simulation time	3689810900 ps
CPU time	269.3 seconds
Started	Apr 23 04:35:02 PM PDT 24
Finished	Apr 23 04:39:32 PM PDT 24
Peak memory	589160 kb
Host	smart-2a9d3def-41c3-4a4e-b19e-8544dd3e9f83
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752065720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.3752065720
Directory	/workspace/12.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.135433826
Short name	T2459
Test name
Test status
Simulation time	29723146025 ps
CPU time	3627.1 seconds
Started	Apr 23 04:34:31 PM PDT 24
Finished	Apr 23 05:34:59 PM PDT 24
Peak memory	585204 kb
Host	smart-58a795c6-35cb-4740-811b-b9e47a467b4e
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135433826 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.chip_same_csr_outstanding.135433826
Directory	/workspace/12.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.chip_tl_errors.2768716118
Short name	T618
Test name
Test status
Simulation time	3141775352 ps
CPU time	95.06 seconds
Started	Apr 23 04:34:32 PM PDT 24
Finished	Apr 23 04:36:07 PM PDT 24
Peak memory	585184 kb
Host	smart-e34c8c3d-b3f3-437a-a936-82c73e5b249a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768716118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2768716118
Directory	/workspace/12.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2358588992
Short name	T437
Test name
Test status
Simulation time	419843333 ps
CPU time	39.13 seconds
Started	Apr 23 04:34:45 PM PDT 24
Finished	Apr 23 04:35:24 PM PDT 24
Peak memory	562668 kb
Host	smart-5d66bb6f-8f6d-4bb5-a95a-0d6147db6047
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358588992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .2358588992
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1594478518
Short name	T2429
Test name
Test status
Simulation time	17642439728 ps
CPU time	326.43 seconds
Started	Apr 23 04:34:48 PM PDT 24
Finished	Apr 23 04:40:15 PM PDT 24
Peak memory	562840 kb
Host	smart-23d71da7-5040-4375-92c5-ab158405b853
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594478518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.1594478518
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3722153350
Short name	T1829
Test name
Test status
Simulation time	1220458975 ps
CPU time	48.6 seconds
Started	Apr 23 04:34:54 PM PDT 24
Finished	Apr 23 04:35:43 PM PDT 24
Peak memory	562712 kb
Host	smart-b88a66ed-256d-4c29-9af9-73701be1deab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722153350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.3722153350
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_error_random.1206991721
Short name	T2369
Test name
Test status
Simulation time	1161197141 ps
CPU time	36.65 seconds
Started	Apr 23 04:34:53 PM PDT 24
Finished	Apr 23 04:35:30 PM PDT 24
Peak memory	562680 kb
Host	smart-3b53c8e8-c0e1-4d08-93c7-1696c9210e95
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206991721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1206991721
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_random.2500521086
Short name	T2775
Test name
Test status
Simulation time	2272003032 ps
CPU time	92.92 seconds
Started	Apr 23 04:34:37 PM PDT 24
Finished	Apr 23 04:36:10 PM PDT 24
Peak memory	562828 kb
Host	smart-702ae577-502e-41c6-9792-ec198d5d89a1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500521086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.2500521086
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3340079126
Short name	T1940
Test name
Test status
Simulation time	54559579956 ps
CPU time	608.52 seconds
Started	Apr 23 04:34:43 PM PDT 24
Finished	Apr 23 04:44:52 PM PDT 24
Peak memory	562792 kb
Host	smart-c3fb3d76-6224-4d0a-96f9-e04785b7e57c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340079126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3340079126
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3347525146
Short name	T1471
Test name
Test status
Simulation time	6858809494 ps
CPU time	125.11 seconds
Started	Apr 23 04:34:45 PM PDT 24
Finished	Apr 23 04:36:51 PM PDT 24
Peak memory	562780 kb
Host	smart-c22b2db7-4f6f-4b5b-beb2-1fb48a542b2a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347525146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3347525146
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.117145287
Short name	T475
Test name
Test status
Simulation time	410940252 ps
CPU time	37.41 seconds
Started	Apr 23 04:34:45 PM PDT 24
Finished	Apr 23 04:35:23 PM PDT 24
Peak memory	562700 kb
Host	smart-d35a0127-a35b-49ad-8b18-89e4cdc5b7dc
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117145287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_dela ys.117145287
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_same_source.1820856427
Short name	T1560
Test name
Test status
Simulation time	135176333 ps
CPU time	7.83 seconds
Started	Apr 23 04:34:51 PM PDT 24
Finished	Apr 23 04:34:59 PM PDT 24
Peak memory	562704 kb
Host	smart-e6fcc5e9-f169-4d89-b904-4f35650b2722
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820856427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1820856427
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke.4203765408
Short name	T2240
Test name
Test status
Simulation time	210800337 ps
CPU time	10.27 seconds
Started	Apr 23 04:34:32 PM PDT 24
Finished	Apr 23 04:34:43 PM PDT 24
Peak memory	562720 kb
Host	smart-bcfadc84-2493-4b94-8952-466d0b3401bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203765408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.4203765408
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3160100234
Short name	T2116
Test name
Test status
Simulation time	6245352315 ps
CPU time	67.59 seconds
Started	Apr 23 04:34:35 PM PDT 24
Finished	Apr 23 04:35:43 PM PDT 24
Peak memory	562796 kb
Host	smart-8010562a-56bb-41b6-8944-6ccf6566722d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160100234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3160100234
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1203087955
Short name	T471
Test name
Test status
Simulation time	4601874884 ps
CPU time	84.95 seconds
Started	Apr 23 04:34:40 PM PDT 24
Finished	Apr 23 04:36:06 PM PDT 24
Peak memory	562764 kb
Host	smart-f1af0a7e-472f-44de-a60c-0ce5ca807439
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203087955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1203087955
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3873079821
Short name	T2056
Test name
Test status
Simulation time	58257527 ps
CPU time	7.64 seconds
Started	Apr 23 04:34:34 PM PDT 24
Finished	Apr 23 04:34:43 PM PDT 24
Peak memory	562668 kb
Host	smart-37868476-d116-4a08-a9ae-5201156e4bf6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873079821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.3873079821
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all.2130004162
Short name	T2608
Test name
Test status
Simulation time	825588572 ps
CPU time	72.57 seconds
Started	Apr 23 04:34:55 PM PDT 24
Finished	Apr 23 04:36:08 PM PDT 24
Peak memory	562928 kb
Host	smart-282a5922-a898-4056-a5d7-32e68bd9d9b5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130004162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2130004162
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1078035488
Short name	T2069
Test name
Test status
Simulation time	11239412419 ps
CPU time	485.6 seconds
Started	Apr 23 04:34:55 PM PDT 24
Finished	Apr 23 04:43:00 PM PDT 24
Peak memory	564012 kb
Host	smart-0af51878-019b-4d73-9fbf-24cae8dd8bee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078035488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1078035488
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1781931203
Short name	T436
Test name
Test status
Simulation time	3905094204 ps
CPU time	275.14 seconds
Started	Apr 23 04:34:54 PM PDT 24
Finished	Apr 23 04:39:30 PM PDT 24
Peak memory	563964 kb
Host	smart-5888ddab-9f6d-473c-b88b-2a95072255c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781931203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.1781931203
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1510052933
Short name	T2354
Test name
Test status
Simulation time	56679088 ps
CPU time	10.37 seconds
Started	Apr 23 04:34:53 PM PDT 24
Finished	Apr 23 04:35:04 PM PDT 24
Peak memory	562732 kb
Host	smart-0b7e7d39-73fb-41dd-9311-d8074a34e05a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510052933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1510052933
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/13.chip_csr_rw.3488597732
Short name	T2754
Test name
Test status
Simulation time	3953435000 ps
CPU time	287.6 seconds
Started	Apr 23 04:35:29 PM PDT 24
Finished	Apr 23 04:40:17 PM PDT 24
Peak memory	589024 kb
Host	smart-155fda6d-eb7a-4778-9d20-dc1861ae75b9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488597732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.3488597732
Directory	/workspace/13.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.112780159
Short name	T2521
Test name
Test status
Simulation time	15972589280 ps
CPU time	2180.61 seconds
Started	Apr 23 04:35:03 PM PDT 24
Finished	Apr 23 05:11:24 PM PDT 24
Peak memory	585100 kb
Host	smart-774ac009-d35d-428c-ba93-acafe721c624
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112780159 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.chip_same_csr_outstanding.112780159
Directory	/workspace/13.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.chip_tl_errors.740320225
Short name	T2619
Test name
Test status
Simulation time	3092920609 ps
CPU time	219.16 seconds
Started	Apr 23 04:35:03 PM PDT 24
Finished	Apr 23 04:38:42 PM PDT 24
Peak memory	585268 kb
Host	smart-4bd530c7-60b1-4ea1-9e34-6105b88a46e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740320225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.740320225
Directory	/workspace/13.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_access_same_device.4039819405
Short name	T2590
Test name
Test status
Simulation time	485168680 ps
CPU time	22.77 seconds
Started	Apr 23 04:35:19 PM PDT 24
Finished	Apr 23 04:35:42 PM PDT 24
Peak memory	562752 kb
Host	smart-d366f74f-ee53-4a89-93ab-cc170a132f0e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039819405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .4039819405
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1082381628
Short name	T1636
Test name
Test status
Simulation time	10313526934 ps
CPU time	172.87 seconds
Started	Apr 23 04:35:21 PM PDT 24
Finished	Apr 23 04:38:14 PM PDT 24
Peak memory	562792 kb
Host	smart-dfc97e75-5702-4786-b05b-6ab2a57e3f97
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082381628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.1082381628
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2606218525
Short name	T1485
Test name
Test status
Simulation time	549497239 ps
CPU time	27.28 seconds
Started	Apr 23 04:35:25 PM PDT 24
Finished	Apr 23 04:35:52 PM PDT 24
Peak memory	562728 kb
Host	smart-207237d3-0213-4828-8524-60939af777d8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606218525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.2606218525
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_error_random.2424897451
Short name	T1335
Test name
Test status
Simulation time	362669873 ps
CPU time	16.07 seconds
Started	Apr 23 04:35:22 PM PDT 24
Finished	Apr 23 04:35:39 PM PDT 24
Peak memory	562700 kb
Host	smart-e23601a1-1ced-4e9d-9fb5-98df3edd1cb5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424897451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2424897451
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_random.2689368088
Short name	T1744
Test name
Test status
Simulation time	583630590 ps
CPU time	56.69 seconds
Started	Apr 23 04:35:13 PM PDT 24
Finished	Apr 23 04:36:10 PM PDT 24
Peak memory	562724 kb
Host	smart-11ad9323-a0c3-47eb-a2f9-c129b03de768
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689368088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.2689368088
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3140216817
Short name	T1333
Test name
Test status
Simulation time	13481154221 ps
CPU time	158.03 seconds
Started	Apr 23 04:35:19 PM PDT 24
Finished	Apr 23 04:37:58 PM PDT 24
Peak memory	562784 kb
Host	smart-5c781039-4d0c-4eb7-a499-99f1226e87aa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140216817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3140216817
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3255652170
Short name	T539
Test name
Test status
Simulation time	50491379350 ps
CPU time	910.09 seconds
Started	Apr 23 04:35:18 PM PDT 24
Finished	Apr 23 04:50:28 PM PDT 24
Peak memory	562816 kb
Host	smart-0961ed7c-fe34-43ba-9b71-8ab2748928e2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255652170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3255652170
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1701508367
Short name	T2482
Test name
Test status
Simulation time	587809100 ps
CPU time	57 seconds
Started	Apr 23 04:35:13 PM PDT 24
Finished	Apr 23 04:36:10 PM PDT 24
Peak memory	562684 kb
Host	smart-19c52e62-9cb2-4a3d-939b-605d81bba28a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701508367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.1701508367
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_same_source.583010167
Short name	T2001
Test name
Test status
Simulation time	131027478 ps
CPU time	14.17 seconds
Started	Apr 23 04:35:22 PM PDT 24
Finished	Apr 23 04:35:37 PM PDT 24
Peak memory	562648 kb
Host	smart-385d000a-f241-4b31-92dd-582fd644e4ab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583010167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.583010167
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke.3321744980
Short name	T1298
Test name
Test status
Simulation time	196931406 ps
CPU time	9.1 seconds
Started	Apr 23 04:35:02 PM PDT 24
Finished	Apr 23 04:35:11 PM PDT 24
Peak memory	562672 kb
Host	smart-70cd02bc-1452-417f-9be1-48a8ee89117a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321744980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3321744980
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.449143573
Short name	T2758
Test name
Test status
Simulation time	5976229152 ps
CPU time	62.03 seconds
Started	Apr 23 04:35:10 PM PDT 24
Finished	Apr 23 04:36:13 PM PDT 24
Peak memory	562764 kb
Host	smart-20e8915b-17ea-4f49-8c64-deecc4e799a5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449143573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.449143573
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1119068484
Short name	T2049
Test name
Test status
Simulation time	6755231724 ps
CPU time	127.09 seconds
Started	Apr 23 04:35:11 PM PDT 24
Finished	Apr 23 04:37:18 PM PDT 24
Peak memory	562804 kb
Host	smart-866a5ff7-fd95-400d-8851-268055617a4d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119068484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1119068484
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.648191815
Short name	T1281
Test name
Test status
Simulation time	39094534 ps
CPU time	6.57 seconds
Started	Apr 23 04:35:07 PM PDT 24
Finished	Apr 23 04:35:14 PM PDT 24
Peak memory	562676 kb
Host	smart-a06e3261-ea53-4bf1-87c4-e1ae3a37a528
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648191815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays .648191815
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all.344572952
Short name	T2230
Test name
Test status
Simulation time	667954133 ps
CPU time	75.39 seconds
Started	Apr 23 04:35:25 PM PDT 24
Finished	Apr 23 04:36:41 PM PDT 24
Peak memory	562928 kb
Host	smart-d7abad56-102b-4927-975b-591b681699d0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344572952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.344572952
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3376418656
Short name	T1990
Test name
Test status
Simulation time	15040057200 ps
CPU time	619.31 seconds
Started	Apr 23 04:35:30 PM PDT 24
Finished	Apr 23 04:45:50 PM PDT 24
Peak memory	563976 kb
Host	smart-284a2a82-4419-4b2b-880b-e217bc66121f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376418656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3376418656
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.454199340
Short name	T2657
Test name
Test status
Simulation time	43474221 ps
CPU time	14.45 seconds
Started	Apr 23 04:35:29 PM PDT 24
Finished	Apr 23 04:35:44 PM PDT 24
Peak memory	563408 kb
Host	smart-509fb9bf-ce4f-46a0-8e95-5e20282a28c0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454199340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_ with_rand_reset.454199340
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.484283329
Short name	T599
Test name
Test status
Simulation time	5107955194 ps
CPU time	463.27 seconds
Started	Apr 23 04:35:30 PM PDT 24
Finished	Apr 23 04:43:13 PM PDT 24
Peak memory	572156 kb
Host	smart-3badc4ce-6999-4aae-925b-2fa66f84bfcc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484283329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_reset_error.484283329
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2264895252
Short name	T1704
Test name
Test status
Simulation time	614426592 ps
CPU time	34.81 seconds
Started	Apr 23 04:35:25 PM PDT 24
Finished	Apr 23 04:36:00 PM PDT 24
Peak memory	562808 kb
Host	smart-0ca574b4-3815-4a13-b08a-8d59f18bb1a5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264895252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2264895252
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/14.chip_csr_rw.1152208667
Short name	T153
Test name
Test status
Simulation time	6297379465 ps
CPU time	631.36 seconds
Started	Apr 23 04:35:48 PM PDT 24
Finished	Apr 23 04:46:20 PM PDT 24
Peak memory	590124 kb
Host	smart-fa6704c3-848e-4018-8b3b-0bf779c7bb4f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152208667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.1152208667
Directory	/workspace/14.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3856120844
Short name	T366
Test name
Test status
Simulation time	15697988282 ps
CPU time	1799.93 seconds
Started	Apr 23 04:35:29 PM PDT 24
Finished	Apr 23 05:05:30 PM PDT 24
Peak memory	585004 kb
Host	smart-875bd3d2-dc0f-4bd2-b064-4f8b527920b2
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856120844 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.3856120844
Directory	/workspace/14.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.chip_tl_errors.1648364716
Short name	T559
Test name
Test status
Simulation time	3635617230 ps
CPU time	194.69 seconds
Started	Apr 23 04:35:31 PM PDT 24
Finished	Apr 23 04:38:46 PM PDT 24
Peak memory	585128 kb
Host	smart-0b0dcdcf-66de-4e69-a4d5-3070a36ad601
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648364716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.1648364716
Directory	/workspace/14.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1115695406
Short name	T2004
Test name
Test status
Simulation time	3108119021 ps
CPU time	150.7 seconds
Started	Apr 23 04:35:39 PM PDT 24
Finished	Apr 23 04:38:10 PM PDT 24
Peak memory	562804 kb
Host	smart-d94c6b91-b30b-4875-8214-6b3fb534c260
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115695406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .1115695406
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3673987911
Short name	T2154
Test name
Test status
Simulation time	47314466878 ps
CPU time	865.41 seconds
Started	Apr 23 04:35:38 PM PDT 24
Finished	Apr 23 04:50:03 PM PDT 24
Peak memory	562880 kb
Host	smart-62b8441c-0f71-408b-907e-b877dadf9643
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673987911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.3673987911
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.865112218
Short name	T2404
Test name
Test status
Simulation time	95303765 ps
CPU time	11.81 seconds
Started	Apr 23 04:35:46 PM PDT 24
Finished	Apr 23 04:35:58 PM PDT 24
Peak memory	562744 kb
Host	smart-43e1bac9-86e6-4cb9-95c0-6f9a2e91412a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865112218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr .865112218
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_error_random.2784268240
Short name	T2251
Test name
Test status
Simulation time	2069641134 ps
CPU time	77.35 seconds
Started	Apr 23 04:35:43 PM PDT 24
Finished	Apr 23 04:37:00 PM PDT 24
Peak memory	562716 kb
Host	smart-443a0d46-287a-4530-879a-05ca28860e5a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784268240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2784268240
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_random.3200461771
Short name	T538
Test name
Test status
Simulation time	410725991 ps
CPU time	37.12 seconds
Started	Apr 23 04:35:34 PM PDT 24
Finished	Apr 23 04:36:11 PM PDT 24
Peak memory	562764 kb
Host	smart-99437a92-6176-43dd-80d6-daa4c5c201f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200461771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.3200461771
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2238897505
Short name	T1750
Test name
Test status
Simulation time	84308624031 ps
CPU time	907.85 seconds
Started	Apr 23 04:35:33 PM PDT 24
Finished	Apr 23 04:50:41 PM PDT 24
Peak memory	562740 kb
Host	smart-76130276-f052-4b16-b8ac-18638614cb1c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238897505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2238897505
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1399848500
Short name	T1326
Test name
Test status
Simulation time	55523120161 ps
CPU time	985.63 seconds
Started	Apr 23 04:35:38 PM PDT 24
Finished	Apr 23 04:52:04 PM PDT 24
Peak memory	562804 kb
Host	smart-2f88031a-6145-4f66-acaf-16e907bdcb31
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399848500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1399848500
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3609442849
Short name	T597
Test name
Test status
Simulation time	194530966 ps
CPU time	21.04 seconds
Started	Apr 23 04:35:35 PM PDT 24
Finished	Apr 23 04:35:56 PM PDT 24
Peak memory	562744 kb
Host	smart-26d512ed-b931-4dd6-bdde-4a45997b6ae6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609442849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.3609442849
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_same_source.1183500525
Short name	T1270
Test name
Test status
Simulation time	173832104 ps
CPU time	8.53 seconds
Started	Apr 23 04:35:37 PM PDT 24
Finished	Apr 23 04:35:46 PM PDT 24
Peak memory	562684 kb
Host	smart-487cf746-38c1-43f8-9264-876cd34b4eeb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183500525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1183500525
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke.116325569
Short name	T1857
Test name
Test status
Simulation time	194050940 ps
CPU time	8.88 seconds
Started	Apr 23 04:35:31 PM PDT 24
Finished	Apr 23 04:35:41 PM PDT 24
Peak memory	562660 kb
Host	smart-c7fbbc97-ea4c-4930-bdbc-261b6615cf59
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116325569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.116325569
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2422152349
Short name	T1248
Test name
Test status
Simulation time	8943212948 ps
CPU time	92.96 seconds
Started	Apr 23 04:35:33 PM PDT 24
Finished	Apr 23 04:37:06 PM PDT 24
Peak memory	562800 kb
Host	smart-09464eb4-1ce6-437a-8c51-02fd2ca09c26
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422152349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2422152349
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2838764918
Short name	T1856
Test name
Test status
Simulation time	5149330192 ps
CPU time	94.32 seconds
Started	Apr 23 04:35:35 PM PDT 24
Finished	Apr 23 04:37:10 PM PDT 24
Peak memory	562796 kb
Host	smart-1865fe98-cc42-40e6-a1d4-c114b41d2153
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838764918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2838764918
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.555560394
Short name	T1537
Test name
Test status
Simulation time	44746098 ps
CPU time	6.64 seconds
Started	Apr 23 04:35:33 PM PDT 24
Finished	Apr 23 04:35:40 PM PDT 24
Peak memory	562680 kb
Host	smart-dc1672c6-93ee-4553-8330-489b9fd3e8de
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555560394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays .555560394
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all.2212304727
Short name	T2221
Test name
Test status
Simulation time	2096494344 ps
CPU time	240.08 seconds
Started	Apr 23 04:35:48 PM PDT 24
Finished	Apr 23 04:39:48 PM PDT 24
Peak memory	563936 kb
Host	smart-4617bcb3-a49c-4ab0-a653-6e7d5c830762
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212304727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2212304727
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2316609701
Short name	T788
Test name
Test status
Simulation time	2700586806 ps
CPU time	267.87 seconds
Started	Apr 23 04:35:52 PM PDT 24
Finished	Apr 23 04:40:20 PM PDT 24
Peak memory	562924 kb
Host	smart-82cfad4e-9ca8-4ca4-8e29-c737c8d25453
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316609701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2316609701
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3004424429
Short name	T1863
Test name
Test status
Simulation time	6824868584 ps
CPU time	322.15 seconds
Started	Apr 23 04:35:44 PM PDT 24
Finished	Apr 23 04:41:07 PM PDT 24
Peak memory	563960 kb
Host	smart-914e956a-449d-40c3-8643-30fac8bc3dad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004424429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.3004424429
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3486474787
Short name	T1651
Test name
Test status
Simulation time	6654252202 ps
CPU time	422.42 seconds
Started	Apr 23 04:35:51 PM PDT 24
Finished	Apr 23 04:42:54 PM PDT 24
Peak memory	573612 kb
Host	smart-8c704122-6f81-4e62-b9f9-b1747898bcc3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486474787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.3486474787
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3375921903
Short name	T1245
Test name
Test status
Simulation time	371636682 ps
CPU time	19.66 seconds
Started	Apr 23 04:35:46 PM PDT 24
Finished	Apr 23 04:36:06 PM PDT 24
Peak memory	562728 kb
Host	smart-e277b3c6-afc1-4bd5-b55a-43db1d90fa8d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375921903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3375921903
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/15.chip_csr_rw.916096000
Short name	T1341
Test name
Test status
Simulation time	4202915710 ps
CPU time	359.5 seconds
Started	Apr 23 04:36:09 PM PDT 24
Finished	Apr 23 04:42:08 PM PDT 24
Peak memory	589716 kb
Host	smart-edd34312-7c98-4d99-a24e-a9b6db53f129
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916096000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.916096000
Directory	/workspace/15.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1761167946
Short name	T2509
Test name
Test status
Simulation time	29262375904 ps
CPU time	2926.96 seconds
Started	Apr 23 04:35:49 PM PDT 24
Finished	Apr 23 05:24:37 PM PDT 24
Peak memory	585208 kb
Host	smart-d0c330dd-5dd4-4c5b-a2cf-3c886bf67985
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761167946 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.1761167946
Directory	/workspace/15.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.chip_tl_errors.1300674718
Short name	T520
Test name
Test status
Simulation time	3564349648 ps
CPU time	222.81 seconds
Started	Apr 23 04:35:49 PM PDT 24
Finished	Apr 23 04:39:32 PM PDT 24
Peak memory	585224 kb
Host	smart-bc648d9e-09e2-4e76-a254-c5cf64739faa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300674718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1300674718
Directory	/workspace/15.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_access_same_device.1613799474
Short name	T792
Test name
Test status
Simulation time	3493824539 ps
CPU time	141.56 seconds
Started	Apr 23 04:36:02 PM PDT 24
Finished	Apr 23 04:38:24 PM PDT 24
Peak memory	562872 kb
Host	smart-ffd1781e-9d76-4335-9b59-3dca357fd40b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613799474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .1613799474
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.249966240
Short name	T2246
Test name
Test status
Simulation time	128852757764 ps
CPU time	2421.57 seconds
Started	Apr 23 04:36:04 PM PDT 24
Finished	Apr 23 05:16:26 PM PDT 24
Peak memory	563040 kb
Host	smart-4d9018fc-3b2f-4ecd-9a95-0123a4e06460
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249966240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_d evice_slow_rsp.249966240
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3946482506
Short name	T2617
Test name
Test status
Simulation time	1206926170 ps
CPU time	53.63 seconds
Started	Apr 23 04:36:07 PM PDT 24
Finished	Apr 23 04:37:00 PM PDT 24
Peak memory	562756 kb
Host	smart-41c01bf2-280c-4693-8580-0a03d6f7cc47
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946482506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.3946482506
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_error_random.899334908
Short name	T1293
Test name
Test status
Simulation time	240599034 ps
CPU time	23.18 seconds
Started	Apr 23 04:36:07 PM PDT 24
Finished	Apr 23 04:36:30 PM PDT 24
Peak memory	562700 kb
Host	smart-7d948f9c-228b-455e-9fcd-33fa7dfca1be
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899334908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.899334908
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_random.2190819389
Short name	T1886
Test name
Test status
Simulation time	492879758 ps
CPU time	40.78 seconds
Started	Apr 23 04:36:00 PM PDT 24
Finished	Apr 23 04:36:41 PM PDT 24
Peak memory	562732 kb
Host	smart-933152fa-0ac6-4a3f-b057-23638b31b29f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190819389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.2190819389
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.3974292855
Short name	T2035
Test name
Test status
Simulation time	53016376585 ps
CPU time	604.01 seconds
Started	Apr 23 04:36:00 PM PDT 24
Finished	Apr 23 04:46:04 PM PDT 24
Peak memory	562824 kb
Host	smart-5e6be7f6-ca55-473c-bd8b-438c732c348f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974292855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3974292855
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1437749309
Short name	T1859
Test name
Test status
Simulation time	37586142648 ps
CPU time	658.45 seconds
Started	Apr 23 04:36:04 PM PDT 24
Finished	Apr 23 04:47:03 PM PDT 24
Peak memory	562808 kb
Host	smart-21f1fcec-6eed-48f7-9696-2730c621e44c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437749309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1437749309
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1531802944
Short name	T1596
Test name
Test status
Simulation time	551322475 ps
CPU time	52.68 seconds
Started	Apr 23 04:35:59 PM PDT 24
Finished	Apr 23 04:36:52 PM PDT 24
Peak memory	562724 kb
Host	smart-bd6f6162-2daa-4ed4-bf1b-25d90d03060b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531802944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.1531802944
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_same_source.2193552108
Short name	T1370
Test name
Test status
Simulation time	83444925 ps
CPU time	9.5 seconds
Started	Apr 23 04:36:09 PM PDT 24
Finished	Apr 23 04:36:19 PM PDT 24
Peak memory	562632 kb
Host	smart-7bea5894-801b-474b-ac4c-0f3c9a96c6ba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193552108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2193552108
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke.3988847046
Short name	T2793
Test name
Test status
Simulation time	175682636 ps
CPU time	9.66 seconds
Started	Apr 23 04:35:53 PM PDT 24
Finished	Apr 23 04:36:03 PM PDT 24
Peak memory	562712 kb
Host	smart-af7f446d-6606-496d-9d22-6ac7b5f6604d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988847046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3988847046
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.637881272
Short name	T2527
Test name
Test status
Simulation time	9942381298 ps
CPU time	107.31 seconds
Started	Apr 23 04:35:58 PM PDT 24
Finished	Apr 23 04:37:46 PM PDT 24
Peak memory	562740 kb
Host	smart-9db29fa1-4715-4428-acc0-a44bd1072635
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637881272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.637881272
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3530646851
Short name	T2133
Test name
Test status
Simulation time	5022358431 ps
CPU time	90.73 seconds
Started	Apr 23 04:35:58 PM PDT 24
Finished	Apr 23 04:37:29 PM PDT 24
Peak memory	562740 kb
Host	smart-3ce96dea-d14c-4f10-b559-8c9fe1dab0b8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530646851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3530646851
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3087732553
Short name	T1299
Test name
Test status
Simulation time	41138573 ps
CPU time	6.63 seconds
Started	Apr 23 04:35:53 PM PDT 24
Finished	Apr 23 04:36:00 PM PDT 24
Peak memory	562716 kb
Host	smart-bcc4fdf3-f241-43dd-94a7-3f83d97e1fd2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087732553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.3087732553
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all.776703703
Short name	T487
Test name
Test status
Simulation time	4761323974 ps
CPU time	210.84 seconds
Started	Apr 23 04:36:10 PM PDT 24
Finished	Apr 23 04:39:41 PM PDT 24
Peak memory	563348 kb
Host	smart-cc7963d8-5a83-47e6-9b05-dfbf2f5f6df0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776703703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.776703703
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.2049887365
Short name	T2562
Test name
Test status
Simulation time	2814595639 ps
CPU time	286.76 seconds
Started	Apr 23 04:36:10 PM PDT 24
Finished	Apr 23 04:40:57 PM PDT 24
Peak memory	563916 kb
Host	smart-e4e242d5-7932-448a-9f04-c27ff64ddb9a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049887365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2049887365
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3813573275
Short name	T2624
Test name
Test status
Simulation time	91009755 ps
CPU time	22.76 seconds
Started	Apr 23 04:36:12 PM PDT 24
Finished	Apr 23 04:36:35 PM PDT 24
Peak memory	563184 kb
Host	smart-4aa0b24d-089b-4370-a0bc-edd13abd812d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813573275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.3813573275
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.848880093
Short name	T1383
Test name
Test status
Simulation time	446389615 ps
CPU time	117.82 seconds
Started	Apr 23 04:36:12 PM PDT 24
Finished	Apr 23 04:38:11 PM PDT 24
Peak memory	563896 kb
Host	smart-380d146e-447b-441b-ab34-197d30388a94
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848880093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_reset_error.848880093
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3967065955
Short name	T1417
Test name
Test status
Simulation time	431272973 ps
CPU time	24.03 seconds
Started	Apr 23 04:36:08 PM PDT 24
Finished	Apr 23 04:36:32 PM PDT 24
Peak memory	562776 kb
Host	smart-1cd83350-7c8a-4096-b63e-437dce5e5a15
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967065955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3967065955
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/16.chip_csr_rw.1673996745
Short name	T2783
Test name
Test status
Simulation time	4608376632 ps
CPU time	351.78 seconds
Started	Apr 23 04:36:36 PM PDT 24
Finished	Apr 23 04:42:28 PM PDT 24
Peak memory	589204 kb
Host	smart-7bcc0454-d4d4-4ae0-852b-80aff5829800
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673996745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.1673996745
Directory	/workspace/16.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1246887993
Short name	T402
Test name
Test status
Simulation time	15015452368 ps
CPU time	1566.11 seconds
Started	Apr 23 04:36:12 PM PDT 24
Finished	Apr 23 05:02:19 PM PDT 24
Peak memory	585108 kb
Host	smart-ad91f50f-aa48-4f39-80ac-d760f4e0587e
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246887993 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.1246887993
Directory	/workspace/16.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.chip_tl_errors.1808083777
Short name	T523
Test name
Test status
Simulation time	3411254982 ps
CPU time	200.54 seconds
Started	Apr 23 04:36:12 PM PDT 24
Finished	Apr 23 04:39:33 PM PDT 24
Peak memory	585216 kb
Host	smart-5af9d02a-9aff-4fb1-9872-fa4e45e653ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808083777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.1808083777
Directory	/workspace/16.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_access_same_device.2591757648
Short name	T443
Test name
Test status
Simulation time	3042797712 ps
CPU time	153.71 seconds
Started	Apr 23 04:36:23 PM PDT 24
Finished	Apr 23 04:38:57 PM PDT 24
Peak memory	562896 kb
Host	smart-61ead57c-ad08-43b8-a863-6313da099e23
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591757648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .2591757648
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2414005969
Short name	T1991
Test name
Test status
Simulation time	64707898566 ps
CPU time	1084.83 seconds
Started	Apr 23 04:36:23 PM PDT 24
Finished	Apr 23 04:54:28 PM PDT 24
Peak memory	571040 kb
Host	smart-6228c1a0-5082-421f-8031-ffb6696d8b5f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414005969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.2414005969
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.264612583
Short name	T509
Test name
Test status
Simulation time	158180945 ps
CPU time	20.35 seconds
Started	Apr 23 04:36:31 PM PDT 24
Finished	Apr 23 04:36:52 PM PDT 24
Peak memory	562716 kb
Host	smart-065c7a19-f818-4da6-bc5e-5152261bcb66
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264612583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr .264612583
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_error_random.3427644792
Short name	T2555
Test name
Test status
Simulation time	292523935 ps
CPU time	24.74 seconds
Started	Apr 23 04:36:25 PM PDT 24
Finished	Apr 23 04:36:50 PM PDT 24
Peak memory	562644 kb
Host	smart-c533cbbf-52f8-46dd-a3ce-29f84bd2bc91
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427644792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3427644792
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_random.516451966
Short name	T1490
Test name
Test status
Simulation time	357356954 ps
CPU time	34.91 seconds
Started	Apr 23 04:36:18 PM PDT 24
Finished	Apr 23 04:36:54 PM PDT 24
Peak memory	562716 kb
Host	smart-b017c10c-13b7-4481-8463-e19102a23652
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516451966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.516451966
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.3617357472
Short name	T2359
Test name
Test status
Simulation time	45109012424 ps
CPU time	500.65 seconds
Started	Apr 23 04:36:20 PM PDT 24
Finished	Apr 23 04:44:41 PM PDT 24
Peak memory	562836 kb
Host	smart-43febc7f-c4de-4aad-8aab-250cc1ce1d42
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617357472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3617357472
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1793031422
Short name	T522
Test name
Test status
Simulation time	62678481472 ps
CPU time	1126.27 seconds
Started	Apr 23 04:36:21 PM PDT 24
Finished	Apr 23 04:55:08 PM PDT 24
Peak memory	562892 kb
Host	smart-2f98b21d-5e05-4cf1-8359-06d74a6936e4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793031422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1793031422
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1300484675
Short name	T415
Test name
Test status
Simulation time	506252997 ps
CPU time	43.76 seconds
Started	Apr 23 04:36:20 PM PDT 24
Finished	Apr 23 04:37:04 PM PDT 24
Peak memory	562704 kb
Host	smart-8fc176cb-607d-45b8-8c26-50ee76b2baf4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300484675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.1300484675
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_same_source.1349440070
Short name	T2067
Test name
Test status
Simulation time	459532103 ps
CPU time	40.39 seconds
Started	Apr 23 04:36:25 PM PDT 24
Finished	Apr 23 04:37:05 PM PDT 24
Peak memory	562764 kb
Host	smart-9b64f7a0-17cc-45ae-8a82-cff722913865
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349440070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1349440070
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke.874112872
Short name	T2062
Test name
Test status
Simulation time	155704766 ps
CPU time	8.24 seconds
Started	Apr 23 04:36:16 PM PDT 24
Finished	Apr 23 04:36:24 PM PDT 24
Peak memory	562616 kb
Host	smart-4cadf102-2e1d-4dc5-94e3-89bfdae0de73
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874112872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.874112872
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2831786198
Short name	T1550
Test name
Test status
Simulation time	7943044742 ps
CPU time	85.17 seconds
Started	Apr 23 04:36:19 PM PDT 24
Finished	Apr 23 04:37:45 PM PDT 24
Peak memory	562756 kb
Host	smart-ca74a26c-d875-41ff-959c-190f77a5bc34
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831786198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2831786198
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1834122554
Short name	T2021
Test name
Test status
Simulation time	5262066705 ps
CPU time	91.59 seconds
Started	Apr 23 04:36:18 PM PDT 24
Finished	Apr 23 04:37:50 PM PDT 24
Peak memory	562792 kb
Host	smart-f0d62a37-3fbe-43f9-9765-837b5e13bc39
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834122554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1834122554
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2267744152
Short name	T2498
Test name
Test status
Simulation time	42464548 ps
CPU time	6.95 seconds
Started	Apr 23 04:36:19 PM PDT 24
Finished	Apr 23 04:36:26 PM PDT 24
Peak memory	562684 kb
Host	smart-4f728cc4-9ac5-4abd-9114-dc0f8a240f5c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267744152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.2267744152
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all.552739585
Short name	T2312
Test name
Test status
Simulation time	4399187043 ps
CPU time	205.52 seconds
Started	Apr 23 04:36:30 PM PDT 24
Finished	Apr 23 04:39:56 PM PDT 24
Peak memory	564004 kb
Host	smart-317bce69-c597-4b09-99eb-21e9a6ad507e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552739585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.552739585
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.142949765
Short name	T1832
Test name
Test status
Simulation time	6100280312 ps
CPU time	258.7 seconds
Started	Apr 23 04:36:30 PM PDT 24
Finished	Apr 23 04:40:49 PM PDT 24
Peak memory	571140 kb
Host	smart-4920a315-4a91-479e-a8d6-d8852c9ca86b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142949765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.142949765
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.958057203
Short name	T1676
Test name
Test status
Simulation time	755225597 ps
CPU time	219.79 seconds
Started	Apr 23 04:36:30 PM PDT 24
Finished	Apr 23 04:40:10 PM PDT 24
Peak memory	572140 kb
Host	smart-f4c02a35-c425-4e24-b83b-61f01f52bb7f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958057203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_ with_rand_reset.958057203
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1623345779
Short name	T1388
Test name
Test status
Simulation time	6302949570 ps
CPU time	412.45 seconds
Started	Apr 23 04:36:33 PM PDT 24
Finished	Apr 23 04:43:27 PM PDT 24
Peak memory	572152 kb
Host	smart-32b5f2b0-c2bc-4ebd-ba02-fd513ddffe54
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623345779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1623345779
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1280790267
Short name	T2762
Test name
Test status
Simulation time	190790530 ps
CPU time	25.47 seconds
Started	Apr 23 04:36:26 PM PDT 24
Finished	Apr 23 04:36:52 PM PDT 24
Peak memory	562796 kb
Host	smart-7544ae9e-ba4e-48d6-84b2-485d4f784ddc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280790267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1280790267
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/17.chip_csr_rw.2242711045
Short name	T1349
Test name
Test status
Simulation time	4776494214 ps
CPU time	554.64 seconds
Started	Apr 23 04:36:52 PM PDT 24
Finished	Apr 23 04:46:07 PM PDT 24
Peak memory	588852 kb
Host	smart-e373a733-9d24-405d-92ad-5267f79e6d1d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242711045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2242711045
Directory	/workspace/17.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.156893722
Short name	T1565
Test name
Test status
Simulation time	15081131844 ps
CPU time	1798.01 seconds
Started	Apr 23 04:36:34 PM PDT 24
Finished	Apr 23 05:06:32 PM PDT 24
Peak memory	585140 kb
Host	smart-68ca3199-e8aa-4e05-b764-cff5e19f1945
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156893722 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.chip_same_csr_outstanding.156893722
Directory	/workspace/17.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.chip_tl_errors.1278572299
Short name	T2706
Test name
Test status
Simulation time	4029998248 ps
CPU time	250.73 seconds
Started	Apr 23 04:36:35 PM PDT 24
Finished	Apr 23 04:40:46 PM PDT 24
Peak memory	593640 kb
Host	smart-491b4cb3-c912-46b9-bc16-695e067f1492
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278572299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1278572299
Directory	/workspace/17.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1940945952
Short name	T2628
Test name
Test status
Simulation time	99350629890 ps
CPU time	1708.02 seconds
Started	Apr 23 04:36:42 PM PDT 24
Finished	Apr 23 05:05:11 PM PDT 24
Peak memory	562952 kb
Host	smart-77a3727d-4900-4c6a-90a0-a95efa738907
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940945952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.1940945952
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2688688613
Short name	T2451
Test name
Test status
Simulation time	238111524 ps
CPU time	14.26 seconds
Started	Apr 23 04:36:46 PM PDT 24
Finished	Apr 23 04:37:01 PM PDT 24
Peak memory	562684 kb
Host	smart-e9d6b165-d96a-4a76-b890-5beb80b5b582
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688688613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.2688688613
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_error_random.666685934
Short name	T2424
Test name
Test status
Simulation time	2333368935 ps
CPU time	90.62 seconds
Started	Apr 23 04:36:42 PM PDT 24
Finished	Apr 23 04:38:13 PM PDT 24
Peak memory	562788 kb
Host	smart-74683e03-09d4-40c5-9bb0-6c6ce33f97dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666685934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.666685934
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_random.3623399587
Short name	T1688
Test name
Test status
Simulation time	128196431 ps
CPU time	15.21 seconds
Started	Apr 23 04:36:37 PM PDT 24
Finished	Apr 23 04:36:52 PM PDT 24
Peak memory	562704 kb
Host	smart-bed4b85a-bf81-49ea-a246-b1dea2588aef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623399587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.3623399587
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3643699572
Short name	T1668
Test name
Test status
Simulation time	57556006973 ps
CPU time	642.79 seconds
Started	Apr 23 04:36:38 PM PDT 24
Finished	Apr 23 04:47:21 PM PDT 24
Peak memory	562788 kb
Host	smart-16d23f1a-cf7a-459d-ae35-567faa9bee1a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643699572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3643699572
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1879039300
Short name	T2629
Test name
Test status
Simulation time	70811084064 ps
CPU time	1281.46 seconds
Started	Apr 23 04:36:39 PM PDT 24
Finished	Apr 23 04:58:02 PM PDT 24
Peak memory	562896 kb
Host	smart-245041a1-080a-40ee-b153-7d8526e27b83
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879039300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1879039300
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2797197371
Short name	T2289
Test name
Test status
Simulation time	143506370 ps
CPU time	15.61 seconds
Started	Apr 23 04:36:40 PM PDT 24
Finished	Apr 23 04:36:55 PM PDT 24
Peak memory	562712 kb
Host	smart-79ca8912-5d4c-4270-8176-b434e027f990
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797197371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.2797197371
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_same_source.2789629599
Short name	T2016
Test name
Test status
Simulation time	903431105 ps
CPU time	29.26 seconds
Started	Apr 23 04:36:39 PM PDT 24
Finished	Apr 23 04:37:08 PM PDT 24
Peak memory	562748 kb
Host	smart-09f60698-8792-4ac0-a2cd-f58c525199ac
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789629599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2789629599
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke.1123694258
Short name	T2060
Test name
Test status
Simulation time	55800804 ps
CPU time	7.26 seconds
Started	Apr 23 04:36:36 PM PDT 24
Finished	Apr 23 04:36:44 PM PDT 24
Peak memory	562724 kb
Host	smart-e58ca51f-8cb6-480e-a9ca-1da5271756b8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123694258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1123694258
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1890041936
Short name	T1934
Test name
Test status
Simulation time	6523600112 ps
CPU time	73.22 seconds
Started	Apr 23 04:36:37 PM PDT 24
Finished	Apr 23 04:37:50 PM PDT 24
Peak memory	562780 kb
Host	smart-b523d18a-fb6a-4c70-8f7c-ae17c30eef7f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890041936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1890041936
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1975270061
Short name	T1416
Test name
Test status
Simulation time	6039691102 ps
CPU time	110.5 seconds
Started	Apr 23 04:36:36 PM PDT 24
Finished	Apr 23 04:38:27 PM PDT 24
Peak memory	562720 kb
Host	smart-71d2ade2-dc7f-4b05-9cdf-0c80515ef5a4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975270061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1975270061
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3855394405
Short name	T1643
Test name
Test status
Simulation time	36830798 ps
CPU time	6.01 seconds
Started	Apr 23 04:36:37 PM PDT 24
Finished	Apr 23 04:36:43 PM PDT 24
Peak memory	562696 kb
Host	smart-be20e4df-b022-4a79-b03a-34d9dc1d793c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855394405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.3855394405
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all.184015600
Short name	T2263
Test name
Test status
Simulation time	2947570855 ps
CPU time	290.92 seconds
Started	Apr 23 04:36:45 PM PDT 24
Finished	Apr 23 04:41:36 PM PDT 24
Peak memory	564020 kb
Host	smart-7af13e0f-1c9e-47a8-861a-41faa7f34e5b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184015600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.184015600
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2388345367
Short name	T1576
Test name
Test status
Simulation time	1128083047 ps
CPU time	113.33 seconds
Started	Apr 23 04:36:47 PM PDT 24
Finished	Apr 23 04:38:41 PM PDT 24
Peak memory	562868 kb
Host	smart-018003fc-9072-4d2a-9889-584cdbad863b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388345367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2388345367
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.2183075503
Short name	T1945
Test name
Test status
Simulation time	333178285 ps
CPU time	19.44 seconds
Started	Apr 23 04:36:47 PM PDT 24
Finished	Apr 23 04:37:06 PM PDT 24
Peak memory	562732 kb
Host	smart-db1134b9-deec-49c4-a903-39bdf3a772b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183075503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2183075503
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/18.chip_csr_rw.2826124101
Short name	T376
Test name
Test status
Simulation time	6354234000 ps
CPU time	596.5 seconds
Started	Apr 23 04:37:04 PM PDT 24
Finished	Apr 23 04:47:01 PM PDT 24
Peak memory	591124 kb
Host	smart-b353c8cd-dbc9-444d-934f-f5a05604af2c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826124101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.2826124101
Directory	/workspace/18.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.255505204
Short name	T1689
Test name
Test status
Simulation time	15277817478 ps
CPU time	1412.59 seconds
Started	Apr 23 04:36:51 PM PDT 24
Finished	Apr 23 05:00:24 PM PDT 24
Peak memory	585080 kb
Host	smart-edc55449-e5c5-40de-863a-3045d1122f5a
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255505204 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.chip_same_csr_outstanding.255505204
Directory	/workspace/18.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_access_same_device.335282275
Short name	T1838
Test name
Test status
Simulation time	2122394953 ps
CPU time	98.75 seconds
Started	Apr 23 04:37:06 PM PDT 24
Finished	Apr 23 04:38:45 PM PDT 24
Peak memory	562688 kb
Host	smart-d1fd1d3c-d9a1-4bad-96b2-08701409124c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335282275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device. 335282275
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3505808980
Short name	T2290
Test name
Test status
Simulation time	120865727965 ps
CPU time	2208.39 seconds
Started	Apr 23 04:37:00 PM PDT 24
Finished	Apr 23 05:13:49 PM PDT 24
Peak memory	562928 kb
Host	smart-e6f0bd7e-d65c-492a-8811-243cac0075a6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505808980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.3505808980
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.228479490
Short name	T2113
Test name
Test status
Simulation time	173152380 ps
CPU time	21.47 seconds
Started	Apr 23 04:37:02 PM PDT 24
Finished	Apr 23 04:37:24 PM PDT 24
Peak memory	562756 kb
Host	smart-4dfaabe3-c0af-4318-8d4d-1efd17e5a8fc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228479490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr .228479490
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_error_random.92712215
Short name	T1267
Test name
Test status
Simulation time	1202502235 ps
CPU time	45.57 seconds
Started	Apr 23 04:37:00 PM PDT 24
Finished	Apr 23 04:37:46 PM PDT 24
Peak memory	562732 kb
Host	smart-7b23cf7c-7052-488c-bf18-d07877e6b6ba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92712215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.92712215
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_random.4214441928
Short name	T2358
Test name
Test status
Simulation time	61449964 ps
CPU time	9.25 seconds
Started	Apr 23 04:36:54 PM PDT 24
Finished	Apr 23 04:37:04 PM PDT 24
Peak memory	562744 kb
Host	smart-c4e82e46-2b38-4122-84f4-74c65acc2fac
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214441928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.4214441928
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2752978005
Short name	T1819
Test name
Test status
Simulation time	64148428017 ps
CPU time	710.3 seconds
Started	Apr 23 04:37:00 PM PDT 24
Finished	Apr 23 04:48:51 PM PDT 24
Peak memory	562828 kb
Host	smart-414cd26c-1f66-40a6-a9a1-87c9ceec50b6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752978005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2752978005
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.2990627574
Short name	T2282
Test name
Test status
Simulation time	15008029526 ps
CPU time	265.04 seconds
Started	Apr 23 04:37:03 PM PDT 24
Finished	Apr 23 04:41:28 PM PDT 24
Peak memory	562848 kb
Host	smart-37c923bc-7c63-4ebd-ab40-1d600832a57c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990627574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2990627574
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3288420896
Short name	T1325
Test name
Test status
Simulation time	86667211 ps
CPU time	11.07 seconds
Started	Apr 23 04:37:04 PM PDT 24
Finished	Apr 23 04:37:15 PM PDT 24
Peak memory	562672 kb
Host	smart-18064cc7-2993-4930-aaaf-1b3613a0c32d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288420896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3288420896
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_same_source.1796585342
Short name	T1933
Test name
Test status
Simulation time	1495691269 ps
CPU time	48.15 seconds
Started	Apr 23 04:37:06 PM PDT 24
Finished	Apr 23 04:37:55 PM PDT 24
Peak memory	562676 kb
Host	smart-fc3fc767-4031-4ef1-a37e-068100b8a761
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796585342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1796585342
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke.1234978340
Short name	T1501
Test name
Test status
Simulation time	256025021 ps
CPU time	10.78 seconds
Started	Apr 23 04:36:54 PM PDT 24
Finished	Apr 23 04:37:06 PM PDT 24
Peak memory	562632 kb
Host	smart-7d308cda-d241-464d-b605-7fa7b3f85501
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234978340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1234978340
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2243697120
Short name	T2676
Test name
Test status
Simulation time	8154415522 ps
CPU time	88.24 seconds
Started	Apr 23 04:36:53 PM PDT 24
Finished	Apr 23 04:38:22 PM PDT 24
Peak memory	562716 kb
Host	smart-402775f2-6fa7-4bd0-a012-b307a3b88c28
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243697120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2243697120
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.909550194
Short name	T2351
Test name
Test status
Simulation time	5239483344 ps
CPU time	95.89 seconds
Started	Apr 23 04:36:57 PM PDT 24
Finished	Apr 23 04:38:33 PM PDT 24
Peak memory	562748 kb
Host	smart-5cc7700d-8b62-4f1f-9f11-508dd8aa2b45
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909550194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.909550194
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1993230830
Short name	T2392
Test name
Test status
Simulation time	46776916 ps
CPU time	6.13 seconds
Started	Apr 23 04:36:53 PM PDT 24
Finished	Apr 23 04:36:59 PM PDT 24
Peak memory	562640 kb
Host	smart-b96f5748-fed6-4140-954d-5eb7db9cee1c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993230830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.1993230830
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3938247243
Short name	T1957
Test name
Test status
Simulation time	9971133698 ps
CPU time	360.95 seconds
Started	Apr 23 04:37:03 PM PDT 24
Finished	Apr 23 04:43:05 PM PDT 24
Peak memory	562952 kb
Host	smart-81d6a1f3-062d-487f-b934-3ff560eea39f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938247243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3938247243
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.410234028
Short name	T2785
Test name
Test status
Simulation time	8260346215 ps
CPU time	351.45 seconds
Started	Apr 23 04:37:05 PM PDT 24
Finished	Apr 23 04:42:57 PM PDT 24
Peak memory	564036 kb
Host	smart-1550f772-5571-41c1-a17c-7f09d00aa4a3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410234028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_ with_rand_reset.410234028
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2069437147
Short name	T2173
Test name
Test status
Simulation time	3257379864 ps
CPU time	198.81 seconds
Started	Apr 23 04:37:05 PM PDT 24
Finished	Apr 23 04:40:24 PM PDT 24
Peak memory	572212 kb
Host	smart-426645c0-73b1-4b1d-b6dd-6fe304506a8d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069437147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.2069437147
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.999805749
Short name	T2677
Test name
Test status
Simulation time	1268191803 ps
CPU time	57.53 seconds
Started	Apr 23 04:37:06 PM PDT 24
Finished	Apr 23 04:38:05 PM PDT 24
Peak memory	562728 kb
Host	smart-f613e045-d770-46b8-a2b3-7912b58f68ec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999805749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.999805749
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/19.chip_csr_rw.3448137438
Short name	T1365
Test name
Test status
Simulation time	6164964840 ps
CPU time	515.99 seconds
Started	Apr 23 04:37:27 PM PDT 24
Finished	Apr 23 04:46:04 PM PDT 24
Peak memory	589212 kb
Host	smart-1453e7d9-ef19-4c8c-a356-664a47fe0d94
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448137438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.3448137438
Directory	/workspace/19.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.1784646967
Short name	T409
Test name
Test status
Simulation time	27626176765 ps
CPU time	3190.84 seconds
Started	Apr 23 04:37:06 PM PDT 24
Finished	Apr 23 05:30:18 PM PDT 24
Peak memory	585196 kb
Host	smart-d6f749b9-a0b1-4c7c-a241-bed18ec4eae0
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784646967 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.1784646967
Directory	/workspace/19.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_access_same_device.1704181652
Short name	T1410
Test name
Test status
Simulation time	2779845492 ps
CPU time	130.77 seconds
Started	Apr 23 04:37:17 PM PDT 24
Finished	Apr 23 04:39:28 PM PDT 24
Peak memory	562776 kb
Host	smart-eabab9e1-99fb-4a59-8c00-28c6acef645d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704181652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .1704181652
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1419251485
Short name	T1996
Test name
Test status
Simulation time	2610780602 ps
CPU time	49.58 seconds
Started	Apr 23 04:37:20 PM PDT 24
Finished	Apr 23 04:38:10 PM PDT 24
Peak memory	562752 kb
Host	smart-fa831d4d-1898-4682-9de3-df38313f474e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419251485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.1419251485
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.3676001686
Short name	T1301
Test name
Test status
Simulation time	127799141 ps
CPU time	17.11 seconds
Started	Apr 23 04:37:23 PM PDT 24
Finished	Apr 23 04:37:40 PM PDT 24
Peak memory	562672 kb
Host	smart-7d41e1ba-3934-4958-99a4-a84f7d04d73f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676001686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.3676001686
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_error_random.2238452887
Short name	T2159
Test name
Test status
Simulation time	115783329 ps
CPU time	12.96 seconds
Started	Apr 23 04:37:26 PM PDT 24
Finished	Apr 23 04:37:39 PM PDT 24
Peak memory	562724 kb
Host	smart-1ab4aeac-3749-4749-ab2a-4dad01a933ee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238452887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2238452887
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_random.848475557
Short name	T2202
Test name
Test status
Simulation time	2454813851 ps
CPU time	104.98 seconds
Started	Apr 23 04:37:11 PM PDT 24
Finished	Apr 23 04:38:56 PM PDT 24
Peak memory	562856 kb
Host	smart-ff0aa2ff-a9de-4f9a-8060-ddfeb3b4e9d3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848475557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.848475557
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_random_large_delays.1224517798
Short name	T2087
Test name
Test status
Simulation time	31442071478 ps
CPU time	351.21 seconds
Started	Apr 23 04:37:13 PM PDT 24
Finished	Apr 23 04:43:05 PM PDT 24
Peak memory	562876 kb
Host	smart-88c12743-ab15-447d-b182-db5199ab6401
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224517798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1224517798
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2401740012
Short name	T488
Test name
Test status
Simulation time	32094755739 ps
CPU time	547.23 seconds
Started	Apr 23 04:37:17 PM PDT 24
Finished	Apr 23 04:46:24 PM PDT 24
Peak memory	562792 kb
Host	smart-ad4d6c1f-d166-470a-ad26-3aa984860c79
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401740012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2401740012
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.448025257
Short name	T2794
Test name
Test status
Simulation time	290387723 ps
CPU time	27.25 seconds
Started	Apr 23 04:37:11 PM PDT 24
Finished	Apr 23 04:37:39 PM PDT 24
Peak memory	562716 kb
Host	smart-883794cf-3a9d-4461-a657-38e91e4040c9
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448025257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_dela ys.448025257
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_same_source.2994945364
Short name	T2460
Test name
Test status
Simulation time	281414398 ps
CPU time	12.63 seconds
Started	Apr 23 04:37:20 PM PDT 24
Finished	Apr 23 04:37:33 PM PDT 24
Peak memory	562740 kb
Host	smart-a0e36226-94a2-433d-a10b-8e8eef0c8274
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994945364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2994945364
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke.2715307045
Short name	T1620
Test name
Test status
Simulation time	50470628 ps
CPU time	6.82 seconds
Started	Apr 23 04:37:05 PM PDT 24
Finished	Apr 23 04:37:12 PM PDT 24
Peak memory	562656 kb
Host	smart-ac15a632-4cfc-4d6f-8062-46e177f068cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715307045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2715307045
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.3600931402
Short name	T1342
Test name
Test status
Simulation time	7154797241 ps
CPU time	79.02 seconds
Started	Apr 23 04:37:10 PM PDT 24
Finished	Apr 23 04:38:29 PM PDT 24
Peak memory	562768 kb
Host	smart-8a45b68d-cb56-40e3-8396-b004605010b9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600931402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3600931402
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2009957005
Short name	T1669
Test name
Test status
Simulation time	4651265453 ps
CPU time	84.98 seconds
Started	Apr 23 04:37:12 PM PDT 24
Finished	Apr 23 04:38:37 PM PDT 24
Peak memory	562716 kb
Host	smart-0cd56073-63f7-4603-aa31-6840c0b08011
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009957005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2009957005
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3640721340
Short name	T2373
Test name
Test status
Simulation time	42218663 ps
CPU time	6.63 seconds
Started	Apr 23 04:37:15 PM PDT 24
Finished	Apr 23 04:37:22 PM PDT 24
Peak memory	562700 kb
Host	smart-e2ad322c-90fe-450c-9cc7-43758f2c938d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640721340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.3640721340
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all.2975471014
Short name	T2086
Test name
Test status
Simulation time	563638037 ps
CPU time	56.06 seconds
Started	Apr 23 04:37:22 PM PDT 24
Finished	Apr 23 04:38:18 PM PDT 24
Peak memory	562804 kb
Host	smart-e0a7854f-7306-46c3-8841-dfe7a3ed6664
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975471014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2975471014
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.1825638768
Short name	T1566
Test name
Test status
Simulation time	5667967478 ps
CPU time	233.26 seconds
Started	Apr 23 04:37:28 PM PDT 24
Finished	Apr 23 04:41:21 PM PDT 24
Peak memory	562836 kb
Host	smart-f86f90f9-2e87-4324-a814-e891f6ff0a3f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825638768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1825638768
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.68274126
Short name	T800
Test name
Test status
Simulation time	2390643975 ps
CPU time	130.93 seconds
Started	Apr 23 04:37:25 PM PDT 24
Finished	Apr 23 04:39:36 PM PDT 24
Peak memory	572064 kb
Host	smart-50e7fd25-87a5-4b7f-8128-7c2bc2604a05
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68274126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_ with_reset_error.68274126
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.2278507317
Short name	T2768
Test name
Test status
Simulation time	1278766351 ps
CPU time	61.32 seconds
Started	Apr 23 04:37:20 PM PDT 24
Finished	Apr 23 04:38:22 PM PDT 24
Peak memory	562828 kb
Host	smart-45fd57b8-ba4a-4474-aa84-07c90ed408f0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278507317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2278507317
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.2810497711
Short name	T1779
Test name
Test status
Simulation time	6502836717 ps
CPU time	597.82 seconds
Started	Apr 23 04:28:29 PM PDT 24
Finished	Apr 23 04:38:27 PM PDT 24
Peak memory	585132 kb
Host	smart-6af0d889-0a2a-44c5-8ea1-f2eede84f4cc
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810497711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.2810497711
Directory	/workspace/2.chip_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_rw.3808835823
Short name	T497
Test name
Test status
Simulation time	6062282536 ps
CPU time	592.82 seconds
Started	Apr 23 04:29:20 PM PDT 24
Finished	Apr 23 04:39:14 PM PDT 24
Peak memory	589028 kb
Host	smart-5180300d-7dfe-4549-884a-1b5ab606cfec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808835823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3808835823
Directory	/workspace/2.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3665586595
Short name	T1777
Test name
Test status
Simulation time	6349216208 ps
CPU time	189.93 seconds
Started	Apr 23 04:28:43 PM PDT 24
Finished	Apr 23 04:31:54 PM PDT 24
Peak memory	580528 kb
Host	smart-b381c359-d862-44c9-a63a-6870119a827a
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665586595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3665586595
Directory	/workspace/2.chip_prim_tl_access/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3314552050
Short name	T2299
Test name
Test status
Simulation time	6974057971 ps
CPU time	216.25 seconds
Started	Apr 23 04:28:44 PM PDT 24
Finished	Apr 23 04:32:21 PM PDT 24
Peak memory	580628 kb
Host	smart-b4463516-0c7a-4db8-929d-1248196d7789
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314552050 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.3314552050
Directory	/workspace/2.chip_rv_dm_lc_disabled/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2251384303
Short name	T411
Test name
Test status
Simulation time	26848069783 ps
CPU time	3755.49 seconds
Started	Apr 23 04:28:41 PM PDT 24
Finished	Apr 23 05:31:17 PM PDT 24
Peak memory	585148 kb
Host	smart-20307241-75dc-4f23-9313-cd5248f62aa5
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251384303 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2251384303
Directory	/workspace/2.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_tl_errors.2223361008
Short name	T631
Test name
Test status
Simulation time	3414108520 ps
CPU time	304.38 seconds
Started	Apr 23 04:28:42 PM PDT 24
Finished	Apr 23 04:33:47 PM PDT 24
Peak memory	585196 kb
Host	smart-98a1ce36-4320-4dfb-ba52-7b227ed47355
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223361008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.2223361008
Directory	/workspace/2.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_access_same_device.3653984598
Short name	T2331
Test name
Test status
Simulation time	723602812 ps
CPU time	69.09 seconds
Started	Apr 23 04:29:04 PM PDT 24
Finished	Apr 23 04:30:14 PM PDT 24
Peak memory	562728 kb
Host	smart-1a17dc46-7ee2-456f-9159-204c463cf555
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653984598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 3653984598
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.1987941540
Short name	T2452
Test name
Test status
Simulation time	143420856076 ps
CPU time	2575.35 seconds
Started	Apr 23 04:29:13 PM PDT 24
Finished	Apr 23 05:12:09 PM PDT 24
Peak memory	562960 kb
Host	smart-ee04cf94-1916-4a7a-811b-685c4c8139a5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987941540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.1987941540
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.191302084
Short name	T2583
Test name
Test status
Simulation time	1024859302 ps
CPU time	40.73 seconds
Started	Apr 23 04:29:13 PM PDT 24
Finished	Apr 23 04:29:54 PM PDT 24
Peak memory	562708 kb
Host	smart-3db65ff3-34a3-412c-862a-703e524a70b4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191302084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr. 191302084
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_error_random.270058567
Short name	T2355
Test name
Test status
Simulation time	91475056 ps
CPU time	13.02 seconds
Started	Apr 23 04:29:20 PM PDT 24
Finished	Apr 23 04:29:33 PM PDT 24
Peak memory	562724 kb
Host	smart-476c6fa8-0f8c-4aa0-8f8c-96585d28427c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270058567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.270058567
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_random.2221298770
Short name	T2125
Test name
Test status
Simulation time	1659071928 ps
CPU time	70.62 seconds
Started	Apr 23 04:28:56 PM PDT 24
Finished	Apr 23 04:30:07 PM PDT 24
Peak memory	562704 kb
Host	smart-e441e7fc-a63a-413c-bdbd-dcc226e3346e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221298770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2221298770
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_random_large_delays.186055490
Short name	T2592
Test name
Test status
Simulation time	49560748592 ps
CPU time	600.91 seconds
Started	Apr 23 04:29:19 PM PDT 24
Finished	Apr 23 04:39:21 PM PDT 24
Peak memory	562844 kb
Host	smart-e25bf22a-f8bb-455a-88ba-103f697a0514
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186055490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.186055490
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.3469232613
Short name	T2445
Test name
Test status
Simulation time	21146012081 ps
CPU time	390.28 seconds
Started	Apr 23 04:28:59 PM PDT 24
Finished	Apr 23 04:35:29 PM PDT 24
Peak memory	562804 kb
Host	smart-8cb53dd1-31ec-4275-a816-2b63a155f17c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469232613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3469232613
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.24544737
Short name	T1864
Test name
Test status
Simulation time	65301991 ps
CPU time	10.59 seconds
Started	Apr 23 04:28:55 PM PDT 24
Finished	Apr 23 04:29:06 PM PDT 24
Peak memory	562744 kb
Host	smart-43bfc167-b525-4bea-ae3f-7f495c61893c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24544737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays .24544737
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_same_source.3744014321
Short name	T1450
Test name
Test status
Simulation time	1493814282 ps
CPU time	55.59 seconds
Started	Apr 23 04:29:25 PM PDT 24
Finished	Apr 23 04:30:21 PM PDT 24
Peak memory	562724 kb
Host	smart-1d8d65ac-b260-491e-b0e2-e080d80d8b6d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744014321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3744014321
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke.3721586186
Short name	T2403
Test name
Test status
Simulation time	46914956 ps
CPU time	7.09 seconds
Started	Apr 23 04:29:14 PM PDT 24
Finished	Apr 23 04:29:22 PM PDT 24
Peak memory	562708 kb
Host	smart-a60dfc79-162f-492f-8229-03285b6bb694
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721586186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3721586186
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.2756701099
Short name	T1522
Test name
Test status
Simulation time	9034485186 ps
CPU time	95.16 seconds
Started	Apr 23 04:28:45 PM PDT 24
Finished	Apr 23 04:30:20 PM PDT 24
Peak memory	562752 kb
Host	smart-54d95950-a430-4208-a89a-fa59d49a778e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756701099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2756701099
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1171830699
Short name	T1332
Test name
Test status
Simulation time	6685921374 ps
CPU time	104.02 seconds
Started	Apr 23 04:28:45 PM PDT 24
Finished	Apr 23 04:30:29 PM PDT 24
Peak memory	562760 kb
Host	smart-181ed295-fa28-4f64-8f7e-b1f846b6223c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171830699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1171830699
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3810093166
Short name	T2048
Test name
Test status
Simulation time	47686824 ps
CPU time	7.33 seconds
Started	Apr 23 04:28:50 PM PDT 24
Finished	Apr 23 04:28:57 PM PDT 24
Peak memory	562720 kb
Host	smart-d2823280-a840-41ba-9098-a704f0d16918
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810093166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .3810093166
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all.4110602683
Short name	T2061
Test name
Test status
Simulation time	8154493873 ps
CPU time	302.98 seconds
Started	Apr 23 04:29:18 PM PDT 24
Finished	Apr 23 04:34:21 PM PDT 24
Peak memory	563936 kb
Host	smart-7a004070-0242-4e33-9db0-db11f3f26765
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110602683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.4110602683
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.898388919
Short name	T801
Test name
Test status
Simulation time	1927357953 ps
CPU time	73.88 seconds
Started	Apr 23 04:29:16 PM PDT 24
Finished	Apr 23 04:30:30 PM PDT 24
Peak memory	562852 kb
Host	smart-c6c88cb0-9b84-4d78-b8e6-f748a2c0db32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898388919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.898388919
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1334103788
Short name	T423
Test name
Test status
Simulation time	3516622223 ps
CPU time	341.76 seconds
Started	Apr 23 04:29:13 PM PDT 24
Finished	Apr 23 04:34:55 PM PDT 24
Peak memory	563952 kb
Host	smart-3510fec7-bb25-46ea-a76d-6c027473e98d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334103788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.1334103788
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2792949042
Short name	T2487
Test name
Test status
Simulation time	20331962288 ps
CPU time	1083.17 seconds
Started	Apr 23 04:29:17 PM PDT 24
Finished	Apr 23 04:47:21 PM PDT 24
Peak memory	572212 kb
Host	smart-0dd8f936-45b1-452b-9e05-a646220964f2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792949042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.2792949042
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.3584788597
Short name	T2522
Test name
Test status
Simulation time	165721469 ps
CPU time	9.64 seconds
Started	Apr 23 04:29:12 PM PDT 24
Finished	Apr 23 04:29:22 PM PDT 24
Peak memory	562756 kb
Host	smart-4cfff0f9-c679-4579-a57e-371b51400010
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584788597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3584788597
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/20.chip_tl_errors.1866894280
Short name	T602
Test name
Test status
Simulation time	2865306344 ps
CPU time	212.27 seconds
Started	Apr 23 04:37:29 PM PDT 24
Finished	Apr 23 04:41:01 PM PDT 24
Peak memory	593368 kb
Host	smart-653a8b6a-2765-4209-89d3-c8fb1de1d9df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866894280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.1866894280
Directory	/workspace/20.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_access_same_device.1397892674
Short name	T780
Test name
Test status
Simulation time	1712058839 ps
CPU time	76.46 seconds
Started	Apr 23 04:37:39 PM PDT 24
Finished	Apr 23 04:38:56 PM PDT 24
Peak memory	562744 kb
Host	smart-612ee936-2138-422d-9637-26ff9ce184cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397892674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .1397892674
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2161938968
Short name	T2219
Test name
Test status
Simulation time	129065814510 ps
CPU time	2203.61 seconds
Started	Apr 23 04:37:39 PM PDT 24
Finished	Apr 23 05:14:24 PM PDT 24
Peak memory	562888 kb
Host	smart-2f220468-b732-4473-b746-f013e55be152
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161938968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.2161938968
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2288751094
Short name	T2567
Test name
Test status
Simulation time	912648626 ps
CPU time	35.95 seconds
Started	Apr 23 04:37:37 PM PDT 24
Finished	Apr 23 04:38:13 PM PDT 24
Peak memory	562704 kb
Host	smart-e21ad1f4-7892-4061-a649-6761e05dc3de
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288751094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.2288751094
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_error_random.903719028
Short name	T2167
Test name
Test status
Simulation time	914358758 ps
CPU time	36.87 seconds
Started	Apr 23 04:37:39 PM PDT 24
Finished	Apr 23 04:38:16 PM PDT 24
Peak memory	562736 kb
Host	smart-fddbd6ee-43bd-4fd7-ac1e-ef62956e6877
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903719028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.903719028
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_random.2553373240
Short name	T2216
Test name
Test status
Simulation time	546677116 ps
CPU time	51.37 seconds
Started	Apr 23 04:37:39 PM PDT 24
Finished	Apr 23 04:38:31 PM PDT 24
Peak memory	562692 kb
Host	smart-1143c7bd-6f74-489d-9a1f-066b440c6edc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553373240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2553373240
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_random_large_delays.1439795037
Short name	T2076
Test name
Test status
Simulation time	68751813186 ps
CPU time	826.15 seconds
Started	Apr 23 04:37:38 PM PDT 24
Finished	Apr 23 04:51:25 PM PDT 24
Peak memory	562808 kb
Host	smart-2510a97d-4c33-4f51-b7e8-204b7d2cbc5f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439795037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1439795037
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.4183743327
Short name	T2780
Test name
Test status
Simulation time	9639531913 ps
CPU time	195.27 seconds
Started	Apr 23 04:37:42 PM PDT 24
Finished	Apr 23 04:40:57 PM PDT 24
Peak memory	562820 kb
Host	smart-5490c60a-f097-4f04-b75d-7bdc9f6daa8b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183743327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.4183743327
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.2867590675
Short name	T1872
Test name
Test status
Simulation time	438089638 ps
CPU time	34.63 seconds
Started	Apr 23 04:37:32 PM PDT 24
Finished	Apr 23 04:38:07 PM PDT 24
Peak memory	562672 kb
Host	smart-8ad2dc46-3cae-4161-a225-08dd94508bd3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867590675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.2867590675
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_same_source.2381288707
Short name	T2599
Test name
Test status
Simulation time	507982167 ps
CPU time	18.36 seconds
Started	Apr 23 04:37:38 PM PDT 24
Finished	Apr 23 04:37:57 PM PDT 24
Peak memory	562752 kb
Host	smart-b358744b-3a67-487a-9b04-be1de82d4f55
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381288707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2381288707
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke.2643540128
Short name	T1908
Test name
Test status
Simulation time	199615148 ps
CPU time	9.63 seconds
Started	Apr 23 04:37:28 PM PDT 24
Finished	Apr 23 04:37:38 PM PDT 24
Peak memory	562632 kb
Host	smart-9fe596dc-a515-4817-83c5-56a49053de11
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643540128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2643540128
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.208951994
Short name	T1228
Test name
Test status
Simulation time	5128907469 ps
CPU time	58.94 seconds
Started	Apr 23 04:37:33 PM PDT 24
Finished	Apr 23 04:38:32 PM PDT 24
Peak memory	562768 kb
Host	smart-4e6a51d5-37a0-4531-901d-0f5ef1e97205
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208951994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.208951994
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.1838030643
Short name	T2066
Test name
Test status
Simulation time	5557204516 ps
CPU time	101.79 seconds
Started	Apr 23 04:37:32 PM PDT 24
Finished	Apr 23 04:39:14 PM PDT 24
Peak memory	562696 kb
Host	smart-83f5681f-d2cf-4140-8332-5eea3eefb0cb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838030643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1838030643
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2383074643
Short name	T1559
Test name
Test status
Simulation time	52063240 ps
CPU time	7.08 seconds
Started	Apr 23 04:37:39 PM PDT 24
Finished	Apr 23 04:37:47 PM PDT 24
Peak memory	562652 kb
Host	smart-fadb0cdb-425c-4261-a100-620b4f8da5df
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383074643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.2383074643
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all.3253248229
Short name	T2437
Test name
Test status
Simulation time	1480705022 ps
CPU time	127.1 seconds
Started	Apr 23 04:37:41 PM PDT 24
Finished	Apr 23 04:39:49 PM PDT 24
Peak memory	563756 kb
Host	smart-c908f33d-fcec-4b48-a3a1-98da42ef3a02
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253248229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3253248229
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.727612948
Short name	T1549
Test name
Test status
Simulation time	6931940875 ps
CPU time	245.35 seconds
Started	Apr 23 04:37:43 PM PDT 24
Finished	Apr 23 04:41:49 PM PDT 24
Peak memory	563100 kb
Host	smart-2e5bc982-7d23-4b6d-8c9c-61c1da017c6c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727612948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.727612948
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2893134233
Short name	T1531
Test name
Test status
Simulation time	155463966 ps
CPU time	61.1 seconds
Started	Apr 23 04:37:41 PM PDT 24
Finished	Apr 23 04:38:43 PM PDT 24
Peak memory	563888 kb
Host	smart-0079d2b0-c83b-4857-af53-1df5d6f94ab5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893134233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.2893134233
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.579017466
Short name	T1463
Test name
Test status
Simulation time	2596014921 ps
CPU time	405.75 seconds
Started	Apr 23 04:37:45 PM PDT 24
Finished	Apr 23 04:44:31 PM PDT 24
Peak memory	572244 kb
Host	smart-5311f42d-a973-4df8-aa66-2f955b372755
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579017466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_reset_error.579017466
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.3821521636
Short name	T2554
Test name
Test status
Simulation time	301994729 ps
CPU time	36.77 seconds
Started	Apr 23 04:37:39 PM PDT 24
Finished	Apr 23 04:38:16 PM PDT 24
Peak memory	562716 kb
Host	smart-5ce08fef-f905-49c0-958a-698322dadef9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821521636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3821521636
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_access_same_device.2935639711
Short name	T82
Test name
Test status
Simulation time	397975668 ps
CPU time	34.11 seconds
Started	Apr 23 04:37:49 PM PDT 24
Finished	Apr 23 04:38:23 PM PDT 24
Peak memory	562756 kb
Host	smart-3d010a91-caee-4ea9-a810-c4f4fbfddc9f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935639711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .2935639711
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3078110558
Short name	T465
Test name
Test status
Simulation time	80448598939 ps
CPU time	1373.85 seconds
Started	Apr 23 04:37:51 PM PDT 24
Finished	Apr 23 05:00:45 PM PDT 24
Peak memory	562836 kb
Host	smart-3e7b8817-00d1-4a78-9e35-d20f3799a5aa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078110558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.3078110558
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1620566434
Short name	T2041
Test name
Test status
Simulation time	118619792 ps
CPU time	16.77 seconds
Started	Apr 23 04:37:55 PM PDT 24
Finished	Apr 23 04:38:12 PM PDT 24
Peak memory	562708 kb
Host	smart-c38af8f4-dd0d-4d77-9110-8a1069f55b98
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620566434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1620566434
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_error_random.2905447335
Short name	T1235
Test name
Test status
Simulation time	913768251 ps
CPU time	37.97 seconds
Started	Apr 23 04:37:52 PM PDT 24
Finished	Apr 23 04:38:31 PM PDT 24
Peak memory	562644 kb
Host	smart-caf0c04e-9f10-412b-9991-487a401efa1c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905447335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2905447335
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_random.3358736158
Short name	T470
Test name
Test status
Simulation time	258364362 ps
CPU time	28.23 seconds
Started	Apr 23 04:37:47 PM PDT 24
Finished	Apr 23 04:38:15 PM PDT 24
Peak memory	562752 kb
Host	smart-b3e77c8f-afbe-4fe2-9d21-0823730b79f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358736158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3358736158
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_random_large_delays.3808042135
Short name	T1251
Test name
Test status
Simulation time	55598467829 ps
CPU time	649.22 seconds
Started	Apr 23 04:37:48 PM PDT 24
Finished	Apr 23 04:48:38 PM PDT 24
Peak memory	562872 kb
Host	smart-f0a3dd6d-d8cc-4121-b5ed-c022c46332fd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808042135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3808042135
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.1305268498
Short name	T2720
Test name
Test status
Simulation time	45694110686 ps
CPU time	811.86 seconds
Started	Apr 23 04:37:50 PM PDT 24
Finished	Apr 23 04:51:22 PM PDT 24
Peak memory	562848 kb
Host	smart-4151d365-2896-4574-b7e2-e5b070c94d2a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305268498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1305268498
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.2169449823
Short name	T2023
Test name
Test status
Simulation time	63235175 ps
CPU time	9.89 seconds
Started	Apr 23 04:37:47 PM PDT 24
Finished	Apr 23 04:37:57 PM PDT 24
Peak memory	562688 kb
Host	smart-638aa87f-743d-44ff-a48a-f2f844f2d6cd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169449823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.2169449823
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_same_source.344074003
Short name	T1423
Test name
Test status
Simulation time	1930874084 ps
CPU time	61.02 seconds
Started	Apr 23 04:37:54 PM PDT 24
Finished	Apr 23 04:38:55 PM PDT 24
Peak memory	562732 kb
Host	smart-628a0974-b83a-45b1-b9bb-5cdc41832ea4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344074003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.344074003
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke.597556919
Short name	T2378
Test name
Test status
Simulation time	149020275 ps
CPU time	9.05 seconds
Started	Apr 23 04:37:46 PM PDT 24
Finished	Apr 23 04:37:55 PM PDT 24
Peak memory	562700 kb
Host	smart-314d6f78-a0be-48ea-9827-91cbe3423765
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597556919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.597556919
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2654044805
Short name	T1311
Test name
Test status
Simulation time	6093816388 ps
CPU time	72.42 seconds
Started	Apr 23 04:37:50 PM PDT 24
Finished	Apr 23 04:39:02 PM PDT 24
Peak memory	562724 kb
Host	smart-7508b544-1c04-41f8-b153-a6faf192e728
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654044805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2654044805
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.371985216
Short name	T1254
Test name
Test status
Simulation time	5139744222 ps
CPU time	92.47 seconds
Started	Apr 23 04:37:46 PM PDT 24
Finished	Apr 23 04:39:19 PM PDT 24
Peak memory	562764 kb
Host	smart-f6566fec-a52f-42fb-b44d-ca1c038fcb6b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371985216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.371985216
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1065004281
Short name	T2576
Test name
Test status
Simulation time	40011660 ps
CPU time	5.77 seconds
Started	Apr 23 04:37:47 PM PDT 24
Finished	Apr 23 04:37:53 PM PDT 24
Peak memory	562684 kb
Host	smart-f0c93220-e30d-4c88-92b6-868c7e23c81c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065004281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.1065004281
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all.1770650353
Short name	T2718
Test name
Test status
Simulation time	14308983628 ps
CPU time	568.62 seconds
Started	Apr 23 04:38:01 PM PDT 24
Finished	Apr 23 04:47:30 PM PDT 24
Peak memory	572204 kb
Host	smart-e302ecda-1a6e-4ec7-8817-a3788e1ec139
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770650353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1770650353
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2212192903
Short name	T2115
Test name
Test status
Simulation time	548705849 ps
CPU time	51.31 seconds
Started	Apr 23 04:37:56 PM PDT 24
Finished	Apr 23 04:38:48 PM PDT 24
Peak memory	562692 kb
Host	smart-dc9850b3-3a61-4db4-b15e-cc9aa0aeb584
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212192903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2212192903
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3130082248
Short name	T421
Test name
Test status
Simulation time	4252029596 ps
CPU time	424.49 seconds
Started	Apr 23 04:37:57 PM PDT 24
Finished	Apr 23 04:45:02 PM PDT 24
Peak memory	572180 kb
Host	smart-63538a51-8ff4-486e-b583-c034927e2095
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130082248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.3130082248
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.602012804
Short name	T2462
Test name
Test status
Simulation time	2745109702 ps
CPU time	251.57 seconds
Started	Apr 23 04:37:57 PM PDT 24
Finished	Apr 23 04:42:09 PM PDT 24
Peak memory	563968 kb
Host	smart-a089b651-e1a8-422c-8b0e-484d6a420ff6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602012804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_reset_error.602012804
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.924135575
Short name	T2471
Test name
Test status
Simulation time	32393568 ps
CPU time	7.23 seconds
Started	Apr 23 04:37:56 PM PDT 24
Finished	Apr 23 04:38:04 PM PDT 24
Peak memory	562748 kb
Host	smart-b67bc865-5f84-4640-bdd0-288d61b6ecc4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924135575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.924135575
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/22.chip_tl_errors.2518339302
Short name	T551
Test name
Test status
Simulation time	3546482512 ps
CPU time	232.33 seconds
Started	Apr 23 04:38:00 PM PDT 24
Finished	Apr 23 04:41:52 PM PDT 24
Peak memory	593416 kb
Host	smart-05a5d721-8d0a-4756-93e0-0958aebfa272
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518339302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2518339302
Directory	/workspace/22.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_access_same_device.72840756
Short name	T2434
Test name
Test status
Simulation time	212755607 ps
CPU time	26.44 seconds
Started	Apr 23 04:38:05 PM PDT 24
Finished	Apr 23 04:38:31 PM PDT 24
Peak memory	562744 kb
Host	smart-9d47fd19-0413-47c5-9d41-782bf3182141
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72840756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.72840756
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.835101854
Short name	T1790
Test name
Test status
Simulation time	10767342793 ps
CPU time	176.1 seconds
Started	Apr 23 04:38:02 PM PDT 24
Finished	Apr 23 04:40:58 PM PDT 24
Peak memory	562732 kb
Host	smart-b5433c27-01d7-48cd-8842-6b9483d3eb93
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835101854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_d evice_slow_rsp.835101854
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.599567347
Short name	T1818
Test name
Test status
Simulation time	163750468 ps
CPU time	21.18 seconds
Started	Apr 23 04:38:04 PM PDT 24
Finished	Apr 23 04:38:26 PM PDT 24
Peak memory	562744 kb
Host	smart-4b988f6e-72bb-405f-85de-8ba3cdea8d37
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599567347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr .599567347
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_error_random.1066719055
Short name	T1568
Test name
Test status
Simulation time	543131846 ps
CPU time	46.05 seconds
Started	Apr 23 04:38:03 PM PDT 24
Finished	Apr 23 04:38:50 PM PDT 24
Peak memory	562696 kb
Host	smart-c0250a9e-1828-4d26-bf21-632530cf6cce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066719055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1066719055
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_random.1566374444
Short name	T1978
Test name
Test status
Simulation time	369820021 ps
CPU time	42.09 seconds
Started	Apr 23 04:37:58 PM PDT 24
Finished	Apr 23 04:38:40 PM PDT 24
Peak memory	562732 kb
Host	smart-42716ef3-7798-465c-b809-d89a84fc45e5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566374444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.1566374444
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_random_large_delays.470009543
Short name	T2558
Test name
Test status
Simulation time	29915981597 ps
CPU time	336.95 seconds
Started	Apr 23 04:38:02 PM PDT 24
Finished	Apr 23 04:43:39 PM PDT 24
Peak memory	562816 kb
Host	smart-3c841bae-d919-40ac-9b58-da0d44124478
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470009543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.470009543
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.1137528038
Short name	T2286
Test name
Test status
Simulation time	14754457049 ps
CPU time	294.04 seconds
Started	Apr 23 04:38:03 PM PDT 24
Finished	Apr 23 04:42:57 PM PDT 24
Peak memory	562852 kb
Host	smart-df9fb9c9-d4a5-4080-abf1-84691161754f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137528038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1137528038
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.2601529052
Short name	T1327
Test name
Test status
Simulation time	42074746 ps
CPU time	7.14 seconds
Started	Apr 23 04:38:03 PM PDT 24
Finished	Apr 23 04:38:11 PM PDT 24
Peak memory	562696 kb
Host	smart-9ebedce3-a64c-4530-9b60-2052d5f63cbe
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601529052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.2601529052
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_same_source.3970396805
Short name	T2666
Test name
Test status
Simulation time	501781823 ps
CPU time	42.3 seconds
Started	Apr 23 04:38:01 PM PDT 24
Finished	Apr 23 04:38:43 PM PDT 24
Peak memory	562732 kb
Host	smart-7302eedc-b4bd-41f3-9503-93e73c7342ab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970396805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3970396805
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke.2140381938
Short name	T2181
Test name
Test status
Simulation time	189279193 ps
CPU time	8.8 seconds
Started	Apr 23 04:38:05 PM PDT 24
Finished	Apr 23 04:38:14 PM PDT 24
Peak memory	562696 kb
Host	smart-2e4ddc40-3155-4bdc-9493-a3f3693cdb82
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140381938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2140381938
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.497390772
Short name	T2654
Test name
Test status
Simulation time	8429225280 ps
CPU time	92.07 seconds
Started	Apr 23 04:37:58 PM PDT 24
Finished	Apr 23 04:39:31 PM PDT 24
Peak memory	562776 kb
Host	smart-c2153889-65bb-47a8-99df-bedad5881546
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497390772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.497390772
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.343032638
Short name	T1825
Test name
Test status
Simulation time	6769366708 ps
CPU time	116.34 seconds
Started	Apr 23 04:37:58 PM PDT 24
Finished	Apr 23 04:39:55 PM PDT 24
Peak memory	562776 kb
Host	smart-231f3f7c-cb60-4d0d-9108-f152cf1c0c02
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343032638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.343032638
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.3746619599
Short name	T1346
Test name
Test status
Simulation time	44941846 ps
CPU time	6.44 seconds
Started	Apr 23 04:38:05 PM PDT 24
Finished	Apr 23 04:38:12 PM PDT 24
Peak memory	562676 kb
Host	smart-814fa60a-1970-4547-aeae-046d746df141
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746619599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.3746619599
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all.1310624560
Short name	T2353
Test name
Test status
Simulation time	11129198981 ps
CPU time	404.85 seconds
Started	Apr 23 04:38:08 PM PDT 24
Finished	Apr 23 04:44:53 PM PDT 24
Peak memory	563956 kb
Host	smart-dfece71a-3cec-4f07-8ae0-c57f25f318ed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310624560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1310624560
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.280351658
Short name	T2257
Test name
Test status
Simulation time	4457762101 ps
CPU time	196 seconds
Started	Apr 23 04:38:08 PM PDT 24
Finished	Apr 23 04:41:25 PM PDT 24
Peak memory	571056 kb
Host	smart-a0e5a1d5-58d2-41fa-86d3-dce7af2ba088
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280351658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.280351658
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.210243798
Short name	T2773
Test name
Test status
Simulation time	216698364 ps
CPU time	95.13 seconds
Started	Apr 23 04:38:09 PM PDT 24
Finished	Apr 23 04:39:44 PM PDT 24
Peak memory	563948 kb
Host	smart-c717fcf0-3874-436a-b3fb-53d0537af66a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210243798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_ with_rand_reset.210243798
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2196340611
Short name	T1695
Test name
Test status
Simulation time	349794893 ps
CPU time	140.53 seconds
Started	Apr 23 04:38:10 PM PDT 24
Finished	Apr 23 04:40:31 PM PDT 24
Peak memory	563952 kb
Host	smart-6aaa0157-d693-49c6-a151-e845e558296c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196340611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.2196340611
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3439012571
Short name	T1701
Test name
Test status
Simulation time	755609097 ps
CPU time	37.83 seconds
Started	Apr 23 04:38:04 PM PDT 24
Finished	Apr 23 04:38:42 PM PDT 24
Peak memory	562780 kb
Host	smart-99fe7b76-c16c-40d7-9b4a-5d4cd3dbdaf0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439012571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3439012571
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_access_same_device.1809857825
Short name	T1745
Test name
Test status
Simulation time	940129387 ps
CPU time	80.95 seconds
Started	Apr 23 04:38:25 PM PDT 24
Finished	Apr 23 04:39:46 PM PDT 24
Peak memory	562696 kb
Host	smart-ccc4e53e-cd58-4285-b507-9aa46f13fb5c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809857825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .1809857825
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.968438597
Short name	T2578
Test name
Test status
Simulation time	21529631519 ps
CPU time	377.39 seconds
Started	Apr 23 04:38:25 PM PDT 24
Finished	Apr 23 04:44:43 PM PDT 24
Peak memory	562780 kb
Host	smart-126c2d3f-1fd8-4bd6-a239-e325ae8c8579
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968438597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_d evice_slow_rsp.968438597
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2075718593
Short name	T2399
Test name
Test status
Simulation time	131719629 ps
CPU time	19.46 seconds
Started	Apr 23 04:38:27 PM PDT 24
Finished	Apr 23 04:38:47 PM PDT 24
Peak memory	562696 kb
Host	smart-442d5d6f-511d-4490-bb7f-4dad82e23d6a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075718593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.2075718593
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_error_random.1927441946
Short name	T2489
Test name
Test status
Simulation time	1355646860 ps
CPU time	49.71 seconds
Started	Apr 23 04:38:31 PM PDT 24
Finished	Apr 23 04:39:21 PM PDT 24
Peak memory	562716 kb
Host	smart-af1773bd-488b-42d1-98e3-dbb5233d0a4c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927441946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1927441946
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_random.3244258566
Short name	T2287
Test name
Test status
Simulation time	140597530 ps
CPU time	9.09 seconds
Started	Apr 23 04:38:20 PM PDT 24
Finished	Apr 23 04:38:29 PM PDT 24
Peak memory	562748 kb
Host	smart-015b4650-2f7d-467d-a20f-ca63d5990da9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244258566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.3244258566
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2029672468
Short name	T1601
Test name
Test status
Simulation time	27447813953 ps
CPU time	327.32 seconds
Started	Apr 23 04:38:21 PM PDT 24
Finished	Apr 23 04:43:48 PM PDT 24
Peak memory	562816 kb
Host	smart-97178f65-dc9f-4e96-b368-bf773a942c0d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029672468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2029672468
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.365321319
Short name	T1504
Test name
Test status
Simulation time	8732464692 ps
CPU time	147.56 seconds
Started	Apr 23 04:38:26 PM PDT 24
Finished	Apr 23 04:40:54 PM PDT 24
Peak memory	562744 kb
Host	smart-f3946a12-b552-462f-9f60-b65fbbb8f396
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365321319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.365321319
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.3981778609
Short name	T2222
Test name
Test status
Simulation time	496286170 ps
CPU time	54.69 seconds
Started	Apr 23 04:38:20 PM PDT 24
Finished	Apr 23 04:39:15 PM PDT 24
Peak memory	562740 kb
Host	smart-70903e4d-45a4-418e-a458-3eca1fe2960c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981778609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.3981778609
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_same_source.2174318509
Short name	T1441
Test name
Test status
Simulation time	166625251 ps
CPU time	8.76 seconds
Started	Apr 23 04:38:29 PM PDT 24
Finished	Apr 23 04:38:38 PM PDT 24
Peak memory	562692 kb
Host	smart-c5e859a5-bcc5-4ea7-988c-19d61be1b939
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174318509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2174318509
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke.4207584082
Short name	T2078
Test name
Test status
Simulation time	235237540 ps
CPU time	10.43 seconds
Started	Apr 23 04:38:09 PM PDT 24
Finished	Apr 23 04:38:20 PM PDT 24
Peak memory	562712 kb
Host	smart-43d6ca3d-df3a-4798-b541-a1c62090e34b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207584082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.4207584082
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.1891676984
Short name	T1737
Test name
Test status
Simulation time	8982277452 ps
CPU time	95.88 seconds
Started	Apr 23 04:38:19 PM PDT 24
Finished	Apr 23 04:39:55 PM PDT 24
Peak memory	562808 kb
Host	smart-fa6651ef-c504-4933-819c-73f1b2f4d837
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891676984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1891676984
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3358738459
Short name	T1518
Test name
Test status
Simulation time	6251535820 ps
CPU time	110.27 seconds
Started	Apr 23 04:38:17 PM PDT 24
Finished	Apr 23 04:40:07 PM PDT 24
Peak memory	562728 kb
Host	smart-a032cd9d-251b-4d47-82c8-de03dbc0428a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358738459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3358738459
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1704555571
Short name	T1269
Test name
Test status
Simulation time	41044470 ps
CPU time	6.61 seconds
Started	Apr 23 04:38:14 PM PDT 24
Finished	Apr 23 04:38:21 PM PDT 24
Peak memory	562712 kb
Host	smart-c0b8a94a-a600-4647-aad7-863532d525d7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704555571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.1704555571
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all.3070662806
Short name	T1611
Test name
Test status
Simulation time	6411788959 ps
CPU time	242.26 seconds
Started	Apr 23 04:38:32 PM PDT 24
Finished	Apr 23 04:42:35 PM PDT 24
Peak memory	563980 kb
Host	smart-6e0f74ef-c6cb-4094-8694-0ab087e60b84
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070662806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3070662806
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.909419325
Short name	T1602
Test name
Test status
Simulation time	1042592070 ps
CPU time	95.24 seconds
Started	Apr 23 04:38:34 PM PDT 24
Finished	Apr 23 04:40:10 PM PDT 24
Peak memory	562796 kb
Host	smart-4ca9c529-8187-4ccb-b44c-a6a0ce8e5cd9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909419325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.909419325
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.4074997104
Short name	T2609
Test name
Test status
Simulation time	25781682511 ps
CPU time	1068.1 seconds
Started	Apr 23 04:38:41 PM PDT 24
Finished	Apr 23 04:56:30 PM PDT 24
Peak memory	572180 kb
Host	smart-47969828-e82c-42ea-ba75-a22859480e13
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074997104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.4074997104
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2475434198
Short name	T1544
Test name
Test status
Simulation time	617061789 ps
CPU time	198.41 seconds
Started	Apr 23 04:38:40 PM PDT 24
Finished	Apr 23 04:41:59 PM PDT 24
Peak memory	572124 kb
Host	smart-76fd5774-85a8-4dec-a9b7-c8db0d0b6c9e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475434198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.2475434198
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.2243477271
Short name	T2036
Test name
Test status
Simulation time	686917807 ps
CPU time	35.49 seconds
Started	Apr 23 04:38:28 PM PDT 24
Finished	Apr 23 04:39:04 PM PDT 24
Peak memory	562768 kb
Host	smart-780f0bde-9065-4bea-bc9a-884aed967f0c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243477271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2243477271
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/24.chip_tl_errors.1424342852
Short name	T514
Test name
Test status
Simulation time	3552339964 ps
CPU time	185.11 seconds
Started	Apr 23 04:38:41 PM PDT 24
Finished	Apr 23 04:41:47 PM PDT 24
Peak memory	585200 kb
Host	smart-0fd0df3d-6e44-4328-bda8-d72552882e1e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424342852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.1424342852
Directory	/workspace/24.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_access_same_device.2621743337
Short name	T753
Test name
Test status
Simulation time	1383135306 ps
CPU time	64.24 seconds
Started	Apr 23 04:38:39 PM PDT 24
Finished	Apr 23 04:39:43 PM PDT 24
Peak memory	562680 kb
Host	smart-944a93b4-01fe-4c74-aae1-68874dc2d46d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621743337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .2621743337
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3164970120
Short name	T2728
Test name
Test status
Simulation time	22628033442 ps
CPU time	402.32 seconds
Started	Apr 23 04:38:42 PM PDT 24
Finished	Apr 23 04:45:25 PM PDT 24
Peak memory	562808 kb
Host	smart-15a20f06-8bac-4c57-84ee-a85d4634e59d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164970120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.3164970120
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1068319384
Short name	T2184
Test name
Test status
Simulation time	161243744 ps
CPU time	20.21 seconds
Started	Apr 23 04:38:42 PM PDT 24
Finished	Apr 23 04:39:02 PM PDT 24
Peak memory	562732 kb
Host	smart-15907605-0792-46ee-a498-80e17f82af94
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068319384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1068319384
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_error_random.662411748
Short name	T2667
Test name
Test status
Simulation time	151309121 ps
CPU time	9.64 seconds
Started	Apr 23 04:38:42 PM PDT 24
Finished	Apr 23 04:38:52 PM PDT 24
Peak memory	562704 kb
Host	smart-a9a8b0fd-4e0a-4a3a-b93f-f7352c7afdc6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662411748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.662411748
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_random.831481556
Short name	T2119
Test name
Test status
Simulation time	1704160486 ps
CPU time	64.65 seconds
Started	Apr 23 04:38:39 PM PDT 24
Finished	Apr 23 04:39:44 PM PDT 24
Peak memory	562764 kb
Host	smart-81f3ae29-b29f-46f6-8ece-2db84bd1049d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831481556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.831481556
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_random_large_delays.3715682447
Short name	T2531
Test name
Test status
Simulation time	84572284505 ps
CPU time	930.35 seconds
Started	Apr 23 04:38:39 PM PDT 24
Finished	Apr 23 04:54:10 PM PDT 24
Peak memory	562896 kb
Host	smart-3321f458-022a-4898-b92d-4d50d016463c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715682447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3715682447
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.1231801508
Short name	T1920
Test name
Test status
Simulation time	18933373520 ps
CPU time	351.19 seconds
Started	Apr 23 04:38:36 PM PDT 24
Finished	Apr 23 04:44:28 PM PDT 24
Peak memory	562824 kb
Host	smart-f05147bd-5fe2-40ce-8264-e995fd67bbe0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231801508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1231801508
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.4112451061
Short name	T1984
Test name
Test status
Simulation time	387902587 ps
CPU time	38.92 seconds
Started	Apr 23 04:38:35 PM PDT 24
Finished	Apr 23 04:39:15 PM PDT 24
Peak memory	562752 kb
Host	smart-9d07ba54-0bfc-43a1-8fdb-6102cf550ae2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112451061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.4112451061
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_same_source.3359348564
Short name	T2673
Test name
Test status
Simulation time	2122505994 ps
CPU time	61.25 seconds
Started	Apr 23 04:38:40 PM PDT 24
Finished	Apr 23 04:39:42 PM PDT 24
Peak memory	562744 kb
Host	smart-8fc9757b-b250-4162-adf6-c0bb8bb8e9b8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359348564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3359348564
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke.4006247140
Short name	T1972
Test name
Test status
Simulation time	205547085 ps
CPU time	8.68 seconds
Started	Apr 23 04:38:41 PM PDT 24
Finished	Apr 23 04:38:50 PM PDT 24
Peak memory	562684 kb
Host	smart-d3896be9-0a0d-4b2a-a829-e2e4a21e5839
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006247140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.4006247140
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.2350141539
Short name	T2013
Test name
Test status
Simulation time	7213480526 ps
CPU time	79.76 seconds
Started	Apr 23 04:38:36 PM PDT 24
Finished	Apr 23 04:39:57 PM PDT 24
Peak memory	562788 kb
Host	smart-751252d8-e1b2-43e2-899b-1eb95004e114
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350141539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2350141539
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3627932775
Short name	T1491
Test name
Test status
Simulation time	3664095920 ps
CPU time	66.85 seconds
Started	Apr 23 04:38:36 PM PDT 24
Finished	Apr 23 04:39:43 PM PDT 24
Peak memory	562788 kb
Host	smart-4d72e80d-2f08-4385-a182-6c37284a0d5a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627932775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3627932775
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.845352263
Short name	T1234
Test name
Test status
Simulation time	41243146 ps
CPU time	5.67 seconds
Started	Apr 23 04:38:35 PM PDT 24
Finished	Apr 23 04:38:41 PM PDT 24
Peak memory	562724 kb
Host	smart-6fc647f1-2593-4fb6-87b8-67ecd74756d2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845352263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .845352263
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all.1891149710
Short name	T1787
Test name
Test status
Simulation time	15437732227 ps
CPU time	514.53 seconds
Started	Apr 23 04:38:43 PM PDT 24
Finished	Apr 23 04:47:18 PM PDT 24
Peak memory	563992 kb
Host	smart-95272ea3-89d6-43aa-bf9c-f94ddf5bbae6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891149710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1891149710
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.1417787058
Short name	T2715
Test name
Test status
Simulation time	2834122839 ps
CPU time	219.76 seconds
Started	Apr 23 04:38:44 PM PDT 24
Finished	Apr 23 04:42:24 PM PDT 24
Peak memory	562936 kb
Host	smart-c6c17d4f-3eaf-4153-bcb1-1569cd413b88
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417787058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1417787058
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3095414502
Short name	T2375
Test name
Test status
Simulation time	3416994953 ps
CPU time	276.53 seconds
Started	Apr 23 04:38:42 PM PDT 24
Finished	Apr 23 04:43:19 PM PDT 24
Peak memory	563956 kb
Host	smart-055dcdb4-a2d5-441a-a7d2-57f4dacaf3e6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095414502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.3095414502
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.4292439782
Short name	T822
Test name
Test status
Simulation time	6432107571 ps
CPU time	331.3 seconds
Started	Apr 23 04:38:45 PM PDT 24
Finished	Apr 23 04:44:17 PM PDT 24
Peak memory	564036 kb
Host	smart-bfa87aa3-5bcc-4f2b-8621-5108da779fee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292439782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.4292439782
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2561523134
Short name	T557
Test name
Test status
Simulation time	59985833 ps
CPU time	9.52 seconds
Started	Apr 23 04:38:42 PM PDT 24
Finished	Apr 23 04:38:51 PM PDT 24
Peak memory	562792 kb
Host	smart-998a0837-cfcf-4628-8f55-f528f37571f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561523134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2561523134
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_access_same_device.2889778901
Short name	T1393
Test name
Test status
Simulation time	402989408 ps
CPU time	40.76 seconds
Started	Apr 23 04:38:57 PM PDT 24
Finished	Apr 23 04:39:38 PM PDT 24
Peak memory	562716 kb
Host	smart-a09c4d44-c5bf-44cb-a330-07df45a029b5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889778901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .2889778901
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1876783334
Short name	T2203
Test name
Test status
Simulation time	32734218848 ps
CPU time	610.58 seconds
Started	Apr 23 04:38:55 PM PDT 24
Finished	Apr 23 04:49:06 PM PDT 24
Peak memory	562828 kb
Host	smart-98a36209-f8d6-41b0-b445-f7165ea94524
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876783334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.1876783334
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.845694830
Short name	T416
Test name
Test status
Simulation time	161767867 ps
CPU time	19.46 seconds
Started	Apr 23 04:38:57 PM PDT 24
Finished	Apr 23 04:39:17 PM PDT 24
Peak memory	562748 kb
Host	smart-2fa63286-5aeb-4f62-8fe4-25ba5eee1371
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845694830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr .845694830
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_error_random.449972202
Short name	T1736
Test name
Test status
Simulation time	56872104 ps
CPU time	8 seconds
Started	Apr 23 04:38:53 PM PDT 24
Finished	Apr 23 04:39:01 PM PDT 24
Peak memory	562668 kb
Host	smart-a0a0bafd-57c5-442b-b0ac-bb851eb075ca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449972202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.449972202
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_random.720876616
Short name	T1962
Test name
Test status
Simulation time	1604019254 ps
CPU time	60.73 seconds
Started	Apr 23 04:38:47 PM PDT 24
Finished	Apr 23 04:39:48 PM PDT 24
Peak memory	562728 kb
Host	smart-53ac1d90-9269-4d7d-948b-11e069e63d12
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720876616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.720876616
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_random_large_delays.3486702753
Short name	T590
Test name
Test status
Simulation time	102043009499 ps
CPU time	1235.86 seconds
Started	Apr 23 04:38:51 PM PDT 24
Finished	Apr 23 04:59:28 PM PDT 24
Peak memory	562816 kb
Host	smart-e599084c-67e4-4b0f-a244-3b27d6364494
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486702753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3486702753
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.4288625769
Short name	T1622
Test name
Test status
Simulation time	62391623671 ps
CPU time	1193.53 seconds
Started	Apr 23 04:38:51 PM PDT 24
Finished	Apr 23 04:58:45 PM PDT 24
Peak memory	562808 kb
Host	smart-c0cd40fa-aae9-4f7f-a60d-f878944564c8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288625769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4288625769
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.2107415032
Short name	T2136
Test name
Test status
Simulation time	451450996 ps
CPU time	38.93 seconds
Started	Apr 23 04:38:50 PM PDT 24
Finished	Apr 23 04:39:30 PM PDT 24
Peak memory	562708 kb
Host	smart-47a7929e-deb8-4cb0-b9b5-92736d84c6a3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107415032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.2107415032
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_same_source.972924961
Short name	T1314
Test name
Test status
Simulation time	498882575 ps
CPU time	18.05 seconds
Started	Apr 23 04:38:57 PM PDT 24
Finished	Apr 23 04:39:15 PM PDT 24
Peak memory	562700 kb
Host	smart-fb046b71-7c63-4f99-bb0f-e3b81dd1d728
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972924961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.972924961
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke.2769404364
Short name	T1727
Test name
Test status
Simulation time	231427088 ps
CPU time	10.33 seconds
Started	Apr 23 04:38:48 PM PDT 24
Finished	Apr 23 04:38:59 PM PDT 24
Peak memory	562732 kb
Host	smart-512d4fb7-0444-4c29-8f4f-d1057c16720d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769404364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2769404364
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1997180687
Short name	T1305
Test name
Test status
Simulation time	6916952673 ps
CPU time	78.54 seconds
Started	Apr 23 04:38:48 PM PDT 24
Finished	Apr 23 04:40:07 PM PDT 24
Peak memory	562732 kb
Host	smart-6fa77fa8-03a9-42cb-8171-7492f1c7a372
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997180687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1997180687
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.44091717
Short name	T2517
Test name
Test status
Simulation time	5385575245 ps
CPU time	93.93 seconds
Started	Apr 23 04:38:49 PM PDT 24
Finished	Apr 23 04:40:24 PM PDT 24
Peak memory	562724 kb
Host	smart-216cbd84-7a50-4fdf-9dd3-2629ff234753
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44091717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.44091717
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.3897978606
Short name	T564
Test name
Test status
Simulation time	57039868 ps
CPU time	7.87 seconds
Started	Apr 23 04:38:49 PM PDT 24
Finished	Apr 23 04:38:58 PM PDT 24
Peak memory	562692 kb
Host	smart-5b36fa2e-8640-4ea0-8992-7c2b81eb4033
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897978606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.3897978606
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all.2689275611
Short name	T1883
Test name
Test status
Simulation time	12372850976 ps
CPU time	486.93 seconds
Started	Apr 23 04:38:56 PM PDT 24
Finished	Apr 23 04:47:03 PM PDT 24
Peak memory	563960 kb
Host	smart-92f84044-082e-4cc2-aa06-dacf3c1c31ba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689275611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2689275611
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1379156992
Short name	T2137
Test name
Test status
Simulation time	812081966 ps
CPU time	83.58 seconds
Started	Apr 23 04:38:58 PM PDT 24
Finished	Apr 23 04:40:22 PM PDT 24
Peak memory	562792 kb
Host	smart-3a79863f-e4c5-46d9-b668-dfd07725d42c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379156992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1379156992
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2714117527
Short name	T2051
Test name
Test status
Simulation time	267307273 ps
CPU time	92.89 seconds
Started	Apr 23 04:38:59 PM PDT 24
Finished	Apr 23 04:40:32 PM PDT 24
Peak memory	563944 kb
Host	smart-a50bb8b1-3c29-4607-888e-09a371bccd0a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714117527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.2714117527
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2682874163
Short name	T1993
Test name
Test status
Simulation time	75169659 ps
CPU time	32.02 seconds
Started	Apr 23 04:38:57 PM PDT 24
Finished	Apr 23 04:39:29 PM PDT 24
Peak memory	562832 kb
Host	smart-e73d4812-d9db-44a9-bb40-2b65a09704e1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682874163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.2682874163
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3156061819
Short name	T2601
Test name
Test status
Simulation time	517723836 ps
CPU time	26.5 seconds
Started	Apr 23 04:38:56 PM PDT 24
Finished	Apr 23 04:39:23 PM PDT 24
Peak memory	562808 kb
Host	smart-c640b464-7ea8-4bcb-b422-f45ac60f0552
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156061819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3156061819
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/26.chip_tl_errors.815968535
Short name	T528
Test name
Test status
Simulation time	4209647896 ps
CPU time	294.87 seconds
Started	Apr 23 04:38:56 PM PDT 24
Finished	Apr 23 04:43:51 PM PDT 24
Peak memory	593312 kb
Host	smart-daee063d-3f72-466a-a9c0-9a88962d8303
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815968535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.815968535
Directory	/workspace/26.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_access_same_device.3167996785
Short name	T1866
Test name
Test status
Simulation time	3311769296 ps
CPU time	135.84 seconds
Started	Apr 23 04:39:05 PM PDT 24
Finished	Apr 23 04:41:21 PM PDT 24
Peak memory	562864 kb
Host	smart-683fbca8-2dcf-486e-a3cc-69e7373b8256
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167996785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .3167996785
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3647628668
Short name	T2692
Test name
Test status
Simulation time	104710346906 ps
CPU time	1866.46 seconds
Started	Apr 23 04:39:07 PM PDT 24
Finished	Apr 23 05:10:14 PM PDT 24
Peak memory	562872 kb
Host	smart-f5cb8e60-5df4-4220-ad09-14d706b9bd1f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647628668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.3647628668
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1088908238
Short name	T1329
Test name
Test status
Simulation time	1001298299 ps
CPU time	43.35 seconds
Started	Apr 23 04:39:08 PM PDT 24
Finished	Apr 23 04:39:52 PM PDT 24
Peak memory	562676 kb
Host	smart-16d2b844-9bcb-46b0-9084-1550100d67c5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088908238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.1088908238
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_error_random.623284262
Short name	T2015
Test name
Test status
Simulation time	351705947 ps
CPU time	16.14 seconds
Started	Apr 23 04:39:08 PM PDT 24
Finished	Apr 23 04:39:25 PM PDT 24
Peak memory	562684 kb
Host	smart-a13bf83f-d626-4ded-86a6-3e2b1760cb69
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623284262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.623284262
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_random.2544298635
Short name	T1588
Test name
Test status
Simulation time	260469252 ps
CPU time	27.06 seconds
Started	Apr 23 04:39:04 PM PDT 24
Finished	Apr 23 04:39:32 PM PDT 24
Peak memory	562712 kb
Host	smart-7774b599-8d66-4833-b94c-b9f68cc88d86
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544298635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.2544298635
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_random_large_delays.3266654580
Short name	T2406
Test name
Test status
Simulation time	102512758816 ps
CPU time	1217.49 seconds
Started	Apr 23 04:39:03 PM PDT 24
Finished	Apr 23 04:59:21 PM PDT 24
Peak memory	562760 kb
Host	smart-6e2be86a-5c43-4613-8934-0c3334aac6a0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266654580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3266654580
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1105939460
Short name	T1480
Test name
Test status
Simulation time	69423464080 ps
CPU time	1227.34 seconds
Started	Apr 23 04:39:07 PM PDT 24
Finished	Apr 23 04:59:35 PM PDT 24
Peak memory	562824 kb
Host	smart-421d8b8e-0174-42a1-93e7-64488090b1e3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105939460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1105939460
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.313407875
Short name	T1678
Test name
Test status
Simulation time	543316985 ps
CPU time	50.97 seconds
Started	Apr 23 04:39:03 PM PDT 24
Finished	Apr 23 04:39:55 PM PDT 24
Peak memory	562740 kb
Host	smart-5f11429a-ade8-46e1-b494-7b179430ab19
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313407875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_dela ys.313407875
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_same_source.562543079
Short name	T1709
Test name
Test status
Simulation time	586376737 ps
CPU time	50.74 seconds
Started	Apr 23 04:39:07 PM PDT 24
Finished	Apr 23 04:39:58 PM PDT 24
Peak memory	562736 kb
Host	smart-27605f28-8ce6-45bc-b4bd-efa4f4fc7e27
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562543079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.562543079
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke.3726446509
Short name	T1897
Test name
Test status
Simulation time	185113941 ps
CPU time	9.39 seconds
Started	Apr 23 04:39:00 PM PDT 24
Finished	Apr 23 04:39:09 PM PDT 24
Peak memory	562704 kb
Host	smart-eca847f0-3271-43d8-ae10-c17a9f53c60e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726446509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3726446509
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.854219093
Short name	T1892
Test name
Test status
Simulation time	10112015899 ps
CPU time	113.9 seconds
Started	Apr 23 04:39:02 PM PDT 24
Finished	Apr 23 04:40:56 PM PDT 24
Peak memory	562744 kb
Host	smart-4ac565e1-4daf-4542-bf55-0d8128bf5e94
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854219093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.854219093
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.4162353481
Short name	T1936
Test name
Test status
Simulation time	5031628534 ps
CPU time	97.36 seconds
Started	Apr 23 04:39:03 PM PDT 24
Finished	Apr 23 04:40:41 PM PDT 24
Peak memory	562796 kb
Host	smart-4d1cc1e1-78b2-4600-93a3-71e8f7d224eb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162353481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.4162353481
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1024756468
Short name	T1607
Test name
Test status
Simulation time	43267827 ps
CPU time	6.61 seconds
Started	Apr 23 04:39:03 PM PDT 24
Finished	Apr 23 04:39:10 PM PDT 24
Peak memory	562724 kb
Host	smart-1e1330eb-f69a-43f5-824b-8408ca2a2cab
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024756468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.1024756468
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all.3573328023
Short name	T2220
Test name
Test status
Simulation time	7991604487 ps
CPU time	274.35 seconds
Started	Apr 23 04:39:12 PM PDT 24
Finished	Apr 23 04:43:46 PM PDT 24
Peak memory	563560 kb
Host	smart-4c36eb87-008a-4dae-8872-9aa13304b587
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573328023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3573328023
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.1863146429
Short name	T1286
Test name
Test status
Simulation time	2032952008 ps
CPU time	86.99 seconds
Started	Apr 23 04:39:08 PM PDT 24
Finished	Apr 23 04:40:36 PM PDT 24
Peak memory	562760 kb
Host	smart-8fb117c6-bd20-4967-a7b2-989276bed76f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863146429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1863146429
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2249492652
Short name	T811
Test name
Test status
Simulation time	6919993730 ps
CPU time	431.03 seconds
Started	Apr 23 04:39:10 PM PDT 24
Finished	Apr 23 04:46:21 PM PDT 24
Peak memory	572212 kb
Host	smart-68b40f0b-bd01-468c-a4be-5b3de2b28070
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249492652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2249492652
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2044451382
Short name	T1766
Test name
Test status
Simulation time	321213978 ps
CPU time	120.5 seconds
Started	Apr 23 04:39:09 PM PDT 24
Finished	Apr 23 04:41:10 PM PDT 24
Peak memory	563932 kb
Host	smart-a86dea91-0359-4232-80ae-e9b4b2960d36
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044451382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.2044451382
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2931428535
Short name	T1955
Test name
Test status
Simulation time	140633602 ps
CPU time	17.71 seconds
Started	Apr 23 04:39:07 PM PDT 24
Finished	Apr 23 04:39:25 PM PDT 24
Peak memory	562812 kb
Host	smart-60ec7689-bddf-49ba-b460-e3a393d39a51
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931428535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2931428535
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_access_same_device.2296639489
Short name	T2529
Test name
Test status
Simulation time	1193596531 ps
CPU time	51.44 seconds
Started	Apr 23 04:39:16 PM PDT 24
Finished	Apr 23 04:40:08 PM PDT 24
Peak memory	562680 kb
Host	smart-4b8ef15d-f3a5-45d6-9e63-dfc75ed271b5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296639489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .2296639489
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3173122347
Short name	T2025
Test name
Test status
Simulation time	18860808793 ps
CPU time	375.3 seconds
Started	Apr 23 04:39:18 PM PDT 24
Finished	Apr 23 04:45:33 PM PDT 24
Peak memory	562908 kb
Host	smart-c9a49c22-ecf0-469f-8961-de99c9dd7ee0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173122347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.3173122347
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.3087289547
Short name	T1548
Test name
Test status
Simulation time	55566070 ps
CPU time	8.66 seconds
Started	Apr 23 04:39:17 PM PDT 24
Finished	Apr 23 04:39:26 PM PDT 24
Peak memory	562664 kb
Host	smart-3915588d-0d6a-47eb-8cca-79e581d1f6cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087289547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.3087289547
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_error_random.3611954690
Short name	T2698
Test name
Test status
Simulation time	2463777054 ps
CPU time	95.24 seconds
Started	Apr 23 04:39:18 PM PDT 24
Finished	Apr 23 04:40:53 PM PDT 24
Peak memory	562744 kb
Host	smart-97522b6b-af38-4737-abc2-c598880c5192
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611954690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3611954690
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_random.1866793195
Short name	T1547
Test name
Test status
Simulation time	55326752 ps
CPU time	9.04 seconds
Started	Apr 23 04:39:14 PM PDT 24
Finished	Apr 23 04:39:23 PM PDT 24
Peak memory	562688 kb
Host	smart-c98e84c0-7ee0-4812-ba41-3e3c0262863a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866793195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1866793195
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_random_large_delays.1469223569
Short name	T2397
Test name
Test status
Simulation time	6264989296 ps
CPU time	64.53 seconds
Started	Apr 23 04:39:18 PM PDT 24
Finished	Apr 23 04:40:23 PM PDT 24
Peak memory	562824 kb
Host	smart-6f72485c-fb2b-466f-9791-06ce1492720a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469223569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1469223569
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.43409087
Short name	T1378
Test name
Test status
Simulation time	28429508661 ps
CPU time	540.17 seconds
Started	Apr 23 04:39:15 PM PDT 24
Finished	Apr 23 04:48:15 PM PDT 24
Peak memory	562780 kb
Host	smart-f8cd2b6b-47ee-47a6-9165-c4bfc125a272
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43409087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.43409087
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.703569451
Short name	T2205
Test name
Test status
Simulation time	162357506 ps
CPU time	16.56 seconds
Started	Apr 23 04:39:13 PM PDT 24
Finished	Apr 23 04:39:30 PM PDT 24
Peak memory	562720 kb
Host	smart-3b4b31cf-83b9-4b7e-bb45-0fbe03ccfcb5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703569451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_dela ys.703569451
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_same_source.1110650557
Short name	T2206
Test name
Test status
Simulation time	183656017 ps
CPU time	16.84 seconds
Started	Apr 23 04:39:15 PM PDT 24
Finished	Apr 23 04:39:32 PM PDT 24
Peak memory	562716 kb
Host	smart-8de68958-0db7-4bcd-971e-99641225463b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110650557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1110650557
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke.2008156144
Short name	T1794
Test name
Test status
Simulation time	55769441 ps
CPU time	7.57 seconds
Started	Apr 23 04:39:13 PM PDT 24
Finished	Apr 23 04:39:21 PM PDT 24
Peak memory	562692 kb
Host	smart-00600fea-8064-48b1-b33f-71de32a67e0a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008156144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2008156144
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.1112476941
Short name	T2410
Test name
Test status
Simulation time	7877057028 ps
CPU time	84.59 seconds
Started	Apr 23 04:39:12 PM PDT 24
Finished	Apr 23 04:40:37 PM PDT 24
Peak memory	562788 kb
Host	smart-4b5a0cf4-47e7-4d8a-96cf-2ffcf11eeb84
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112476941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1112476941
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2056377614
Short name	T2473
Test name
Test status
Simulation time	5071495501 ps
CPU time	89.37 seconds
Started	Apr 23 04:39:12 PM PDT 24
Finished	Apr 23 04:40:42 PM PDT 24
Peak memory	562732 kb
Host	smart-80f0cfba-45c3-4054-94e7-401ee36f3c9c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056377614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2056377614
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3737146351
Short name	T2382
Test name
Test status
Simulation time	39152468 ps
CPU time	5.99 seconds
Started	Apr 23 04:39:11 PM PDT 24
Finished	Apr 23 04:39:18 PM PDT 24
Peak memory	562700 kb
Host	smart-a813f61d-fceb-493a-9d5a-22051128c1ea
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737146351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.3737146351
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all.3169329047
Short name	T1862
Test name
Test status
Simulation time	15791738597 ps
CPU time	690.77 seconds
Started	Apr 23 04:39:19 PM PDT 24
Finished	Apr 23 04:50:50 PM PDT 24
Peak memory	563596 kb
Host	smart-1d4bc83e-0b9d-4ade-b493-af1caf1018ad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169329047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3169329047
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.4167029361
Short name	T2090
Test name
Test status
Simulation time	629279555 ps
CPU time	61.24 seconds
Started	Apr 23 04:39:23 PM PDT 24
Finished	Apr 23 04:40:25 PM PDT 24
Peak memory	562728 kb
Host	smart-2748519b-83f3-4f24-9df3-a236255078d5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167029361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.4167029361
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.212564107
Short name	T2345
Test name
Test status
Simulation time	1371073997 ps
CPU time	146.4 seconds
Started	Apr 23 04:39:19 PM PDT 24
Finished	Apr 23 04:41:46 PM PDT 24
Peak memory	572164 kb
Host	smart-9acc1408-6d95-49a7-9764-d1f533b60a37
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212564107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_ with_rand_reset.212564107
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.525553185
Short name	T2308
Test name
Test status
Simulation time	193661053 ps
CPU time	66.37 seconds
Started	Apr 23 04:39:19 PM PDT 24
Finished	Apr 23 04:40:26 PM PDT 24
Peak memory	563924 kb
Host	smart-083f8726-8902-4393-af52-b059f0221291
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525553185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_reset_error.525553185
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.1258983451
Short name	T1275
Test name
Test status
Simulation time	414121074 ps
CPU time	21.76 seconds
Started	Apr 23 04:39:19 PM PDT 24
Finished	Apr 23 04:39:41 PM PDT 24
Peak memory	562812 kb
Host	smart-c49f34dc-a5e3-4a7a-82e8-e914b683a53a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258983451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1258983451
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/28.chip_tl_errors.2567823511
Short name	T1387
Test name
Test status
Simulation time	2750163110 ps
CPU time	92.88 seconds
Started	Apr 23 04:39:19 PM PDT 24
Finished	Apr 23 04:40:52 PM PDT 24
Peak memory	585136 kb
Host	smart-f3067ecf-a64b-4c2e-9603-6be27f4faa15
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567823511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2567823511
Directory	/workspace/28.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_access_same_device.3028632671
Short name	T1910
Test name
Test status
Simulation time	934164830 ps
CPU time	43.79 seconds
Started	Apr 23 04:39:24 PM PDT 24
Finished	Apr 23 04:40:08 PM PDT 24
Peak memory	562744 kb
Host	smart-d11c6a00-7c5a-4313-9740-4d79d4f7eaed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028632671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .3028632671
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3662675013
Short name	T772
Test name
Test status
Simulation time	140158350555 ps
CPU time	2447.36 seconds
Started	Apr 23 04:39:27 PM PDT 24
Finished	Apr 23 05:20:15 PM PDT 24
Peak memory	562896 kb
Host	smart-3ed1831b-ddcc-43b0-b3b3-d514177c5d6d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662675013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.3662675013
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.253016580
Short name	T1771
Test name
Test status
Simulation time	241467195 ps
CPU time	13.99 seconds
Started	Apr 23 04:39:25 PM PDT 24
Finished	Apr 23 04:39:40 PM PDT 24
Peak memory	562680 kb
Host	smart-b53e8274-7f0f-45ee-8727-e7ba1cb31f0c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253016580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr .253016580
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_error_random.2388205958
Short name	T2164
Test name
Test status
Simulation time	293946780 ps
CPU time	13.43 seconds
Started	Apr 23 04:39:31 PM PDT 24
Finished	Apr 23 04:39:45 PM PDT 24
Peak memory	562700 kb
Host	smart-a90b8a36-ff0f-4101-9428-6b8e6b939776
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388205958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2388205958
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_random.1117176596
Short name	T1498
Test name
Test status
Simulation time	1911617792 ps
CPU time	63.35 seconds
Started	Apr 23 04:39:21 PM PDT 24
Finished	Apr 23 04:40:24 PM PDT 24
Peak memory	562764 kb
Host	smart-a0052624-1d92-4c3e-b2f9-af873cee64e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117176596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1117176596
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_random_large_delays.1909583240
Short name	T2144
Test name
Test status
Simulation time	17213242881 ps
CPU time	174.75 seconds
Started	Apr 23 04:39:23 PM PDT 24
Finished	Apr 23 04:42:18 PM PDT 24
Peak memory	562740 kb
Host	smart-1d942881-1b86-4434-816c-accbd6189734
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909583240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1909583240
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3308575727
Short name	T1748
Test name
Test status
Simulation time	10302658593 ps
CPU time	183.01 seconds
Started	Apr 23 04:39:24 PM PDT 24
Finished	Apr 23 04:42:27 PM PDT 24
Peak memory	562808 kb
Host	smart-d7c6978c-335d-4505-b77f-8ac3c4f19683
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308575727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3308575727
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.4123522085
Short name	T2465
Test name
Test status
Simulation time	279528442 ps
CPU time	31.41 seconds
Started	Apr 23 04:39:25 PM PDT 24
Finished	Apr 23 04:39:56 PM PDT 24
Peak memory	562716 kb
Host	smart-17a45407-9b38-4335-a7ae-72f296392987
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123522085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.4123522085
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_same_source.2270307260
Short name	T2047
Test name
Test status
Simulation time	241510661 ps
CPU time	21.8 seconds
Started	Apr 23 04:39:26 PM PDT 24
Finished	Apr 23 04:39:48 PM PDT 24
Peak memory	562752 kb
Host	smart-1460fbc0-3602-433c-a39d-32903c71f4ff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270307260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2270307260
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke.3761338001
Short name	T1740
Test name
Test status
Simulation time	47042311 ps
CPU time	5.82 seconds
Started	Apr 23 04:39:18 PM PDT 24
Finished	Apr 23 04:39:24 PM PDT 24
Peak memory	562628 kb
Host	smart-a67b315a-db82-422d-82d3-6e2649de6b0c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761338001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3761338001
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.2940135432
Short name	T2281
Test name
Test status
Simulation time	5251907684 ps
CPU time	59.84 seconds
Started	Apr 23 04:39:24 PM PDT 24
Finished	Apr 23 04:40:24 PM PDT 24
Peak memory	562776 kb
Host	smart-cd139d0a-6c53-47c7-ae77-fee282f4c8bd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940135432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2940135432
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3747071134
Short name	T1697
Test name
Test status
Simulation time	4119222307 ps
CPU time	75.42 seconds
Started	Apr 23 04:39:20 PM PDT 24
Finished	Apr 23 04:40:36 PM PDT 24
Peak memory	562784 kb
Host	smart-87769998-1eae-4aa8-a57d-4bad456ab7c1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747071134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3747071134
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.884703518
Short name	T1403
Test name
Test status
Simulation time	53438355 ps
CPU time	6.92 seconds
Started	Apr 23 04:39:23 PM PDT 24
Finished	Apr 23 04:39:30 PM PDT 24
Peak memory	562728 kb
Host	smart-45ae45d9-8a41-4aa1-af7e-24093f5e8b18
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884703518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays .884703518
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all.2092380785
Short name	T576
Test name
Test status
Simulation time	4074981553 ps
CPU time	186.35 seconds
Started	Apr 23 04:39:27 PM PDT 24
Finished	Apr 23 04:42:34 PM PDT 24
Peak memory	563964 kb
Host	smart-351264cb-cb27-47f2-abe6-927ea267340d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092380785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2092380785
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2183264501
Short name	T2690
Test name
Test status
Simulation time	6646500839 ps
CPU time	262.35 seconds
Started	Apr 23 04:39:25 PM PDT 24
Finished	Apr 23 04:43:48 PM PDT 24
Peak memory	562936 kb
Host	smart-84ef4156-5e80-4d10-a3d0-be702bde1e66
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183264501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2183264501
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3577381227
Short name	T2310
Test name
Test status
Simulation time	691830282 ps
CPU time	197.91 seconds
Started	Apr 23 04:39:30 PM PDT 24
Finished	Apr 23 04:42:48 PM PDT 24
Peak memory	572136 kb
Host	smart-e9fd5726-8d0c-4481-93d1-0928c062a32e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577381227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.3577381227
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3599397016
Short name	T2000
Test name
Test status
Simulation time	992540106 ps
CPU time	88.15 seconds
Started	Apr 23 04:39:34 PM PDT 24
Finished	Apr 23 04:41:02 PM PDT 24
Peak memory	563560 kb
Host	smart-4b0d6a94-6308-4f5e-82f5-947249bf1e8b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599397016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.3599397016
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.3956702624
Short name	T2277
Test name
Test status
Simulation time	422622989 ps
CPU time	21.32 seconds
Started	Apr 23 04:39:28 PM PDT 24
Finished	Apr 23 04:39:49 PM PDT 24
Peak memory	562720 kb
Host	smart-9468b108-e491-47cf-8ce3-1fd462a28f38
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956702624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3956702624
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/29.chip_tl_errors.2234168063
Short name	T532
Test name
Test status
Simulation time	2966595156 ps
CPU time	166.04 seconds
Started	Apr 23 04:39:35 PM PDT 24
Finished	Apr 23 04:42:22 PM PDT 24
Peak memory	585972 kb
Host	smart-dc18cc36-1ea6-49da-8d9c-9657941f6079
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234168063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.2234168063
Directory	/workspace/29.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_access_same_device.4182347425
Short name	T2030
Test name
Test status
Simulation time	2870037549 ps
CPU time	134.08 seconds
Started	Apr 23 04:39:37 PM PDT 24
Finished	Apr 23 04:41:52 PM PDT 24
Peak memory	562820 kb
Host	smart-210b119b-5a6e-4b2f-b762-be8c0a588eaa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182347425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .4182347425
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3293296686
Short name	T2402
Test name
Test status
Simulation time	121116455113 ps
CPU time	2244.75 seconds
Started	Apr 23 04:39:36 PM PDT 24
Finished	Apr 23 05:17:01 PM PDT 24
Peak memory	562868 kb
Host	smart-b1c1a6d9-3773-4a90-a4bc-0649c99ec536
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293296686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.3293296686
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2827651637
Short name	T2543
Test name
Test status
Simulation time	201153273 ps
CPU time	12.43 seconds
Started	Apr 23 04:39:37 PM PDT 24
Finished	Apr 23 04:39:49 PM PDT 24
Peak memory	562656 kb
Host	smart-42c95897-81d1-4768-86ea-1f0ba4a28619
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827651637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.2827651637
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_error_random.2211312994
Short name	T1851
Test name
Test status
Simulation time	2192015893 ps
CPU time	80.62 seconds
Started	Apr 23 04:39:38 PM PDT 24
Finished	Apr 23 04:40:58 PM PDT 24
Peak memory	562792 kb
Host	smart-e888195d-4083-4e3e-8923-5b8ee892c560
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211312994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2211312994
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_random.3192207782
Short name	T1729
Test name
Test status
Simulation time	1877437030 ps
CPU time	74.66 seconds
Started	Apr 23 04:39:35 PM PDT 24
Finished	Apr 23 04:40:50 PM PDT 24
Peak memory	562708 kb
Host	smart-d910b619-3d47-44a0-b8dd-a5cbf859ab17
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192207782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.3192207782
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_random_large_delays.433757234
Short name	T2776
Test name
Test status
Simulation time	15404547641 ps
CPU time	173.98 seconds
Started	Apr 23 04:39:36 PM PDT 24
Finished	Apr 23 04:42:30 PM PDT 24
Peak memory	562828 kb
Host	smart-a40ca3fd-0632-463d-95b5-f37728d08a70
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433757234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.433757234
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.4214787899
Short name	T553
Test name
Test status
Simulation time	55621330528 ps
CPU time	1023.45 seconds
Started	Apr 23 04:39:42 PM PDT 24
Finished	Apr 23 04:56:46 PM PDT 24
Peak memory	562720 kb
Host	smart-33d8e0b1-568d-47f3-9551-9c137917b269
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214787899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.4214787899
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.717912122
Short name	T1803
Test name
Test status
Simulation time	159709425 ps
CPU time	15.75 seconds
Started	Apr 23 04:39:43 PM PDT 24
Finished	Apr 23 04:39:59 PM PDT 24
Peak memory	562628 kb
Host	smart-82939ad4-29a8-40ee-8b4a-004c1c9080da
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717912122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_dela ys.717912122
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_same_source.4014147828
Short name	T548
Test name
Test status
Simulation time	1534776364 ps
CPU time	51.13 seconds
Started	Apr 23 04:39:41 PM PDT 24
Finished	Apr 23 04:40:33 PM PDT 24
Peak memory	562696 kb
Host	smart-8e02e200-2947-45d0-8b27-e1f575bd6094
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014147828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4014147828
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke.1300753580
Short name	T1973
Test name
Test status
Simulation time	189215749 ps
CPU time	9.34 seconds
Started	Apr 23 04:39:40 PM PDT 24
Finished	Apr 23 04:39:50 PM PDT 24
Peak memory	562680 kb
Host	smart-2002d4eb-2c03-4244-99bf-43d21a7b2ab2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300753580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1300753580
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1152382997
Short name	T2418
Test name
Test status
Simulation time	7967874691 ps
CPU time	82.06 seconds
Started	Apr 23 04:39:35 PM PDT 24
Finished	Apr 23 04:40:57 PM PDT 24
Peak memory	562792 kb
Host	smart-f80f5e6f-458a-4642-a54b-66fed0c7ff60
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152382997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1152382997
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2029671330
Short name	T2089
Test name
Test status
Simulation time	6234408200 ps
CPU time	110.54 seconds
Started	Apr 23 04:39:40 PM PDT 24
Finished	Apr 23 04:41:31 PM PDT 24
Peak memory	562768 kb
Host	smart-7e83adcf-a6ab-4708-9d5e-139e2c3debec
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029671330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2029671330
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1820493745
Short name	T1260
Test name
Test status
Simulation time	41126464 ps
CPU time	6.52 seconds
Started	Apr 23 04:39:34 PM PDT 24
Finished	Apr 23 04:39:41 PM PDT 24
Peak memory	562688 kb
Host	smart-3cd2f2fc-6b25-4898-a4a2-962c85985a71
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820493745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.1820493745
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all.1132741666
Short name	T472
Test name
Test status
Simulation time	11297641879 ps
CPU time	485.34 seconds
Started	Apr 23 04:39:41 PM PDT 24
Finished	Apr 23 04:47:46 PM PDT 24
Peak memory	563968 kb
Host	smart-5665365e-56bb-4a08-8a04-a9f568673a5a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132741666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1132741666
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.2297464720
Short name	T773
Test name
Test status
Simulation time	3431642059 ps
CPU time	316.41 seconds
Started	Apr 23 04:39:39 PM PDT 24
Finished	Apr 23 04:44:56 PM PDT 24
Peak memory	563972 kb
Host	smart-cdb8b93f-a5c9-4048-9987-81c3d6e9fb5b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297464720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2297464720
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2660286963
Short name	T526
Test name
Test status
Simulation time	143532547 ps
CPU time	35.7 seconds
Started	Apr 23 04:39:40 PM PDT 24
Finished	Apr 23 04:40:16 PM PDT 24
Peak memory	563708 kb
Host	smart-f5096272-eb39-4b72-a88c-4c02f0018b63
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660286963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.2660286963
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2006600014
Short name	T1792
Test name
Test status
Simulation time	565416565 ps
CPU time	182.01 seconds
Started	Apr 23 04:39:51 PM PDT 24
Finished	Apr 23 04:42:53 PM PDT 24
Peak memory	572084 kb
Host	smart-297bf84d-8d43-4f09-a4cf-ea3dec747c38
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006600014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.2006600014
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.4033205773
Short name	T1758
Test name
Test status
Simulation time	599682023 ps
CPU time	30.36 seconds
Started	Apr 23 04:39:40 PM PDT 24
Finished	Apr 23 04:40:11 PM PDT 24
Peak memory	562764 kb
Host	smart-8fc0b5e7-e24b-4ce4-9c7f-61e3ed43107f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033205773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.4033205773
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_aliasing.1912129039
Short name	T1987
Test name
Test status
Simulation time	31480442845 ps
CPU time	4594.73 seconds
Started	Apr 23 04:29:27 PM PDT 24
Finished	Apr 23 05:46:02 PM PDT 24
Peak memory	585476 kb
Host	smart-a23b17db-c29e-4d28-bbf3-dec729bdbb4d
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912129039 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.1912129039
Directory	/workspace/3.chip_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.2223865516
Short name	T1967
Test name
Test status
Simulation time	6198363937 ps
CPU time	727.09 seconds
Started	Apr 23 04:29:24 PM PDT 24
Finished	Apr 23 04:41:31 PM PDT 24
Peak memory	585108 kb
Host	smart-f1b8d5b4-0b74-44fd-90d7-0ac50c5d7403
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223865516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.2223865516
Directory	/workspace/3.chip_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2835807311
Short name	T146
Test name
Test status
Simulation time	4653935427 ps
CPU time	186.59 seconds
Started	Apr 23 04:30:10 PM PDT 24
Finished	Apr 23 04:33:17 PM PDT 24
Peak memory	652768 kb
Host	smart-956e3075-527d-419b-b7f3-b22a8796dbac
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835807311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.2835807311
Directory	/workspace/3.chip_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_rw.3899936677
Short name	T1409
Test name
Test status
Simulation time	4230150980 ps
CPU time	393.94 seconds
Started	Apr 23 04:30:21 PM PDT 24
Finished	Apr 23 04:36:55 PM PDT 24
Peak memory	588612 kb
Host	smart-1f847a0e-f420-4829-90df-8f69297ecf9e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899936677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.3899936677
Directory	/workspace/3.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_tl_errors.2670882210
Short name	T536
Test name
Test status
Simulation time	2812009417 ps
CPU time	236.6 seconds
Started	Apr 23 04:29:26 PM PDT 24
Finished	Apr 23 04:33:23 PM PDT 24
Peak memory	600500 kb
Host	smart-c37ba852-3361-409a-ac51-4f53bacda139
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670882210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2670882210
Directory	/workspace/3.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_access_same_device.1650744655
Short name	T2733
Test name
Test status
Simulation time	684902994 ps
CPU time	62.08 seconds
Started	Apr 23 04:30:01 PM PDT 24
Finished	Apr 23 04:31:04 PM PDT 24
Peak memory	562748 kb
Host	smart-3ad8247f-66a1-4d72-a878-29c86e264c98
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650744655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 1650744655
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2384087336
Short name	T1462
Test name
Test status
Simulation time	43289981236 ps
CPU time	760.8 seconds
Started	Apr 23 04:29:59 PM PDT 24
Finished	Apr 23 04:42:40 PM PDT 24
Peak memory	562816 kb
Host	smart-373c49b7-d458-4ec8-ac29-560d0681ed4d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384087336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.2384087336
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1725940650
Short name	T2648
Test name
Test status
Simulation time	48842215 ps
CPU time	9.36 seconds
Started	Apr 23 04:30:05 PM PDT 24
Finished	Apr 23 04:30:15 PM PDT 24
Peak memory	562736 kb
Host	smart-da04151a-5988-4b99-baee-6a36c86d21bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725940650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .1725940650
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_error_random.753466873
Short name	T2649
Test name
Test status
Simulation time	535262069 ps
CPU time	51.65 seconds
Started	Apr 23 04:30:02 PM PDT 24
Finished	Apr 23 04:30:54 PM PDT 24
Peak memory	562692 kb
Host	smart-aaa7a1cc-c19e-48db-b4a2-46759324af70
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753466873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.753466873
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_random.427010392
Short name	T1675
Test name
Test status
Simulation time	2167249078 ps
CPU time	101.68 seconds
Started	Apr 23 04:29:42 PM PDT 24
Finished	Apr 23 04:31:24 PM PDT 24
Peak memory	562780 kb
Host	smart-dfa15bc4-128f-4b3f-8af3-ae22c8679d21
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427010392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.427010392
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_random_large_delays.3707784028
Short name	T2589
Test name
Test status
Simulation time	56421260433 ps
CPU time	678.39 seconds
Started	Apr 23 04:29:48 PM PDT 24
Finished	Apr 23 04:41:07 PM PDT 24
Peak memory	562772 kb
Host	smart-64c3462d-ff2f-4bd0-9458-3cd2eac1df91
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707784028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3707784028
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.4153095501
Short name	T2491
Test name
Test status
Simulation time	66047116871 ps
CPU time	1115.15 seconds
Started	Apr 23 04:29:55 PM PDT 24
Finished	Apr 23 04:48:31 PM PDT 24
Peak memory	562852 kb
Host	smart-2037952f-fc07-4312-8507-5f306a6b350f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153095501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4153095501
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.2356314558
Short name	T2309
Test name
Test status
Simulation time	554235702 ps
CPU time	59.66 seconds
Started	Apr 23 04:29:48 PM PDT 24
Finished	Apr 23 04:30:48 PM PDT 24
Peak memory	562732 kb
Host	smart-3051aacc-3215-408a-82c4-664586454cf4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356314558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.2356314558
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_same_source.2363757764
Short name	T2200
Test name
Test status
Simulation time	73096683 ps
CPU time	8.21 seconds
Started	Apr 23 04:30:01 PM PDT 24
Finished	Apr 23 04:30:09 PM PDT 24
Peak memory	562744 kb
Host	smart-1a5c54b6-e4fd-4305-8d59-9eab31091a7c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363757764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2363757764
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke.2854805810
Short name	T2151
Test name
Test status
Simulation time	46460000 ps
CPU time	6.87 seconds
Started	Apr 23 04:29:37 PM PDT 24
Finished	Apr 23 04:29:44 PM PDT 24
Peak memory	562732 kb
Host	smart-2681d3f1-e1bb-4d33-8664-52d21959b6b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854805810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2854805810
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.4033996869
Short name	T2237
Test name
Test status
Simulation time	10163423173 ps
CPU time	115.78 seconds
Started	Apr 23 04:29:44 PM PDT 24
Finished	Apr 23 04:31:40 PM PDT 24
Peak memory	562808 kb
Host	smart-5db1780c-0626-4534-84f2-7a3808b2f5aa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033996869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4033996869
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3639018441
Short name	T1599
Test name
Test status
Simulation time	5743128541 ps
CPU time	110.33 seconds
Started	Apr 23 04:29:46 PM PDT 24
Finished	Apr 23 04:31:37 PM PDT 24
Peak memory	562744 kb
Host	smart-fa7ffb43-b5dc-4d5c-a5c0-4b249917c5b1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639018441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3639018441
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.791767208
Short name	T1563
Test name
Test status
Simulation time	47696160 ps
CPU time	6.47 seconds
Started	Apr 23 04:29:35 PM PDT 24
Finished	Apr 23 04:29:42 PM PDT 24
Peak memory	562700 kb
Host	smart-b689da2c-9ff5-44e2-b107-e8b96daa9d89
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791767208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays. 791767208
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all.392987842
Short name	T2114
Test name
Test status
Simulation time	2151531126 ps
CPU time	216.76 seconds
Started	Apr 23 04:30:08 PM PDT 24
Finished	Apr 23 04:33:46 PM PDT 24
Peak memory	564012 kb
Host	smart-07b0feda-fc3f-4dc5-940d-8f651d4791ca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392987842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.392987842
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.182407174
Short name	T2228
Test name
Test status
Simulation time	1729319561 ps
CPU time	64.65 seconds
Started	Apr 23 04:30:15 PM PDT 24
Finished	Apr 23 04:31:20 PM PDT 24
Peak memory	562748 kb
Host	smart-939ead96-dd72-41f7-b324-d84864876be9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182407174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.182407174
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1659807415
Short name	T2626
Test name
Test status
Simulation time	2200898140 ps
CPU time	356.61 seconds
Started	Apr 23 04:30:07 PM PDT 24
Finished	Apr 23 04:36:04 PM PDT 24
Peak memory	572144 kb
Host	smart-3372cb1b-3799-45f9-afb8-8bfc2b469340
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659807415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.1659807415
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1892417471
Short name	T1411
Test name
Test status
Simulation time	69845425 ps
CPU time	48.4 seconds
Started	Apr 23 04:30:12 PM PDT 24
Finished	Apr 23 04:31:01 PM PDT 24
Peak memory	563264 kb
Host	smart-4c6f8982-ee1b-40a8-9cc3-cd96f49f8185
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892417471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.1892417471
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.3794449962
Short name	T1635
Test name
Test status
Simulation time	198462646 ps
CPU time	12.67 seconds
Started	Apr 23 04:30:05 PM PDT 24
Finished	Apr 23 04:30:18 PM PDT 24
Peak memory	562764 kb
Host	smart-5fe423eb-e922-4cc3-b3fd-49b060b185c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794449962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3794449962
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_access_same_device.1973357974
Short name	T2743
Test name
Test status
Simulation time	610472853 ps
CPU time	64.46 seconds
Started	Apr 23 04:39:45 PM PDT 24
Finished	Apr 23 04:40:50 PM PDT 24
Peak memory	562784 kb
Host	smart-3b83871a-99da-4789-8240-dd21cff0d10a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973357974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .1973357974
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2359755311
Short name	T1613
Test name
Test status
Simulation time	36055377401 ps
CPU time	622.65 seconds
Started	Apr 23 04:39:50 PM PDT 24
Finished	Apr 23 04:50:13 PM PDT 24
Peak memory	562884 kb
Host	smart-29c8446f-5661-4f37-b30b-b50db26f4abf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359755311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.2359755311
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2576098024
Short name	T2551
Test name
Test status
Simulation time	395263607 ps
CPU time	21.12 seconds
Started	Apr 23 04:39:48 PM PDT 24
Finished	Apr 23 04:40:10 PM PDT 24
Peak memory	562700 kb
Host	smart-dc53c5d7-2eda-4f23-8d0b-a4440130c324
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576098024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.2576098024
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_error_random.945363814
Short name	T1238
Test name
Test status
Simulation time	1336179130 ps
CPU time	48.68 seconds
Started	Apr 23 04:39:56 PM PDT 24
Finished	Apr 23 04:40:45 PM PDT 24
Peak memory	562732 kb
Host	smart-9992837b-d471-4eb9-9934-cb4d0c2aed04
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945363814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.945363814
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_random.124328332
Short name	T2679
Test name
Test status
Simulation time	1166779146 ps
CPU time	47.09 seconds
Started	Apr 23 04:39:46 PM PDT 24
Finished	Apr 23 04:40:33 PM PDT 24
Peak memory	562712 kb
Host	smart-6d48ece5-b282-4de9-b471-8be005d1bed3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124328332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.124328332
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_random_large_delays.538563751
Short name	T1488
Test name
Test status
Simulation time	24372574119 ps
CPU time	265.56 seconds
Started	Apr 23 04:39:45 PM PDT 24
Finished	Apr 23 04:44:11 PM PDT 24
Peak memory	562792 kb
Host	smart-0415b61c-cdaa-49e3-9437-ddbd66df2903
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538563751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.538563751
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.3531292583
Short name	T552
Test name
Test status
Simulation time	6427271952 ps
CPU time	111.86 seconds
Started	Apr 23 04:39:48 PM PDT 24
Finished	Apr 23 04:41:40 PM PDT 24
Peak memory	562776 kb
Host	smart-101ad54a-91f0-4d03-9424-50dfddbb2cf0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531292583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3531292583
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.273394280
Short name	T2703
Test name
Test status
Simulation time	33508372 ps
CPU time	6.44 seconds
Started	Apr 23 04:39:44 PM PDT 24
Finished	Apr 23 04:39:51 PM PDT 24
Peak memory	562740 kb
Host	smart-9572cd46-9d17-47b3-ad4b-6d510b99837e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273394280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_dela ys.273394280
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_same_source.855627319
Short name	T2232
Test name
Test status
Simulation time	2185565485 ps
CPU time	74.44 seconds
Started	Apr 23 04:39:52 PM PDT 24
Finished	Apr 23 04:41:07 PM PDT 24
Peak memory	562780 kb
Host	smart-143d62ff-28b7-4e58-9cc4-aad34f2b1cd3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855627319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.855627319
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke.2783068966
Short name	T1842
Test name
Test status
Simulation time	48291430 ps
CPU time	6.96 seconds
Started	Apr 23 04:39:46 PM PDT 24
Finished	Apr 23 04:39:54 PM PDT 24
Peak memory	562652 kb
Host	smart-499ed75c-e583-4404-9eff-316713032e8a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783068966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2783068966
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.2428700231
Short name	T1361
Test name
Test status
Simulation time	7618514003 ps
CPU time	81.49 seconds
Started	Apr 23 04:39:46 PM PDT 24
Finished	Apr 23 04:41:08 PM PDT 24
Peak memory	562792 kb
Host	smart-5ae49ff2-ff41-402c-a5ef-32cc0e17e98c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428700231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2428700231
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.115174117
Short name	T2336
Test name
Test status
Simulation time	3864144866 ps
CPU time	74.49 seconds
Started	Apr 23 04:39:45 PM PDT 24
Finished	Apr 23 04:41:00 PM PDT 24
Peak memory	562728 kb
Host	smart-d74993dd-83fc-4641-b34f-24a294f37f15
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115174117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.115174117
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1044552553
Short name	T1322
Test name
Test status
Simulation time	43886179 ps
CPU time	6.09 seconds
Started	Apr 23 04:39:44 PM PDT 24
Finished	Apr 23 04:39:50 PM PDT 24
Peak memory	562692 kb
Host	smart-d51cb9a9-b9db-4a79-bfa4-71ca0ce8cb9c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044552553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.1044552553
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3115576088
Short name	T2559
Test name
Test status
Simulation time	6575123588 ps
CPU time	275.51 seconds
Started	Apr 23 04:39:58 PM PDT 24
Finished	Apr 23 04:44:34 PM PDT 24
Peak memory	563100 kb
Host	smart-f62ac46b-cb42-4cf9-8f89-a3222535745f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115576088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3115576088
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.645775026
Short name	T810
Test name
Test status
Simulation time	12247407955 ps
CPU time	718.34 seconds
Started	Apr 23 04:39:50 PM PDT 24
Finished	Apr 23 04:51:49 PM PDT 24
Peak memory	572200 kb
Host	smart-2508b4d8-610b-4fd0-9d9b-147023b092cb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645775026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_ with_rand_reset.645775026
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2420918297
Short name	T2313
Test name
Test status
Simulation time	3904351465 ps
CPU time	192.11 seconds
Started	Apr 23 04:39:56 PM PDT 24
Finished	Apr 23 04:43:09 PM PDT 24
Peak memory	563932 kb
Host	smart-c34860c1-d590-4f8b-a14c-cafd78113446
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420918297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.2420918297
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.1198801780
Short name	T2204
Test name
Test status
Simulation time	925596104 ps
CPU time	47.02 seconds
Started	Apr 23 04:39:48 PM PDT 24
Finished	Apr 23 04:40:35 PM PDT 24
Peak memory	562736 kb
Host	smart-f74d4564-b391-46ba-8212-f34b74d14090
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198801780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1198801780
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_access_same_device.2353926339
Short name	T2176
Test name
Test status
Simulation time	2316378338 ps
CPU time	113.48 seconds
Started	Apr 23 04:39:57 PM PDT 24
Finished	Apr 23 04:41:51 PM PDT 24
Peak memory	562916 kb
Host	smart-4b6fb1ed-16c0-458f-8cfa-9f836d66bbef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353926339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .2353926339
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1109343692
Short name	T1431
Test name
Test status
Simulation time	21434365329 ps
CPU time	413.75 seconds
Started	Apr 23 04:39:58 PM PDT 24
Finished	Apr 23 04:46:52 PM PDT 24
Peak memory	562804 kb
Host	smart-d4ab8ec0-9198-4e3b-b203-43c7bb16877b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109343692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.1109343692
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3039709503
Short name	T2596
Test name
Test status
Simulation time	283915452 ps
CPU time	32.55 seconds
Started	Apr 23 04:40:00 PM PDT 24
Finished	Apr 23 04:40:33 PM PDT 24
Peak memory	562716 kb
Host	smart-a193bcf7-ab51-4cac-977d-6efda7c6396b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039709503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3039709503
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_error_random.4120672865
Short name	T2163
Test name
Test status
Simulation time	201972246 ps
CPU time	10.84 seconds
Started	Apr 23 04:39:59 PM PDT 24
Finished	Apr 23 04:40:11 PM PDT 24
Peak memory	562664 kb
Host	smart-272480a8-3d9a-41ca-a6c5-d08adf9d3a19
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120672865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.4120672865
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_random.3788200792
Short name	T1912
Test name
Test status
Simulation time	121252030 ps
CPU time	13.97 seconds
Started	Apr 23 04:39:56 PM PDT 24
Finished	Apr 23 04:40:10 PM PDT 24
Peak memory	562740 kb
Host	smart-1e9e9900-9fc0-4e8e-903c-80db5ae49247
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788200792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.3788200792
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_random_large_delays.224807202
Short name	T1734
Test name
Test status
Simulation time	29744079446 ps
CPU time	327.6 seconds
Started	Apr 23 04:39:59 PM PDT 24
Finished	Apr 23 04:45:27 PM PDT 24
Peak memory	562720 kb
Host	smart-4e2294c0-3197-494a-847a-35ebde0516f4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224807202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.224807202
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.3179673881
Short name	T405
Test name
Test status
Simulation time	60367074828 ps
CPU time	1183.98 seconds
Started	Apr 23 04:39:58 PM PDT 24
Finished	Apr 23 04:59:43 PM PDT 24
Peak memory	562824 kb
Host	smart-9823e7fb-f9d3-4e67-929f-eb1a401d623a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179673881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3179673881
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.537723144
Short name	T605
Test name
Test status
Simulation time	503195691 ps
CPU time	47.9 seconds
Started	Apr 23 04:39:54 PM PDT 24
Finished	Apr 23 04:40:42 PM PDT 24
Peak memory	562748 kb
Host	smart-5ca81d52-0c60-42b5-99c2-513350cd7091
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537723144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_dela ys.537723144
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_same_source.2719699337
Short name	T1624
Test name
Test status
Simulation time	2249417891 ps
CPU time	74.24 seconds
Started	Apr 23 04:39:59 PM PDT 24
Finished	Apr 23 04:41:14 PM PDT 24
Peak memory	562756 kb
Host	smart-2f128828-7e4a-437e-914c-23bd40852365
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719699337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2719699337
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke.3095022379
Short name	T1356
Test name
Test status
Simulation time	260700136 ps
CPU time	11.24 seconds
Started	Apr 23 04:39:53 PM PDT 24
Finished	Apr 23 04:40:05 PM PDT 24
Peak memory	562680 kb
Host	smart-b28222f2-5dab-40a8-830e-ae17c7ab186d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095022379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3095022379
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.3979704385
Short name	T1557
Test name
Test status
Simulation time	9013931430 ps
CPU time	101.87 seconds
Started	Apr 23 04:39:56 PM PDT 24
Finished	Apr 23 04:41:38 PM PDT 24
Peak memory	562776 kb
Host	smart-f3ab199f-cb67-4118-a7a2-652144e0a17d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979704385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3979704385
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2205370622
Short name	T2395
Test name
Test status
Simulation time	5790707743 ps
CPU time	106.39 seconds
Started	Apr 23 04:39:56 PM PDT 24
Finished	Apr 23 04:41:43 PM PDT 24
Peak memory	562780 kb
Host	smart-e9ab411b-9c2e-4c0c-b5c4-0a79471941b0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205370622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2205370622
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.353656630
Short name	T1672
Test name
Test status
Simulation time	53887805 ps
CPU time	6.65 seconds
Started	Apr 23 04:39:56 PM PDT 24
Finished	Apr 23 04:40:03 PM PDT 24
Peak memory	562708 kb
Host	smart-b64f3cf7-8c14-4a46-ac83-7b67917d4581
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353656630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays .353656630
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all.2920048640
Short name	T494
Test name
Test status
Simulation time	6557497032 ps
CPU time	257.06 seconds
Started	Apr 23 04:40:03 PM PDT 24
Finished	Apr 23 04:44:20 PM PDT 24
Peak memory	564012 kb
Host	smart-13780e1d-b1d4-4eea-a73b-9ca7849b8fad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920048640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2920048640
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.2056416072
Short name	T2631
Test name
Test status
Simulation time	11106066168 ps
CPU time	444.98 seconds
Started	Apr 23 04:40:03 PM PDT 24
Finished	Apr 23 04:47:28 PM PDT 24
Peak memory	564028 kb
Host	smart-52779db2-dd3d-4d73-a1ed-373dfa49cf92
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056416072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2056416072
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.923362344
Short name	T1741
Test name
Test status
Simulation time	192572928 ps
CPU time	94.26 seconds
Started	Apr 23 04:40:05 PM PDT 24
Finished	Apr 23 04:41:39 PM PDT 24
Peak memory	563928 kb
Host	smart-2e692db6-9006-4149-8a45-68df0448c572
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923362344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.923362344
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1832653929
Short name	T813
Test name
Test status
Simulation time	277612225 ps
CPU time	171.39 seconds
Started	Apr 23 04:40:03 PM PDT 24
Finished	Apr 23 04:42:55 PM PDT 24
Peak memory	563940 kb
Host	smart-086d9c32-0260-4341-b839-b97b5eade74f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832653929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.1832653929
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.3922271755
Short name	T507
Test name
Test status
Simulation time	380828424 ps
CPU time	20.07 seconds
Started	Apr 23 04:40:00 PM PDT 24
Finished	Apr 23 04:40:20 PM PDT 24
Peak memory	562784 kb
Host	smart-1d9a4205-f992-4db9-93b9-329012ca253c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922271755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3922271755
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_access_same_device.4160980301
Short name	T1506
Test name
Test status
Simulation time	481118164 ps
CPU time	44.16 seconds
Started	Apr 23 04:40:13 PM PDT 24
Finished	Apr 23 04:40:57 PM PDT 24
Peak memory	562760 kb
Host	smart-779809d4-e61c-4b46-8ada-15515cb17de1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160980301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .4160980301
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.584517691
Short name	T798
Test name
Test status
Simulation time	6180964834 ps
CPU time	110.07 seconds
Started	Apr 23 04:40:11 PM PDT 24
Finished	Apr 23 04:42:01 PM PDT 24
Peak memory	562812 kb
Host	smart-5dd3108a-9e17-4d74-bfba-a4b47d4df86d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584517691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_d evice_slow_rsp.584517691
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1285298691
Short name	T1759
Test name
Test status
Simulation time	1365072588 ps
CPU time	53.46 seconds
Started	Apr 23 04:40:13 PM PDT 24
Finished	Apr 23 04:41:06 PM PDT 24
Peak memory	562724 kb
Host	smart-1958448a-d101-400f-acfe-22b92832322d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285298691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.1285298691
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_error_random.1746674054
Short name	T1385
Test name
Test status
Simulation time	1582343173 ps
CPU time	56.63 seconds
Started	Apr 23 04:40:13 PM PDT 24
Finished	Apr 23 04:41:10 PM PDT 24
Peak memory	562664 kb
Host	smart-04e1e7e2-0f4d-4557-a7a2-7654cca5909c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746674054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1746674054
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_random.150564006
Short name	T2611
Test name
Test status
Simulation time	279336355 ps
CPU time	11.11 seconds
Started	Apr 23 04:40:14 PM PDT 24
Finished	Apr 23 04:40:26 PM PDT 24
Peak memory	562740 kb
Host	smart-3cc9bba0-af79-46c6-b0dd-a2b88fab913e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150564006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.150564006
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_random_large_delays.4103873479
Short name	T2338
Test name
Test status
Simulation time	16373171874 ps
CPU time	201.04 seconds
Started	Apr 23 04:40:10 PM PDT 24
Finished	Apr 23 04:43:31 PM PDT 24
Peak memory	562792 kb
Host	smart-6598b147-b418-4591-81ed-fa4ff44820fb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103873479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.4103873479
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.3991076218
Short name	T1670
Test name
Test status
Simulation time	10002303242 ps
CPU time	194.44 seconds
Started	Apr 23 04:40:16 PM PDT 24
Finished	Apr 23 04:43:30 PM PDT 24
Peak memory	562764 kb
Host	smart-b2aade53-4109-45d8-90f1-6652d6c2e6ff
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991076218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3991076218
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.3342570325
Short name	T1995
Test name
Test status
Simulation time	250339279 ps
CPU time	21.83 seconds
Started	Apr 23 04:40:10 PM PDT 24
Finished	Apr 23 04:40:32 PM PDT 24
Peak memory	562728 kb
Host	smart-1dad6736-61e3-42c4-9f99-e8817fb78b82
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342570325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.3342570325
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_same_source.3172537855
Short name	T1447
Test name
Test status
Simulation time	475213377 ps
CPU time	16.97 seconds
Started	Apr 23 04:40:14 PM PDT 24
Finished	Apr 23 04:40:32 PM PDT 24
Peak memory	562744 kb
Host	smart-d24e6270-2bcc-4e1b-a006-ce45a68dacf6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172537855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3172537855
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke.1695901979
Short name	T2229
Test name
Test status
Simulation time	51518113 ps
CPU time	6.53 seconds
Started	Apr 23 04:40:02 PM PDT 24
Finished	Apr 23 04:40:09 PM PDT 24
Peak memory	562692 kb
Host	smart-3e1d6b20-b29d-4d6b-b599-adc198e3de93
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695901979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1695901979
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.4126555329
Short name	T1844
Test name
Test status
Simulation time	7182781038 ps
CPU time	75.67 seconds
Started	Apr 23 04:40:09 PM PDT 24
Finished	Apr 23 04:41:25 PM PDT 24
Peak memory	562760 kb
Host	smart-c8ec8d3d-0d8e-44a2-aaa7-ec5db7890dbe
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126555329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4126555329
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.971609514
Short name	T2512
Test name
Test status
Simulation time	3654253932 ps
CPU time	62.38 seconds
Started	Apr 23 04:40:13 PM PDT 24
Finished	Apr 23 04:41:16 PM PDT 24
Peak memory	562768 kb
Host	smart-537a2c68-4ada-4a18-9c8a-02ef4483ccfc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971609514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.971609514
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.2372489497
Short name	T1915
Test name
Test status
Simulation time	44407583 ps
CPU time	6.76 seconds
Started	Apr 23 04:40:07 PM PDT 24
Finished	Apr 23 04:40:15 PM PDT 24
Peak memory	562716 kb
Host	smart-351f16eb-6d00-438d-bdff-caab718ceac5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372489497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.2372489497
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all.486651445
Short name	T1791
Test name
Test status
Simulation time	2234463385 ps
CPU time	207.56 seconds
Started	Apr 23 04:40:17 PM PDT 24
Finished	Apr 23 04:43:45 PM PDT 24
Peak memory	563940 kb
Host	smart-cad49bfa-2bfd-47d2-ac01-a6157233b7a8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486651445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.486651445
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.3336832677
Short name	T2468
Test name
Test status
Simulation time	9202689345 ps
CPU time	344.99 seconds
Started	Apr 23 04:40:16 PM PDT 24
Finished	Apr 23 04:46:02 PM PDT 24
Peak memory	563924 kb
Host	smart-e75779b7-54f4-40b9-a5fc-48b0ea8ca58b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336832677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3336832677
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2595678003
Short name	T441
Test name
Test status
Simulation time	2587554677 ps
CPU time	420.37 seconds
Started	Apr 23 04:40:22 PM PDT 24
Finished	Apr 23 04:47:22 PM PDT 24
Peak memory	572048 kb
Host	smart-7a42d12b-cf16-4832-88bc-6ff663d80560
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595678003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.2595678003
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1359094535
Short name	T2674
Test name
Test status
Simulation time	136234492 ps
CPU time	74.17 seconds
Started	Apr 23 04:40:22 PM PDT 24
Finished	Apr 23 04:41:37 PM PDT 24
Peak memory	563828 kb
Host	smart-287cb69e-02c0-40d7-81bb-e35e3cf034c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359094535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.1359094535
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1935282496
Short name	T573
Test name
Test status
Simulation time	49909741 ps
CPU time	9.01 seconds
Started	Apr 23 04:40:13 PM PDT 24
Finished	Apr 23 04:40:22 PM PDT 24
Peak memory	562792 kb
Host	smart-5b4f17b9-a34b-4b26-b658-98f4639e4aa2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935282496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1935282496
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_access_same_device.2415409246
Short name	T1946
Test name
Test status
Simulation time	3182045971 ps
CPU time	147.55 seconds
Started	Apr 23 04:40:20 PM PDT 24
Finished	Apr 23 04:42:48 PM PDT 24
Peak memory	562864 kb
Host	smart-e2da11aa-5e09-4f3c-9886-39991934208c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415409246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .2415409246
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3159803227
Short name	T2217
Test name
Test status
Simulation time	129163585489 ps
CPU time	2193.08 seconds
Started	Apr 23 04:40:21 PM PDT 24
Finished	Apr 23 05:16:55 PM PDT 24
Peak memory	562816 kb
Host	smart-7013b38c-2ece-4b5a-80f5-3e1f4658f359
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159803227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.3159803227
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3571526795
Short name	T1812
Test name
Test status
Simulation time	244694229 ps
CPU time	30 seconds
Started	Apr 23 04:40:26 PM PDT 24
Finished	Apr 23 04:40:56 PM PDT 24
Peak memory	562752 kb
Host	smart-afc23abd-a48b-4eda-b7d6-e6ed4eed3538
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571526795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.3571526795
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_error_random.1625563335
Short name	T1376
Test name
Test status
Simulation time	285035674 ps
CPU time	25.34 seconds
Started	Apr 23 04:40:22 PM PDT 24
Finished	Apr 23 04:40:48 PM PDT 24
Peak memory	562728 kb
Host	smart-ea018128-9838-4cd5-bdd8-1e946ea83504
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625563335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1625563335
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_random.4022123218
Short name	T1612
Test name
Test status
Simulation time	733588646 ps
CPU time	29.38 seconds
Started	Apr 23 04:40:21 PM PDT 24
Finished	Apr 23 04:40:51 PM PDT 24
Peak memory	562732 kb
Host	smart-0108a1ce-d35b-4941-949e-b7e7bfff21a9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022123218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.4022123218
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3817896384
Short name	T1536
Test name
Test status
Simulation time	99631464061 ps
CPU time	1071.77 seconds
Started	Apr 23 04:40:19 PM PDT 24
Finished	Apr 23 04:58:11 PM PDT 24
Peak memory	562816 kb
Host	smart-694d8973-743f-4a9b-8aff-a1c5f692e098
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817896384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3817896384
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.3308206273
Short name	T2024
Test name
Test status
Simulation time	63382028540 ps
CPU time	1217.71 seconds
Started	Apr 23 04:40:19 PM PDT 24
Finished	Apr 23 05:00:37 PM PDT 24
Peak memory	562824 kb
Host	smart-f02f0bb2-0a1e-4323-99b7-de5134c2b1f5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308206273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3308206273
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1558893328
Short name	T1572
Test name
Test status
Simulation time	621974133 ps
CPU time	49.11 seconds
Started	Apr 23 04:40:19 PM PDT 24
Finished	Apr 23 04:41:08 PM PDT 24
Peak memory	562728 kb
Host	smart-ea06764a-d110-46f9-9d67-54d53bea1fa2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558893328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.1558893328
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_same_source.549250195
Short name	T1569
Test name
Test status
Simulation time	610294395 ps
CPU time	21.13 seconds
Started	Apr 23 04:40:22 PM PDT 24
Finished	Apr 23 04:40:43 PM PDT 24
Peak memory	562732 kb
Host	smart-d9c409ae-09e1-42c5-8dbe-d3b7db095b92
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549250195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.549250195
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke.363935392
Short name	T2490
Test name
Test status
Simulation time	44401794 ps
CPU time	5.9 seconds
Started	Apr 23 04:40:20 PM PDT 24
Finished	Apr 23 04:40:26 PM PDT 24
Peak memory	562712 kb
Host	smart-9e7df8d6-f281-4c87-8d61-17cc621274b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363935392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.363935392
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.1481589708
Short name	T449
Test name
Test status
Simulation time	6286080849 ps
CPU time	68.03 seconds
Started	Apr 23 04:40:17 PM PDT 24
Finished	Apr 23 04:41:26 PM PDT 24
Peak memory	562780 kb
Host	smart-c16c16a5-dfa0-4b78-97df-1e1c62521458
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481589708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1481589708
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1049658343
Short name	T1425
Test name
Test status
Simulation time	5027930518 ps
CPU time	87.59 seconds
Started	Apr 23 04:40:19 PM PDT 24
Finished	Apr 23 04:41:47 PM PDT 24
Peak memory	562768 kb
Host	smart-69ada6e6-ea50-4392-b286-2434423e36d5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049658343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1049658343
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3834968911
Short name	T2303
Test name
Test status
Simulation time	49706160 ps
CPU time	6.58 seconds
Started	Apr 23 04:40:19 PM PDT 24
Finished	Apr 23 04:40:26 PM PDT 24
Peak memory	562688 kb
Host	smart-2d9d507c-47f1-4a56-87c2-125a8de6ebb7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834968911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.3834968911
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all.3002878582
Short name	T2725
Test name
Test status
Simulation time	13425542194 ps
CPU time	562.34 seconds
Started	Apr 23 04:40:26 PM PDT 24
Finished	Apr 23 04:49:49 PM PDT 24
Peak memory	563576 kb
Host	smart-01c70d43-d859-44b7-9cf7-c10b9864c926
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002878582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3002878582
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3471601023
Short name	T2425
Test name
Test status
Simulation time	6868135351 ps
CPU time	245.32 seconds
Started	Apr 23 04:40:26 PM PDT 24
Finished	Apr 23 04:44:32 PM PDT 24
Peak memory	562940 kb
Host	smart-2f279794-d370-4949-b7ef-8de5e038858b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471601023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3471601023
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2542590533
Short name	T2713
Test name
Test status
Simulation time	6300311820 ps
CPU time	812.56 seconds
Started	Apr 23 04:40:27 PM PDT 24
Finished	Apr 23 04:54:00 PM PDT 24
Peak memory	572228 kb
Host	smart-f67bc00d-502f-46fe-b24b-ee93ed4db116
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542590533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.2542590533
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1459815664
Short name	T799
Test name
Test status
Simulation time	3039434754 ps
CPU time	276.2 seconds
Started	Apr 23 04:40:23 PM PDT 24
Finished	Apr 23 04:44:59 PM PDT 24
Peak memory	572156 kb
Host	smart-bc07af1b-e776-4c84-a132-4f14a79463ed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459815664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.1459815664
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.1951234775
Short name	T467
Test name
Test status
Simulation time	33984799 ps
CPU time	7.19 seconds
Started	Apr 23 04:40:21 PM PDT 24
Finished	Apr 23 04:40:29 PM PDT 24
Peak memory	562800 kb
Host	smart-87c9ffa2-6e6f-48b7-ac10-016c4e7458ad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951234775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1951234775
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_access_same_device.2798723386
Short name	T757
Test name
Test status
Simulation time	751607411 ps
CPU time	61.2 seconds
Started	Apr 23 04:40:28 PM PDT 24
Finished	Apr 23 04:41:30 PM PDT 24
Peak memory	562756 kb
Host	smart-1d821e23-ff50-443a-804f-e34f5b34b98d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798723386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .2798723386
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3870718884
Short name	T2508
Test name
Test status
Simulation time	138024243182 ps
CPU time	2591.54 seconds
Started	Apr 23 04:40:33 PM PDT 24
Finished	Apr 23 05:23:45 PM PDT 24
Peak memory	562972 kb
Host	smart-74ba3f76-6bc5-45bd-b1ca-afb55d34367d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870718884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.3870718884
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3952946548
Short name	T2741
Test name
Test status
Simulation time	62024711 ps
CPU time	9.72 seconds
Started	Apr 23 04:40:32 PM PDT 24
Finished	Apr 23 04:40:42 PM PDT 24
Peak memory	562700 kb
Host	smart-9c5e2451-430f-4e43-b8c5-fb1a80d6950a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952946548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.3952946548
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_error_random.1892658185
Short name	T2342
Test name
Test status
Simulation time	240151454 ps
CPU time	11.44 seconds
Started	Apr 23 04:40:35 PM PDT 24
Finished	Apr 23 04:40:47 PM PDT 24
Peak memory	562708 kb
Host	smart-d1d5bac0-243c-43f7-8738-60e23d2c89e2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892658185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1892658185
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_random.2474294508
Short name	T2433
Test name
Test status
Simulation time	409331450 ps
CPU time	16.77 seconds
Started	Apr 23 04:40:32 PM PDT 24
Finished	Apr 23 04:40:49 PM PDT 24
Peak memory	562740 kb
Host	smart-95354cfd-cd60-4ea5-bdba-80772b28bb07
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474294508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.2474294508
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_random_large_delays.822084034
Short name	T1616
Test name
Test status
Simulation time	6447925363 ps
CPU time	72.06 seconds
Started	Apr 23 04:40:31 PM PDT 24
Finished	Apr 23 04:41:44 PM PDT 24
Peak memory	562784 kb
Host	smart-6a08375b-f0e7-4091-a1e3-1867062e99dc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822084034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.822084034
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.3923077768
Short name	T1637
Test name
Test status
Simulation time	28830631279 ps
CPU time	523.02 seconds
Started	Apr 23 04:40:28 PM PDT 24
Finished	Apr 23 04:49:11 PM PDT 24
Peak memory	562780 kb
Host	smart-1cfe81dd-7d3b-4716-bec8-46f63dc8388a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923077768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3923077768
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2019150733
Short name	T1644
Test name
Test status
Simulation time	44944101 ps
CPU time	6.94 seconds
Started	Apr 23 04:40:28 PM PDT 24
Finished	Apr 23 04:40:35 PM PDT 24
Peak memory	562676 kb
Host	smart-d49e6821-a064-45a6-9436-ad7e9adb9206
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019150733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.2019150733
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_same_source.2025065442
Short name	T457
Test name
Test status
Simulation time	465511817 ps
CPU time	36.34 seconds
Started	Apr 23 04:40:30 PM PDT 24
Finished	Apr 23 04:41:06 PM PDT 24
Peak memory	562716 kb
Host	smart-aa672571-0cc5-40d9-ae39-84a7f15102a9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025065442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2025065442
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke.4068647468
Short name	T2101
Test name
Test status
Simulation time	269696254 ps
CPU time	11.85 seconds
Started	Apr 23 04:40:28 PM PDT 24
Finished	Apr 23 04:40:40 PM PDT 24
Peak memory	562688 kb
Host	smart-4d2a3a1d-3c6c-4868-93ac-8a6436f673c0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068647468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.4068647468
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2340876395
Short name	T2370
Test name
Test status
Simulation time	8471967756 ps
CPU time	99.75 seconds
Started	Apr 23 04:40:24 PM PDT 24
Finished	Apr 23 04:42:04 PM PDT 24
Peak memory	562796 kb
Host	smart-0fb2c050-f8dd-4eac-ae6d-854fbb450253
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340876395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2340876395
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.942424613
Short name	T1690
Test name
Test status
Simulation time	6664654506 ps
CPU time	124.11 seconds
Started	Apr 23 04:40:35 PM PDT 24
Finished	Apr 23 04:42:40 PM PDT 24
Peak memory	562788 kb
Host	smart-198474be-d45d-454a-b427-a38889300c19
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942424613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.942424613
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.91815222
Short name	T2630
Test name
Test status
Simulation time	38855672 ps
CPU time	6.06 seconds
Started	Apr 23 04:40:29 PM PDT 24
Finished	Apr 23 04:40:35 PM PDT 24
Peak memory	562688 kb
Host	smart-2d1f09d8-df9d-42e4-ac8a-b4ee844e4aa2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91815222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.91815222
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all.180566217
Short name	T2711
Test name
Test status
Simulation time	7944462123 ps
CPU time	281.08 seconds
Started	Apr 23 04:40:36 PM PDT 24
Finished	Apr 23 04:45:18 PM PDT 24
Peak memory	563932 kb
Host	smart-50576cea-8273-4954-a8da-7e35b9adf3e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180566217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.180566217
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.3002227086
Short name	T2600
Test name
Test status
Simulation time	2628940303 ps
CPU time	205.34 seconds
Started	Apr 23 04:40:36 PM PDT 24
Finished	Apr 23 04:44:02 PM PDT 24
Peak memory	562804 kb
Host	smart-86981172-65a3-41b9-a40e-68e72910860e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002227086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3002227086
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.476676574
Short name	T2094
Test name
Test status
Simulation time	679195677 ps
CPU time	280.6 seconds
Started	Apr 23 04:40:35 PM PDT 24
Finished	Apr 23 04:45:16 PM PDT 24
Peak memory	572152 kb
Host	smart-107e69a2-f7f6-49eb-930a-a309f960702e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476676574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_ with_rand_reset.476676574
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1196541590
Short name	T2791
Test name
Test status
Simulation time	74591575 ps
CPU time	53.92 seconds
Started	Apr 23 04:40:36 PM PDT 24
Finished	Apr 23 04:41:30 PM PDT 24
Peak memory	563576 kb
Host	smart-46a2c6a9-d822-4c99-888d-8f6ba9a50f93
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196541590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.1196541590
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.1370617935
Short name	T1879
Test name
Test status
Simulation time	262593996 ps
CPU time	36.6 seconds
Started	Apr 23 04:40:32 PM PDT 24
Finished	Apr 23 04:41:09 PM PDT 24
Peak memory	562756 kb
Host	smart-9f2d0bde-d650-4b7a-853f-70519fe44763
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370617935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1370617935
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_access_same_device.3789583986
Short name	T1374
Test name
Test status
Simulation time	641508090 ps
CPU time	57.03 seconds
Started	Apr 23 04:40:40 PM PDT 24
Finished	Apr 23 04:41:37 PM PDT 24
Peak memory	562744 kb
Host	smart-b1f07b4a-bc46-4950-94d3-6b5683787c97
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789583986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3789583986
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.864660188
Short name	T790
Test name
Test status
Simulation time	29863129559 ps
CPU time	513.09 seconds
Started	Apr 23 04:40:43 PM PDT 24
Finished	Apr 23 04:49:17 PM PDT 24
Peak memory	562828 kb
Host	smart-882c3bfd-6e61-4ae1-af7b-caaa30069015
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864660188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_d evice_slow_rsp.864660188
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3443286967
Short name	T506
Test name
Test status
Simulation time	568587408 ps
CPU time	25.18 seconds
Started	Apr 23 04:40:43 PM PDT 24
Finished	Apr 23 04:41:09 PM PDT 24
Peak memory	562752 kb
Host	smart-62b58f83-586b-4f12-a800-9f85323dea4c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443286967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.3443286967
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_error_random.851403441
Short name	T1749
Test name
Test status
Simulation time	1334931437 ps
CPU time	49.04 seconds
Started	Apr 23 04:40:42 PM PDT 24
Finished	Apr 23 04:41:32 PM PDT 24
Peak memory	562684 kb
Host	smart-79a9f700-661b-4acf-81d5-5ba69fd22ecf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851403441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.851403441
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_random.1057502040
Short name	T1400
Test name
Test status
Simulation time	89391741 ps
CPU time	10.97 seconds
Started	Apr 23 04:40:37 PM PDT 24
Finished	Apr 23 04:40:48 PM PDT 24
Peak memory	562716 kb
Host	smart-881d1a8d-d551-4ae6-b697-c0f305262e1a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057502040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.1057502040
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3560605987
Short name	T1629
Test name
Test status
Simulation time	78392416665 ps
CPU time	809.52 seconds
Started	Apr 23 04:40:39 PM PDT 24
Finished	Apr 23 04:54:09 PM PDT 24
Peak memory	562828 kb
Host	smart-b7da931c-fc8a-402a-8ef1-d9752ed7bd53
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560605987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3560605987
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.1699168484
Short name	T1330
Test name
Test status
Simulation time	6081365834 ps
CPU time	115.29 seconds
Started	Apr 23 04:40:39 PM PDT 24
Finished	Apr 23 04:42:36 PM PDT 24
Peak memory	562780 kb
Host	smart-694ddd2e-e30a-4b1f-8f15-327f87b84343
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699168484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1699168484
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.866464419
Short name	T452
Test name
Test status
Simulation time	445955930 ps
CPU time	43.82 seconds
Started	Apr 23 04:40:40 PM PDT 24
Finished	Apr 23 04:41:24 PM PDT 24
Peak memory	562672 kb
Host	smart-502ea1ab-4e32-4fea-b501-44f7b155014a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866464419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_dela ys.866464419
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_same_source.1352345348
Short name	T1593
Test name
Test status
Simulation time	231819803 ps
CPU time	21.53 seconds
Started	Apr 23 04:40:42 PM PDT 24
Finished	Apr 23 04:41:04 PM PDT 24
Peak memory	562728 kb
Host	smart-5b1f6e65-40ad-4279-8dea-56f53970c56c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352345348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1352345348
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke.2695505666
Short name	T1716
Test name
Test status
Simulation time	200245955 ps
CPU time	9.27 seconds
Started	Apr 23 04:40:40 PM PDT 24
Finished	Apr 23 04:40:50 PM PDT 24
Peak memory	562732 kb
Host	smart-365f674b-0cee-4aa9-8951-f49ab8f0c96a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695505666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2695505666
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.2865968441
Short name	T2585
Test name
Test status
Simulation time	6372921868 ps
CPU time	73.91 seconds
Started	Apr 23 04:40:41 PM PDT 24
Finished	Apr 23 04:41:56 PM PDT 24
Peak memory	562768 kb
Host	smart-ccbcce67-2d17-4180-a176-85402c2a4a3e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865968441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2865968441
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.3964774067
Short name	T1287
Test name
Test status
Simulation time	5488366936 ps
CPU time	100.85 seconds
Started	Apr 23 04:40:38 PM PDT 24
Finished	Apr 23 04:42:19 PM PDT 24
Peak memory	562768 kb
Host	smart-9d318fc8-df10-4ecb-a039-fcc378d39bac
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964774067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3964774067
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.330181382
Short name	T1460
Test name
Test status
Simulation time	50602529 ps
CPU time	6.34 seconds
Started	Apr 23 04:40:39 PM PDT 24
Finished	Apr 23 04:40:46 PM PDT 24
Peak memory	562684 kb
Host	smart-bdf755aa-84f0-4349-8b88-677c5425b919
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330181382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays .330181382
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all.4052298735
Short name	T584
Test name
Test status
Simulation time	7328782882 ps
CPU time	275.83 seconds
Started	Apr 23 04:40:45 PM PDT 24
Finished	Apr 23 04:45:21 PM PDT 24
Peak memory	563804 kb
Host	smart-c7077e11-5def-43bd-a9d2-d088973bca73
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052298735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4052298735
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.618504704
Short name	T1894
Test name
Test status
Simulation time	10414852476 ps
CPU time	542.63 seconds
Started	Apr 23 04:40:41 PM PDT 24
Finished	Apr 23 04:49:45 PM PDT 24
Peak memory	572196 kb
Host	smart-6f662afd-785b-410c-893e-a42febec08e5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618504704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_ with_rand_reset.618504704
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.2211514945
Short name	T2171
Test name
Test status
Simulation time	3070226667 ps
CPU time	349.7 seconds
Started	Apr 23 04:40:45 PM PDT 24
Finished	Apr 23 04:46:35 PM PDT 24
Peak memory	572156 kb
Host	smart-76718f92-3b0f-4951-b147-292b301ac9ef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211514945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.2211514945
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.3456215790
Short name	T1302
Test name
Test status
Simulation time	332303640 ps
CPU time	38.76 seconds
Started	Apr 23 04:40:39 PM PDT 24
Finished	Apr 23 04:41:19 PM PDT 24
Peak memory	562724 kb
Host	smart-5d70a521-4800-4d95-955b-e78486f1d19a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456215790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3456215790
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_access_same_device.2998264148
Short name	T2197
Test name
Test status
Simulation time	423250365 ps
CPU time	40.86 seconds
Started	Apr 23 04:40:48 PM PDT 24
Finished	Apr 23 04:41:29 PM PDT 24
Peak memory	562712 kb
Host	smart-207d4468-ed5b-43fd-b3c3-729fc7aa0e10
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998264148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .2998264148
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1697640178
Short name	T2501
Test name
Test status
Simulation time	299449031 ps
CPU time	32.42 seconds
Started	Apr 23 04:40:50 PM PDT 24
Finished	Apr 23 04:41:23 PM PDT 24
Peak memory	562708 kb
Host	smart-dd777db0-1786-474b-8c23-16eec8081447
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697640178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.1697640178
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_error_random.1409130185
Short name	T1617
Test name
Test status
Simulation time	514821015 ps
CPU time	21.96 seconds
Started	Apr 23 04:40:48 PM PDT 24
Finished	Apr 23 04:41:11 PM PDT 24
Peak memory	562680 kb
Host	smart-6c5b488b-639f-4033-8bc9-f7ef1aae9283
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409130185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1409130185
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_random.3440527404
Short name	T1419
Test name
Test status
Simulation time	755836375 ps
CPU time	30.66 seconds
Started	Apr 23 04:40:45 PM PDT 24
Finished	Apr 23 04:41:17 PM PDT 24
Peak memory	562744 kb
Host	smart-3b07d282-a0f4-4675-8f7d-8848e272d421
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440527404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.3440527404
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_random_large_delays.4065476422
Short name	T1300
Test name
Test status
Simulation time	51389132654 ps
CPU time	587.81 seconds
Started	Apr 23 04:40:45 PM PDT 24
Finished	Apr 23 04:50:33 PM PDT 24
Peak memory	562756 kb
Host	smart-3315746b-31cd-4954-8a5a-8f4f883fd4f6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065476422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.4065476422
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.2563646762
Short name	T2174
Test name
Test status
Simulation time	38937581550 ps
CPU time	727.85 seconds
Started	Apr 23 04:40:48 PM PDT 24
Finished	Apr 23 04:52:56 PM PDT 24
Peak memory	562792 kb
Host	smart-6954f491-84bd-46ae-8d4f-ba0a43e80dfe
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563646762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2563646762
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.4008388173
Short name	T1730
Test name
Test status
Simulation time	112894866 ps
CPU time	14.65 seconds
Started	Apr 23 04:40:48 PM PDT 24
Finished	Apr 23 04:41:03 PM PDT 24
Peak memory	562708 kb
Host	smart-6f7b204f-27a8-4021-b3d1-ae36e23a109a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008388173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.4008388173
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_same_source.467099628
Short name	T2328
Test name
Test status
Simulation time	2073339223 ps
CPU time	70.36 seconds
Started	Apr 23 04:40:48 PM PDT 24
Finished	Apr 23 04:41:59 PM PDT 24
Peak memory	562744 kb
Host	smart-24c4f569-e6d1-4b10-9fbb-33004a374f90
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467099628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.467099628
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke.4061807681
Short name	T1694
Test name
Test status
Simulation time	53055948 ps
CPU time	7.15 seconds
Started	Apr 23 04:40:44 PM PDT 24
Finished	Apr 23 04:40:51 PM PDT 24
Peak memory	562732 kb
Host	smart-41d3ffdb-8802-4b58-940c-cbcea36cd01e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061807681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4061807681
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.2443662629
Short name	T2530
Test name
Test status
Simulation time	8059817742 ps
CPU time	92.65 seconds
Started	Apr 23 04:40:47 PM PDT 24
Finished	Apr 23 04:42:20 PM PDT 24
Peak memory	562800 kb
Host	smart-259b3709-ac68-439b-8baa-7833f3e4fb2e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443662629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2443662629
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.182310742
Short name	T1927
Test name
Test status
Simulation time	5531437804 ps
CPU time	95.15 seconds
Started	Apr 23 04:40:48 PM PDT 24
Finished	Apr 23 04:42:23 PM PDT 24
Peak memory	562764 kb
Host	smart-5e505f78-a710-4b92-9e5c-a7582a76a00a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182310742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.182310742
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2146522303
Short name	T2729
Test name
Test status
Simulation time	50307926 ps
CPU time	6.91 seconds
Started	Apr 23 04:40:50 PM PDT 24
Finished	Apr 23 04:40:57 PM PDT 24
Peak memory	562696 kb
Host	smart-ebb4c8ce-c9f1-48b8-b963-8ea5ef471df6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146522303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.2146522303
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all.581917798
Short name	T1591
Test name
Test status
Simulation time	11130897557 ps
CPU time	489.81 seconds
Started	Apr 23 04:40:51 PM PDT 24
Finished	Apr 23 04:49:01 PM PDT 24
Peak memory	571140 kb
Host	smart-c117c173-959a-46be-a85b-ce78365d3008
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581917798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.581917798
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.2455924380
Short name	T2582
Test name
Test status
Simulation time	202362180 ps
CPU time	8.76 seconds
Started	Apr 23 04:40:51 PM PDT 24
Finished	Apr 23 04:41:01 PM PDT 24
Peak memory	562704 kb
Host	smart-666af6dc-876c-42f6-80f7-89f90178151e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455924380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2455924380
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.4156723103
Short name	T1938
Test name
Test status
Simulation time	4756368288 ps
CPU time	270.23 seconds
Started	Apr 23 04:40:51 PM PDT 24
Finished	Apr 23 04:45:22 PM PDT 24
Peak memory	563980 kb
Host	smart-382eb5ae-362c-473c-97ec-192b9b62d0c0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156723103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.4156723103
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1285935433
Short name	T1630
Test name
Test status
Simulation time	1756713306 ps
CPU time	195.79 seconds
Started	Apr 23 04:40:56 PM PDT 24
Finished	Apr 23 04:44:12 PM PDT 24
Peak memory	563880 kb
Host	smart-7137f15c-eb85-4eaa-9213-ce8f2c0ba47c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285935433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.1285935433
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.4272242840
Short name	T1822
Test name
Test status
Simulation time	478404853 ps
CPU time	22.73 seconds
Started	Apr 23 04:40:49 PM PDT 24
Finished	Apr 23 04:41:12 PM PDT 24
Peak memory	562756 kb
Host	smart-208df3ec-d2b7-401f-8272-0a6e8c85a93a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272242840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.4272242840
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_access_same_device.1241315671
Short name	T2386
Test name
Test status
Simulation time	2300393123 ps
CPU time	103.91 seconds
Started	Apr 23 04:41:05 PM PDT 24
Finished	Apr 23 04:42:49 PM PDT 24
Peak memory	562792 kb
Host	smart-b50b3ef3-f145-49f8-82ca-fec8b6c9ef5a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241315671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .1241315671
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1770167455
Short name	T620
Test name
Test status
Simulation time	76368039360 ps
CPU time	1403.55 seconds
Started	Apr 23 04:41:04 PM PDT 24
Finished	Apr 23 05:04:28 PM PDT 24
Peak memory	562796 kb
Host	smart-31f94028-16d1-42ea-ac42-baada440020c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770167455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.1770167455
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.598504849
Short name	T1375
Test name
Test status
Simulation time	99368552 ps
CPU time	13.47 seconds
Started	Apr 23 04:41:06 PM PDT 24
Finished	Apr 23 04:41:19 PM PDT 24
Peak memory	562704 kb
Host	smart-80fa3731-5c08-49cf-8cbc-41cc704e8386
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598504849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr .598504849
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_error_random.1554797825
Short name	T1449
Test name
Test status
Simulation time	678501431 ps
CPU time	27.12 seconds
Started	Apr 23 04:41:04 PM PDT 24
Finished	Apr 23 04:41:31 PM PDT 24
Peak memory	562716 kb
Host	smart-dc485a6f-b863-4f66-a3c6-9615ba6731fe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554797825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1554797825
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_random.1475211805
Short name	T2088
Test name
Test status
Simulation time	842759331 ps
CPU time	33.99 seconds
Started	Apr 23 04:41:01 PM PDT 24
Finished	Apr 23 04:41:35 PM PDT 24
Peak memory	562732 kb
Host	smart-c09f36c3-5fb9-4778-bf73-fdecc8b22cff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475211805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.1475211805
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_random_large_delays.2318255117
Short name	T2414
Test name
Test status
Simulation time	33924138171 ps
CPU time	356.69 seconds
Started	Apr 23 04:41:02 PM PDT 24
Finished	Apr 23 04:46:59 PM PDT 24
Peak memory	562824 kb
Host	smart-cd69870a-a177-427f-b1ef-86af41564e1d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318255117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2318255117
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.319184826
Short name	T2172
Test name
Test status
Simulation time	2105426352 ps
CPU time	36.8 seconds
Started	Apr 23 04:41:03 PM PDT 24
Finished	Apr 23 04:41:40 PM PDT 24
Peak memory	562716 kb
Host	smart-3b9160d4-cfcb-42a1-8684-ddf5a50c190a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319184826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.319184826
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1667508880
Short name	T2670
Test name
Test status
Simulation time	384472437 ps
CPU time	37.67 seconds
Started	Apr 23 04:41:02 PM PDT 24
Finished	Apr 23 04:41:40 PM PDT 24
Peak memory	562740 kb
Host	smart-17c0154e-fa9f-428c-b44b-2404b53e4233
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667508880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.1667508880
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_same_source.4130076286
Short name	T2779
Test name
Test status
Simulation time	502148689 ps
CPU time	18.94 seconds
Started	Apr 23 04:41:05 PM PDT 24
Finished	Apr 23 04:41:25 PM PDT 24
Peak memory	562728 kb
Host	smart-d5928631-d1f9-43d1-8aa0-6fc345df218d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130076286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.4130076286
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke.3075559775
Short name	T1592
Test name
Test status
Simulation time	167401125 ps
CPU time	8.08 seconds
Started	Apr 23 04:40:54 PM PDT 24
Finished	Apr 23 04:41:02 PM PDT 24
Peak memory	562692 kb
Host	smart-9f663584-2fe6-4c30-98dc-8faf0f117a88
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075559775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3075559775
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.59015124
Short name	T1874
Test name
Test status
Simulation time	6908007348 ps
CPU time	80.42 seconds
Started	Apr 23 04:40:56 PM PDT 24
Finished	Apr 23 04:42:17 PM PDT 24
Peak memory	562788 kb
Host	smart-7d6c8486-3eb2-484d-8c84-53175b815eba
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59015124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.59015124
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3996786736
Short name	T2387
Test name
Test status
Simulation time	4834507416 ps
CPU time	90.43 seconds
Started	Apr 23 04:40:57 PM PDT 24
Finished	Apr 23 04:42:28 PM PDT 24
Peak memory	562788 kb
Host	smart-515cb5c8-1bdc-495d-af0c-8033b0eaa812
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996786736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3996786736
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2583726103
Short name	T2253
Test name
Test status
Simulation time	37185572 ps
CPU time	5.7 seconds
Started	Apr 23 04:40:57 PM PDT 24
Finished	Apr 23 04:41:03 PM PDT 24
Peak memory	562640 kb
Host	smart-1b16c59e-10c3-4b29-8e40-ed88245fdd74
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583726103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2583726103
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all.2677880130
Short name	T1446
Test name
Test status
Simulation time	9946487135 ps
CPU time	385.22 seconds
Started	Apr 23 04:41:07 PM PDT 24
Finished	Apr 23 04:47:33 PM PDT 24
Peak memory	563920 kb
Host	smart-7eb12a2c-8bce-47bc-9fbd-428560ee6e52
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677880130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2677880130
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2997022166
Short name	T1650
Test name
Test status
Simulation time	2430723842 ps
CPU time	313.24 seconds
Started	Apr 23 04:41:05 PM PDT 24
Finished	Apr 23 04:46:19 PM PDT 24
Peak memory	572220 kb
Host	smart-d37fe630-cd8f-49f5-af9b-556e4d3be849
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997022166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.2997022166
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2363504300
Short name	T2453
Test name
Test status
Simulation time	1172435170 ps
CPU time	233.84 seconds
Started	Apr 23 04:41:07 PM PDT 24
Finished	Apr 23 04:45:01 PM PDT 24
Peak memory	572100 kb
Host	smart-664ce1a5-9c4f-4406-91a9-e27f202c5067
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363504300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.2363504300
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.792977231
Short name	T583
Test name
Test status
Simulation time	461694191 ps
CPU time	22.08 seconds
Started	Apr 23 04:41:03 PM PDT 24
Finished	Apr 23 04:41:25 PM PDT 24
Peak memory	562736 kb
Host	smart-598a9370-7094-4689-9e4d-7bd8aa344f90
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792977231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.792977231
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_access_same_device.1197328957
Short name	T1875
Test name
Test status
Simulation time	1741868679 ps
CPU time	70.57 seconds
Started	Apr 23 04:41:13 PM PDT 24
Finished	Apr 23 04:42:23 PM PDT 24
Peak memory	562776 kb
Host	smart-69a35e40-f4b7-4a24-bf33-3ee4e037887e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197328957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .1197328957
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.109701169
Short name	T2008
Test name
Test status
Simulation time	129095998653 ps
CPU time	2329.15 seconds
Started	Apr 23 04:41:13 PM PDT 24
Finished	Apr 23 05:20:03 PM PDT 24
Peak memory	562960 kb
Host	smart-32dde0ce-2282-4d19-b459-a6ddcd7e6f9c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109701169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_d evice_slow_rsp.109701169
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.265460677
Short name	T2740
Test name
Test status
Simulation time	93067387 ps
CPU time	12.76 seconds
Started	Apr 23 04:41:18 PM PDT 24
Finished	Apr 23 04:41:31 PM PDT 24
Peak memory	562688 kb
Host	smart-ed87ceb1-e356-45d7-9ad5-533945125815
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265460677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr .265460677
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_error_random.2952679262
Short name	T1756
Test name
Test status
Simulation time	624086557 ps
CPU time	23.55 seconds
Started	Apr 23 04:41:13 PM PDT 24
Finished	Apr 23 04:41:37 PM PDT 24
Peak memory	562696 kb
Host	smart-7b2ba5b6-c128-4da4-982c-ae9cfdfb544b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952679262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2952679262
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_random.2440882959
Short name	T1767
Test name
Test status
Simulation time	2583840550 ps
CPU time	104.48 seconds
Started	Apr 23 04:41:15 PM PDT 24
Finished	Apr 23 04:43:00 PM PDT 24
Peak memory	562760 kb
Host	smart-f9f44a04-1619-486f-8667-51d7a983f451
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440882959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2440882959
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_random_large_delays.3777569183
Short name	T1344
Test name
Test status
Simulation time	48568086619 ps
CPU time	515.88 seconds
Started	Apr 23 04:41:12 PM PDT 24
Finished	Apr 23 04:49:48 PM PDT 24
Peak memory	562824 kb
Host	smart-55a402e1-2844-4bdc-bdeb-b553d40d3c96
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777569183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3777569183
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.575984411
Short name	T1381
Test name
Test status
Simulation time	56408219109 ps
CPU time	997.02 seconds
Started	Apr 23 04:41:14 PM PDT 24
Finished	Apr 23 04:57:52 PM PDT 24
Peak memory	562860 kb
Host	smart-aff7da74-4be6-4b5b-ab1a-742ee5d07869
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575984411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.575984411
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.3527432505
Short name	T1285
Test name
Test status
Simulation time	301726653 ps
CPU time	26.21 seconds
Started	Apr 23 04:41:14 PM PDT 24
Finished	Apr 23 04:41:40 PM PDT 24
Peak memory	562680 kb
Host	smart-d5f9fd8d-9691-4c8c-a526-f699a898d54c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527432505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.3527432505
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_same_source.3117535286
Short name	T2409
Test name
Test status
Simulation time	1607050233 ps
CPU time	48.35 seconds
Started	Apr 23 04:41:14 PM PDT 24
Finished	Apr 23 04:42:02 PM PDT 24
Peak memory	562724 kb
Host	smart-344bd016-48f9-43c6-956e-ec0d9c4dc419
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117535286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3117535286
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke.3355964230
Short name	T1861
Test name
Test status
Simulation time	207874544 ps
CPU time	10.71 seconds
Started	Apr 23 04:41:07 PM PDT 24
Finished	Apr 23 04:41:18 PM PDT 24
Peak memory	562720 kb
Host	smart-a2f3164d-f306-4a66-8fa9-694d40ae0b79
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355964230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3355964230
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.914504911
Short name	T1805
Test name
Test status
Simulation time	9426893648 ps
CPU time	110.59 seconds
Started	Apr 23 04:41:08 PM PDT 24
Finished	Apr 23 04:42:59 PM PDT 24
Peak memory	562804 kb
Host	smart-f671ad27-92e4-4d3b-a292-6d9c08c985a8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914504911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.914504911
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3843843981
Short name	T1876
Test name
Test status
Simulation time	5607428748 ps
CPU time	97.59 seconds
Started	Apr 23 04:41:07 PM PDT 24
Finished	Apr 23 04:42:44 PM PDT 24
Peak memory	562724 kb
Host	smart-712f3d27-a40d-4986-af52-3e495ed66852
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843843981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3843843981
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1823679264
Short name	T1493
Test name
Test status
Simulation time	42098510 ps
CPU time	6.51 seconds
Started	Apr 23 04:41:09 PM PDT 24
Finished	Apr 23 04:41:16 PM PDT 24
Peak memory	562700 kb
Host	smart-4f2bd254-d8ef-4866-862c-44a8bbfd49a2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823679264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.1823679264
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all.1170340116
Short name	T1614
Test name
Test status
Simulation time	6578207383 ps
CPU time	323.85 seconds
Started	Apr 23 04:41:17 PM PDT 24
Finished	Apr 23 04:46:41 PM PDT 24
Peak memory	563952 kb
Host	smart-c8aa015a-6975-4cab-93e3-cd94b8ecaece
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170340116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1170340116
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.2986549989
Short name	T1334
Test name
Test status
Simulation time	1367076589 ps
CPU time	110.62 seconds
Started	Apr 23 04:41:17 PM PDT 24
Finished	Apr 23 04:43:08 PM PDT 24
Peak memory	562904 kb
Host	smart-5003beb8-f586-4ddf-989c-9d432defc783
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986549989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2986549989
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.612621371
Short name	T1535
Test name
Test status
Simulation time	2948920990 ps
CPU time	380.03 seconds
Started	Apr 23 04:41:19 PM PDT 24
Finished	Apr 23 04:47:39 PM PDT 24
Peak memory	564020 kb
Host	smart-660586c4-c439-41da-a5ac-7cfc8a7df4f9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612621371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_ with_rand_reset.612621371
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1745608080
Short name	T1424
Test name
Test status
Simulation time	279635726 ps
CPU time	95.24 seconds
Started	Apr 23 04:41:22 PM PDT 24
Finished	Apr 23 04:42:57 PM PDT 24
Peak memory	563968 kb
Host	smart-fbc16aa4-c860-4755-8677-72e52335ea8a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745608080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.1745608080
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.2653536858
Short name	T1778
Test name
Test status
Simulation time	394510150 ps
CPU time	18.94 seconds
Started	Apr 23 04:41:16 PM PDT 24
Finished	Apr 23 04:41:36 PM PDT 24
Peak memory	562800 kb
Host	smart-740aee53-d8b8-4b02-b698-b34b5d671845
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653536858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2653536858
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_access_same_device.557298563
Short name	T2538
Test name
Test status
Simulation time	1758276338 ps
CPU time	81.63 seconds
Started	Apr 23 04:41:24 PM PDT 24
Finished	Apr 23 04:42:46 PM PDT 24
Peak memory	562772 kb
Host	smart-ec365e51-249e-4df7-b197-54a319fbc739
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557298563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device. 557298563
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.706960121
Short name	T760
Test name
Test status
Simulation time	97890753175 ps
CPU time	1697.34 seconds
Started	Apr 23 04:41:24 PM PDT 24
Finished	Apr 23 05:09:42 PM PDT 24
Peak memory	562904 kb
Host	smart-7627a941-4bf5-4090-8f61-beedb0e60033
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706960121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_d evice_slow_rsp.706960121
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.417096099
Short name	T2305
Test name
Test status
Simulation time	75928596 ps
CPU time	12.04 seconds
Started	Apr 23 04:41:30 PM PDT 24
Finished	Apr 23 04:41:43 PM PDT 24
Peak memory	562688 kb
Host	smart-95907cf3-5ea9-4bab-ae93-bba8c97d97e3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417096099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr .417096099
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_error_random.2302780229
Short name	T85
Test name
Test status
Simulation time	1099498250 ps
CPU time	35.72 seconds
Started	Apr 23 04:41:32 PM PDT 24
Finished	Apr 23 04:42:08 PM PDT 24
Peak memory	562680 kb
Host	smart-2c92f762-984a-45a2-9684-3ac755f315ec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302780229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2302780229
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_random.2421411658
Short name	T546
Test name
Test status
Simulation time	2102489980 ps
CPU time	74.75 seconds
Started	Apr 23 04:41:20 PM PDT 24
Finished	Apr 23 04:42:35 PM PDT 24
Peak memory	562776 kb
Host	smart-dd3ccdd8-5c83-4413-a995-44cb8a77417f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421411658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2421411658
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3927206808
Short name	T2770
Test name
Test status
Simulation time	25262807344 ps
CPU time	269.98 seconds
Started	Apr 23 04:41:24 PM PDT 24
Finished	Apr 23 04:45:54 PM PDT 24
Peak memory	562816 kb
Host	smart-9205f197-af35-4a36-a872-bb6294cf4457
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927206808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3927206808
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.481165700
Short name	T490
Test name
Test status
Simulation time	55161664198 ps
CPU time	974.01 seconds
Started	Apr 23 04:41:20 PM PDT 24
Finished	Apr 23 04:57:34 PM PDT 24
Peak memory	562840 kb
Host	smart-a2cb0594-7728-401c-a941-8668146d91a8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481165700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.481165700
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.2034036414
Short name	T1315
Test name
Test status
Simulation time	233523530 ps
CPU time	24.68 seconds
Started	Apr 23 04:41:22 PM PDT 24
Finished	Apr 23 04:41:47 PM PDT 24
Peak memory	562752 kb
Host	smart-ef0c6355-b577-4345-aa8c-d2ae0f1d226c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034036414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.2034036414
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_same_source.775300517
Short name	T2564
Test name
Test status
Simulation time	550303813 ps
CPU time	42.57 seconds
Started	Apr 23 04:41:27 PM PDT 24
Finished	Apr 23 04:42:10 PM PDT 24
Peak memory	562720 kb
Host	smart-513fb1c8-6d24-479b-a2fb-233fa07f869d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775300517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.775300517
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke.3350807101
Short name	T2734
Test name
Test status
Simulation time	228523066 ps
CPU time	8.89 seconds
Started	Apr 23 04:41:21 PM PDT 24
Finished	Apr 23 04:41:30 PM PDT 24
Peak memory	562720 kb
Host	smart-e64469f8-a391-4284-8c9c-8e99ffcfdbe0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350807101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3350807101
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.3402754603
Short name	T2439
Test name
Test status
Simulation time	7772803329 ps
CPU time	84.39 seconds
Started	Apr 23 04:41:20 PM PDT 24
Finished	Apr 23 04:42:45 PM PDT 24
Peak memory	562764 kb
Host	smart-c33ca1d9-6d65-4bd4-9ec5-2189bfbd2b79
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402754603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3402754603
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2271578347
Short name	T2223
Test name
Test status
Simulation time	5932150494 ps
CPU time	108.91 seconds
Started	Apr 23 04:41:21 PM PDT 24
Finished	Apr 23 04:43:10 PM PDT 24
Peak memory	562808 kb
Host	smart-4d146271-8508-4c9d-9288-a05295833026
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271578347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2271578347
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3591963923
Short name	T2326
Test name
Test status
Simulation time	45461095 ps
CPU time	6.55 seconds
Started	Apr 23 04:41:25 PM PDT 24
Finished	Apr 23 04:41:32 PM PDT 24
Peak memory	562724 kb
Host	smart-1bbbc22f-341c-4ecc-996b-f62028cb5e81
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591963923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.3591963923
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all.1862398407
Short name	T2249
Test name
Test status
Simulation time	4523959678 ps
CPU time	383.98 seconds
Started	Apr 23 04:41:30 PM PDT 24
Finished	Apr 23 04:47:54 PM PDT 24
Peak memory	563968 kb
Host	smart-1d4c4b8b-f5d5-46ff-8807-3d20f85ed825
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862398407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1862398407
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.994528328
Short name	T2756
Test name
Test status
Simulation time	658198088 ps
CPU time	64.16 seconds
Started	Apr 23 04:41:27 PM PDT 24
Finished	Apr 23 04:42:31 PM PDT 24
Peak memory	562788 kb
Host	smart-cc049024-a69b-4781-a9fa-eb3dfde5278f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994528328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.994528328
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2680982925
Short name	T2639
Test name
Test status
Simulation time	10950454998 ps
CPU time	549.2 seconds
Started	Apr 23 04:41:26 PM PDT 24
Finished	Apr 23 04:50:36 PM PDT 24
Peak memory	572208 kb
Host	smart-161acea9-ff8d-4a5f-82f0-d3b4639e5ee5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680982925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.2680982925
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3652343320
Short name	T1662
Test name
Test status
Simulation time	160304603 ps
CPU time	53 seconds
Started	Apr 23 04:41:29 PM PDT 24
Finished	Apr 23 04:42:23 PM PDT 24
Peak memory	563340 kb
Host	smart-a0c8b767-fb07-480a-a9ef-70040201644e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652343320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.3652343320
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1915158556
Short name	T1944
Test name
Test status
Simulation time	304558317 ps
CPU time	37.05 seconds
Started	Apr 23 04:41:25 PM PDT 24
Finished	Apr 23 04:42:02 PM PDT 24
Peak memory	562800 kb
Host	smart-ea66b850-0d64-4910-94ac-8b8455ef148a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915158556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1915158556
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_aliasing.3389762434
Short name	T2177
Test name
Test status
Simulation time	63336865693 ps
CPU time	8522.43 seconds
Started	Apr 23 04:30:26 PM PDT 24
Finished	Apr 23 06:52:30 PM PDT 24
Peak memory	627244 kb
Host	smart-f3ca0a64-54d2-4ad8-8522-ad81dfab98e8
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389762434 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.3389762434
Directory	/workspace/4.chip_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.38507298
Short name	T2705
Test name
Test status
Simulation time	5863301361 ps
CPU time	537.27 seconds
Started	Apr 23 04:30:19 PM PDT 24
Finished	Apr 23 04:39:17 PM PDT 24
Peak memory	585056 kb
Host	smart-d439d945-e53b-4390-bd5c-51c68054d8bd
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38507298 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.38507298
Directory	/workspace/4.chip_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.3686995052
Short name	T1686
Test name
Test status
Simulation time	30864549691 ps
CPU time	3374.1 seconds
Started	Apr 23 04:30:26 PM PDT 24
Finished	Apr 23 05:26:41 PM PDT 24
Peak memory	585044 kb
Host	smart-7fcb9eb9-0114-4da3-992c-a450575d7dbd
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686995052 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.3686995052
Directory	/workspace/4.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_tl_errors.2613527929
Short name	T516
Test name
Test status
Simulation time	2829613526 ps
CPU time	176.64 seconds
Started	Apr 23 04:30:28 PM PDT 24
Finished	Apr 23 04:33:24 PM PDT 24
Peak memory	593412 kb
Host	smart-86fddd27-6716-442e-b19e-b27eb76bba5b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613527929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2613527929
Directory	/workspace/4.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_access_same_device.390138809
Short name	T2594
Test name
Test status
Simulation time	490792331 ps
CPU time	48.63 seconds
Started	Apr 23 04:30:42 PM PDT 24
Finished	Apr 23 04:31:30 PM PDT 24
Peak memory	562736 kb
Host	smart-2b9dcb22-2d02-4a15-a2c4-4655a9f4897e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390138809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.390138809
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3971792272
Short name	T2777
Test name
Test status
Simulation time	29156283454 ps
CPU time	544.04 seconds
Started	Apr 23 04:30:47 PM PDT 24
Finished	Apr 23 04:39:52 PM PDT 24
Peak memory	562840 kb
Host	smart-13874ef8-fc63-4163-b5a2-3c25085d890f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971792272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.3971792272
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1205456411
Short name	T2563
Test name
Test status
Simulation time	51269100 ps
CPU time	8.14 seconds
Started	Apr 23 04:30:51 PM PDT 24
Finished	Apr 23 04:31:00 PM PDT 24
Peak memory	562712 kb
Host	smart-3c305b76-9285-4126-9536-e2dd425a687a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205456411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1205456411
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_error_random.3860918229
Short name	T2645
Test name
Test status
Simulation time	1954554879 ps
CPU time	73.08 seconds
Started	Apr 23 04:30:50 PM PDT 24
Finished	Apr 23 04:32:03 PM PDT 24
Peak memory	562736 kb
Host	smart-637aed34-b1d9-4cb6-844a-5973f01fbb7f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860918229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3860918229
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_random.1054059185
Short name	T1997
Test name
Test status
Simulation time	2102988867 ps
CPU time	111.34 seconds
Started	Apr 23 04:30:42 PM PDT 24
Finished	Apr 23 04:32:34 PM PDT 24
Peak memory	562756 kb
Host	smart-e8e3ed58-de23-49e9-9e0b-1cce37d9f7b0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054059185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.1054059185
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_random_large_delays.2235895014
Short name	T1543
Test name
Test status
Simulation time	70953780037 ps
CPU time	797.97 seconds
Started	Apr 23 04:30:42 PM PDT 24
Finished	Apr 23 04:44:00 PM PDT 24
Peak memory	562792 kb
Host	smart-743eafc5-55cf-4272-9463-c75e9c65e04b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235895014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2235895014
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1215855687
Short name	T2106
Test name
Test status
Simulation time	6901703496 ps
CPU time	123.15 seconds
Started	Apr 23 04:30:43 PM PDT 24
Finished	Apr 23 04:32:47 PM PDT 24
Peak memory	562768 kb
Host	smart-29c7c369-4bed-4548-b141-7e7032d252f8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215855687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1215855687
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3753539927
Short name	T1415
Test name
Test status
Simulation time	361444034 ps
CPU time	33.08 seconds
Started	Apr 23 04:30:39 PM PDT 24
Finished	Apr 23 04:31:13 PM PDT 24
Peak memory	562720 kb
Host	smart-86a7fb78-56da-4ebe-a30f-4c57af57a318
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753539927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.3753539927
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_same_source.2289313697
Short name	T1809
Test name
Test status
Simulation time	123963156 ps
CPU time	12.04 seconds
Started	Apr 23 04:30:49 PM PDT 24
Finished	Apr 23 04:31:02 PM PDT 24
Peak memory	562716 kb
Host	smart-71cbfdcb-0e07-47b3-9f07-f89a478777f0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289313697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2289313697
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke.2443781889
Short name	T2196
Test name
Test status
Simulation time	49272049 ps
CPU time	6.65 seconds
Started	Apr 23 04:30:32 PM PDT 24
Finished	Apr 23 04:30:39 PM PDT 24
Peak memory	562716 kb
Host	smart-e8942717-b48b-4262-8c81-0ef02674721a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443781889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2443781889
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.3097704173
Short name	T1843
Test name
Test status
Simulation time	9459857380 ps
CPU time	98.67 seconds
Started	Apr 23 04:30:38 PM PDT 24
Finished	Apr 23 04:32:17 PM PDT 24
Peak memory	562800 kb
Host	smart-9cea9596-7bd7-499b-8a3e-bed9b67f4fa7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097704173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3097704173
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1172145574
Short name	T1656
Test name
Test status
Simulation time	5305785273 ps
CPU time	92.03 seconds
Started	Apr 23 04:30:41 PM PDT 24
Finished	Apr 23 04:32:13 PM PDT 24
Peak memory	562752 kb
Host	smart-2f585fee-cdbc-4b6a-82d4-284b71373806
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172145574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1172145574
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.414722582
Short name	T1768
Test name
Test status
Simulation time	44402745 ps
CPU time	6.8 seconds
Started	Apr 23 04:30:37 PM PDT 24
Finished	Apr 23 04:30:44 PM PDT 24
Peak memory	562696 kb
Host	smart-c875b804-e8f4-454b-a425-90105cbea8bb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414722582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays. 414722582
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all.1253211667
Short name	T2484
Test name
Test status
Simulation time	8939577289 ps
CPU time	319.31 seconds
Started	Apr 23 04:30:52 PM PDT 24
Finished	Apr 23 04:36:12 PM PDT 24
Peak memory	563904 kb
Host	smart-ab370ec3-9eea-4871-b896-6f9d7b86b437
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253211667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1253211667
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.829282217
Short name	T1935
Test name
Test status
Simulation time	3769960519 ps
CPU time	157.06 seconds
Started	Apr 23 04:31:01 PM PDT 24
Finished	Apr 23 04:33:39 PM PDT 24
Peak memory	562944 kb
Host	smart-d432ad7a-d3ef-405e-9de8-11558c14f481
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829282217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.829282217
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.4080970652
Short name	T2105
Test name
Test status
Simulation time	170232699 ps
CPU time	72.58 seconds
Started	Apr 23 04:31:01 PM PDT 24
Finished	Apr 23 04:32:14 PM PDT 24
Peak memory	563880 kb
Host	smart-9d14defe-6581-4521-9755-609af723961b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080970652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.4080970652
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3014007021
Short name	T2716
Test name
Test status
Simulation time	428566320 ps
CPU time	58.24 seconds
Started	Apr 23 04:31:07 PM PDT 24
Finished	Apr 23 04:32:06 PM PDT 24
Peak memory	563476 kb
Host	smart-67e4c5af-00ba-4b20-a9a3-6f8ed30a747f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014007021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.3014007021
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.41089702
Short name	T2065
Test name
Test status
Simulation time	96384326 ps
CPU time	14.82 seconds
Started	Apr 23 04:30:49 PM PDT 24
Finished	Apr 23 04:31:04 PM PDT 24
Peak memory	562816 kb
Host	smart-76444a08-9818-4a7e-84a5-556f46444d57
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.41089702
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_access_same_device.2112229125
Short name	T2736
Test name
Test status
Simulation time	1391800098 ps
CPU time	64.7 seconds
Started	Apr 23 04:41:29 PM PDT 24
Finished	Apr 23 04:42:34 PM PDT 24
Peak memory	562768 kb
Host	smart-461ddf6d-f8c8-43d4-89e9-a222da103913
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112229125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .2112229125
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.4071653711
Short name	T1711
Test name
Test status
Simulation time	68044071038 ps
CPU time	1205.29 seconds
Started	Apr 23 04:41:35 PM PDT 24
Finished	Apr 23 05:01:40 PM PDT 24
Peak memory	562896 kb
Host	smart-c038422b-215b-4961-a1b3-e332c8582554
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071653711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.4071653711
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.218968428
Short name	T1497
Test name
Test status
Simulation time	40526588 ps
CPU time	7.93 seconds
Started	Apr 23 04:41:36 PM PDT 24
Finished	Apr 23 04:41:44 PM PDT 24
Peak memory	562696 kb
Host	smart-4c4c16aa-63b0-4aed-b191-4c73425b6e1b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218968428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr .218968428
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_error_random.1561834568
Short name	T2579
Test name
Test status
Simulation time	1654454432 ps
CPU time	70.18 seconds
Started	Apr 23 04:41:36 PM PDT 24
Finished	Apr 23 04:42:46 PM PDT 24
Peak memory	562664 kb
Host	smart-afa76918-12c5-4b5a-9313-ab5f7cf4eba3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561834568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1561834568
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_random.3657002994
Short name	T2034
Test name
Test status
Simulation time	143751083 ps
CPU time	15.63 seconds
Started	Apr 23 04:41:33 PM PDT 24
Finished	Apr 23 04:41:49 PM PDT 24
Peak memory	562740 kb
Host	smart-0e590c56-92e9-4974-9f81-05eae184d875
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657002994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.3657002994
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_random_large_delays.62332104
Short name	T2109
Test name
Test status
Simulation time	63147649414 ps
CPU time	694.89 seconds
Started	Apr 23 04:41:30 PM PDT 24
Finished	Apr 23 04:53:05 PM PDT 24
Peak memory	562804 kb
Host	smart-b60a3393-989e-4fc2-adf3-675d34f3cbf7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62332104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.62332104
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.510657027
Short name	T2755
Test name
Test status
Simulation time	17495125449 ps
CPU time	310.24 seconds
Started	Apr 23 04:41:30 PM PDT 24
Finished	Apr 23 04:46:40 PM PDT 24
Peak memory	562796 kb
Host	smart-11f0d2c4-7c7e-4eb6-a917-9a24fe82d1a7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510657027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.510657027
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1091405809
Short name	T2102
Test name
Test status
Simulation time	41052199 ps
CPU time	7.16 seconds
Started	Apr 23 04:41:32 PM PDT 24
Finished	Apr 23 04:41:40 PM PDT 24
Peak memory	562724 kb
Host	smart-c3d1e10d-a0d1-431c-ad05-22537d721ea0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091405809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1091405809
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_same_source.2939932059
Short name	T1773
Test name
Test status
Simulation time	525396389 ps
CPU time	37.25 seconds
Started	Apr 23 04:41:34 PM PDT 24
Finished	Apr 23 04:42:12 PM PDT 24
Peak memory	562748 kb
Host	smart-30884846-095d-4504-907c-bde31087bc69
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939932059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2939932059
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke.2778929491
Short name	T2298
Test name
Test status
Simulation time	221112249 ps
CPU time	10.03 seconds
Started	Apr 23 04:41:30 PM PDT 24
Finished	Apr 23 04:41:41 PM PDT 24
Peak memory	562668 kb
Host	smart-c73e4a8f-9a16-46b5-8db2-3a73a981c3e9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778929491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2778929491
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1662908112
Short name	T2494
Test name
Test status
Simulation time	9407804863 ps
CPU time	99.62 seconds
Started	Apr 23 04:41:34 PM PDT 24
Finished	Apr 23 04:43:14 PM PDT 24
Peak memory	562720 kb
Host	smart-2de208f6-298c-4685-addf-b3d4470b8c97
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662908112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1662908112
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.802570808
Short name	T2268
Test name
Test status
Simulation time	5601986985 ps
CPU time	103.26 seconds
Started	Apr 23 04:41:31 PM PDT 24
Finished	Apr 23 04:43:15 PM PDT 24
Peak memory	562748 kb
Host	smart-059021b0-1018-40d3-82f1-bddab4e51d56
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802570808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.802570808
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2703269821
Short name	T1466
Test name
Test status
Simulation time	51981995 ps
CPU time	6.41 seconds
Started	Apr 23 04:41:32 PM PDT 24
Finished	Apr 23 04:41:38 PM PDT 24
Peak memory	562676 kb
Host	smart-e1ffbba6-2b9c-4d67-8914-163929a8559c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703269821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.2703269821
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all.1393010733
Short name	T2126
Test name
Test status
Simulation time	1513446531 ps
CPU time	136.82 seconds
Started	Apr 23 04:41:37 PM PDT 24
Finished	Apr 23 04:43:54 PM PDT 24
Peak memory	562936 kb
Host	smart-2b0f5b21-c5b8-4cc2-aeb1-0583c2d53777
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393010733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1393010733
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.2948342797
Short name	T2247
Test name
Test status
Simulation time	13825841501 ps
CPU time	481.79 seconds
Started	Apr 23 04:41:44 PM PDT 24
Finished	Apr 23 04:49:46 PM PDT 24
Peak memory	564000 kb
Host	smart-5c0ff6e9-2264-4875-b04a-e87183bfecc2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948342797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2948342797
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.4103339740
Short name	T1806
Test name
Test status
Simulation time	23168828 ps
CPU time	25.55 seconds
Started	Apr 23 04:41:40 PM PDT 24
Finished	Apr 23 04:42:06 PM PDT 24
Peak memory	562888 kb
Host	smart-76534238-eb31-4419-bc41-7277f7289963
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103339740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.4103339740
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.1577839082
Short name	T2156
Test name
Test status
Simulation time	7973341136 ps
CPU time	378.86 seconds
Started	Apr 23 04:41:44 PM PDT 24
Finished	Apr 23 04:48:03 PM PDT 24
Peak memory	572180 kb
Host	smart-a318ff19-7f53-4a01-b1bd-3f3f2b97bdb1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577839082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.1577839082
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.635225080
Short name	T455
Test name
Test status
Simulation time	112048682 ps
CPU time	9.49 seconds
Started	Apr 23 04:41:37 PM PDT 24
Finished	Apr 23 04:41:47 PM PDT 24
Peak memory	562764 kb
Host	smart-a9f7ff17-f030-4e3d-bbfe-654919e19385
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635225080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.635225080
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_access_same_device.4163271782
Short name	T1554
Test name
Test status
Simulation time	1115970279 ps
CPU time	78.63 seconds
Started	Apr 23 04:41:43 PM PDT 24
Finished	Apr 23 04:43:02 PM PDT 24
Peak memory	562780 kb
Host	smart-2fefbb46-38c3-43a1-ba5e-e8f3c0b29f39
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163271782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .4163271782
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2316399491
Short name	T1847
Test name
Test status
Simulation time	122072315322 ps
CPU time	2436.29 seconds
Started	Apr 23 04:41:50 PM PDT 24
Finished	Apr 23 05:22:27 PM PDT 24
Peak memory	562880 kb
Host	smart-e2f836de-28e1-44d2-bb43-5c44f1a5abff
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316399491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.2316399491
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.17187387
Short name	T1951
Test name
Test status
Simulation time	89560030 ps
CPU time	12.08 seconds
Started	Apr 23 04:41:50 PM PDT 24
Finished	Apr 23 04:42:02 PM PDT 24
Peak memory	562668 kb
Host	smart-0ae09b85-667a-4b71-975f-4b21a8d70cce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17187387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.17187387
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_error_random.426889494
Short name	T2623
Test name
Test status
Simulation time	611264442 ps
CPU time	25.19 seconds
Started	Apr 23 04:41:48 PM PDT 24
Finished	Apr 23 04:42:13 PM PDT 24
Peak memory	562636 kb
Host	smart-91d0a490-96ff-44e1-a122-a8512ca70e54
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426889494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.426889494
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_random.3761708759
Short name	T2710
Test name
Test status
Simulation time	991851572 ps
CPU time	39.51 seconds
Started	Apr 23 04:41:47 PM PDT 24
Finished	Apr 23 04:42:26 PM PDT 24
Peak memory	562720 kb
Host	smart-016a29bc-421d-4c23-94e1-925d204bbb44
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761708759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.3761708759
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_random_large_delays.580919298
Short name	T1343
Test name
Test status
Simulation time	62673393759 ps
CPU time	689.54 seconds
Started	Apr 23 04:41:43 PM PDT 24
Finished	Apr 23 04:53:13 PM PDT 24
Peak memory	562800 kb
Host	smart-381761a8-50dc-468f-88f2-76912a590aa9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580919298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.580919298
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.3188619152
Short name	T2141
Test name
Test status
Simulation time	46081828349 ps
CPU time	841.01 seconds
Started	Apr 23 04:41:44 PM PDT 24
Finished	Apr 23 04:55:46 PM PDT 24
Peak memory	562812 kb
Host	smart-61487cdd-6b4f-44ca-9982-cced2ec401c4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188619152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3188619152
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2466129327
Short name	T1674
Test name
Test status
Simulation time	196910515 ps
CPU time	20.33 seconds
Started	Apr 23 04:41:45 PM PDT 24
Finished	Apr 23 04:42:06 PM PDT 24
Peak memory	562696 kb
Host	smart-60a49768-8254-4da1-8ddc-746ddb37f77a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466129327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2466129327
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_same_source.3639683263
Short name	T2730
Test name
Test status
Simulation time	326087503 ps
CPU time	26.59 seconds
Started	Apr 23 04:41:48 PM PDT 24
Finished	Apr 23 04:42:14 PM PDT 24
Peak memory	562732 kb
Host	smart-402d2518-3e84-49d0-a0b5-c744c8bbfc1c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639683263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3639683263
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke.680531287
Short name	T1225
Test name
Test status
Simulation time	173671252 ps
CPU time	8.88 seconds
Started	Apr 23 04:41:41 PM PDT 24
Finished	Apr 23 04:41:50 PM PDT 24
Peak memory	562664 kb
Host	smart-321399b8-4ad1-41f2-89aa-65d55189d9f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680531287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.680531287
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.74375841
Short name	T596
Test name
Test status
Simulation time	7630910921 ps
CPU time	89.55 seconds
Started	Apr 23 04:41:46 PM PDT 24
Finished	Apr 23 04:43:16 PM PDT 24
Peak memory	562792 kb
Host	smart-1543d50a-d168-444a-b30f-1849c403a0a6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74375841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.74375841
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.475357008
Short name	T1755
Test name
Test status
Simulation time	5225765622 ps
CPU time	91.14 seconds
Started	Apr 23 04:41:42 PM PDT 24
Finished	Apr 23 04:43:13 PM PDT 24
Peak memory	562768 kb
Host	smart-c314ab39-3a37-470b-bb7f-0e618fde339d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475357008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.475357008
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2542193932
Short name	T2074
Test name
Test status
Simulation time	49585234 ps
CPU time	7.12 seconds
Started	Apr 23 04:41:42 PM PDT 24
Finished	Apr 23 04:41:49 PM PDT 24
Peak memory	562680 kb
Host	smart-c58c8402-aa84-4604-af54-1d14219c432e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542193932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.2542193932
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all.4290572353
Short name	T1960
Test name
Test status
Simulation time	11117914728 ps
CPU time	439.54 seconds
Started	Apr 23 04:41:46 PM PDT 24
Finished	Apr 23 04:49:06 PM PDT 24
Peak memory	563524 kb
Host	smart-46d1e204-2405-4fd6-a0bd-22d428d34247
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290572353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.4290572353
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1093019125
Short name	T1685
Test name
Test status
Simulation time	15362774953 ps
CPU time	626.1 seconds
Started	Apr 23 04:41:49 PM PDT 24
Finished	Apr 23 04:52:15 PM PDT 24
Peak memory	563992 kb
Host	smart-b7c8d144-29ed-4392-8812-f8e9a076389a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093019125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1093019125
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3191326662
Short name	T1980
Test name
Test status
Simulation time	63865850 ps
CPU time	28.82 seconds
Started	Apr 23 04:41:45 PM PDT 24
Finished	Apr 23 04:42:14 PM PDT 24
Peak memory	563108 kb
Host	smart-620f2d83-fab2-4ae8-a68e-09e745c1c62b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191326662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.3191326662
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1101266872
Short name	T1924
Test name
Test status
Simulation time	389058350 ps
CPU time	129.28 seconds
Started	Apr 23 04:41:51 PM PDT 24
Finished	Apr 23 04:44:01 PM PDT 24
Peak memory	563960 kb
Host	smart-3cc87eb1-9a26-4892-af42-e0750b56e789
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101266872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.1101266872
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.1354446124
Short name	T1958
Test name
Test status
Simulation time	915708199 ps
CPU time	39.74 seconds
Started	Apr 23 04:41:48 PM PDT 24
Finished	Apr 23 04:42:28 PM PDT 24
Peak memory	562792 kb
Host	smart-d76dcf81-1698-4597-a5fc-968a10f857dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354446124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1354446124
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_access_same_device.2477239165
Short name	T2283
Test name
Test status
Simulation time	2248683362 ps
CPU time	94.62 seconds
Started	Apr 23 04:41:51 PM PDT 24
Finished	Apr 23 04:43:26 PM PDT 24
Peak memory	562788 kb
Host	smart-f4131f91-18bc-4119-b68f-d42d01c8db36
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477239165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .2477239165
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.3793137544
Short name	T2002
Test name
Test status
Simulation time	34288827673 ps
CPU time	623.94 seconds
Started	Apr 23 04:41:54 PM PDT 24
Finished	Apr 23 04:52:18 PM PDT 24
Peak memory	562844 kb
Host	smart-982a0cec-e56a-4687-9eff-a00e9906ed3a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793137544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.3793137544
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3526239662
Short name	T1871
Test name
Test status
Simulation time	69343314 ps
CPU time	10.83 seconds
Started	Apr 23 04:41:52 PM PDT 24
Finished	Apr 23 04:42:03 PM PDT 24
Peak memory	562744 kb
Host	smart-b9eb7ec8-b901-4ffd-942a-63fac2297673
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526239662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.3526239662
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_error_random.764313556
Short name	T1240
Test name
Test status
Simulation time	1886336678 ps
CPU time	72.09 seconds
Started	Apr 23 04:41:53 PM PDT 24
Finished	Apr 23 04:43:05 PM PDT 24
Peak memory	562720 kb
Host	smart-68d3007a-4720-4896-a50f-5d6c1f65e9b0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764313556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.764313556
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_random.452885497
Short name	T2306
Test name
Test status
Simulation time	1629019370 ps
CPU time	62.67 seconds
Started	Apr 23 04:41:52 PM PDT 24
Finished	Apr 23 04:42:55 PM PDT 24
Peak memory	562760 kb
Host	smart-1b845fcb-08b7-4c28-872f-9b5dae231e1e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452885497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.452885497
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3372614954
Short name	T588
Test name
Test status
Simulation time	56583603165 ps
CPU time	606.53 seconds
Started	Apr 23 04:41:51 PM PDT 24
Finished	Apr 23 04:51:58 PM PDT 24
Peak memory	562828 kb
Host	smart-a5181517-0abb-451a-b7ce-8da98da05a5a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372614954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3372614954
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.3217703908
Short name	T2183
Test name
Test status
Simulation time	72877989738 ps
CPU time	1348.48 seconds
Started	Apr 23 04:41:56 PM PDT 24
Finished	Apr 23 05:04:24 PM PDT 24
Peak memory	562812 kb
Host	smart-8eee11ff-3fe5-48f7-ab5f-31a01475e6c0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217703908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3217703908
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.2727029889
Short name	T489
Test name
Test status
Simulation time	146447028 ps
CPU time	16.48 seconds
Started	Apr 23 04:41:55 PM PDT 24
Finished	Apr 23 04:42:11 PM PDT 24
Peak memory	562728 kb
Host	smart-cb19c07d-4397-4fcb-904d-9722f93bf2c7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727029889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.2727029889
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_same_source.195652482
Short name	T1476
Test name
Test status
Simulation time	309707378 ps
CPU time	21.67 seconds
Started	Apr 23 04:41:51 PM PDT 24
Finished	Apr 23 04:42:13 PM PDT 24
Peak memory	562724 kb
Host	smart-c6f73ae6-f373-4d09-aca2-57750ff675af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195652482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.195652482
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke.407692526
Short name	T2162
Test name
Test status
Simulation time	43504751 ps
CPU time	6.59 seconds
Started	Apr 23 04:41:48 PM PDT 24
Finished	Apr 23 04:41:55 PM PDT 24
Peak memory	562708 kb
Host	smart-2d908739-ba0c-4355-8458-0342a4797087
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407692526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.407692526
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.913102066
Short name	T1451
Test name
Test status
Simulation time	7172111642 ps
CPU time	86.36 seconds
Started	Apr 23 04:41:52 PM PDT 24
Finished	Apr 23 04:43:18 PM PDT 24
Peak memory	562776 kb
Host	smart-c7ee35eb-7c30-483d-a892-ef87b20f704a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913102066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.913102066
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.515589735
Short name	T2423
Test name
Test status
Simulation time	5185581321 ps
CPU time	93.89 seconds
Started	Apr 23 04:41:54 PM PDT 24
Finished	Apr 23 04:43:28 PM PDT 24
Peak memory	562776 kb
Host	smart-c8d1eb0c-7fba-4cd3-9c69-d2561fa5231a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515589735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.515589735
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.813328870
Short name	T2152
Test name
Test status
Simulation time	50053651 ps
CPU time	7.03 seconds
Started	Apr 23 04:41:54 PM PDT 24
Finished	Apr 23 04:42:02 PM PDT 24
Peak memory	562648 kb
Host	smart-d84996b9-f980-4621-8979-b580d905704c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813328870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays .813328870
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all.1757607683
Short name	T1639
Test name
Test status
Simulation time	4308439310 ps
CPU time	364.07 seconds
Started	Apr 23 04:41:56 PM PDT 24
Finished	Apr 23 04:48:00 PM PDT 24
Peak memory	563928 kb
Host	smart-acd25722-135d-4d18-8896-b427e8ba3545
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757607683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1757607683
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2446796274
Short name	T417
Test name
Test status
Simulation time	1681189387 ps
CPU time	226.63 seconds
Started	Apr 23 04:41:58 PM PDT 24
Finished	Apr 23 04:45:45 PM PDT 24
Peak memory	572148 kb
Host	smart-0e2eb1a5-5a27-4940-9b53-d5fb21cbfa6a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446796274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.2446796274
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.2858435218
Short name	T2046
Test name
Test status
Simulation time	14552299520 ps
CPU time	691.59 seconds
Started	Apr 23 04:41:55 PM PDT 24
Finished	Apr 23 04:53:27 PM PDT 24
Peak memory	572220 kb
Host	smart-45d62cad-1ebe-4c8c-a323-3608b8f7e1f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858435218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.2858435218
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.735204629
Short name	T2693
Test name
Test status
Simulation time	124921967 ps
CPU time	18.84 seconds
Started	Apr 23 04:41:52 PM PDT 24
Finished	Apr 23 04:42:12 PM PDT 24
Peak memory	562772 kb
Host	smart-ab715c08-3ad0-4326-a0a9-8fd560ca7535
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735204629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.735204629
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_access_same_device.2051289180
Short name	T1870
Test name
Test status
Simulation time	431443859 ps
CPU time	34.12 seconds
Started	Apr 23 04:42:01 PM PDT 24
Finished	Apr 23 04:42:36 PM PDT 24
Peak memory	562700 kb
Host	smart-5b7e1559-7bd2-4d01-89b4-6c79990df69d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051289180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .2051289180
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.545186986
Short name	T2565
Test name
Test status
Simulation time	53797862051 ps
CPU time	1038.36 seconds
Started	Apr 23 04:42:03 PM PDT 24
Finished	Apr 23 04:59:22 PM PDT 24
Peak memory	562800 kb
Host	smart-bc0461fa-fc1b-4299-b84c-e262fb3beecf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545186986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_d evice_slow_rsp.545186986
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3889808614
Short name	T1885
Test name
Test status
Simulation time	1274092419 ps
CPU time	46.72 seconds
Started	Apr 23 04:42:04 PM PDT 24
Finished	Apr 23 04:42:51 PM PDT 24
Peak memory	562740 kb
Host	smart-1e0a595b-1e8b-49e3-b516-692efcca424a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889808614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.3889808614
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_error_random.3239258449
Short name	T1372
Test name
Test status
Simulation time	147408423 ps
CPU time	7.91 seconds
Started	Apr 23 04:42:05 PM PDT 24
Finished	Apr 23 04:42:13 PM PDT 24
Peak memory	562668 kb
Host	smart-9aae1328-609c-4284-b01d-b92ac59b5af0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239258449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3239258449
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_random.2525104465
Short name	T1989
Test name
Test status
Simulation time	1812782367 ps
CPU time	65.59 seconds
Started	Apr 23 04:41:58 PM PDT 24
Finished	Apr 23 04:43:04 PM PDT 24
Peak memory	562716 kb
Host	smart-e2edb674-f611-40ac-be1b-af089d6702b6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525104465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.2525104465
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2302153620
Short name	T1706
Test name
Test status
Simulation time	60510941003 ps
CPU time	708.4 seconds
Started	Apr 23 04:42:01 PM PDT 24
Finished	Apr 23 04:53:49 PM PDT 24
Peak memory	562820 kb
Host	smart-65b855ad-7b20-4a8e-a708-ee5da93f8f6f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302153620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2302153620
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.327529004
Short name	T545
Test name
Test status
Simulation time	56327018050 ps
CPU time	949.26 seconds
Started	Apr 23 04:42:02 PM PDT 24
Finished	Apr 23 04:57:52 PM PDT 24
Peak memory	562760 kb
Host	smart-7f1f0f38-c47d-48da-981e-69ff556a058d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327529004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.327529004
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.634021940
Short name	T2132
Test name
Test status
Simulation time	196361029 ps
CPU time	20.28 seconds
Started	Apr 23 04:42:01 PM PDT 24
Finished	Apr 23 04:42:22 PM PDT 24
Peak memory	562740 kb
Host	smart-d4242e91-cdae-44e7-a781-f93c265eb5a5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634021940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_dela ys.634021940
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_same_source.1824892896
Short name	T2242
Test name
Test status
Simulation time	160050836 ps
CPU time	16.58 seconds
Started	Apr 23 04:42:02 PM PDT 24
Finished	Apr 23 04:42:19 PM PDT 24
Peak memory	562656 kb
Host	smart-d895fdfd-8ba2-42d0-be53-595ad967e9fa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824892896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1824892896
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke.114331719
Short name	T2443
Test name
Test status
Simulation time	216093566 ps
CPU time	8.51 seconds
Started	Apr 23 04:41:57 PM PDT 24
Finished	Apr 23 04:42:05 PM PDT 24
Peak memory	562652 kb
Host	smart-f9229f79-6fb5-46f8-a05a-db1e58df6493
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114331719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.114331719
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.472296432
Short name	T1889
Test name
Test status
Simulation time	8245354734 ps
CPU time	93.63 seconds
Started	Apr 23 04:41:59 PM PDT 24
Finished	Apr 23 04:43:33 PM PDT 24
Peak memory	562800 kb
Host	smart-f83a8740-ddd3-4808-a3e4-7b32bb70ddde
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472296432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.472296432
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3280859926
Short name	T1371
Test name
Test status
Simulation time	4454048308 ps
CPU time	78.32 seconds
Started	Apr 23 04:41:57 PM PDT 24
Finished	Apr 23 04:43:16 PM PDT 24
Peak memory	562732 kb
Host	smart-cbad4c33-27d3-49b8-ad34-fd2d244f1aa1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280859926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3280859926
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2968130297
Short name	T1222
Test name
Test status
Simulation time	36424648 ps
CPU time	6.25 seconds
Started	Apr 23 04:41:59 PM PDT 24
Finished	Apr 23 04:42:06 PM PDT 24
Peak memory	562696 kb
Host	smart-bc25400e-9884-4742-b2b7-45be1aaa8812
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968130297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.2968130297
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all.3666327158
Short name	T1558
Test name
Test status
Simulation time	656855641 ps
CPU time	23.69 seconds
Started	Apr 23 04:42:06 PM PDT 24
Finished	Apr 23 04:42:30 PM PDT 24
Peak memory	562760 kb
Host	smart-14d2b7ad-7e13-46f0-b06a-ab9a162911d1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666327158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3666327158
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1706816732
Short name	T1458
Test name
Test status
Simulation time	668853888 ps
CPU time	50.91 seconds
Started	Apr 23 04:42:09 PM PDT 24
Finished	Apr 23 04:43:00 PM PDT 24
Peak memory	562776 kb
Host	smart-0321053e-c89f-4e2f-9b24-2026993481e1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706816732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1706816732
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3035787886
Short name	T779
Test name
Test status
Simulation time	5580378565 ps
CPU time	372.46 seconds
Started	Apr 23 04:42:09 PM PDT 24
Finished	Apr 23 04:48:22 PM PDT 24
Peak memory	572236 kb
Host	smart-bc746ece-393a-4849-9944-c26b80fdf791
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035787886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.3035787886
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.4195855390
Short name	T483
Test name
Test status
Simulation time	752868037 ps
CPU time	37.16 seconds
Started	Apr 23 04:42:01 PM PDT 24
Finished	Apr 23 04:42:38 PM PDT 24
Peak memory	562808 kb
Host	smart-698cc239-a026-44ef-88fa-884afc222c7c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195855390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.4195855390
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_access_same_device.3040381241
Short name	T2467
Test name
Test status
Simulation time	1498114784 ps
CPU time	70.98 seconds
Started	Apr 23 04:42:15 PM PDT 24
Finished	Apr 23 04:43:26 PM PDT 24
Peak memory	562720 kb
Host	smart-400455e7-fb10-4e22-a65f-11bef3f85004
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040381241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .3040381241
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1675141343
Short name	T1751
Test name
Test status
Simulation time	66390193567 ps
CPU time	1181.01 seconds
Started	Apr 23 04:42:11 PM PDT 24
Finished	Apr 23 05:01:52 PM PDT 24
Peak memory	562836 kb
Host	smart-7dd6fc7d-7ca7-401b-97bd-33e4d72dc624
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675141343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.1675141343
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.716520666
Short name	T2444
Test name
Test status
Simulation time	1012484475 ps
CPU time	43.55 seconds
Started	Apr 23 04:42:13 PM PDT 24
Finished	Apr 23 04:42:57 PM PDT 24
Peak memory	562668 kb
Host	smart-ea6d69ea-98c8-495f-961e-07e5dc2fc790
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716520666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr .716520666
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_error_random.1795132199
Short name	T1284
Test name
Test status
Simulation time	31302653 ps
CPU time	5.97 seconds
Started	Apr 23 04:42:17 PM PDT 24
Finished	Apr 23 04:42:23 PM PDT 24
Peak memory	562704 kb
Host	smart-15560513-536a-493d-b917-70c8898a25e3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795132199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1795132199
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_random.3008067969
Short name	T1982
Test name
Test status
Simulation time	1906113226 ps
CPU time	73.02 seconds
Started	Apr 23 04:42:07 PM PDT 24
Finished	Apr 23 04:43:21 PM PDT 24
Peak memory	562716 kb
Host	smart-c70d64bb-b9d0-43aa-acb0-fc407cbe67f5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008067969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.3008067969
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_random_large_delays.1444647109
Short name	T540
Test name
Test status
Simulation time	76684575985 ps
CPU time	878.34 seconds
Started	Apr 23 04:42:13 PM PDT 24
Finished	Apr 23 04:56:52 PM PDT 24
Peak memory	562848 kb
Host	smart-84c51403-9913-4692-81a2-5770544155f4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444647109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1444647109
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3190283350
Short name	T447
Test name
Test status
Simulation time	24578332135 ps
CPU time	457.62 seconds
Started	Apr 23 04:42:15 PM PDT 24
Finished	Apr 23 04:49:53 PM PDT 24
Peak memory	562764 kb
Host	smart-8fed1a54-2e31-405b-8410-78cc1ba542bd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190283350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3190283350
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.2224654079
Short name	T1414
Test name
Test status
Simulation time	252068127 ps
CPU time	24.1 seconds
Started	Apr 23 04:42:08 PM PDT 24
Finished	Apr 23 04:42:33 PM PDT 24
Peak memory	562736 kb
Host	smart-bbd307e6-aff5-498e-9079-d3eca5cef929
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224654079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.2224654079
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_same_source.3477568300
Short name	T1841
Test name
Test status
Simulation time	196425779 ps
CPU time	16.79 seconds
Started	Apr 23 04:42:14 PM PDT 24
Finished	Apr 23 04:42:32 PM PDT 24
Peak memory	562748 kb
Host	smart-f467f930-14d2-489a-9b4f-ad7d982e1f4c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477568300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3477568300
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke.2099833598
Short name	T2744
Test name
Test status
Simulation time	185304666 ps
CPU time	8.91 seconds
Started	Apr 23 04:42:04 PM PDT 24
Finished	Apr 23 04:42:14 PM PDT 24
Peak memory	562672 kb
Host	smart-94eb2791-101b-434b-83c2-0a2345baf9ec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099833598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2099833598
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.3010124640
Short name	T2010
Test name
Test status
Simulation time	6018250389 ps
CPU time	66.09 seconds
Started	Apr 23 04:42:08 PM PDT 24
Finished	Apr 23 04:43:14 PM PDT 24
Peak memory	562764 kb
Host	smart-94521e2d-9042-4dce-b1d1-3b29c6b88229
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010124640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3010124640
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1079169491
Short name	T1811
Test name
Test status
Simulation time	5115650619 ps
CPU time	88.58 seconds
Started	Apr 23 04:42:08 PM PDT 24
Finished	Apr 23 04:43:37 PM PDT 24
Peak memory	562772 kb
Host	smart-73ac7012-6014-4917-96bd-d329de4279c3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079169491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1079169491
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.623987821
Short name	T1600
Test name
Test status
Simulation time	36400181 ps
CPU time	6.12 seconds
Started	Apr 23 04:42:06 PM PDT 24
Finished	Apr 23 04:42:12 PM PDT 24
Peak memory	562704 kb
Host	smart-eedce268-4713-4c1d-a52c-2a6b947848c7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623987821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays .623987821
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all.871219314
Short name	T1719
Test name
Test status
Simulation time	12226594647 ps
CPU time	460.91 seconds
Started	Apr 23 04:42:18 PM PDT 24
Finished	Apr 23 04:50:00 PM PDT 24
Peak memory	572224 kb
Host	smart-7a735a09-f9cb-4e87-ab56-75d71b5c4813
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871219314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.871219314
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.4183446631
Short name	T2160
Test name
Test status
Simulation time	701097851 ps
CPU time	52.97 seconds
Started	Apr 23 04:42:17 PM PDT 24
Finished	Apr 23 04:43:10 PM PDT 24
Peak memory	562740 kb
Host	smart-fcc8d84c-f772-4c9e-bc46-c3bda8858686
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183446631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.4183446631
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3131919610
Short name	T2700
Test name
Test status
Simulation time	719822443 ps
CPU time	337.29 seconds
Started	Apr 23 04:42:17 PM PDT 24
Finished	Apr 23 04:47:55 PM PDT 24
Peak memory	572124 kb
Host	smart-dbc23fd9-16cb-45b1-b219-06fbb30de02c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131919610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.3131919610
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2029873478
Short name	T1278
Test name
Test status
Simulation time	115214397 ps
CPU time	42.9 seconds
Started	Apr 23 04:42:17 PM PDT 24
Finished	Apr 23 04:43:00 PM PDT 24
Peak memory	563328 kb
Host	smart-90c3932e-79d9-4c64-bc36-57d3ba310db9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029873478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.2029873478
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2154281859
Short name	T1484
Test name
Test status
Simulation time	76040338 ps
CPU time	7.1 seconds
Started	Apr 23 04:42:13 PM PDT 24
Finished	Apr 23 04:42:20 PM PDT 24
Peak memory	562692 kb
Host	smart-20bcf70e-ff2b-4166-8a15-3917563cb8eb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154281859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2154281859
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_access_same_device.823133234
Short name	T1846
Test name
Test status
Simulation time	973527522 ps
CPU time	80.01 seconds
Started	Apr 23 04:42:20 PM PDT 24
Finished	Apr 23 04:43:40 PM PDT 24
Peak memory	562736 kb
Host	smart-fdae38ac-d1b3-4c01-9fa9-b70ee353afb4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823133234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device. 823133234
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1442152324
Short name	T2275
Test name
Test status
Simulation time	113469482281 ps
CPU time	1850.28 seconds
Started	Apr 23 04:42:22 PM PDT 24
Finished	Apr 23 05:13:13 PM PDT 24
Peak memory	562904 kb
Host	smart-baf26683-da09-4c2e-9267-fad685073f56
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442152324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.1442152324
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.4112011153
Short name	T1691
Test name
Test status
Simulation time	289084958 ps
CPU time	30.12 seconds
Started	Apr 23 04:42:27 PM PDT 24
Finished	Apr 23 04:42:57 PM PDT 24
Peak memory	562732 kb
Host	smart-241d3f4c-8968-4147-8b81-d747c76220c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112011153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.4112011153
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_error_random.571553630
Short name	T1615
Test name
Test status
Simulation time	118041036 ps
CPU time	7.05 seconds
Started	Apr 23 04:42:25 PM PDT 24
Finished	Apr 23 04:42:33 PM PDT 24
Peak memory	562652 kb
Host	smart-f73fccd7-dbc3-436f-8c35-99c619f7dcd5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571553630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.571553630
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_random.105052376
Short name	T1804
Test name
Test status
Simulation time	835245355 ps
CPU time	34.19 seconds
Started	Apr 23 04:42:25 PM PDT 24
Finished	Apr 23 04:43:00 PM PDT 24
Peak memory	562656 kb
Host	smart-fd3fdbec-4670-46b6-84a9-7e23f130ee27
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105052376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.105052376
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2164067184
Short name	T1633
Test name
Test status
Simulation time	3473959758 ps
CPU time	37.01 seconds
Started	Apr 23 04:42:21 PM PDT 24
Finished	Apr 23 04:42:58 PM PDT 24
Peak memory	562768 kb
Host	smart-7f00f53b-0f48-4ed8-994d-07f72485678f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164067184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2164067184
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.2468201763
Short name	T2712
Test name
Test status
Simulation time	20579883189 ps
CPU time	385.47 seconds
Started	Apr 23 04:42:26 PM PDT 24
Finished	Apr 23 04:48:52 PM PDT 24
Peak memory	562720 kb
Host	smart-99a3c844-c9d4-4e19-8d05-4d5d226a6f5e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468201763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2468201763
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.831784513
Short name	T1261
Test name
Test status
Simulation time	35055503 ps
CPU time	6.05 seconds
Started	Apr 23 04:42:24 PM PDT 24
Finished	Apr 23 04:42:30 PM PDT 24
Peak memory	562700 kb
Host	smart-82ce04af-0067-4ab6-8db2-f2a96703908b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831784513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_dela ys.831784513
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_same_source.2801153095
Short name	T2405
Test name
Test status
Simulation time	522112852 ps
CPU time	17.8 seconds
Started	Apr 23 04:42:19 PM PDT 24
Finished	Apr 23 04:42:38 PM PDT 24
Peak memory	562756 kb
Host	smart-8de04d95-aa90-401b-b8dc-ec72fbffea7a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801153095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2801153095
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke.2020868725
Short name	T1505
Test name
Test status
Simulation time	170138430 ps
CPU time	8.52 seconds
Started	Apr 23 04:42:16 PM PDT 24
Finished	Apr 23 04:42:25 PM PDT 24
Peak memory	562676 kb
Host	smart-7e835a5b-eb90-4a12-b6aa-3971462aeaed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020868725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2020868725
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.2745567096
Short name	T1266
Test name
Test status
Simulation time	8147885298 ps
CPU time	94.14 seconds
Started	Apr 23 04:42:20 PM PDT 24
Finished	Apr 23 04:43:54 PM PDT 24
Peak memory	562736 kb
Host	smart-f8f9eba3-a07f-4672-92be-8ed1f6eecf71
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745567096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2745567096
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2775381854
Short name	T1433
Test name
Test status
Simulation time	4811015066 ps
CPU time	85.08 seconds
Started	Apr 23 04:42:26 PM PDT 24
Finished	Apr 23 04:43:51 PM PDT 24
Peak memory	562780 kb
Host	smart-b1998e58-b177-4cae-9b5a-a70b01ddfbda
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775381854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2775381854
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2847221738
Short name	T1402
Test name
Test status
Simulation time	44217685 ps
CPU time	6.65 seconds
Started	Apr 23 04:42:26 PM PDT 24
Finished	Apr 23 04:42:33 PM PDT 24
Peak memory	562612 kb
Host	smart-e70e5cc2-be10-4705-94e6-7dd0f41570e2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847221738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.2847221738
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all.2924377340
Short name	T2668
Test name
Test status
Simulation time	3224930228 ps
CPU time	323.08 seconds
Started	Apr 23 04:42:27 PM PDT 24
Finished	Apr 23 04:47:51 PM PDT 24
Peak memory	564020 kb
Host	smart-3ce37ae0-c055-4831-a5db-060206d94058
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924377340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2924377340
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.2731692568
Short name	T768
Test name
Test status
Simulation time	3411674056 ps
CPU time	219.33 seconds
Started	Apr 23 04:42:26 PM PDT 24
Finished	Apr 23 04:46:06 PM PDT 24
Peak memory	562992 kb
Host	smart-559277c9-5cbe-4d86-b326-aab4f919ff5c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731692568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2731692568
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1062381413
Short name	T460
Test name
Test status
Simulation time	6790728020 ps
CPU time	777.46 seconds
Started	Apr 23 04:42:21 PM PDT 24
Finished	Apr 23 04:55:19 PM PDT 24
Peak memory	572160 kb
Host	smart-9e926ed3-070a-4acb-adb3-3851c205bccb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062381413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.1062381413
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2225238496
Short name	T2432
Test name
Test status
Simulation time	2854798086 ps
CPU time	363.39 seconds
Started	Apr 23 04:42:25 PM PDT 24
Finished	Apr 23 04:48:29 PM PDT 24
Peak memory	572176 kb
Host	smart-ee9ef441-96ca-460b-b06e-f078f05565a5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225238496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.2225238496
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.2700390934
Short name	T2413
Test name
Test status
Simulation time	966582675 ps
CPU time	39.1 seconds
Started	Apr 23 04:42:23 PM PDT 24
Finished	Apr 23 04:43:02 PM PDT 24
Peak memory	562772 kb
Host	smart-261d82ec-ddf8-4bbd-91bc-29469da6b7b0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700390934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2700390934
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_access_same_device.3322328535
Short name	T2441
Test name
Test status
Simulation time	3104327414 ps
CPU time	136.61 seconds
Started	Apr 23 04:42:32 PM PDT 24
Finished	Apr 23 04:44:49 PM PDT 24
Peak memory	562832 kb
Host	smart-3f78b146-1f38-4846-aad2-fd3b007b822e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322328535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .3322328535
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2063901431
Short name	T1401
Test name
Test status
Simulation time	36670466831 ps
CPU time	704.85 seconds
Started	Apr 23 04:42:30 PM PDT 24
Finished	Apr 23 04:54:15 PM PDT 24
Peak memory	562820 kb
Host	smart-abbe6483-1f76-4e8b-866b-b1e2f50b2d66
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063901431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.2063901431
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2286831998
Short name	T1963
Test name
Test status
Simulation time	1447016957 ps
CPU time	60.84 seconds
Started	Apr 23 04:42:33 PM PDT 24
Finished	Apr 23 04:43:34 PM PDT 24
Peak memory	562712 kb
Host	smart-9e466397-68ea-486d-8ac4-f6ca423d5fd3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286831998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.2286831998
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_error_random.879054897
Short name	T1367
Test name
Test status
Simulation time	518576541 ps
CPU time	18.06 seconds
Started	Apr 23 04:42:31 PM PDT 24
Finished	Apr 23 04:42:49 PM PDT 24
Peak memory	562732 kb
Host	smart-9601bac2-d264-47af-a3e6-6f7841b70bc5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879054897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.879054897
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_random.4209632771
Short name	T440
Test name
Test status
Simulation time	2308406131 ps
CPU time	95.05 seconds
Started	Apr 23 04:42:26 PM PDT 24
Finished	Apr 23 04:44:01 PM PDT 24
Peak memory	562804 kb
Host	smart-5bef1f6b-c647-4956-97f5-12958e1494a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209632771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.4209632771
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_random_large_delays.3436943065
Short name	T1820
Test name
Test status
Simulation time	56874136335 ps
CPU time	649.82 seconds
Started	Apr 23 04:42:27 PM PDT 24
Finished	Apr 23 04:53:17 PM PDT 24
Peak memory	562756 kb
Host	smart-124ab2ea-4f59-4d3a-acd3-81f375b84b31
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436943065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3436943065
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2320389789
Short name	T1429
Test name
Test status
Simulation time	51517155519 ps
CPU time	972.97 seconds
Started	Apr 23 04:42:27 PM PDT 24
Finished	Apr 23 04:58:40 PM PDT 24
Peak memory	562772 kb
Host	smart-21b5f77b-6404-434b-b8de-e3034b5047ce
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320389789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2320389789
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.2513759524
Short name	T1355
Test name
Test status
Simulation time	594330185 ps
CPU time	53.2 seconds
Started	Apr 23 04:42:25 PM PDT 24
Finished	Apr 23 04:43:19 PM PDT 24
Peak memory	562748 kb
Host	smart-3547bf81-07fc-4e41-8d50-e2373ce777e4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513759524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.2513759524
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_same_source.1172760032
Short name	T2295
Test name
Test status
Simulation time	507632926 ps
CPU time	37.37 seconds
Started	Apr 23 04:42:29 PM PDT 24
Finished	Apr 23 04:43:07 PM PDT 24
Peak memory	562768 kb
Host	smart-55c186e1-0b45-4034-8e9d-72f183758bcc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172760032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1172760032
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke.2983034917
Short name	T2314
Test name
Test status
Simulation time	49864919 ps
CPU time	6.14 seconds
Started	Apr 23 04:42:28 PM PDT 24
Finished	Apr 23 04:42:34 PM PDT 24
Peak memory	562676 kb
Host	smart-3647b163-ffc8-4b03-a0d0-b1388b62259e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983034917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2983034917
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.4233919763
Short name	T1337
Test name
Test status
Simulation time	7976647195 ps
CPU time	85.93 seconds
Started	Apr 23 04:42:26 PM PDT 24
Finished	Apr 23 04:43:52 PM PDT 24
Peak memory	562792 kb
Host	smart-622a01a3-2b38-4391-80a5-1765bd673bea
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233919763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.4233919763
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1233394071
Short name	T2301
Test name
Test status
Simulation time	6341003150 ps
CPU time	109.58 seconds
Started	Apr 23 04:42:27 PM PDT 24
Finished	Apr 23 04:44:17 PM PDT 24
Peak memory	562788 kb
Host	smart-b250145b-0868-4c5d-b59b-a2a764edd9f1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233394071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1233394071
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3625038419
Short name	T1224
Test name
Test status
Simulation time	49428465 ps
CPU time	6.37 seconds
Started	Apr 23 04:42:25 PM PDT 24
Finished	Apr 23 04:42:32 PM PDT 24
Peak memory	562636 kb
Host	smart-43fc4dbb-e0b4-4ce9-a47b-08d6a06181da
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625038419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.3625038419
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.1775333732
Short name	T2544
Test name
Test status
Simulation time	2569689827 ps
CPU time	210.86 seconds
Started	Apr 23 04:42:34 PM PDT 24
Finished	Apr 23 04:46:05 PM PDT 24
Peak memory	563996 kb
Host	smart-01c52c06-bd07-4f9b-99f8-58bb351f705d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775333732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1775333732
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1976727635
Short name	T818
Test name
Test status
Simulation time	221546319 ps
CPU time	153.71 seconds
Started	Apr 23 04:42:33 PM PDT 24
Finished	Apr 23 04:45:07 PM PDT 24
Peak memory	563952 kb
Host	smart-6a59ae2d-98b1-49e4-993c-01d8cf414458
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976727635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1976727635
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3442127127
Short name	T781
Test name
Test status
Simulation time	7924688369 ps
CPU time	525.41 seconds
Started	Apr 23 04:42:33 PM PDT 24
Finished	Apr 23 04:51:19 PM PDT 24
Peak memory	572212 kb
Host	smart-8cd76302-756c-4237-a7bf-12680b5c3037
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442127127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.3442127127
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.899275322
Short name	T2394
Test name
Test status
Simulation time	606656081 ps
CPU time	28.96 seconds
Started	Apr 23 04:42:34 PM PDT 24
Finished	Apr 23 04:43:03 PM PDT 24
Peak memory	562760 kb
Host	smart-a3e1abf2-e147-4860-91b0-5e5a2cc63e48
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899275322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.899275322
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_access_same_device.3215765472
Short name	T2180
Test name
Test status
Simulation time	1387322916 ps
CPU time	72.02 seconds
Started	Apr 23 04:42:37 PM PDT 24
Finished	Apr 23 04:43:49 PM PDT 24
Peak memory	562716 kb
Host	smart-56af9ca8-3973-4a78-b1ad-0911e799bff3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215765472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .3215765472
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2208933020
Short name	T770
Test name
Test status
Simulation time	31251822501 ps
CPU time	526.2 seconds
Started	Apr 23 04:42:36 PM PDT 24
Finished	Apr 23 04:51:22 PM PDT 24
Peak memory	562804 kb
Host	smart-5689d46c-37b0-4044-b2e9-65573889ad36
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208933020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.2208933020
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.3256020765
Short name	T1407
Test name
Test status
Simulation time	292922471 ps
CPU time	33.77 seconds
Started	Apr 23 04:42:40 PM PDT 24
Finished	Apr 23 04:43:14 PM PDT 24
Peak memory	562740 kb
Host	smart-3a5c88c8-cccd-4dee-9596-f7b92d7220c8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256020765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.3256020765
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_error_random.4052783545
Short name	T1742
Test name
Test status
Simulation time	337967902 ps
CPU time	35.85 seconds
Started	Apr 23 04:42:40 PM PDT 24
Finished	Apr 23 04:43:17 PM PDT 24
Peak memory	562688 kb
Host	smart-2d0478d8-568a-4ea5-9d5b-319c55c9e708
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052783545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.4052783545
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_random.1921804708
Short name	T1907
Test name
Test status
Simulation time	1711136538 ps
CPU time	71.08 seconds
Started	Apr 23 04:42:36 PM PDT 24
Finished	Apr 23 04:43:47 PM PDT 24
Peak memory	562764 kb
Host	smart-53e5a022-c37e-47d4-b92c-9e37482abf8c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921804708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.1921804708
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3476096116
Short name	T2179
Test name
Test status
Simulation time	104767215328 ps
CPU time	1262.96 seconds
Started	Apr 23 04:42:36 PM PDT 24
Finished	Apr 23 05:03:40 PM PDT 24
Peak memory	562864 kb
Host	smart-9e1012ae-f982-40f6-b1dc-8526cc856e4c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476096116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3476096116
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.500693945
Short name	T2239
Test name
Test status
Simulation time	68520256969 ps
CPU time	1209.93 seconds
Started	Apr 23 04:42:38 PM PDT 24
Finished	Apr 23 05:02:49 PM PDT 24
Peak memory	562824 kb
Host	smart-31bb6300-a444-481f-a7ea-8c82a91b7458
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500693945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.500693945
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.540905128
Short name	T2426
Test name
Test status
Simulation time	250981466 ps
CPU time	24.72 seconds
Started	Apr 23 04:42:39 PM PDT 24
Finished	Apr 23 04:43:04 PM PDT 24
Peak memory	562772 kb
Host	smart-8b481328-72cd-4fa6-9295-3a90eb48bdab
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540905128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_dela ys.540905128
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_same_source.251940618
Short name	T2212
Test name
Test status
Simulation time	128277106 ps
CPU time	12.94 seconds
Started	Apr 23 04:42:40 PM PDT 24
Finished	Apr 23 04:42:53 PM PDT 24
Peak memory	562744 kb
Host	smart-e25cadee-14c3-4449-aa91-11b1c5f16ae4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251940618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.251940618
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke.1313779963
Short name	T2524
Test name
Test status
Simulation time	237052515 ps
CPU time	10.82 seconds
Started	Apr 23 04:42:31 PM PDT 24
Finished	Apr 23 04:42:42 PM PDT 24
Peak memory	562648 kb
Host	smart-fcd9aadf-b981-44d2-916c-6874eb3026e2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313779963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1313779963
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.1013724855
Short name	T2691
Test name
Test status
Simulation time	8730860065 ps
CPU time	103.76 seconds
Started	Apr 23 04:42:35 PM PDT 24
Finished	Apr 23 04:44:19 PM PDT 24
Peak memory	562768 kb
Host	smart-1cdc399b-c0f1-42ea-ad0c-480127c851ab
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013724855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1013724855
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1298575185
Short name	T2097
Test name
Test status
Simulation time	6711016630 ps
CPU time	117.37 seconds
Started	Apr 23 04:42:36 PM PDT 24
Finished	Apr 23 04:44:33 PM PDT 24
Peak memory	562744 kb
Host	smart-9fc3e26d-c3ec-4342-ad17-a128be056b0d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298575185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1298575185
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.620358601
Short name	T1641
Test name
Test status
Simulation time	39920244 ps
CPU time	6.34 seconds
Started	Apr 23 04:42:36 PM PDT 24
Finished	Apr 23 04:42:42 PM PDT 24
Peak memory	562624 kb
Host	smart-eef1dba0-af1e-4191-bdda-dd7e89fc94e1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620358601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays .620358601
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all.3414838903
Short name	T2031
Test name
Test status
Simulation time	890089023 ps
CPU time	72.95 seconds
Started	Apr 23 04:42:38 PM PDT 24
Finished	Apr 23 04:43:52 PM PDT 24
Peak memory	563420 kb
Host	smart-fc1cb08f-8221-4812-8853-8b54fc6983c1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414838903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3414838903
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.3231312161
Short name	T2546
Test name
Test status
Simulation time	8335296709 ps
CPU time	318.69 seconds
Started	Apr 23 04:42:42 PM PDT 24
Finished	Apr 23 04:48:01 PM PDT 24
Peak memory	563888 kb
Host	smart-1307c603-627f-4c5d-a19a-b3923528608d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231312161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3231312161
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2871634949
Short name	T2568
Test name
Test status
Simulation time	3931496277 ps
CPU time	395.54 seconds
Started	Apr 23 04:42:40 PM PDT 24
Finished	Apr 23 04:49:16 PM PDT 24
Peak memory	572212 kb
Host	smart-b990ebb1-a47b-41d5-8a48-b3dc117f744c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871634949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.2871634949
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.910544912
Short name	T2075
Test name
Test status
Simulation time	6122542243 ps
CPU time	382.62 seconds
Started	Apr 23 04:42:47 PM PDT 24
Finished	Apr 23 04:49:10 PM PDT 24
Peak memory	572176 kb
Host	smart-d2339248-056b-4370-8891-6cc3fe23abc0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910544912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_reset_error.910544912
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.4285931929
Short name	T582
Test name
Test status
Simulation time	140676417 ps
CPU time	19.84 seconds
Started	Apr 23 04:42:40 PM PDT 24
Finished	Apr 23 04:43:00 PM PDT 24
Peak memory	562796 kb
Host	smart-e4e073a6-edf3-4e35-8e43-13a8c22dc177
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285931929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.4285931929
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_access_same_device.1334712666
Short name	T1638
Test name
Test status
Simulation time	627695179 ps
CPU time	62.78 seconds
Started	Apr 23 04:42:51 PM PDT 24
Finished	Apr 23 04:43:54 PM PDT 24
Peak memory	562716 kb
Host	smart-ab8e9f02-1ed9-4e8d-bcdb-4aa6e434ce85
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334712666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .1334712666
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.315125690
Short name	T2520
Test name
Test status
Simulation time	53414094 ps
CPU time	8.78 seconds
Started	Apr 23 04:42:50 PM PDT 24
Finished	Apr 23 04:42:59 PM PDT 24
Peak memory	562764 kb
Host	smart-a683bac4-44dc-4d98-8b31-09c99480778c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315125690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr .315125690
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_error_random.1108840396
Short name	T2110
Test name
Test status
Simulation time	848349631 ps
CPU time	27.62 seconds
Started	Apr 23 04:42:47 PM PDT 24
Finished	Apr 23 04:43:15 PM PDT 24
Peak memory	562672 kb
Host	smart-8f2d44d7-77c7-4861-9128-6d824bf1db64
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108840396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1108840396
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_random.2724013373
Short name	T2319
Test name
Test status
Simulation time	228535144 ps
CPU time	22.3 seconds
Started	Apr 23 04:42:43 PM PDT 24
Finished	Apr 23 04:43:06 PM PDT 24
Peak memory	562724 kb
Host	smart-7947357d-cefc-41d4-b07d-7bcde1abbe46
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724013373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2724013373
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3856231919
Short name	T1983
Test name
Test status
Simulation time	53552260579 ps
CPU time	559.19 seconds
Started	Apr 23 04:42:48 PM PDT 24
Finished	Apr 23 04:52:07 PM PDT 24
Peak memory	562760 kb
Host	smart-ecbe8119-ceec-4ed8-a244-bd9b592bc452
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856231919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3856231919
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.3951556220
Short name	T533
Test name
Test status
Simulation time	10401122713 ps
CPU time	200.51 seconds
Started	Apr 23 04:42:44 PM PDT 24
Finished	Apr 23 04:46:05 PM PDT 24
Peak memory	562804 kb
Host	smart-14d35552-4c09-437b-a56e-6e33dd85fc58
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951556220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3951556220
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.3426880579
Short name	T1316
Test name
Test status
Simulation time	96470251 ps
CPU time	11.27 seconds
Started	Apr 23 04:42:42 PM PDT 24
Finished	Apr 23 04:42:54 PM PDT 24
Peak memory	562708 kb
Host	smart-04b0354a-821c-415f-b9ac-c41fc593cb64
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426880579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.3426880579
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_same_source.930222295
Short name	T1348
Test name
Test status
Simulation time	184674693 ps
CPU time	15.35 seconds
Started	Apr 23 04:42:52 PM PDT 24
Finished	Apr 23 04:43:08 PM PDT 24
Peak memory	562676 kb
Host	smart-87f55dbc-ddb9-4ae6-8db9-2e760e4d29b7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930222295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.930222295
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke.2431337832
Short name	T2513
Test name
Test status
Simulation time	246708241 ps
CPU time	10.82 seconds
Started	Apr 23 04:42:43 PM PDT 24
Finished	Apr 23 04:42:54 PM PDT 24
Peak memory	562684 kb
Host	smart-3047a348-e4e2-4510-91dd-6cbb5eb68cd0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431337832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2431337832
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.407693194
Short name	T1258
Test name
Test status
Simulation time	6626387572 ps
CPU time	76.26 seconds
Started	Apr 23 04:42:42 PM PDT 24
Finished	Apr 23 04:43:59 PM PDT 24
Peak memory	562776 kb
Host	smart-4072f5bb-7e50-4fe5-848e-59f4958a73bd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407693194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.407693194
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3100282972
Short name	T1467
Test name
Test status
Simulation time	4482149501 ps
CPU time	88.31 seconds
Started	Apr 23 04:42:41 PM PDT 24
Finished	Apr 23 04:44:10 PM PDT 24
Peak memory	562804 kb
Host	smart-108a80c9-d674-4acc-83fe-f715b362a037
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100282972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3100282972
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.923537767
Short name	T1807
Test name
Test status
Simulation time	48499694 ps
CPU time	7.03 seconds
Started	Apr 23 04:42:46 PM PDT 24
Finished	Apr 23 04:42:53 PM PDT 24
Peak memory	562676 kb
Host	smart-85033dba-7749-4a85-98c2-959dbdd5a571
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923537767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .923537767
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all.3650420601
Short name	T1788
Test name
Test status
Simulation time	12752215763 ps
CPU time	523.56 seconds
Started	Apr 23 04:42:48 PM PDT 24
Finished	Apr 23 04:51:32 PM PDT 24
Peak memory	563996 kb
Host	smart-9f11308e-58a2-474e-95dd-e306c890cf37
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650420601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3650420601
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.3323672499
Short name	T2143
Test name
Test status
Simulation time	3347139344 ps
CPU time	294.62 seconds
Started	Apr 23 04:42:54 PM PDT 24
Finished	Apr 23 04:47:48 PM PDT 24
Peak memory	563960 kb
Host	smart-36a8f29d-4f13-4aec-80c5-770c8c953ad3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323672499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3323672499
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1509778491
Short name	T828
Test name
Test status
Simulation time	613656802 ps
CPU time	151.03 seconds
Started	Apr 23 04:42:49 PM PDT 24
Finished	Apr 23 04:45:21 PM PDT 24
Peak memory	563868 kb
Host	smart-194f3e4a-c23a-4190-ac7a-38619ef51226
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509778491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.1509778491
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.4209866176
Short name	T2250
Test name
Test status
Simulation time	4021506928 ps
CPU time	453.54 seconds
Started	Apr 23 04:42:51 PM PDT 24
Finished	Apr 23 04:50:25 PM PDT 24
Peak memory	572220 kb
Host	smart-20a1b7e5-16df-4079-9012-416a3b7b0fe7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209866176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.4209866176
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.416681295
Short name	T1303
Test name
Test status
Simulation time	21598711 ps
CPU time	5.86 seconds
Started	Apr 23 04:42:47 PM PDT 24
Finished	Apr 23 04:42:54 PM PDT 24
Peak memory	562728 kb
Host	smart-a8680c69-51d7-4692-b5d0-b43cdc977112
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416681295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.416681295
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_access_same_device.2474113353
Short name	T2224
Test name
Test status
Simulation time	3308526172 ps
CPU time	141.5 seconds
Started	Apr 23 04:42:58 PM PDT 24
Finished	Apr 23 04:45:20 PM PDT 24
Peak memory	562832 kb
Host	smart-357503a6-fbdd-49d6-9cbf-f65e43672f2c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474113353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .2474113353
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1000924426
Short name	T2226
Test name
Test status
Simulation time	98652931846 ps
CPU time	1630.04 seconds
Started	Apr 23 04:42:59 PM PDT 24
Finished	Apr 23 05:10:09 PM PDT 24
Peak memory	562852 kb
Host	smart-e7f9a99a-4733-462f-a30a-de460df7a965
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000924426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.1000924426
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1978132357
Short name	T2207
Test name
Test status
Simulation time	96346205 ps
CPU time	14.01 seconds
Started	Apr 23 04:43:03 PM PDT 24
Finished	Apr 23 04:43:17 PM PDT 24
Peak memory	562744 kb
Host	smart-f465d170-6767-4dea-9050-18de6e45de4a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978132357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1978132357
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_error_random.3934607910
Short name	T2450
Test name
Test status
Simulation time	1478310927 ps
CPU time	59.57 seconds
Started	Apr 23 04:43:00 PM PDT 24
Finished	Apr 23 04:44:00 PM PDT 24
Peak memory	562728 kb
Host	smart-d11d0284-1e7d-4514-b5b8-e255d503ff23
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934607910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3934607910
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_random.4035553106
Short name	T2332
Test name
Test status
Simulation time	27296521 ps
CPU time	6.16 seconds
Started	Apr 23 04:42:57 PM PDT 24
Finished	Apr 23 04:43:03 PM PDT 24
Peak memory	562720 kb
Host	smart-ef497c48-1a8e-4c02-9f64-876ceb8261ef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035553106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.4035553106
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_random_large_delays.525496360
Short name	T2357
Test name
Test status
Simulation time	26621595302 ps
CPU time	299.93 seconds
Started	Apr 23 04:42:56 PM PDT 24
Finished	Apr 23 04:47:56 PM PDT 24
Peak memory	562840 kb
Host	smart-9150b72f-b181-4b5f-82af-3b0cb56506b0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525496360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.525496360
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.3858444927
Short name	T453
Test name
Test status
Simulation time	23847726598 ps
CPU time	435.24 seconds
Started	Apr 23 04:42:57 PM PDT 24
Finished	Apr 23 04:50:13 PM PDT 24
Peak memory	562808 kb
Host	smart-b3a14a95-6864-4b4e-b2a1-d019dd2efd15
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858444927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3858444927
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.3776834288
Short name	T2525
Test name
Test status
Simulation time	604455127 ps
CPU time	54.17 seconds
Started	Apr 23 04:42:57 PM PDT 24
Finished	Apr 23 04:43:52 PM PDT 24
Peak memory	562788 kb
Host	smart-07f073cb-5250-48b8-b988-09218cea91f3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776834288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.3776834288
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_same_source.1823734167
Short name	T2265
Test name
Test status
Simulation time	2092192184 ps
CPU time	62.95 seconds
Started	Apr 23 04:43:06 PM PDT 24
Finished	Apr 23 04:44:09 PM PDT 24
Peak memory	562672 kb
Host	smart-be66f65b-7a87-4e39-b777-2c0b799aafed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823734167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1823734167
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke.3209815655
Short name	T2339
Test name
Test status
Simulation time	265211679 ps
CPU time	10.8 seconds
Started	Apr 23 04:42:57 PM PDT 24
Finished	Apr 23 04:43:08 PM PDT 24
Peak memory	562720 kb
Host	smart-ca54d780-23e9-4f81-afc3-d98baa500442
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209815655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3209815655
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1908954421
Short name	T1459
Test name
Test status
Simulation time	6411861777 ps
CPU time	76.72 seconds
Started	Apr 23 04:42:54 PM PDT 24
Finished	Apr 23 04:44:11 PM PDT 24
Peak memory	562796 kb
Host	smart-6acc393b-f860-49ad-87df-5bed40ab4128
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908954421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1908954421
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3129327957
Short name	T1294
Test name
Test status
Simulation time	5371933042 ps
CPU time	103.46 seconds
Started	Apr 23 04:42:56 PM PDT 24
Finished	Apr 23 04:44:40 PM PDT 24
Peak memory	562800 kb
Host	smart-4e2e25f2-c12f-478b-9c54-88ed77e215d4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129327957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3129327957
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.416482634
Short name	T1782
Test name
Test status
Simulation time	51334889 ps
CPU time	6.6 seconds
Started	Apr 23 04:42:53 PM PDT 24
Finished	Apr 23 04:43:00 PM PDT 24
Peak memory	562728 kb
Host	smart-60ec03dd-edb0-4a69-94f1-e3162e6e64aa
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416482634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays .416482634
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all.3803730839
Short name	T458
Test name
Test status
Simulation time	3895935838 ps
CPU time	159.58 seconds
Started	Apr 23 04:43:02 PM PDT 24
Finished	Apr 23 04:45:42 PM PDT 24
Peak memory	562876 kb
Host	smart-ab45f634-c92a-46bb-b443-61456e84b935
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803730839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3803730839
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2382156264
Short name	T1313
Test name
Test status
Simulation time	7339481613 ps
CPU time	284.08 seconds
Started	Apr 23 04:43:03 PM PDT 24
Finished	Apr 23 04:47:47 PM PDT 24
Peak memory	563464 kb
Host	smart-e2082528-2346-45d8-8c73-0e9450080179
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382156264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2382156264
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2576459447
Short name	T2500
Test name
Test status
Simulation time	247943300 ps
CPU time	114.6 seconds
Started	Apr 23 04:43:06 PM PDT 24
Finished	Apr 23 04:45:01 PM PDT 24
Peak memory	563840 kb
Host	smart-e10ed1b6-c6fb-40eb-848a-8a9dfbd34851
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576459447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.2576459447
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1965585630
Short name	T2497
Test name
Test status
Simulation time	367451895 ps
CPU time	123.73 seconds
Started	Apr 23 04:43:06 PM PDT 24
Finished	Apr 23 04:45:10 PM PDT 24
Peak memory	572084 kb
Host	smart-7e9ccf0e-8f7e-4406-8c3f-bb7073402b28
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965585630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.1965585630
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.2495167948
Short name	T543
Test name
Test status
Simulation time	320594264 ps
CPU time	37.95 seconds
Started	Apr 23 04:43:00 PM PDT 24
Finished	Apr 23 04:43:38 PM PDT 24
Peak memory	562808 kb
Host	smart-ced20860-9576-4bae-836e-dd733ca1c54c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495167948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2495167948
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/5.chip_csr_rw.1873483033
Short name	T1571
Test name
Test status
Simulation time	3706378924 ps
CPU time	304.79 seconds
Started	Apr 23 04:31:35 PM PDT 24
Finished	Apr 23 04:36:40 PM PDT 24
Peak memory	588640 kb
Host	smart-b870dd03-1be9-402d-9b87-d746a8b79ca7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873483033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.1873483033
Directory	/workspace/5.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.3093783167
Short name	T347
Test name
Test status
Simulation time	15644253862 ps
CPU time	1993.04 seconds
Started	Apr 23 04:31:11 PM PDT 24
Finished	Apr 23 05:04:25 PM PDT 24
Peak memory	585032 kb
Host	smart-304e5623-3e12-4f12-9d68-25065bc9bf3d
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093783167 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.3093783167
Directory	/workspace/5.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_access_same_device.2044430078
Short name	T2408
Test name
Test status
Simulation time	2001222075 ps
CPU time	93.76 seconds
Started	Apr 23 04:31:25 PM PDT 24
Finished	Apr 23 04:32:59 PM PDT 24
Peak memory	562756 kb
Host	smart-a6f7d7d6-f79a-4496-ae16-e488fe0141df
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044430078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 2044430078
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2314549713
Short name	T1318
Test name
Test status
Simulation time	82921464 ps
CPU time	7.15 seconds
Started	Apr 23 04:31:27 PM PDT 24
Finished	Apr 23 04:31:35 PM PDT 24
Peak memory	562716 kb
Host	smart-e1a8d0c9-804b-454f-8fbd-2667de6e8d35
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314549713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .2314549713
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_error_random.1096266906
Short name	T1826
Test name
Test status
Simulation time	2060220982 ps
CPU time	72.17 seconds
Started	Apr 23 04:31:30 PM PDT 24
Finished	Apr 23 04:32:42 PM PDT 24
Peak memory	562704 kb
Host	smart-b6e5fdaa-aa70-4d9c-87c2-f7ce22919918
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096266906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1096266906
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_random.1581481350
Short name	T554
Test name
Test status
Simulation time	553386252 ps
CPU time	52.36 seconds
Started	Apr 23 04:31:21 PM PDT 24
Finished	Apr 23 04:32:14 PM PDT 24
Peak memory	562688 kb
Host	smart-d66e445b-e96a-442f-970a-6fd43068bd9d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581481350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1581481350
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1695516729
Short name	T2634
Test name
Test status
Simulation time	96118615219 ps
CPU time	1070.4 seconds
Started	Apr 23 04:31:20 PM PDT 24
Finished	Apr 23 04:49:11 PM PDT 24
Peak memory	562820 kb
Host	smart-dbc2e80b-c07c-4953-b31d-45af9b91f530
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695516729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1695516729
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.3886803587
Short name	T2020
Test name
Test status
Simulation time	3624701666 ps
CPU time	67.36 seconds
Started	Apr 23 04:31:19 PM PDT 24
Finished	Apr 23 04:32:27 PM PDT 24
Peak memory	562804 kb
Host	smart-412ecfe2-0402-4fd9-b1f3-4ee98be7ef92
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886803587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3886803587
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.4203353466
Short name	T464
Test name
Test status
Simulation time	111458538 ps
CPU time	14.57 seconds
Started	Apr 23 04:31:18 PM PDT 24
Finished	Apr 23 04:31:33 PM PDT 24
Peak memory	562684 kb
Host	smart-968b70d8-0ae8-46c6-aa43-2dc255ac47a1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203353466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.4203353466
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_same_source.1469984436
Short name	T1986
Test name
Test status
Simulation time	745697829 ps
CPU time	30.02 seconds
Started	Apr 23 04:31:32 PM PDT 24
Finished	Apr 23 04:32:03 PM PDT 24
Peak memory	562712 kb
Host	smart-d03f6b6e-9bca-4353-9d51-2f3e978c55f5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469984436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1469984436
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke.1351836059
Short name	T1655
Test name
Test status
Simulation time	161253665 ps
CPU time	8.37 seconds
Started	Apr 23 04:31:14 PM PDT 24
Finished	Apr 23 04:31:23 PM PDT 24
Peak memory	562704 kb
Host	smart-252e0e05-1a49-4738-a1df-6d11942cb4b6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351836059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1351836059
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.2783534402
Short name	T2478
Test name
Test status
Simulation time	8386310067 ps
CPU time	95.95 seconds
Started	Apr 23 04:31:21 PM PDT 24
Finished	Apr 23 04:32:58 PM PDT 24
Peak memory	562776 kb
Host	smart-1f68dc7a-09f6-4070-8ad2-045dba9c3c66
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783534402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2783534402
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2017062956
Short name	T1236
Test name
Test status
Simulation time	4161380397 ps
CPU time	76.9 seconds
Started	Apr 23 04:31:22 PM PDT 24
Finished	Apr 23 04:32:39 PM PDT 24
Peak memory	562776 kb
Host	smart-159d35d5-fa5e-4871-aef6-32a3dd89106f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017062956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2017062956
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3308041905
Short name	T1229
Test name
Test status
Simulation time	36538585 ps
CPU time	6.08 seconds
Started	Apr 23 04:31:17 PM PDT 24
Finished	Apr 23 04:31:24 PM PDT 24
Peak memory	562704 kb
Host	smart-f466b27d-07c8-45cc-8129-8ba5b446c707
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308041905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .3308041905
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.3187643332
Short name	T1421
Test name
Test status
Simulation time	4465527160 ps
CPU time	168.05 seconds
Started	Apr 23 04:31:37 PM PDT 24
Finished	Apr 23 04:34:25 PM PDT 24
Peak memory	562796 kb
Host	smart-d34d71ef-a965-4f81-b47e-a916b0934651
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187643332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3187643332
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.4168629154
Short name	T1852
Test name
Test status
Simulation time	32109320 ps
CPU time	47.59 seconds
Started	Apr 23 04:31:31 PM PDT 24
Finished	Apr 23 04:32:19 PM PDT 24
Peak memory	563604 kb
Host	smart-3da3d915-3588-4422-b02d-dea71ccefe67
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168629154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.4168629154
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1498103445
Short name	T2782
Test name
Test status
Simulation time	135398529 ps
CPU time	65.23 seconds
Started	Apr 23 04:31:34 PM PDT 24
Finished	Apr 23 04:32:40 PM PDT 24
Peak memory	563940 kb
Host	smart-5e1fb227-5f4e-479c-ab83-e5261213771c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498103445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.1498103445
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.578204501
Short name	T1389
Test name
Test status
Simulation time	184791317 ps
CPU time	23.06 seconds
Started	Apr 23 04:31:30 PM PDT 24
Finished	Apr 23 04:31:53 PM PDT 24
Peak memory	562760 kb
Host	smart-b44d2d03-19e8-445d-9d05-c2c7d7ff84c5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578204501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.578204501
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_access_same_device.1007185996
Short name	T769
Test name
Test status
Simulation time	1842269901 ps
CPU time	74.5 seconds
Started	Apr 23 04:43:13 PM PDT 24
Finished	Apr 23 04:44:28 PM PDT 24
Peak memory	562740 kb
Host	smart-fc5561b6-9ab8-451d-8afe-bf4fd5ab9822
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007185996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1007185996
Directory	/workspace/50.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2366269686
Short name	T797
Test name
Test status
Simulation time	69981842381 ps
CPU time	1161.32 seconds
Started	Apr 23 04:43:07 PM PDT 24
Finished	Apr 23 05:02:29 PM PDT 24
Peak memory	562860 kb
Host	smart-fdfb1a39-dc21-4c29-aadd-59b472047eff
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366269686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.2366269686
Directory	/workspace/50.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.2113435597
Short name	T2259
Test name
Test status
Simulation time	1348468803 ps
CPU time	53.74 seconds
Started	Apr 23 04:43:07 PM PDT 24
Finished	Apr 23 04:44:01 PM PDT 24
Peak memory	562660 kb
Host	smart-217354a0-e960-4c52-9a1b-d9b153eb9690
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113435597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.2113435597
Directory	/workspace/50.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_error_random.2014982055
Short name	T2293
Test name
Test status
Simulation time	337822762 ps
CPU time	15.49 seconds
Started	Apr 23 04:43:06 PM PDT 24
Finished	Apr 23 04:43:22 PM PDT 24
Peak memory	562708 kb
Host	smart-4fde6ba7-4b0b-49e3-b31e-64ad7b4c5847
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014982055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.2014982055
Directory	/workspace/50.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_random.2013634422
Short name	T2480
Test name
Test status
Simulation time	426641760 ps
CPU time	43.22 seconds
Started	Apr 23 04:43:11 PM PDT 24
Finished	Apr 23 04:43:54 PM PDT 24
Peak memory	562696 kb
Host	smart-e4aaa73a-329c-400e-ae67-7867c8d33631
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013634422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.2013634422
Directory	/workspace/50.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1879696916
Short name	T1959
Test name
Test status
Simulation time	10682898437 ps
CPU time	117.45 seconds
Started	Apr 23 04:43:09 PM PDT 24
Finished	Apr 23 04:45:07 PM PDT 24
Peak memory	562776 kb
Host	smart-654d7d7d-9422-4eac-9d55-8c6922db2149
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879696916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1879696916
Directory	/workspace/50.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.2846208490
Short name	T1739
Test name
Test status
Simulation time	41977118679 ps
CPU time	776.27 seconds
Started	Apr 23 04:43:08 PM PDT 24
Finished	Apr 23 04:56:05 PM PDT 24
Peak memory	562840 kb
Host	smart-6b10800c-95fc-4a78-acb0-c641af261b1f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846208490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.2846208490
Directory	/workspace/50.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1286823029
Short name	T2537
Test name
Test status
Simulation time	133574485 ps
CPU time	14.79 seconds
Started	Apr 23 04:43:07 PM PDT 24
Finished	Apr 23 04:43:22 PM PDT 24
Peak memory	562724 kb
Host	smart-be5dd49d-cf96-4759-b0bc-066aa0819481
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286823029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.1286823029
Directory	/workspace/50.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_same_source.2691305095
Short name	T1539
Test name
Test status
Simulation time	1853921697 ps
CPU time	60.69 seconds
Started	Apr 23 04:43:11 PM PDT 24
Finished	Apr 23 04:44:12 PM PDT 24
Peak memory	562724 kb
Host	smart-48564218-88cb-41a3-a605-c9ad7491ceda
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691305095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.2691305095
Directory	/workspace/50.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke.2738037914
Short name	T2099
Test name
Test status
Simulation time	148617448 ps
CPU time	7.33 seconds
Started	Apr 23 04:43:03 PM PDT 24
Finished	Apr 23 04:43:11 PM PDT 24
Peak memory	562720 kb
Host	smart-5329bcaa-dd40-4be3-b1ac-2faab246105f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738037914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.2738037914
Directory	/workspace/50.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2703762749
Short name	T2191
Test name
Test status
Simulation time	10666012302 ps
CPU time	109.48 seconds
Started	Apr 23 04:43:06 PM PDT 24
Finished	Apr 23 04:44:55 PM PDT 24
Peak memory	562748 kb
Host	smart-7b693bd5-120c-45b9-9ad4-2247075c6985
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703762749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2703762749
Directory	/workspace/50.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2279354746
Short name	T2093
Test name
Test status
Simulation time	4482034385 ps
CPU time	86.71 seconds
Started	Apr 23 04:43:07 PM PDT 24
Finished	Apr 23 04:44:34 PM PDT 24
Peak memory	562756 kb
Host	smart-c7e16cb3-3ab5-4991-a0be-6656203b267f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279354746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2279354746
Directory	/workspace/50.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3807561384
Short name	T1331
Test name
Test status
Simulation time	47822420 ps
CPU time	6.99 seconds
Started	Apr 23 04:43:07 PM PDT 24
Finished	Apr 23 04:43:14 PM PDT 24
Peak memory	562636 kb
Host	smart-23d845c9-de48-47fc-b8f8-b54fa272a9c8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807561384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.3807561384
Directory	/workspace/50.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.1146128055
Short name	T2781
Test name
Test status
Simulation time	1299335499 ps
CPU time	106.21 seconds
Started	Apr 23 04:43:09 PM PDT 24
Finished	Apr 23 04:44:55 PM PDT 24
Peak memory	562984 kb
Host	smart-a90efb31-c11a-4497-ba53-0cfeb3dc54b4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146128055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.1146128055
Directory	/workspace/50.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3125302252
Short name	T1966
Test name
Test status
Simulation time	311189147 ps
CPU time	100.01 seconds
Started	Apr 23 04:43:14 PM PDT 24
Finished	Apr 23 04:44:54 PM PDT 24
Peak memory	563916 kb
Host	smart-dc5db37f-53a3-482e-aabf-089777f079da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125302252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.3125302252
Directory	/workspace/50.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.66090514
Short name	T1379
Test name
Test status
Simulation time	325688011 ps
CPU time	168.48 seconds
Started	Apr 23 04:43:14 PM PDT 24
Finished	Apr 23 04:46:03 PM PDT 24
Peak memory	572124 kb
Host	smart-cab572fa-8aeb-4c01-b501-485368d0dec0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66090514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_ with_reset_error.66090514
Directory	/workspace/50.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2293341153
Short name	T2134
Test name
Test status
Simulation time	249675917 ps
CPU time	12.74 seconds
Started	Apr 23 04:43:14 PM PDT 24
Finished	Apr 23 04:43:27 PM PDT 24
Peak memory	562772 kb
Host	smart-c7ce05c2-7b99-4c82-94b4-e4ba4bdefc02
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293341153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.2293341153
Directory	/workspace/50.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_access_same_device.2372560247
Short name	T1954
Test name
Test status
Simulation time	630258017 ps
CPU time	49.77 seconds
Started	Apr 23 04:43:19 PM PDT 24
Finished	Apr 23 04:44:09 PM PDT 24
Peak memory	562764 kb
Host	smart-5a8ca0d6-e318-4b7f-839c-63ff1c3ceb65
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372560247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .2372560247
Directory	/workspace/51.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.851399936
Short name	T1747
Test name
Test status
Simulation time	56715023729 ps
CPU time	1054.75 seconds
Started	Apr 23 04:43:19 PM PDT 24
Finished	Apr 23 05:00:54 PM PDT 24
Peak memory	562856 kb
Host	smart-6ed371af-c8e3-4677-a862-e9861417d2b0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851399936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d evice_slow_rsp.851399936
Directory	/workspace/51.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.172471342
Short name	T1878
Test name
Test status
Simulation time	1185232654 ps
CPU time	46.97 seconds
Started	Apr 23 04:43:15 PM PDT 24
Finished	Apr 23 04:44:02 PM PDT 24
Peak memory	562716 kb
Host	smart-f17c50b9-aad9-4b96-8909-32844486bdfe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172471342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr .172471342
Directory	/workspace/51.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_error_random.1269386398
Short name	T2771
Test name
Test status
Simulation time	1698531227 ps
CPU time	60.79 seconds
Started	Apr 23 04:43:17 PM PDT 24
Finished	Apr 23 04:44:19 PM PDT 24
Peak memory	562736 kb
Host	smart-71dc028e-14a0-4860-b0d4-29ec75643689
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269386398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.1269386398
Directory	/workspace/51.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_random.3024673893
Short name	T491
Test name
Test status
Simulation time	931295427 ps
CPU time	38.31 seconds
Started	Apr 23 04:43:21 PM PDT 24
Finished	Apr 23 04:44:00 PM PDT 24
Peak memory	562724 kb
Host	smart-ed289c36-99c6-49fa-9838-182174a30054
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024673893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3024673893
Directory	/workspace/51.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_random_large_delays.4293156892
Short name	T2169
Test name
Test status
Simulation time	84269259144 ps
CPU time	944.53 seconds
Started	Apr 23 04:43:17 PM PDT 24
Finished	Apr 23 04:59:01 PM PDT 24
Peak memory	562816 kb
Host	smart-dfc8725a-39b3-4d4c-86df-686604333473
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293156892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.4293156892
Directory	/workspace/51.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2713079247
Short name	T2535
Test name
Test status
Simulation time	38635423640 ps
CPU time	649.59 seconds
Started	Apr 23 04:43:18 PM PDT 24
Finished	Apr 23 04:54:07 PM PDT 24
Peak memory	562788 kb
Host	smart-6a7c09ea-05ad-456f-a32c-78a8e732bbb8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713079247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2713079247
Directory	/workspace/51.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.1195941677
Short name	T2235
Test name
Test status
Simulation time	619140173 ps
CPU time	51.8 seconds
Started	Apr 23 04:43:17 PM PDT 24
Finished	Apr 23 04:44:09 PM PDT 24
Peak memory	562732 kb
Host	smart-d2be32cf-8298-447c-bb5d-324b6e211f7c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195941677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.1195941677
Directory	/workspace/51.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_same_source.2463194009
Short name	T2765
Test name
Test status
Simulation time	1876000710 ps
CPU time	57.99 seconds
Started	Apr 23 04:43:17 PM PDT 24
Finished	Apr 23 04:44:15 PM PDT 24
Peak memory	562740 kb
Host	smart-6f5a8c38-ec0a-4c35-a3d2-7fb36318cebb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463194009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2463194009
Directory	/workspace/51.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke.2161822567
Short name	T600
Test name
Test status
Simulation time	39318961 ps
CPU time	6.62 seconds
Started	Apr 23 04:43:14 PM PDT 24
Finished	Apr 23 04:43:21 PM PDT 24
Peak memory	562680 kb
Host	smart-362c4018-bdff-47fd-a517-89d8e55fcda3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161822567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2161822567
Directory	/workspace/51.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.617260567
Short name	T1247
Test name
Test status
Simulation time	7792839974 ps
CPU time	83.4 seconds
Started	Apr 23 04:43:12 PM PDT 24
Finished	Apr 23 04:44:36 PM PDT 24
Peak memory	562768 kb
Host	smart-9550b065-2de5-4186-a6e3-2676c558595b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617260567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.617260567
Directory	/workspace/51.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2108906439
Short name	T2150
Test name
Test status
Simulation time	4685579601 ps
CPU time	86.63 seconds
Started	Apr 23 04:43:17 PM PDT 24
Finished	Apr 23 04:44:44 PM PDT 24
Peak memory	562768 kb
Host	smart-eb116217-f4da-427e-8a4e-1214006e6441
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108906439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.2108906439
Directory	/workspace/51.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2379841121
Short name	T1351
Test name
Test status
Simulation time	48357602 ps
CPU time	6.32 seconds
Started	Apr 23 04:43:15 PM PDT 24
Finished	Apr 23 04:43:21 PM PDT 24
Peak memory	562700 kb
Host	smart-faf88814-1277-4464-8a57-2b4b965eca64
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379841121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.2379841121
Directory	/workspace/51.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all.2254312102
Short name	T454
Test name
Test status
Simulation time	8394500209 ps
CPU time	303.29 seconds
Started	Apr 23 04:43:19 PM PDT 24
Finished	Apr 23 04:48:22 PM PDT 24
Peak memory	563916 kb
Host	smart-95b62d86-ac60-4f66-a2e6-16c4ab84d4bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254312102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.2254312102
Directory	/workspace/51.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.431555459
Short name	T2264
Test name
Test status
Simulation time	800744078 ps
CPU time	64.19 seconds
Started	Apr 23 04:43:21 PM PDT 24
Finished	Apr 23 04:44:25 PM PDT 24
Peak memory	562880 kb
Host	smart-40f48911-d1af-4f85-9fa6-6ec5aad1ccff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431555459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.431555459
Directory	/workspace/51.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2460266359
Short name	T1540
Test name
Test status
Simulation time	56759115 ps
CPU time	31.98 seconds
Started	Apr 23 04:43:23 PM PDT 24
Finished	Apr 23 04:43:55 PM PDT 24
Peak memory	563360 kb
Host	smart-c741fe3c-d4cc-4afc-b1d6-41011b751181
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460266359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.2460266359
Directory	/workspace/51.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2196979858
Short name	T2412
Test name
Test status
Simulation time	1811152923 ps
CPU time	167.48 seconds
Started	Apr 23 04:43:19 PM PDT 24
Finished	Apr 23 04:46:06 PM PDT 24
Peak memory	563824 kb
Host	smart-01fca051-9385-4572-8e48-6e4d718263bd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196979858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.2196979858
Directory	/workspace/51.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2083268990
Short name	T1468
Test name
Test status
Simulation time	98514443 ps
CPU time	15.36 seconds
Started	Apr 23 04:43:21 PM PDT 24
Finished	Apr 23 04:43:37 PM PDT 24
Peak memory	562736 kb
Host	smart-b24be74e-aeda-4322-b0dd-d47ca0d1706f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083268990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2083268990
Directory	/workspace/51.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_access_same_device.3334487066
Short name	T2182
Test name
Test status
Simulation time	2740357577 ps
CPU time	118.38 seconds
Started	Apr 23 04:43:21 PM PDT 24
Finished	Apr 23 04:45:20 PM PDT 24
Peak memory	562816 kb
Host	smart-9ab893e7-0710-4cbb-9bf5-72c1dd7e0346
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334487066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .3334487066
Directory	/workspace/52.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.1527425623
Short name	T2571
Test name
Test status
Simulation time	156188608342 ps
CPU time	2735.22 seconds
Started	Apr 23 04:43:22 PM PDT 24
Finished	Apr 23 05:28:58 PM PDT 24
Peak memory	562972 kb
Host	smart-94725b01-d954-4131-abf1-1fda260a14d2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527425623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.1527425623
Directory	/workspace/52.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2567536664
Short name	T1663
Test name
Test status
Simulation time	411150056 ps
CPU time	19.33 seconds
Started	Apr 23 04:43:26 PM PDT 24
Finished	Apr 23 04:43:46 PM PDT 24
Peak memory	562732 kb
Host	smart-b3854540-6051-4b4f-8406-12c642c4e17e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567536664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.2567536664
Directory	/workspace/52.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_error_random.26346876
Short name	T1679
Test name
Test status
Simulation time	566481757 ps
CPU time	20.69 seconds
Started	Apr 23 04:43:29 PM PDT 24
Finished	Apr 23 04:43:50 PM PDT 24
Peak memory	562712 kb
Host	smart-6a9e3dc0-3c82-4392-89a8-538cbcb35388
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26346876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.26346876
Directory	/workspace/52.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_random.1167946482
Short name	T1923
Test name
Test status
Simulation time	387558473 ps
CPU time	34.07 seconds
Started	Apr 23 04:43:27 PM PDT 24
Finished	Apr 23 04:44:02 PM PDT 24
Peak memory	562736 kb
Host	smart-f29defe9-d391-48f8-ada5-dce24116b154
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167946482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1167946482
Directory	/workspace/52.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_random_large_delays.1262432496
Short name	T1386
Test name
Test status
Simulation time	18822375933 ps
CPU time	207.85 seconds
Started	Apr 23 04:43:27 PM PDT 24
Finished	Apr 23 04:46:55 PM PDT 24
Peak memory	562796 kb
Host	smart-9d917938-dc09-43f4-8c66-e06666ab9ae3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262432496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1262432496
Directory	/workspace/52.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.3285790244
Short name	T1932
Test name
Test status
Simulation time	30343387509 ps
CPU time	571.89 seconds
Started	Apr 23 04:43:25 PM PDT 24
Finished	Apr 23 04:52:57 PM PDT 24
Peak memory	562800 kb
Host	smart-62d28819-16d2-49ed-a791-746fc422f491
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285790244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.3285790244
Directory	/workspace/52.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.893778304
Short name	T529
Test name
Test status
Simulation time	464358030 ps
CPU time	45.49 seconds
Started	Apr 23 04:43:21 PM PDT 24
Finished	Apr 23 04:44:07 PM PDT 24
Peak memory	562748 kb
Host	smart-87f13b87-5c0c-4168-84c7-a34f27855e7d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893778304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_dela ys.893778304
Directory	/workspace/52.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_same_source.4071485926
Short name	T1974
Test name
Test status
Simulation time	2559274249 ps
CPU time	74.92 seconds
Started	Apr 23 04:43:22 PM PDT 24
Finished	Apr 23 04:44:37 PM PDT 24
Peak memory	562748 kb
Host	smart-cc9a4103-7e16-4ee4-85de-e384ae3c6dec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071485926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.4071485926
Directory	/workspace/52.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke.1726560280
Short name	T1849
Test name
Test status
Simulation time	47583290 ps
CPU time	6.83 seconds
Started	Apr 23 04:43:18 PM PDT 24
Finished	Apr 23 04:43:25 PM PDT 24
Peak memory	562676 kb
Host	smart-e27f8a8e-455d-492a-bdd7-f963a7666119
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726560280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1726560280
Directory	/workspace/52.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.3141118013
Short name	T1512
Test name
Test status
Simulation time	9240306409 ps
CPU time	100.54 seconds
Started	Apr 23 04:43:21 PM PDT 24
Finished	Apr 23 04:45:02 PM PDT 24
Peak memory	562764 kb
Host	smart-8cb95d5c-debc-487c-a1e8-b63f508a5b9c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141118013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.3141118013
Directory	/workspace/52.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2618678679
Short name	T2234
Test name
Test status
Simulation time	4780944683 ps
CPU time	87.17 seconds
Started	Apr 23 04:43:24 PM PDT 24
Finished	Apr 23 04:44:52 PM PDT 24
Peak memory	562716 kb
Host	smart-51c302d8-e3f3-40c2-b1aa-fc31c209136f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618678679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.2618678679
Directory	/workspace/52.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3258097338
Short name	T2440
Test name
Test status
Simulation time	47264970 ps
CPU time	6.66 seconds
Started	Apr 23 04:43:21 PM PDT 24
Finished	Apr 23 04:43:28 PM PDT 24
Peak memory	562668 kb
Host	smart-aa062e00-6def-4c31-a923-2ff151727b36
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258097338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.3258097338
Directory	/workspace/52.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all.1248882498
Short name	T2604
Test name
Test status
Simulation time	9562461189 ps
CPU time	370.52 seconds
Started	Apr 23 04:43:26 PM PDT 24
Finished	Apr 23 04:49:37 PM PDT 24
Peak memory	563564 kb
Host	smart-ad9222b2-cbce-430b-91dc-85d91a144d89
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248882498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.1248882498
Directory	/workspace/52.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.3565266671
Short name	T1743
Test name
Test status
Simulation time	2521508241 ps
CPU time	208.59 seconds
Started	Apr 23 04:43:26 PM PDT 24
Finished	Apr 23 04:46:55 PM PDT 24
Peak memory	562912 kb
Host	smart-2cec9582-eca5-4e31-8db0-4849fc182ffc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565266671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.3565266671
Directory	/workspace/52.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2024152821
Short name	T2107
Test name
Test status
Simulation time	358857487 ps
CPU time	154.03 seconds
Started	Apr 23 04:43:34 PM PDT 24
Finished	Apr 23 04:46:09 PM PDT 24
Peak memory	563880 kb
Host	smart-4165f078-45d6-4c0c-b234-a7851c577f70
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024152821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.2024152821
Directory	/workspace/52.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2902565097
Short name	T1941
Test name
Test status
Simulation time	279550728 ps
CPU time	79.82 seconds
Started	Apr 23 04:43:26 PM PDT 24
Finished	Apr 23 04:44:46 PM PDT 24
Peak memory	572164 kb
Host	smart-529655b0-b742-40e2-945c-8a2fa19ccfc3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902565097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.2902565097
Directory	/workspace/52.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.3066328378
Short name	T1394
Test name
Test status
Simulation time	1287346434 ps
CPU time	52.39 seconds
Started	Apr 23 04:43:27 PM PDT 24
Finished	Apr 23 04:44:19 PM PDT 24
Peak memory	562816 kb
Host	smart-caaf7599-9dcf-4b6c-954f-a89dc1361cf5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066328378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.3066328378
Directory	/workspace/52.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_access_same_device.772630265
Short name	T755
Test name
Test status
Simulation time	810278763 ps
CPU time	36.18 seconds
Started	Apr 23 04:43:32 PM PDT 24
Finished	Apr 23 04:44:09 PM PDT 24
Peak memory	562720 kb
Host	smart-ecaa332b-5e83-4dbf-a341-a186d6c042b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772630265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device. 772630265
Directory	/workspace/53.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.4288370746
Short name	T2580
Test name
Test status
Simulation time	83842667042 ps
CPU time	1537.37 seconds
Started	Apr 23 04:43:33 PM PDT 24
Finished	Apr 23 05:09:11 PM PDT 24
Peak memory	562928 kb
Host	smart-3dcb3f26-8b93-4bb2-91e2-d3cf4cbf68cb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288370746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.4288370746
Directory	/workspace/53.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3613530770
Short name	T2548
Test name
Test status
Simulation time	271986488 ps
CPU time	14 seconds
Started	Apr 23 04:43:32 PM PDT 24
Finished	Apr 23 04:43:46 PM PDT 24
Peak memory	562644 kb
Host	smart-ac608b2a-4402-462d-9446-84aec104bef5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613530770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3613530770
Directory	/workspace/53.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_error_random.1177820645
Short name	T1321
Test name
Test status
Simulation time	2334642280 ps
CPU time	76.93 seconds
Started	Apr 23 04:43:34 PM PDT 24
Finished	Apr 23 04:44:51 PM PDT 24
Peak memory	562788 kb
Host	smart-5bcf0ec6-a6d3-4c6b-92f5-8c6bbeabbdb8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177820645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.1177820645
Directory	/workspace/53.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_random.3230270557
Short name	T2507
Test name
Test status
Simulation time	486009515 ps
CPU time	47.75 seconds
Started	Apr 23 04:43:29 PM PDT 24
Finished	Apr 23 04:44:17 PM PDT 24
Peak memory	562748 kb
Host	smart-c093ce12-f6d1-4bcc-88ac-cb78256c57af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230270557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.3230270557
Directory	/workspace/53.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3908046420
Short name	T1837
Test name
Test status
Simulation time	16761367212 ps
CPU time	190.65 seconds
Started	Apr 23 04:43:29 PM PDT 24
Finished	Apr 23 04:46:40 PM PDT 24
Peak memory	562824 kb
Host	smart-d3b5417e-9e11-45c5-87bb-6f3457d8199b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908046420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3908046420
Directory	/workspace/53.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.1586831946
Short name	T1881
Test name
Test status
Simulation time	40040512422 ps
CPU time	740.95 seconds
Started	Apr 23 04:43:33 PM PDT 24
Finished	Apr 23 04:55:55 PM PDT 24
Peak memory	562816 kb
Host	smart-cbc5ca25-926f-41ca-b93e-b9245ea2d59c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586831946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.1586831946
Directory	/workspace/53.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.1166153836
Short name	T2012
Test name
Test status
Simulation time	173596805 ps
CPU time	19.77 seconds
Started	Apr 23 04:43:39 PM PDT 24
Finished	Apr 23 04:43:59 PM PDT 24
Peak memory	562716 kb
Host	smart-67c145b1-66eb-4a72-8e0e-29b5cf0dc9e5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166153836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.1166153836
Directory	/workspace/53.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_same_source.1347147605
Short name	T2077
Test name
Test status
Simulation time	1246440411 ps
CPU time	34.96 seconds
Started	Apr 23 04:43:34 PM PDT 24
Finished	Apr 23 04:44:10 PM PDT 24
Peak memory	562692 kb
Host	smart-ca091804-f9d6-427e-81c6-967005095731
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347147605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.1347147605
Directory	/workspace/53.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke.1899940975
Short name	T2708
Test name
Test status
Simulation time	52300983 ps
CPU time	7.1 seconds
Started	Apr 23 04:43:28 PM PDT 24
Finished	Apr 23 04:43:36 PM PDT 24
Peak memory	562680 kb
Host	smart-f20b00f2-23ba-482c-9395-db8354c298da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899940975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1899940975
Directory	/workspace/53.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3640392532
Short name	T2660
Test name
Test status
Simulation time	8211090235 ps
CPU time	90.8 seconds
Started	Apr 23 04:43:28 PM PDT 24
Finished	Apr 23 04:44:59 PM PDT 24
Peak memory	562784 kb
Host	smart-5403a475-cba5-4145-bb5d-fbf6c3fb55a8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640392532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.3640392532
Directory	/workspace/53.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3371608085
Short name	T1789
Test name
Test status
Simulation time	4385354432 ps
CPU time	78.66 seconds
Started	Apr 23 04:43:30 PM PDT 24
Finished	Apr 23 04:44:49 PM PDT 24
Peak memory	562776 kb
Host	smart-9c1ca555-6aae-457a-810d-a12e94a76474
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371608085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.3371608085
Directory	/workspace/53.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.3497199158
Short name	T2427
Test name
Test status
Simulation time	43326348 ps
CPU time	6.28 seconds
Started	Apr 23 04:43:29 PM PDT 24
Finished	Apr 23 04:43:36 PM PDT 24
Peak memory	562676 kb
Host	smart-3dcb1e48-739f-42cc-9364-d1ee9041bd9b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497199158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.3497199158
Directory	/workspace/53.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all.897821471
Short name	T2492
Test name
Test status
Simulation time	2915455789 ps
CPU time	262.08 seconds
Started	Apr 23 04:43:31 PM PDT 24
Finished	Apr 23 04:47:53 PM PDT 24
Peak memory	564028 kb
Host	smart-f1b02119-9a0e-4527-892a-52e70a7799e1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897821471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.897821471
Directory	/workspace/53.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1932542017
Short name	T2231
Test name
Test status
Simulation time	11787684028 ps
CPU time	410.19 seconds
Started	Apr 23 04:43:34 PM PDT 24
Finished	Apr 23 04:50:24 PM PDT 24
Peak memory	562908 kb
Host	smart-8bd57476-f6c5-445d-8b2b-c8af80b43e64
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932542017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1932542017
Directory	/workspace/53.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3018393985
Short name	T430
Test name
Test status
Simulation time	510413866 ps
CPU time	216.27 seconds
Started	Apr 23 04:43:34 PM PDT 24
Finished	Apr 23 04:47:10 PM PDT 24
Peak memory	572000 kb
Host	smart-d42b4792-2776-4c0d-905b-70b33084dae4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018393985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.3018393985
Directory	/workspace/53.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2594993405
Short name	T794
Test name
Test status
Simulation time	2659516896 ps
CPU time	143.53 seconds
Started	Apr 23 04:43:39 PM PDT 24
Finished	Apr 23 04:46:03 PM PDT 24
Peak memory	563952 kb
Host	smart-8066ed13-ec3e-4cbd-946e-a45249bb0798
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594993405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.2594993405
Directory	/workspace/53.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.164012436
Short name	T1652
Test name
Test status
Simulation time	188021708 ps
CPU time	27.77 seconds
Started	Apr 23 04:43:32 PM PDT 24
Finished	Apr 23 04:44:00 PM PDT 24
Peak memory	562800 kb
Host	smart-92bd348f-3234-4cbc-9569-578ce897761b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164012436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.164012436
Directory	/workspace/53.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_access_same_device.2457379550
Short name	T2687
Test name
Test status
Simulation time	1109841599 ps
CPU time	42.69 seconds
Started	Apr 23 04:43:49 PM PDT 24
Finished	Apr 23 04:44:32 PM PDT 24
Peak memory	562764 kb
Host	smart-cb2347ad-35f5-4790-b9dd-6350ba18797b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457379550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .2457379550
Directory	/workspace/54.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.4236234452
Short name	T795
Test name
Test status
Simulation time	29233068621 ps
CPU time	572.39 seconds
Started	Apr 23 04:43:41 PM PDT 24
Finished	Apr 23 04:53:14 PM PDT 24
Peak memory	562864 kb
Host	smart-9e3c2678-3d54-4874-9516-c46d7361e942
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236234452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.4236234452
Directory	/workspace/54.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2222648527
Short name	T2574
Test name
Test status
Simulation time	308399397 ps
CPU time	33.91 seconds
Started	Apr 23 04:43:44 PM PDT 24
Finished	Apr 23 04:44:18 PM PDT 24
Peak memory	562740 kb
Host	smart-a5aabd3b-b106-412e-8127-60a94c46f837
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222648527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.2222648527
Directory	/workspace/54.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_error_random.2064682776
Short name	T1397
Test name
Test status
Simulation time	1841048153 ps
CPU time	63.94 seconds
Started	Apr 23 04:43:49 PM PDT 24
Finished	Apr 23 04:44:54 PM PDT 24
Peak memory	562728 kb
Host	smart-8be5e06f-a534-4743-8777-704c9b9d9b4e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064682776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2064682776
Directory	/workspace/54.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_random.3889316502
Short name	T1735
Test name
Test status
Simulation time	1272694083 ps
CPU time	50.69 seconds
Started	Apr 23 04:43:39 PM PDT 24
Finished	Apr 23 04:44:30 PM PDT 24
Peak memory	562644 kb
Host	smart-943d1b87-aa1b-488a-a1d9-284f04a97952
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889316502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3889316502
Directory	/workspace/54.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_random_large_delays.1874858700
Short name	T1831
Test name
Test status
Simulation time	49594365827 ps
CPU time	506.65 seconds
Started	Apr 23 04:43:43 PM PDT 24
Finished	Apr 23 04:52:10 PM PDT 24
Peak memory	562796 kb
Host	smart-ceabe4cd-9550-410b-aac2-638c9e7aa82b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874858700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.1874858700
Directory	/workspace/54.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2607028702
Short name	T2533
Test name
Test status
Simulation time	16442109441 ps
CPU time	313.26 seconds
Started	Apr 23 04:43:40 PM PDT 24
Finished	Apr 23 04:48:53 PM PDT 24
Peak memory	562792 kb
Host	smart-bd6af8a9-7c96-491d-ae46-e602dca92f24
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607028702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2607028702
Directory	/workspace/54.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.105077187
Short name	T2737
Test name
Test status
Simulation time	456710019 ps
CPU time	43.21 seconds
Started	Apr 23 04:43:43 PM PDT 24
Finished	Apr 23 04:44:27 PM PDT 24
Peak memory	562684 kb
Host	smart-7985e9df-8045-4cde-84e4-1084cbcb7b50
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105077187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_dela ys.105077187
Directory	/workspace/54.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_same_source.1702099547
Short name	T1833
Test name
Test status
Simulation time	1082058657 ps
CPU time	35.38 seconds
Started	Apr 23 04:43:43 PM PDT 24
Finished	Apr 23 04:44:19 PM PDT 24
Peak memory	562704 kb
Host	smart-cf1b7b0f-1fb9-49e2-8414-bcffa5727fb9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702099547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.1702099547
Directory	/workspace/54.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke.3114591553
Short name	T2360
Test name
Test status
Simulation time	175674323 ps
CPU time	8.89 seconds
Started	Apr 23 04:43:35 PM PDT 24
Finished	Apr 23 04:43:45 PM PDT 24
Peak memory	562684 kb
Host	smart-a9d54fd8-b5cf-4a60-9750-d65650897784
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114591553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3114591553
Directory	/workspace/54.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.3326098720
Short name	T1350
Test name
Test status
Simulation time	6390584379 ps
CPU time	68.1 seconds
Started	Apr 23 04:43:37 PM PDT 24
Finished	Apr 23 04:44:45 PM PDT 24
Peak memory	562808 kb
Host	smart-cda5c0d8-946a-4202-a964-1496ad8ee2ec
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326098720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.3326098720
Directory	/workspace/54.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.2262663422
Short name	T2469
Test name
Test status
Simulation time	4425404021 ps
CPU time	78.77 seconds
Started	Apr 23 04:43:39 PM PDT 24
Finished	Apr 23 04:44:58 PM PDT 24
Peak memory	562792 kb
Host	smart-e54b3473-845c-45cf-8a7f-84e44190260f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262663422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.2262663422
Directory	/workspace/54.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1888974210
Short name	T1255
Test name
Test status
Simulation time	40971708 ps
CPU time	6.45 seconds
Started	Apr 23 04:43:34 PM PDT 24
Finished	Apr 23 04:43:40 PM PDT 24
Peak memory	562628 kb
Host	smart-be04d454-a33d-4ad3-a46d-5ae03d544333
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888974210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1888974210
Directory	/workspace/54.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all.776014880
Short name	T604
Test name
Test status
Simulation time	4309141782 ps
CPU time	175.38 seconds
Started	Apr 23 04:43:49 PM PDT 24
Finished	Apr 23 04:46:44 PM PDT 24
Peak memory	563048 kb
Host	smart-d9018441-147d-49ee-9f01-1f4af2e86459
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776014880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.776014880
Directory	/workspace/54.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.992449487
Short name	T1834
Test name
Test status
Simulation time	1071201621 ps
CPU time	101.01 seconds
Started	Apr 23 04:43:46 PM PDT 24
Finished	Apr 23 04:45:27 PM PDT 24
Peak memory	562848 kb
Host	smart-6190383e-305a-4ea4-b20e-4c91a803c416
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992449487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.992449487
Directory	/workspace/54.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3336615734
Short name	T2288
Test name
Test status
Simulation time	346794853 ps
CPU time	43.96 seconds
Started	Apr 23 04:43:49 PM PDT 24
Finished	Apr 23 04:44:33 PM PDT 24
Peak memory	563932 kb
Host	smart-bcf5acfb-cf17-4501-9790-a1a5b035082a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336615734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.3336615734
Directory	/workspace/54.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3612956096
Short name	T2528
Test name
Test status
Simulation time	180540685 ps
CPU time	101.08 seconds
Started	Apr 23 04:43:46 PM PDT 24
Finished	Apr 23 04:45:28 PM PDT 24
Peak memory	563844 kb
Host	smart-e6f1430d-f236-415e-847f-8d0db739e16c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612956096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.3612956096
Directory	/workspace/54.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.4122008592
Short name	T1473
Test name
Test status
Simulation time	1167479001 ps
CPU time	45.58 seconds
Started	Apr 23 04:43:48 PM PDT 24
Finished	Apr 23 04:44:33 PM PDT 24
Peak memory	562796 kb
Host	smart-edfc8be2-5fe3-426a-b36c-3414ba3870dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122008592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.4122008592
Directory	/workspace/54.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_access_same_device.2544160932
Short name	T804
Test name
Test status
Simulation time	1941689418 ps
CPU time	85.26 seconds
Started	Apr 23 04:43:49 PM PDT 24
Finished	Apr 23 04:45:14 PM PDT 24
Peak memory	562776 kb
Host	smart-ff4db2c0-a6b0-414e-bf08-c1c39c98afe6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544160932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .2544160932
Directory	/workspace/55.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1947022539
Short name	T2633
Test name
Test status
Simulation time	131448595362 ps
CPU time	2318.23 seconds
Started	Apr 23 04:43:52 PM PDT 24
Finished	Apr 23 05:22:30 PM PDT 24
Peak memory	562952 kb
Host	smart-87144390-05b6-457b-8fb7-674c89644fc2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947022539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.1947022539
Directory	/workspace/55.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.935758350
Short name	T2731
Test name
Test status
Simulation time	120834574 ps
CPU time	14.03 seconds
Started	Apr 23 04:44:00 PM PDT 24
Finished	Apr 23 04:44:14 PM PDT 24
Peak memory	562688 kb
Host	smart-bf781705-aa65-4e87-af2e-80ce68091510
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935758350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr .935758350
Directory	/workspace/55.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_error_random.1329296119
Short name	T1320
Test name
Test status
Simulation time	322844297 ps
CPU time	25.59 seconds
Started	Apr 23 04:44:03 PM PDT 24
Finished	Apr 23 04:44:29 PM PDT 24
Peak memory	562720 kb
Host	smart-7618bfff-7adc-4300-990d-655e49fffb02
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329296119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1329296119
Directory	/workspace/55.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_random.4224664152
Short name	T2385
Test name
Test status
Simulation time	248688780 ps
CPU time	22.41 seconds
Started	Apr 23 04:43:58 PM PDT 24
Finished	Apr 23 04:44:20 PM PDT 24
Peak memory	562696 kb
Host	smart-982ab6df-2068-4877-8a24-7cb047e003dd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224664152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.4224664152
Directory	/workspace/55.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_random_large_delays.457019384
Short name	T1426
Test name
Test status
Simulation time	61474321451 ps
CPU time	604.29 seconds
Started	Apr 23 04:43:58 PM PDT 24
Finished	Apr 23 04:54:02 PM PDT 24
Peak memory	562772 kb
Host	smart-a2c54c31-c8a3-404c-ac80-574b4828a8bf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457019384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.457019384
Directory	/workspace/55.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.3276435835
Short name	T474
Test name
Test status
Simulation time	48119194229 ps
CPU time	917.26 seconds
Started	Apr 23 04:43:52 PM PDT 24
Finished	Apr 23 04:59:09 PM PDT 24
Peak memory	562816 kb
Host	smart-ec1c3f6e-6a69-4874-9d5d-19d3bc69436b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276435835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3276435835
Directory	/workspace/55.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.3180293316
Short name	T587
Test name
Test status
Simulation time	370534807 ps
CPU time	38.97 seconds
Started	Apr 23 04:43:50 PM PDT 24
Finished	Apr 23 04:44:29 PM PDT 24
Peak memory	562776 kb
Host	smart-89bb1215-eb0c-476b-9a6a-b1b0ed094ac6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180293316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.3180293316
Directory	/workspace/55.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_same_source.155268980
Short name	T1884
Test name
Test status
Simulation time	532858377 ps
CPU time	36.67 seconds
Started	Apr 23 04:43:50 PM PDT 24
Finished	Apr 23 04:44:27 PM PDT 24
Peak memory	562748 kb
Host	smart-4834998a-c981-4c3f-90f4-05c3edec0554
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155268980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.155268980
Directory	/workspace/55.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke.444278602
Short name	T1823
Test name
Test status
Simulation time	51082000 ps
CPU time	6.27 seconds
Started	Apr 23 04:43:57 PM PDT 24
Finished	Apr 23 04:44:03 PM PDT 24
Peak memory	562684 kb
Host	smart-4cf68216-4d44-4c12-a955-faed9efc9a79
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444278602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.444278602
Directory	/workspace/55.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2966384672
Short name	T1422
Test name
Test status
Simulation time	8023924716 ps
CPU time	84.63 seconds
Started	Apr 23 04:43:46 PM PDT 24
Finished	Apr 23 04:45:11 PM PDT 24
Peak memory	562772 kb
Host	smart-2016ad85-1804-48ca-9099-bbf100af1cfc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966384672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2966384672
Directory	/workspace/55.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1112707081
Short name	T2774
Test name
Test status
Simulation time	5647001611 ps
CPU time	91.11 seconds
Started	Apr 23 04:43:58 PM PDT 24
Finished	Apr 23 04:45:29 PM PDT 24
Peak memory	562756 kb
Host	smart-195c345e-4de6-470a-bf55-acf6f742b706
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112707081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.1112707081
Directory	/workspace/55.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.1669481296
Short name	T1994
Test name
Test status
Simulation time	46581726 ps
CPU time	7.34 seconds
Started	Apr 23 04:43:49 PM PDT 24
Finished	Apr 23 04:43:57 PM PDT 24
Peak memory	562668 kb
Host	smart-9735d8a2-1d4b-489a-893f-4b79c9a041ed
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669481296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.1669481296
Directory	/workspace/55.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all.3374132237
Short name	T1482
Test name
Test status
Simulation time	176523230 ps
CPU time	15.2 seconds
Started	Apr 23 04:44:03 PM PDT 24
Finished	Apr 23 04:44:19 PM PDT 24
Peak memory	562764 kb
Host	smart-b6d43e1b-232c-42c1-8d17-cd74e480f0fb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374132237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3374132237
Directory	/workspace/55.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.1997796979
Short name	T1976
Test name
Test status
Simulation time	5623080247 ps
CPU time	199.47 seconds
Started	Apr 23 04:43:52 PM PDT 24
Finished	Apr 23 04:47:11 PM PDT 24
Peak memory	571068 kb
Host	smart-3b5e1f62-9fbf-4912-9690-ccc77558aa1d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997796979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.1997796979
Directory	/workspace/55.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2420059410
Short name	T2658
Test name
Test status
Simulation time	426911126 ps
CPU time	127.58 seconds
Started	Apr 23 04:43:53 PM PDT 24
Finished	Apr 23 04:46:01 PM PDT 24
Peak memory	563908 kb
Host	smart-28f3fbb3-3461-4080-b244-49e5efe632ef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420059410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.2420059410
Directory	/workspace/55.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.616120612
Short name	T2602
Test name
Test status
Simulation time	1710245398 ps
CPU time	290.84 seconds
Started	Apr 23 04:43:56 PM PDT 24
Finished	Apr 23 04:48:47 PM PDT 24
Peak memory	572100 kb
Host	smart-7d1b7a48-f1cb-4eff-ae96-07a01470f3c8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616120612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_reset_error.616120612
Directory	/workspace/55.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.2118842070
Short name	T2685
Test name
Test status
Simulation time	126937125 ps
CPU time	9.01 seconds
Started	Apr 23 04:43:53 PM PDT 24
Finished	Apr 23 04:44:03 PM PDT 24
Peak memory	562752 kb
Host	smart-89fd0ae1-ae84-4efb-b91c-cf3fed8420cf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118842070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.2118842070
Directory	/workspace/55.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_access_same_device.1576621287
Short name	T2291
Test name
Test status
Simulation time	203304606 ps
CPU time	16.64 seconds
Started	Apr 23 04:43:57 PM PDT 24
Finished	Apr 23 04:44:14 PM PDT 24
Peak memory	562732 kb
Host	smart-37a7e52b-5353-430d-96c9-0b587d1ab10e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576621287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .1576621287
Directory	/workspace/56.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3246392019
Short name	T1821
Test name
Test status
Simulation time	49823347910 ps
CPU time	836.45 seconds
Started	Apr 23 04:43:58 PM PDT 24
Finished	Apr 23 04:57:54 PM PDT 24
Peak memory	562768 kb
Host	smart-7410b667-72e3-4fcb-8512-bcb8a1cacf90
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246392019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.3246392019
Directory	/workspace/56.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3090289056
Short name	T1307
Test name
Test status
Simulation time	257145322 ps
CPU time	25.94 seconds
Started	Apr 23 04:43:59 PM PDT 24
Finished	Apr 23 04:44:26 PM PDT 24
Peak memory	562728 kb
Host	smart-ed34cffd-e01b-42f5-9d3d-c89cf8a06b40
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090289056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.3090289056
Directory	/workspace/56.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_error_random.1509476133
Short name	T2637
Test name
Test status
Simulation time	2246690790 ps
CPU time	83.76 seconds
Started	Apr 23 04:43:59 PM PDT 24
Finished	Apr 23 04:45:23 PM PDT 24
Peak memory	562744 kb
Host	smart-019f9804-62da-4cac-a373-e0a7f6f04f85
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509476133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.1509476133
Directory	/workspace/56.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_random.2744948833
Short name	T1665
Test name
Test status
Simulation time	2218809051 ps
CPU time	78.38 seconds
Started	Apr 23 04:44:02 PM PDT 24
Finished	Apr 23 04:45:21 PM PDT 24
Peak memory	562808 kb
Host	smart-ef048676-73ac-4d94-b427-93eaf1d62e27
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744948833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2744948833
Directory	/workspace/56.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_random_large_delays.2818032662
Short name	T2178
Test name
Test status
Simulation time	71093506180 ps
CPU time	841.76 seconds
Started	Apr 23 04:43:58 PM PDT 24
Finished	Apr 23 04:58:00 PM PDT 24
Peak memory	562712 kb
Host	smart-3c0005fb-d720-4aa6-98af-4d28e47e38a9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818032662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.2818032662
Directory	/workspace/56.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.53910730
Short name	T1456
Test name
Test status
Simulation time	7364816729 ps
CPU time	117.77 seconds
Started	Apr 23 04:44:02 PM PDT 24
Finished	Apr 23 04:46:00 PM PDT 24
Peak memory	562784 kb
Host	smart-42faa35d-4ccb-4955-a84a-f4e36ed1ebe9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53910730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.53910730
Directory	/workspace/56.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.2291589798
Short name	T2366
Test name
Test status
Simulation time	480701863 ps
CPU time	42.65 seconds
Started	Apr 23 04:44:02 PM PDT 24
Finished	Apr 23 04:44:45 PM PDT 24
Peak memory	562756 kb
Host	smart-c3e755d3-42dd-4b9c-8f3e-2a69eeed5807
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291589798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.2291589798
Directory	/workspace/56.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_same_source.1207389214
Short name	T2470
Test name
Test status
Simulation time	1743234075 ps
CPU time	52.39 seconds
Started	Apr 23 04:43:58 PM PDT 24
Finished	Apr 23 04:44:50 PM PDT 24
Peak memory	562716 kb
Host	smart-9b80007c-9089-453b-8a11-279f192e434a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207389214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.1207389214
Directory	/workspace/56.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke.3466813210
Short name	T2053
Test name
Test status
Simulation time	224837359 ps
CPU time	11.04 seconds
Started	Apr 23 04:43:53 PM PDT 24
Finished	Apr 23 04:44:04 PM PDT 24
Peak memory	562692 kb
Host	smart-e7bd9ce2-65c0-4da3-9e2f-27148974d771
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466813210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.3466813210
Directory	/workspace/56.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3863735257
Short name	T2428
Test name
Test status
Simulation time	6987940537 ps
CPU time	74.2 seconds
Started	Apr 23 04:44:00 PM PDT 24
Finished	Apr 23 04:45:14 PM PDT 24
Peak memory	562764 kb
Host	smart-6c99fd6d-3c25-4880-bcac-d1adfdb7e899
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863735257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3863735257
Directory	/workspace/56.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1309806012
Short name	T1323
Test name
Test status
Simulation time	6021011503 ps
CPU time	102.52 seconds
Started	Apr 23 04:43:58 PM PDT 24
Finished	Apr 23 04:45:41 PM PDT 24
Peak memory	562792 kb
Host	smart-19ab055e-a9f9-454b-b530-59d3c963e2e9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309806012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.1309806012
Directory	/workspace/56.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3802318034
Short name	T2684
Test name
Test status
Simulation time	45893590 ps
CPU time	6.42 seconds
Started	Apr 23 04:43:53 PM PDT 24
Finished	Apr 23 04:44:00 PM PDT 24
Peak memory	562720 kb
Host	smart-b0030089-0882-4eef-a161-cc48c25dca05
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802318034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.3802318034
Directory	/workspace/56.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all.1939352946
Short name	T1586
Test name
Test status
Simulation time	6981140279 ps
CPU time	301.14 seconds
Started	Apr 23 04:43:59 PM PDT 24
Finished	Apr 23 04:49:01 PM PDT 24
Peak memory	571680 kb
Host	smart-7da3f7c8-7101-4110-b161-572f5c4656ed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939352946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.1939352946
Directory	/workspace/56.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.1040268960
Short name	T2503
Test name
Test status
Simulation time	14031176352 ps
CPU time	544.41 seconds
Started	Apr 23 04:44:01 PM PDT 24
Finished	Apr 23 04:53:06 PM PDT 24
Peak memory	564032 kb
Host	smart-c43be6ba-548b-4f1b-9a70-f8570a3f50c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040268960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.1040268960
Directory	/workspace/56.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2439690268
Short name	T2128
Test name
Test status
Simulation time	699557055 ps
CPU time	279.04 seconds
Started	Apr 23 04:43:59 PM PDT 24
Finished	Apr 23 04:48:38 PM PDT 24
Peak memory	572144 kb
Host	smart-5be0f9d3-7b64-428d-88bc-900d80668ac7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439690268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.2439690268
Directory	/workspace/56.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1489400147
Short name	T808
Test name
Test status
Simulation time	5539197768 ps
CPU time	554.23 seconds
Started	Apr 23 04:43:59 PM PDT 24
Finished	Apr 23 04:53:14 PM PDT 24
Peak memory	572200 kb
Host	smart-a4c91a3b-5219-4c3f-b32c-9ab19d825551
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489400147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.1489400147
Directory	/workspace/56.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.1909846491
Short name	T2573
Test name
Test status
Simulation time	1053242990 ps
CPU time	50.11 seconds
Started	Apr 23 04:43:59 PM PDT 24
Finished	Apr 23 04:44:50 PM PDT 24
Peak memory	562836 kb
Host	smart-6fba6126-7fd0-412e-9c5c-3931ad082c50
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909846491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.1909846491
Directory	/workspace/56.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_access_same_device.2432682167
Short name	T403
Test name
Test status
Simulation time	2203256778 ps
CPU time	105.3 seconds
Started	Apr 23 04:44:05 PM PDT 24
Finished	Apr 23 04:45:51 PM PDT 24
Peak memory	562864 kb
Host	smart-83050fc4-97bf-4f00-b1c6-3a42f03faee4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432682167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .2432682167
Directory	/workspace/57.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1055133549
Short name	T2669
Test name
Test status
Simulation time	281514138 ps
CPU time	33.79 seconds
Started	Apr 23 04:44:10 PM PDT 24
Finished	Apr 23 04:44:44 PM PDT 24
Peak memory	562728 kb
Host	smart-23d830f4-70da-48f4-8883-280e6b1870e6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055133549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.1055133549
Directory	/workspace/57.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_error_random.574988970
Short name	T2269
Test name
Test status
Simulation time	298347859 ps
CPU time	28.49 seconds
Started	Apr 23 04:44:08 PM PDT 24
Finished	Apr 23 04:44:37 PM PDT 24
Peak memory	562656 kb
Host	smart-1e14f4b2-16eb-4216-a58f-eb8be8fc9fd1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574988970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.574988970
Directory	/workspace/57.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_random.4002885831
Short name	T2241
Test name
Test status
Simulation time	1598042859 ps
CPU time	67.63 seconds
Started	Apr 23 04:44:07 PM PDT 24
Finished	Apr 23 04:45:15 PM PDT 24
Peak memory	562780 kb
Host	smart-a8b0c7a9-c737-4fd9-a652-93db45556d80
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002885831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.4002885831
Directory	/workspace/57.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_random_large_delays.3936563835
Short name	T2005
Test name
Test status
Simulation time	93556600870 ps
CPU time	944.97 seconds
Started	Apr 23 04:44:09 PM PDT 24
Finished	Apr 23 04:59:54 PM PDT 24
Peak memory	562776 kb
Host	smart-14e2f037-4005-4189-a6f0-85a065b728ed
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936563835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.3936563835
Directory	/workspace/57.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.1501047067
Short name	T1714
Test name
Test status
Simulation time	35437905622 ps
CPU time	637.93 seconds
Started	Apr 23 04:44:05 PM PDT 24
Finished	Apr 23 04:54:43 PM PDT 24
Peak memory	562744 kb
Host	smart-8db54762-7921-4f38-85f9-00f58aaa925d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501047067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.1501047067
Directory	/workspace/57.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2039713600
Short name	T2792
Test name
Test status
Simulation time	507522245 ps
CPU time	40.94 seconds
Started	Apr 23 04:44:10 PM PDT 24
Finished	Apr 23 04:44:51 PM PDT 24
Peak memory	562680 kb
Host	smart-d19ac93b-3f24-4958-87fe-4cec4e009186
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039713600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.2039713600
Directory	/workspace/57.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_same_source.1310086955
Short name	T1724
Test name
Test status
Simulation time	1989930398 ps
CPU time	64.07 seconds
Started	Apr 23 04:44:09 PM PDT 24
Finished	Apr 23 04:45:13 PM PDT 24
Peak memory	562720 kb
Host	smart-9a06987c-375a-4aa1-b378-e7d83eff7c6b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310086955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.1310086955
Directory	/workspace/57.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke.3483756300
Short name	T1478
Test name
Test status
Simulation time	158211052 ps
CPU time	8.3 seconds
Started	Apr 23 04:44:04 PM PDT 24
Finished	Apr 23 04:44:12 PM PDT 24
Peak memory	562680 kb
Host	smart-134e61c8-d1c8-4f18-b4d1-da7a4eb440a3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483756300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.3483756300
Directory	/workspace/57.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1858286042
Short name	T1524
Test name
Test status
Simulation time	9037683761 ps
CPU time	100.02 seconds
Started	Apr 23 04:44:03 PM PDT 24
Finished	Apr 23 04:45:44 PM PDT 24
Peak memory	562808 kb
Host	smart-9aa309cd-f238-4cd7-b563-0a397bd2ad37
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858286042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1858286042
Directory	/workspace/57.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1629378707
Short name	T1377
Test name
Test status
Simulation time	5758892947 ps
CPU time	102.59 seconds
Started	Apr 23 04:44:01 PM PDT 24
Finished	Apr 23 04:45:43 PM PDT 24
Peak memory	562780 kb
Host	smart-2402fa28-a31f-46b2-8077-e1e6e7410465
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629378707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.1629378707
Directory	/workspace/57.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.311926334
Short name	T2267
Test name
Test status
Simulation time	44367341 ps
CPU time	6.61 seconds
Started	Apr 23 04:44:02 PM PDT 24
Finished	Apr 23 04:44:09 PM PDT 24
Peak memory	562724 kb
Host	smart-ca326cf5-5563-4d40-a483-53e59971d086
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311926334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays .311926334
Directory	/workspace/57.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all.1193319946
Short name	T2054
Test name
Test status
Simulation time	2692533817 ps
CPU time	186.34 seconds
Started	Apr 23 04:44:07 PM PDT 24
Finished	Apr 23 04:47:14 PM PDT 24
Peak memory	563932 kb
Host	smart-eaff4d99-9639-4d46-a7f1-ebde26a0b40c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193319946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.1193319946
Directory	/workspace/57.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2425760769
Short name	T1700
Test name
Test status
Simulation time	216850365 ps
CPU time	9.92 seconds
Started	Apr 23 04:44:11 PM PDT 24
Finished	Apr 23 04:44:21 PM PDT 24
Peak memory	562700 kb
Host	smart-3adda104-637c-4fc0-8ed0-7fa7a2c22825
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425760769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2425760769
Directory	/workspace/57.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2319707529
Short name	T815
Test name
Test status
Simulation time	864575417 ps
CPU time	311.96 seconds
Started	Apr 23 04:44:09 PM PDT 24
Finished	Apr 23 04:49:21 PM PDT 24
Peak memory	572088 kb
Host	smart-6e9a3569-8526-4024-b6d7-6c2e7080dcfc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319707529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.2319707529
Directory	/workspace/57.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.475338925
Short name	T510
Test name
Test status
Simulation time	831066523 ps
CPU time	256.05 seconds
Started	Apr 23 04:44:13 PM PDT 24
Finished	Apr 23 04:48:29 PM PDT 24
Peak memory	572176 kb
Host	smart-33424aff-f87f-4e0d-bac3-6868ab895aba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475338925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_reset_error.475338925
Directory	/workspace/57.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.4206187768
Short name	T1452
Test name
Test status
Simulation time	66245549 ps
CPU time	5.84 seconds
Started	Apr 23 04:44:08 PM PDT 24
Finished	Apr 23 04:44:15 PM PDT 24
Peak memory	562712 kb
Host	smart-8d200de8-56a8-4a8a-9e05-eaf78a22b1ed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206187768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.4206187768
Directory	/workspace/57.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_access_same_device.3858710897
Short name	T1619
Test name
Test status
Simulation time	347629271 ps
CPU time	30.43 seconds
Started	Apr 23 04:44:13 PM PDT 24
Finished	Apr 23 04:44:43 PM PDT 24
Peak memory	562676 kb
Host	smart-e7e91910-bfb1-408a-91e8-928304759aab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858710897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .3858710897
Directory	/workspace/58.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3358293800
Short name	T2052
Test name
Test status
Simulation time	83876508523 ps
CPU time	1479.47 seconds
Started	Apr 23 04:44:13 PM PDT 24
Finished	Apr 23 05:08:53 PM PDT 24
Peak memory	562864 kb
Host	smart-b374543c-c74d-44e0-9a03-466459760c9a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358293800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.3358293800
Directory	/workspace/58.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.356007638
Short name	T2284
Test name
Test status
Simulation time	279344910 ps
CPU time	15.58 seconds
Started	Apr 23 04:44:17 PM PDT 24
Finished	Apr 23 04:44:33 PM PDT 24
Peak memory	562708 kb
Host	smart-cd62adf2-a904-4c6c-a199-9c59cc9f218b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356007638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr .356007638
Directory	/workspace/58.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_error_random.1461817507
Short name	T2581
Test name
Test status
Simulation time	42286622 ps
CPU time	6.76 seconds
Started	Apr 23 04:44:14 PM PDT 24
Finished	Apr 23 04:44:21 PM PDT 24
Peak memory	562708 kb
Host	smart-2739e985-2068-4559-8516-8b3de4ccddd1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461817507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.1461817507
Directory	/workspace/58.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_random.2034634132
Short name	T2636
Test name
Test status
Simulation time	1028397378 ps
CPU time	39.93 seconds
Started	Apr 23 04:44:11 PM PDT 24
Finished	Apr 23 04:44:51 PM PDT 24
Peak memory	562748 kb
Host	smart-36985895-eb3d-4459-9b40-cc8b54462df6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034634132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.2034634132
Directory	/workspace/58.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_random_large_delays.2502802286
Short name	T2316
Test name
Test status
Simulation time	78615820982 ps
CPU time	820.19 seconds
Started	Apr 23 04:44:14 PM PDT 24
Finished	Apr 23 04:57:54 PM PDT 24
Peak memory	562848 kb
Host	smart-7379b33c-35ff-4797-ad5e-46a65dacbcd0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502802286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.2502802286
Directory	/workspace/58.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.745987891
Short name	T2117
Test name
Test status
Simulation time	14907118861 ps
CPU time	265.45 seconds
Started	Apr 23 04:44:14 PM PDT 24
Finished	Apr 23 04:48:40 PM PDT 24
Peak memory	562800 kb
Host	smart-3db647d0-6e11-4f31-baf6-af7c4c587d23
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745987891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.745987891
Directory	/workspace/58.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3673353972
Short name	T484
Test name
Test status
Simulation time	580543178 ps
CPU time	53.44 seconds
Started	Apr 23 04:44:11 PM PDT 24
Finished	Apr 23 04:45:05 PM PDT 24
Peak memory	562732 kb
Host	smart-1054f3e8-1bba-4f09-b62e-e160a37b2e8a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673353972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.3673353972
Directory	/workspace/58.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_same_source.4084128184
Short name	T2595
Test name
Test status
Simulation time	2725354909 ps
CPU time	85.46 seconds
Started	Apr 23 04:44:15 PM PDT 24
Finished	Apr 23 04:45:40 PM PDT 24
Peak memory	562784 kb
Host	smart-cebdb8a3-acbf-46ab-8063-5fe38e329dc6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084128184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.4084128184
Directory	/workspace/58.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke.3053633582
Short name	T2356
Test name
Test status
Simulation time	184763063 ps
CPU time	8.33 seconds
Started	Apr 23 04:44:13 PM PDT 24
Finished	Apr 23 04:44:21 PM PDT 24
Peak memory	562672 kb
Host	smart-c9bf1112-9284-420a-940e-bd95abb698fb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053633582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.3053633582
Directory	/workspace/58.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.1629919340
Short name	T2317
Test name
Test status
Simulation time	10540213213 ps
CPU time	118.17 seconds
Started	Apr 23 04:44:12 PM PDT 24
Finished	Apr 23 04:46:10 PM PDT 24
Peak memory	562716 kb
Host	smart-b205eec8-ddcc-4d48-b2ef-152424e9b702
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629919340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.1629919340
Directory	/workspace/58.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.698169811
Short name	T2083
Test name
Test status
Simulation time	6404818646 ps
CPU time	112.04 seconds
Started	Apr 23 04:44:13 PM PDT 24
Finished	Apr 23 04:46:05 PM PDT 24
Peak memory	562744 kb
Host	smart-b35e8827-b66e-4ce6-bda7-1bb947f0b25d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698169811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.698169811
Directory	/workspace/58.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3513448872
Short name	T2145
Test name
Test status
Simulation time	38544662 ps
CPU time	6.39 seconds
Started	Apr 23 04:44:10 PM PDT 24
Finished	Apr 23 04:44:16 PM PDT 24
Peak memory	562712 kb
Host	smart-9c8a0271-045c-42e9-a3b8-d9574840a44d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513448872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.3513448872
Directory	/workspace/58.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all.1952036427
Short name	T2707
Test name
Test status
Simulation time	638153801 ps
CPU time	54.04 seconds
Started	Apr 23 04:44:18 PM PDT 24
Finished	Apr 23 04:45:12 PM PDT 24
Peak memory	562900 kb
Host	smart-e4042f23-da0e-4c58-89d4-8f2d560429a5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952036427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.1952036427
Directory	/workspace/58.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.4072431830
Short name	T1279
Test name
Test status
Simulation time	11399857344 ps
CPU time	389.52 seconds
Started	Apr 23 04:44:18 PM PDT 24
Finished	Apr 23 04:50:48 PM PDT 24
Peak memory	563908 kb
Host	smart-0705018b-7ad7-4b88-a719-90a4c6a0c7bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072431830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.4072431830
Directory	/workspace/58.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3797988459
Short name	T469
Test name
Test status
Simulation time	2871565707 ps
CPU time	304.95 seconds
Started	Apr 23 04:44:17 PM PDT 24
Finished	Apr 23 04:49:22 PM PDT 24
Peak memory	572184 kb
Host	smart-524a00ca-bc3c-41c9-899e-3a73f11448bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797988459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3797988459
Directory	/workspace/58.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.4057817288
Short name	T817
Test name
Test status
Simulation time	204362032 ps
CPU time	44.21 seconds
Started	Apr 23 04:44:21 PM PDT 24
Finished	Apr 23 04:45:05 PM PDT 24
Peak memory	563160 kb
Host	smart-3f130b10-dde5-415f-b15d-922506ad05fa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057817288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.4057817288
Directory	/workspace/58.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3681558254
Short name	T1765
Test name
Test status
Simulation time	1003390006 ps
CPU time	42.44 seconds
Started	Apr 23 04:44:17 PM PDT 24
Finished	Apr 23 04:44:59 PM PDT 24
Peak memory	562740 kb
Host	smart-84df5fb1-03d3-456d-8088-f6c2b8113f26
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681558254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.3681558254
Directory	/workspace/58.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_access_same_device.2784071035
Short name	T1916
Test name
Test status
Simulation time	928498789 ps
CPU time	47.77 seconds
Started	Apr 23 04:44:25 PM PDT 24
Finished	Apr 23 04:45:13 PM PDT 24
Peak memory	562724 kb
Host	smart-909efbbc-202b-4706-bea1-25daec72870d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784071035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .2784071035
Directory	/workspace/59.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.762918058
Short name	T2420
Test name
Test status
Simulation time	13435017481 ps
CPU time	240.67 seconds
Started	Apr 23 04:44:26 PM PDT 24
Finished	Apr 23 04:48:28 PM PDT 24
Peak memory	562764 kb
Host	smart-9fdb9450-a236-4c8c-bceb-bf466c837d44
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762918058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_d evice_slow_rsp.762918058
Directory	/workspace/59.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.507441339
Short name	T2215
Test name
Test status
Simulation time	18854046 ps
CPU time	5.52 seconds
Started	Apr 23 04:44:28 PM PDT 24
Finished	Apr 23 04:44:34 PM PDT 24
Peak memory	562712 kb
Host	smart-aa3dfca9-365d-4d07-bd6f-14aa9a51a82e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507441339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr .507441339
Directory	/workspace/59.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_error_random.3292908674
Short name	T2297
Test name
Test status
Simulation time	507508199 ps
CPU time	20.6 seconds
Started	Apr 23 04:44:29 PM PDT 24
Finished	Apr 23 04:44:50 PM PDT 24
Peak memory	562656 kb
Host	smart-304043bd-4da2-4f94-93c5-06ad9c65e87a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292908674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.3292908674
Directory	/workspace/59.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_random.4048147101
Short name	T393
Test name
Test status
Simulation time	505868197 ps
CPU time	44.06 seconds
Started	Apr 23 04:44:25 PM PDT 24
Finished	Apr 23 04:45:10 PM PDT 24
Peak memory	562764 kb
Host	smart-fa471a3e-711f-4299-bda4-30bba38d3900
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048147101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.4048147101
Directory	/workspace/59.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_random_large_delays.2067880349
Short name	T1272
Test name
Test status
Simulation time	46964642137 ps
CPU time	473.97 seconds
Started	Apr 23 04:44:25 PM PDT 24
Finished	Apr 23 04:52:20 PM PDT 24
Peak memory	562756 kb
Host	smart-193bf0fa-4ba1-412f-b4d9-c4d424db9040
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067880349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.2067880349
Directory	/workspace/59.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3627130626
Short name	T541
Test name
Test status
Simulation time	22807873593 ps
CPU time	422.63 seconds
Started	Apr 23 04:44:24 PM PDT 24
Finished	Apr 23 04:51:27 PM PDT 24
Peak memory	562792 kb
Host	smart-a7121e76-52c9-44f8-9f97-e0d4ad3f6c1a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627130626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.3627130626
Directory	/workspace/59.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.3207960940
Short name	T1929
Test name
Test status
Simulation time	83341610 ps
CPU time	10.56 seconds
Started	Apr 23 04:44:26 PM PDT 24
Finished	Apr 23 04:44:37 PM PDT 24
Peak memory	562752 kb
Host	smart-4acbdc6d-9fe3-4b73-a6a8-f6a3a7d62704
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207960940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.3207960940
Directory	/workspace/59.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_same_source.3555738426
Short name	T1477
Test name
Test status
Simulation time	964410613 ps
CPU time	26.63 seconds
Started	Apr 23 04:44:24 PM PDT 24
Finished	Apr 23 04:44:51 PM PDT 24
Peak memory	562720 kb
Host	smart-51ac1a3d-e5f4-497c-a89c-22f80a701876
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555738426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3555738426
Directory	/workspace/59.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke.3308790935
Short name	T2717
Test name
Test status
Simulation time	49008501 ps
CPU time	6.89 seconds
Started	Apr 23 04:44:23 PM PDT 24
Finished	Apr 23 04:44:30 PM PDT 24
Peak memory	562672 kb
Host	smart-97a4d829-08ff-4014-8cb3-13dfec2c5b8e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308790935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3308790935
Directory	/workspace/59.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1995335450
Short name	T2662
Test name
Test status
Simulation time	7623405272 ps
CPU time	85.59 seconds
Started	Apr 23 04:44:24 PM PDT 24
Finished	Apr 23 04:45:50 PM PDT 24
Peak memory	562772 kb
Host	smart-3204fc93-a30b-4f70-82ed-4ea977bbfdab
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995335450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1995335450
Directory	/workspace/59.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1838493425
Short name	T1291
Test name
Test status
Simulation time	5199110170 ps
CPU time	94.18 seconds
Started	Apr 23 04:44:23 PM PDT 24
Finished	Apr 23 04:45:58 PM PDT 24
Peak memory	562804 kb
Host	smart-3b135271-67ca-4f8a-8fe3-000e16c3b071
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838493425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.1838493425
Directory	/workspace/59.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1767404982
Short name	T2719
Test name
Test status
Simulation time	49589163 ps
CPU time	6.4 seconds
Started	Apr 23 04:44:23 PM PDT 24
Finished	Apr 23 04:44:29 PM PDT 24
Peak memory	562724 kb
Host	smart-544ccc87-cbc5-4616-a068-1eb9b008752f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767404982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.1767404982
Directory	/workspace/59.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all.2813432956
Short name	T425
Test name
Test status
Simulation time	17424990246 ps
CPU time	862.9 seconds
Started	Apr 23 04:44:28 PM PDT 24
Finished	Apr 23 04:58:51 PM PDT 24
Peak memory	563712 kb
Host	smart-6c8c8dc4-bce4-4008-8047-0e74d5634cac
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813432956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.2813432956
Directory	/workspace/59.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.3437506259
Short name	T1243
Test name
Test status
Simulation time	3477887275 ps
CPU time	132.62 seconds
Started	Apr 23 04:44:36 PM PDT 24
Finished	Apr 23 04:46:48 PM PDT 24
Peak memory	562872 kb
Host	smart-b517753c-b935-4b5b-8f99-d6ed09581b49
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437506259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.3437506259
Directory	/workspace/59.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.888225117
Short name	T1587
Test name
Test status
Simulation time	232796033 ps
CPU time	148.38 seconds
Started	Apr 23 04:44:29 PM PDT 24
Finished	Apr 23 04:46:58 PM PDT 24
Peak memory	572124 kb
Host	smart-e9bd516b-94b2-490f-8df7-93c269ac0e0d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888225117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_ with_rand_reset.888225117
Directory	/workspace/59.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1078419266
Short name	T2796
Test name
Test status
Simulation time	484631671 ps
CPU time	131.65 seconds
Started	Apr 23 04:44:34 PM PDT 24
Finished	Apr 23 04:46:46 PM PDT 24
Peak memory	572144 kb
Host	smart-e370a6df-d78b-416c-a447-0e89a93ccf22
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078419266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.1078419266
Directory	/workspace/59.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.269840418
Short name	T2038
Test name
Test status
Simulation time	770445423 ps
CPU time	36.18 seconds
Started	Apr 23 04:44:28 PM PDT 24
Finished	Apr 23 04:45:04 PM PDT 24
Peak memory	562776 kb
Host	smart-58d246f6-2fbb-4d19-941a-548715f01a46
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269840418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.269840418
Directory	/workspace/59.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/6.chip_csr_rw.3721053692
Short name	T2362
Test name
Test status
Simulation time	4955677128 ps
CPU time	494.68 seconds
Started	Apr 23 04:32:18 PM PDT 24
Finished	Apr 23 04:40:33 PM PDT 24
Peak memory	590860 kb
Host	smart-35dfcafe-eaaa-4f65-bba1-b6b3de4336bc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721053692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.3721053692
Directory	/workspace/6.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.1883278362
Short name	T368
Test name
Test status
Simulation time	32944357124 ps
CPU time	4052.87 seconds
Started	Apr 23 04:31:41 PM PDT 24
Finished	Apr 23 05:39:15 PM PDT 24
Peak memory	585112 kb
Host	smart-23108096-62f1-49a6-947f-9b18f2831bd5
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883278362 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.1883278362
Directory	/workspace/6.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.chip_tl_errors.1049741481
Short name	T634
Test name
Test status
Simulation time	3041788936 ps
CPU time	192.27 seconds
Started	Apr 23 04:31:45 PM PDT 24
Finished	Apr 23 04:34:57 PM PDT 24
Peak memory	585204 kb
Host	smart-15db7158-fd8c-4625-a74a-b5145ace2692
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049741481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1049741481
Directory	/workspace/6.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_access_same_device.1837343681
Short name	T1567
Test name
Test status
Simulation time	2594706924 ps
CPU time	120.03 seconds
Started	Apr 23 04:32:02 PM PDT 24
Finished	Apr 23 04:34:02 PM PDT 24
Peak memory	562908 kb
Host	smart-a161e6d4-95d8-4b60-8481-6c12995b7b35
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837343681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 1837343681
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2375580769
Short name	T787
Test name
Test status
Simulation time	46629631194 ps
CPU time	827.65 seconds
Started	Apr 23 04:31:59 PM PDT 24
Finished	Apr 23 04:45:47 PM PDT 24
Peak memory	562824 kb
Host	smart-13e52ab0-86b9-4706-a2f5-16ce8909e3b9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375580769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.2375580769
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3985551800
Short name	T1223
Test name
Test status
Simulation time	182950333 ps
CPU time	12.14 seconds
Started	Apr 23 04:32:10 PM PDT 24
Finished	Apr 23 04:32:22 PM PDT 24
Peak memory	562756 kb
Host	smart-8c99f6c9-405c-4ae7-822c-9ca0cdc2cbaa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985551800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3985551800
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_error_random.359997177
Short name	T2607
Test name
Test status
Simulation time	1380884263 ps
CPU time	46.14 seconds
Started	Apr 23 04:32:07 PM PDT 24
Finished	Apr 23 04:32:54 PM PDT 24
Peak memory	562680 kb
Host	smart-3efd615a-ccda-42f4-8d73-8d60ff7783ba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359997177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.359997177
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_random.3728457391
Short name	T429
Test name
Test status
Simulation time	1431378778 ps
CPU time	61.23 seconds
Started	Apr 23 04:31:57 PM PDT 24
Finished	Apr 23 04:32:58 PM PDT 24
Peak memory	562732 kb
Host	smart-e1180bba-e54c-4693-9be8-05441715ff79
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728457391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.3728457391
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_random_large_delays.2026962095
Short name	T477
Test name
Test status
Simulation time	89042029666 ps
CPU time	984.04 seconds
Started	Apr 23 04:31:57 PM PDT 24
Finished	Apr 23 04:48:21 PM PDT 24
Peak memory	562816 kb
Host	smart-368c4958-ad92-4341-a1bb-264eede72e12
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026962095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2026962095
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.3581010027
Short name	T1511
Test name
Test status
Simulation time	15744704542 ps
CPU time	251.37 seconds
Started	Apr 23 04:32:02 PM PDT 24
Finished	Apr 23 04:36:14 PM PDT 24
Peak memory	562812 kb
Host	smart-ca44e704-b431-4468-b2c9-bf0b373af914
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581010027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3581010027
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.1094049420
Short name	T1556
Test name
Test status
Simulation time	42498535 ps
CPU time	7.47 seconds
Started	Apr 23 04:31:57 PM PDT 24
Finished	Apr 23 04:32:04 PM PDT 24
Peak memory	562708 kb
Host	smart-ca2af970-7838-4e66-ba98-53c712ba85f5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094049420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.1094049420
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_same_source.3501489256
Short name	T2218
Test name
Test status
Simulation time	1212498483 ps
CPU time	44.11 seconds
Started	Apr 23 04:32:04 PM PDT 24
Finished	Apr 23 04:32:48 PM PDT 24
Peak memory	562712 kb
Host	smart-9b037c58-973a-464c-8fc2-ab500d159443
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501489256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3501489256
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke.3402894424
Short name	T562
Test name
Test status
Simulation time	204160066 ps
CPU time	9.68 seconds
Started	Apr 23 04:31:52 PM PDT 24
Finished	Apr 23 04:32:01 PM PDT 24
Peak memory	562708 kb
Host	smart-ea8485ef-6acc-4bb9-a2b3-1b4be876a9bd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402894424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3402894424
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.991757555
Short name	T1465
Test name
Test status
Simulation time	6434745813 ps
CPU time	75.28 seconds
Started	Apr 23 04:31:53 PM PDT 24
Finished	Apr 23 04:33:09 PM PDT 24
Peak memory	562780 kb
Host	smart-920b4899-ebb5-4796-9f43-578d7f0b032b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991757555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.991757555
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1760413414
Short name	T2709
Test name
Test status
Simulation time	4855144674 ps
CPU time	86.8 seconds
Started	Apr 23 04:31:53 PM PDT 24
Finished	Apr 23 04:33:20 PM PDT 24
Peak memory	562792 kb
Host	smart-cf442ef3-6668-4f30-99cc-c4b53471359f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760413414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1760413414
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.428529061
Short name	T2003
Test name
Test status
Simulation time	46535881 ps
CPU time	7.08 seconds
Started	Apr 23 04:31:53 PM PDT 24
Finished	Apr 23 04:32:00 PM PDT 24
Peak memory	562720 kb
Host	smart-2f36eb9f-014e-4299-a295-4fb2609248fd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428529061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays. 428529061
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all.3879995018
Short name	T2477
Test name
Test status
Simulation time	12698625741 ps
CPU time	483.15 seconds
Started	Apr 23 04:32:09 PM PDT 24
Finished	Apr 23 04:40:12 PM PDT 24
Peak memory	563452 kb
Host	smart-0e88700f-f1f7-456f-81e1-163a88a79913
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879995018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3879995018
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3919443292
Short name	T2058
Test name
Test status
Simulation time	14173693879 ps
CPU time	523.09 seconds
Started	Apr 23 04:32:13 PM PDT 24
Finished	Apr 23 04:40:56 PM PDT 24
Peak memory	563988 kb
Host	smart-6e6ca263-e47f-4f0f-8e4d-a430bf0f39df
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919443292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3919443292
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2530329823
Short name	T2688
Test name
Test status
Simulation time	43661854 ps
CPU time	40.26 seconds
Started	Apr 23 04:32:15 PM PDT 24
Finished	Apr 23 04:32:55 PM PDT 24
Peak memory	563888 kb
Host	smart-3dfcf303-0475-4ccc-a2d6-f814e0cac758
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530329823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.2530329823
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.743088577
Short name	T2749
Test name
Test status
Simulation time	9056992109 ps
CPU time	837.66 seconds
Started	Apr 23 04:32:16 PM PDT 24
Finished	Apr 23 04:46:14 PM PDT 24
Peak memory	577432 kb
Host	smart-6dea4a7a-5b32-4d41-ac61-dd417479611b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743088577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_reset_error.743088577
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_access_same_device.3809990515
Short name	T2121
Test name
Test status
Simulation time	1909273970 ps
CPU time	73.27 seconds
Started	Apr 23 04:44:38 PM PDT 24
Finished	Apr 23 04:45:52 PM PDT 24
Peak memory	562748 kb
Host	smart-6119d367-c81a-4e8f-aac6-f4d863d5b339
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809990515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .3809990515
Directory	/workspace/60.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.4082553399
Short name	T2071
Test name
Test status
Simulation time	112240014203 ps
CPU time	1963.96 seconds
Started	Apr 23 04:44:35 PM PDT 24
Finished	Apr 23 05:17:19 PM PDT 24
Peak memory	562820 kb
Host	smart-329ff754-5a0f-4cf9-9b85-5fecdb5d8796
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082553399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.4082553399
Directory	/workspace/60.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1567051870
Short name	T2192
Test name
Test status
Simulation time	86076066 ps
CPU time	13.11 seconds
Started	Apr 23 04:44:46 PM PDT 24
Finished	Apr 23 04:44:59 PM PDT 24
Peak memory	562656 kb
Host	smart-918a3ac6-2cd4-4c5a-a1f5-c08d65aaa6c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567051870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.1567051870
Directory	/workspace/60.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_error_random.2881103377
Short name	T1440
Test name
Test status
Simulation time	491105910 ps
CPU time	43.42 seconds
Started	Apr 23 04:44:46 PM PDT 24
Finished	Apr 23 04:45:30 PM PDT 24
Peak memory	562696 kb
Host	smart-cee6d85d-4db6-49c1-8bb7-4cd268b7a775
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881103377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.2881103377
Directory	/workspace/60.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_random.4015432888
Short name	T1720
Test name
Test status
Simulation time	937335853 ps
CPU time	35.91 seconds
Started	Apr 23 04:44:30 PM PDT 24
Finished	Apr 23 04:45:06 PM PDT 24
Peak memory	562672 kb
Host	smart-148894a3-5f38-4bc7-bcda-e76216764ac2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015432888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.4015432888
Directory	/workspace/60.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_random_large_delays.4103339324
Short name	T2739
Test name
Test status
Simulation time	107636354076 ps
CPU time	1250.9 seconds
Started	Apr 23 04:44:36 PM PDT 24
Finished	Apr 23 05:05:27 PM PDT 24
Peak memory	562792 kb
Host	smart-f499e103-3f19-47d8-ab33-4a2ec810a6ab
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103339324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.4103339324
Directory	/workspace/60.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.3034706474
Short name	T1913
Test name
Test status
Simulation time	14436712585 ps
CPU time	268.68 seconds
Started	Apr 23 04:44:37 PM PDT 24
Finished	Apr 23 04:49:06 PM PDT 24
Peak memory	562816 kb
Host	smart-f7dc5d6b-01ac-4f70-8eab-d9a50be58cc5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034706474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.3034706474
Directory	/workspace/60.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.1345735263
Short name	T1362
Test name
Test status
Simulation time	179567861 ps
CPU time	18.99 seconds
Started	Apr 23 04:44:35 PM PDT 24
Finished	Apr 23 04:44:54 PM PDT 24
Peak memory	562720 kb
Host	smart-34725100-842b-4693-88a3-0b7a95b8651c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345735263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.1345735263
Directory	/workspace/60.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_same_source.896930579
Short name	T1914
Test name
Test status
Simulation time	61889912 ps
CPU time	8.09 seconds
Started	Apr 23 04:44:50 PM PDT 24
Finished	Apr 23 04:44:58 PM PDT 24
Peak memory	562740 kb
Host	smart-02cc9b94-a84b-4737-a458-5736b5085b02
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896930579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.896930579
Directory	/workspace/60.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke.2866263288
Short name	T2185
Test name
Test status
Simulation time	230520928 ps
CPU time	11.51 seconds
Started	Apr 23 04:44:31 PM PDT 24
Finished	Apr 23 04:44:43 PM PDT 24
Peak memory	562684 kb
Host	smart-87f69b87-017e-494b-8a62-0c3f19b5e984
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866263288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.2866263288
Directory	/workspace/60.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.3452547353
Short name	T569
Test name
Test status
Simulation time	8577847878 ps
CPU time	90.21 seconds
Started	Apr 23 04:44:33 PM PDT 24
Finished	Apr 23 04:46:04 PM PDT 24
Peak memory	562764 kb
Host	smart-9bfa73c9-a6f3-4573-b1f5-4b4b25699271
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452547353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.3452547353
Directory	/workspace/60.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.2191320154
Short name	T1681
Test name
Test status
Simulation time	5881764593 ps
CPU time	110.17 seconds
Started	Apr 23 04:44:30 PM PDT 24
Finished	Apr 23 04:46:21 PM PDT 24
Peak memory	562756 kb
Host	smart-299f08c6-acc6-4011-b4be-40344ecfb3ef
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191320154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.2191320154
Directory	/workspace/60.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1153847226
Short name	T2396
Test name
Test status
Simulation time	56866555 ps
CPU time	7.27 seconds
Started	Apr 23 04:44:32 PM PDT 24
Finished	Apr 23 04:44:40 PM PDT 24
Peak memory	562672 kb
Host	smart-66fc4349-7077-4161-b4ab-5e0fd161ecfb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153847226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.1153847226
Directory	/workspace/60.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all.566531534
Short name	T1645
Test name
Test status
Simulation time	1308217187 ps
CPU time	121.66 seconds
Started	Apr 23 04:44:47 PM PDT 24
Finished	Apr 23 04:46:49 PM PDT 24
Peak memory	563844 kb
Host	smart-ec7bdeeb-e13d-4000-ae8c-bca4cc34fe8d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566531534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.566531534
Directory	/workspace/60.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.2161349100
Short name	T1319
Test name
Test status
Simulation time	845580467 ps
CPU time	78.43 seconds
Started	Apr 23 04:44:45 PM PDT 24
Finished	Apr 23 04:46:04 PM PDT 24
Peak memory	562848 kb
Host	smart-3be1e7f2-af13-439f-83e5-bd3fc935ae54
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161349100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.2161349100
Directory	/workspace/60.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3908453610
Short name	T2767
Test name
Test status
Simulation time	101845085 ps
CPU time	68.72 seconds
Started	Apr 23 04:44:46 PM PDT 24
Finished	Apr 23 04:45:55 PM PDT 24
Peak memory	563844 kb
Host	smart-b77d19b2-dc2c-4f44-bf9a-f793c43ab136
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908453610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.3908453610
Directory	/workspace/60.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.1111266910
Short name	T2486
Test name
Test status
Simulation time	361768117 ps
CPU time	18.73 seconds
Started	Apr 23 04:44:48 PM PDT 24
Finished	Apr 23 04:45:07 PM PDT 24
Peak memory	562752 kb
Host	smart-fe1830cf-12f6-4086-98b8-fad3a9370029
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111266910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.1111266910
Directory	/workspace/60.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_access_same_device.3227465848
Short name	T2255
Test name
Test status
Simulation time	2052483574 ps
CPU time	94 seconds
Started	Apr 23 04:44:48 PM PDT 24
Finished	Apr 23 04:46:23 PM PDT 24
Peak memory	562724 kb
Host	smart-d5ddd9e4-330e-48e1-91e8-bb463ad20b44
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227465848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .3227465848
Directory	/workspace/61.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.4282904731
Short name	T2080
Test name
Test status
Simulation time	23534143365 ps
CPU time	402 seconds
Started	Apr 23 04:44:58 PM PDT 24
Finished	Apr 23 04:51:40 PM PDT 24
Peak memory	562796 kb
Host	smart-407afad9-eb01-477c-bc22-3d08955d7de8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282904731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.4282904731
Directory	/workspace/61.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.115749866
Short name	T2789
Test name
Test status
Simulation time	1204611785 ps
CPU time	56.2 seconds
Started	Apr 23 04:44:49 PM PDT 24
Finished	Apr 23 04:45:46 PM PDT 24
Peak memory	562724 kb
Host	smart-802adf33-e757-491c-8059-1fb82ba40bd2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115749866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr .115749866
Directory	/workspace/61.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_error_random.1505220304
Short name	T2485
Test name
Test status
Simulation time	160837742 ps
CPU time	8.57 seconds
Started	Apr 23 04:44:50 PM PDT 24
Finished	Apr 23 04:44:59 PM PDT 24
Peak memory	562660 kb
Host	smart-415aa17d-c18f-4bbe-9b31-8361667686d7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505220304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1505220304
Directory	/workspace/61.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_random.1234051521
Short name	T2201
Test name
Test status
Simulation time	404950924 ps
CPU time	35.77 seconds
Started	Apr 23 04:44:57 PM PDT 24
Finished	Apr 23 04:45:34 PM PDT 24
Peak memory	562728 kb
Host	smart-97997a24-9ab2-4754-b271-a90025753453
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234051521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.1234051521
Directory	/workspace/61.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_random_large_delays.1228841795
Short name	T2042
Test name
Test status
Simulation time	56177798896 ps
CPU time	677.71 seconds
Started	Apr 23 04:44:52 PM PDT 24
Finished	Apr 23 04:56:10 PM PDT 24
Peak memory	562824 kb
Host	smart-9cc8739d-4aed-40cc-b9a8-f933dbb74758
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228841795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.1228841795
Directory	/workspace/61.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.2410305861
Short name	T1354
Test name
Test status
Simulation time	13921037349 ps
CPU time	260.6 seconds
Started	Apr 23 04:44:58 PM PDT 24
Finished	Apr 23 04:49:19 PM PDT 24
Peak memory	562796 kb
Host	smart-f7100e1f-0a3e-4cbf-9e7b-f6b7beab9ee0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410305861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.2410305861
Directory	/workspace/61.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.502684284
Short name	T537
Test name
Test status
Simulation time	156215689 ps
CPU time	17.89 seconds
Started	Apr 23 04:44:47 PM PDT 24
Finished	Apr 23 04:45:05 PM PDT 24
Peak memory	562668 kb
Host	smart-6ff178d0-11b7-41fb-a1ca-2e399bd2d115
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502684284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_dela ys.502684284
Directory	/workspace/61.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_same_source.167865502
Short name	T2140
Test name
Test status
Simulation time	619809787 ps
CPU time	18.07 seconds
Started	Apr 23 04:44:48 PM PDT 24
Finished	Apr 23 04:45:07 PM PDT 24
Peak memory	562720 kb
Host	smart-daab335b-d747-4abc-b2cd-319fcdf1b77f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167865502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.167865502
Directory	/workspace/61.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke.3404667824
Short name	T2311
Test name
Test status
Simulation time	197474584 ps
CPU time	9.3 seconds
Started	Apr 23 04:44:51 PM PDT 24
Finished	Apr 23 04:45:00 PM PDT 24
Peak memory	562728 kb
Host	smart-e1d43780-b62f-4234-8b4f-9427647f0c37
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404667824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3404667824
Directory	/workspace/61.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.997580713
Short name	T2502
Test name
Test status
Simulation time	6453494129 ps
CPU time	73.65 seconds
Started	Apr 23 04:44:47 PM PDT 24
Finished	Apr 23 04:46:01 PM PDT 24
Peak memory	562760 kb
Host	smart-e4ecbcad-5c5a-4ca0-b5c6-76fe2a4dd31b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997580713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.997580713
Directory	/workspace/61.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1928564222
Short name	T1264
Test name
Test status
Simulation time	5285760745 ps
CPU time	94.64 seconds
Started	Apr 23 04:44:46 PM PDT 24
Finished	Apr 23 04:46:22 PM PDT 24
Peak memory	562808 kb
Host	smart-74d36a55-a448-406c-b355-2c7886a6166f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928564222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.1928564222
Directory	/workspace/61.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3162303213
Short name	T561
Test name
Test status
Simulation time	50894191 ps
CPU time	6.83 seconds
Started	Apr 23 04:44:49 PM PDT 24
Finished	Apr 23 04:44:56 PM PDT 24
Peak memory	562708 kb
Host	smart-988694a5-13e6-4816-ae51-ef3cc3d9fb89
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162303213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.3162303213
Directory	/workspace/61.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all.2011886002
Short name	T1783
Test name
Test status
Simulation time	2355150008 ps
CPU time	85.15 seconds
Started	Apr 23 04:44:48 PM PDT 24
Finished	Apr 23 04:46:14 PM PDT 24
Peak memory	562884 kb
Host	smart-4f77a646-459f-41e3-bd8d-ead887b47602
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011886002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.2011886002
Directory	/workspace/61.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.1655617425
Short name	T761
Test name
Test status
Simulation time	15591412814 ps
CPU time	504.97 seconds
Started	Apr 23 04:44:57 PM PDT 24
Finished	Apr 23 04:53:23 PM PDT 24
Peak memory	562932 kb
Host	smart-6b03f1fc-24e8-4419-a42d-6f5c9c7f86f4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655617425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.1655617425
Directory	/workspace/61.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.2628267314
Short name	T1648
Test name
Test status
Simulation time	768034961 ps
CPU time	245.54 seconds
Started	Apr 23 04:44:52 PM PDT 24
Finished	Apr 23 04:48:58 PM PDT 24
Peak memory	572132 kb
Host	smart-ac3b202f-1612-4926-a1d3-4bbae35b86e6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628267314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.2628267314
Directory	/workspace/61.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2189273377
Short name	T2615
Test name
Test status
Simulation time	244023455 ps
CPU time	95.36 seconds
Started	Apr 23 04:44:49 PM PDT 24
Finished	Apr 23 04:46:25 PM PDT 24
Peak memory	563956 kb
Host	smart-8eaeb78f-75d6-4357-b41f-eec3ab3d6db1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189273377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.2189273377
Directory	/workspace/61.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.702130077
Short name	T1437
Test name
Test status
Simulation time	71420344 ps
CPU time	6.77 seconds
Started	Apr 23 04:44:49 PM PDT 24
Finished	Apr 23 04:44:56 PM PDT 24
Peak memory	562724 kb
Host	smart-24597781-293b-4364-bde6-d6cc740e03d6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702130077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.702130077
Directory	/workspace/61.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_access_same_device.455063768
Short name	T1500
Test name
Test status
Simulation time	732755663 ps
CPU time	40.45 seconds
Started	Apr 23 04:44:57 PM PDT 24
Finished	Apr 23 04:45:38 PM PDT 24
Peak memory	562732 kb
Host	smart-8c620ade-b751-433d-a5fc-9565ebb885ba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455063768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device. 455063768
Directory	/workspace/62.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.412054892
Short name	T2340
Test name
Test status
Simulation time	67477437989 ps
CPU time	1203.59 seconds
Started	Apr 23 04:44:59 PM PDT 24
Finished	Apr 23 05:05:03 PM PDT 24
Peak memory	562820 kb
Host	smart-2c425a41-7111-4071-97f4-cf01807f4717
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412054892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d evice_slow_rsp.412054892
Directory	/workspace/62.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.925094413
Short name	T1289
Test name
Test status
Simulation time	113708174 ps
CPU time	15.45 seconds
Started	Apr 23 04:44:56 PM PDT 24
Finished	Apr 23 04:45:12 PM PDT 24
Peak memory	562744 kb
Host	smart-d4fdba5c-1e37-41af-ba20-14460963ce38
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925094413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr .925094413
Directory	/workspace/62.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_error_random.1410437629
Short name	T2032
Test name
Test status
Simulation time	527258464 ps
CPU time	20.16 seconds
Started	Apr 23 04:44:57 PM PDT 24
Finished	Apr 23 04:45:17 PM PDT 24
Peak memory	562696 kb
Host	smart-661b4e38-c224-4a28-a937-4ed12bc63b7b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410437629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1410437629
Directory	/workspace/62.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_random.315930432
Short name	T1703
Test name
Test status
Simulation time	1167737134 ps
CPU time	43.52 seconds
Started	Apr 23 04:44:55 PM PDT 24
Finished	Apr 23 04:45:39 PM PDT 24
Peak memory	562736 kb
Host	smart-d495fdff-7b36-412e-8bd4-6c0a155a96eb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315930432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.315930432
Directory	/workspace/62.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_random_large_delays.3361250975
Short name	T1439
Test name
Test status
Simulation time	92505074281 ps
CPU time	974.11 seconds
Started	Apr 23 04:44:57 PM PDT 24
Finished	Apr 23 05:01:11 PM PDT 24
Peak memory	562848 kb
Host	smart-cae6e77f-c958-4530-99ff-32b41bdeb210
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361250975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.3361250975
Directory	/workspace/62.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.464366130
Short name	T2463
Test name
Test status
Simulation time	27967631673 ps
CPU time	523.17 seconds
Started	Apr 23 04:44:57 PM PDT 24
Finished	Apr 23 04:53:41 PM PDT 24
Peak memory	562788 kb
Host	smart-8e6cc5a9-96c3-4757-a098-c66802a7a98a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464366130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.464366130
Directory	/workspace/62.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2336592864
Short name	T1687
Test name
Test status
Simulation time	602363979 ps
CPU time	52.14 seconds
Started	Apr 23 04:44:55 PM PDT 24
Finished	Apr 23 04:45:48 PM PDT 24
Peak memory	562660 kb
Host	smart-15f5968b-b9b1-4351-adcc-6efcaf4ad036
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336592864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.2336592864
Directory	/workspace/62.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_same_source.2742729732
Short name	T1373
Test name
Test status
Simulation time	1526154599 ps
CPU time	53.51 seconds
Started	Apr 23 04:44:57 PM PDT 24
Finished	Apr 23 04:45:51 PM PDT 24
Peak memory	562740 kb
Host	smart-8a58b6da-7c9a-4324-946a-6af03d74b8f3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742729732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2742729732
Directory	/workspace/62.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke.1937979755
Short name	T1513
Test name
Test status
Simulation time	179246612 ps
CPU time	8.83 seconds
Started	Apr 23 04:44:54 PM PDT 24
Finished	Apr 23 04:45:03 PM PDT 24
Peak memory	562684 kb
Host	smart-ebfac2a5-8042-4f59-89d4-c8d8689c1377
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937979755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.1937979755
Directory	/workspace/62.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.4079998915
Short name	T1233
Test name
Test status
Simulation time	6282495295 ps
CPU time	66.24 seconds
Started	Apr 23 04:44:57 PM PDT 24
Finished	Apr 23 04:46:04 PM PDT 24
Peak memory	562744 kb
Host	smart-c8e6c60b-ac77-4ad6-b881-80e71a579008
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079998915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.4079998915
Directory	/workspace/62.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3258154131
Short name	T1845
Test name
Test status
Simulation time	4878911158 ps
CPU time	86.35 seconds
Started	Apr 23 04:44:59 PM PDT 24
Finished	Apr 23 04:46:25 PM PDT 24
Peak memory	562768 kb
Host	smart-1ad04f8e-e796-4179-9bce-db9b908fe698
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258154131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3258154131
Directory	/workspace/62.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1234122476
Short name	T1445
Test name
Test status
Simulation time	46875939 ps
CPU time	6.44 seconds
Started	Apr 23 04:44:59 PM PDT 24
Finished	Apr 23 04:45:06 PM PDT 24
Peak memory	562700 kb
Host	smart-158ce67b-7f0b-45d5-9646-d6f62cf53697
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234122476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.1234122476
Directory	/workspace/62.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all.1914088239
Short name	T1364
Test name
Test status
Simulation time	8511904435 ps
CPU time	397.54 seconds
Started	Apr 23 04:44:55 PM PDT 24
Finished	Apr 23 04:51:33 PM PDT 24
Peak memory	563960 kb
Host	smart-57e7e756-ce20-44b6-bc2d-70de0a5140b7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914088239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1914088239
Directory	/workspace/62.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.945770826
Short name	T1608
Test name
Test status
Simulation time	13995301172 ps
CPU time	512.64 seconds
Started	Apr 23 04:45:00 PM PDT 24
Finished	Apr 23 04:53:33 PM PDT 24
Peak memory	564000 kb
Host	smart-436fa759-a392-4709-a97c-8e7056c91112
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945770826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.945770826
Directory	/workspace/62.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2780700431
Short name	T2108
Test name
Test status
Simulation time	314511267 ps
CPU time	126.75 seconds
Started	Apr 23 04:45:01 PM PDT 24
Finished	Apr 23 04:47:08 PM PDT 24
Peak memory	563968 kb
Host	smart-0379d3f9-e57d-48fe-9790-4bcf7650c97f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780700431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.2780700431
Directory	/workspace/62.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.32379505
Short name	T1555
Test name
Test status
Simulation time	536907695 ps
CPU time	126.53 seconds
Started	Apr 23 04:45:01 PM PDT 24
Finished	Apr 23 04:47:07 PM PDT 24
Peak memory	572136 kb
Host	smart-dc863b8f-9a91-4d9f-aebf-175d7f21d216
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32379505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_ with_reset_error.32379505
Directory	/workspace/62.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.3963667799
Short name	T574
Test name
Test status
Simulation time	306344465 ps
CPU time	34.31 seconds
Started	Apr 23 04:44:57 PM PDT 24
Finished	Apr 23 04:45:31 PM PDT 24
Peak memory	562800 kb
Host	smart-61cda1d3-a4ba-4cb7-b4e5-802dfbccc3df
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963667799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.3963667799
Directory	/workspace/62.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_access_same_device.4225084669
Short name	T2752
Test name
Test status
Simulation time	408869805 ps
CPU time	35.17 seconds
Started	Apr 23 04:45:10 PM PDT 24
Finished	Apr 23 04:45:46 PM PDT 24
Peak memory	562732 kb
Host	smart-23e9df97-7f4f-4005-a188-65a8f34d5446
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225084669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .4225084669
Directory	/workspace/63.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.408628012
Short name	T2213
Test name
Test status
Simulation time	87884933345 ps
CPU time	1500.37 seconds
Started	Apr 23 04:45:10 PM PDT 24
Finished	Apr 23 05:10:11 PM PDT 24
Peak memory	562828 kb
Host	smart-ed44b935-9567-40de-9251-a80b4fc5189b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408628012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_d evice_slow_rsp.408628012
Directory	/workspace/63.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.3191165433
Short name	T2536
Test name
Test status
Simulation time	268520866 ps
CPU time	33.95 seconds
Started	Apr 23 04:45:09 PM PDT 24
Finished	Apr 23 04:45:43 PM PDT 24
Peak memory	562760 kb
Host	smart-59cb3381-93b6-4193-9003-3d3e727ea2d5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191165433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.3191165433
Directory	/workspace/63.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_error_random.3366171554
Short name	T1815
Test name
Test status
Simulation time	1942770631 ps
CPU time	63.77 seconds
Started	Apr 23 04:45:05 PM PDT 24
Finished	Apr 23 04:46:09 PM PDT 24
Peak memory	562728 kb
Host	smart-faa333e2-1ae8-42c3-97c4-405ff7ab4ec4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366171554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.3366171554
Directory	/workspace/63.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_random.2163870729
Short name	T2245
Test name
Test status
Simulation time	1942145130 ps
CPU time	89.09 seconds
Started	Apr 23 04:45:03 PM PDT 24
Finished	Apr 23 04:46:33 PM PDT 24
Peak memory	562704 kb
Host	smart-3824c6c4-a2da-4777-aefb-32983819871f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163870729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2163870729
Directory	/workspace/63.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1475701649
Short name	T2642
Test name
Test status
Simulation time	28505380537 ps
CPU time	300.48 seconds
Started	Apr 23 04:45:07 PM PDT 24
Finished	Apr 23 04:50:08 PM PDT 24
Peak memory	562828 kb
Host	smart-b324916c-7cde-452a-9b7b-0b4bb45cef9b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475701649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.1475701649
Directory	/workspace/63.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.170736266
Short name	T2454
Test name
Test status
Simulation time	27425851308 ps
CPU time	514.5 seconds
Started	Apr 23 04:45:06 PM PDT 24
Finished	Apr 23 04:53:41 PM PDT 24
Peak memory	562824 kb
Host	smart-ac312346-7d07-4247-ac5b-d41a41a2e92b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170736266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.170736266
Directory	/workspace/63.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.643832925
Short name	T1793
Test name
Test status
Simulation time	33606883 ps
CPU time	6.85 seconds
Started	Apr 23 04:45:07 PM PDT 24
Finished	Apr 23 04:45:15 PM PDT 24
Peak memory	562664 kb
Host	smart-0dfab529-ca47-4c6c-a5d3-81a71e4e2ecd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643832925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela ys.643832925
Directory	/workspace/63.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_same_source.646480405
Short name	T1887
Test name
Test status
Simulation time	197342610 ps
CPU time	18.09 seconds
Started	Apr 23 04:45:10 PM PDT 24
Finished	Apr 23 04:45:28 PM PDT 24
Peak memory	562720 kb
Host	smart-183e924e-8041-4aef-a980-72d86b9f790b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646480405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.646480405
Directory	/workspace/63.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke.314009152
Short name	T2747
Test name
Test status
Simulation time	223177245 ps
CPU time	10.32 seconds
Started	Apr 23 04:45:00 PM PDT 24
Finished	Apr 23 04:45:11 PM PDT 24
Peak memory	562704 kb
Host	smart-711abf18-60aa-4ee9-bdde-a86b078a7c99
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314009152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.314009152
Directory	/workspace/63.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.500783650
Short name	T1420
Test name
Test status
Simulation time	8730449209 ps
CPU time	96.06 seconds
Started	Apr 23 04:45:02 PM PDT 24
Finished	Apr 23 04:46:38 PM PDT 24
Peak memory	562772 kb
Host	smart-d340cece-7138-4709-b18a-4da08a13e2d9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500783650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.500783650
Directory	/workspace/63.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3879121236
Short name	T1521
Test name
Test status
Simulation time	4915664300 ps
CPU time	87.56 seconds
Started	Apr 23 04:45:04 PM PDT 24
Finished	Apr 23 04:46:32 PM PDT 24
Peak memory	562776 kb
Host	smart-02e91c29-4bf2-47b6-a237-1b1cde0eb440
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879121236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.3879121236
Directory	/workspace/63.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2107450817
Short name	T1581
Test name
Test status
Simulation time	41901521 ps
CPU time	5.99 seconds
Started	Apr 23 04:44:59 PM PDT 24
Finished	Apr 23 04:45:05 PM PDT 24
Peak memory	562680 kb
Host	smart-58f5ffbc-122e-4dc7-bc96-e914311149b7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107450817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.2107450817
Directory	/workspace/63.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all.2583098397
Short name	T2018
Test name
Test status
Simulation time	14736248695 ps
CPU time	559.66 seconds
Started	Apr 23 04:45:09 PM PDT 24
Finished	Apr 23 04:54:29 PM PDT 24
Peak memory	563756 kb
Host	smart-676b48ef-2369-4e92-9568-e821fd116bd0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583098397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2583098397
Directory	/workspace/63.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.1830530672
Short name	T1271
Test name
Test status
Simulation time	870496891 ps
CPU time	64.51 seconds
Started	Apr 23 04:45:10 PM PDT 24
Finished	Apr 23 04:46:15 PM PDT 24
Peak memory	562836 kb
Host	smart-702d7dfa-35d6-463a-b20c-0b7e78215b59
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830530672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.1830530672
Directory	/workspace/63.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1523896032
Short name	T777
Test name
Test status
Simulation time	15669199937 ps
CPU time	796.32 seconds
Started	Apr 23 04:45:10 PM PDT 24
Finished	Apr 23 04:58:27 PM PDT 24
Peak memory	572152 kb
Host	smart-ced564d6-9db0-417a-b06d-eb42ac58ea2e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523896032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.1523896032
Directory	/workspace/63.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.2099657785
Short name	T2146
Test name
Test status
Simulation time	597435518 ps
CPU time	29.69 seconds
Started	Apr 23 04:45:09 PM PDT 24
Finished	Apr 23 04:45:39 PM PDT 24
Peak memory	562772 kb
Host	smart-6d55a185-e135-4013-a7c8-148aa2d64136
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099657785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.2099657785
Directory	/workspace/63.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_access_same_device.2242028723
Short name	T2417
Test name
Test status
Simulation time	494893555 ps
CPU time	42.01 seconds
Started	Apr 23 04:45:25 PM PDT 24
Finished	Apr 23 04:46:07 PM PDT 24
Peak memory	562720 kb
Host	smart-3b186d15-517a-4241-a68c-3437e3313696
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242028723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .2242028723
Directory	/workspace/64.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1976260341
Short name	T1956
Test name
Test status
Simulation time	20855919361 ps
CPU time	365.39 seconds
Started	Apr 23 04:45:17 PM PDT 24
Finished	Apr 23 04:51:22 PM PDT 24
Peak memory	562800 kb
Host	smart-1d0c1d23-98de-4aba-9519-9b57c6ba25e0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976260341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.1976260341
Directory	/workspace/64.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.291957726
Short name	T1634
Test name
Test status
Simulation time	1352911079 ps
CPU time	54.37 seconds
Started	Apr 23 04:45:16 PM PDT 24
Finished	Apr 23 04:46:11 PM PDT 24
Peak memory	562720 kb
Host	smart-47c32c07-d771-4692-b2bd-235b174d9d25
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291957726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr .291957726
Directory	/workspace/64.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_error_random.611592358
Short name	T2788
Test name
Test status
Simulation time	581763383 ps
CPU time	24.27 seconds
Started	Apr 23 04:45:15 PM PDT 24
Finished	Apr 23 04:45:39 PM PDT 24
Peak memory	562700 kb
Host	smart-64e7589c-7e78-4b43-8e99-b69ad046e9df
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611592358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.611592358
Directory	/workspace/64.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_random.51316588
Short name	T593
Test name
Test status
Simulation time	425865617 ps
CPU time	38.12 seconds
Started	Apr 23 04:45:13 PM PDT 24
Finished	Apr 23 04:45:51 PM PDT 24
Peak memory	562752 kb
Host	smart-6f1aa041-9051-4190-af7e-aef36a6d326c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51316588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.51316588
Directory	/workspace/64.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_random_large_delays.2953612017
Short name	T451
Test name
Test status
Simulation time	64432977661 ps
CPU time	714.06 seconds
Started	Apr 23 04:45:14 PM PDT 24
Finished	Apr 23 04:57:08 PM PDT 24
Peak memory	562776 kb
Host	smart-e37d0a65-fc65-41d2-8dfd-2368f8f02d89
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953612017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.2953612017
Directory	/workspace/64.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.3194489761
Short name	T1780
Test name
Test status
Simulation time	36174693316 ps
CPU time	663.26 seconds
Started	Apr 23 04:45:13 PM PDT 24
Finished	Apr 23 04:56:16 PM PDT 24
Peak memory	562804 kb
Host	smart-25938ca9-46ca-4447-930b-3413cba34930
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194489761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.3194489761
Directory	/workspace/64.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.2456974678
Short name	T2225
Test name
Test status
Simulation time	497851607 ps
CPU time	49.05 seconds
Started	Apr 23 04:45:13 PM PDT 24
Finished	Apr 23 04:46:02 PM PDT 24
Peak memory	562692 kb
Host	smart-6941730b-36c5-44fd-a613-d8708e238562
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456974678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.2456974678
Directory	/workspace/64.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_same_source.341287203
Short name	T550
Test name
Test status
Simulation time	280485290 ps
CPU time	10.67 seconds
Started	Apr 23 04:45:16 PM PDT 24
Finished	Apr 23 04:45:27 PM PDT 24
Peak memory	562728 kb
Host	smart-8ed1122c-b7bd-4030-984c-558859fbe0fe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341287203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.341287203
Directory	/workspace/64.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke.2536111525
Short name	T1432
Test name
Test status
Simulation time	46220854 ps
CPU time	6.32 seconds
Started	Apr 23 04:45:09 PM PDT 24
Finished	Apr 23 04:45:16 PM PDT 24
Peak memory	562720 kb
Host	smart-2a8c216c-cabf-4b03-8c72-02e109b1ee57
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536111525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.2536111525
Directory	/workspace/64.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.2167116004
Short name	T2496
Test name
Test status
Simulation time	9429333084 ps
CPU time	104.48 seconds
Started	Apr 23 04:45:12 PM PDT 24
Finished	Apr 23 04:46:57 PM PDT 24
Peak memory	562772 kb
Host	smart-5bce61d4-a248-4af8-af92-c1191a93a28f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167116004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.2167116004
Directory	/workspace/64.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2904842131
Short name	T2349
Test name
Test status
Simulation time	5252166138 ps
CPU time	91.53 seconds
Started	Apr 23 04:45:13 PM PDT 24
Finished	Apr 23 04:46:45 PM PDT 24
Peak memory	562796 kb
Host	smart-99f36ddd-59ae-4349-9ccc-58ca35657ec4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904842131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.2904842131
Directory	/workspace/64.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.4146607196
Short name	T2422
Test name
Test status
Simulation time	41813035 ps
CPU time	6.26 seconds
Started	Apr 23 04:45:13 PM PDT 24
Finished	Apr 23 04:45:19 PM PDT 24
Peak memory	562692 kb
Host	smart-bda80d3a-4edd-408c-be44-c715d89aed37
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146607196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.4146607196
Directory	/workspace/64.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all.1846146307
Short name	T1858
Test name
Test status
Simulation time	1853886947 ps
CPU time	157.61 seconds
Started	Apr 23 04:45:24 PM PDT 24
Finished	Apr 23 04:48:02 PM PDT 24
Peak memory	562976 kb
Host	smart-c143b567-c9ac-4916-ad44-6c2a65673702
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846146307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1846146307
Directory	/workspace/64.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1527981313
Short name	T1603
Test name
Test status
Simulation time	1017768936 ps
CPU time	85.02 seconds
Started	Apr 23 04:45:17 PM PDT 24
Finished	Apr 23 04:46:42 PM PDT 24
Peak memory	562856 kb
Host	smart-c2f3d19d-db9b-496d-ac28-9b014c921332
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527981313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1527981313
Directory	/workspace/64.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.2017853115
Short name	T1988
Test name
Test status
Simulation time	448690948 ps
CPU time	226.9 seconds
Started	Apr 23 04:45:25 PM PDT 24
Finished	Apr 23 04:49:12 PM PDT 24
Peak memory	563896 kb
Host	smart-453f0645-61e1-4362-8022-e13035488a96
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017853115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.2017853115
Directory	/workspace/64.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2108131425
Short name	T827
Test name
Test status
Simulation time	8234167704 ps
CPU time	384.76 seconds
Started	Apr 23 04:45:17 PM PDT 24
Finished	Apr 23 04:51:42 PM PDT 24
Peak memory	572124 kb
Host	smart-3acf9eb4-94ad-4112-998d-ada78bc4931e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108131425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.2108131425
Directory	/workspace/64.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.1736261110
Short name	T2479
Test name
Test status
Simulation time	986386352 ps
CPU time	40.33 seconds
Started	Apr 23 04:45:18 PM PDT 24
Finished	Apr 23 04:45:59 PM PDT 24
Peak memory	562776 kb
Host	smart-a8dbdbd3-fc42-4bb8-8b0a-47de053a27f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736261110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.1736261110
Directory	/workspace/64.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_access_same_device.1295941050
Short name	T2763
Test name
Test status
Simulation time	985257000 ps
CPU time	81.89 seconds
Started	Apr 23 04:45:25 PM PDT 24
Finished	Apr 23 04:46:47 PM PDT 24
Peak memory	562804 kb
Host	smart-43704eab-f5d4-489b-8c12-073c09daee5f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295941050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .1295941050
Directory	/workspace/65.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2226174571
Short name	T803
Test name
Test status
Simulation time	141671114774 ps
CPU time	2374.09 seconds
Started	Apr 23 04:45:24 PM PDT 24
Finished	Apr 23 05:24:59 PM PDT 24
Peak memory	562944 kb
Host	smart-77068761-8df8-4a05-8bf5-814b3dde3507
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226174571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.2226174571
Directory	/workspace/65.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2047772580
Short name	T1605
Test name
Test status
Simulation time	134429073 ps
CPU time	8.58 seconds
Started	Apr 23 04:45:24 PM PDT 24
Finished	Apr 23 04:45:33 PM PDT 24
Peak memory	562704 kb
Host	smart-254b68d1-4a04-471a-b001-ffe75ccb9b35
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047772580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.2047772580
Directory	/workspace/65.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_error_random.913730541
Short name	T2138
Test name
Test status
Simulation time	351401800 ps
CPU time	26.5 seconds
Started	Apr 23 04:45:25 PM PDT 24
Finished	Apr 23 04:45:52 PM PDT 24
Peak memory	562712 kb
Host	smart-a797cc49-5e89-45c6-af86-a81107746230
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913730541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.913730541
Directory	/workspace/65.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_random.746890503
Short name	T2456
Test name
Test status
Simulation time	309061009 ps
CPU time	30.45 seconds
Started	Apr 23 04:45:21 PM PDT 24
Finished	Apr 23 04:45:51 PM PDT 24
Peak memory	562692 kb
Host	smart-5dac5ce9-9e72-47b5-8364-50e5d6f77422
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746890503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.746890503
Directory	/workspace/65.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_random_large_delays.4712572
Short name	T2398
Test name
Test status
Simulation time	61301752111 ps
CPU time	658.73 seconds
Started	Apr 23 04:45:21 PM PDT 24
Finished	Apr 23 04:56:20 PM PDT 24
Peak memory	562840 kb
Host	smart-d5fe6f83-6efa-4432-9926-da4f025e5c88
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4712572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.4712572
Directory	/workspace/65.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.4037764601
Short name	T595
Test name
Test status
Simulation time	23310076158 ps
CPU time	399.8 seconds
Started	Apr 23 04:45:22 PM PDT 24
Finished	Apr 23 04:52:02 PM PDT 24
Peak memory	562804 kb
Host	smart-fd4cfce8-fd8b-4457-a642-4ce87e0339ab
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037764601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.4037764601
Directory	/workspace/65.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3798388704
Short name	T555
Test name
Test status
Simulation time	207802330 ps
CPU time	20.27 seconds
Started	Apr 23 04:45:26 PM PDT 24
Finished	Apr 23 04:45:46 PM PDT 24
Peak memory	562712 kb
Host	smart-1fd18e8f-cbe5-4105-b458-4ee2d3059323
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798388704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.3798388704
Directory	/workspace/65.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_same_source.434854878
Short name	T2641
Test name
Test status
Simulation time	1875320205 ps
CPU time	61.52 seconds
Started	Apr 23 04:45:25 PM PDT 24
Finished	Apr 23 04:46:27 PM PDT 24
Peak memory	562728 kb
Host	smart-0317856d-9d90-4f62-bfbc-0d5cf19c76f8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434854878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.434854878
Directory	/workspace/65.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke.2607493064
Short name	T1835
Test name
Test status
Simulation time	196829546 ps
CPU time	8.24 seconds
Started	Apr 23 04:45:16 PM PDT 24
Finished	Apr 23 04:45:24 PM PDT 24
Peak memory	562692 kb
Host	smart-179bcaf6-e92c-4eb5-9ac0-e9ef11c1fe85
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607493064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.2607493064
Directory	/workspace/65.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.93704383
Short name	T2519
Test name
Test status
Simulation time	7593648817 ps
CPU time	81.7 seconds
Started	Apr 23 04:45:19 PM PDT 24
Finished	Apr 23 04:46:41 PM PDT 24
Peak memory	562780 kb
Host	smart-12517c98-a1d7-409d-ae7a-2448eb4436cc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93704383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.93704383
Directory	/workspace/65.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.569610634
Short name	T1237
Test name
Test status
Simulation time	4682888615 ps
CPU time	85.99 seconds
Started	Apr 23 04:45:18 PM PDT 24
Finished	Apr 23 04:46:44 PM PDT 24
Peak memory	562788 kb
Host	smart-ca4dd1aa-4232-4ffa-ad7f-84aef6cf06ca
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569610634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.569610634
Directory	/workspace/65.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.473883234
Short name	T1347
Test name
Test status
Simulation time	50189210 ps
CPU time	6.35 seconds
Started	Apr 23 04:45:26 PM PDT 24
Finished	Apr 23 04:45:32 PM PDT 24
Peak memory	562676 kb
Host	smart-5cbc11a3-0603-4c8b-9435-30a735893cf5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473883234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays .473883234
Directory	/workspace/65.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all.4225283813
Short name	T1430
Test name
Test status
Simulation time	2263064651 ps
CPU time	83.03 seconds
Started	Apr 23 04:45:28 PM PDT 24
Finished	Apr 23 04:46:51 PM PDT 24
Peak memory	562924 kb
Host	smart-cce70968-34a3-415d-90a8-aab13deeadb2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225283813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.4225283813
Directory	/workspace/65.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.538712578
Short name	T2664
Test name
Test status
Simulation time	4417886849 ps
CPU time	155.11 seconds
Started	Apr 23 04:45:26 PM PDT 24
Finished	Apr 23 04:48:02 PM PDT 24
Peak memory	563028 kb
Host	smart-00cc11ce-3c6c-4ee9-b4aa-f5b0439eee66
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538712578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.538712578
Directory	/workspace/65.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2743957166
Short name	T825
Test name
Test status
Simulation time	4286787949 ps
CPU time	366.14 seconds
Started	Apr 23 04:45:25 PM PDT 24
Finished	Apr 23 04:51:32 PM PDT 24
Peak memory	572200 kb
Host	smart-b9b03379-4ad1-4b76-a559-1012a4c13df7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743957166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.2743957166
Directory	/workspace/65.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.3771256932
Short name	T1708
Test name
Test status
Simulation time	85380267 ps
CPU time	23.14 seconds
Started	Apr 23 04:45:31 PM PDT 24
Finished	Apr 23 04:45:55 PM PDT 24
Peak memory	562872 kb
Host	smart-668c5ab6-283f-4c25-be28-33d5c895b4ce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771256932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.3771256932
Directory	/workspace/65.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.2624038895
Short name	T2732
Test name
Test status
Simulation time	886686480 ps
CPU time	36.91 seconds
Started	Apr 23 04:45:24 PM PDT 24
Finished	Apr 23 04:46:01 PM PDT 24
Peak memory	562848 kb
Host	smart-c4787700-7e8f-409f-8f23-9f3b17cb01bc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624038895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.2624038895
Directory	/workspace/65.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_access_same_device.2324081670
Short name	T2122
Test name
Test status
Simulation time	1823460744 ps
CPU time	91.52 seconds
Started	Apr 23 04:45:37 PM PDT 24
Finished	Apr 23 04:47:09 PM PDT 24
Peak memory	562752 kb
Host	smart-b565b108-1953-477d-9bdc-a41bf66025be
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324081670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2324081670
Directory	/workspace/66.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1383254479
Short name	T1444
Test name
Test status
Simulation time	47128509715 ps
CPU time	790.57 seconds
Started	Apr 23 04:45:40 PM PDT 24
Finished	Apr 23 04:58:51 PM PDT 24
Peak memory	562920 kb
Host	smart-7dd334d6-fb9d-4ac4-a32f-b7582a145620
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383254479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.1383254479
Directory	/workspace/66.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.451452805
Short name	T2556
Test name
Test status
Simulation time	240635010 ps
CPU time	11.63 seconds
Started	Apr 23 04:45:40 PM PDT 24
Finished	Apr 23 04:45:52 PM PDT 24
Peak memory	562732 kb
Host	smart-8182c48b-0877-4fda-be0d-61c7a897566d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451452805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr .451452805
Directory	/workspace/66.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_error_random.1863564769
Short name	T2616
Test name
Test status
Simulation time	2277933742 ps
CPU time	82.13 seconds
Started	Apr 23 04:45:38 PM PDT 24
Finished	Apr 23 04:47:00 PM PDT 24
Peak memory	562788 kb
Host	smart-61755346-def3-4b93-b24a-ebf22a2b494b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863564769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.1863564769
Directory	/workspace/66.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_random.1163545869
Short name	T594
Test name
Test status
Simulation time	1240560602 ps
CPU time	48.62 seconds
Started	Apr 23 04:45:30 PM PDT 24
Finished	Apr 23 04:46:19 PM PDT 24
Peak memory	562768 kb
Host	smart-acc8e832-da2a-45dd-85d7-4309b3069708
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163545869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1163545869
Directory	/workspace/66.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_random_large_delays.1109189389
Short name	T2727
Test name
Test status
Simulation time	97833302319 ps
CPU time	1169.02 seconds
Started	Apr 23 04:45:32 PM PDT 24
Finished	Apr 23 05:05:01 PM PDT 24
Peak memory	562788 kb
Host	smart-29e40813-6014-4ecd-a5ea-0a2bdfef3f6f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109189389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.1109189389
Directory	/workspace/66.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1382311740
Short name	T422
Test name
Test status
Simulation time	62142423653 ps
CPU time	1156.13 seconds
Started	Apr 23 04:45:29 PM PDT 24
Finished	Apr 23 05:04:46 PM PDT 24
Peak memory	562812 kb
Host	smart-4c585bd4-7a61-4897-92aa-4dd057db74f4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382311740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.1382311740
Directory	/workspace/66.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.3569054505
Short name	T2411
Test name
Test status
Simulation time	166553525 ps
CPU time	17.63 seconds
Started	Apr 23 04:45:28 PM PDT 24
Finished	Apr 23 04:45:46 PM PDT 24
Peak memory	562740 kb
Host	smart-7beb1091-7aab-48d3-b6b0-2a70490580f0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569054505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.3569054505
Directory	/workspace/66.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_same_source.2304541783
Short name	T1901
Test name
Test status
Simulation time	504333267 ps
CPU time	41.69 seconds
Started	Apr 23 04:45:37 PM PDT 24
Finished	Apr 23 04:46:19 PM PDT 24
Peak memory	562748 kb
Host	smart-e00c046d-6cb9-405b-9ffe-6eb02b3010dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304541783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2304541783
Directory	/workspace/66.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke.4236616964
Short name	T1649
Test name
Test status
Simulation time	224021503 ps
CPU time	10.18 seconds
Started	Apr 23 04:45:28 PM PDT 24
Finished	Apr 23 04:45:39 PM PDT 24
Peak memory	562668 kb
Host	smart-d7784cfe-302d-4c9a-9a0a-45baba9c5af1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236616964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.4236616964
Directory	/workspace/66.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2232345270
Short name	T2472
Test name
Test status
Simulation time	6525954792 ps
CPU time	70.18 seconds
Started	Apr 23 04:45:29 PM PDT 24
Finished	Apr 23 04:46:39 PM PDT 24
Peak memory	562728 kb
Host	smart-601cbad3-b1ca-4020-b36e-b8a01e656b38
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232345270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2232345270
Directory	/workspace/66.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1368114841
Short name	T2147
Test name
Test status
Simulation time	5609128218 ps
CPU time	103.57 seconds
Started	Apr 23 04:45:31 PM PDT 24
Finished	Apr 23 04:47:14 PM PDT 24
Peak memory	562720 kb
Host	smart-a1779a14-45dc-4e02-9c14-ee9c1ffe7db7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368114841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.1368114841
Directory	/workspace/66.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.636739758
Short name	T2518
Test name
Test status
Simulation time	42230532 ps
CPU time	6.53 seconds
Started	Apr 23 04:45:30 PM PDT 24
Finished	Apr 23 04:45:37 PM PDT 24
Peak memory	562688 kb
Host	smart-48013c19-b566-4faa-8164-a597cacbb5cc
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636739758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays .636739758
Directory	/workspace/66.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all.1322841950
Short name	T479
Test name
Test status
Simulation time	3066123526 ps
CPU time	251.31 seconds
Started	Apr 23 04:45:35 PM PDT 24
Finished	Apr 23 04:49:47 PM PDT 24
Peak memory	563972 kb
Host	smart-4cbe6422-db7f-4847-8e2d-8e25b7cbb65d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322841950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1322841950
Directory	/workspace/66.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.1975685701
Short name	T2055
Test name
Test status
Simulation time	2059650028 ps
CPU time	145.03 seconds
Started	Apr 23 04:45:40 PM PDT 24
Finished	Apr 23 04:48:05 PM PDT 24
Peak memory	562860 kb
Host	smart-193903f3-d4a5-418f-9e5a-0034f98bf001
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975685701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.1975685701
Directory	/workspace/66.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2823563954
Short name	T814
Test name
Test status
Simulation time	215898259 ps
CPU time	76.26 seconds
Started	Apr 23 04:45:40 PM PDT 24
Finished	Apr 23 04:46:56 PM PDT 24
Peak memory	563956 kb
Host	smart-5828dc49-dbcb-4ed7-b60b-b8b97810beea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823563954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.2823563954
Directory	/workspace/66.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.2507848878
Short name	T1454
Test name
Test status
Simulation time	746331718 ps
CPU time	213.19 seconds
Started	Apr 23 04:45:39 PM PDT 24
Finished	Apr 23 04:49:12 PM PDT 24
Peak memory	572140 kb
Host	smart-3469fc0b-9e4a-42f2-818f-e793387cf657
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507848878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.2507848878
Directory	/workspace/66.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.831317454
Short name	T1282
Test name
Test status
Simulation time	248453720 ps
CPU time	30.74 seconds
Started	Apr 23 04:45:35 PM PDT 24
Finished	Apr 23 04:46:06 PM PDT 24
Peak memory	562804 kb
Host	smart-a3f3710b-2bac-49e1-a813-be9bc05c244e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831317454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.831317454
Directory	/workspace/66.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_access_same_device.3321223096
Short name	T2421
Test name
Test status
Simulation time	795718752 ps
CPU time	62.07 seconds
Started	Apr 23 04:45:53 PM PDT 24
Finished	Apr 23 04:46:55 PM PDT 24
Peak memory	562744 kb
Host	smart-135c73c5-b11b-40e2-a3e5-aabfa64b3631
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321223096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .3321223096
Directory	/workspace/67.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.967319317
Short name	T2738
Test name
Test status
Simulation time	90726591093 ps
CPU time	1543.84 seconds
Started	Apr 23 04:45:48 PM PDT 24
Finished	Apr 23 05:11:32 PM PDT 24
Peak memory	562992 kb
Host	smart-d6bb8554-d22d-4627-a6b0-b49a3f455dce
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967319317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_d evice_slow_rsp.967319317
Directory	/workspace/67.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3440867996
Short name	T1642
Test name
Test status
Simulation time	344974921 ps
CPU time	34.78 seconds
Started	Apr 23 04:45:48 PM PDT 24
Finished	Apr 23 04:46:23 PM PDT 24
Peak memory	562712 kb
Host	smart-1a8432d7-71b6-4ce0-8cd2-b2d7de6c4f69
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440867996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.3440867996
Directory	/workspace/67.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_error_random.431496266
Short name	T2681
Test name
Test status
Simulation time	1334273164 ps
CPU time	45.61 seconds
Started	Apr 23 04:45:49 PM PDT 24
Finished	Apr 23 04:46:35 PM PDT 24
Peak memory	562688 kb
Host	smart-4539e7a5-49b9-44c8-ace4-58605fbb2a07
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431496266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.431496266
Directory	/workspace/67.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_random.3535913691
Short name	T1492
Test name
Test status
Simulation time	1178317788 ps
CPU time	42.51 seconds
Started	Apr 23 04:45:47 PM PDT 24
Finished	Apr 23 04:46:30 PM PDT 24
Peak memory	562708 kb
Host	smart-cc9be618-69fa-4929-b6ce-f48b0455ffed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535913691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.3535913691
Directory	/workspace/67.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1329634604
Short name	T438
Test name
Test status
Simulation time	82791168118 ps
CPU time	867.39 seconds
Started	Apr 23 04:45:46 PM PDT 24
Finished	Apr 23 05:00:14 PM PDT 24
Peak memory	562784 kb
Host	smart-6a46fdc2-b845-47b6-a80c-79e01191c410
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329634604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.1329634604
Directory	/workspace/67.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.600624401
Short name	T1523
Test name
Test status
Simulation time	10303535480 ps
CPU time	195.7 seconds
Started	Apr 23 04:45:45 PM PDT 24
Finished	Apr 23 04:49:01 PM PDT 24
Peak memory	562776 kb
Host	smart-d123af17-b901-4bf5-896f-26eea6a6551c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600624401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.600624401
Directory	/workspace/67.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.2559943249
Short name	T1609
Test name
Test status
Simulation time	555472536 ps
CPU time	51.38 seconds
Started	Apr 23 04:45:44 PM PDT 24
Finished	Apr 23 04:46:35 PM PDT 24
Peak memory	562736 kb
Host	smart-f6b61752-5bb5-4f8b-b7b3-6d2ab59f4863
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559943249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.2559943249
Directory	/workspace/67.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_same_source.2848436407
Short name	T1764
Test name
Test status
Simulation time	1770614899 ps
CPU time	53.98 seconds
Started	Apr 23 04:45:47 PM PDT 24
Finished	Apr 23 04:46:42 PM PDT 24
Peak memory	562680 kb
Host	smart-35426204-7b64-4758-af90-9dc5c0b5c24a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848436407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.2848436407
Directory	/workspace/67.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke.713837710
Short name	T1231
Test name
Test status
Simulation time	49978822 ps
CPU time	6.81 seconds
Started	Apr 23 04:45:42 PM PDT 24
Finished	Apr 23 04:45:49 PM PDT 24
Peak memory	562656 kb
Host	smart-7abb5416-53fa-4508-b603-00d9670ca402
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713837710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.713837710
Directory	/workspace/67.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.1029145589
Short name	T2726
Test name
Test status
Simulation time	10025682914 ps
CPU time	118.3 seconds
Started	Apr 23 04:45:42 PM PDT 24
Finished	Apr 23 04:47:41 PM PDT 24
Peak memory	562804 kb
Host	smart-d08ad0f6-2896-4e79-a7e5-5521bb34dd4e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029145589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.1029145589
Directory	/workspace/67.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2463618113
Short name	T2656
Test name
Test status
Simulation time	4334996155 ps
CPU time	82.41 seconds
Started	Apr 23 04:45:42 PM PDT 24
Finished	Apr 23 04:47:05 PM PDT 24
Peak memory	562792 kb
Host	smart-b01b2fb9-0f6b-4acf-b550-9e04b73aa74f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463618113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2463618113
Directory	/workspace/67.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3970035092
Short name	T1448
Test name
Test status
Simulation time	49736030 ps
CPU time	5.96 seconds
Started	Apr 23 04:45:47 PM PDT 24
Finished	Apr 23 04:45:54 PM PDT 24
Peak memory	562672 kb
Host	smart-330f2571-2832-429e-91d7-c5b1a9efea6d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970035092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.3970035092
Directory	/workspace/67.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all.2501903319
Short name	T434
Test name
Test status
Simulation time	3403085764 ps
CPU time	300.4 seconds
Started	Apr 23 04:45:48 PM PDT 24
Finished	Apr 23 04:50:49 PM PDT 24
Peak memory	564020 kb
Host	smart-06dc0078-ed6b-40de-a975-3ef29ab4f780
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501903319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.2501903319
Directory	/workspace/67.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3524929287
Short name	T2276
Test name
Test status
Simulation time	11896975998 ps
CPU time	458.86 seconds
Started	Apr 23 04:45:48 PM PDT 24
Finished	Apr 23 04:53:27 PM PDT 24
Peak memory	562904 kb
Host	smart-04db0e57-f3fc-4419-b934-61c40f8b3ecd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524929287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3524929287
Directory	/workspace/67.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2884738794
Short name	T2506
Test name
Test status
Simulation time	8378626365 ps
CPU time	544.04 seconds
Started	Apr 23 04:45:46 PM PDT 24
Finished	Apr 23 04:54:51 PM PDT 24
Peak memory	572140 kb
Host	smart-3ab4035b-1719-4a6f-ac88-7494721376c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884738794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.2884738794
Directory	/workspace/67.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1941266138
Short name	T2532
Test name
Test status
Simulation time	99824623 ps
CPU time	24.67 seconds
Started	Apr 23 04:45:48 PM PDT 24
Finished	Apr 23 04:46:13 PM PDT 24
Peak memory	562880 kb
Host	smart-6e32f80e-9ac2-4048-bae7-c00335f96978
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941266138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.1941266138
Directory	/workspace/67.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3839790098
Short name	T2304
Test name
Test status
Simulation time	250054362 ps
CPU time	13.42 seconds
Started	Apr 23 04:45:47 PM PDT 24
Finished	Apr 23 04:46:00 PM PDT 24
Peak memory	562724 kb
Host	smart-646d2fea-01dd-4b9e-8cea-ecbe9aeaea54
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839790098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3839790098
Directory	/workspace/67.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_access_same_device.1551134673
Short name	T2550
Test name
Test status
Simulation time	495587633 ps
CPU time	40.45 seconds
Started	Apr 23 04:45:56 PM PDT 24
Finished	Apr 23 04:46:37 PM PDT 24
Peak memory	562768 kb
Host	smart-c050599c-d093-463e-963b-a068e2ce937d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551134673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .1551134673
Directory	/workspace/68.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.995496043
Short name	T2659
Test name
Test status
Simulation time	118291376913 ps
CPU time	2058.67 seconds
Started	Apr 23 04:45:55 PM PDT 24
Finished	Apr 23 05:20:15 PM PDT 24
Peak memory	562880 kb
Host	smart-5c41bb2b-8967-4251-972b-a39774600749
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995496043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_d evice_slow_rsp.995496043
Directory	/workspace/68.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3422813669
Short name	T1436
Test name
Test status
Simulation time	956979705 ps
CPU time	41.98 seconds
Started	Apr 23 04:45:54 PM PDT 24
Finished	Apr 23 04:46:37 PM PDT 24
Peak memory	562764 kb
Host	smart-5a84a780-3fe5-47b1-99d4-81adb1717872
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422813669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.3422813669
Directory	/workspace/68.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_error_random.3902915070
Short name	T1252
Test name
Test status
Simulation time	435803164 ps
CPU time	39.28 seconds
Started	Apr 23 04:45:57 PM PDT 24
Finished	Apr 23 04:46:37 PM PDT 24
Peak memory	562676 kb
Host	smart-edfe8cfb-9c9e-4545-bb9a-e2006671a1ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902915070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.3902915070
Directory	/workspace/68.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_random.2196564862
Short name	T1992
Test name
Test status
Simulation time	80500390 ps
CPU time	6.75 seconds
Started	Apr 23 04:45:51 PM PDT 24
Finished	Apr 23 04:45:58 PM PDT 24
Peak memory	562680 kb
Host	smart-80f33d0c-577a-45fa-8dca-dd602c511e97
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196564862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.2196564862
Directory	/workspace/68.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_random_large_delays.3802407709
Short name	T1785
Test name
Test status
Simulation time	75278991189 ps
CPU time	799.34 seconds
Started	Apr 23 04:45:54 PM PDT 24
Finished	Apr 23 04:59:14 PM PDT 24
Peak memory	562824 kb
Host	smart-72ec3112-99df-49d8-a6bd-e45994f54d97
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802407709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.3802407709
Directory	/workspace/68.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.167645507
Short name	T1525
Test name
Test status
Simulation time	13785686778 ps
CPU time	247.88 seconds
Started	Apr 23 04:45:53 PM PDT 24
Finished	Apr 23 04:50:01 PM PDT 24
Peak memory	562848 kb
Host	smart-3aa07120-8fc9-4c32-96a8-4f127ab29a18
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167645507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.167645507
Directory	/workspace/68.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3170848641
Short name	T1595
Test name
Test status
Simulation time	93047281 ps
CPU time	9.77 seconds
Started	Apr 23 04:45:52 PM PDT 24
Finished	Apr 23 04:46:02 PM PDT 24
Peak memory	562708 kb
Host	smart-3fc10d44-1168-450e-bfef-d77aa7bc30bc
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170848641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.3170848641
Directory	/workspace/68.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_same_source.996322589
Short name	T2651
Test name
Test status
Simulation time	848388028 ps
CPU time	28.82 seconds
Started	Apr 23 04:45:57 PM PDT 24
Finished	Apr 23 04:46:27 PM PDT 24
Peak memory	562748 kb
Host	smart-a1f355bb-7ab6-4a28-b3c4-ac5edeeaefa2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996322589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.996322589
Directory	/workspace/68.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke.580191908
Short name	T2285
Test name
Test status
Simulation time	189423924 ps
CPU time	8.54 seconds
Started	Apr 23 04:45:53 PM PDT 24
Finished	Apr 23 04:46:02 PM PDT 24
Peak memory	562696 kb
Host	smart-9422be06-b9b2-449f-bf6d-90b8fe1a6392
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580191908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.580191908
Directory	/workspace/68.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.3098090485
Short name	T1583
Test name
Test status
Simulation time	6977212126 ps
CPU time	79.6 seconds
Started	Apr 23 04:45:52 PM PDT 24
Finished	Apr 23 04:47:12 PM PDT 24
Peak memory	562724 kb
Host	smart-74145a6e-0690-496d-9e60-85f63a302273
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098090485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.3098090485
Directory	/workspace/68.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3766639395
Short name	T2753
Test name
Test status
Simulation time	5060292970 ps
CPU time	86.53 seconds
Started	Apr 23 04:45:52 PM PDT 24
Finished	Apr 23 04:47:19 PM PDT 24
Peak memory	562764 kb
Host	smart-d69e7a0d-e0c4-49ca-97b3-6c3c04f43a58
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766639395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3766639395
Directory	/workspace/68.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2654547119
Short name	T2511
Test name
Test status
Simulation time	43665299 ps
CPU time	6.58 seconds
Started	Apr 23 04:45:52 PM PDT 24
Finished	Apr 23 04:45:59 PM PDT 24
Peak memory	562668 kb
Host	smart-d0f9b6b7-d9ef-4132-a3fc-ac2b17238f28
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654547119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.2654547119
Directory	/workspace/68.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all.49414864
Short name	T1692
Test name
Test status
Simulation time	4353080238 ps
CPU time	397.41 seconds
Started	Apr 23 04:45:58 PM PDT 24
Finished	Apr 23 04:52:36 PM PDT 24
Peak memory	563608 kb
Host	smart-de5a93ef-e9ff-476e-9e5f-aaa351f77520
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49414864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.49414864
Directory	/workspace/68.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.980594173
Short name	T2096
Test name
Test status
Simulation time	10329176326 ps
CPU time	378.82 seconds
Started	Apr 23 04:45:56 PM PDT 24
Finished	Apr 23 04:52:16 PM PDT 24
Peak memory	562968 kb
Host	smart-63e3dd61-1c35-4542-9077-867240d7c82b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980594173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.980594173
Directory	/workspace/68.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.779907442
Short name	T2772
Test name
Test status
Simulation time	95506553 ps
CPU time	25.7 seconds
Started	Apr 23 04:46:01 PM PDT 24
Finished	Apr 23 04:46:27 PM PDT 24
Peak memory	562872 kb
Host	smart-25845cf6-2f0c-4c34-b8cb-fe40b938341f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779907442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_reset_error.779907442
Directory	/workspace/68.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.3451201155
Short name	T1268
Test name
Test status
Simulation time	232760874 ps
CPU time	28.97 seconds
Started	Apr 23 04:45:54 PM PDT 24
Finished	Apr 23 04:46:23 PM PDT 24
Peak memory	562780 kb
Host	smart-da17f3ad-92a4-4d9a-8f2d-08a963c59909
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451201155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.3451201155
Directory	/workspace/68.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_access_same_device.2262810575
Short name	T2610
Test name
Test status
Simulation time	2169328298 ps
CPU time	102.71 seconds
Started	Apr 23 04:45:59 PM PDT 24
Finished	Apr 23 04:47:42 PM PDT 24
Peak memory	562788 kb
Host	smart-9dee6e30-4c9c-4642-9615-bcf8358d8e39
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262810575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .2262810575
Directory	/workspace/69.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3116670260
Short name	T2495
Test name
Test status
Simulation time	4955010763 ps
CPU time	90.03 seconds
Started	Apr 23 04:46:03 PM PDT 24
Finished	Apr 23 04:47:34 PM PDT 24
Peak memory	562784 kb
Host	smart-12bde351-ae13-42ff-9db5-e40f816aab8d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116670260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.3116670260
Directory	/workspace/69.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.736445784
Short name	T1860
Test name
Test status
Simulation time	178289455 ps
CPU time	21.75 seconds
Started	Apr 23 04:46:05 PM PDT 24
Finished	Apr 23 04:46:27 PM PDT 24
Peak memory	562704 kb
Host	smart-9a44a2d6-b97c-4857-ad7f-a853448b8f1a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736445784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr .736445784
Directory	/workspace/69.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_error_random.3157972239
Short name	T2760
Test name
Test status
Simulation time	189066962 ps
CPU time	16.97 seconds
Started	Apr 23 04:46:05 PM PDT 24
Finished	Apr 23 04:46:23 PM PDT 24
Peak memory	562688 kb
Host	smart-2ae4b574-deda-4813-8f7c-b158d0c7b6f4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157972239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.3157972239
Directory	/workspace/69.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_random.2674543762
Short name	T2493
Test name
Test status
Simulation time	1845140721 ps
CPU time	70.88 seconds
Started	Apr 23 04:45:56 PM PDT 24
Finished	Apr 23 04:47:07 PM PDT 24
Peak memory	562736 kb
Host	smart-8e264dfd-d0f8-4e11-95e4-5f960f97c49c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674543762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2674543762
Directory	/workspace/69.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2566339330
Short name	T1985
Test name
Test status
Simulation time	44835765461 ps
CPU time	473.9 seconds
Started	Apr 23 04:46:00 PM PDT 24
Finished	Apr 23 04:53:55 PM PDT 24
Peak memory	562816 kb
Host	smart-313061aa-d4fe-49c1-967d-35310baef640
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566339330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2566339330
Directory	/workspace/69.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.3447103463
Short name	T1646
Test name
Test status
Simulation time	22178862296 ps
CPU time	387.42 seconds
Started	Apr 23 04:46:02 PM PDT 24
Finished	Apr 23 04:52:30 PM PDT 24
Peak memory	562808 kb
Host	smart-52303c3e-626c-45bf-bbf1-7c49b6b66a6d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447103463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.3447103463
Directory	/workspace/69.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3671090493
Short name	T2761
Test name
Test status
Simulation time	178915989 ps
CPU time	18.81 seconds
Started	Apr 23 04:45:58 PM PDT 24
Finished	Apr 23 04:46:17 PM PDT 24
Peak memory	562684 kb
Host	smart-dd585d21-c36b-4113-ad0b-84833fadffc1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671090493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.3671090493
Directory	/workspace/69.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_same_source.2093455969
Short name	T1682
Test name
Test status
Simulation time	2504637900 ps
CPU time	80.06 seconds
Started	Apr 23 04:45:59 PM PDT 24
Finished	Apr 23 04:47:20 PM PDT 24
Peak memory	562760 kb
Host	smart-8cb4f0fc-22f4-4149-b587-25165270dda0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093455969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.2093455969
Directory	/workspace/69.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke.1225817567
Short name	T2043
Test name
Test status
Simulation time	47939504 ps
CPU time	6.62 seconds
Started	Apr 23 04:46:00 PM PDT 24
Finished	Apr 23 04:46:07 PM PDT 24
Peak memory	562716 kb
Host	smart-579e34a6-8cf6-460b-89f6-75eaa33d8ea8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225817567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.1225817567
Directory	/workspace/69.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.134735092
Short name	T1775
Test name
Test status
Simulation time	5492634913 ps
CPU time	61.05 seconds
Started	Apr 23 04:45:58 PM PDT 24
Finished	Apr 23 04:47:00 PM PDT 24
Peak memory	562772 kb
Host	smart-785f308b-b9ac-405f-9959-b4464f7f1dd4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134735092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.134735092
Directory	/workspace/69.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1080407901
Short name	T1336
Test name
Test status
Simulation time	4174518461 ps
CPU time	74.1 seconds
Started	Apr 23 04:45:59 PM PDT 24
Finished	Apr 23 04:47:14 PM PDT 24
Peak memory	562772 kb
Host	smart-8521797d-ccd3-4c5b-ad2b-abb672131126
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080407901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.1080407901
Directory	/workspace/69.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2412861020
Short name	T1256
Test name
Test status
Simulation time	38363309 ps
CPU time	5.81 seconds
Started	Apr 23 04:45:58 PM PDT 24
Finished	Apr 23 04:46:04 PM PDT 24
Peak memory	562660 kb
Host	smart-e5da731d-983b-4b7b-aa2b-5113c5c7511b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412861020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.2412861020
Directory	/workspace/69.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all.1341150246
Short name	T2714
Test name
Test status
Simulation time	3852225191 ps
CPU time	157.53 seconds
Started	Apr 23 04:46:03 PM PDT 24
Finished	Apr 23 04:48:42 PM PDT 24
Peak memory	563764 kb
Host	smart-a37f0d74-503f-4e15-b8c9-69e91315e887
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341150246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.1341150246
Directory	/workspace/69.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.4229181699
Short name	T2244
Test name
Test status
Simulation time	1300551360 ps
CPU time	105.63 seconds
Started	Apr 23 04:46:04 PM PDT 24
Finished	Apr 23 04:47:50 PM PDT 24
Peak memory	562988 kb
Host	smart-a62977ee-fb51-4cde-ab37-7e2cb9a32d03
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229181699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.4229181699
Directory	/workspace/69.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.4216201420
Short name	T476
Test name
Test status
Simulation time	1397471446 ps
CPU time	178.71 seconds
Started	Apr 23 04:46:03 PM PDT 24
Finished	Apr 23 04:49:03 PM PDT 24
Peak memory	563920 kb
Host	smart-03362649-664c-44df-86a1-d1fa5faabe4d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216201420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.4216201420
Directory	/workspace/69.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.4060381720
Short name	T2586
Test name
Test status
Simulation time	699105061 ps
CPU time	189.2 seconds
Started	Apr 23 04:46:06 PM PDT 24
Finished	Apr 23 04:49:16 PM PDT 24
Peak memory	572044 kb
Host	smart-7428aaad-66c6-4f62-af86-43ad8c3d487c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060381720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.4060381720
Directory	/workspace/69.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.3765874466
Short name	T1610
Test name
Test status
Simulation time	98459459 ps
CPU time	14.36 seconds
Started	Apr 23 04:46:06 PM PDT 24
Finished	Apr 23 04:46:21 PM PDT 24
Peak memory	562816 kb
Host	smart-9fcf0a60-4937-45dc-baec-44c707e275ad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765874466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.3765874466
Directory	/workspace/69.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/7.chip_csr_rw.1284503282
Short name	T348
Test name
Test status
Simulation time	3913933022 ps
CPU time	235.59 seconds
Started	Apr 23 04:32:48 PM PDT 24
Finished	Apr 23 04:36:44 PM PDT 24
Peak memory	589048 kb
Host	smart-706e59cf-8593-4810-aae6-564855f50722
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284503282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.1284503282
Directory	/workspace/7.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2306999824
Short name	T407
Test name
Test status
Simulation time	14714581712 ps
CPU time	1611.98 seconds
Started	Apr 23 04:32:13 PM PDT 24
Finished	Apr 23 04:59:06 PM PDT 24
Peak memory	585120 kb
Host	smart-07808508-6b26-49e7-95ce-57278305e7fc
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306999824 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.2306999824
Directory	/workspace/7.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.chip_tl_errors.2339289007
Short name	T1673
Test name
Test status
Simulation time	2851581140 ps
CPU time	234.5 seconds
Started	Apr 23 04:32:17 PM PDT 24
Finished	Apr 23 04:36:12 PM PDT 24
Peak memory	593528 kb
Host	smart-f6d3a553-7d9c-4248-8b41-daeca8f7b89e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339289007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.2339289007
Directory	/workspace/7.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_access_same_device.1800138780
Short name	T1896
Test name
Test status
Simulation time	1984964304 ps
CPU time	96.3 seconds
Started	Apr 23 04:32:32 PM PDT 24
Finished	Apr 23 04:34:08 PM PDT 24
Peak memory	562720 kb
Host	smart-72d70c5f-4f4b-436d-80cc-e8ade8b7d014
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800138780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 1800138780
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.3995458807
Short name	T2365
Test name
Test status
Simulation time	525065830 ps
CPU time	23.34 seconds
Started	Apr 23 04:32:39 PM PDT 24
Finished	Apr 23 04:33:03 PM PDT 24
Peak memory	562720 kb
Host	smart-c6963009-526b-4ad1-9e8b-7f6cedf824fa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995458807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .3995458807
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_error_random.1965659366
Short name	T1398
Test name
Test status
Simulation time	2306866270 ps
CPU time	92.03 seconds
Started	Apr 23 04:32:39 PM PDT 24
Finished	Apr 23 04:34:11 PM PDT 24
Peak memory	562772 kb
Host	smart-1ee43c1d-4016-4cb8-9310-50989bef827c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965659366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1965659366
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_random.666127110
Short name	T585
Test name
Test status
Simulation time	2061017940 ps
CPU time	87.28 seconds
Started	Apr 23 04:32:28 PM PDT 24
Finished	Apr 23 04:33:55 PM PDT 24
Peak memory	562744 kb
Host	smart-ee8eec2e-1841-416d-a931-e1e6f0e0a91e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666127110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.666127110
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2358727205
Short name	T2614
Test name
Test status
Simulation time	35131663698 ps
CPU time	411.07 seconds
Started	Apr 23 04:32:32 PM PDT 24
Finished	Apr 23 04:39:23 PM PDT 24
Peak memory	562820 kb
Host	smart-d7750667-3fd0-4820-86f9-a1b53ba54f2d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358727205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2358727205
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.2751619643
Short name	T2227
Test name
Test status
Simulation time	20634618762 ps
CPU time	366 seconds
Started	Apr 23 04:32:30 PM PDT 24
Finished	Apr 23 04:38:37 PM PDT 24
Peak memory	562852 kb
Host	smart-bdade42a-05b9-4b96-be8c-fb11cf2a2808
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751619643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2751619643
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.184640653
Short name	T2127
Test name
Test status
Simulation time	227796455 ps
CPU time	22.2 seconds
Started	Apr 23 04:32:28 PM PDT 24
Finished	Apr 23 04:32:50 PM PDT 24
Peak memory	562696 kb
Host	smart-53ddd16f-18e6-482c-9c2d-c562521b5450
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184640653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delay s.184640653
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_same_source.4113001131
Short name	T1640
Test name
Test status
Simulation time	308272300 ps
CPU time	23.97 seconds
Started	Apr 23 04:32:35 PM PDT 24
Finished	Apr 23 04:32:59 PM PDT 24
Peak memory	562720 kb
Host	smart-0b4d3f6a-4529-4fad-b9b7-d2c91760e683
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113001131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.4113001131
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke.3530729834
Short name	T1434
Test name
Test status
Simulation time	198380142 ps
CPU time	9.68 seconds
Started	Apr 23 04:32:18 PM PDT 24
Finished	Apr 23 04:32:28 PM PDT 24
Peak memory	562640 kb
Host	smart-52e666d1-8414-4d66-a90e-26b0bf4699e5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530729834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3530729834
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.1218806513
Short name	T2256
Test name
Test status
Simulation time	8294761789 ps
CPU time	94.36 seconds
Started	Apr 23 04:32:23 PM PDT 24
Finished	Apr 23 04:33:57 PM PDT 24
Peak memory	562792 kb
Host	smart-b4d27494-2972-43f0-947c-24dff6152ea5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218806513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1218806513
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.2618514754
Short name	T2260
Test name
Test status
Simulation time	6194224800 ps
CPU time	103.08 seconds
Started	Apr 23 04:32:22 PM PDT 24
Finished	Apr 23 04:34:05 PM PDT 24
Peak memory	562752 kb
Host	smart-f8c6d1f0-b42b-410c-98e4-2ddcc97701cd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618514754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2618514754
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3459157878
Short name	T1830
Test name
Test status
Simulation time	51483254 ps
CPU time	6.71 seconds
Started	Apr 23 04:32:22 PM PDT 24
Finished	Apr 23 04:32:29 PM PDT 24
Peak memory	562712 kb
Host	smart-5a4f4044-4f7b-4c36-8378-66e3a1f3568b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459157878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .3459157878
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all.1023487206
Short name	T2393
Test name
Test status
Simulation time	9640453470 ps
CPU time	361.54 seconds
Started	Apr 23 04:32:38 PM PDT 24
Finished	Apr 23 04:38:40 PM PDT 24
Peak memory	563900 kb
Host	smart-fd5b5d24-4c8d-4914-a910-ce18266aa9bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023487206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1023487206
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2656982268
Short name	T511
Test name
Test status
Simulation time	7409433719 ps
CPU time	288.37 seconds
Started	Apr 23 04:32:46 PM PDT 24
Finished	Apr 23 04:37:35 PM PDT 24
Peak memory	563968 kb
Host	smart-cb726c5d-2585-4c85-8469-d1adb8b8f6d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656982268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2656982268
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3134337255
Short name	T2557
Test name
Test status
Simulation time	3868644163 ps
CPU time	261.83 seconds
Started	Apr 23 04:32:40 PM PDT 24
Finished	Apr 23 04:37:03 PM PDT 24
Peak memory	564008 kb
Host	smart-ffaaf4fd-15dd-4caf-b468-31ab6f159c9b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134337255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.3134337255
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.4068661236
Short name	T1395
Test name
Test status
Simulation time	2852257952 ps
CPU time	356.81 seconds
Started	Apr 23 04:32:45 PM PDT 24
Finished	Apr 23 04:38:42 PM PDT 24
Peak memory	564032 kb
Host	smart-7ec86725-dc31-4658-9e58-ae506c96f47d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068661236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.4068661236
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.799609278
Short name	T1582
Test name
Test status
Simulation time	728014920 ps
CPU time	28.99 seconds
Started	Apr 23 04:32:38 PM PDT 24
Finished	Apr 23 04:33:07 PM PDT 24
Peak memory	562756 kb
Host	smart-4321660b-2a07-478c-b299-2738fb3f1ff8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799609278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.799609278
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_access_same_device.3698286632
Short name	T1352
Test name
Test status
Simulation time	1034261871 ps
CPU time	47.09 seconds
Started	Apr 23 04:46:11 PM PDT 24
Finished	Apr 23 04:46:59 PM PDT 24
Peak memory	562688 kb
Host	smart-a1a1d4a0-3692-465d-86d6-bfa0ad021216
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698286632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .3698286632
Directory	/workspace/70.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.4265947199
Short name	T791
Test name
Test status
Simulation time	55300108137 ps
CPU time	1049.38 seconds
Started	Apr 23 04:46:12 PM PDT 24
Finished	Apr 23 05:03:42 PM PDT 24
Peak memory	562896 kb
Host	smart-379591e1-493f-4bb2-a89e-936a1113ff91
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265947199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.4265947199
Directory	/workspace/70.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2083962617
Short name	T2466
Test name
Test status
Simulation time	980914006 ps
CPU time	41.47 seconds
Started	Apr 23 04:46:08 PM PDT 24
Finished	Apr 23 04:46:51 PM PDT 24
Peak memory	562736 kb
Host	smart-c51c31dd-52c9-4755-8ff3-f4411efc220d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083962617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.2083962617
Directory	/workspace/70.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_error_random.1001277344
Short name	T2352
Test name
Test status
Simulation time	2532109099 ps
CPU time	100.57 seconds
Started	Apr 23 04:46:11 PM PDT 24
Finished	Apr 23 04:47:52 PM PDT 24
Peak memory	562784 kb
Host	smart-2247aaf2-7440-4c35-a947-606b51d9ece8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001277344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.1001277344
Directory	/workspace/70.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_random.3629616227
Short name	T1390
Test name
Test status
Simulation time	1635486308 ps
CPU time	60.63 seconds
Started	Apr 23 04:46:06 PM PDT 24
Finished	Apr 23 04:47:07 PM PDT 24
Peak memory	562728 kb
Host	smart-61435f81-2349-4c34-88f7-20e7cb4ca5f2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629616227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.3629616227
Directory	/workspace/70.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3769303294
Short name	T462
Test name
Test status
Simulation time	98908009249 ps
CPU time	1110.38 seconds
Started	Apr 23 04:46:10 PM PDT 24
Finished	Apr 23 05:04:40 PM PDT 24
Peak memory	562836 kb
Host	smart-cf9e192f-ccf8-41fa-9339-809eded713d6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769303294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3769303294
Directory	/workspace/70.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2803530760
Short name	T2098
Test name
Test status
Simulation time	3511573806 ps
CPU time	67.42 seconds
Started	Apr 23 04:46:11 PM PDT 24
Finished	Apr 23 04:47:19 PM PDT 24
Peak memory	562732 kb
Host	smart-800fd992-76ad-4c59-9494-34f04ba46e3c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803530760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2803530760
Directory	/workspace/70.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.208248033
Short name	T1975
Test name
Test status
Simulation time	34297443 ps
CPU time	6.21 seconds
Started	Apr 23 04:46:08 PM PDT 24
Finished	Apr 23 04:46:15 PM PDT 24
Peak memory	562660 kb
Host	smart-49f20b91-1efc-4e3f-80fe-53a37f645257
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208248033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_dela ys.208248033
Directory	/workspace/70.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_same_source.106361195
Short name	T2300
Test name
Test status
Simulation time	2477942354 ps
CPU time	86.26 seconds
Started	Apr 23 04:46:10 PM PDT 24
Finished	Apr 23 04:47:37 PM PDT 24
Peak memory	562708 kb
Host	smart-45004618-27c2-4787-ae10-cbbc0e71197b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106361195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.106361195
Directory	/workspace/70.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke.3401249247
Short name	T1575
Test name
Test status
Simulation time	50054003 ps
CPU time	6.71 seconds
Started	Apr 23 04:46:04 PM PDT 24
Finished	Apr 23 04:46:11 PM PDT 24
Peak memory	562728 kb
Host	smart-777da67c-eb65-4798-8f60-626cbdfe41ff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401249247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.3401249247
Directory	/workspace/70.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.3053530930
Short name	T2334
Test name
Test status
Simulation time	9498992952 ps
CPU time	105.6 seconds
Started	Apr 23 04:46:06 PM PDT 24
Finished	Apr 23 04:47:52 PM PDT 24
Peak memory	562768 kb
Host	smart-c44dd20a-3bde-42dc-8158-a49a1e0f3d63
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053530930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.3053530930
Directory	/workspace/70.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3961887117
Short name	T1242
Test name
Test status
Simulation time	5611350265 ps
CPU time	105.4 seconds
Started	Apr 23 04:46:06 PM PDT 24
Finished	Apr 23 04:47:52 PM PDT 24
Peak memory	562804 kb
Host	smart-5ad58c09-1ef2-4b4c-8724-169b05362d7a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961887117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.3961887117
Directory	/workspace/70.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1187893764
Short name	T1230
Test name
Test status
Simulation time	45212250 ps
CPU time	6.26 seconds
Started	Apr 23 04:46:07 PM PDT 24
Finished	Apr 23 04:46:13 PM PDT 24
Peak memory	562708 kb
Host	smart-ae03b642-c394-4048-81d3-293db40b5565
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187893764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.1187893764
Directory	/workspace/70.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all.2569019472
Short name	T1232
Test name
Test status
Simulation time	199333654 ps
CPU time	18.29 seconds
Started	Apr 23 04:46:15 PM PDT 24
Finished	Apr 23 04:46:34 PM PDT 24
Peak memory	562764 kb
Host	smart-433cfbc5-e608-4719-b814-6eea400a9ddd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569019472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2569019472
Directory	/workspace/70.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.1856148147
Short name	T1340
Test name
Test status
Simulation time	5049292167 ps
CPU time	189.45 seconds
Started	Apr 23 04:46:13 PM PDT 24
Finished	Apr 23 04:49:23 PM PDT 24
Peak memory	562948 kb
Host	smart-26c0c87b-a696-4bba-a423-5b603bcb85a1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856148147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.1856148147
Directory	/workspace/70.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3264447773
Short name	T1921
Test name
Test status
Simulation time	38747937 ps
CPU time	27.35 seconds
Started	Apr 23 04:46:14 PM PDT 24
Finished	Apr 23 04:46:42 PM PDT 24
Peak memory	563288 kb
Host	smart-f0be04ef-1723-448c-aa18-fa032589dbc0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264447773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.3264447773
Directory	/workspace/70.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3280198623
Short name	T758
Test name
Test status
Simulation time	9799456397 ps
CPU time	579.64 seconds
Started	Apr 23 04:46:14 PM PDT 24
Finished	Apr 23 04:55:55 PM PDT 24
Peak memory	572200 kb
Host	smart-b7bf1c73-2b3f-4dfe-848a-749c025c0d45
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280198623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.3280198623
Directory	/workspace/70.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2589132322
Short name	T2683
Test name
Test status
Simulation time	959538188 ps
CPU time	41.32 seconds
Started	Apr 23 04:46:10 PM PDT 24
Finished	Apr 23 04:46:52 PM PDT 24
Peak memory	562796 kb
Host	smart-13d407fc-491d-4338-84b3-f2fbf3b70d27
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589132322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2589132322
Directory	/workspace/70.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_access_same_device.2815953110
Short name	T448
Test name
Test status
Simulation time	2280285172 ps
CPU time	101.46 seconds
Started	Apr 23 04:46:19 PM PDT 24
Finished	Apr 23 04:48:01 PM PDT 24
Peak memory	562756 kb
Host	smart-14786a0c-d67d-478e-b145-8e5ca9d9931e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815953110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .2815953110
Directory	/workspace/71.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.4239875292
Short name	T2449
Test name
Test status
Simulation time	60521837575 ps
CPU time	1039.52 seconds
Started	Apr 23 04:46:23 PM PDT 24
Finished	Apr 23 05:03:43 PM PDT 24
Peak memory	562924 kb
Host	smart-858250d9-9d77-4cbf-88db-88f1268a5a67
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239875292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.4239875292
Directory	/workspace/71.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3261889126
Short name	T2198
Test name
Test status
Simulation time	100526637 ps
CPU time	12.86 seconds
Started	Apr 23 04:46:24 PM PDT 24
Finished	Apr 23 04:46:37 PM PDT 24
Peak memory	562648 kb
Host	smart-de5551bc-5284-4dc2-aebf-096e2475a900
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261889126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.3261889126
Directory	/workspace/71.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_error_random.1101211649
Short name	T1408
Test name
Test status
Simulation time	899660914 ps
CPU time	31.1 seconds
Started	Apr 23 04:46:26 PM PDT 24
Finished	Apr 23 04:46:57 PM PDT 24
Peak memory	562728 kb
Host	smart-06ad8e41-4ba3-4e3f-b41d-12b4d384dc5b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101211649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.1101211649
Directory	/workspace/71.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_random.3621253377
Short name	T2627
Test name
Test status
Simulation time	873144847 ps
CPU time	36.6 seconds
Started	Apr 23 04:46:16 PM PDT 24
Finished	Apr 23 04:46:53 PM PDT 24
Peak memory	562756 kb
Host	smart-38c6d7f7-fe63-42ba-9f7a-2644ccd95bf2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621253377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.3621253377
Directory	/workspace/71.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_random_large_delays.992919342
Short name	T2084
Test name
Test status
Simulation time	63737662623 ps
CPU time	672.94 seconds
Started	Apr 23 04:46:21 PM PDT 24
Finished	Apr 23 04:57:34 PM PDT 24
Peak memory	562804 kb
Host	smart-1e870acc-eac9-44e1-82e2-b2bd7d0358b8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992919342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.992919342
Directory	/workspace/71.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.4113102732
Short name	T2722
Test name
Test status
Simulation time	11924449600 ps
CPU time	224.96 seconds
Started	Apr 23 04:46:24 PM PDT 24
Finished	Apr 23 04:50:10 PM PDT 24
Peak memory	562812 kb
Host	smart-8d28d3c9-8dba-44ce-a772-2f86ad23c25b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113102732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.4113102732
Directory	/workspace/71.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2903480810
Short name	T1363
Test name
Test status
Simulation time	626354826 ps
CPU time	50.33 seconds
Started	Apr 23 04:46:17 PM PDT 24
Finished	Apr 23 04:47:08 PM PDT 24
Peak memory	562708 kb
Host	smart-bb80804b-6177-49bb-9f17-9b9d47a483e5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903480810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.2903480810
Directory	/workspace/71.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_same_source.2829257663
Short name	T1306
Test name
Test status
Simulation time	1710905062 ps
CPU time	50.13 seconds
Started	Apr 23 04:46:19 PM PDT 24
Finished	Apr 23 04:47:09 PM PDT 24
Peak memory	562732 kb
Host	smart-6d8184c7-f3df-46fe-b426-05c303522abe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829257663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.2829257663
Directory	/workspace/71.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke.555849003
Short name	T1717
Test name
Test status
Simulation time	269715550 ps
CPU time	11.41 seconds
Started	Apr 23 04:46:18 PM PDT 24
Finished	Apr 23 04:46:30 PM PDT 24
Peak memory	562680 kb
Host	smart-34d50940-766b-4692-a065-11617eb9b47c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555849003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.555849003
Directory	/workspace/71.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.3632519587
Short name	T1968
Test name
Test status
Simulation time	7684114376 ps
CPU time	89.73 seconds
Started	Apr 23 04:46:16 PM PDT 24
Finished	Apr 23 04:47:46 PM PDT 24
Peak memory	562796 kb
Host	smart-98be9a14-c874-4f54-9bdc-4b8164f5f44b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632519587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.3632519587
Directory	/workspace/71.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.3568599282
Short name	T2390
Test name
Test status
Simulation time	6178663212 ps
CPU time	109.8 seconds
Started	Apr 23 04:46:17 PM PDT 24
Finished	Apr 23 04:48:07 PM PDT 24
Peak memory	562796 kb
Host	smart-d0905dc6-bbc3-4626-8fa2-fea505954386
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568599282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.3568599282
Directory	/workspace/71.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2888586087
Short name	T2149
Test name
Test status
Simulation time	48064009 ps
CPU time	6.12 seconds
Started	Apr 23 04:46:20 PM PDT 24
Finished	Apr 23 04:46:26 PM PDT 24
Peak memory	562656 kb
Host	smart-5cfa7dc1-0286-45d2-8086-10addd5d81c6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888586087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.2888586087
Directory	/workspace/71.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all.1120032521
Short name	T2416
Test name
Test status
Simulation time	6988059711 ps
CPU time	254.12 seconds
Started	Apr 23 04:46:23 PM PDT 24
Finished	Apr 23 04:50:38 PM PDT 24
Peak memory	563376 kb
Host	smart-984b1ed2-625a-45a2-a74c-b312f634744a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120032521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.1120032521
Directory	/workspace/71.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.389313861
Short name	T432
Test name
Test status
Simulation time	6869921511 ps
CPU time	555.26 seconds
Started	Apr 23 04:46:26 PM PDT 24
Finished	Apr 23 04:55:42 PM PDT 24
Peak memory	572236 kb
Host	smart-79549d01-bdb6-4b97-9170-6012e4840562
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389313861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_ with_rand_reset.389313861
Directory	/workspace/71.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1890220098
Short name	T2175
Test name
Test status
Simulation time	1387174718 ps
CPU time	64.52 seconds
Started	Apr 23 04:46:22 PM PDT 24
Finished	Apr 23 04:47:27 PM PDT 24
Peak memory	562812 kb
Host	smart-2cafb440-1ce5-44ae-9b76-fc361dba700f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890220098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1890220098
Directory	/workspace/71.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_access_same_device.126232730
Short name	T1580
Test name
Test status
Simulation time	2593975753 ps
CPU time	105.58 seconds
Started	Apr 23 04:46:36 PM PDT 24
Finished	Apr 23 04:48:22 PM PDT 24
Peak memory	562728 kb
Host	smart-2142d5f8-2a0f-4fb3-985a-aac3f1919da3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126232730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device. 126232730
Directory	/workspace/72.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1790488837
Short name	T778
Test name
Test status
Simulation time	70806868377 ps
CPU time	1235.49 seconds
Started	Apr 23 04:46:36 PM PDT 24
Finished	Apr 23 05:07:12 PM PDT 24
Peak memory	562916 kb
Host	smart-8d128aa7-970d-4b28-aa8b-a9d6ede024c5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790488837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.1790488837
Directory	/workspace/72.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3062742058
Short name	T2377
Test name
Test status
Simulation time	1037037778 ps
CPU time	45.75 seconds
Started	Apr 23 04:46:36 PM PDT 24
Finished	Apr 23 04:47:22 PM PDT 24
Peak memory	562684 kb
Host	smart-2f4e995a-5f7b-4808-85f3-65604dba7fc4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062742058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.3062742058
Directory	/workspace/72.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_error_random.693715528
Short name	T1220
Test name
Test status
Simulation time	140795330 ps
CPU time	8.26 seconds
Started	Apr 23 04:46:35 PM PDT 24
Finished	Apr 23 04:46:44 PM PDT 24
Peak memory	562728 kb
Host	smart-0f8c5c6b-e015-4404-a2c2-d9a3d826071c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693715528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.693715528
Directory	/workspace/72.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_random.3139408328
Short name	T2757
Test name
Test status
Simulation time	533489588 ps
CPU time	47.44 seconds
Started	Apr 23 04:46:29 PM PDT 24
Finished	Apr 23 04:47:17 PM PDT 24
Peak memory	562708 kb
Host	smart-34ff2987-d78d-46f0-a779-41598380ee3b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139408328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.3139408328
Directory	/workspace/72.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_random_large_delays.1832876622
Short name	T1702
Test name
Test status
Simulation time	59346762273 ps
CPU time	715.11 seconds
Started	Apr 23 04:46:34 PM PDT 24
Finished	Apr 23 04:58:29 PM PDT 24
Peak memory	562764 kb
Host	smart-a94882e2-4b39-4624-97a0-b2d6b790dc1d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832876622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.1832876622
Directory	/workspace/72.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.624890258
Short name	T1868
Test name
Test status
Simulation time	22222319101 ps
CPU time	382.76 seconds
Started	Apr 23 04:46:34 PM PDT 24
Finished	Apr 23 04:52:58 PM PDT 24
Peak memory	562792 kb
Host	smart-7631dadb-c0c8-4e5e-bdc3-bf268a985026
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624890258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.624890258
Directory	/workspace/72.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3523084368
Short name	T2597
Test name
Test status
Simulation time	350270780 ps
CPU time	34.04 seconds
Started	Apr 23 04:46:30 PM PDT 24
Finished	Apr 23 04:47:04 PM PDT 24
Peak memory	562700 kb
Host	smart-f593ef98-e070-4e7a-a6a7-0bcad88e6a9b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523084368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.3523084368
Directory	/workspace/72.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_same_source.2617793787
Short name	T1428
Test name
Test status
Simulation time	933106029 ps
CPU time	32.02 seconds
Started	Apr 23 04:46:37 PM PDT 24
Finished	Apr 23 04:47:09 PM PDT 24
Peak memory	562708 kb
Host	smart-83b788e3-89ab-4145-8f48-43a53e6ecaba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617793787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.2617793787
Directory	/workspace/72.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke.3662629499
Short name	T1528
Test name
Test status
Simulation time	175455988 ps
CPU time	8.25 seconds
Started	Apr 23 04:46:26 PM PDT 24
Finished	Apr 23 04:46:35 PM PDT 24
Peak memory	562696 kb
Host	smart-2e522711-c747-447f-bacd-7d18e247c6bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662629499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.3662629499
Directory	/workspace/72.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.3011681606
Short name	T1304
Test name
Test status
Simulation time	8988348546 ps
CPU time	106.03 seconds
Started	Apr 23 04:46:30 PM PDT 24
Finished	Apr 23 04:48:16 PM PDT 24
Peak memory	562784 kb
Host	smart-68a8ec28-17db-441b-abb8-acf59951ad7a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011681606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.3011681606
Directory	/workspace/72.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1388270835
Short name	T1509
Test name
Test status
Simulation time	4823489665 ps
CPU time	88.83 seconds
Started	Apr 23 04:46:31 PM PDT 24
Finished	Apr 23 04:48:00 PM PDT 24
Peak memory	562756 kb
Host	smart-0acdb738-38bc-4f05-9701-59d40259f9e1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388270835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.1388270835
Directory	/workspace/72.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.463717842
Short name	T1760
Test name
Test status
Simulation time	40494453 ps
CPU time	6.01 seconds
Started	Apr 23 04:46:33 PM PDT 24
Finished	Apr 23 04:46:39 PM PDT 24
Peak memory	562688 kb
Host	smart-86b43fc7-97d4-4103-bda9-1ad0fd73575b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463717842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays .463717842
Directory	/workspace/72.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all.3954053321
Short name	T762
Test name
Test status
Simulation time	4370340685 ps
CPU time	155.7 seconds
Started	Apr 23 04:46:38 PM PDT 24
Finished	Apr 23 04:49:14 PM PDT 24
Peak memory	563116 kb
Host	smart-fa357703-4cae-460f-955d-f400164ba3bd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954053321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3954053321
Directory	/workspace/72.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1222131776
Short name	T2380
Test name
Test status
Simulation time	133084319 ps
CPU time	42.54 seconds
Started	Apr 23 04:46:38 PM PDT 24
Finished	Apr 23 04:47:21 PM PDT 24
Peak memory	563864 kb
Host	smart-576e3cdd-df76-4c85-9b1e-a5afbe97cb53
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222131776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.1222131776
Directory	/workspace/72.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1512888707
Short name	T2678
Test name
Test status
Simulation time	341324769 ps
CPU time	97.01 seconds
Started	Apr 23 04:46:39 PM PDT 24
Finished	Apr 23 04:48:17 PM PDT 24
Peak memory	572044 kb
Host	smart-ba447cea-c351-452c-8a33-7c610368994c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512888707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.1512888707
Directory	/workspace/72.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.2743058024
Short name	T1917
Test name
Test status
Simulation time	1296876705 ps
CPU time	59.93 seconds
Started	Apr 23 04:46:37 PM PDT 24
Finished	Apr 23 04:47:38 PM PDT 24
Peak memory	562788 kb
Host	smart-050d1526-434e-4dd6-b369-868b53f9820e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743058024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.2743058024
Directory	/workspace/72.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_access_same_device.1083074654
Short name	T2505
Test name
Test status
Simulation time	538921223 ps
CPU time	28.63 seconds
Started	Apr 23 04:46:47 PM PDT 24
Finished	Apr 23 04:47:16 PM PDT 24
Peak memory	562736 kb
Host	smart-d4308ec4-c244-4277-8433-e1dfeae90da1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083074654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .1083074654
Directory	/workspace/73.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.60800395
Short name	T1392
Test name
Test status
Simulation time	61621188563 ps
CPU time	1100.52 seconds
Started	Apr 23 04:46:44 PM PDT 24
Finished	Apr 23 05:05:05 PM PDT 24
Peak memory	562884 kb
Host	smart-72c3cf24-15d1-43c8-96a9-b517b13e2016
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60800395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_de vice_slow_rsp.60800395
Directory	/workspace/73.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2596970936
Short name	T1358
Test name
Test status
Simulation time	65590523 ps
CPU time	6.51 seconds
Started	Apr 23 04:46:51 PM PDT 24
Finished	Apr 23 04:46:58 PM PDT 24
Peak memory	562688 kb
Host	smart-a46389d3-0eeb-415f-81fd-ed02deae4197
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596970936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.2596970936
Directory	/workspace/73.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_error_random.241470420
Short name	T1412
Test name
Test status
Simulation time	169414264 ps
CPU time	8.67 seconds
Started	Apr 23 04:46:46 PM PDT 24
Finished	Apr 23 04:46:55 PM PDT 24
Peak memory	562704 kb
Host	smart-2aa84a92-20f0-4294-96c1-729bf74adec7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241470420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.241470420
Directory	/workspace/73.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_random.3910709756
Short name	T2735
Test name
Test status
Simulation time	631991308 ps
CPU time	22.78 seconds
Started	Apr 23 04:46:41 PM PDT 24
Finished	Apr 23 04:47:05 PM PDT 24
Peak memory	562728 kb
Host	smart-a70314e7-143f-4bb7-b1e6-ff2a1a6330b4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910709756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.3910709756
Directory	/workspace/73.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_random_large_delays.752308738
Short name	T2751
Test name
Test status
Simulation time	27462296930 ps
CPU time	325.27 seconds
Started	Apr 23 04:46:43 PM PDT 24
Finished	Apr 23 04:52:08 PM PDT 24
Peak memory	562824 kb
Host	smart-cca63de8-1813-4474-a232-d7b1ed66f636
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752308738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.752308738
Directory	/workspace/73.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.359317129
Short name	T1405
Test name
Test status
Simulation time	14635510129 ps
CPU time	267.58 seconds
Started	Apr 23 04:46:41 PM PDT 24
Finished	Apr 23 04:51:09 PM PDT 24
Peak memory	562800 kb
Host	smart-e0521f6c-29bb-4ef3-ac3a-34bfd955fc2c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359317129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.359317129
Directory	/workspace/73.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.124011642
Short name	T2208
Test name
Test status
Simulation time	535659953 ps
CPU time	51.96 seconds
Started	Apr 23 04:46:41 PM PDT 24
Finished	Apr 23 04:47:34 PM PDT 24
Peak memory	562716 kb
Host	smart-d880d815-02df-4ffd-afb3-2e194ed13d0c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124011642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_dela ys.124011642
Directory	/workspace/73.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_same_source.2051254180
Short name	T1526
Test name
Test status
Simulation time	1959889885 ps
CPU time	61.51 seconds
Started	Apr 23 04:46:44 PM PDT 24
Finished	Apr 23 04:47:46 PM PDT 24
Peak memory	562668 kb
Host	smart-fcd9d735-6673-41be-ab76-a7b0174f4a56
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051254180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2051254180
Directory	/workspace/73.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke.629719687
Short name	T1922
Test name
Test status
Simulation time	220583984 ps
CPU time	9.71 seconds
Started	Apr 23 04:46:41 PM PDT 24
Finished	Apr 23 04:46:52 PM PDT 24
Peak memory	562700 kb
Host	smart-4a09dc09-b8ed-4d65-bc8e-a7235ce099ba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629719687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.629719687
Directory	/workspace/73.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.3371777644
Short name	T1594
Test name
Test status
Simulation time	8084682166 ps
CPU time	99 seconds
Started	Apr 23 04:46:46 PM PDT 24
Finished	Apr 23 04:48:25 PM PDT 24
Peak memory	562776 kb
Host	smart-e825d37a-7416-4e75-b8f0-6d80f61c9887
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371777644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.3371777644
Directory	/workspace/73.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1764277591
Short name	T2333
Test name
Test status
Simulation time	5963508118 ps
CPU time	108.14 seconds
Started	Apr 23 04:46:44 PM PDT 24
Finished	Apr 23 04:48:32 PM PDT 24
Peak memory	562816 kb
Host	smart-d969799b-5a50-4930-81f0-f05864c0e675
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764277591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1764277591
Directory	/workspace/73.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.338213088
Short name	T1339
Test name
Test status
Simulation time	49190735 ps
CPU time	6.41 seconds
Started	Apr 23 04:46:40 PM PDT 24
Finished	Apr 23 04:46:47 PM PDT 24
Peak memory	562716 kb
Host	smart-a73d09e8-08ea-4b7f-9fb7-6e7a50b025b8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338213088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays .338213088
Directory	/workspace/73.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all.2055975970
Short name	T2750
Test name
Test status
Simulation time	3395084676 ps
CPU time	290.26 seconds
Started	Apr 23 04:46:48 PM PDT 24
Finished	Apr 23 04:51:38 PM PDT 24
Peak memory	564032 kb
Host	smart-f66fb21e-42bf-4ce6-b2a6-e1656b96a863
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055975970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.2055975970
Directory	/workspace/73.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2797803936
Short name	T1647
Test name
Test status
Simulation time	9851275695 ps
CPU time	376.12 seconds
Started	Apr 23 04:46:51 PM PDT 24
Finished	Apr 23 04:53:07 PM PDT 24
Peak memory	563544 kb
Host	smart-e2e93458-6d81-4a52-a5cc-222b074971dd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797803936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2797803936
Directory	/workspace/73.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3716406916
Short name	T2647
Test name
Test status
Simulation time	4983821980 ps
CPU time	539.91 seconds
Started	Apr 23 04:46:49 PM PDT 24
Finished	Apr 23 04:55:50 PM PDT 24
Peak memory	572168 kb
Host	smart-d28b9f79-699e-4aeb-899f-313d529ae98c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716406916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.3716406916
Directory	/workspace/73.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3443607636
Short name	T1598
Test name
Test status
Simulation time	2916012271 ps
CPU time	108.16 seconds
Started	Apr 23 04:46:49 PM PDT 24
Finished	Apr 23 04:48:37 PM PDT 24
Peak memory	562932 kb
Host	smart-1fe2d282-a5ef-49cd-bd1d-3351c124e358
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443607636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.3443607636
Directory	/workspace/73.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.2332476842
Short name	T2189
Test name
Test status
Simulation time	225088797 ps
CPU time	31.42 seconds
Started	Apr 23 04:46:47 PM PDT 24
Finished	Apr 23 04:47:18 PM PDT 24
Peak memory	562792 kb
Host	smart-00b52de6-1df7-472e-ab78-b6504df23a7f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332476842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.2332476842
Directory	/workspace/73.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_access_same_device.3636367937
Short name	T1904
Test name
Test status
Simulation time	16440793 ps
CPU time	6.79 seconds
Started	Apr 23 04:46:55 PM PDT 24
Finished	Apr 23 04:47:02 PM PDT 24
Peak memory	562736 kb
Host	smart-bc6e0651-af0b-4925-93c5-2574fbc03c02
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636367937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .3636367937
Directory	/workspace/74.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1324642253
Short name	T1507
Test name
Test status
Simulation time	14360053028 ps
CPU time	253.27 seconds
Started	Apr 23 04:46:54 PM PDT 24
Finished	Apr 23 04:51:07 PM PDT 24
Peak memory	562788 kb
Host	smart-d52e0d2f-9087-47c9-b967-235e47a66370
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324642253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.1324642253
Directory	/workspace/74.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3652905082
Short name	T1280
Test name
Test status
Simulation time	799175720 ps
CPU time	35.68 seconds
Started	Apr 23 04:46:57 PM PDT 24
Finished	Apr 23 04:47:33 PM PDT 24
Peak memory	562728 kb
Host	smart-a25799b6-4024-47b4-8804-9088115f2ca4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652905082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.3652905082
Directory	/workspace/74.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_error_random.264042034
Short name	T1949
Test name
Test status
Simulation time	88291037 ps
CPU time	12.07 seconds
Started	Apr 23 04:46:57 PM PDT 24
Finished	Apr 23 04:47:10 PM PDT 24
Peak memory	562700 kb
Host	smart-89d5bd30-0293-49a2-8473-fa9e6a9648b0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264042034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.264042034
Directory	/workspace/74.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_random.4056618903
Short name	T1353
Test name
Test status
Simulation time	752273983 ps
CPU time	26.01 seconds
Started	Apr 23 04:46:53 PM PDT 24
Finished	Apr 23 04:47:19 PM PDT 24
Peak memory	562780 kb
Host	smart-00f55dfb-e98f-4c7a-8e75-80c8d6915fab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056618903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.4056618903
Directory	/workspace/74.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1733458229
Short name	T2262
Test name
Test status
Simulation time	34227972808 ps
CPU time	409.06 seconds
Started	Apr 23 04:46:53 PM PDT 24
Finished	Apr 23 04:53:43 PM PDT 24
Peak memory	562792 kb
Host	smart-e10c151f-b60e-41fd-ab3e-b65b19389e86
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733458229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1733458229
Directory	/workspace/74.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.2431456923
Short name	T1699
Test name
Test status
Simulation time	14909760398 ps
CPU time	285.96 seconds
Started	Apr 23 04:46:56 PM PDT 24
Finished	Apr 23 04:51:42 PM PDT 24
Peak memory	562764 kb
Host	smart-022cdbc6-9e99-47a7-9b79-2200d0702dce
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431456923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.2431456923
Directory	/workspace/74.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.4049390175
Short name	T531
Test name
Test status
Simulation time	452429733 ps
CPU time	43.25 seconds
Started	Apr 23 04:46:52 PM PDT 24
Finished	Apr 23 04:47:36 PM PDT 24
Peak memory	562748 kb
Host	smart-5a7ca6b9-2b96-418f-b173-a7e3e7b482c3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049390175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.4049390175
Directory	/workspace/74.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_same_source.4178225948
Short name	T2476
Test name
Test status
Simulation time	1018905504 ps
CPU time	33.38 seconds
Started	Apr 23 04:46:55 PM PDT 24
Finished	Apr 23 04:47:29 PM PDT 24
Peak memory	562756 kb
Host	smart-9402e19d-b5db-4cad-ae8c-9901826ebdca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178225948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.4178225948
Directory	/workspace/74.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke.3544091432
Short name	T2011
Test name
Test status
Simulation time	237412346 ps
CPU time	11.24 seconds
Started	Apr 23 04:46:45 PM PDT 24
Finished	Apr 23 04:46:57 PM PDT 24
Peak memory	562620 kb
Host	smart-6edd8706-1cff-479f-b201-066544d2b5ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544091432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.3544091432
Directory	/workspace/74.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.3155360825
Short name	T2689
Test name
Test status
Simulation time	5207990719 ps
CPU time	54.62 seconds
Started	Apr 23 04:46:54 PM PDT 24
Finished	Apr 23 04:47:49 PM PDT 24
Peak memory	562760 kb
Host	smart-f1e627b6-86a7-4463-aa26-2cbeaca78924
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155360825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.3155360825
Directory	/workspace/74.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.2384361396
Short name	T1632
Test name
Test status
Simulation time	5267735087 ps
CPU time	99.42 seconds
Started	Apr 23 04:46:51 PM PDT 24
Finished	Apr 23 04:48:31 PM PDT 24
Peak memory	562748 kb
Host	smart-435450b9-c149-47ac-b3b6-9909a1c4b236
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384361396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.2384361396
Directory	/workspace/74.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1622990156
Short name	T2254
Test name
Test status
Simulation time	48583561 ps
CPU time	6.4 seconds
Started	Apr 23 04:46:48 PM PDT 24
Finished	Apr 23 04:46:55 PM PDT 24
Peak memory	562684 kb
Host	smart-82fba2a2-46c6-410f-bcee-6ab402b06457
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622990156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.1622990156
Directory	/workspace/74.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all.2793487689
Short name	T534
Test name
Test status
Simulation time	3184296730 ps
CPU time	109.01 seconds
Started	Apr 23 04:46:59 PM PDT 24
Finished	Apr 23 04:48:48 PM PDT 24
Peak memory	562940 kb
Host	smart-31641f80-44c6-4a63-8ce6-deeab5c7a950
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793487689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2793487689
Directory	/workspace/74.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.2772117660
Short name	T1442
Test name
Test status
Simulation time	2675417873 ps
CPU time	221.99 seconds
Started	Apr 23 04:46:59 PM PDT 24
Finished	Apr 23 04:50:42 PM PDT 24
Peak memory	562912 kb
Host	smart-e836b1a0-2fc5-4a75-aaa8-16ab41caeb19
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772117660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.2772117660
Directory	/workspace/74.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1281442589
Short name	T1906
Test name
Test status
Simulation time	6899243651 ps
CPU time	433.99 seconds
Started	Apr 23 04:46:57 PM PDT 24
Finished	Apr 23 04:54:11 PM PDT 24
Peak memory	572216 kb
Host	smart-00a013d0-3c7b-41b8-8e6e-9f89c98bb0db
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281442589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.1281442589
Directory	/workspace/74.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3811606177
Short name	T2372
Test name
Test status
Simulation time	6745692479 ps
CPU time	370.88 seconds
Started	Apr 23 04:47:03 PM PDT 24
Finished	Apr 23 04:53:14 PM PDT 24
Peak memory	572212 kb
Host	smart-8a1b907c-2692-45f8-9e66-b0fd0218f8cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811606177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.3811606177
Directory	/workspace/74.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.473401237
Short name	T2199
Test name
Test status
Simulation time	1156904598 ps
CPU time	56.08 seconds
Started	Apr 23 04:46:59 PM PDT 24
Finished	Apr 23 04:47:55 PM PDT 24
Peak memory	562808 kb
Host	smart-69c880a6-6d64-4395-8393-f068d1ff5ece
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473401237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.473401237
Directory	/workspace/74.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_access_same_device.4030231013
Short name	T2006
Test name
Test status
Simulation time	2784485830 ps
CPU time	135.43 seconds
Started	Apr 23 04:47:02 PM PDT 24
Finished	Apr 23 04:49:18 PM PDT 24
Peak memory	562788 kb
Host	smart-ec7e9a06-3514-42a8-8e51-4bfd3212abc6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030231013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .4030231013
Directory	/workspace/75.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.734443184
Short name	T2092
Test name
Test status
Simulation time	103480232213 ps
CPU time	1804.47 seconds
Started	Apr 23 04:47:01 PM PDT 24
Finished	Apr 23 05:17:06 PM PDT 24
Peak memory	562920 kb
Host	smart-08648f1d-2004-4d96-a560-0d15a970ff91
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734443184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_d evice_slow_rsp.734443184
Directory	/workspace/75.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3340572771
Short name	T2073
Test name
Test status
Simulation time	293542230 ps
CPU time	30.81 seconds
Started	Apr 23 04:47:01 PM PDT 24
Finished	Apr 23 04:47:32 PM PDT 24
Peak memory	562744 kb
Host	smart-e1abed73-b411-444b-9308-2fb136637c06
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340572771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.3340572771
Directory	/workspace/75.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_error_random.2678205559
Short name	T2266
Test name
Test status
Simulation time	1480179776 ps
CPU time	57.96 seconds
Started	Apr 23 04:47:04 PM PDT 24
Finished	Apr 23 04:48:03 PM PDT 24
Peak memory	562712 kb
Host	smart-95177156-ed91-44b4-a5a2-20779d38fa3b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678205559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2678205559
Directory	/workspace/75.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_random.2142791632
Short name	T1707
Test name
Test status
Simulation time	1531452625 ps
CPU time	54.96 seconds
Started	Apr 23 04:47:04 PM PDT 24
Finished	Apr 23 04:48:00 PM PDT 24
Peak memory	562752 kb
Host	smart-6bdcb9e3-6c75-470e-8eb7-93137424fa05
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142791632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.2142791632
Directory	/workspace/75.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3580505688
Short name	T2296
Test name
Test status
Simulation time	108273042049 ps
CPU time	1099.51 seconds
Started	Apr 23 04:47:02 PM PDT 24
Finished	Apr 23 05:05:22 PM PDT 24
Peak memory	562840 kb
Host	smart-224c2435-66ee-4430-b15c-d9cd72a18d05
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580505688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.3580505688
Directory	/workspace/75.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3287604196
Short name	T2787
Test name
Test status
Simulation time	14431088436 ps
CPU time	275.7 seconds
Started	Apr 23 04:47:03 PM PDT 24
Finished	Apr 23 04:51:39 PM PDT 24
Peak memory	562800 kb
Host	smart-d552cd12-f7df-43eb-9cfd-539442fc7596
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287604196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3287604196
Directory	/workspace/75.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.220459022
Short name	T578
Test name
Test status
Simulation time	394270519 ps
CPU time	40.47 seconds
Started	Apr 23 04:47:00 PM PDT 24
Finished	Apr 23 04:47:40 PM PDT 24
Peak memory	562736 kb
Host	smart-52b8ec13-9f21-422a-accd-d3ae8c531ca2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220459022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_dela ys.220459022
Directory	/workspace/75.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_same_source.1155086994
Short name	T1774
Test name
Test status
Simulation time	2360259200 ps
CPU time	70.97 seconds
Started	Apr 23 04:47:05 PM PDT 24
Finished	Apr 23 04:48:17 PM PDT 24
Peak memory	562796 kb
Host	smart-5ac51759-e536-49ee-b6f6-0a648e3b0cee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155086994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.1155086994
Directory	/workspace/75.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke.904448588
Short name	T1308
Test name
Test status
Simulation time	245598001 ps
CPU time	10.6 seconds
Started	Apr 23 04:46:57 PM PDT 24
Finished	Apr 23 04:47:08 PM PDT 24
Peak memory	562680 kb
Host	smart-1175669a-7148-4730-b47c-868e55160cec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904448588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.904448588
Directory	/workspace/75.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.1834735877
Short name	T2499
Test name
Test status
Simulation time	7124951211 ps
CPU time	75.18 seconds
Started	Apr 23 04:47:04 PM PDT 24
Finished	Apr 23 04:48:19 PM PDT 24
Peak memory	562764 kb
Host	smart-cfce5275-a8a5-4fcf-81f4-cc4ae07e0d0d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834735877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.1834735877
Directory	/workspace/75.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3040761189
Short name	T1369
Test name
Test status
Simulation time	4535467082 ps
CPU time	75.49 seconds
Started	Apr 23 04:47:03 PM PDT 24
Finished	Apr 23 04:48:19 PM PDT 24
Peak memory	562784 kb
Host	smart-9e6a0547-19de-4772-98fc-0e0e73382df2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040761189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.3040761189
Directory	/workspace/75.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.3591610602
Short name	T2131
Test name
Test status
Simulation time	43095702 ps
CPU time	6.59 seconds
Started	Apr 23 04:47:00 PM PDT 24
Finished	Apr 23 04:47:07 PM PDT 24
Peak memory	562692 kb
Host	smart-25153b3c-9ad7-414e-b310-d7c3dc04df7c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591610602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.3591610602
Directory	/workspace/75.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all.1655986231
Short name	T493
Test name
Test status
Simulation time	16284661001 ps
CPU time	582.76 seconds
Started	Apr 23 04:47:01 PM PDT 24
Finished	Apr 23 04:56:45 PM PDT 24
Peak memory	563944 kb
Host	smart-bbe2dacd-2616-48d9-a1f8-d2fc364ed932
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655986231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.1655986231
Directory	/workspace/75.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.3158853885
Short name	T1570
Test name
Test status
Simulation time	577878118 ps
CPU time	52.69 seconds
Started	Apr 23 04:47:01 PM PDT 24
Finished	Apr 23 04:47:54 PM PDT 24
Peak memory	562812 kb
Host	smart-8ef8710c-1163-4545-94fb-3c866dfa4192
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158853885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.3158853885
Directory	/workspace/75.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1859046712
Short name	T2435
Test name
Test status
Simulation time	9501680147 ps
CPU time	609.33 seconds
Started	Apr 23 04:47:00 PM PDT 24
Finished	Apr 23 04:57:09 PM PDT 24
Peak memory	572176 kb
Host	smart-a9df226b-12c0-41a5-aef3-43f9bf8ca390
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859046712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.1859046712
Directory	/workspace/75.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1928179043
Short name	T1515
Test name
Test status
Simulation time	1362870889 ps
CPU time	59.29 seconds
Started	Apr 23 04:47:02 PM PDT 24
Finished	Apr 23 04:48:01 PM PDT 24
Peak memory	562728 kb
Host	smart-4a5fff08-c649-4e2c-a7cc-6dec7e9c4762
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928179043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.1928179043
Directory	/workspace/75.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_access_same_device.1170908932
Short name	T1455
Test name
Test status
Simulation time	577001759 ps
CPU time	27.46 seconds
Started	Apr 23 04:47:07 PM PDT 24
Finished	Apr 23 04:47:34 PM PDT 24
Peak memory	562716 kb
Host	smart-1fde45c5-a498-4b53-9564-48f0c8f73977
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170908932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .1170908932
Directory	/workspace/76.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3491404773
Short name	T2663
Test name
Test status
Simulation time	69258309 ps
CPU time	9.91 seconds
Started	Apr 23 04:47:16 PM PDT 24
Finished	Apr 23 04:47:26 PM PDT 24
Peak memory	562704 kb
Host	smart-8ad776c6-72ce-4f8c-848e-9d0c83b99a74
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491404773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.3491404773
Directory	/workspace/76.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_error_random.3110128402
Short name	T2483
Test name
Test status
Simulation time	526835711 ps
CPU time	21.8 seconds
Started	Apr 23 04:47:11 PM PDT 24
Finished	Apr 23 04:47:33 PM PDT 24
Peak memory	562676 kb
Host	smart-77772795-1ffb-432a-b1c1-c317b589c617
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110128402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3110128402
Directory	/workspace/76.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_random.168434703
Short name	T2039
Test name
Test status
Simulation time	618683062 ps
CPU time	49.29 seconds
Started	Apr 23 04:47:09 PM PDT 24
Finished	Apr 23 04:47:58 PM PDT 24
Peak memory	562708 kb
Host	smart-3524c547-441d-4efd-b51e-591d6dede541
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168434703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.168434703
Directory	/workspace/76.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_random_large_delays.2811932204
Short name	T1718
Test name
Test status
Simulation time	79833033760 ps
CPU time	900.61 seconds
Started	Apr 23 04:47:08 PM PDT 24
Finished	Apr 23 05:02:09 PM PDT 24
Peak memory	562780 kb
Host	smart-2647156e-cb46-4be0-8fcf-071cf7347c31
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811932204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.2811932204
Directory	/workspace/76.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.1023339773
Short name	T2644
Test name
Test status
Simulation time	20016229759 ps
CPU time	321.36 seconds
Started	Apr 23 04:47:08 PM PDT 24
Finished	Apr 23 04:52:30 PM PDT 24
Peak memory	562812 kb
Host	smart-ff9b1dd7-5903-49ae-957c-547d78709abb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023339773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.1023339773
Directory	/workspace/76.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.4067668642
Short name	T1998
Test name
Test status
Simulation time	624594673 ps
CPU time	56.75 seconds
Started	Apr 23 04:47:09 PM PDT 24
Finished	Apr 23 04:48:06 PM PDT 24
Peak memory	562696 kb
Host	smart-05cd5483-323a-46c7-b2da-95522d402a84
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067668642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.4067668642
Directory	/workspace/76.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_same_source.927708161
Short name	T1534
Test name
Test status
Simulation time	1073238644 ps
CPU time	34.31 seconds
Started	Apr 23 04:47:09 PM PDT 24
Finished	Apr 23 04:47:44 PM PDT 24
Peak memory	562724 kb
Host	smart-5778030e-1324-4b10-8f21-be8e0c5a9ffe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927708161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.927708161
Directory	/workspace/76.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke.405658621
Short name	T2258
Test name
Test status
Simulation time	55872225 ps
CPU time	6.96 seconds
Started	Apr 23 04:47:08 PM PDT 24
Finished	Apr 23 04:47:15 PM PDT 24
Peak memory	562708 kb
Host	smart-3ae3d797-3647-4ac7-b947-72ebb1e8ee3b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405658621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.405658621
Directory	/workspace/76.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.3261541211
Short name	T2696
Test name
Test status
Simulation time	7328751206 ps
CPU time	80.7 seconds
Started	Apr 23 04:47:02 PM PDT 24
Finished	Apr 23 04:48:23 PM PDT 24
Peak memory	562776 kb
Host	smart-f7eaaec6-b9dd-498e-8820-574f1f82b611
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261541211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.3261541211
Directory	/workspace/76.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2492793985
Short name	T1317
Test name
Test status
Simulation time	5614428611 ps
CPU time	100.58 seconds
Started	Apr 23 04:47:04 PM PDT 24
Finished	Apr 23 04:48:45 PM PDT 24
Peak memory	562756 kb
Host	smart-1d6c7948-f450-4243-815e-ebad0e440d8b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492793985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.2492793985
Directory	/workspace/76.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.42457806
Short name	T2458
Test name
Test status
Simulation time	40839127 ps
CPU time	6.32 seconds
Started	Apr 23 04:47:04 PM PDT 24
Finished	Apr 23 04:47:10 PM PDT 24
Peak memory	562704 kb
Host	smart-49c377ca-6a9e-4d3d-b28a-a76a9e0bcf88
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42457806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays.42457806
Directory	/workspace/76.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.3314449869
Short name	T1965
Test name
Test status
Simulation time	2246664710 ps
CPU time	99.61 seconds
Started	Apr 23 04:47:12 PM PDT 24
Finished	Apr 23 04:48:52 PM PDT 24
Peak memory	562848 kb
Host	smart-2f8ae202-74eb-4ea7-8e30-5231582a0fe5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314449869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3314449869
Directory	/workspace/76.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1455281802
Short name	T2745
Test name
Test status
Simulation time	344456126 ps
CPU time	166.2 seconds
Started	Apr 23 04:47:12 PM PDT 24
Finished	Apr 23 04:49:59 PM PDT 24
Peak memory	563928 kb
Host	smart-4682c932-186c-45f9-8840-0818df82ad15
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455281802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.1455281802
Directory	/workspace/76.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.336089454
Short name	T1854
Test name
Test status
Simulation time	1758980777 ps
CPU time	212.94 seconds
Started	Apr 23 04:47:14 PM PDT 24
Finished	Apr 23 04:50:47 PM PDT 24
Peak memory	572108 kb
Host	smart-d22c2829-58bb-408d-affe-a1575c905117
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336089454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_reset_error.336089454
Directory	/workspace/76.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1886682516
Short name	T1657
Test name
Test status
Simulation time	724857900 ps
CPU time	33.53 seconds
Started	Apr 23 04:47:12 PM PDT 24
Finished	Apr 23 04:47:46 PM PDT 24
Peak memory	562776 kb
Host	smart-57568d4d-8de8-4004-8f56-fbcfaee6a1c2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886682516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1886682516
Directory	/workspace/76.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_access_same_device.3629435969
Short name	T2431
Test name
Test status
Simulation time	743771209 ps
CPU time	62.51 seconds
Started	Apr 23 04:47:18 PM PDT 24
Finished	Apr 23 04:48:21 PM PDT 24
Peak memory	562740 kb
Host	smart-1d58d0d8-8464-4aca-a464-2f3caa6b8ba7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629435969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .3629435969
Directory	/workspace/77.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.588063632
Short name	T1597
Test name
Test status
Simulation time	65173916845 ps
CPU time	1123.83 seconds
Started	Apr 23 04:47:19 PM PDT 24
Finished	Apr 23 05:06:03 PM PDT 24
Peak memory	562748 kb
Host	smart-3f691592-c6bd-424e-9dc0-8a94cb69d34a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588063632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_d evice_slow_rsp.588063632
Directory	/workspace/77.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2310735052
Short name	T2070
Test name
Test status
Simulation time	663436621 ps
CPU time	29.21 seconds
Started	Apr 23 04:47:22 PM PDT 24
Finished	Apr 23 04:47:51 PM PDT 24
Peak memory	562752 kb
Host	smart-c753f1ab-26ef-426c-91f8-52fb43fac673
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310735052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.2310735052
Directory	/workspace/77.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_error_random.3544398978
Short name	T1384
Test name
Test status
Simulation time	264730188 ps
CPU time	26.79 seconds
Started	Apr 23 04:47:18 PM PDT 24
Finished	Apr 23 04:47:45 PM PDT 24
Peak memory	562680 kb
Host	smart-bc6a7abd-de9d-48da-b9a3-025a0e2dac67
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544398978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3544398978
Directory	/workspace/77.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_random.3283170320
Short name	T1309
Test name
Test status
Simulation time	2462748265 ps
CPU time	98.11 seconds
Started	Apr 23 04:47:16 PM PDT 24
Finished	Apr 23 04:48:54 PM PDT 24
Peak memory	562796 kb
Host	smart-b899a630-d12e-4704-828c-0fd404f0f31a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283170320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3283170320
Directory	/workspace/77.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_random_large_delays.387314754
Short name	T2686
Test name
Test status
Simulation time	86462306972 ps
CPU time	925.35 seconds
Started	Apr 23 04:47:17 PM PDT 24
Finished	Apr 23 05:02:42 PM PDT 24
Peak memory	562776 kb
Host	smart-c2267339-2134-4d6c-bfc9-a8e524399835
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387314754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.387314754
Directory	/workspace/77.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.1224320559
Short name	T1713
Test name
Test status
Simulation time	42191165766 ps
CPU time	726.5 seconds
Started	Apr 23 04:47:18 PM PDT 24
Finished	Apr 23 04:59:25 PM PDT 24
Peak memory	562864 kb
Host	smart-93b25902-ecce-4a50-873d-95441c6842f2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224320559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.1224320559
Directory	/workspace/77.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1664042040
Short name	T450
Test name
Test status
Simulation time	281161807 ps
CPU time	29.55 seconds
Started	Apr 23 04:47:14 PM PDT 24
Finished	Apr 23 04:47:44 PM PDT 24
Peak memory	562748 kb
Host	smart-f67969dc-e470-4e55-bfbe-07a853f5cc1a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664042040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.1664042040
Directory	/workspace/77.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_same_source.3838608356
Short name	T570
Test name
Test status
Simulation time	629285602 ps
CPU time	21.12 seconds
Started	Apr 23 04:47:19 PM PDT 24
Finished	Apr 23 04:47:41 PM PDT 24
Peak memory	562676 kb
Host	smart-b3353b48-7e9c-41ed-928d-454871c220a1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838608356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3838608356
Directory	/workspace/77.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke.1044757819
Short name	T1905
Test name
Test status
Simulation time	44345991 ps
CPU time	6.52 seconds
Started	Apr 23 04:47:15 PM PDT 24
Finished	Apr 23 04:47:21 PM PDT 24
Peak memory	562728 kb
Host	smart-a378ca05-cbee-4e7a-99a9-64b73969686a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044757819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1044757819
Directory	/workspace/77.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.1155714142
Short name	T1721
Test name
Test status
Simulation time	10495429066 ps
CPU time	106.08 seconds
Started	Apr 23 04:47:14 PM PDT 24
Finished	Apr 23 04:49:00 PM PDT 24
Peak memory	562804 kb
Host	smart-19bf7415-193a-48ea-b689-a86dc467d1b6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155714142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1155714142
Directory	/workspace/77.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.116186628
Short name	T2650
Test name
Test status
Simulation time	4131196876 ps
CPU time	68.57 seconds
Started	Apr 23 04:47:16 PM PDT 24
Finished	Apr 23 04:48:25 PM PDT 24
Peak memory	562756 kb
Host	smart-a7f07cea-9e9e-4064-ba99-8747d1d4e4b5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116186628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.116186628
Directory	/workspace/77.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2809537269
Short name	T2407
Test name
Test status
Simulation time	42685460 ps
CPU time	6.21 seconds
Started	Apr 23 04:47:16 PM PDT 24
Finished	Apr 23 04:47:23 PM PDT 24
Peak memory	562724 kb
Host	smart-45131a00-d43f-4d0b-be49-9914da472938
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809537269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.2809537269
Directory	/workspace/77.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all.2154800761
Short name	T527
Test name
Test status
Simulation time	5784854330 ps
CPU time	265.93 seconds
Started	Apr 23 04:47:22 PM PDT 24
Finished	Apr 23 04:51:48 PM PDT 24
Peak memory	563056 kb
Host	smart-3c3602e9-5e35-4da0-bbea-b17aca77ae5d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154800761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.2154800761
Directory	/workspace/77.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.2141413438
Short name	T2321
Test name
Test status
Simulation time	1628750222 ps
CPU time	121.61 seconds
Started	Apr 23 04:47:27 PM PDT 24
Finished	Apr 23 04:49:29 PM PDT 24
Peak memory	562816 kb
Host	smart-0440479e-2107-49d7-8ce2-867d430e6cbe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141413438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.2141413438
Directory	/workspace/77.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3334440260
Short name	T1532
Test name
Test status
Simulation time	769583085 ps
CPU time	279.08 seconds
Started	Apr 23 04:47:25 PM PDT 24
Finished	Apr 23 04:52:04 PM PDT 24
Peak memory	572180 kb
Host	smart-05552535-41df-402d-92f0-ce00376cbe2f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334440260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.3334440260
Directory	/workspace/77.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2550682504
Short name	T1810
Test name
Test status
Simulation time	7496932312 ps
CPU time	294.18 seconds
Started	Apr 23 04:47:21 PM PDT 24
Finished	Apr 23 04:52:16 PM PDT 24
Peak memory	572192 kb
Host	smart-c3351d98-5a73-4c5f-b7e1-cfbbe513e430
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550682504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.2550682504
Directory	/workspace/77.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1286411615
Short name	T435
Test name
Test status
Simulation time	716828827 ps
CPU time	36.83 seconds
Started	Apr 23 04:47:19 PM PDT 24
Finished	Apr 23 04:47:56 PM PDT 24
Peak memory	562696 kb
Host	smart-0c2fadb9-b537-4e44-92d1-629511e5d153
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286411615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1286411615
Directory	/workspace/77.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_access_same_device.2619880973
Short name	T2103
Test name
Test status
Simulation time	2545333323 ps
CPU time	113.41 seconds
Started	Apr 23 04:47:30 PM PDT 24
Finished	Apr 23 04:49:24 PM PDT 24
Peak memory	562896 kb
Host	smart-d77c5883-7a23-4c99-b646-fa95069a9273
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619880973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .2619880973
Directory	/workspace/78.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3561409016
Short name	T793
Test name
Test status
Simulation time	11018244703 ps
CPU time	199.72 seconds
Started	Apr 23 04:47:36 PM PDT 24
Finished	Apr 23 04:50:56 PM PDT 24
Peak memory	562744 kb
Host	smart-0f8045bc-dfb1-406e-9e5c-ba0e0b30def1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561409016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.3561409016
Directory	/workspace/78.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2496829734
Short name	T1626
Test name
Test status
Simulation time	322273819 ps
CPU time	36.61 seconds
Started	Apr 23 04:47:36 PM PDT 24
Finished	Apr 23 04:48:13 PM PDT 24
Peak memory	562652 kb
Host	smart-aa6e8d3c-46c1-4b28-b4c8-58ad7e1636f5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496829734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.2496829734
Directory	/workspace/78.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_error_random.50878879
Short name	T1671
Test name
Test status
Simulation time	2077013266 ps
CPU time	79.42 seconds
Started	Apr 23 04:47:32 PM PDT 24
Finished	Apr 23 04:48:52 PM PDT 24
Peak memory	562692 kb
Host	smart-da57224d-863a-4f0f-9b61-6446b62fe76b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50878879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.50878879
Directory	/workspace/78.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_random.2638062129
Short name	T2190
Test name
Test status
Simulation time	420451412 ps
CPU time	39.46 seconds
Started	Apr 23 04:47:27 PM PDT 24
Finished	Apr 23 04:48:06 PM PDT 24
Peak memory	562732 kb
Host	smart-2fee2420-cb88-44c1-9c6a-dff8527cd48f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638062129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2638062129
Directory	/workspace/78.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_random_large_delays.4163993159
Short name	T2620
Test name
Test status
Simulation time	104330116184 ps
CPU time	1110.01 seconds
Started	Apr 23 04:47:27 PM PDT 24
Finished	Apr 23 05:05:57 PM PDT 24
Peak memory	562792 kb
Host	smart-2c7e38d9-b89c-4ff6-b73e-c4cd99bf5c78
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163993159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.4163993159
Directory	/workspace/78.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.3102884306
Short name	T2368
Test name
Test status
Simulation time	7803928696 ps
CPU time	142.33 seconds
Started	Apr 23 04:47:34 PM PDT 24
Finished	Apr 23 04:49:56 PM PDT 24
Peak memory	562812 kb
Host	smart-7a18075e-6b73-4fe0-94d8-c7f523ffc032
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102884306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.3102884306
Directory	/workspace/78.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1443836143
Short name	T572
Test name
Test status
Simulation time	423754453 ps
CPU time	36.24 seconds
Started	Apr 23 04:47:27 PM PDT 24
Finished	Apr 23 04:48:04 PM PDT 24
Peak memory	562708 kb
Host	smart-044849c0-f25a-4f97-afb8-4a87e4901d26
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443836143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.1443836143
Directory	/workspace/78.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_same_source.3606239119
Short name	T1391
Test name
Test status
Simulation time	843127641 ps
CPU time	25.36 seconds
Started	Apr 23 04:47:29 PM PDT 24
Finished	Apr 23 04:47:54 PM PDT 24
Peak memory	562696 kb
Host	smart-d1218600-ea66-4e86-b8b4-ca561a7d4d5d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606239119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3606239119
Directory	/workspace/78.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke.1488449021
Short name	T621
Test name
Test status
Simulation time	48754958 ps
CPU time	6.97 seconds
Started	Apr 23 04:47:22 PM PDT 24
Finished	Apr 23 04:47:29 PM PDT 24
Peak memory	562652 kb
Host	smart-b0ee0150-b0ac-4da1-9d03-52f8932138c2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488449021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.1488449021
Directory	/workspace/78.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.3845940924
Short name	T2680
Test name
Test status
Simulation time	8383813970 ps
CPU time	87.16 seconds
Started	Apr 23 04:47:25 PM PDT 24
Finished	Apr 23 04:48:53 PM PDT 24
Peak memory	562760 kb
Host	smart-5e848a2c-6e55-4736-b2bc-6dae34df822b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845940924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.3845940924
Directory	/workspace/78.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1241145010
Short name	T1406
Test name
Test status
Simulation time	4976260348 ps
CPU time	89.91 seconds
Started	Apr 23 04:47:24 PM PDT 24
Finished	Apr 23 04:48:54 PM PDT 24
Peak memory	562768 kb
Host	smart-d02d21c7-525f-4a2f-a9fa-54902fdfdf27
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241145010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.1241145010
Directory	/workspace/78.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1837987971
Short name	T1530
Test name
Test status
Simulation time	51231770 ps
CPU time	6.91 seconds
Started	Apr 23 04:47:21 PM PDT 24
Finished	Apr 23 04:47:29 PM PDT 24
Peak memory	562704 kb
Host	smart-c67844d2-5d02-4e44-9fba-cf075ba1b2c5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837987971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.1837987971
Directory	/workspace/78.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all.2207329242
Short name	T2129
Test name
Test status
Simulation time	1992383730 ps
CPU time	90.36 seconds
Started	Apr 23 04:47:38 PM PDT 24
Finished	Apr 23 04:49:08 PM PDT 24
Peak memory	562852 kb
Host	smart-e052e34a-1d9e-425b-9f8a-2e11358a3204
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207329242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2207329242
Directory	/workspace/78.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.733748465
Short name	T2057
Test name
Test status
Simulation time	2839624906 ps
CPU time	115.75 seconds
Started	Apr 23 04:47:37 PM PDT 24
Finished	Apr 23 04:49:33 PM PDT 24
Peak memory	562880 kb
Host	smart-49ebae9e-dafe-408c-9b9d-9d96dedac422
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733748465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.733748465
Directory	/workspace/78.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2676566683
Short name	T1937
Test name
Test status
Simulation time	916056766 ps
CPU time	331.88 seconds
Started	Apr 23 04:47:37 PM PDT 24
Finished	Apr 23 04:53:10 PM PDT 24
Peak memory	572160 kb
Host	smart-0118293f-5fea-4d9f-95c6-ff5be5443180
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676566683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.2676566683
Directory	/workspace/78.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1628424051
Short name	T2545
Test name
Test status
Simulation time	667712394 ps
CPU time	233.67 seconds
Started	Apr 23 04:47:33 PM PDT 24
Finished	Apr 23 04:51:27 PM PDT 24
Peak memory	572100 kb
Host	smart-1b58a347-9dc4-43d3-861d-5682df365f5e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628424051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.1628424051
Directory	/workspace/78.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.465334153
Short name	T2572
Test name
Test status
Simulation time	775066421 ps
CPU time	32.75 seconds
Started	Apr 23 04:47:32 PM PDT 24
Finished	Apr 23 04:48:05 PM PDT 24
Peak memory	562784 kb
Host	smart-05cc7ea5-26c8-4fdb-b785-236e458d097e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465334153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.465334153
Directory	/workspace/78.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_access_same_device.1968548604
Short name	T2675
Test name
Test status
Simulation time	952921931 ps
CPU time	84.31 seconds
Started	Apr 23 04:47:39 PM PDT 24
Finished	Apr 23 04:49:04 PM PDT 24
Peak memory	562804 kb
Host	smart-dd9b42c6-fe9d-4508-9827-cf86ba6a06b2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968548604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .1968548604
Directory	/workspace/79.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.378460216
Short name	T1453
Test name
Test status
Simulation time	15580264417 ps
CPU time	286.14 seconds
Started	Apr 23 04:47:40 PM PDT 24
Finished	Apr 23 04:52:27 PM PDT 24
Peak memory	562748 kb
Host	smart-87bacd59-0978-4f6e-a2ef-10d65c625543
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378460216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_d evice_slow_rsp.378460216
Directory	/workspace/79.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1248937853
Short name	T1799
Test name
Test status
Simulation time	160920442 ps
CPU time	20.73 seconds
Started	Apr 23 04:47:43 PM PDT 24
Finished	Apr 23 04:48:04 PM PDT 24
Peak memory	562644 kb
Host	smart-d37c086c-91cb-4cef-a3a0-3812718b1c4e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248937853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.1248937853
Directory	/workspace/79.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_error_random.2153239740
Short name	T1276
Test name
Test status
Simulation time	2207105820 ps
CPU time	81.25 seconds
Started	Apr 23 04:47:40 PM PDT 24
Finished	Apr 23 04:49:01 PM PDT 24
Peak memory	562744 kb
Host	smart-c6c5b08e-ae31-4738-a361-38653e485713
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153239740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.2153239740
Directory	/workspace/79.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_random.2491145583
Short name	T1723
Test name
Test status
Simulation time	1276995981 ps
CPU time	46.5 seconds
Started	Apr 23 04:47:36 PM PDT 24
Finished	Apr 23 04:48:23 PM PDT 24
Peak memory	562728 kb
Host	smart-d872a711-8317-4018-a6d3-f702c15bc012
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491145583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.2491145583
Directory	/workspace/79.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3066908613
Short name	T2446
Test name
Test status
Simulation time	92257369901 ps
CPU time	1111.65 seconds
Started	Apr 23 04:47:42 PM PDT 24
Finished	Apr 23 05:06:14 PM PDT 24
Peak memory	562764 kb
Host	smart-5619110c-708f-4f12-9948-e3bc534b319d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066908613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3066908613
Directory	/workspace/79.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.4195786743
Short name	T589
Test name
Test status
Simulation time	41530447415 ps
CPU time	775.11 seconds
Started	Apr 23 04:47:36 PM PDT 24
Finished	Apr 23 05:00:31 PM PDT 24
Peak memory	562832 kb
Host	smart-b76cc086-d1b2-4106-a132-b9c3f40b3f05
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195786743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.4195786743
Directory	/workspace/79.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.852127332
Short name	T1499
Test name
Test status
Simulation time	311905377 ps
CPU time	32.37 seconds
Started	Apr 23 04:47:37 PM PDT 24
Finished	Apr 23 04:48:10 PM PDT 24
Peak memory	562656 kb
Host	smart-1b6f1014-c559-48d8-9ed3-59e08edc9b11
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852127332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_dela ys.852127332
Directory	/workspace/79.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_same_source.1313095115
Short name	T2280
Test name
Test status
Simulation time	903286016 ps
CPU time	31.37 seconds
Started	Apr 23 04:47:41 PM PDT 24
Finished	Apr 23 04:48:13 PM PDT 24
Peak memory	562712 kb
Host	smart-ce158561-ba88-4c3b-afa4-c1c30169a57d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313095115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.1313095115
Directory	/workspace/79.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke.2598543970
Short name	T1574
Test name
Test status
Simulation time	186731797 ps
CPU time	8.92 seconds
Started	Apr 23 04:47:37 PM PDT 24
Finished	Apr 23 04:47:46 PM PDT 24
Peak memory	562696 kb
Host	smart-81f42186-e54c-42dc-becf-a432eb7bc335
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598543970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2598543970
Directory	/workspace/79.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3212338813
Short name	T830
Test name
Test status
Simulation time	8688295360 ps
CPU time	95.51 seconds
Started	Apr 23 04:47:38 PM PDT 24
Finished	Apr 23 04:49:14 PM PDT 24
Peak memory	562808 kb
Host	smart-d6c51a10-e7ac-422e-9a64-f48045a25719
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212338813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.3212338813
Directory	/workspace/79.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.3712594049
Short name	T2488
Test name
Test status
Simulation time	5232314513 ps
CPU time	96.92 seconds
Started	Apr 23 04:47:36 PM PDT 24
Finished	Apr 23 04:49:14 PM PDT 24
Peak memory	562796 kb
Host	smart-90a6745b-fdc0-4428-a128-366d6ceb8962
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712594049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.3712594049
Directory	/workspace/79.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.708787585
Short name	T580
Test name
Test status
Simulation time	46676081 ps
CPU time	6.71 seconds
Started	Apr 23 04:47:37 PM PDT 24
Finished	Apr 23 04:47:44 PM PDT 24
Peak memory	562648 kb
Host	smart-e6081932-7c3d-4dfb-8764-ef3cf713a903
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708787585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays .708787585
Directory	/workspace/79.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all.4257032787
Short name	T565
Test name
Test status
Simulation time	3575700304 ps
CPU time	140.25 seconds
Started	Apr 23 04:47:41 PM PDT 24
Finished	Apr 23 04:50:01 PM PDT 24
Peak memory	563016 kb
Host	smart-246537bb-9da8-49b7-a853-5c584e576775
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257032787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.4257032787
Directory	/workspace/79.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.2425127900
Short name	T1487
Test name
Test status
Simulation time	11220362388 ps
CPU time	439.44 seconds
Started	Apr 23 04:47:43 PM PDT 24
Finished	Apr 23 04:55:03 PM PDT 24
Peak memory	563992 kb
Host	smart-fc8b4d8e-d7ad-4357-a070-1a8f12979e23
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425127900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.2425127900
Directory	/workspace/79.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1414796340
Short name	T2381
Test name
Test status
Simulation time	17109022901 ps
CPU time	851.86 seconds
Started	Apr 23 04:47:44 PM PDT 24
Finished	Apr 23 05:01:56 PM PDT 24
Peak memory	572244 kb
Host	smart-91a7c8c2-ad00-4821-8cfa-f1baea842afb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414796340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.1414796340
Directory	/workspace/79.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.573253126
Short name	T2059
Test name
Test status
Simulation time	9448411787 ps
CPU time	428.66 seconds
Started	Apr 23 04:47:44 PM PDT 24
Finished	Apr 23 04:54:53 PM PDT 24
Peak memory	563984 kb
Host	smart-1666686c-dead-4e24-8323-6da046cbf2bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573253126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_reset_error.573253126
Directory	/workspace/79.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3871515081
Short name	T2155
Test name
Test status
Simulation time	1351672994 ps
CPU time	64.23 seconds
Started	Apr 23 04:47:41 PM PDT 24
Finished	Apr 23 04:48:45 PM PDT 24
Peak memory	562792 kb
Host	smart-c609b4c1-7592-455f-9690-4fc5ae0ed1c3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871515081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3871515081
Directory	/workspace/79.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/8.chip_csr_rw.2977927292
Short name	T2033
Test name
Test status
Simulation time	3736573692 ps
CPU time	301.19 seconds
Started	Apr 23 04:33:17 PM PDT 24
Finished	Apr 23 04:38:19 PM PDT 24
Peak memory	589396 kb
Host	smart-97a712d4-6e20-4366-8037-54be192009ae
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977927292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.2977927292
Directory	/workspace/8.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.chip_tl_errors.1690005921
Short name	T633
Test name
Test status
Simulation time	2883597032 ps
CPU time	190.21 seconds
Started	Apr 23 04:32:53 PM PDT 24
Finished	Apr 23 04:36:04 PM PDT 24
Peak memory	585260 kb
Host	smart-876baa14-7b1d-41ab-b074-e75dbb9214b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690005921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1690005921
Directory	/workspace/8.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_access_same_device.1065132285
Short name	T495
Test name
Test status
Simulation time	432185397 ps
CPU time	46.25 seconds
Started	Apr 23 04:33:07 PM PDT 24
Finished	Apr 23 04:33:54 PM PDT 24
Peak memory	562748 kb
Host	smart-d65c806e-d929-4ba7-987a-3b189de6e994
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065132285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 1065132285
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1863540192
Short name	T2161
Test name
Test status
Simulation time	142012292 ps
CPU time	9.48 seconds
Started	Apr 23 04:33:13 PM PDT 24
Finished	Apr 23 04:33:23 PM PDT 24
Peak memory	562736 kb
Host	smart-700ffb4a-494d-475a-9a13-9e4c89bbb2fd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863540192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .1863540192
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_error_random.2638955394
Short name	T1776
Test name
Test status
Simulation time	227312563 ps
CPU time	12.42 seconds
Started	Apr 23 04:33:13 PM PDT 24
Finished	Apr 23 04:33:25 PM PDT 24
Peak memory	562700 kb
Host	smart-627a8736-c217-405b-b366-f5f21a293954
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638955394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2638955394
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_random.3173812283
Short name	T1802
Test name
Test status
Simulation time	415377077 ps
CPU time	39.09 seconds
Started	Apr 23 04:33:02 PM PDT 24
Finished	Apr 23 04:33:41 PM PDT 24
Peak memory	562756 kb
Host	smart-c859cc46-c259-42c3-b8f5-02631be224f9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173812283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3173812283
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_random_large_delays.3605519184
Short name	T1578
Test name
Test status
Simulation time	8255860767 ps
CPU time	93.45 seconds
Started	Apr 23 04:33:00 PM PDT 24
Finished	Apr 23 04:34:33 PM PDT 24
Peak memory	562836 kb
Host	smart-99310e2b-c45d-4c00-9096-9b85591e4b7e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605519184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3605519184
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.807783360
Short name	T2379
Test name
Test status
Simulation time	33427587261 ps
CPU time	606.17 seconds
Started	Apr 23 04:33:06 PM PDT 24
Finished	Apr 23 04:43:13 PM PDT 24
Peak memory	562824 kb
Host	smart-75851722-145d-4928-b5fc-16996f5b6ffa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807783360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.807783360
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.305058106
Short name	T2539
Test name
Test status
Simulation time	67053121 ps
CPU time	9.15 seconds
Started	Apr 23 04:33:00 PM PDT 24
Finished	Apr 23 04:33:10 PM PDT 24
Peak memory	562716 kb
Host	smart-5a143ff3-e117-4fbf-aebb-37edf5bb350b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305058106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delay s.305058106
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_same_source.496413344
Short name	T2243
Test name
Test status
Simulation time	542804675 ps
CPU time	45.55 seconds
Started	Apr 23 04:33:21 PM PDT 24
Finished	Apr 23 04:34:07 PM PDT 24
Peak memory	562736 kb
Host	smart-4ba39164-3c49-4515-8a27-aa928012a345
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496413344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.496413344
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke.634064995
Short name	T1873
Test name
Test status
Simulation time	42712255 ps
CPU time	6.74 seconds
Started	Apr 23 04:33:00 PM PDT 24
Finished	Apr 23 04:33:07 PM PDT 24
Peak memory	562736 kb
Host	smart-6da5473c-a18d-4231-b819-9b400c6b08b4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634064995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.634064995
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.419665827
Short name	T2575
Test name
Test status
Simulation time	9823885482 ps
CPU time	105.44 seconds
Started	Apr 23 04:32:57 PM PDT 24
Finished	Apr 23 04:34:43 PM PDT 24
Peak memory	562800 kb
Host	smart-6d41db0d-4aac-4958-a40c-fe2e0da44ab0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419665827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.419665827
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.2250156726
Short name	T1890
Test name
Test status
Simulation time	6474154712 ps
CPU time	115.51 seconds
Started	Apr 23 04:32:57 PM PDT 24
Finished	Apr 23 04:34:53 PM PDT 24
Peak memory	562736 kb
Host	smart-1c91abac-1375-4fca-a60f-e71428ad8251
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250156726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2250156726
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3829215455
Short name	T2694
Test name
Test status
Simulation time	39473887 ps
CPU time	6.5 seconds
Started	Apr 23 04:33:00 PM PDT 24
Finished	Apr 23 04:33:06 PM PDT 24
Peak memory	562664 kb
Host	smart-65957f0e-ba56-4562-98cb-5dd896200b90
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829215455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .3829215455
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all.2302162376
Short name	T2561
Test name
Test status
Simulation time	1139168066 ps
CPU time	81.25 seconds
Started	Apr 23 04:33:14 PM PDT 24
Finished	Apr 23 04:34:36 PM PDT 24
Peak memory	563400 kb
Host	smart-f6f5b7b5-ad51-48c2-8a1a-abc064ff36ba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302162376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2302162376
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3420460313
Short name	T1297
Test name
Test status
Simulation time	2115140058 ps
CPU time	188.86 seconds
Started	Apr 23 04:33:17 PM PDT 24
Finished	Apr 23 04:36:26 PM PDT 24
Peak memory	563112 kb
Host	smart-5e98c798-27b9-42a8-8b11-3a692a43c058
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420460313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3420460313
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1908899161
Short name	T2790
Test name
Test status
Simulation time	1299170717 ps
CPU time	201.24 seconds
Started	Apr 23 04:33:13 PM PDT 24
Finished	Apr 23 04:36:34 PM PDT 24
Peak memory	572072 kb
Host	smart-66ebe2f2-b7d7-4dfc-b39a-d8d486468e48
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908899161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.1908899161
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1992182780
Short name	T1489
Test name
Test status
Simulation time	2178197705 ps
CPU time	283.46 seconds
Started	Apr 23 04:33:13 PM PDT 24
Finished	Apr 23 04:37:57 PM PDT 24
Peak memory	572164 kb
Host	smart-a19cd71d-7da3-48cd-9cb0-bbd2d7142159
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992182780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.1992182780
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.288990324
Short name	T1677
Test name
Test status
Simulation time	128133856 ps
CPU time	16.18 seconds
Started	Apr 23 04:33:12 PM PDT 24
Finished	Apr 23 04:33:29 PM PDT 24
Peak memory	562760 kb
Host	smart-b95de21b-366a-42bb-a53b-2997f237b456
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288990324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.288990324
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_access_same_device.2737352218
Short name	T2040
Test name
Test status
Simulation time	850106464 ps
CPU time	42.45 seconds
Started	Apr 23 04:47:48 PM PDT 24
Finished	Apr 23 04:48:31 PM PDT 24
Peak memory	562736 kb
Host	smart-ebb470e4-7282-4da9-ab74-597f70ec587c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737352218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .2737352218
Directory	/workspace/80.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.4147696792
Short name	T1324
Test name
Test status
Simulation time	23921004757 ps
CPU time	413.08 seconds
Started	Apr 23 04:47:51 PM PDT 24
Finished	Apr 23 04:54:44 PM PDT 24
Peak memory	562824 kb
Host	smart-0cf37d1b-6d56-4df8-945a-6a21a4c7721c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147696792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.4147696792
Directory	/workspace/80.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2002765472
Short name	T1274
Test name
Test status
Simulation time	204820160 ps
CPU time	22.54 seconds
Started	Apr 23 04:47:52 PM PDT 24
Finished	Apr 23 04:48:15 PM PDT 24
Peak memory	562712 kb
Host	smart-610a9064-e2fb-42ac-bbfb-722e513a0acf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002765472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.2002765472
Directory	/workspace/80.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_error_random.123793854
Short name	T2672
Test name
Test status
Simulation time	197339585 ps
CPU time	11.1 seconds
Started	Apr 23 04:47:51 PM PDT 24
Finished	Apr 23 04:48:03 PM PDT 24
Peak memory	562708 kb
Host	smart-534ee8d3-a3a1-4dc4-954e-a02f77defe87
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123793854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.123793854
Directory	/workspace/80.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_random.1037833941
Short name	T2346
Test name
Test status
Simulation time	2195045757 ps
CPU time	90.34 seconds
Started	Apr 23 04:47:52 PM PDT 24
Finished	Apr 23 04:49:23 PM PDT 24
Peak memory	562792 kb
Host	smart-ee997602-a655-44d3-8abe-570aba306647
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037833941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.1037833941
Directory	/workspace/80.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1217985704
Short name	T1292
Test name
Test status
Simulation time	43421117432 ps
CPU time	485.38 seconds
Started	Apr 23 04:47:47 PM PDT 24
Finished	Apr 23 04:55:53 PM PDT 24
Peak memory	562804 kb
Host	smart-cbfe3ede-887b-4d03-8cfb-565a75a25362
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217985704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.1217985704
Directory	/workspace/80.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.808232390
Short name	T1495
Test name
Test status
Simulation time	17307143627 ps
CPU time	332.06 seconds
Started	Apr 23 04:47:49 PM PDT 24
Finished	Apr 23 04:53:21 PM PDT 24
Peak memory	562832 kb
Host	smart-e6bf6ba3-6f56-4862-b8c1-2b38e4078233
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808232390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.808232390
Directory	/workspace/80.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.3645771720
Short name	T2401
Test name
Test status
Simulation time	555527874 ps
CPU time	51.2 seconds
Started	Apr 23 04:47:47 PM PDT 24
Finished	Apr 23 04:48:39 PM PDT 24
Peak memory	562768 kb
Host	smart-cc92554c-2c93-48f9-a72a-f9506d962155
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645771720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.3645771720
Directory	/workspace/80.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_same_source.316484081
Short name	T1900
Test name
Test status
Simulation time	322502368 ps
CPU time	28.63 seconds
Started	Apr 23 04:47:53 PM PDT 24
Finished	Apr 23 04:48:22 PM PDT 24
Peak memory	562712 kb
Host	smart-6712c4f7-e16b-425e-84c4-dbf1f10be825
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316484081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.316484081
Directory	/workspace/80.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke.3836538141
Short name	T1295
Test name
Test status
Simulation time	178388246 ps
CPU time	9.27 seconds
Started	Apr 23 04:47:42 PM PDT 24
Finished	Apr 23 04:47:51 PM PDT 24
Peak memory	562704 kb
Host	smart-a9c8479a-465b-476a-a7e1-61b9971c1679
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836538141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.3836538141
Directory	/workspace/80.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.2970184056
Short name	T575
Test name
Test status
Simulation time	7866630754 ps
CPU time	80.41 seconds
Started	Apr 23 04:47:49 PM PDT 24
Finished	Apr 23 04:49:09 PM PDT 24
Peak memory	562780 kb
Host	smart-735667c7-0ad3-4f51-8996-b7810c3d1a60
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970184056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.2970184056
Directory	/workspace/80.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.2405332113
Short name	T1573
Test name
Test status
Simulation time	3629395004 ps
CPU time	65.05 seconds
Started	Apr 23 04:47:48 PM PDT 24
Finished	Apr 23 04:48:53 PM PDT 24
Peak memory	562780 kb
Host	smart-08b7ac71-9b41-468a-accd-0abe66351738
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405332113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.2405332113
Directory	/workspace/80.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2287954755
Short name	T1930
Test name
Test status
Simulation time	41607612 ps
CPU time	6.12 seconds
Started	Apr 23 04:47:46 PM PDT 24
Finished	Apr 23 04:47:52 PM PDT 24
Peak memory	562716 kb
Host	smart-6e2d105f-6fe3-4de8-addd-7853a6ac3c53
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287954755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.2287954755
Directory	/workspace/80.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all.604027874
Short name	T1877
Test name
Test status
Simulation time	931297714 ps
CPU time	41.69 seconds
Started	Apr 23 04:47:53 PM PDT 24
Finished	Apr 23 04:48:35 PM PDT 24
Peak memory	562728 kb
Host	smart-f6ed183b-a794-42e4-85b5-30aa2449973c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604027874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.604027874
Directory	/workspace/80.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2654374593
Short name	T1239
Test name
Test status
Simulation time	4357762740 ps
CPU time	163.79 seconds
Started	Apr 23 04:47:54 PM PDT 24
Finished	Apr 23 04:50:38 PM PDT 24
Peak memory	562892 kb
Host	smart-6178f485-b040-4e98-870f-c8c2599108e9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654374593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2654374593
Directory	/workspace/80.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2945784803
Short name	T2188
Test name
Test status
Simulation time	558492502 ps
CPU time	217.01 seconds
Started	Apr 23 04:47:51 PM PDT 24
Finished	Apr 23 04:51:28 PM PDT 24
Peak memory	572144 kb
Host	smart-34ac8b93-87e9-4cc9-8e07-c8d8a0e51c80
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945784803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2945784803
Directory	/workspace/80.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1568598811
Short name	T2638
Test name
Test status
Simulation time	10225922714 ps
CPU time	412.69 seconds
Started	Apr 23 04:47:52 PM PDT 24
Finished	Apr 23 04:54:45 PM PDT 24
Peak memory	572208 kb
Host	smart-07260368-74e9-448b-b16f-88ffc15a91e2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568598811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.1568598811
Directory	/workspace/80.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.2820438098
Short name	T1628
Test name
Test status
Simulation time	773840172 ps
CPU time	35.23 seconds
Started	Apr 23 04:47:51 PM PDT 24
Finished	Apr 23 04:48:27 PM PDT 24
Peak memory	562776 kb
Host	smart-0abd2362-6121-48e7-8d1f-7a8b11dc9a98
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820438098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.2820438098
Directory	/workspace/80.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_access_same_device.759946822
Short name	T431
Test name
Test status
Simulation time	2755535232 ps
CPU time	105.7 seconds
Started	Apr 23 04:47:57 PM PDT 24
Finished	Apr 23 04:49:42 PM PDT 24
Peak memory	562848 kb
Host	smart-fd69b8f8-5b78-455e-9031-617e3c93fbd6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759946822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device. 759946822
Directory	/workspace/81.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3950656592
Short name	T1561
Test name
Test status
Simulation time	72574588136 ps
CPU time	1289.77 seconds
Started	Apr 23 04:48:06 PM PDT 24
Finished	Apr 23 05:09:36 PM PDT 24
Peak memory	562872 kb
Host	smart-f89bb287-4c44-40a6-940d-e8e01cef12c8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950656592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3950656592
Directory	/workspace/81.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.476018878
Short name	T2671
Test name
Test status
Simulation time	178977869 ps
CPU time	9.9 seconds
Started	Apr 23 04:48:01 PM PDT 24
Finished	Apr 23 04:48:11 PM PDT 24
Peak memory	562740 kb
Host	smart-05ff1178-996a-49ef-850e-31b6bccb234d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476018878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr .476018878
Directory	/workspace/81.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_error_random.3760791443
Short name	T2584
Test name
Test status
Simulation time	90134815 ps
CPU time	10.89 seconds
Started	Apr 23 04:47:59 PM PDT 24
Finished	Apr 23 04:48:10 PM PDT 24
Peak memory	562692 kb
Host	smart-6d26a752-88d0-4c76-a0c3-17acdf6d39aa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760791443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.3760791443
Directory	/workspace/81.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_random.235634775
Short name	T1882
Test name
Test status
Simulation time	683409362 ps
CPU time	25.41 seconds
Started	Apr 23 04:47:52 PM PDT 24
Finished	Apr 23 04:48:18 PM PDT 24
Peak memory	562668 kb
Host	smart-cc815be3-c85c-48c2-8e6b-6015fcb4d1cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235634775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.235634775
Directory	/workspace/81.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_random_large_delays.1644933388
Short name	T2682
Test name
Test status
Simulation time	4691979184 ps
CPU time	52.83 seconds
Started	Apr 23 04:48:06 PM PDT 24
Finished	Apr 23 04:48:59 PM PDT 24
Peak memory	562792 kb
Host	smart-4b1da10d-e843-450e-86f8-ee8a24f680ad
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644933388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.1644933388
Directory	/workspace/81.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.1000477847
Short name	T530
Test name
Test status
Simulation time	67096588012 ps
CPU time	1266.62 seconds
Started	Apr 23 04:47:57 PM PDT 24
Finished	Apr 23 05:09:03 PM PDT 24
Peak memory	562820 kb
Host	smart-52e90cb8-e668-4a4a-8119-fe62757e21ad
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000477847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.1000477847
Directory	/workspace/81.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.1007320082
Short name	T1585
Test name
Test status
Simulation time	434329870 ps
CPU time	42.32 seconds
Started	Apr 23 04:47:54 PM PDT 24
Finished	Apr 23 04:48:36 PM PDT 24
Peak memory	562704 kb
Host	smart-3643be6a-29fb-4195-b321-281b13c378f8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007320082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.1007320082
Directory	/workspace/81.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_same_source.2607037137
Short name	T1733
Test name
Test status
Simulation time	289129353 ps
CPU time	23.19 seconds
Started	Apr 23 04:47:59 PM PDT 24
Finished	Apr 23 04:48:22 PM PDT 24
Peak memory	562716 kb
Host	smart-7ce38f74-21be-4daa-89a8-2d056529ab27
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607037137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2607037137
Directory	/workspace/81.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke.4186178793
Short name	T1312
Test name
Test status
Simulation time	49208049 ps
CPU time	6.53 seconds
Started	Apr 23 04:48:04 PM PDT 24
Finished	Apr 23 04:48:11 PM PDT 24
Peak memory	562700 kb
Host	smart-cacbb79f-bf50-4f3e-8100-8d4e83625eb0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186178793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.4186178793
Directory	/workspace/81.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1375835391
Short name	T568
Test name
Test status
Simulation time	7240785773 ps
CPU time	85.4 seconds
Started	Apr 23 04:47:53 PM PDT 24
Finished	Apr 23 04:49:19 PM PDT 24
Peak memory	562772 kb
Host	smart-c330cda6-887b-427e-8738-fe05ea10d680
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375835391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1375835391
Directory	/workspace/81.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.4120777890
Short name	T1710
Test name
Test status
Simulation time	4146996678 ps
CPU time	74.17 seconds
Started	Apr 23 04:47:54 PM PDT 24
Finished	Apr 23 04:49:09 PM PDT 24
Peak memory	562776 kb
Host	smart-6ea2e0a1-73dc-4858-9dbb-42fc5317ca5b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120777890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.4120777890
Directory	/workspace/81.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3671816359
Short name	T1772
Test name
Test status
Simulation time	51544070 ps
CPU time	7.12 seconds
Started	Apr 23 04:47:55 PM PDT 24
Finished	Apr 23 04:48:02 PM PDT 24
Peak memory	562724 kb
Host	smart-17e8e9c6-226e-4e08-868e-ae32971a6784
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671816359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.3671816359
Directory	/workspace/81.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all.4199023069
Short name	T560
Test name
Test status
Simulation time	3192378025 ps
CPU time	246.58 seconds
Started	Apr 23 04:48:02 PM PDT 24
Finished	Apr 23 04:52:09 PM PDT 24
Peak memory	563956 kb
Host	smart-4a5b05ac-e01c-4032-9bab-55b50b04fcf1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199023069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.4199023069
Directory	/workspace/81.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1556774520
Short name	T1553
Test name
Test status
Simulation time	459360832 ps
CPU time	42.08 seconds
Started	Apr 23 04:48:03 PM PDT 24
Finished	Apr 23 04:48:45 PM PDT 24
Peak memory	562780 kb
Host	smart-c379106b-44d9-42d3-af82-d3cb9e5ab579
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556774520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1556774520
Directory	/workspace/81.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3140568610
Short name	T1562
Test name
Test status
Simulation time	224089198 ps
CPU time	53.56 seconds
Started	Apr 23 04:48:05 PM PDT 24
Finished	Apr 23 04:48:58 PM PDT 24
Peak memory	563860 kb
Host	smart-28eabc41-c4fe-45e2-b77f-bb87ae643e9b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140568610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.3140568610
Directory	/workspace/81.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1910919807
Short name	T812
Test name
Test status
Simulation time	592080023 ps
CPU time	123.35 seconds
Started	Apr 23 04:48:06 PM PDT 24
Finished	Apr 23 04:50:10 PM PDT 24
Peak memory	572100 kb
Host	smart-a6825a29-6f73-44e1-b708-6cdfa415df6c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910919807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.1910919807
Directory	/workspace/81.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.343478282
Short name	T2124
Test name
Test status
Simulation time	1170123677 ps
CPU time	49.17 seconds
Started	Apr 23 04:48:02 PM PDT 24
Finished	Apr 23 04:48:51 PM PDT 24
Peak memory	562708 kb
Host	smart-65b5e609-253f-4d5f-bdb1-a03bfc382df0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343478282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.343478282
Directory	/workspace/81.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_access_same_device.826613589
Short name	T2142
Test name
Test status
Simulation time	2959768791 ps
CPU time	117 seconds
Started	Apr 23 04:48:02 PM PDT 24
Finished	Apr 23 04:50:00 PM PDT 24
Peak memory	562860 kb
Host	smart-2db2b735-a7a0-4ae2-a581-23e13777a1d7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826613589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device. 826613589
Directory	/workspace/82.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.4148925582
Short name	T2085
Test name
Test status
Simulation time	6241773907 ps
CPU time	108.34 seconds
Started	Apr 23 04:48:03 PM PDT 24
Finished	Apr 23 04:49:52 PM PDT 24
Peak memory	562824 kb
Host	smart-160afbfd-95e6-4716-aecf-5218a5684029
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148925582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.4148925582
Directory	/workspace/82.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2638155733
Short name	T1475
Test name
Test status
Simulation time	481866642 ps
CPU time	22.81 seconds
Started	Apr 23 04:48:08 PM PDT 24
Finished	Apr 23 04:48:31 PM PDT 24
Peak memory	562700 kb
Host	smart-d65c47a8-7b77-4bc8-a167-38624ac4fe02
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638155733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.2638155733
Directory	/workspace/82.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_error_random.4262988524
Short name	T2278
Test name
Test status
Simulation time	309084246 ps
CPU time	27.72 seconds
Started	Apr 23 04:48:08 PM PDT 24
Finished	Apr 23 04:48:36 PM PDT 24
Peak memory	562740 kb
Host	smart-f3d3d121-b0a3-40b6-a9fc-bfc7005f7576
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262988524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.4262988524
Directory	/workspace/82.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_random.2721956484
Short name	T2166
Test name
Test status
Simulation time	292887334 ps
CPU time	24.25 seconds
Started	Apr 23 04:48:03 PM PDT 24
Finished	Apr 23 04:48:27 PM PDT 24
Peak memory	562740 kb
Host	smart-4e85b1ee-8711-4628-b2c1-a67180d4eda8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721956484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.2721956484
Directory	/workspace/82.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2975687862
Short name	T2549
Test name
Test status
Simulation time	116625573736 ps
CPU time	1242.36 seconds
Started	Apr 23 04:48:05 PM PDT 24
Finished	Apr 23 05:08:47 PM PDT 24
Peak memory	562836 kb
Host	smart-818e2a34-fa95-45a7-89e8-1782e8815f65
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975687862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.2975687862
Directory	/workspace/82.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.3599469309
Short name	T2214
Test name
Test status
Simulation time	6548439736 ps
CPU time	119.88 seconds
Started	Apr 23 04:48:03 PM PDT 24
Finished	Apr 23 04:50:03 PM PDT 24
Peak memory	562772 kb
Host	smart-279d12b3-7385-4783-bf99-1f70c21d8682
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599469309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.3599469309
Directory	/workspace/82.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.4058671199
Short name	T2534
Test name
Test status
Simulation time	317770867 ps
CPU time	31.28 seconds
Started	Apr 23 04:48:06 PM PDT 24
Finished	Apr 23 04:48:37 PM PDT 24
Peak memory	562716 kb
Host	smart-1f78abca-2026-41fe-98d6-67d2632e2569
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058671199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.4058671199
Directory	/workspace/82.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_same_source.1855623785
Short name	T2028
Test name
Test status
Simulation time	2265955647 ps
CPU time	74.03 seconds
Started	Apr 23 04:48:08 PM PDT 24
Finished	Apr 23 04:49:22 PM PDT 24
Peak memory	562740 kb
Host	smart-5a4df732-24d0-4345-90a2-0ac75b156f38
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855623785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1855623785
Directory	/workspace/82.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke.16345577
Short name	T2795
Test name
Test status
Simulation time	218090770 ps
CPU time	9.9 seconds
Started	Apr 23 04:48:06 PM PDT 24
Finished	Apr 23 04:48:16 PM PDT 24
Peak memory	562692 kb
Host	smart-45a669fd-7213-4806-b340-443db67360fd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16345577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.16345577
Directory	/workspace/82.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.748530011
Short name	T1813
Test name
Test status
Simulation time	7730150375 ps
CPU time	83.36 seconds
Started	Apr 23 04:48:07 PM PDT 24
Finished	Apr 23 04:49:30 PM PDT 24
Peak memory	562776 kb
Host	smart-f27ff63c-1ac6-4f20-93ef-223eaa16abb7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748530011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.748530011
Directory	/workspace/82.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.4110733246
Short name	T1265
Test name
Test status
Simulation time	5899140668 ps
CPU time	108.46 seconds
Started	Apr 23 04:48:04 PM PDT 24
Finished	Apr 23 04:49:52 PM PDT 24
Peak memory	562744 kb
Host	smart-9145b2bb-3e1a-46c2-92f6-144285937d5b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110733246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.4110733246
Directory	/workspace/82.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.786103025
Short name	T1241
Test name
Test status
Simulation time	41685612 ps
CPU time	5.57 seconds
Started	Apr 23 04:48:03 PM PDT 24
Finished	Apr 23 04:48:08 PM PDT 24
Peak memory	562636 kb
Host	smart-f8288c7c-1e15-45e6-8f19-d30be30b6715
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786103025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays .786103025
Directory	/workspace/82.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all.2384262280
Short name	T1865
Test name
Test status
Simulation time	3150433930 ps
CPU time	130.37 seconds
Started	Apr 23 04:48:11 PM PDT 24
Finished	Apr 23 04:50:22 PM PDT 24
Peak memory	563044 kb
Host	smart-d1287767-b0f9-4b80-8b5e-11514acba049
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384262280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2384262280
Directory	/workspace/82.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1201672270
Short name	T2400
Test name
Test status
Simulation time	2959633236 ps
CPU time	252.37 seconds
Started	Apr 23 04:48:10 PM PDT 24
Finished	Apr 23 04:52:23 PM PDT 24
Peak memory	562944 kb
Host	smart-808f1100-32f1-4a1b-9109-55d1764d1c48
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201672270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.1201672270
Directory	/workspace/82.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2326421621
Short name	T1753
Test name
Test status
Simulation time	6808724395 ps
CPU time	715.1 seconds
Started	Apr 23 04:48:12 PM PDT 24
Finished	Apr 23 05:00:08 PM PDT 24
Peak memory	572188 kb
Host	smart-76ce4c76-ec2b-450e-982f-d2a6ce39969e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326421621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.2326421621
Directory	/workspace/82.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2663735148
Short name	T1795
Test name
Test status
Simulation time	67937535 ps
CPU time	12.26 seconds
Started	Apr 23 04:48:13 PM PDT 24
Finished	Apr 23 04:48:26 PM PDT 24
Peak memory	562780 kb
Host	smart-b9220b9a-fbed-4e4b-bae8-241120433561
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663735148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.2663735148
Directory	/workspace/82.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.3150096733
Short name	T2391
Test name
Test status
Simulation time	1351654979 ps
CPU time	62.77 seconds
Started	Apr 23 04:48:06 PM PDT 24
Finished	Apr 23 04:49:09 PM PDT 24
Peak memory	562788 kb
Host	smart-b0f2cacc-8d65-443c-9f0e-483de075e324
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150096733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.3150096733
Directory	/workspace/82.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_access_same_device.112666118
Short name	T677
Test name
Test status
Simulation time	1100969301 ps
CPU time	43.01 seconds
Started	Apr 23 04:48:18 PM PDT 24
Finished	Apr 23 04:49:01 PM PDT 24
Peak memory	562760 kb
Host	smart-8e5df974-9381-41f0-8ce6-b112e1dbcb30
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112666118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device. 112666118
Directory	/workspace/83.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.493413227
Short name	T1538
Test name
Test status
Simulation time	12984626968 ps
CPU time	235.88 seconds
Started	Apr 23 04:48:17 PM PDT 24
Finished	Apr 23 04:52:13 PM PDT 24
Peak memory	562820 kb
Host	smart-1cb149b4-5c3d-420b-82a7-5d6711477137
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493413227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_d evice_slow_rsp.493413227
Directory	/workspace/83.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2884926788
Short name	T1969
Test name
Test status
Simulation time	60956568 ps
CPU time	9.12 seconds
Started	Apr 23 04:48:16 PM PDT 24
Finished	Apr 23 04:48:25 PM PDT 24
Peak memory	562732 kb
Host	smart-054a6af0-7a4e-443c-86e2-9cad772700ce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884926788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.2884926788
Directory	/workspace/83.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_error_random.1392878467
Short name	T2448
Test name
Test status
Simulation time	30254672 ps
CPU time	5.67 seconds
Started	Apr 23 04:48:23 PM PDT 24
Finished	Apr 23 04:48:29 PM PDT 24
Peak memory	562684 kb
Host	smart-d0de2bc3-c3bc-4bd9-801c-7d16c2502572
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392878467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.1392878467
Directory	/workspace/83.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_random.678569978
Short name	T1902
Test name
Test status
Simulation time	1435057056 ps
CPU time	51.69 seconds
Started	Apr 23 04:48:15 PM PDT 24
Finished	Apr 23 04:49:07 PM PDT 24
Peak memory	562752 kb
Host	smart-dbb4b3c7-b824-4bf7-a07b-4db5743f5693
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678569978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.678569978
Directory	/workspace/83.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_random_large_delays.799376565
Short name	T2655
Test name
Test status
Simulation time	115386555376 ps
CPU time	1173.95 seconds
Started	Apr 23 04:48:24 PM PDT 24
Finished	Apr 23 05:07:58 PM PDT 24
Peak memory	562804 kb
Host	smart-2a0f7b61-34f8-464a-ada2-a6dc1e1b8750
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799376565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.799376565
Directory	/workspace/83.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.511851393
Short name	T2335
Test name
Test status
Simulation time	27385228643 ps
CPU time	525.74 seconds
Started	Apr 23 04:48:16 PM PDT 24
Finished	Apr 23 04:57:02 PM PDT 24
Peak memory	562740 kb
Host	smart-4a3204d7-ef56-4ff8-a9e1-f91a56efdf82
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511851393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.511851393
Directory	/workspace/83.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1947781202
Short name	T1909
Test name
Test status
Simulation time	457859402 ps
CPU time	46.09 seconds
Started	Apr 23 04:48:14 PM PDT 24
Finished	Apr 23 04:49:01 PM PDT 24
Peak memory	562744 kb
Host	smart-f197ae27-d4d2-402d-a7af-d37de6d87deb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947781202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1947781202
Directory	/workspace/83.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_same_source.1801525656
Short name	T1683
Test name
Test status
Simulation time	562573176 ps
CPU time	44.36 seconds
Started	Apr 23 04:48:19 PM PDT 24
Finished	Apr 23 04:49:04 PM PDT 24
Peak memory	562744 kb
Host	smart-9f6a4267-2ff0-4a39-8fe9-3a1fbc5afdd3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801525656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1801525656
Directory	/workspace/83.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke.75510277
Short name	T2211
Test name
Test status
Simulation time	178992729 ps
CPU time	8.71 seconds
Started	Apr 23 04:48:10 PM PDT 24
Finished	Apr 23 04:48:19 PM PDT 24
Peak memory	562720 kb
Host	smart-b2762329-cd32-4875-9f28-2d3c424cad1b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75510277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.75510277
Directory	/workspace/83.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.172301405
Short name	T1253
Test name
Test status
Simulation time	8402350485 ps
CPU time	92.54 seconds
Started	Apr 23 04:48:13 PM PDT 24
Finished	Apr 23 04:49:46 PM PDT 24
Peak memory	562796 kb
Host	smart-8c2a3682-b035-4f62-867a-c18bacea1e58
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172301405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.172301405
Directory	/workspace/83.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1804809708
Short name	T1926
Test name
Test status
Simulation time	6361923713 ps
CPU time	118.51 seconds
Started	Apr 23 04:48:14 PM PDT 24
Finished	Apr 23 04:50:13 PM PDT 24
Peak memory	562744 kb
Host	smart-b8567de0-9e7e-4c09-9bca-b3f5363c1735
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804809708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.1804809708
Directory	/workspace/83.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1161827467
Short name	T1786
Test name
Test status
Simulation time	55053217 ps
CPU time	7.26 seconds
Started	Apr 23 04:48:14 PM PDT 24
Finished	Apr 23 04:48:22 PM PDT 24
Peak memory	562700 kb
Host	smart-0cf6937c-eaef-4f4a-967a-fb8dde23b610
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161827467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.1161827467
Directory	/workspace/83.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all.1174387507
Short name	T1684
Test name
Test status
Simulation time	8871232755 ps
CPU time	364.02 seconds
Started	Apr 23 04:48:17 PM PDT 24
Finished	Apr 23 04:54:21 PM PDT 24
Peak memory	563824 kb
Host	smart-89376044-dcba-427f-8ca3-77e07d7f9abb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174387507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.1174387507
Directory	/workspace/83.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3167964748
Short name	T2724
Test name
Test status
Simulation time	3695541930 ps
CPU time	143.3 seconds
Started	Apr 23 04:48:23 PM PDT 24
Finished	Apr 23 04:50:47 PM PDT 24
Peak memory	562820 kb
Host	smart-da5a626b-07e0-483a-b358-162cb5a06b39
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167964748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3167964748
Directory	/workspace/83.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.892712944
Short name	T1529
Test name
Test status
Simulation time	255755230 ps
CPU time	133.88 seconds
Started	Apr 23 04:48:18 PM PDT 24
Finished	Apr 23 04:50:32 PM PDT 24
Peak memory	572136 kb
Host	smart-61fb7144-2eb8-4fe5-99ef-fe413bdf9576
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892712944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_rand_reset.892712944
Directory	/workspace/83.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.1116895234
Short name	T767
Test name
Test status
Simulation time	10554508170 ps
CPU time	504.58 seconds
Started	Apr 23 04:48:25 PM PDT 24
Finished	Apr 23 04:56:50 PM PDT 24
Peak memory	572128 kb
Host	smart-f30b7245-bb87-4fe5-bd31-34befe078ced
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116895234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.1116895234
Directory	/workspace/83.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.2960898692
Short name	T2323
Test name
Test status
Simulation time	35748077 ps
CPU time	8.04 seconds
Started	Apr 23 04:48:23 PM PDT 24
Finished	Apr 23 04:48:31 PM PDT 24
Peak memory	562748 kb
Host	smart-495415fd-f193-4837-9697-0bfb45a3d396
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960898692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.2960898692
Directory	/workspace/83.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_access_same_device.724448827
Short name	T641
Test name
Test status
Simulation time	647469722 ps
CPU time	32.15 seconds
Started	Apr 23 04:48:28 PM PDT 24
Finished	Apr 23 04:49:00 PM PDT 24
Peak memory	562748 kb
Host	smart-c26894db-f4b0-4b97-ab48-39d1c66c0833
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724448827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device. 724448827
Directory	/workspace/84.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.202903866
Short name	T2315
Test name
Test status
Simulation time	127240299757 ps
CPU time	2229.1 seconds
Started	Apr 23 04:48:28 PM PDT 24
Finished	Apr 23 05:25:37 PM PDT 24
Peak memory	562820 kb
Host	smart-212f7629-608f-49ae-896d-24a7521c99a1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202903866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_d evice_slow_rsp.202903866
Directory	/workspace/84.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3642430240
Short name	T2064
Test name
Test status
Simulation time	17069654 ps
CPU time	5.03 seconds
Started	Apr 23 04:48:34 PM PDT 24
Finished	Apr 23 04:48:39 PM PDT 24
Peak memory	562696 kb
Host	smart-07758aa3-12e6-45b3-a36d-1871ee8a48c3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642430240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.3642430240
Directory	/workspace/84.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_error_random.886730682
Short name	T1496
Test name
Test status
Simulation time	861092372 ps
CPU time	31.99 seconds
Started	Apr 23 04:48:32 PM PDT 24
Finished	Apr 23 04:49:04 PM PDT 24
Peak memory	562716 kb
Host	smart-e4a107ab-d0a9-47a6-bcca-42d646b57e2e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886730682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.886730682
Directory	/workspace/84.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_random.3058675362
Short name	T433
Test name
Test status
Simulation time	1296436774 ps
CPU time	54.55 seconds
Started	Apr 23 04:48:27 PM PDT 24
Finished	Apr 23 04:49:22 PM PDT 24
Peak memory	562756 kb
Host	smart-9b40037e-286a-4d01-93c1-f89985981e59
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058675362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.3058675362
Directory	/workspace/84.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1704849248
Short name	T1519
Test name
Test status
Simulation time	66067922998 ps
CPU time	760.29 seconds
Started	Apr 23 04:48:32 PM PDT 24
Finished	Apr 23 05:01:13 PM PDT 24
Peak memory	562848 kb
Host	smart-6725d5ec-d12f-4b15-8a79-b784c6a0718a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704849248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1704849248
Directory	/workspace/84.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3284467349
Short name	T2457
Test name
Test status
Simulation time	66240374650 ps
CPU time	1284.68 seconds
Started	Apr 23 04:48:30 PM PDT 24
Finished	Apr 23 05:09:55 PM PDT 24
Peak memory	562764 kb
Host	smart-49ea304e-9801-47fa-9a78-4547f5a1267f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284467349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3284467349
Directory	/workspace/84.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.755021983
Short name	T1631
Test name
Test status
Simulation time	375148251 ps
CPU time	35.69 seconds
Started	Apr 23 04:48:28 PM PDT 24
Finished	Apr 23 04:49:04 PM PDT 24
Peak memory	562752 kb
Host	smart-053f2904-0bbd-4459-8d6c-f1860ae59f03
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755021983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela ys.755021983
Directory	/workspace/84.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_same_source.899598452
Short name	T2547
Test name
Test status
Simulation time	1361084768 ps
CPU time	45.21 seconds
Started	Apr 23 04:48:29 PM PDT 24
Finished	Apr 23 04:49:15 PM PDT 24
Peak memory	562728 kb
Host	smart-bacc6094-7bd4-4c5a-850a-3acaa2dba907
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899598452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.899598452
Directory	/workspace/84.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke.562660100
Short name	T1249
Test name
Test status
Simulation time	49415345 ps
CPU time	7.48 seconds
Started	Apr 23 04:48:20 PM PDT 24
Finished	Apr 23 04:48:28 PM PDT 24
Peak memory	562692 kb
Host	smart-ff207cd2-9af2-4b9e-8e32-a8c499f35d72
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562660100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.562660100
Directory	/workspace/84.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.773305070
Short name	T2050
Test name
Test status
Simulation time	10263451842 ps
CPU time	114.39 seconds
Started	Apr 23 04:48:29 PM PDT 24
Finished	Apr 23 04:50:24 PM PDT 24
Peak memory	562804 kb
Host	smart-4e45dbe4-97ec-4686-b6e5-be264d326886
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773305070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.773305070
Directory	/workspace/84.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.2369536769
Short name	T1259
Test name
Test status
Simulation time	6546754139 ps
CPU time	119.62 seconds
Started	Apr 23 04:48:27 PM PDT 24
Finished	Apr 23 04:50:27 PM PDT 24
Peak memory	562720 kb
Host	smart-d59da46c-5e4a-4bc7-b363-e7ff57b28734
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369536769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.2369536769
Directory	/workspace/84.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.632749811
Short name	T1781
Test name
Test status
Simulation time	40782829 ps
CPU time	6.04 seconds
Started	Apr 23 04:48:23 PM PDT 24
Finished	Apr 23 04:48:29 PM PDT 24
Peak memory	562692 kb
Host	smart-31072302-a6e5-427e-bf01-7368beb0ef8e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632749811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays .632749811
Directory	/workspace/84.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all.2789677269
Short name	T2027
Test name
Test status
Simulation time	17560260732 ps
CPU time	710.79 seconds
Started	Apr 23 04:48:33 PM PDT 24
Finished	Apr 23 05:00:24 PM PDT 24
Peak memory	572136 kb
Host	smart-871ece82-5455-41cf-989d-bda8a93b45fd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789677269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2789677269
Directory	/workspace/84.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2844456193
Short name	T624
Test name
Test status
Simulation time	9385461728 ps
CPU time	344.61 seconds
Started	Apr 23 04:48:33 PM PDT 24
Finished	Apr 23 04:54:18 PM PDT 24
Peak memory	563976 kb
Host	smart-14bc8ef5-f7d3-405c-aabe-9722b13f2589
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844456193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2844456193
Directory	/workspace/84.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2665409367
Short name	T829
Test name
Test status
Simulation time	880970067 ps
CPU time	132.47 seconds
Started	Apr 23 04:48:37 PM PDT 24
Finished	Apr 23 04:50:49 PM PDT 24
Peak memory	572132 kb
Host	smart-69d7013f-86cf-481a-8f99-cc21e19df32b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665409367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2665409367
Directory	/workspace/84.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.4019393210
Short name	T1366
Test name
Test status
Simulation time	157013510 ps
CPU time	21.43 seconds
Started	Apr 23 04:48:30 PM PDT 24
Finished	Apr 23 04:48:52 PM PDT 24
Peak memory	562776 kb
Host	smart-ff2ace78-c16f-4127-b6af-d249b190447b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019393210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.4019393210
Directory	/workspace/84.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_access_same_device.754867780
Short name	T786
Test name
Test status
Simulation time	307392410 ps
CPU time	16.32 seconds
Started	Apr 23 04:48:47 PM PDT 24
Finished	Apr 23 04:49:04 PM PDT 24
Peak memory	561896 kb
Host	smart-2f8b4590-b5d6-49e4-92aa-cf4f6139b0ba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754867780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device. 754867780
Directory	/workspace/85.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1327809143
Short name	T466
Test name
Test status
Simulation time	31885687161 ps
CPU time	583.7 seconds
Started	Apr 23 04:48:44 PM PDT 24
Finished	Apr 23 04:58:28 PM PDT 24
Peak memory	562864 kb
Host	smart-d9cd3ab4-ebb7-478f-874e-3e4e09b115b1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327809143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.1327809143
Directory	/workspace/85.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1209122566
Short name	T1604
Test name
Test status
Simulation time	124221695 ps
CPU time	15.02 seconds
Started	Apr 23 04:48:48 PM PDT 24
Finished	Apr 23 04:49:04 PM PDT 24
Peak memory	561884 kb
Host	smart-8a3fccb4-99cb-49a2-9188-38a463f6b1b4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209122566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1209122566
Directory	/workspace/85.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_error_random.414933696
Short name	T558
Test name
Test status
Simulation time	255009566 ps
CPU time	23.95 seconds
Started	Apr 23 04:48:43 PM PDT 24
Finished	Apr 23 04:49:08 PM PDT 24
Peak memory	562680 kb
Host	smart-598b6d3f-4179-4e80-84b4-f0f93ab2e5f5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414933696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.414933696
Directory	/workspace/85.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_random.418536703
Short name	T2165
Test name
Test status
Simulation time	2522766216 ps
CPU time	86.09 seconds
Started	Apr 23 04:48:47 PM PDT 24
Finished	Apr 23 04:50:14 PM PDT 24
Peak memory	561988 kb
Host	smart-d9ecab45-a511-44d0-88e7-6813f29101ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418536703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.418536703
Directory	/workspace/85.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_random_large_delays.3676545805
Short name	T2643
Test name
Test status
Simulation time	103019774579 ps
CPU time	1115.77 seconds
Started	Apr 23 04:48:40 PM PDT 24
Finished	Apr 23 05:07:16 PM PDT 24
Peak memory	562792 kb
Host	smart-7827ebdf-206f-4e1f-90a0-8812a044ac39
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676545805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.3676545805
Directory	/workspace/85.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.672042032
Short name	T2516
Test name
Test status
Simulation time	11193839444 ps
CPU time	203.66 seconds
Started	Apr 23 04:48:40 PM PDT 24
Finished	Apr 23 04:52:05 PM PDT 24
Peak memory	562724 kb
Host	smart-b2046dfb-8cb2-4b31-a08d-f7e525fb6367
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672042032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.672042032
Directory	/workspace/85.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3762990487
Short name	T1836
Test name
Test status
Simulation time	530659329 ps
CPU time	50.82 seconds
Started	Apr 23 04:48:39 PM PDT 24
Finished	Apr 23 04:49:30 PM PDT 24
Peak memory	562712 kb
Host	smart-150f680f-1fa7-4eba-aa19-8f7aea4fc439
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762990487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.3762990487
Directory	/workspace/85.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_same_source.2181911291
Short name	T1981
Test name
Test status
Simulation time	2162491271 ps
CPU time	62.7 seconds
Started	Apr 23 04:48:48 PM PDT 24
Finished	Apr 23 04:49:51 PM PDT 24
Peak memory	561960 kb
Host	smart-a45cc400-a3df-4e09-89f8-6d5e91ab3023
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181911291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.2181911291
Directory	/workspace/85.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke.1368938461
Short name	T2118
Test name
Test status
Simulation time	180915627 ps
CPU time	8.39 seconds
Started	Apr 23 04:48:33 PM PDT 24
Finished	Apr 23 04:48:42 PM PDT 24
Peak memory	562676 kb
Host	smart-aa4363f7-0edc-4901-8102-2f8be5a4c0cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368938461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1368938461
Directory	/workspace/85.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2746086523
Short name	T1867
Test name
Test status
Simulation time	6203727193 ps
CPU time	71.11 seconds
Started	Apr 23 04:48:35 PM PDT 24
Finished	Apr 23 04:49:47 PM PDT 24
Peak memory	562800 kb
Host	smart-25cab637-c775-4829-9abd-36de479f38ea
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746086523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2746086523
Directory	/workspace/85.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.29553844
Short name	T2635
Test name
Test status
Simulation time	4665419551 ps
CPU time	83.27 seconds
Started	Apr 23 04:48:37 PM PDT 24
Finished	Apr 23 04:50:00 PM PDT 24
Peak memory	562796 kb
Host	smart-ef5086d4-1cbf-4ef2-9531-b5297be10660
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29553844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.29553844
Directory	/workspace/85.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.1128735485
Short name	T2148
Test name
Test status
Simulation time	46241814 ps
CPU time	5.71 seconds
Started	Apr 23 04:48:37 PM PDT 24
Finished	Apr 23 04:48:43 PM PDT 24
Peak memory	562720 kb
Host	smart-bf4efeab-a392-40cb-a3c6-6800c3f47dc3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128735485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.1128735485
Directory	/workspace/85.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all.4141110964
Short name	T2759
Test name
Test status
Simulation time	14184134631 ps
CPU time	530.33 seconds
Started	Apr 23 04:48:41 PM PDT 24
Finished	Apr 23 04:57:32 PM PDT 24
Peak memory	563984 kb
Host	smart-658aff93-452f-4eee-a4c3-be5c3bba2ba0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141110964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.4141110964
Directory	/workspace/85.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.332364855
Short name	T789
Test name
Test status
Simulation time	1744615118 ps
CPU time	139.79 seconds
Started	Apr 23 04:48:45 PM PDT 24
Finished	Apr 23 04:51:05 PM PDT 24
Peak memory	562756 kb
Host	smart-4f2e2a7f-5f03-4e5d-8a73-fdc256adcd7b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332364855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.332364855
Directory	/workspace/85.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1002333667
Short name	T1510
Test name
Test status
Simulation time	701651201 ps
CPU time	237.82 seconds
Started	Apr 23 04:48:42 PM PDT 24
Finished	Apr 23 04:52:40 PM PDT 24
Peak memory	572120 kb
Host	smart-a1d545c2-f4c4-4049-8817-88920f84443b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002333667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.1002333667
Directory	/workspace/85.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2678021723
Short name	T2168
Test name
Test status
Simulation time	589547512 ps
CPU time	192.82 seconds
Started	Apr 23 04:48:47 PM PDT 24
Finished	Apr 23 04:52:00 PM PDT 24
Peak memory	572124 kb
Host	smart-92ae81df-f2b7-42d7-8498-f3cb4bbc1c8f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678021723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.2678021723
Directory	/workspace/85.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.152468695
Short name	T1246
Test name
Test status
Simulation time	100271510 ps
CPU time	12.75 seconds
Started	Apr 23 04:48:41 PM PDT 24
Finished	Apr 23 04:48:55 PM PDT 24
Peak memory	562776 kb
Host	smart-a0ac303c-3a0b-40cf-8e71-a38f7d99a184
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152468695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.152468695
Directory	/workspace/85.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_access_same_device.2030431370
Short name	T759
Test name
Test status
Simulation time	1971863661 ps
CPU time	86.41 seconds
Started	Apr 23 04:48:46 PM PDT 24
Finished	Apr 23 04:50:13 PM PDT 24
Peak memory	562764 kb
Host	smart-32806a18-f6f7-49d5-ae7e-8d138e4c8f17
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030431370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .2030431370
Directory	/workspace/86.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3421930601
Short name	T796
Test name
Test status
Simulation time	121820481509 ps
CPU time	2046.13 seconds
Started	Apr 23 04:48:55 PM PDT 24
Finished	Apr 23 05:23:01 PM PDT 24
Peak memory	562924 kb
Host	smart-aa2bc49b-387d-4039-a49a-584908c95a18
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421930601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.3421930601
Directory	/workspace/86.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.987474395
Short name	T2009
Test name
Test status
Simulation time	330996466 ps
CPU time	34.18 seconds
Started	Apr 23 04:48:54 PM PDT 24
Finished	Apr 23 04:49:28 PM PDT 24
Peak memory	562696 kb
Host	smart-5d75bacf-8d0a-4d53-b739-0b76ba38fba3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987474395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr .987474395
Directory	/workspace/86.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_error_random.4116348871
Short name	T1283
Test name
Test status
Simulation time	196500876 ps
CPU time	16.98 seconds
Started	Apr 23 04:48:55 PM PDT 24
Finished	Apr 23 04:49:12 PM PDT 24
Peak memory	562716 kb
Host	smart-fbd7c956-f44d-4152-a311-706f87b05114
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116348871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.4116348871
Directory	/workspace/86.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_random.173054783
Short name	T2318
Test name
Test status
Simulation time	297135116 ps
CPU time	15.31 seconds
Started	Apr 23 04:48:48 PM PDT 24
Finished	Apr 23 04:49:04 PM PDT 24
Peak memory	562700 kb
Host	smart-d39661e2-1377-4ef6-b29b-73cd6f06677d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173054783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.173054783
Directory	/workspace/86.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_random_large_delays.4077898843
Short name	T1359
Test name
Test status
Simulation time	24310118967 ps
CPU time	271.6 seconds
Started	Apr 23 04:48:46 PM PDT 24
Finished	Apr 23 04:53:17 PM PDT 24
Peak memory	562740 kb
Host	smart-2178f8f1-8bb5-4c68-84e8-d11f9caa4e87
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077898843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.4077898843
Directory	/workspace/86.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.3580719957
Short name	T1427
Test name
Test status
Simulation time	49205643613 ps
CPU time	935.33 seconds
Started	Apr 23 04:48:46 PM PDT 24
Finished	Apr 23 05:04:22 PM PDT 24
Peak memory	562808 kb
Host	smart-d577bb8c-ea62-4cb0-83aa-fe365d7a99dd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580719957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.3580719957
Directory	/workspace/86.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.4063539346
Short name	T404
Test name
Test status
Simulation time	286427768 ps
CPU time	25.8 seconds
Started	Apr 23 04:48:47 PM PDT 24
Finished	Apr 23 04:49:13 PM PDT 24
Peak memory	562700 kb
Host	smart-a1f63c44-117a-49dc-bb69-db9c40a35588
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063539346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.4063539346
Directory	/workspace/86.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_same_source.198993422
Short name	T2029
Test name
Test status
Simulation time	1964819181 ps
CPU time	54.08 seconds
Started	Apr 23 04:48:53 PM PDT 24
Finished	Apr 23 04:49:47 PM PDT 24
Peak memory	561896 kb
Host	smart-8c2092fb-fb94-4d7c-a782-f40c07c70c8c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198993422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.198993422
Directory	/workspace/86.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke.1305569988
Short name	T2588
Test name
Test status
Simulation time	58688937 ps
CPU time	7.36 seconds
Started	Apr 23 04:48:43 PM PDT 24
Finished	Apr 23 04:48:51 PM PDT 24
Peak memory	562732 kb
Host	smart-1f8c8232-ceed-44cf-a8df-2b4359f3d674
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305569988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.1305569988
Directory	/workspace/86.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.484895898
Short name	T512
Test name
Test status
Simulation time	8693046865 ps
CPU time	99.08 seconds
Started	Apr 23 04:48:47 PM PDT 24
Finished	Apr 23 04:50:26 PM PDT 24
Peak memory	562760 kb
Host	smart-1030777b-b0b2-480e-830e-69665d887443
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484895898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.484895898
Directory	/workspace/86.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3176618626
Short name	T1698
Test name
Test status
Simulation time	7171096624 ps
CPU time	123.5 seconds
Started	Apr 23 04:48:48 PM PDT 24
Finished	Apr 23 04:50:52 PM PDT 24
Peak memory	562792 kb
Host	smart-357ce4db-f1e7-467d-8de5-510b237e350f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176618626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.3176618626
Directory	/workspace/86.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.4212786243
Short name	T1244
Test name
Test status
Simulation time	47049261 ps
CPU time	6.2 seconds
Started	Apr 23 04:48:43 PM PDT 24
Finished	Apr 23 04:48:49 PM PDT 24
Peak memory	562640 kb
Host	smart-b7ebe0c0-38cb-4418-be6f-4ca577e0ded7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212786243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.4212786243
Directory	/workspace/86.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all.2174047408
Short name	T1952
Test name
Test status
Simulation time	11415866496 ps
CPU time	412.96 seconds
Started	Apr 23 04:48:56 PM PDT 24
Finished	Apr 23 04:55:49 PM PDT 24
Peak memory	563468 kb
Host	smart-dfa66c96-6246-40c4-ad5c-55a35a4146ae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174047408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2174047408
Directory	/workspace/86.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2063011256
Short name	T2569
Test name
Test status
Simulation time	5940424710 ps
CPU time	219.55 seconds
Started	Apr 23 04:48:51 PM PDT 24
Finished	Apr 23 04:52:31 PM PDT 24
Peak memory	563060 kb
Host	smart-ca06f019-4702-4bf8-b95a-4d7477cb6d1a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063011256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.2063011256
Directory	/workspace/86.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2757618330
Short name	T2618
Test name
Test status
Simulation time	1945151828 ps
CPU time	214.57 seconds
Started	Apr 23 04:48:50 PM PDT 24
Finished	Apr 23 04:52:25 PM PDT 24
Peak memory	563908 kb
Host	smart-1ee4be6d-ed4f-427a-93a8-b46a91261372
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757618330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.2757618330
Directory	/workspace/86.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.597075893
Short name	T2570
Test name
Test status
Simulation time	282855065 ps
CPU time	102.56 seconds
Started	Apr 23 04:48:53 PM PDT 24
Finished	Apr 23 04:50:36 PM PDT 24
Peak memory	563908 kb
Host	smart-073875a4-128b-4dd8-8b2a-0563620012bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597075893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_reset_error.597075893
Directory	/workspace/86.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.2004758606
Short name	T2274
Test name
Test status
Simulation time	1480695399 ps
CPU time	57.38 seconds
Started	Apr 23 04:48:52 PM PDT 24
Finished	Apr 23 04:49:49 PM PDT 24
Peak memory	562796 kb
Host	smart-174bb1c7-af20-4e50-bbe4-088dda74b686
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004758606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.2004758606
Directory	/workspace/86.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_access_same_device.1168889616
Short name	T764
Test name
Test status
Simulation time	1566568402 ps
CPU time	66.24 seconds
Started	Apr 23 04:49:00 PM PDT 24
Finished	Apr 23 04:50:07 PM PDT 24
Peak memory	562756 kb
Host	smart-ada2534b-7b43-45e2-92e3-8065c6640ece
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168889616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .1168889616
Directory	/workspace/87.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2127888021
Short name	T2307
Test name
Test status
Simulation time	119576511454 ps
CPU time	2052.23 seconds
Started	Apr 23 04:48:59 PM PDT 24
Finished	Apr 23 05:23:12 PM PDT 24
Peak memory	562932 kb
Host	smart-a83a60c1-b099-4cca-a807-cce5fea65b07
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127888021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.2127888021
Directory	/workspace/87.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.3127961957
Short name	T2415
Test name
Test status
Simulation time	207024880 ps
CPU time	25.82 seconds
Started	Apr 23 04:49:03 PM PDT 24
Finished	Apr 23 04:49:30 PM PDT 24
Peak memory	562668 kb
Host	smart-ff3bd785-a318-47f7-bc33-c5df0aa75e39
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127961957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.3127961957
Directory	/workspace/87.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_error_random.3138330020
Short name	T505
Test name
Test status
Simulation time	429107951 ps
CPU time	39.58 seconds
Started	Apr 23 04:48:57 PM PDT 24
Finished	Apr 23 04:49:36 PM PDT 24
Peak memory	562704 kb
Host	smart-cfa0ac87-b0b9-44a2-86b1-e83909e77294
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138330020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.3138330020
Directory	/workspace/87.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_random.4062509318
Short name	T2374
Test name
Test status
Simulation time	523118526 ps
CPU time	42.66 seconds
Started	Apr 23 04:48:55 PM PDT 24
Finished	Apr 23 04:49:38 PM PDT 24
Peak memory	562704 kb
Host	smart-08af429b-b98c-4f9f-90dd-471de531b67a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062509318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.4062509318
Directory	/workspace/87.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_random_large_delays.3698408955
Short name	T1483
Test name
Test status
Simulation time	81450467716 ps
CPU time	1020.09 seconds
Started	Apr 23 04:48:57 PM PDT 24
Finished	Apr 23 05:05:58 PM PDT 24
Peak memory	562780 kb
Host	smart-f5d6a1d0-0214-4c9c-a427-7c6aba146da3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698408955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.3698408955
Directory	/workspace/87.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.352841987
Short name	T1693
Test name
Test status
Simulation time	39602360814 ps
CPU time	689.44 seconds
Started	Apr 23 04:48:59 PM PDT 24
Finished	Apr 23 05:00:28 PM PDT 24
Peak memory	562848 kb
Host	smart-071fc641-6f12-45a7-899a-143c1806d6d8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352841987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.352841987
Directory	/workspace/87.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.4126856505
Short name	T1546
Test name
Test status
Simulation time	573261846 ps
CPU time	47.67 seconds
Started	Apr 23 04:48:55 PM PDT 24
Finished	Apr 23 04:49:43 PM PDT 24
Peak memory	562756 kb
Host	smart-2815b9f1-02fa-479e-9e14-44abd939616b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126856505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.4126856505
Directory	/workspace/87.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_same_source.892333147
Short name	T1520
Test name
Test status
Simulation time	364827787 ps
CPU time	28.44 seconds
Started	Apr 23 04:48:57 PM PDT 24
Finished	Apr 23 04:49:26 PM PDT 24
Peak memory	562732 kb
Host	smart-e3264748-33ab-4fb6-beb9-4a6e408c22f9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892333147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.892333147
Directory	/workspace/87.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke.1725232372
Short name	T2236
Test name
Test status
Simulation time	42405938 ps
CPU time	6.46 seconds
Started	Apr 23 04:48:55 PM PDT 24
Finished	Apr 23 04:49:02 PM PDT 24
Peak memory	562660 kb
Host	smart-cf2e5632-8d24-4c43-9e63-b7c3bbc807cd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725232372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.1725232372
Directory	/workspace/87.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.1978366601
Short name	T1368
Test name
Test status
Simulation time	6366004824 ps
CPU time	69.18 seconds
Started	Apr 23 04:48:57 PM PDT 24
Finished	Apr 23 04:50:06 PM PDT 24
Peak memory	562768 kb
Host	smart-23df9faa-ca71-4495-aea9-dae4238c06f8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978366601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1978366601
Directory	/workspace/87.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1340503075
Short name	T2153
Test name
Test status
Simulation time	5359145818 ps
CPU time	97.78 seconds
Started	Apr 23 04:48:57 PM PDT 24
Finished	Apr 23 04:50:35 PM PDT 24
Peak memory	562792 kb
Host	smart-1ec7e268-c546-40f7-8650-37f4adafb857
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340503075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.1340503075
Directory	/workspace/87.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3818016606
Short name	T2455
Test name
Test status
Simulation time	50095525 ps
CPU time	6.7 seconds
Started	Apr 23 04:49:00 PM PDT 24
Finished	Apr 23 04:49:07 PM PDT 24
Peak memory	562728 kb
Host	smart-80034159-51c7-4dab-863f-6ad1937d58bd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818016606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3818016606
Directory	/workspace/87.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all.1503514008
Short name	T1481
Test name
Test status
Simulation time	1102350053 ps
CPU time	44.39 seconds
Started	Apr 23 04:48:59 PM PDT 24
Finished	Apr 23 04:49:44 PM PDT 24
Peak memory	562812 kb
Host	smart-4ae22e0a-858c-45db-a345-0ea42b48fab6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503514008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.1503514008
Directory	/workspace/87.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.3998311882
Short name	T2665
Test name
Test status
Simulation time	1389912444 ps
CPU time	103.54 seconds
Started	Apr 23 04:49:01 PM PDT 24
Finished	Apr 23 04:50:45 PM PDT 24
Peak memory	562828 kb
Host	smart-61f75ef1-29d8-4d61-bab0-cc22ab731c1b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998311882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.3998311882
Directory	/workspace/87.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3257071717
Short name	T2542
Test name
Test status
Simulation time	318849557 ps
CPU time	154.62 seconds
Started	Apr 23 04:48:59 PM PDT 24
Finished	Apr 23 04:51:34 PM PDT 24
Peak memory	563972 kb
Host	smart-1886ffbd-c0bd-44c8-9398-52dafe9aba7f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257071717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.3257071717
Directory	/workspace/87.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.4011858226
Short name	T826
Test name
Test status
Simulation time	651541553 ps
CPU time	208.71 seconds
Started	Apr 23 04:48:59 PM PDT 24
Finished	Apr 23 04:52:28 PM PDT 24
Peak memory	572100 kb
Host	smart-94f2e8c8-1065-42bd-a560-c7fb92dca69a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011858226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.4011858226
Directory	/workspace/87.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.2519550145
Short name	T2324
Test name
Test status
Simulation time	729389410 ps
CPU time	33.44 seconds
Started	Apr 23 04:48:59 PM PDT 24
Finished	Apr 23 04:49:33 PM PDT 24
Peak memory	562748 kb
Host	smart-aad3f76b-25ad-46c9-a577-423027bb49b5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519550145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.2519550145
Directory	/workspace/87.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_access_same_device.1686081418
Short name	T775
Test name
Test status
Simulation time	1021894630 ps
CPU time	43.96 seconds
Started	Apr 23 04:49:07 PM PDT 24
Finished	Apr 23 04:49:51 PM PDT 24
Peak memory	562772 kb
Host	smart-ee462b29-cab9-4cfd-b52a-aa7f438e43fb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686081418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .1686081418
Directory	/workspace/88.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1381878905
Short name	T2100
Test name
Test status
Simulation time	12308815622 ps
CPU time	214.63 seconds
Started	Apr 23 04:49:05 PM PDT 24
Finished	Apr 23 04:52:40 PM PDT 24
Peak memory	562792 kb
Host	smart-266bf55a-3e5c-49d8-8bae-652e3ae27bad
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381878905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.1381878905
Directory	/workspace/88.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.4069730451
Short name	T1964
Test name
Test status
Simulation time	78811849 ps
CPU time	12.56 seconds
Started	Apr 23 04:49:09 PM PDT 24
Finished	Apr 23 04:49:22 PM PDT 24
Peak memory	562720 kb
Host	smart-a166482c-7957-4206-b277-6f5a486a5fb4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069730451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.4069730451
Directory	/workspace/88.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_error_random.1592487680
Short name	T1816
Test name
Test status
Simulation time	576588498 ps
CPU time	44.3 seconds
Started	Apr 23 04:49:11 PM PDT 24
Finished	Apr 23 04:49:55 PM PDT 24
Peak memory	562740 kb
Host	smart-a02430a6-8f8d-40c2-bfd8-c418e66f6fe9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592487680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1592487680
Directory	/workspace/88.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_random.1773395478
Short name	T2721
Test name
Test status
Simulation time	2589437120 ps
CPU time	102.18 seconds
Started	Apr 23 04:49:03 PM PDT 24
Finished	Apr 23 04:50:45 PM PDT 24
Peak memory	562812 kb
Host	smart-c6911001-19e3-4bef-acfe-1456b79e5c6e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773395478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.1773395478
Directory	/workspace/88.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.1599806047
Short name	T2784
Test name
Test status
Simulation time	73912743395 ps
CPU time	1253.55 seconds
Started	Apr 23 04:49:04 PM PDT 24
Finished	Apr 23 05:09:58 PM PDT 24
Peak memory	562804 kb
Host	smart-16d65142-54e3-4b09-9376-169e020c85f4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599806047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.1599806047
Directory	/workspace/88.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.2402443127
Short name	T547
Test name
Test status
Simulation time	642246173 ps
CPU time	56.17 seconds
Started	Apr 23 04:49:04 PM PDT 24
Finished	Apr 23 04:50:00 PM PDT 24
Peak memory	562752 kb
Host	smart-39c7910a-83ec-40ce-80bc-e889d790a878
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402443127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.2402443127
Directory	/workspace/88.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_same_source.284025129
Short name	T1732
Test name
Test status
Simulation time	1378338866 ps
CPU time	45.96 seconds
Started	Apr 23 04:49:07 PM PDT 24
Finished	Apr 23 04:49:53 PM PDT 24
Peak memory	562696 kb
Host	smart-ef167f31-7cc7-434d-a8d9-282faf99cf76
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284025129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.284025129
Directory	/workspace/88.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke.1703304226
Short name	T1880
Test name
Test status
Simulation time	50763225 ps
CPU time	6.45 seconds
Started	Apr 23 04:49:04 PM PDT 24
Finished	Apr 23 04:49:10 PM PDT 24
Peak memory	562648 kb
Host	smart-5b5f0ec8-8d12-49d3-a2d8-49ca3a07d319
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703304226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.1703304226
Directory	/workspace/88.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.2942205004
Short name	T1226
Test name
Test status
Simulation time	8898660963 ps
CPU time	94.81 seconds
Started	Apr 23 04:49:03 PM PDT 24
Finished	Apr 23 04:50:38 PM PDT 24
Peak memory	562772 kb
Host	smart-f5eda45b-5c76-4377-9a2c-00567fc3f9fd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942205004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.2942205004
Directory	/workspace/88.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3807012439
Short name	T1853
Test name
Test status
Simulation time	4974248426 ps
CPU time	92.96 seconds
Started	Apr 23 04:49:01 PM PDT 24
Finished	Apr 23 04:50:34 PM PDT 24
Peak memory	562744 kb
Host	smart-7e305e19-6651-4504-b48c-cae9a9d97086
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807012439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3807012439
Directory	/workspace/88.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.506293408
Short name	T1514
Test name
Test status
Simulation time	50954816 ps
CPU time	6.36 seconds
Started	Apr 23 04:49:01 PM PDT 24
Finished	Apr 23 04:49:08 PM PDT 24
Peak memory	562712 kb
Host	smart-c4c418cb-04af-49e7-bed7-504b840bf666
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506293408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays .506293408
Directory	/workspace/88.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.946194980
Short name	T2766
Test name
Test status
Simulation time	3218638853 ps
CPU time	282.54 seconds
Started	Apr 23 04:49:11 PM PDT 24
Finished	Apr 23 04:53:53 PM PDT 24
Peak memory	564000 kb
Host	smart-ae87dd73-d8fa-4699-9bea-3b3080a2d25e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946194980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_ with_rand_reset.946194980
Directory	/workspace/88.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2016677627
Short name	T2389
Test name
Test status
Simulation time	6441053225 ps
CPU time	431.88 seconds
Started	Apr 23 04:49:12 PM PDT 24
Finished	Apr 23 04:56:24 PM PDT 24
Peak memory	572212 kb
Host	smart-912a7408-c241-43b4-af0c-56b59add6f6b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016677627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.2016677627
Directory	/workspace/88.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.2652381484
Short name	T2017
Test name
Test status
Simulation time	263854639 ps
CPU time	13.79 seconds
Started	Apr 23 04:49:12 PM PDT 24
Finished	Apr 23 04:49:26 PM PDT 24
Peak memory	562764 kb
Host	smart-baf72775-56c7-4f06-a8e4-3ff91a9a0324
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652381484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.2652381484
Directory	/workspace/88.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_access_same_device.658706786
Short name	T419
Test name
Test status
Simulation time	1010006393 ps
CPU time	79.35 seconds
Started	Apr 23 04:49:18 PM PDT 24
Finished	Apr 23 04:50:37 PM PDT 24
Peak memory	562716 kb
Host	smart-82d54b87-90dd-485f-813d-7a5b2e9f7236
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658706786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device. 658706786
Directory	/workspace/89.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.2130212718
Short name	T1796
Test name
Test status
Simulation time	132594306285 ps
CPU time	2229.67 seconds
Started	Apr 23 04:49:18 PM PDT 24
Finished	Apr 23 05:26:28 PM PDT 24
Peak memory	563088 kb
Host	smart-17c456b8-5a17-41e0-ae1e-b9e939a3c2d2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130212718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.2130212718
Directory	/workspace/89.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.260731770
Short name	T2419
Test name
Test status
Simulation time	1171690759 ps
CPU time	45.41 seconds
Started	Apr 23 04:49:19 PM PDT 24
Finished	Apr 23 04:50:05 PM PDT 24
Peak memory	562696 kb
Host	smart-3fc8c51e-9b7b-4a47-8fe4-2ddf743467e5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260731770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr .260731770
Directory	/workspace/89.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_error_random.2399744940
Short name	T231
Test name
Test status
Simulation time	1838196860 ps
CPU time	58.88 seconds
Started	Apr 23 04:49:19 PM PDT 24
Finished	Apr 23 04:50:18 PM PDT 24
Peak memory	562724 kb
Host	smart-0cb7a40b-cd0c-4b20-b6d9-e95ef1e969dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399744940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.2399744940
Directory	/workspace/89.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_random.2966905784
Short name	T2447
Test name
Test status
Simulation time	483956887 ps
CPU time	23.15 seconds
Started	Apr 23 04:49:17 PM PDT 24
Finished	Apr 23 04:49:40 PM PDT 24
Peak memory	562764 kb
Host	smart-42beae60-c6d6-4e95-8477-b8c16cfcc1b7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966905784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.2966905784
Directory	/workspace/89.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3032111938
Short name	T1808
Test name
Test status
Simulation time	77312023095 ps
CPU time	837.18 seconds
Started	Apr 23 04:49:15 PM PDT 24
Finished	Apr 23 05:03:12 PM PDT 24
Peak memory	562828 kb
Host	smart-00f97652-eec3-4076-b322-dbe0a2eb5a5f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032111938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3032111938
Directory	/workspace/89.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3405772824
Short name	T1621
Test name
Test status
Simulation time	3629276688 ps
CPU time	65.17 seconds
Started	Apr 23 04:49:18 PM PDT 24
Finished	Apr 23 04:50:23 PM PDT 24
Peak memory	562736 kb
Host	smart-3e111464-518c-46b0-944d-3bc4b3ff53b6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405772824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3405772824
Directory	/workspace/89.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.399514213
Short name	T1399
Test name
Test status
Simulation time	198732041 ps
CPU time	19.55 seconds
Started	Apr 23 04:49:18 PM PDT 24
Finished	Apr 23 04:49:38 PM PDT 24
Peak memory	562672 kb
Host	smart-678cddd6-c37e-43c9-b12f-3e69f5777c1e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399514213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_dela ys.399514213
Directory	/workspace/89.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_same_source.2428526460
Short name	T2526
Test name
Test status
Simulation time	1277956857 ps
CPU time	40.78 seconds
Started	Apr 23 04:49:18 PM PDT 24
Finished	Apr 23 04:49:59 PM PDT 24
Peak memory	562740 kb
Host	smart-1d70c57a-f323-4926-9fa8-fc43489e79b5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428526460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2428526460
Directory	/workspace/89.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke.366271347
Short name	T1517
Test name
Test status
Simulation time	176491795 ps
CPU time	8.97 seconds
Started	Apr 23 04:49:11 PM PDT 24
Finished	Apr 23 04:49:21 PM PDT 24
Peak memory	562728 kb
Host	smart-a43e3a86-8959-4d63-ae53-5ab352313cb1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366271347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.366271347
Directory	/workspace/89.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3670860444
Short name	T1731
Test name
Test status
Simulation time	8178643008 ps
CPU time	89.22 seconds
Started	Apr 23 04:49:12 PM PDT 24
Finished	Apr 23 04:50:41 PM PDT 24
Peak memory	562768 kb
Host	smart-677e580a-4afe-4d03-b7c3-4d81be8c3d3a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670860444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3670860444
Directory	/workspace/89.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3109940527
Short name	T1227
Test name
Test status
Simulation time	4287707656 ps
CPU time	74.49 seconds
Started	Apr 23 04:49:14 PM PDT 24
Finished	Apr 23 04:50:29 PM PDT 24
Peak memory	562696 kb
Host	smart-5c8c947f-1699-4009-9015-5763337664d1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109940527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3109940527
Directory	/workspace/89.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.3812924552
Short name	T1761
Test name
Test status
Simulation time	41477753 ps
CPU time	5.88 seconds
Started	Apr 23 04:49:14 PM PDT 24
Finished	Apr 23 04:49:20 PM PDT 24
Peak memory	562704 kb
Host	smart-a50cdade-fce9-487d-9d67-b7ebeebb9977
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812924552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.3812924552
Directory	/workspace/89.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all.1967214016
Short name	T2330
Test name
Test status
Simulation time	6901730560 ps
CPU time	303.82 seconds
Started	Apr 23 04:49:17 PM PDT 24
Finished	Apr 23 04:54:21 PM PDT 24
Peak memory	563988 kb
Host	smart-9a42d005-7115-4785-a840-a6403545b566
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967214016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.1967214016
Directory	/workspace/89.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2429863367
Short name	T2044
Test name
Test status
Simulation time	1852180362 ps
CPU time	164.29 seconds
Started	Apr 23 04:49:22 PM PDT 24
Finished	Apr 23 04:52:07 PM PDT 24
Peak memory	571220 kb
Host	smart-4e98dcd9-c7f2-481b-b55c-0b66e0fc53b6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429863367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2429863367
Directory	/workspace/89.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.581004587
Short name	T2702
Test name
Test status
Simulation time	17387309240 ps
CPU time	960.46 seconds
Started	Apr 23 04:49:19 PM PDT 24
Finished	Apr 23 05:05:19 PM PDT 24
Peak memory	572192 kb
Host	smart-80999086-d03c-4a12-b80d-9e0b1025fe88
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581004587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_ with_rand_reset.581004587
Directory	/workspace/89.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.449015143
Short name	T1413
Test name
Test status
Simulation time	238502132 ps
CPU time	78.32 seconds
Started	Apr 23 04:49:20 PM PDT 24
Finished	Apr 23 04:50:39 PM PDT 24
Peak memory	563860 kb
Host	smart-0ab4db02-811f-4a40-b634-a74622f6356d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449015143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.449015143
Directory	/workspace/89.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.2591178810
Short name	T2612
Test name
Test status
Simulation time	20094772 ps
CPU time	5.2 seconds
Started	Apr 23 04:49:17 PM PDT 24
Finished	Apr 23 04:49:23 PM PDT 24
Peak memory	562752 kb
Host	smart-586a7227-aa9f-4f48-90a8-f2bbf504d3c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591178810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.2591178810
Directory	/workspace/89.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/9.chip_csr_rw.4291994194
Short name	T496
Test name
Test status
Simulation time	6289531280 ps
CPU time	663.1 seconds
Started	Apr 23 04:33:46 PM PDT 24
Finished	Apr 23 04:44:50 PM PDT 24
Peak memory	589372 kb
Host	smart-604cd48b-1bd3-42ee-aa2d-ff324a0552cf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291994194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.4291994194
Directory	/workspace/9.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.2597558879
Short name	T369
Test name
Test status
Simulation time	34076236699 ps
CPU time	4495.21 seconds
Started	Apr 23 04:33:17 PM PDT 24
Finished	Apr 23 05:48:13 PM PDT 24
Peak memory	585104 kb
Host	smart-2a38d5f1-cc58-4449-98b2-b75a84299240
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597558879 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.2597558879
Directory	/workspace/9.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_access_same_device.4028465359
Short name	T1722
Test name
Test status
Simulation time	1381125305 ps
CPU time	59.7 seconds
Started	Apr 23 04:33:33 PM PDT 24
Finished	Apr 23 04:34:33 PM PDT 24
Peak memory	562792 kb
Host	smart-806ab337-57eb-4bf9-990c-acb38a22e28e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028465359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 4028465359
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2138193976
Short name	T2327
Test name
Test status
Simulation time	56251818699 ps
CPU time	1067.03 seconds
Started	Apr 23 04:33:35 PM PDT 24
Finished	Apr 23 04:51:23 PM PDT 24
Peak memory	562932 kb
Host	smart-eb33beec-31f9-4a61-ac3d-8a774d760333
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138193976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2138193976
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.845788858
Short name	T1824
Test name
Test status
Simulation time	97192632 ps
CPU time	8.66 seconds
Started	Apr 23 04:33:46 PM PDT 24
Finished	Apr 23 04:33:55 PM PDT 24
Peak memory	562676 kb
Host	smart-aa4ed764-8017-4a8c-bf85-810027a64ea1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845788858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr. 845788858
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_error_random.2837909312
Short name	T2193
Test name
Test status
Simulation time	501255576 ps
CPU time	45.5 seconds
Started	Apr 23 04:33:36 PM PDT 24
Finished	Apr 23 04:34:22 PM PDT 24
Peak memory	562740 kb
Host	smart-056c6733-20ed-4cab-a1a7-51642bc7a3b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837909312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2837909312
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_random.3340740296
Short name	T1479
Test name
Test status
Simulation time	1988187169 ps
CPU time	71.01 seconds
Started	Apr 23 04:33:30 PM PDT 24
Finished	Apr 23 04:34:41 PM PDT 24
Peak memory	562724 kb
Host	smart-22a7b166-088a-452d-aac8-dcf5798cb285
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340740296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.3340740296
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_random_large_delays.4025599028
Short name	T463
Test name
Test status
Simulation time	37565146411 ps
CPU time	405.87 seconds
Started	Apr 23 04:33:30 PM PDT 24
Finished	Apr 23 04:40:16 PM PDT 24
Peak memory	562820 kb
Host	smart-5ea5071a-6936-4117-8076-fe11b01e0096
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025599028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4025599028
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1723599513
Short name	T2104
Test name
Test status
Simulation time	8414175721 ps
CPU time	147.38 seconds
Started	Apr 23 04:33:31 PM PDT 24
Finished	Apr 23 04:35:59 PM PDT 24
Peak memory	562824 kb
Host	smart-fdc43328-bb61-46ca-9891-5d82dc1e8a6c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723599513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1723599513
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2141753814
Short name	T542
Test name
Test status
Simulation time	398450970 ps
CPU time	38.28 seconds
Started	Apr 23 04:33:29 PM PDT 24
Finished	Apr 23 04:34:08 PM PDT 24
Peak memory	562736 kb
Host	smart-a9ebeb0b-b7f9-4386-b570-b5a9bb04eab8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141753814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2141753814
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_same_source.1907463161
Short name	T2438
Test name
Test status
Simulation time	1896495420 ps
CPU time	69.9 seconds
Started	Apr 23 04:33:42 PM PDT 24
Finished	Apr 23 04:34:52 PM PDT 24
Peak memory	562676 kb
Host	smart-4ed4bb2c-43c4-404a-b2a2-0ea3cf6bfbd6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907463161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1907463161
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke.4227088521
Short name	T1953
Test name
Test status
Simulation time	50923108 ps
CPU time	7.13 seconds
Started	Apr 23 04:33:25 PM PDT 24
Finished	Apr 23 04:33:33 PM PDT 24
Peak memory	562736 kb
Host	smart-106383f7-17a8-4cf3-a10d-3d261a734089
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227088521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.4227088521
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.333784069
Short name	T1310
Test name
Test status
Simulation time	6473517222 ps
CPU time	76.45 seconds
Started	Apr 23 04:33:23 PM PDT 24
Finished	Apr 23 04:34:40 PM PDT 24
Peak memory	562784 kb
Host	smart-a408bfc8-b67f-43ac-bde6-40bab58dec74
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333784069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.333784069
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3916299729
Short name	T2210
Test name
Test status
Simulation time	3846851203 ps
CPU time	68.21 seconds
Started	Apr 23 04:33:25 PM PDT 24
Finished	Apr 23 04:34:34 PM PDT 24
Peak memory	562748 kb
Host	smart-69a0b2f9-8758-4e19-a9ff-02b46e3be8dd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916299729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3916299729
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.3065370993
Short name	T1551
Test name
Test status
Simulation time	47401940 ps
CPU time	6.47 seconds
Started	Apr 23 04:33:22 PM PDT 24
Finished	Apr 23 04:33:29 PM PDT 24
Peak memory	562688 kb
Host	smart-2aef7c6e-7f4e-43e3-b5f0-f87a6a9817fb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065370993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .3065370993
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all.1476671697
Short name	T2037
Test name
Test status
Simulation time	1395642175 ps
CPU time	127.14 seconds
Started	Apr 23 04:33:43 PM PDT 24
Finished	Apr 23 04:35:50 PM PDT 24
Peak memory	563804 kb
Host	smart-3533f921-1bc1-4c12-9dcd-6acbab2636f5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476671697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1476671697
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2911361271
Short name	T502
Test name
Test status
Simulation time	9618036267 ps
CPU time	307.1 seconds
Started	Apr 23 04:33:52 PM PDT 24
Finished	Apr 23 04:38:59 PM PDT 24
Peak memory	563576 kb
Host	smart-6a0c3806-f555-443c-a8ca-041b5b4fdd78
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911361271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2911361271
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1668124713
Short name	T1918
Test name
Test status
Simulation time	271828469 ps
CPU time	123.34 seconds
Started	Apr 23 04:33:44 PM PDT 24
Finished	Apr 23 04:35:48 PM PDT 24
Peak memory	563912 kb
Host	smart-ea119aee-e960-41bd-aabb-14679c70e85b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668124713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.1668124713
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.654587434
Short name	T1943
Test name
Test status
Simulation time	17271838495 ps
CPU time	778.01 seconds
Started	Apr 23 04:33:46 PM PDT 24
Finished	Apr 23 04:46:44 PM PDT 24
Peak memory	572220 kb
Host	smart-cd0161a9-0932-438b-a95d-502045e85609
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654587434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.654587434
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3208306252
Short name	T1752
Test name
Test status
Simulation time	192123656 ps
CPU time	11.26 seconds
Started	Apr 23 04:33:39 PM PDT 24
Finished	Apr 23 04:33:50 PM PDT 24
Peak memory	562804 kb
Host	smart-fb8de56a-1ba2-4243-ac4a-889bebff0a9c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208306252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3208306252
Directory	/workspace/9.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.988368117
Short name	T2661
Test name
Test status
Simulation time	44637077141 ps
CPU time	769.73 seconds
Started	Apr 23 04:49:26 PM PDT 24
Finished	Apr 23 05:02:16 PM PDT 24
Peak memory	562780 kb
Host	smart-ac3ca37d-f344-4a51-a6a4-2ba7a9e9b4a9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988368117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.988368117
Directory	/workspace/90.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1376118140
Short name	T1623
Test name
Test status
Simulation time	177551148 ps
CPU time	11.19 seconds
Started	Apr 23 04:49:30 PM PDT 24
Finished	Apr 23 04:49:41 PM PDT 24
Peak memory	562752 kb
Host	smart-b1b7f822-0042-4d06-a65c-ecb25980d8a7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376118140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.1376118140
Directory	/workspace/90.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_error_random.2079915992
Short name	T2112
Test name
Test status
Simulation time	603135760 ps
CPU time	49.89 seconds
Started	Apr 23 04:49:27 PM PDT 24
Finished	Apr 23 04:50:17 PM PDT 24
Peak memory	562728 kb
Host	smart-efa07108-9413-43aa-bf21-b633ce61c4c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079915992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.2079915992
Directory	/workspace/90.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_random.2206067312
Short name	T473
Test name
Test status
Simulation time	188726560 ps
CPU time	18.58 seconds
Started	Apr 23 04:49:20 PM PDT 24
Finished	Apr 23 04:49:39 PM PDT 24
Peak memory	562764 kb
Host	smart-7990950e-1bca-4492-8246-f39b9f30512a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206067312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2206067312
Directory	/workspace/90.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_random_large_delays.1027982885
Short name	T486
Test name
Test status
Simulation time	44628484090 ps
CPU time	472.19 seconds
Started	Apr 23 04:49:31 PM PDT 24
Finished	Apr 23 04:57:24 PM PDT 24
Peak memory	562804 kb
Host	smart-12e83bd5-72da-4117-b724-b10a21df2e05
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027982885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.1027982885
Directory	/workspace/90.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.103773719
Short name	T2329
Test name
Test status
Simulation time	50331346428 ps
CPU time	868.99 seconds
Started	Apr 23 04:49:26 PM PDT 24
Finished	Apr 23 05:03:56 PM PDT 24
Peak memory	562740 kb
Host	smart-d81dd6f0-aca9-430a-8f1d-ffe7efdf6c31
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103773719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.103773719
Directory	/workspace/90.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2073257274
Short name	T1903
Test name
Test status
Simulation time	517700492 ps
CPU time	47.56 seconds
Started	Apr 23 04:49:22 PM PDT 24
Finished	Apr 23 04:50:09 PM PDT 24
Peak memory	562728 kb
Host	smart-da21fcd7-0f5d-40dd-b478-80231e6ef796
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073257274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.2073257274
Directory	/workspace/90.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_same_source.3326424714
Short name	T577
Test name
Test status
Simulation time	2387836617 ps
CPU time	67.71 seconds
Started	Apr 23 04:49:25 PM PDT 24
Finished	Apr 23 04:50:33 PM PDT 24
Peak memory	562804 kb
Host	smart-0a29c394-ff1a-4364-9784-83031fabf03e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326424714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.3326424714
Directory	/workspace/90.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke.124650973
Short name	T2461
Test name
Test status
Simulation time	201741767 ps
CPU time	9.59 seconds
Started	Apr 23 04:49:22 PM PDT 24
Finished	Apr 23 04:49:32 PM PDT 24
Peak memory	562688 kb
Host	smart-76b5eaa0-3fd9-49c1-875a-3efa1f7f3b99
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124650973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.124650973
Directory	/workspace/90.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.3026554054
Short name	T2510
Test name
Test status
Simulation time	7797264131 ps
CPU time	82.84 seconds
Started	Apr 23 04:49:22 PM PDT 24
Finished	Apr 23 04:50:45 PM PDT 24
Peak memory	562764 kb
Host	smart-8df97577-72e2-41d6-bad3-f83fb0613466
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026554054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.3026554054
Directory	/workspace/90.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2525767994
Short name	T1382
Test name
Test status
Simulation time	6156408528 ps
CPU time	114.42 seconds
Started	Apr 23 04:49:23 PM PDT 24
Finished	Apr 23 04:51:18 PM PDT 24
Peak memory	562724 kb
Host	smart-0d0f5965-66db-4f7c-914a-613837a9effb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525767994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.2525767994
Directory	/workspace/90.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2712732116
Short name	T2701
Test name
Test status
Simulation time	47332263 ps
CPU time	6.71 seconds
Started	Apr 23 04:49:22 PM PDT 24
Finished	Apr 23 04:49:29 PM PDT 24
Peak memory	562680 kb
Host	smart-7b549686-6b32-4f09-ab57-a55049aea846
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712732116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.2712732116
Directory	/workspace/90.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all.365999346
Short name	T426
Test name
Test status
Simulation time	7636281851 ps
CPU time	300.34 seconds
Started	Apr 23 04:49:30 PM PDT 24
Finished	Apr 23 04:54:31 PM PDT 24
Peak memory	562956 kb
Host	smart-6c8d6350-c52c-4852-9430-627e64590adc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365999346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.365999346
Directory	/workspace/90.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.304736728
Short name	T625
Test name
Test status
Simulation time	3962635104 ps
CPU time	309.85 seconds
Started	Apr 23 04:49:28 PM PDT 24
Finished	Apr 23 04:54:38 PM PDT 24
Peak memory	564028 kb
Host	smart-dad6b739-e1a7-455e-a7f4-98b91045926f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304736728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.304736728
Directory	/workspace/90.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.1008602836
Short name	T468
Test name
Test status
Simulation time	11485034970 ps
CPU time	585.49 seconds
Started	Apr 23 04:49:28 PM PDT 24
Finished	Apr 23 04:59:14 PM PDT 24
Peak memory	572208 kb
Host	smart-927eadf4-fd08-4cb5-b500-b91572c97508
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008602836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.1008602836
Directory	/workspace/90.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.707144536
Short name	T807
Test name
Test status
Simulation time	433533466 ps
CPU time	141.43 seconds
Started	Apr 23 04:49:28 PM PDT 24
Finished	Apr 23 04:51:49 PM PDT 24
Peak memory	563900 kb
Host	smart-2e9fb71a-d65e-4651-87cf-3d882676c9e9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707144536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_reset_error.707144536
Directory	/workspace/90.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.1362705294
Short name	T439
Test name
Test status
Simulation time	459997065 ps
CPU time	20.31 seconds
Started	Apr 23 04:49:25 PM PDT 24
Finished	Apr 23 04:49:46 PM PDT 24
Peak memory	562796 kb
Host	smart-89ff8f9b-dc63-4324-b646-2b9a98ef96af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362705294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.1362705294
Directory	/workspace/90.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_access_same_device.4166530712
Short name	T776
Test name
Test status
Simulation time	846817553 ps
CPU time	40.85 seconds
Started	Apr 23 04:49:40 PM PDT 24
Finished	Apr 23 04:50:21 PM PDT 24
Peak memory	562760 kb
Host	smart-38261f96-4724-429f-85f9-ee55168faed5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166530712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .4166530712
Directory	/workspace/91.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1387474882
Short name	T783
Test name
Test status
Simulation time	88971791091 ps
CPU time	1612.37 seconds
Started	Apr 23 04:49:40 PM PDT 24
Finished	Apr 23 05:16:33 PM PDT 24
Peak memory	562812 kb
Host	smart-ee3db613-d2ed-45e4-9546-56213befbcd0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387474882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.1387474882
Directory	/workspace/91.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.4004143758
Short name	T1257
Test name
Test status
Simulation time	1140472969 ps
CPU time	49.44 seconds
Started	Apr 23 04:49:41 PM PDT 24
Finished	Apr 23 04:50:31 PM PDT 24
Peak memory	562748 kb
Host	smart-1f10357a-2620-4b57-9525-fb56fb0e713a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004143758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.4004143758
Directory	/workspace/91.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_error_random.135894363
Short name	T2091
Test name
Test status
Simulation time	39291844 ps
CPU time	6.13 seconds
Started	Apr 23 04:49:40 PM PDT 24
Finished	Apr 23 04:49:46 PM PDT 24
Peak memory	562724 kb
Host	smart-24efbb90-4b0e-4350-b783-d305dff95852
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135894363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.135894363
Directory	/workspace/91.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_random.1486648297
Short name	T524
Test name
Test status
Simulation time	2187981040 ps
CPU time	82.64 seconds
Started	Apr 23 04:49:35 PM PDT 24
Finished	Apr 23 04:50:58 PM PDT 24
Peak memory	562808 kb
Host	smart-3e6a5ed8-2ed6-4447-856c-5b15f456db71
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486648297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.1486648297
Directory	/workspace/91.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_random_large_delays.959560956
Short name	T515
Test name
Test status
Simulation time	108784351641 ps
CPU time	1313.54 seconds
Started	Apr 23 04:49:36 PM PDT 24
Finished	Apr 23 05:11:30 PM PDT 24
Peak memory	562820 kb
Host	smart-f5bbf826-f58a-4198-84e2-d79448f7cf04
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959560956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.959560956
Directory	/workspace/91.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.2011895764
Short name	T1898
Test name
Test status
Simulation time	3035364157 ps
CPU time	54.79 seconds
Started	Apr 23 04:49:35 PM PDT 24
Finished	Apr 23 04:50:30 PM PDT 24
Peak memory	562768 kb
Host	smart-f9c0a280-4a78-43cc-9c31-abb2f1fa5a70
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011895764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.2011895764
Directory	/workspace/91.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.2835727996
Short name	T1457
Test name
Test status
Simulation time	431550292 ps
CPU time	39.51 seconds
Started	Apr 23 04:49:35 PM PDT 24
Finished	Apr 23 04:50:14 PM PDT 24
Peak memory	562760 kb
Host	smart-d6657d3a-8c49-457b-a5a9-99966d34f8e1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835727996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.2835727996
Directory	/workspace/91.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_same_source.435027961
Short name	T1273
Test name
Test status
Simulation time	704997939 ps
CPU time	25.19 seconds
Started	Apr 23 04:49:37 PM PDT 24
Finished	Apr 23 04:50:02 PM PDT 24
Peak memory	562680 kb
Host	smart-9c07a5b4-53e9-4123-81d9-096d0dcca276
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435027961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.435027961
Directory	/workspace/91.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke.298240036
Short name	T2361
Test name
Test status
Simulation time	50491255 ps
CPU time	7.14 seconds
Started	Apr 23 04:49:28 PM PDT 24
Finished	Apr 23 04:49:35 PM PDT 24
Peak memory	562684 kb
Host	smart-d0e5eac7-a984-4e1d-be56-287b2004c50e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298240036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.298240036
Directory	/workspace/91.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2464473680
Short name	T2158
Test name
Test status
Simulation time	8627344235 ps
CPU time	91.88 seconds
Started	Apr 23 04:49:32 PM PDT 24
Finished	Apr 23 04:51:04 PM PDT 24
Peak memory	562748 kb
Host	smart-d91efe14-1c89-4b74-a2bc-55d761a87d4b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464473680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2464473680
Directory	/workspace/91.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1951811600
Short name	T1502
Test name
Test status
Simulation time	4884017583 ps
CPU time	89.85 seconds
Started	Apr 23 04:49:32 PM PDT 24
Finished	Apr 23 04:51:02 PM PDT 24
Peak memory	562804 kb
Host	smart-6dbdda0e-c7ee-411d-a3e2-3706f766660d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951811600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.1951811600
Directory	/workspace/91.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1655921218
Short name	T459
Test name
Test status
Simulation time	54488538 ps
CPU time	7.37 seconds
Started	Apr 23 04:49:36 PM PDT 24
Finished	Apr 23 04:49:43 PM PDT 24
Peak memory	562692 kb
Host	smart-6051f685-a9da-42d5-90df-84bb3afae376
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655921218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.1655921218
Directory	/workspace/91.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all.2095776910
Short name	T2621
Test name
Test status
Simulation time	11093777450 ps
CPU time	382.92 seconds
Started	Apr 23 04:49:43 PM PDT 24
Finished	Apr 23 04:56:06 PM PDT 24
Peak memory	563440 kb
Host	smart-eac5899c-1c2f-4802-bfc0-909b3df03b15
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095776910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.2095776910
Directory	/workspace/91.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.760698985
Short name	T2625
Test name
Test status
Simulation time	10040544348 ps
CPU time	378.07 seconds
Started	Apr 23 04:49:41 PM PDT 24
Finished	Apr 23 04:56:00 PM PDT 24
Peak memory	563796 kb
Host	smart-393698e8-9683-418c-8e91-cb554c730a38
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760698985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.760698985
Directory	/workspace/91.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1986338829
Short name	T2388
Test name
Test status
Simulation time	6958553 ps
CPU time	16.52 seconds
Started	Apr 23 04:49:40 PM PDT 24
Finished	Apr 23 04:49:57 PM PDT 24
Peak memory	562604 kb
Host	smart-245d608e-bdb1-4b47-8ac6-e12c3412a892
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986338829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.1986338829
Directory	/workspace/91.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2593090571
Short name	T809
Test name
Test status
Simulation time	136495531 ps
CPU time	51.13 seconds
Started	Apr 23 04:49:45 PM PDT 24
Finished	Apr 23 04:50:37 PM PDT 24
Peak memory	563516 kb
Host	smart-814827f6-f82d-4a85-9772-1113c6db7152
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593090571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.2593090571
Directory	/workspace/91.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3524901958
Short name	T566
Test name
Test status
Simulation time	951715440 ps
CPU time	45.6 seconds
Started	Apr 23 04:49:41 PM PDT 24
Finished	Apr 23 04:50:27 PM PDT 24
Peak memory	562760 kb
Host	smart-0eea1046-8027-4942-a89b-299f7e0d3a22
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524901958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.3524901958
Directory	/workspace/91.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_access_same_device.452013034
Short name	T480
Test name
Test status
Simulation time	465099150 ps
CPU time	32.87 seconds
Started	Apr 23 04:49:46 PM PDT 24
Finished	Apr 23 04:50:19 PM PDT 24
Peak memory	562684 kb
Host	smart-6368881a-1fca-46ea-8fe6-9985d0d1d567
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452013034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device. 452013034
Directory	/workspace/92.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3634730819
Short name	T1827
Test name
Test status
Simulation time	83248969260 ps
CPU time	1452.45 seconds
Started	Apr 23 04:49:49 PM PDT 24
Finished	Apr 23 05:14:02 PM PDT 24
Peak memory	562932 kb
Host	smart-59a0f074-781e-4919-8801-a2e7f23b6e5f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634730819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.3634730819
Directory	/workspace/92.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.2879035433
Short name	T1277
Test name
Test status
Simulation time	39062004 ps
CPU time	6.9 seconds
Started	Apr 23 04:49:50 PM PDT 24
Finished	Apr 23 04:49:58 PM PDT 24
Peak memory	562696 kb
Host	smart-a1337071-6e0f-432b-a49b-962f3683ad08
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879035433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.2879035433
Directory	/workspace/92.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_error_random.1392075716
Short name	T2111
Test name
Test status
Simulation time	590013442 ps
CPU time	54.57 seconds
Started	Apr 23 04:49:51 PM PDT 24
Finished	Apr 23 04:50:46 PM PDT 24
Peak memory	562708 kb
Host	smart-3c8f52a3-876a-4811-89f2-2f63c7d34ab8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392075716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.1392075716
Directory	/workspace/92.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_random.1073753873
Short name	T1979
Test name
Test status
Simulation time	140937197 ps
CPU time	16.01 seconds
Started	Apr 23 04:49:53 PM PDT 24
Finished	Apr 23 04:50:09 PM PDT 24
Peak memory	562764 kb
Host	smart-f948c341-dc64-4dd6-aa05-d6d6c21a383d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073753873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.1073753873
Directory	/workspace/92.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_random_large_delays.3783640575
Short name	T1653
Test name
Test status
Simulation time	25785221758 ps
CPU time	312.1 seconds
Started	Apr 23 04:49:47 PM PDT 24
Finished	Apr 23 04:55:00 PM PDT 24
Peak memory	562808 kb
Host	smart-f7e5e6d8-8597-4ae6-a808-fe2b2c17def2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783640575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.3783640575
Directory	/workspace/92.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1491993682
Short name	T1770
Test name
Test status
Simulation time	3577066216 ps
CPU time	67.21 seconds
Started	Apr 23 04:49:51 PM PDT 24
Finished	Apr 23 04:50:59 PM PDT 24
Peak memory	562812 kb
Host	smart-47cd728e-6de8-4cf8-8ece-d0506a469ec5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491993682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1491993682
Directory	/workspace/92.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.746186930
Short name	T1435
Test name
Test status
Simulation time	395976391 ps
CPU time	34.19 seconds
Started	Apr 23 04:49:49 PM PDT 24
Finished	Apr 23 04:50:24 PM PDT 24
Peak memory	562676 kb
Host	smart-82801a7e-e5f8-4278-bb10-b2432c1d9c40
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746186930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_dela ys.746186930
Directory	/workspace/92.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_same_source.291990111
Short name	T2026
Test name
Test status
Simulation time	2671137302 ps
CPU time	75.22 seconds
Started	Apr 23 04:49:50 PM PDT 24
Finished	Apr 23 04:51:05 PM PDT 24
Peak memory	562764 kb
Host	smart-011c3272-4260-4e47-b2d6-33931ea2a9c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291990111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.291990111
Directory	/workspace/92.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke.1432734169
Short name	T1290
Test name
Test status
Simulation time	48536184 ps
CPU time	6.41 seconds
Started	Apr 23 04:49:44 PM PDT 24
Finished	Apr 23 04:49:51 PM PDT 24
Peak memory	562680 kb
Host	smart-17fc3c1e-5851-4e15-a112-e23a630c1935
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432734169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.1432734169
Directory	/workspace/92.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3638982685
Short name	T2514
Test name
Test status
Simulation time	7838112965 ps
CPU time	83.51 seconds
Started	Apr 23 04:49:43 PM PDT 24
Finished	Apr 23 04:51:07 PM PDT 24
Peak memory	562716 kb
Host	smart-e88560dc-7792-44b7-9584-37e5a601123c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638982685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.3638982685
Directory	/workspace/92.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.726082624
Short name	T2341
Test name
Test status
Simulation time	4725822080 ps
CPU time	84.32 seconds
Started	Apr 23 04:49:48 PM PDT 24
Finished	Apr 23 04:51:13 PM PDT 24
Peak memory	562808 kb
Host	smart-157fbeef-722e-4e0a-b995-966eb5d4d97c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726082624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.726082624
Directory	/workspace/92.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1554299729
Short name	T1627
Test name
Test status
Simulation time	43660098 ps
CPU time	6.52 seconds
Started	Apr 23 04:49:43 PM PDT 24
Finished	Apr 23 04:49:50 PM PDT 24
Peak memory	562712 kb
Host	smart-bacf6f4b-785a-4788-b35c-beedbb606c66
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554299729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.1554299729
Directory	/workspace/92.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all.2713378357
Short name	T2699
Test name
Test status
Simulation time	4469399091 ps
CPU time	177.73 seconds
Started	Apr 23 04:49:51 PM PDT 24
Finished	Apr 23 04:52:49 PM PDT 24
Peak memory	563900 kb
Host	smart-1bf77d4d-373a-4f29-9adc-72e10c370c79
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713378357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2713378357
Directory	/workspace/92.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.1239502783
Short name	T2723
Test name
Test status
Simulation time	11240652073 ps
CPU time	368.71 seconds
Started	Apr 23 04:49:54 PM PDT 24
Finished	Apr 23 04:56:03 PM PDT 24
Peak memory	563980 kb
Host	smart-02f12589-6c94-447c-b85e-a8ddc7825398
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239502783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.1239502783
Directory	/workspace/92.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.3774911848
Short name	T2598
Test name
Test status
Simulation time	4421401205 ps
CPU time	282.01 seconds
Started	Apr 23 04:49:51 PM PDT 24
Finished	Apr 23 04:54:33 PM PDT 24
Peak memory	563948 kb
Host	smart-3ca61160-9cb6-4653-a905-03561da9c950
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774911848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.3774911848
Directory	/workspace/92.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.434020322
Short name	T2606
Test name
Test status
Simulation time	67615981 ps
CPU time	32.78 seconds
Started	Apr 23 04:49:55 PM PDT 24
Finished	Apr 23 04:50:28 PM PDT 24
Peak memory	562908 kb
Host	smart-7fad6d49-62f8-46c5-9a8f-188e97f53d76
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434020322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_reset_error.434020322
Directory	/workspace/92.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.956558755
Short name	T2337
Test name
Test status
Simulation time	937764620 ps
CPU time	38.57 seconds
Started	Apr 23 04:49:51 PM PDT 24
Finished	Apr 23 04:50:30 PM PDT 24
Peak memory	562804 kb
Host	smart-edba1599-6a4d-437d-9f34-7739e75ba525
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956558755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.956558755
Directory	/workspace/92.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_access_same_device.2870625991
Short name	T2515
Test name
Test status
Simulation time	86955072 ps
CPU time	9.3 seconds
Started	Apr 23 04:50:00 PM PDT 24
Finished	Apr 23 04:50:10 PM PDT 24
Peak memory	562732 kb
Host	smart-b7766dd0-835a-4cb4-961b-6488cfd53ff3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870625991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .2870625991
Directory	/workspace/93.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.764014054
Short name	T1438
Test name
Test status
Simulation time	27206396748 ps
CPU time	477.88 seconds
Started	Apr 23 04:50:00 PM PDT 24
Finished	Apr 23 04:57:58 PM PDT 24
Peak memory	562860 kb
Host	smart-9c4bf718-c567-4dab-88ac-e37957b2a81c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764014054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_d evice_slow_rsp.764014054
Directory	/workspace/93.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2399000394
Short name	T1800
Test name
Test status
Simulation time	206211844 ps
CPU time	10.93 seconds
Started	Apr 23 04:50:00 PM PDT 24
Finished	Apr 23 04:50:11 PM PDT 24
Peak memory	562716 kb
Host	smart-b7ce7d95-791c-4ab7-ae49-94e294852bdc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399000394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.2399000394
Directory	/workspace/93.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_error_random.3677655500
Short name	T1869
Test name
Test status
Simulation time	497359710 ps
CPU time	20.09 seconds
Started	Apr 23 04:49:59 PM PDT 24
Finished	Apr 23 04:50:20 PM PDT 24
Peak memory	562708 kb
Host	smart-fae4a7d7-3e2e-41f0-b519-611090e647e9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677655500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.3677655500
Directory	/workspace/93.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_random.2800198557
Short name	T1606
Test name
Test status
Simulation time	1327090131 ps
CPU time	48.12 seconds
Started	Apr 23 04:50:04 PM PDT 24
Finished	Apr 23 04:50:52 PM PDT 24
Peak memory	562748 kb
Host	smart-af327712-a659-47d2-9e32-2a1257dadbbc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800198557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.2800198557
Directory	/workspace/93.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_random_large_delays.2412115879
Short name	T1262
Test name
Test status
Simulation time	16138698951 ps
CPU time	171.15 seconds
Started	Apr 23 04:50:01 PM PDT 24
Finished	Apr 23 04:52:53 PM PDT 24
Peak memory	562784 kb
Host	smart-562532fb-b248-44d0-9ad2-d7b944626f7e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412115879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.2412115879
Directory	/workspace/93.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3970141351
Short name	T1891
Test name
Test status
Simulation time	28084135237 ps
CPU time	515.98 seconds
Started	Apr 23 04:50:06 PM PDT 24
Finished	Apr 23 04:58:42 PM PDT 24
Peak memory	562820 kb
Host	smart-08c494a1-7051-4dca-82ef-2fc349500579
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970141351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3970141351
Directory	/workspace/93.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.1150587206
Short name	T1658
Test name
Test status
Simulation time	440942817 ps
CPU time	36.25 seconds
Started	Apr 23 04:49:58 PM PDT 24
Finished	Apr 23 04:50:35 PM PDT 24
Peak memory	562756 kb
Host	smart-a99386ea-8663-46d9-b9f6-42e462d16a1a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150587206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.1150587206
Directory	/workspace/93.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_same_source.903838903
Short name	T1801
Test name
Test status
Simulation time	519613522 ps
CPU time	38.91 seconds
Started	Apr 23 04:50:06 PM PDT 24
Finished	Apr 23 04:50:45 PM PDT 24
Peak memory	562724 kb
Host	smart-140401fb-40f9-4231-83e3-46d1572f02ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903838903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.903838903
Directory	/workspace/93.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke.234435685
Short name	T1590
Test name
Test status
Simulation time	52887823 ps
CPU time	6.54 seconds
Started	Apr 23 04:49:56 PM PDT 24
Finished	Apr 23 04:50:03 PM PDT 24
Peak memory	562676 kb
Host	smart-35cc11a0-dace-4f7c-bcc9-9fefb8dc7af7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234435685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.234435685
Directory	/workspace/93.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.2823100641
Short name	T2139
Test name
Test status
Simulation time	8099949249 ps
CPU time	92.75 seconds
Started	Apr 23 04:49:55 PM PDT 24
Finished	Apr 23 04:51:28 PM PDT 24
Peak memory	562704 kb
Host	smart-ee17ca11-d639-4120-ae6c-dbfe7eed1aa6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823100641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2823100641
Directory	/workspace/93.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.261651854
Short name	T2560
Test name
Test status
Simulation time	4531622899 ps
CPU time	79.96 seconds
Started	Apr 23 04:50:00 PM PDT 24
Finished	Apr 23 04:51:21 PM PDT 24
Peak memory	562756 kb
Host	smart-a83806e5-99d9-4ac8-81c6-cf273f307cea
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261651854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.261651854
Directory	/workspace/93.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2325107072
Short name	T1762
Test name
Test status
Simulation time	44996555 ps
CPU time	6.42 seconds
Started	Apr 23 04:49:54 PM PDT 24
Finished	Apr 23 04:50:01 PM PDT 24
Peak memory	562708 kb
Host	smart-e4d5888c-ff67-4ae1-a3e1-598c27b6f63a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325107072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.2325107072
Directory	/workspace/93.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all.2224485509
Short name	T444
Test name
Test status
Simulation time	11062027984 ps
CPU time	494.84 seconds
Started	Apr 23 04:50:04 PM PDT 24
Finished	Apr 23 04:58:19 PM PDT 24
Peak memory	563948 kb
Host	smart-85bb54c5-a0d3-4d3e-a6b7-14deef098011
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224485509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2224485509
Directory	/workspace/93.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.2637713904
Short name	T784
Test name
Test status
Simulation time	16871587418 ps
CPU time	579.45 seconds
Started	Apr 23 04:50:07 PM PDT 24
Finished	Apr 23 04:59:46 PM PDT 24
Peak memory	564000 kb
Host	smart-0bf21cdf-db82-4aa1-bdd7-68627b6f8303
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637713904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.2637713904
Directory	/workspace/93.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3424559178
Short name	T821
Test name
Test status
Simulation time	7268497700 ps
CPU time	477.51 seconds
Started	Apr 23 04:50:01 PM PDT 24
Finished	Apr 23 04:57:59 PM PDT 24
Peak memory	572216 kb
Host	smart-f7f4bf4b-91e2-420e-8f2e-5fbb4d575652
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424559178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3424559178
Directory	/workspace/93.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.26609119
Short name	T1552
Test name
Test status
Simulation time	6127406325 ps
CPU time	604.81 seconds
Started	Apr 23 04:50:03 PM PDT 24
Finished	Apr 23 05:00:08 PM PDT 24
Peak memory	572200 kb
Host	smart-aa77744e-a523-46df-b96c-aa8984871c61
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26609119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_ with_reset_error.26609119
Directory	/workspace/93.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.2393409425
Short name	T2742
Test name
Test status
Simulation time	137321981 ps
CPU time	9.31 seconds
Started	Apr 23 04:49:58 PM PDT 24
Finished	Apr 23 04:50:08 PM PDT 24
Peak memory	562764 kb
Host	smart-0fa36167-0dc8-45e0-8a0b-cd67f1e124ed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393409425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.2393409425
Directory	/workspace/93.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_access_same_device.4205775239
Short name	T2613
Test name
Test status
Simulation time	1714303500 ps
CPU time	84.25 seconds
Started	Apr 23 04:50:05 PM PDT 24
Finished	Apr 23 04:51:30 PM PDT 24
Peak memory	562780 kb
Host	smart-430e8fb6-2225-4452-a3f6-e439b009137a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205775239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .4205775239
Directory	/workspace/94.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1920743132
Short name	T1971
Test name
Test status
Simulation time	109045617113 ps
CPU time	1916.33 seconds
Started	Apr 23 04:50:07 PM PDT 24
Finished	Apr 23 05:22:04 PM PDT 24
Peak memory	562852 kb
Host	smart-53b238f3-9aa2-413e-847d-deb1d2cd7d6c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920743132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.1920743132
Directory	/workspace/94.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3427135677
Short name	T2195
Test name
Test status
Simulation time	89331224 ps
CPU time	12.26 seconds
Started	Apr 23 04:50:08 PM PDT 24
Finished	Apr 23 04:50:20 PM PDT 24
Peak memory	562680 kb
Host	smart-7a3cddc4-b6bc-4d21-89cb-6747dc2acb32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427135677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.3427135677
Directory	/workspace/94.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_error_random.3114207028
Short name	T2273
Test name
Test status
Simulation time	1561822997 ps
CPU time	53.95 seconds
Started	Apr 23 04:50:04 PM PDT 24
Finished	Apr 23 04:50:58 PM PDT 24
Peak memory	562688 kb
Host	smart-4aa8b8d8-c8c7-491c-b542-4afd813a887c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114207028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.3114207028
Directory	/workspace/94.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_random.3219386632
Short name	T2063
Test name
Test status
Simulation time	618512996 ps
CPU time	50.89 seconds
Started	Apr 23 04:50:00 PM PDT 24
Finished	Apr 23 04:50:52 PM PDT 24
Peak memory	562784 kb
Host	smart-99ab1a16-53e4-4ee0-8202-66a7b3efa122
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219386632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.3219386632
Directory	/workspace/94.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_random_large_delays.3245565082
Short name	T2481
Test name
Test status
Simulation time	17553491286 ps
CPU time	187.51 seconds
Started	Apr 23 04:50:09 PM PDT 24
Finished	Apr 23 04:53:17 PM PDT 24
Peak memory	562804 kb
Host	smart-8cfa3048-fa5c-4cab-a82f-f7da25f40563
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245565082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.3245565082
Directory	/workspace/94.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.4287221502
Short name	T2464
Test name
Test status
Simulation time	7680174917 ps
CPU time	144.84 seconds
Started	Apr 23 04:50:05 PM PDT 24
Finished	Apr 23 04:52:30 PM PDT 24
Peak memory	562760 kb
Host	smart-e655caf2-5427-4246-8546-f6e8ffffdc48
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287221502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.4287221502
Directory	/workspace/94.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.1186658295
Short name	T2786
Test name
Test status
Simulation time	375227544 ps
CPU time	39.1 seconds
Started	Apr 23 04:50:07 PM PDT 24
Finished	Apr 23 04:50:46 PM PDT 24
Peak memory	562720 kb
Host	smart-ce0aec3f-10ea-470e-8760-1f195d31fb7c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186658295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.1186658295
Directory	/workspace/94.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_same_source.4005132578
Short name	T2022
Test name
Test status
Simulation time	2501465315 ps
CPU time	85 seconds
Started	Apr 23 04:50:06 PM PDT 24
Finished	Apr 23 04:51:32 PM PDT 24
Peak memory	562804 kb
Host	smart-a5af203d-9c6a-42f2-a3cb-351a6a6aaf20
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005132578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.4005132578
Directory	/workspace/94.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke.3776674614
Short name	T1728
Test name
Test status
Simulation time	173845916 ps
CPU time	8.35 seconds
Started	Apr 23 04:50:07 PM PDT 24
Finished	Apr 23 04:50:15 PM PDT 24
Peak memory	562724 kb
Host	smart-6323af79-0dff-4565-8d74-129974e2e965
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776674614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3776674614
Directory	/workspace/94.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.3620548096
Short name	T1474
Test name
Test status
Simulation time	9728904128 ps
CPU time	101.51 seconds
Started	Apr 23 04:50:02 PM PDT 24
Finished	Apr 23 04:51:44 PM PDT 24
Peak memory	562780 kb
Host	smart-b8db5eb0-c36d-4d2b-87e2-c715dbf4bfa5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620548096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.3620548096
Directory	/workspace/94.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.172598971
Short name	T2553
Test name
Test status
Simulation time	6711811888 ps
CPU time	114.82 seconds
Started	Apr 23 04:50:02 PM PDT 24
Finished	Apr 23 04:51:57 PM PDT 24
Peak memory	562744 kb
Host	smart-f8d70fdd-33e9-49dd-a169-14a7fdccb81b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172598971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.172598971
Directory	/workspace/94.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.4036256056
Short name	T2605
Test name
Test status
Simulation time	48923299 ps
CPU time	6.48 seconds
Started	Apr 23 04:50:05 PM PDT 24
Finished	Apr 23 04:50:12 PM PDT 24
Peak memory	562672 kb
Host	smart-77dea701-e7cd-4bb7-b98a-55e55d5c1eaf
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036256056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.4036256056
Directory	/workspace/94.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all.334523855
Short name	T2593
Test name
Test status
Simulation time	11556452102 ps
CPU time	397.94 seconds
Started	Apr 23 04:50:08 PM PDT 24
Finished	Apr 23 04:56:46 PM PDT 24
Peak memory	563488 kb
Host	smart-7b0df0ba-e4ef-40c5-bca5-4d9bbdb1d532
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334523855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.334523855
Directory	/workspace/94.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2869548753
Short name	T2697
Test name
Test status
Simulation time	8091455909 ps
CPU time	298.07 seconds
Started	Apr 23 04:50:13 PM PDT 24
Finished	Apr 23 04:55:11 PM PDT 24
Peak memory	562952 kb
Host	smart-5cb5b79c-93bf-4745-956e-7b339d381cd2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869548753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2869548753
Directory	/workspace/94.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3174166142
Short name	T1664
Test name
Test status
Simulation time	343206985 ps
CPU time	101.4 seconds
Started	Apr 23 04:50:07 PM PDT 24
Finished	Apr 23 04:51:49 PM PDT 24
Peak memory	563892 kb
Host	smart-9899d524-8a18-489e-a22b-7eedd3fe2aca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174166142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.3174166142
Directory	/workspace/94.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3853043606
Short name	T1380
Test name
Test status
Simulation time	97973520 ps
CPU time	35.55 seconds
Started	Apr 23 04:50:07 PM PDT 24
Finished	Apr 23 04:50:43 PM PDT 24
Peak memory	563264 kb
Host	smart-05f1db66-9ed9-4fb5-81c9-89f577732d1e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853043606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.3853043606
Directory	/workspace/94.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.75991496
Short name	T1970
Test name
Test status
Simulation time	195304444 ps
CPU time	27.23 seconds
Started	Apr 23 04:50:09 PM PDT 24
Finished	Apr 23 04:50:36 PM PDT 24
Peak memory	562768 kb
Host	smart-28c5e543-0222-4ed6-bc87-f3abdae149d7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75991496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.75991496
Directory	/workspace/94.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_access_same_device.2524097426
Short name	T2095
Test name
Test status
Simulation time	1012599747 ps
CPU time	78.75 seconds
Started	Apr 23 04:50:19 PM PDT 24
Finished	Apr 23 04:51:38 PM PDT 24
Peak memory	562740 kb
Host	smart-6e13e61f-ffa1-4866-99fa-5fc8fb5e87ce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524097426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .2524097426
Directory	/workspace/95.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1004621052
Short name	T2523
Test name
Test status
Simulation time	89076821201 ps
CPU time	1533.89 seconds
Started	Apr 23 04:50:14 PM PDT 24
Finished	Apr 23 05:15:48 PM PDT 24
Peak memory	562912 kb
Host	smart-a482e594-67de-4c7e-b8e3-996c84c6edfd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004621052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.1004621052
Directory	/workspace/95.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.1766176225
Short name	T1508
Test name
Test status
Simulation time	99147498 ps
CPU time	14.55 seconds
Started	Apr 23 04:50:18 PM PDT 24
Finished	Apr 23 04:50:32 PM PDT 24
Peak memory	562704 kb
Host	smart-46b3cbe8-e3a6-49d4-95a7-a2c11a8cd7ef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766176225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.1766176225
Directory	/workspace/95.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_error_random.1839544123
Short name	T1680
Test name
Test status
Simulation time	35355972 ps
CPU time	6.07 seconds
Started	Apr 23 04:50:13 PM PDT 24
Finished	Apr 23 04:50:20 PM PDT 24
Peak memory	562700 kb
Host	smart-e6d67800-db70-48cd-b1ea-e3b1525200ce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839544123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1839544123
Directory	/workspace/95.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_random.2652986099
Short name	T2019
Test name
Test status
Simulation time	154302877 ps
CPU time	9.13 seconds
Started	Apr 23 04:50:10 PM PDT 24
Finished	Apr 23 04:50:19 PM PDT 24
Peak memory	562740 kb
Host	smart-a21a5492-d8ef-4263-9734-0a40a04e6d91
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652986099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2652986099
Directory	/workspace/95.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_random_large_delays.456180960
Short name	T1464
Test name
Test status
Simulation time	30688237534 ps
CPU time	325.71 seconds
Started	Apr 23 04:50:11 PM PDT 24
Finished	Apr 23 04:55:37 PM PDT 24
Peak memory	562772 kb
Host	smart-19cd0277-db0e-493b-85e9-3145f916f872
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456180960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.456180960
Directory	/workspace/95.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.3723029241
Short name	T1798
Test name
Test status
Simulation time	18859702528 ps
CPU time	338.25 seconds
Started	Apr 23 04:50:11 PM PDT 24
Finished	Apr 23 04:55:50 PM PDT 24
Peak memory	562804 kb
Host	smart-2d33ada5-3b93-4007-bda6-2708da4691de
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723029241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.3723029241
Directory	/workspace/95.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.511944144
Short name	T1533
Test name
Test status
Simulation time	383321827 ps
CPU time	41.02 seconds
Started	Apr 23 04:50:14 PM PDT 24
Finished	Apr 23 04:50:56 PM PDT 24
Peak memory	562708 kb
Host	smart-83f8c04d-1294-4e22-b840-30b422f09697
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511944144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_dela ys.511944144
Directory	/workspace/95.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_same_source.3770370002
Short name	T482
Test name
Test status
Simulation time	1408133706 ps
CPU time	41.34 seconds
Started	Apr 23 04:50:16 PM PDT 24
Finished	Apr 23 04:50:57 PM PDT 24
Peak memory	562704 kb
Host	smart-66f3ceaa-f3eb-4f04-8c4b-f6fedaa2360d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770370002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.3770370002
Directory	/workspace/95.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke.876467620
Short name	T2233
Test name
Test status
Simulation time	195536759 ps
CPU time	9.65 seconds
Started	Apr 23 04:50:12 PM PDT 24
Finished	Apr 23 04:50:22 PM PDT 24
Peak memory	562712 kb
Host	smart-756557d3-4982-4fb9-83a8-cbe62cebda1f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876467620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.876467620
Directory	/workspace/95.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.33762338
Short name	T1469
Test name
Test status
Simulation time	5842814478 ps
CPU time	63.97 seconds
Started	Apr 23 04:50:15 PM PDT 24
Finished	Apr 23 04:51:19 PM PDT 24
Peak memory	562764 kb
Host	smart-3a7d93c2-dd0d-42ee-a25f-6d0d35816c11
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33762338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.33762338
Directory	/workspace/95.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.598460754
Short name	T2504
Test name
Test status
Simulation time	4591199406 ps
CPU time	86.16 seconds
Started	Apr 23 04:50:12 PM PDT 24
Finished	Apr 23 04:51:38 PM PDT 24
Peak memory	562788 kb
Host	smart-6496f408-10bd-45b8-a296-81db7cd6d07c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598460754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.598460754
Directory	/workspace/95.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3024765108
Short name	T2695
Test name
Test status
Simulation time	56676742 ps
CPU time	7.12 seconds
Started	Apr 23 04:50:14 PM PDT 24
Finished	Apr 23 04:50:21 PM PDT 24
Peak memory	562704 kb
Host	smart-dff25470-2a47-4d07-94bd-ba4a2b57c09c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024765108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.3024765108
Directory	/workspace/95.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all.4226862819
Short name	T446
Test name
Test status
Simulation time	3219735345 ps
CPU time	272.96 seconds
Started	Apr 23 04:50:21 PM PDT 24
Finished	Apr 23 04:54:55 PM PDT 24
Peak memory	572152 kb
Host	smart-fb07e11f-53d3-418b-8e89-af7dafac3be4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226862819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.4226862819
Directory	/workspace/95.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.920524742
Short name	T1911
Test name
Test status
Simulation time	6138401441 ps
CPU time	232.19 seconds
Started	Apr 23 04:50:18 PM PDT 24
Finished	Apr 23 04:54:11 PM PDT 24
Peak memory	562920 kb
Host	smart-c002e5a5-8502-4cf0-b6ae-3cf61a684ded
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920524742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.920524742
Directory	/workspace/95.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.1849755320
Short name	T1470
Test name
Test status
Simulation time	265760923 ps
CPU time	93.04 seconds
Started	Apr 23 04:50:17 PM PDT 24
Finished	Apr 23 04:51:50 PM PDT 24
Peak memory	563908 kb
Host	smart-878375cb-30f1-4e56-8a48-dedd1809a25d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849755320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.1849755320
Directory	/workspace/95.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1132098911
Short name	T1784
Test name
Test status
Simulation time	413994345 ps
CPU time	157.96 seconds
Started	Apr 23 04:50:22 PM PDT 24
Finished	Apr 23 04:53:00 PM PDT 24
Peak memory	563888 kb
Host	smart-03ba9b99-b236-42d6-9db9-f1b17d04de23
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132098911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.1132098911
Directory	/workspace/95.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.459739961
Short name	T2045
Test name
Test status
Simulation time	1361874427 ps
CPU time	63.76 seconds
Started	Apr 23 04:50:21 PM PDT 24
Finished	Apr 23 04:51:25 PM PDT 24
Peak memory	562784 kb
Host	smart-1dad66a0-b11e-4801-80b4-2e44cb2e03c0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459739961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.459739961
Directory	/workspace/95.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_access_same_device.4072831538
Short name	T2704
Test name
Test status
Simulation time	373897797 ps
CPU time	21.58 seconds
Started	Apr 23 04:50:24 PM PDT 24
Finished	Apr 23 04:50:46 PM PDT 24
Peak memory	562716 kb
Host	smart-e18deb7a-72f9-4213-a25b-2884b1076e93
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072831538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .4072831538
Directory	/workspace/96.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2748613152
Short name	T765
Test name
Test status
Simulation time	90414773160 ps
CPU time	1564.54 seconds
Started	Apr 23 04:50:25 PM PDT 24
Finished	Apr 23 05:16:30 PM PDT 24
Peak memory	562852 kb
Host	smart-594269b3-7dbb-46be-9702-4e184e598da4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748613152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.2748613152
Directory	/workspace/96.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.2080230938
Short name	T1288
Test name
Test status
Simulation time	34415863 ps
CPU time	7.56 seconds
Started	Apr 23 04:50:28 PM PDT 24
Finished	Apr 23 04:50:36 PM PDT 24
Peak memory	562720 kb
Host	smart-95ab415f-8336-423f-b2a1-59ac9998d990
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080230938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.2080230938
Directory	/workspace/96.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_error_random.3731417643
Short name	T1618
Test name
Test status
Simulation time	1703276243 ps
CPU time	56.49 seconds
Started	Apr 23 04:50:24 PM PDT 24
Finished	Apr 23 04:51:21 PM PDT 24
Peak memory	562640 kb
Host	smart-515e6b29-472e-4b88-a110-5c480b5e99cf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731417643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3731417643
Directory	/workspace/96.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_random.3270709860
Short name	T1584
Test name
Test status
Simulation time	203217861 ps
CPU time	24.61 seconds
Started	Apr 23 04:50:21 PM PDT 24
Finished	Apr 23 04:50:46 PM PDT 24
Peak memory	562768 kb
Host	smart-614e9284-9861-48db-8107-2777c472c093
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270709860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.3270709860
Directory	/workspace/96.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_random_large_delays.815835301
Short name	T2320
Test name
Test status
Simulation time	58595587364 ps
CPU time	688.32 seconds
Started	Apr 23 04:50:22 PM PDT 24
Finished	Apr 23 05:01:51 PM PDT 24
Peak memory	562776 kb
Host	smart-7055951a-b955-4e1a-92c2-e9bbffe5bfeb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815835301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.815835301
Directory	/workspace/96.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.995317834
Short name	T1345
Test name
Test status
Simulation time	30062085720 ps
CPU time	531.85 seconds
Started	Apr 23 04:50:27 PM PDT 24
Finished	Apr 23 04:59:19 PM PDT 24
Peak memory	562780 kb
Host	smart-f7ce8d11-af2a-4546-9e1d-8bb372141709
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995317834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.995317834
Directory	/workspace/96.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2164297148
Short name	T1577
Test name
Test status
Simulation time	470881967 ps
CPU time	46.9 seconds
Started	Apr 23 04:50:23 PM PDT 24
Finished	Apr 23 04:51:11 PM PDT 24
Peak memory	562720 kb
Host	smart-b8efb13f-a8f5-4ce7-b5f8-99d550d08db4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164297148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.2164297148
Directory	/workspace/96.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_same_source.922797335
Short name	T2769
Test name
Test status
Simulation time	502300053 ps
CPU time	18.59 seconds
Started	Apr 23 04:50:26 PM PDT 24
Finished	Apr 23 04:50:45 PM PDT 24
Peak memory	562748 kb
Host	smart-01154c61-d4ef-4029-bfba-6a78f414fd20
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922797335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.922797335
Directory	/workspace/96.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke.2017901338
Short name	T1763
Test name
Test status
Simulation time	198002008 ps
CPU time	8.85 seconds
Started	Apr 23 04:50:17 PM PDT 24
Finished	Apr 23 04:50:26 PM PDT 24
Peak memory	562680 kb
Host	smart-0f0a7113-6c33-49bd-bcf0-d1cfca87e5b6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017901338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.2017901338
Directory	/workspace/96.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.3879919106
Short name	T1360
Test name
Test status
Simulation time	6716394728 ps
CPU time	72.64 seconds
Started	Apr 23 04:50:22 PM PDT 24
Finished	Apr 23 04:51:35 PM PDT 24
Peak memory	562796 kb
Host	smart-a0e12f26-7de7-4b8a-9c23-780e21840fd4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879919106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.3879919106
Directory	/workspace/96.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.902625263
Short name	T591
Test name
Test status
Simulation time	4921842555 ps
CPU time	84.2 seconds
Started	Apr 23 04:50:17 PM PDT 24
Finished	Apr 23 04:51:42 PM PDT 24
Peak memory	562772 kb
Host	smart-62cf6e96-c0eb-4e41-8abb-d821c066c836
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902625263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.902625263
Directory	/workspace/96.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.4002200458
Short name	T1221
Test name
Test status
Simulation time	42264533 ps
CPU time	6.47 seconds
Started	Apr 23 04:50:17 PM PDT 24
Finished	Apr 23 04:50:23 PM PDT 24
Peak memory	562724 kb
Host	smart-d4850f8b-7487-4aa1-b575-34f67d47cf01
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002200458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.4002200458
Directory	/workspace/96.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all.1855161407
Short name	T563
Test name
Test status
Simulation time	2460556084 ps
CPU time	200.54 seconds
Started	Apr 23 04:50:29 PM PDT 24
Finished	Apr 23 04:53:50 PM PDT 24
Peak memory	564032 kb
Host	smart-2f23b94e-854d-4e5b-9264-77554fc6ec55
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855161407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.1855161407
Directory	/workspace/96.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.1373259076
Short name	T2292
Test name
Test status
Simulation time	20386837499 ps
CPU time	658.45 seconds
Started	Apr 23 04:50:31 PM PDT 24
Finished	Apr 23 05:01:30 PM PDT 24
Peak memory	563992 kb
Host	smart-a5dde626-e59b-44c0-9d63-e4ee61d18617
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373259076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.1373259076
Directory	/workspace/96.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2256689929
Short name	T2746
Test name
Test status
Simulation time	9229194206 ps
CPU time	359.41 seconds
Started	Apr 23 04:50:32 PM PDT 24
Finished	Apr 23 04:56:32 PM PDT 24
Peak memory	572244 kb
Host	smart-79b416f5-2cea-4d2c-99a6-7e6fa9080ccf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256689929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.2256689929
Directory	/workspace/96.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.797807934
Short name	T2367
Test name
Test status
Simulation time	964282603 ps
CPU time	43.19 seconds
Started	Apr 23 04:50:31 PM PDT 24
Finished	Apr 23 04:51:15 PM PDT 24
Peak memory	562792 kb
Host	smart-65fe9b25-872c-4092-948a-25d89c50e6c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797807934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.797807934
Directory	/workspace/96.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_access_same_device.3766145164
Short name	T1654
Test name
Test status
Simulation time	2311676945 ps
CPU time	112.97 seconds
Started	Apr 23 04:50:38 PM PDT 24
Finished	Apr 23 04:52:31 PM PDT 24
Peak memory	562868 kb
Host	smart-561d31cd-f6dc-4732-825e-c04222010333
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766145164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .3766145164
Directory	/workspace/97.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.2017904870
Short name	T782
Test name
Test status
Simulation time	63966978689 ps
CPU time	1106.46 seconds
Started	Apr 23 04:50:39 PM PDT 24
Finished	Apr 23 05:09:06 PM PDT 24
Peak memory	562816 kb
Host	smart-3dc4a0b3-df53-4b94-80b1-3d013df19d2e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017904870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.2017904870
Directory	/workspace/97.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3710577206
Short name	T2474
Test name
Test status
Simulation time	397220459 ps
CPU time	15.85 seconds
Started	Apr 23 04:50:40 PM PDT 24
Finished	Apr 23 04:50:57 PM PDT 24
Peak memory	562740 kb
Host	smart-df12eba1-d2bc-449b-af23-bdaaab7cda4f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710577206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.3710577206
Directory	/workspace/97.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_error_random.2538551027
Short name	T2079
Test name
Test status
Simulation time	120910855 ps
CPU time	12.69 seconds
Started	Apr 23 04:50:46 PM PDT 24
Finished	Apr 23 04:50:59 PM PDT 24
Peak memory	562624 kb
Host	smart-4d563e49-3528-47dd-91c4-7dc17a1c36fa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538551027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2538551027
Directory	/workspace/97.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_random.4193479741
Short name	T1486
Test name
Test status
Simulation time	274678809 ps
CPU time	24.83 seconds
Started	Apr 23 04:50:35 PM PDT 24
Finished	Apr 23 04:51:00 PM PDT 24
Peak memory	562712 kb
Host	smart-5f406a1e-7c7a-4388-8204-f85b1a8f41af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193479741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.4193479741
Directory	/workspace/97.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1486196750
Short name	T2344
Test name
Test status
Simulation time	101906782823 ps
CPU time	1157.78 seconds
Started	Apr 23 04:50:37 PM PDT 24
Finished	Apr 23 05:09:55 PM PDT 24
Peak memory	562824 kb
Host	smart-9cae49ac-6509-446b-bdb7-c84013cb0033
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486196750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1486196750
Directory	/workspace/97.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.2862311846
Short name	T2294
Test name
Test status
Simulation time	21240724666 ps
CPU time	353.85 seconds
Started	Apr 23 04:50:37 PM PDT 24
Finished	Apr 23 04:56:31 PM PDT 24
Peak memory	562796 kb
Host	smart-8ebcda0b-bb24-4423-b752-35d78a41c892
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862311846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.2862311846
Directory	/workspace/97.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.3523378368
Short name	T2442
Test name
Test status
Simulation time	431260237 ps
CPU time	36.72 seconds
Started	Apr 23 04:50:37 PM PDT 24
Finished	Apr 23 04:51:14 PM PDT 24
Peak memory	562752 kb
Host	smart-b53820ac-a86d-432e-b5d7-5cd6a5f58b2e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523378368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.3523378368
Directory	/workspace/97.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_same_source.2641076251
Short name	T2436
Test name
Test status
Simulation time	262003223 ps
CPU time	22.76 seconds
Started	Apr 23 04:50:42 PM PDT 24
Finished	Apr 23 04:51:05 PM PDT 24
Peak memory	562708 kb
Host	smart-e41874e0-5ebd-4c2b-98db-2946a078a470
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641076251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.2641076251
Directory	/workspace/97.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke.100714693
Short name	T2194
Test name
Test status
Simulation time	43484819 ps
CPU time	6.25 seconds
Started	Apr 23 04:50:30 PM PDT 24
Finished	Apr 23 04:50:37 PM PDT 24
Peak memory	562696 kb
Host	smart-969be948-246a-440a-ac06-4b190caf0d4e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100714693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.100714693
Directory	/workspace/97.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.279951496
Short name	T1839
Test name
Test status
Simulation time	6956065758 ps
CPU time	80.1 seconds
Started	Apr 23 04:50:36 PM PDT 24
Finished	Apr 23 04:51:57 PM PDT 24
Peak memory	562800 kb
Host	smart-47a8728f-e0ed-46f0-9f70-683328007052
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279951496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.279951496
Directory	/workspace/97.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1279747557
Short name	T2248
Test name
Test status
Simulation time	4499896545 ps
CPU time	81.96 seconds
Started	Apr 23 04:50:35 PM PDT 24
Finished	Apr 23 04:51:57 PM PDT 24
Peak memory	562780 kb
Host	smart-16660ad1-dbc6-4ba4-8ed1-f1ac6e948903
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279747557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.1279747557
Directory	/workspace/97.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.3184968330
Short name	T1564
Test name
Test status
Simulation time	41324066 ps
CPU time	6.06 seconds
Started	Apr 23 04:50:37 PM PDT 24
Finished	Apr 23 04:50:43 PM PDT 24
Peak memory	562684 kb
Host	smart-ba0f1f72-b5e7-4108-bad2-ec6b7b31f363
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184968330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.3184968330
Directory	/workspace/97.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all.2170466467
Short name	T424
Test name
Test status
Simulation time	18850675788 ps
CPU time	657.71 seconds
Started	Apr 23 04:50:47 PM PDT 24
Finished	Apr 23 05:01:45 PM PDT 24
Peak memory	563932 kb
Host	smart-4551b4e2-2ce8-4dfd-8a2a-3394d22d93a3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170466467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2170466467
Directory	/workspace/97.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3339456712
Short name	T766
Test name
Test status
Simulation time	1740254180 ps
CPU time	100.7 seconds
Started	Apr 23 04:50:44 PM PDT 24
Finished	Apr 23 04:52:25 PM PDT 24
Peak memory	570208 kb
Host	smart-5007140d-efe2-4821-9240-a878531777ad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339456712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3339456712
Directory	/workspace/97.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.2825140889
Short name	T420
Test name
Test status
Simulation time	299662309 ps
CPU time	159.09 seconds
Started	Apr 23 04:50:46 PM PDT 24
Finished	Apr 23 04:53:26 PM PDT 24
Peak memory	572060 kb
Host	smart-2d3e90f3-8324-454f-9551-b1a02a96e510
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825140889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.2825140889
Directory	/workspace/97.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1003860779
Short name	T1919
Test name
Test status
Simulation time	458887118 ps
CPU time	149.7 seconds
Started	Apr 23 04:50:45 PM PDT 24
Finished	Apr 23 04:53:16 PM PDT 24
Peak memory	563956 kb
Host	smart-858641a8-f652-4538-8e4c-10de7b640281
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003860779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.1003860779
Directory	/workspace/97.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.2279785417
Short name	T1746
Test name
Test status
Simulation time	279076644 ps
CPU time	28.81 seconds
Started	Apr 23 04:50:44 PM PDT 24
Finished	Apr 23 04:51:13 PM PDT 24
Peak memory	561924 kb
Host	smart-25e349b5-516c-45fc-a455-e550e4022952
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279785417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.2279785417
Directory	/workspace/97.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_access_same_device.3061701301
Short name	T802
Test name
Test status
Simulation time	667252901 ps
CPU time	30.65 seconds
Started	Apr 23 04:50:48 PM PDT 24
Finished	Apr 23 04:51:19 PM PDT 24
Peak memory	562768 kb
Host	smart-32d95ecf-0c55-4f1e-a8a9-421acc905018
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061701301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .3061701301
Directory	/workspace/98.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3381763784
Short name	T1715
Test name
Test status
Simulation time	67598195309 ps
CPU time	1187.37 seconds
Started	Apr 23 04:50:52 PM PDT 24
Finished	Apr 23 05:10:40 PM PDT 24
Peak memory	562840 kb
Host	smart-57141b76-e21e-42a3-8127-865cfa46cee9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381763784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.3381763784
Directory	/workspace/98.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.2474343475
Short name	T2653
Test name
Test status
Simulation time	366287155 ps
CPU time	16.63 seconds
Started	Apr 23 04:50:52 PM PDT 24
Finished	Apr 23 04:51:09 PM PDT 24
Peak memory	562752 kb
Host	smart-74e5dd9e-55dc-4b73-9aac-45f81776339b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474343475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.2474343475
Directory	/workspace/98.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_error_random.92223427
Short name	T1797
Test name
Test status
Simulation time	157336562 ps
CPU time	17.26 seconds
Started	Apr 23 04:50:52 PM PDT 24
Finished	Apr 23 04:51:10 PM PDT 24
Peak memory	562700 kb
Host	smart-d5e1a0d6-46ae-4934-b5e7-a52b1c2f0a72
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92223427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.92223427
Directory	/workspace/98.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_random.4200350916
Short name	T2186
Test name
Test status
Simulation time	38836297 ps
CPU time	7.25 seconds
Started	Apr 23 04:50:44 PM PDT 24
Finished	Apr 23 04:50:51 PM PDT 24
Peak memory	562756 kb
Host	smart-6918cd0b-da3e-4133-9baa-52efd2b04d90
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200350916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.4200350916
Directory	/workspace/98.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3795198449
Short name	T2566
Test name
Test status
Simulation time	99731477174 ps
CPU time	1167.78 seconds
Started	Apr 23 04:50:46 PM PDT 24
Finished	Apr 23 05:10:14 PM PDT 24
Peak memory	562852 kb
Host	smart-5693e278-fd49-4734-b4fb-33a5318b3d18
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795198449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.3795198449
Directory	/workspace/98.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.3991393709
Short name	T1948
Test name
Test status
Simulation time	12296823869 ps
CPU time	220.84 seconds
Started	Apr 23 04:50:49 PM PDT 24
Finished	Apr 23 04:54:30 PM PDT 24
Peak memory	562784 kb
Host	smart-823c6872-9f7a-4e92-8f7f-d2c2066a7754
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991393709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.3991393709
Directory	/workspace/98.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.2788218698
Short name	T2646
Test name
Test status
Simulation time	577324919 ps
CPU time	47.75 seconds
Started	Apr 23 04:50:45 PM PDT 24
Finished	Apr 23 04:51:34 PM PDT 24
Peak memory	562728 kb
Host	smart-8024c786-8234-44cf-acb8-a1eb2c87ec78
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788218698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.2788218698
Directory	/workspace/98.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_same_source.1682115707
Short name	T1712
Test name
Test status
Simulation time	549736609 ps
CPU time	36.57 seconds
Started	Apr 23 04:50:48 PM PDT 24
Finished	Apr 23 04:51:24 PM PDT 24
Peak memory	562756 kb
Host	smart-4ecb5694-7884-401b-af22-59bf99ae2df3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682115707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.1682115707
Directory	/workspace/98.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke.2961973889
Short name	T2350
Test name
Test status
Simulation time	229292667 ps
CPU time	10.31 seconds
Started	Apr 23 04:50:42 PM PDT 24
Finished	Apr 23 04:50:52 PM PDT 24
Peak memory	562696 kb
Host	smart-5620148c-edc7-484c-953a-b4a205bcc61d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961973889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.2961973889
Directory	/workspace/98.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3912587374
Short name	T598
Test name
Test status
Simulation time	9096515748 ps
CPU time	98.85 seconds
Started	Apr 23 04:50:44 PM PDT 24
Finished	Apr 23 04:52:23 PM PDT 24
Peak memory	562812 kb
Host	smart-877090a5-177c-45ca-90ee-802355275e6b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912587374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3912587374
Directory	/workspace/98.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1126749758
Short name	T2270
Test name
Test status
Simulation time	4147640685 ps
CPU time	74.62 seconds
Started	Apr 23 04:50:48 PM PDT 24
Finished	Apr 23 04:52:03 PM PDT 24
Peak memory	562728 kb
Host	smart-482ce3e1-4186-4e04-a95b-df7968412028
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126749758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1126749758
Directory	/workspace/98.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1440067384
Short name	T2271
Test name
Test status
Simulation time	47582297 ps
CPU time	6.73 seconds
Started	Apr 23 04:50:48 PM PDT 24
Finished	Apr 23 04:50:55 PM PDT 24
Peak memory	562664 kb
Host	smart-300900f5-a9cf-45d9-8e41-70349adb7d82
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440067384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.1440067384
Directory	/workspace/98.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all.2982262063
Short name	T1418
Test name
Test status
Simulation time	394223529 ps
CPU time	37.02 seconds
Started	Apr 23 04:50:50 PM PDT 24
Finished	Apr 23 04:51:27 PM PDT 24
Peak memory	562788 kb
Host	smart-78f9a2cd-5008-4561-bbe6-38b228654cbd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982262063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.2982262063
Directory	/workspace/98.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.2577512347
Short name	T1527
Test name
Test status
Simulation time	1112558213 ps
CPU time	41.26 seconds
Started	Apr 23 04:51:00 PM PDT 24
Finished	Apr 23 04:51:42 PM PDT 24
Peak memory	562712 kb
Host	smart-7429c44e-fb7e-4197-a1ca-0b69e8cf9959
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577512347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.2577512347
Directory	/workspace/98.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1817292228
Short name	T823
Test name
Test status
Simulation time	379009682 ps
CPU time	138.24 seconds
Started	Apr 23 04:50:51 PM PDT 24
Finished	Apr 23 04:53:10 PM PDT 24
Peak memory	563892 kb
Host	smart-f161bf48-d39f-40ef-870c-169f49dc4bd0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817292228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.1817292228
Directory	/workspace/98.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.2571651864
Short name	T2347
Test name
Test status
Simulation time	1009992710 ps
CPU time	207.19 seconds
Started	Apr 23 04:50:57 PM PDT 24
Finished	Apr 23 04:54:24 PM PDT 24
Peak memory	572088 kb
Host	smart-d47a2ce8-c9f0-4e28-9331-823aa7d4b346
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571651864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.2571651864
Directory	/workspace/98.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1911143830
Short name	T1661
Test name
Test status
Simulation time	240872466 ps
CPU time	33.02 seconds
Started	Apr 23 04:50:50 PM PDT 24
Finished	Apr 23 04:51:23 PM PDT 24
Peak memory	562756 kb
Host	smart-b327458a-d24e-4727-ae2a-ca6b464bbbb5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911143830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1911143830
Directory	/workspace/98.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_access_same_device.597725691
Short name	T805
Test name
Test status
Simulation time	1570796401 ps
CPU time	63.1 seconds
Started	Apr 23 04:51:05 PM PDT 24
Finished	Apr 23 04:52:08 PM PDT 24
Peak memory	562724 kb
Host	smart-a77511e8-6a08-42da-a8c3-c9d9bcacd6ca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597725691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device. 597725691
Directory	/workspace/99.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2707484922
Short name	T2279
Test name
Test status
Simulation time	66289222165 ps
CPU time	1074.47 seconds
Started	Apr 23 04:51:05 PM PDT 24
Finished	Apr 23 05:09:00 PM PDT 24
Peak memory	562864 kb
Host	smart-90f3659e-577a-417d-a475-c3cb123f7001
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707484922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.2707484922
Directory	/workspace/99.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.429519874
Short name	T1545
Test name
Test status
Simulation time	431315526 ps
CPU time	20.99 seconds
Started	Apr 23 04:51:03 PM PDT 24
Finished	Apr 23 04:51:24 PM PDT 24
Peak memory	562716 kb
Host	smart-4e507a57-d5f5-434b-b513-cd3d5d967388
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429519874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr .429519874
Directory	/workspace/99.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_error_random.280031333
Short name	T1696
Test name
Test status
Simulation time	2462706807 ps
CPU time	90.77 seconds
Started	Apr 23 04:51:01 PM PDT 24
Finished	Apr 23 04:52:32 PM PDT 24
Peak memory	562740 kb
Host	smart-72f8fd70-80a6-4824-83b0-b002c3db4118
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280031333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.280031333
Directory	/workspace/99.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_random.2377691507
Short name	T1999
Test name
Test status
Simulation time	1317126634 ps
CPU time	50.09 seconds
Started	Apr 23 04:51:00 PM PDT 24
Finished	Apr 23 04:51:51 PM PDT 24
Peak memory	562712 kb
Host	smart-35fd34e3-5812-4323-84c5-c963c3aa4995
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377691507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2377691507
Directory	/workspace/99.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_random_large_delays.436755751
Short name	T1516
Test name
Test status
Simulation time	41693310579 ps
CPU time	487.82 seconds
Started	Apr 23 04:50:59 PM PDT 24
Finished	Apr 23 04:59:08 PM PDT 24
Peak memory	562832 kb
Host	smart-54a8068e-6cce-4855-8c24-262a3a4aa4b3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436755751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.436755751
Directory	/workspace/99.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3659257175
Short name	T2363
Test name
Test status
Simulation time	59666887260 ps
CPU time	1102.11 seconds
Started	Apr 23 04:50:59 PM PDT 24
Finished	Apr 23 05:09:21 PM PDT 24
Peak memory	562896 kb
Host	smart-9b721ae3-1acf-4789-ac42-d03ec3cedef6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659257175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3659257175
Directory	/workspace/99.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.382848145
Short name	T2082
Test name
Test status
Simulation time	175670722 ps
CPU time	16.66 seconds
Started	Apr 23 04:50:55 PM PDT 24
Finished	Apr 23 04:51:13 PM PDT 24
Peak memory	562784 kb
Host	smart-a4577a95-2cac-43d4-982f-6a23da493805
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382848145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_dela ys.382848145
Directory	/workspace/99.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_same_source.2287638171
Short name	T1542
Test name
Test status
Simulation time	179437915 ps
CPU time	15.97 seconds
Started	Apr 23 04:51:04 PM PDT 24
Finished	Apr 23 04:51:21 PM PDT 24
Peak memory	562720 kb
Host	smart-ee535ac7-e919-442c-80f7-03f1b2b34aa8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287638171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2287638171
Directory	/workspace/99.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke.1366741902
Short name	T1942
Test name
Test status
Simulation time	49858874 ps
CPU time	6.58 seconds
Started	Apr 23 04:50:56 PM PDT 24
Finished	Apr 23 04:51:03 PM PDT 24
Peak memory	562748 kb
Host	smart-a50a46f7-e1a8-4b67-98c8-a1def57e8897
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366741902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.1366741902
Directory	/workspace/99.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.767610484
Short name	T1396
Test name
Test status
Simulation time	8851692079 ps
CPU time	102.98 seconds
Started	Apr 23 04:51:02 PM PDT 24
Finished	Apr 23 04:52:45 PM PDT 24
Peak memory	562776 kb
Host	smart-e40f2e4e-a14a-46fe-8309-0d0aeda72d3f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767610484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.767610484
Directory	/workspace/99.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2979653149
Short name	T1840
Test name
Test status
Simulation time	5419863314 ps
CPU time	95.77 seconds
Started	Apr 23 04:50:56 PM PDT 24
Finished	Apr 23 04:52:32 PM PDT 24
Peak memory	562760 kb
Host	smart-710e7e46-15b0-4b7d-a7c2-412ecf0172a2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979653149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2979653149
Directory	/workspace/99.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.4236620079
Short name	T2632
Test name
Test status
Simulation time	40542723 ps
CPU time	5.93 seconds
Started	Apr 23 04:50:55 PM PDT 24
Finished	Apr 23 04:51:01 PM PDT 24
Peak memory	562704 kb
Host	smart-b80f89f6-4b76-48ee-99da-43a83948584c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236620079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.4236620079
Directory	/workspace/99.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all.2435379153
Short name	T2371
Test name
Test status
Simulation time	12285443120 ps
CPU time	474.25 seconds
Started	Apr 23 04:51:01 PM PDT 24
Finished	Apr 23 04:58:56 PM PDT 24
Peak memory	563556 kb
Host	smart-1672e720-d212-4086-8be9-f93cf209a094
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435379153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.2435379153
Directory	/workspace/99.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.2390125084
Short name	T1660
Test name
Test status
Simulation time	2666338472 ps
CPU time	102.91 seconds
Started	Apr 23 04:51:06 PM PDT 24
Finished	Apr 23 04:52:49 PM PDT 24
Peak memory	562848 kb
Host	smart-5a3544dc-2c22-42c2-a94b-131dd192ff65
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390125084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.2390125084
Directory	/workspace/99.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.968704135
Short name	T2364
Test name
Test status
Simulation time	10320642026 ps
CPU time	679.91 seconds
Started	Apr 23 04:51:03 PM PDT 24
Finished	Apr 23 05:02:24 PM PDT 24
Peak memory	572232 kb
Host	smart-106f9b3a-191a-4a1e-bcad-7c52735659c1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968704135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_ with_rand_reset.968704135
Directory	/workspace/99.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3011427321
Short name	T1659
Test name
Test status
Simulation time	881908707 ps
CPU time	69.89 seconds
Started	Apr 23 04:51:02 PM PDT 24
Finished	Apr 23 04:52:12 PM PDT 24
Peak memory	563656 kb
Host	smart-2fe04524-8eb1-4246-b550-96cbe4b5c8d1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011427321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.3011427321
Directory	/workspace/99.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.1739525626
Short name	T1541
Test name
Test status
Simulation time	557356699 ps
CPU time	24.46 seconds
Started	Apr 23 04:50:58 PM PDT 24
Finished	Apr 23 04:51:23 PM PDT 24
Peak memory	562792 kb
Host	smart-96867516-010d-480c-9ffa-724a1c80a690
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739525626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.1739525626
Directory	/workspace/99.xbar_unmapped_addr/latest

Test location	/workspace/coverage/default/0.chip_jtag_mem_access.2169238024
Short name	T84
Test name
Test status
Simulation time	13284494728 ps
CPU time	1411.46 seconds
Started	Apr 23 03:45:56 PM PDT 24
Finished	Apr 23 04:09:29 PM PDT 24
Peak memory	599832 kb
Host	smart-7c77655a-254e-43c3-9925-06b2fb09c405
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169238024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2 169238024
Directory	/workspace/0.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/0.chip_sival_flash_info_access.1326822180
Short name	T1138
Test name
Test status
Simulation time	2553763710 ps
CPU time	225.8 seconds
Started	Apr 23 03:50:12 PM PDT 24
Finished	Apr 23 03:53:59 PM PDT 24
Peak memory	599916 kb
Host	smart-ab2020ab-045e-494c-94f2-1f273768beb5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1326822180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.1326822180
Directory	/workspace/0.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc.1454600126
Short name	T934
Test name
Test status
Simulation time	2692020616 ps
CPU time	181.29 seconds
Started	Apr 23 03:51:57 PM PDT 24
Finished	Apr 23 03:54:59 PM PDT 24
Peak memory	599920 kb
Host	smart-d9cc3d41-ef25-4496-9673-d82cefcf2c22
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454600126 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.1454600126
Directory	/workspace/0.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3483825702
Short name	T1121
Test name
Test status
Simulation time	2920116773 ps
CPU time	258.28 seconds
Started	Apr 23 03:52:54 PM PDT 24
Finished	Apr 23 03:57:13 PM PDT 24
Peak memory	599996 kb
Host	smart-9955f184-8ccd-49df-981e-6bb26f0beba5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483 825702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.3483825702
Directory	/workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1033263818
Short name	T1156
Test name
Test status
Simulation time	2969252187 ps
CPU time	244.31 seconds
Started	Apr 23 03:55:52 PM PDT 24
Finished	Apr 23 03:59:56 PM PDT 24
Peak memory	600224 kb
Host	smart-72319f5e-44c9-4c34-91aa-8c1d315d6708
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033263818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.1033263818
Directory	/workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_entropy.2273837699
Short name	T636
Test name
Test status
Simulation time	2443704744 ps
CPU time	217.88 seconds
Started	Apr 23 03:52:52 PM PDT 24
Finished	Apr 23 03:56:31 PM PDT 24
Peak memory	600164 kb
Host	smart-d431ddcd-03ee-488b-906c-a1e7bc87034c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273837699 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.2273837699
Directory	/workspace/0.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_idle.395076904
Short name	T837
Test name
Test status
Simulation time	2520761880 ps
CPU time	247.63 seconds
Started	Apr 23 03:51:43 PM PDT 24
Finished	Apr 23 03:55:51 PM PDT 24
Peak memory	599904 kb
Host	smart-2a3471f0-ec9d-4f5f-96d6-0afeea2611dd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395076904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.395076904
Directory	/workspace/0.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_masking_off.2461512292
Short name	T255
Test name
Test status
Simulation time	2993310333 ps
CPU time	332.84 seconds
Started	Apr 23 03:52:17 PM PDT 24
Finished	Apr 23 03:57:50 PM PDT 24
Peak memory	600476 kb
Host	smart-7859057a-1958-414f-963e-47a83814250a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461512292 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2461512292
Directory	/workspace/0.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_smoketest.2385787484
Short name	T1093
Test name
Test status
Simulation time	2688513950 ps
CPU time	340.7 seconds
Started	Apr 23 04:01:38 PM PDT 24
Finished	Apr 23 04:07:20 PM PDT 24
Peak memory	600152 kb
Host	smart-82ab2707-3e44-4aab-b53b-02c4bf2c2976
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385787484 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2385787484
Directory	/workspace/0.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.634357870
Short name	T1195
Test name
Test status
Simulation time	3412963770 ps
CPU time	297.1 seconds
Started	Apr 23 03:54:22 PM PDT 24
Finished	Apr 23 03:59:19 PM PDT 24
Peak memory	600744 kb
Host	smart-0d5861e5-b396-4035-a8c2-f7cc76ba27cb
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=634357870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.634357870
Directory	/workspace/0.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.841698873
Short name	T887
Test name
Test status
Simulation time	4370216240 ps
CPU time	493.57 seconds
Started	Apr 23 03:51:32 PM PDT 24
Finished	Apr 23 03:59:46 PM PDT 24
Peak memory	607456 kb
Host	smart-8a35526f-b82b-4cd0-9b65-2cba784f35cc
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=841698873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.841698873
Directory	/workspace/0.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3703087053
Short name	T203
Test name
Test status
Simulation time	6793689286 ps
CPU time	1163.58 seconds
Started	Apr 23 03:52:04 PM PDT 24
Finished	Apr 23 04:11:28 PM PDT 24
Peak memory	600264 kb
Host	smart-dd2abb45-455d-4614-8047-7cc463ce0ae6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703087053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.3703087053
Directory	/workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4126409283
Short name	T89
Test name
Test status
Simulation time	9392213920 ps
CPU time	943.46 seconds
Started	Apr 23 03:52:03 PM PDT 24
Finished	Apr 23 04:07:47 PM PDT 24
Peak memory	601768 kb
Host	smart-52edce80-b2fe-4b4c-9a56-e8f13edfdec6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126409283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.4126409283
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4088168626
Short name	T275
Test name
Test status
Simulation time	5912868460 ps
CPU time	541.01 seconds
Started	Apr 23 03:52:26 PM PDT 24
Finished	Apr 23 04:01:28 PM PDT 24
Peak memory	600216 kb
Host	smart-90d8c352-b834-4749-9543-6612fe640e04
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4088168626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.4088168626
Directory	/workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3940205879
Short name	T945
Test name
Test status
Simulation time	254553635904 ps
CPU time	13071.2 seconds
Started	Apr 23 03:51:39 PM PDT 24
Finished	Apr 23 07:29:32 PM PDT 24
Peak memory	601564 kb
Host	smart-d22abe0b-07fd-4fe3-9db1-a8108b5e05a8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940205879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3940205879
Directory	/workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_test.585098634
Short name	T64
Test name
Test status
Simulation time	2908825496 ps
CPU time	273.83 seconds
Started	Apr 23 03:52:56 PM PDT 24
Finished	Apr 23 03:57:31 PM PDT 24
Peak memory	600224 kb
Host	smart-bf98e750-3cb2-4a27-8cae-358e1659a6c8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585098634 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_alert_test.585098634
Directory	/workspace/0.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2805272164
Short name	T832
Test name
Test status
Simulation time	6369044894 ps
CPU time	487.02 seconds
Started	Apr 23 03:51:26 PM PDT 24
Finished	Apr 23 03:59:34 PM PDT 24
Peak memory	600492 kb
Host	smart-02094678-0f0a-45c9-af3d-142a327df27e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2805272164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2805272164
Directory	/workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1353417044
Short name	T859
Test name
Test status
Simulation time	2674414044 ps
CPU time	262.24 seconds
Started	Apr 23 04:01:42 PM PDT 24
Finished	Apr 23 04:06:05 PM PDT 24
Peak memory	599944 kb
Host	smart-5e1710df-aef3-45cc-ad9e-70cab3ab31f7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353417044 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.1353417044
Directory	/workspace/0.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1403802902
Short name	T1001
Test name
Test status
Simulation time	7852839524 ps
CPU time	665.4 seconds
Started	Apr 23 03:53:05 PM PDT 24
Finished	Apr 23 04:04:11 PM PDT 24
Peak memory	599412 kb
Host	smart-281b147d-1ea0-48ec-8f0c-b1b7c3d6c0be
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1403802902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1403802902
Directory	/workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3940557045
Short name	T1004
Test name
Test status
Simulation time	5675019050 ps
CPU time	598.46 seconds
Started	Apr 23 03:51:34 PM PDT 24
Finished	Apr 23 04:01:33 PM PDT 24
Peak memory	600504 kb
Host	smart-b264ef7f-48da-4ef1-b0ee-2f37c53596fd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3940557045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3940557045
Directory	/workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.261229552
Short name	T387
Test name
Test status
Simulation time	5886362744 ps
CPU time	834.14 seconds
Started	Apr 23 03:56:56 PM PDT 24
Finished	Apr 23 04:10:51 PM PDT 24
Peak memory	606564 kb
Host	smart-021961a6-c7e5-41e4-aead-b1d4f3608256
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261229552 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.261229552
Directory	/workspace/0.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4129998991
Short name	T840
Test name
Test status
Simulation time	5376009396 ps
CPU time	450.71 seconds
Started	Apr 23 03:56:06 PM PDT 24
Finished	Apr 23 04:03:38 PM PDT 24
Peak memory	611600 kb
Host	smart-3075bc38-f928-4e83-aed6-58a8830e1911
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=4129998991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.4129998991
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3323752805
Short name	T49
Test name
Test status
Simulation time	4659408432 ps
CPU time	539.61 seconds
Started	Apr 23 03:54:25 PM PDT 24
Finished	Apr 23 04:03:25 PM PDT 24
Peak memory	604308 kb
Host	smart-462671ac-f04d-44e2-896e-93429ed28e14
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323752805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3323752805
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3180961686
Short name	T1043
Test name
Test status
Simulation time	4013047976 ps
CPU time	524.96 seconds
Started	Apr 23 03:52:25 PM PDT 24
Finished	Apr 23 04:01:10 PM PDT 24
Peak memory	604232 kb
Host	smart-df2ea386-2431-47c5-b63f-c5bd60ab2d85
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180961686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3180961686
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2266491000
Short name	T894
Test name
Test status
Simulation time	5296950162 ps
CPU time	614.42 seconds
Started	Apr 23 03:53:46 PM PDT 24
Finished	Apr 23 04:04:01 PM PDT 24
Peak memory	604208 kb
Host	smart-feeb14c0-1c6c-481e-8c3c-23a385bd08b4
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266491000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2266491000
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3179379493
Short name	T862
Test name
Test status
Simulation time	4716888086 ps
CPU time	425.99 seconds
Started	Apr 23 03:52:15 PM PDT 24
Finished	Apr 23 03:59:22 PM PDT 24
Peak memory	604236 kb
Host	smart-375ff090-e743-43fa-b8fd-16305b114b54
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179379493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3179379493
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2233073990
Short name	T1132
Test name
Test status
Simulation time	5043942248 ps
CPU time	524.14 seconds
Started	Apr 23 03:53:23 PM PDT 24
Finished	Apr 23 04:02:08 PM PDT 24
Peak memory	604184 kb
Host	smart-816b7429-081c-4de0-860b-ea5e33de717b
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233073990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2233073990
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.768652063
Short name	T852
Test name
Test status
Simulation time	2787521561 ps
CPU time	290.09 seconds
Started	Apr 23 03:56:05 PM PDT 24
Finished	Apr 23 04:00:56 PM PDT 24
Peak memory	600136 kb
Host	smart-2a50890b-9514-4af6-b963-ac8f6ecc4288
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768652063 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_clkmgr_jitter.768652063
Directory	/workspace/0.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1722751215
Short name	T1181
Test name
Test status
Simulation time	3178452008 ps
CPU time	339.84 seconds
Started	Apr 23 03:53:37 PM PDT 24
Finished	Apr 23 03:59:18 PM PDT 24
Peak memory	599884 kb
Host	smart-e3e032f9-eaf1-4cc6-9c62-cacbf9089615
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722751215 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.1722751215
Directory	/workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2418914536
Short name	T1039
Test name
Test status
Simulation time	2894875821 ps
CPU time	144.6 seconds
Started	Apr 23 03:55:28 PM PDT 24
Finished	Apr 23 03:57:53 PM PDT 24
Peak memory	599936 kb
Host	smart-752b0041-54e1-48d7-9ba7-528eef8c017f
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418914536 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.2418914536
Directory	/workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2561631096
Short name	T960
Test name
Test status
Simulation time	5059274988 ps
CPU time	399.2 seconds
Started	Apr 23 03:53:43 PM PDT 24
Finished	Apr 23 04:00:23 PM PDT 24
Peak memory	600352 kb
Host	smart-d6a64a12-be70-437c-8baa-3d5dc50dafd2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561631096 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.2561631096
Directory	/workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3487978499
Short name	T942
Test name
Test status
Simulation time	4973721384 ps
CPU time	535.47 seconds
Started	Apr 23 03:57:14 PM PDT 24
Finished	Apr 23 04:06:11 PM PDT 24
Peak memory	599280 kb
Host	smart-cbca337f-7110-42f2-bd43-6d20c462e2b8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487978499 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.3487978499
Directory	/workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3431737948
Short name	T948
Test name
Test status
Simulation time	4456154062 ps
CPU time	388.48 seconds
Started	Apr 23 03:57:15 PM PDT 24
Finished	Apr 23 04:03:45 PM PDT 24
Peak memory	600188 kb
Host	smart-78ed1c72-b8e3-4eec-ab73-e75e11ee57bd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431737948 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.3431737948
Directory	/workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1783047459
Short name	T902
Test name
Test status
Simulation time	4604083446 ps
CPU time	414.77 seconds
Started	Apr 23 03:53:57 PM PDT 24
Finished	Apr 23 04:00:52 PM PDT 24
Peak memory	600296 kb
Host	smart-c057c072-5c54-48d5-b536-88f894850656
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783047459 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.1783047459
Directory	/workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.4034659187
Short name	T978
Test name
Test status
Simulation time	11715116612 ps
CPU time	975.94 seconds
Started	Apr 23 03:57:47 PM PDT 24
Finished	Apr 23 04:14:03 PM PDT 24
Peak memory	600444 kb
Host	smart-55b249c1-0661-4212-b7fb-a34585405466
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034659187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.4034659187
Directory	/workspace/0.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.65892890
Short name	T973
Test name
Test status
Simulation time	3439253304 ps
CPU time	311.62 seconds
Started	Apr 23 03:52:15 PM PDT 24
Finished	Apr 23 03:57:26 PM PDT 24
Peak memory	599872 kb
Host	smart-c5c7788d-8259-40c7-9f70-ca5faf4c509b
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65892890 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.65892890
Directory	/workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2618755312
Short name	T389
Test name
Test status
Simulation time	4188309510 ps
CPU time	460.92 seconds
Started	Apr 23 03:53:12 PM PDT 24
Finished	Apr 23 04:00:53 PM PDT 24
Peak memory	599908 kb
Host	smart-bc643e94-6b9e-475d-a119-823ce55668ac
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618755312 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.2618755312
Directory	/workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1600361185
Short name	T1067
Test name
Test status
Simulation time	2198916424 ps
CPU time	138.42 seconds
Started	Apr 23 04:01:09 PM PDT 24
Finished	Apr 23 04:03:27 PM PDT 24
Peak memory	599860 kb
Host	smart-f65833e8-ffe9-4b28-b554-3716340f8805
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600361185 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.1600361185
Directory	/workspace/0.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_coremark.2366155929
Short name	T926
Test name
Test status
Simulation time	50512981934 ps
CPU time	10148.6 seconds
Started	Apr 23 03:52:49 PM PDT 24
Finished	Apr 23 06:41:59 PM PDT 24
Peak memory	600464 kb
Host	smart-2886dd51-f26d-4fa0-8f55-bfc397a26b42
User	root
Command	/workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2366155929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.2366155929
Directory	/workspace/0.chip_sw_coremark/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2043179003
Short name	T1182
Test name
Test status
Simulation time	13434508912 ps
CPU time	3580.58 seconds
Started	Apr 23 03:55:05 PM PDT 24
Finished	Apr 23 04:54:46 PM PDT 24
Peak memory	600284 kb
Host	smart-b51f28cd-1b54-4d0c-9558-04e80366e84f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043179003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2043179003
Directory	/workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3275708520
Short name	T117
Test name
Test status
Simulation time	21462088243 ps
CPU time	3756.42 seconds
Started	Apr 23 03:56:06 PM PDT 24
Finished	Apr 23 04:58:44 PM PDT 24
Peak memory	600388 kb
Host	smart-a2f9b7cb-0df2-4566-ae91-8d102bb58858
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275708520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _csrng_edn_concurrency_reduced_freq.3275708520
Directory	/workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_kat_test.3967896556
Short name	T880
Test name
Test status
Simulation time	2556997774 ps
CPU time	187.79 seconds
Started	Apr 23 03:51:07 PM PDT 24
Finished	Apr 23 03:54:15 PM PDT 24
Peak memory	599920 kb
Host	smart-306b2da0-fb18-4425-a928-3a02c161b8a9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967896556 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3967896556
Directory	/workspace/0.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4239442276
Short name	T354
Test name
Test status
Simulation time	6748683850 ps
CPU time	510.79 seconds
Started	Apr 23 03:53:15 PM PDT 24
Finished	Apr 23 04:01:46 PM PDT 24
Peak memory	601792 kb
Host	smart-71dfbec9-9727-40f2-917b-187307e1cff9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239442276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.4239442276
Directory	/workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_smoketest.615236323
Short name	T1024
Test name
Test status
Simulation time	2753161192 ps
CPU time	245.62 seconds
Started	Apr 23 04:02:22 PM PDT 24
Finished	Apr 23 04:06:28 PM PDT 24
Peak memory	599816 kb
Host	smart-7cdf75ca-edad-44ca-b25a-6adef87066b0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615236323 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_csrng_smoketest.615236323
Directory	/workspace/0.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_auto_mode.2824752814
Short name	T613
Test name
Test status
Simulation time	4237354016 ps
CPU time	804.91 seconds
Started	Apr 23 03:51:53 PM PDT 24
Finished	Apr 23 04:05:18 PM PDT 24
Peak memory	600292 kb
Host	smart-d874ec8a-5a91-4e95-822d-aeafabcbd9dc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824752814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.2824752814
Directory	/workspace/0.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1929616168
Short name	T119
Test name
Test status
Simulation time	4725719866 ps
CPU time	658.59 seconds
Started	Apr 23 03:55:14 PM PDT 24
Finished	Apr 23 04:06:13 PM PDT 24
Peak memory	600420 kb
Host	smart-084b89c3-b81c-4f88-aca9-e42f7503b613
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929616168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.1929616168
Directory	/workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_kat.434282354
Short name	T882
Test name
Test status
Simulation time	3318363322 ps
CPU time	519.12 seconds
Started	Apr 23 03:53:48 PM PDT 24
Finished	Apr 23 04:02:28 PM PDT 24
Peak memory	605796 kb
Host	smart-49cb28e6-9f0b-46c5-b20e-9b13fe9a2e08
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434282354 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_edn_kat.434282354
Directory	/workspace/0.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_sw_mode.2149265780
Short name	T917
Test name
Test status
Simulation time	10961057080 ps
CPU time	2682.93 seconds
Started	Apr 23 03:52:08 PM PDT 24
Finished	Apr 23 04:36:51 PM PDT 24
Peak memory	600216 kb
Host	smart-e71a40f9-72c1-47c1-ad69-689ffa62beb8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149265780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.2149265780
Directory	/workspace/0.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2769317728
Short name	T359
Test name
Test status
Simulation time	2338820030 ps
CPU time	160.58 seconds
Started	Apr 23 03:52:48 PM PDT 24
Finished	Apr 23 03:55:29 PM PDT 24
Peak memory	599888 kb
Host	smart-c5f08976-db45-4353-afc9-28fa3968ff36
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27 69317728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2769317728
Directory	/workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.661892807
Short name	T1173
Test name
Test status
Simulation time	2602905500 ps
CPU time	185.06 seconds
Started	Apr 23 03:52:53 PM PDT 24
Finished	Apr 23 03:55:58 PM PDT 24
Peak memory	599976 kb
Host	smart-a83a6008-579d-414f-9c71-5b7e23c4a4ec
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661892807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.661892807
Directory	/workspace/0.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2942751352
Short name	T132
Test name
Test status
Simulation time	3590309088 ps
CPU time	390.91 seconds
Started	Apr 23 04:01:52 PM PDT 24
Finished	Apr 23 04:08:24 PM PDT 24
Peak memory	599948 kb
Host	smart-61710fc3-2b95-4f5d-ab58-a267cf9cb133
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2942751352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.2942751352
Directory	/workspace/0.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_example_concurrency.1343576391
Short name	T1077
Test name
Test status
Simulation time	3198027880 ps
CPU time	226.59 seconds
Started	Apr 23 03:50:17 PM PDT 24
Finished	Apr 23 03:54:04 PM PDT 24
Peak memory	599884 kb
Host	smart-88e532d9-d6e7-4af4-8720-bf2bf79834a0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343576391 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.1343576391
Directory	/workspace/0.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_example_flash.1003293920
Short name	T1118
Test name
Test status
Simulation time	2700556404 ps
CPU time	157.88 seconds
Started	Apr 23 03:50:36 PM PDT 24
Finished	Apr 23 03:53:15 PM PDT 24
Peak memory	599876 kb
Host	smart-082d215b-1d15-498f-af8a-51d00cff15b0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003293920 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.1003293920
Directory	/workspace/0.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/0.chip_sw_example_manufacturer.1904393644
Short name	T1213
Test name
Test status
Simulation time	2650976666 ps
CPU time	212.62 seconds
Started	Apr 23 03:51:48 PM PDT 24
Finished	Apr 23 03:55:21 PM PDT 24
Peak memory	599880 kb
Host	smart-1f7f8ad1-7482-48f4-bdf9-be05441ce16b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904393644 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.1904393644
Directory	/workspace/0.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/0.chip_sw_example_rom.2994055950
Short name	T114
Test name
Test status
Simulation time	2354895768 ps
CPU time	115.08 seconds
Started	Apr 23 03:49:23 PM PDT 24
Finished	Apr 23 03:51:19 PM PDT 24
Peak memory	598500 kb
Host	smart-b3ed919c-6c12-4d92-8f12-39dc77f5b71f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994055950 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.2994055950
Directory	/workspace/0.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_crash_alert.3349483298
Short name	T998
Test name
Test status
Simulation time	5541460800 ps
CPU time	523.94 seconds
Started	Apr 23 03:55:07 PM PDT 24
Finished	Apr 23 04:03:51 PM PDT 24
Peak memory	601996 kb
Host	smart-2240161f-bffd-4007-82a6-1ee7ab6d2787
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3349483298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.3349483298
Directory	/workspace/0.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2096108674
Short name	T291
Test name
Test status
Simulation time	5605138680 ps
CPU time	783.93 seconds
Started	Apr 23 03:50:58 PM PDT 24
Finished	Apr 23 04:04:03 PM PDT 24
Peak memory	600180 kb
Host	smart-619369e9-6f3a-4188-a075-e3e6a9483ea9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096108674 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.2096108674
Directory	/workspace/0.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3915712128
Short name	T110
Test name
Test status
Simulation time	6202598644 ps
CPU time	1003.78 seconds
Started	Apr 23 03:51:59 PM PDT 24
Finished	Apr 23 04:08:44 PM PDT 24
Peak memory	600152 kb
Host	smart-ccb874a2-ab51-48b8-90cc-664c2bab355d
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915712128 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.3915712128
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2791909475
Short name	T1016
Test name
Test status
Simulation time	6903197451 ps
CPU time	906.29 seconds
Started	Apr 23 03:55:20 PM PDT 24
Finished	Apr 23 04:10:27 PM PDT 24
Peak memory	600120 kb
Host	smart-2b2b5ac4-97d9-45a8-921e-9126b1d8f974
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791909475 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2791909475
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.912311897
Short name	T925
Test name
Test status
Simulation time	5882332916 ps
CPU time	1100.89 seconds
Started	Apr 23 03:51:52 PM PDT 24
Finished	Apr 23 04:10:14 PM PDT 24
Peak memory	600308 kb
Host	smart-7971b6c0-c299-427f-921a-c832142ec23c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912311897 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.912311897
Directory	/workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.390107753
Short name	T1110
Test name
Test status
Simulation time	3503378050 ps
CPU time	324.83 seconds
Started	Apr 23 03:51:30 PM PDT 24
Finished	Apr 23 03:56:55 PM PDT 24
Peak memory	599880 kb
Host	smart-7e3045cd-6a2e-470f-94c1-a035a68ac54f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390107753 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.390107753
Directory	/workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.473020119
Short name	T247
Test name
Test status
Simulation time	5327915696 ps
CPU time	937.82 seconds
Started	Apr 23 04:00:43 PM PDT 24
Finished	Apr 23 04:16:22 PM PDT 24
Peak memory	600168 kb
Host	smart-b7486d1b-7c77-4f9b-bb02-3eb94984a8ae
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473020119 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.473020119
Directory	/workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2921598899
Short name	T303
Test name
Test status
Simulation time	5043703552 ps
CPU time	580.43 seconds
Started	Apr 23 03:55:06 PM PDT 24
Finished	Apr 23 04:04:47 PM PDT 24
Peak memory	600252 kb
Host	smart-4cf1cbc2-ca05-4b22-a374-924947d0040e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2921598899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2921598899
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_init.1332416101
Short name	T174
Test name
Test status
Simulation time	23343734850 ps
CPU time	1866.14 seconds
Started	Apr 23 03:50:13 PM PDT 24
Finished	Apr 23 04:21:20 PM PDT 24
Peak memory	603564 kb
Host	smart-742cc467-1aef-431d-b8aa-bcff9305832c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332416101 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.1332416101
Directory	/workspace/0.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3119554027
Short name	T214
Test name
Test status
Simulation time	17355769051 ps
CPU time	1663.96 seconds
Started	Apr 23 03:53:59 PM PDT 24
Finished	Apr 23 04:21:44 PM PDT 24
Peak memory	606532 kb
Host	smart-2b464271-515b-4151-b4a1-86bbbc387b6a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3119554027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.3119554027
Directory	/workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.474284193
Short name	T188
Test name
Test status
Simulation time	2516230990 ps
CPU time	206.85 seconds
Started	Apr 23 03:58:46 PM PDT 24
Finished	Apr 23 04:02:13 PM PDT 24
Peak memory	599924 kb
Host	smart-9585d375-27b9-478d-bf87-c0ae9583aab1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=474284193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.474284193
Directory	/workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2080608915
Short name	T964
Test name
Test status
Simulation time	2968037134 ps
CPU time	254.76 seconds
Started	Apr 23 04:01:41 PM PDT 24
Finished	Apr 23 04:05:56 PM PDT 24
Peak memory	600296 kb
Host	smart-7da5e12e-8420-49a2-bb3b-982a3e43b1bc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080608915 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2080608915
Directory	/workspace/0.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc.1667335875
Short name	T850
Test name
Test status
Simulation time	2972040368 ps
CPU time	234.21 seconds
Started	Apr 23 03:52:57 PM PDT 24
Finished	Apr 23 03:56:52 PM PDT 24
Peak memory	599848 kb
Host	smart-f5b5a573-082e-4f8a-a102-6c5f139d9871
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667335875 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.1667335875
Directory	/workspace/0.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3051041191
Short name	T1071
Test name
Test status
Simulation time	2621754280 ps
CPU time	208.85 seconds
Started	Apr 23 03:55:57 PM PDT 24
Finished	Apr 23 03:59:26 PM PDT 24
Peak memory	599876 kb
Host	smart-d8e4af71-b02a-4372-8ba4-b8e44733799f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051041191 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.3051041191
Directory	/workspace/0.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.298734665
Short name	T1193
Test name
Test status
Simulation time	2148804859 ps
CPU time	202.04 seconds
Started	Apr 23 03:52:22 PM PDT 24
Finished	Apr 23 03:55:44 PM PDT 24
Peak memory	599984 kb
Host	smart-d4497198-07ab-4e3d-8459-ceb9cbbbd6e0
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298734665 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.298734665
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.413359734
Short name	T981
Test name
Test status
Simulation time	2623301107 ps
CPU time	210.01 seconds
Started	Apr 23 03:54:25 PM PDT 24
Finished	Apr 23 03:57:56 PM PDT 24
Peak memory	599984 kb
Host	smart-bf684d6e-b182-4086-b872-bab84f0b188a
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413359734 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.413359734
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1611557024
Short name	T991
Test name
Test status
Simulation time	2904311000 ps
CPU time	280.41 seconds
Started	Apr 23 04:01:39 PM PDT 24
Finished	Apr 23 04:06:20 PM PDT 24
Peak memory	599848 kb
Host	smart-373923d4-2caf-43db-80a5-b2f7d4130203
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611557024 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.1611557024
Directory	/workspace/0.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.193389754
Short name	T326
Test name
Test status
Simulation time	4258799868 ps
CPU time	469.72 seconds
Started	Apr 23 03:51:11 PM PDT 24
Finished	Apr 23 03:59:02 PM PDT 24
Peak memory	600904 kb
Host	smart-bf75186a-84ce-4750-a4fe-b6f660f0a112
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193389754 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.193389754
Directory	/workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4013210942
Short name	T313
Test name
Test status
Simulation time	4739520400 ps
CPU time	695.67 seconds
Started	Apr 23 03:50:38 PM PDT 24
Finished	Apr 23 04:02:15 PM PDT 24
Peak memory	600324 kb
Host	smart-7cfed5b3-0a5e-4eac-9e05-f3540e810453
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013210942 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.4013210942
Directory	/workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1975858012
Short name	T315
Test name
Test status
Simulation time	5513728962 ps
CPU time	734.26 seconds
Started	Apr 23 03:52:03 PM PDT 24
Finished	Apr 23 04:04:18 PM PDT 24
Peak memory	600376 kb
Host	smart-414e8da4-19bc-4467-93b5-09eb6dbe1471
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975858012 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1975858012
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.637943472
Short name	T150
Test name
Test status
Simulation time	64635840507 ps
CPU time	12300.2 seconds
Started	Apr 23 03:52:24 PM PDT 24
Finished	Apr 23 07:17:26 PM PDT 24
Peak memory	615832 kb
Host	smart-4f50d49e-b4ec-4d6e-a6f9-5348614c099a
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=637943472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.637943472
Directory	/workspace/0.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3565804316
Short name	T1188
Test name
Test status
Simulation time	5611565340 ps
CPU time	467.26 seconds
Started	Apr 23 03:52:02 PM PDT 24
Finished	Apr 23 03:59:49 PM PDT 24
Peak memory	607252 kb
Host	smart-ce6fe636-4836-4211-8b4e-30d3be4ad0c2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565 804316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.3565804316
Directory	/workspace/0.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.4074006036
Short name	T1090
Test name
Test status
Simulation time	3769480814 ps
CPU time	293.63 seconds
Started	Apr 23 03:55:06 PM PDT 24
Finished	Apr 23 04:00:00 PM PDT 24
Peak memory	607520 kb
Host	smart-e30c754b-717a-4d91-9d7d-997b9b7986d5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4074006036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.4074006036
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.719322772
Short name	T946
Test name
Test status
Simulation time	4751533792 ps
CPU time	274.06 seconds
Started	Apr 23 03:53:32 PM PDT 24
Finished	Apr 23 03:58:08 PM PDT 24
Peak memory	607528 kb
Host	smart-07d5ef7f-a225-4b8f-8a22-f1d0eb3214b4
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=719322772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.719322772
Directory	/workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1430792808
Short name	T206
Test name
Test status
Simulation time	4942498296 ps
CPU time	350.1 seconds
Started	Apr 23 03:54:50 PM PDT 24
Finished	Apr 23 04:00:41 PM PDT 24
Peak memory	601040 kb
Host	smart-0acfa015-3ae7-4a62-8e16-731756a211af
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143079 2808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.1430792808
Directory	/workspace/0.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.594033172
Short name	T253
Test name
Test status
Simulation time	4739171690 ps
CPU time	560.49 seconds
Started	Apr 23 03:55:17 PM PDT 24
Finished	Apr 23 04:04:38 PM PDT 24
Peak memory	600920 kb
Host	smart-e965dbe9-fa6c-49fb-841b-c6d3e7ea7141
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59403 3172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.594033172
Directory	/workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_app_rom.391056555
Short name	T1153
Test name
Test status
Simulation time	2905909560 ps
CPU time	192.84 seconds
Started	Apr 23 03:53:01 PM PDT 24
Finished	Apr 23 03:56:14 PM PDT 24
Peak memory	600224 kb
Host	smart-91119bd3-ade9-41e8-8faf-d5736b13acae
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391056555 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_app_rom.391056555
Directory	/workspace/0.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_entropy.4194415144
Short name	T1064
Test name
Test status
Simulation time	2658585300 ps
CPU time	256.37 seconds
Started	Apr 23 03:52:02 PM PDT 24
Finished	Apr 23 03:56:20 PM PDT 24
Peak memory	599924 kb
Host	smart-84a1efa6-e4ac-4c3f-88b9-47ee655fa2b2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194415144 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.4194415144
Directory	/workspace/0.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_idle.2026390177
Short name	T1030
Test name
Test status
Simulation time	2587607768 ps
CPU time	258.6 seconds
Started	Apr 23 03:54:07 PM PDT 24
Finished	Apr 23 03:58:26 PM PDT 24
Peak memory	599852 kb
Host	smart-54eb3be0-572c-4967-83ee-935a059591d0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026390177 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2026390177
Directory	/workspace/0.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4002802502
Short name	T936
Test name
Test status
Simulation time	2486448038 ps
CPU time	206.16 seconds
Started	Apr 23 03:54:48 PM PDT 24
Finished	Apr 23 03:58:14 PM PDT 24
Peak memory	599888 kb
Host	smart-84927a27-7f41-4966-a9fc-01d7ea8c829c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002802502 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.4002802502
Directory	/workspace/0.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1890425541
Short name	T1015
Test name
Test status
Simulation time	2989978234 ps
CPU time	321.95 seconds
Started	Apr 23 03:53:44 PM PDT 24
Finished	Apr 23 03:59:06 PM PDT 24
Peak memory	599944 kb
Host	smart-54d7fc69-03fa-4977-bc40-55e75912db93
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890425541 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.1890425541
Directory	/workspace/0.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2211953290
Short name	T947
Test name
Test status
Simulation time	3207413377 ps
CPU time	247 seconds
Started	Apr 23 03:54:29 PM PDT 24
Finished	Apr 23 03:58:37 PM PDT 24
Peak memory	599976 kb
Host	smart-4a45938c-c78d-4eaa-8a64-e8787079addb
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211953290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2211953290
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3450743127
Short name	T976
Test name
Test status
Simulation time	3380364229 ps
CPU time	180.89 seconds
Started	Apr 23 03:53:45 PM PDT 24
Finished	Apr 23 03:56:46 PM PDT 24
Peak memory	599764 kb
Host	smart-95f483b7-4d2a-4b6d-8170-4d463b591e22
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34507431 27 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3450743127
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_smoketest.3774700611
Short name	T1029
Test name
Test status
Simulation time	2922100012 ps
CPU time	301.63 seconds
Started	Apr 23 04:02:07 PM PDT 24
Finished	Apr 23 04:07:09 PM PDT 24
Peak memory	600204 kb
Host	smart-4726ef71-c3e3-4456-90be-5c77bc9e7055
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774700611 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.3774700611
Directory	/workspace/0.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2120061872
Short name	T1063
Test name
Test status
Simulation time	3211201186 ps
CPU time	256.29 seconds
Started	Apr 23 03:51:16 PM PDT 24
Finished	Apr 23 03:55:32 PM PDT 24
Peak memory	600160 kb
Host	smart-e1140a43-32aa-4054-b0e6-abb3790124e3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120061872 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.2120061872
Directory	/workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3287123326
Short name	T607
Test name
Test status
Simulation time	2379546103 ps
CPU time	130.78 seconds
Started	Apr 23 03:53:35 PM PDT 24
Finished	Apr 23 03:55:49 PM PDT 24
Peak memory	609836 kb
Host	smart-0433a0fa-56d6-4abd-9345-9f4760b07bfd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287123326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.3287123326
Directory	/workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1489551424
Short name	T101
Test name
Test status
Simulation time	2987406718 ps
CPU time	160.33 seconds
Started	Apr 23 03:51:45 PM PDT 24
Finished	Apr 23 03:54:26 PM PDT 24
Peak memory	611148 kb
Host	smart-cd2fd10c-8bf4-4e01-93b1-d6d4a3cba1ee
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489551424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1489551424
Directory	/workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1352753669
Short name	T1021
Test name
Test status
Simulation time	3455330201 ps
CPU time	172.79 seconds
Started	Apr 23 03:52:35 PM PDT 24
Finished	Apr 23 03:55:29 PM PDT 24
Peak memory	610720 kb
Host	smart-f520f0e3-3e06-4c67-98f2-2801748a17d8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352753669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.1352753669
Directory	/workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.87586494
Short name	T916
Test name
Test status
Simulation time	4855193482 ps
CPU time	339.54 seconds
Started	Apr 23 03:52:18 PM PDT 24
Finished	Apr 23 03:57:59 PM PDT 24
Peak memory	611664 kb
Host	smart-fda0d6c4-ee77-4153-be08-3eaa0812d74f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87586494 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.87586494
Directory	/workspace/0.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.533876776
Short name	T608
Test name
Test status
Simulation time	2313770845 ps
CPU time	105.2 seconds
Started	Apr 23 03:51:35 PM PDT 24
Finished	Apr 23 03:53:20 PM PDT 24
Peak memory	606896 kb
Host	smart-90af87f0-f348-4153-9442-14e109b85a0a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=533876776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.533876776
Directory	/workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3484309475
Short name	T69
Test name
Test status
Simulation time	2704725119 ps
CPU time	104.22 seconds
Started	Apr 23 03:51:14 PM PDT 24
Finished	Apr 23 03:52:59 PM PDT 24
Peak memory	606948 kb
Host	smart-3fb315fa-afd1-44d3-a5e6-12ff06bfc733
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484309475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3484309475
Directory	/workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2953313309
Short name	T1119
Test name
Test status
Simulation time	47788325185 ps
CPU time	6539.8 seconds
Started	Apr 23 03:53:29 PM PDT 24
Finished	Apr 23 05:42:33 PM PDT 24
Peak memory	608756 kb
Host	smart-352ca5fb-8062-4c6f-a052-6b2fca508931
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953313309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.2953313309
Directory	/workspace/0.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.853584818
Short name	T1105
Test name
Test status
Simulation time	8044703762 ps
CPU time	715.85 seconds
Started	Apr 23 03:52:13 PM PDT 24
Finished	Apr 23 04:04:10 PM PDT 24
Peak memory	607520 kb
Host	smart-4055bea4-5808-46c0-97f0-6bbc871c542a
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=853584818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.853584818
Directory	/workspace/0.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1995013799
Short name	T1083
Test name
Test status
Simulation time	45975325840 ps
CPU time	5057.34 seconds
Started	Apr 23 03:53:37 PM PDT 24
Finished	Apr 23 05:17:57 PM PDT 24
Peak memory	608792 kb
Host	smart-64f08077-1000-433e-b25d-e6fcfb11e430
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995013799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.1995013799
Directory	/workspace/0.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.104491971
Short name	T875
Test name
Test status
Simulation time	28194247309 ps
CPU time	2338.78 seconds
Started	Apr 23 03:53:27 PM PDT 24
Finished	Apr 23 04:32:29 PM PDT 24
Peak memory	606548 kb
Host	smart-b7a6dfce-b567-4371-b765-d63e5a7a982f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=104491971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunl ocks.104491971
Directory	/workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.861822756
Short name	T414
Test name
Test status
Simulation time	17256480796 ps
CPU time	4013.3 seconds
Started	Apr 23 03:51:56 PM PDT 24
Finished	Apr 23 04:58:50 PM PDT 24
Peak memory	600364 kb
Host	smart-ff6faaa6-acd5-40d0-934a-552a22f162de
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=861822756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.861822756
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4248670010
Short name	T1041
Test name
Test status
Simulation time	18298175258 ps
CPU time	3953.34 seconds
Started	Apr 23 03:55:29 PM PDT 24
Finished	Apr 23 05:01:23 PM PDT 24
Peak memory	600348 kb
Host	smart-9bbc33a0-b19f-43e1-8401-9809d6cf11dd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4248670010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4248670010
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.305160896
Short name	T612
Test name
Test status
Simulation time	24624782788 ps
CPU time	3818.79 seconds
Started	Apr 23 03:54:12 PM PDT 24
Finished	Apr 23 04:57:52 PM PDT 24
Peak memory	600244 kb
Host	smart-a8d5d8b2-76c2-4306-8347-55e0a9363efe
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305160896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.305160896
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2222459525
Short name	T1098
Test name
Test status
Simulation time	3923313792 ps
CPU time	490.52 seconds
Started	Apr 23 03:53:14 PM PDT 24
Finished	Apr 23 04:01:25 PM PDT 24
Peak memory	599880 kb
Host	smart-3d7884ff-9169-4248-bd30-1a2320b81bbd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222459525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2222459525
Directory	/workspace/0.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_randomness.4410027
Short name	T993
Test name
Test status
Simulation time	5806153226 ps
CPU time	707.28 seconds
Started	Apr 23 03:53:02 PM PDT 24
Finished	Apr 23 04:04:50 PM PDT 24
Peak memory	600312 kb
Host	smart-e4ee2aab-a18b-450d-b52a-eb2f1d1dda8a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4410027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.4410027
Directory	/workspace/0.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_smoketest.2770533259
Short name	T855
Test name
Test status
Simulation time	6298420468 ps
CPU time	1181.47 seconds
Started	Apr 23 04:02:03 PM PDT 24
Finished	Apr 23 04:21:45 PM PDT 24
Peak memory	600272 kb
Host	smart-ce5dc675-f349-4df8-9944-c341f1d7fc22
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770533259 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.2770533259
Directory	/workspace/0.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1723109136
Short name	T172
Test name
Test status
Simulation time	7535863392 ps
CPU time	1244.78 seconds
Started	Apr 23 03:52:34 PM PDT 24
Finished	Apr 23 04:13:21 PM PDT 24
Peak memory	600276 kb
Host	smart-6d1938a7-f2c6-429d-92c4-0196edfdbc1e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1723109136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1723109136
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2149615524
Short name	T919
Test name
Test status
Simulation time	7327598220 ps
CPU time	1267.83 seconds
Started	Apr 23 03:53:12 PM PDT 24
Finished	Apr 23 04:14:20 PM PDT 24
Peak memory	600528 kb
Host	smart-73b18bbf-3313-42e3-9314-b5eea962d23f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2149615524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.2149615524
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.383578190
Short name	T1003
Test name
Test status
Simulation time	8517889000 ps
CPU time	1071.85 seconds
Started	Apr 23 03:52:13 PM PDT 24
Finished	Apr 23 04:10:06 PM PDT 24
Peak memory	600508 kb
Host	smart-61dcfe69-07ee-4cbd-b6f0-4d725311588e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=383578190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.383578190
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3573740867
Short name	T1201
Test name
Test status
Simulation time	4204377172 ps
CPU time	561.55 seconds
Started	Apr 23 03:52:27 PM PDT 24
Finished	Apr 23 04:01:49 PM PDT 24
Peak memory	600204 kb
Host	smart-59aa6b4f-c35e-4060-9f7a-b0eae405d904
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3573740867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3573740867
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2982511031
Short name	T972
Test name
Test status
Simulation time	2919147016 ps
CPU time	242.88 seconds
Started	Apr 23 04:03:02 PM PDT 24
Finished	Apr 23 04:07:05 PM PDT 24
Peak memory	600160 kb
Host	smart-7bc3e25b-0abb-4469-bdc3-ffa5aa5af196
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982511031 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.2982511031
Directory	/workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_power_idle_load.2411498473
Short name	T190
Test name
Test status
Simulation time	4226086296 ps
CPU time	566.45 seconds
Started	Apr 23 03:57:55 PM PDT 24
Finished	Apr 23 04:07:22 PM PDT 24
Peak memory	600152 kb
Host	smart-2e8bbc6d-dcd6-4f45-b225-f5eb4bae5ded
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411498473 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2411498473
Directory	/workspace/0.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/0.chip_sw_power_sleep_load.1566093697
Short name	T1069
Test name
Test status
Simulation time	10774396348 ps
CPU time	523.3 seconds
Started	Apr 23 03:56:29 PM PDT 24
Finished	Apr 23 04:05:13 PM PDT 24
Peak memory	600848 kb
Host	smart-22cdd49b-9c1d-4615-8e1d-b17fc11dd5a3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566093697 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.1566093697
Directory	/workspace/0.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2937485195
Short name	T500
Test name
Test status
Simulation time	12440120141 ps
CPU time	1548.52 seconds
Started	Apr 23 03:51:20 PM PDT 24
Finished	Apr 23 04:17:10 PM PDT 24
Peak memory	601228 kb
Host	smart-dbe1b0a6-abeb-40eb-b715-0393a5db0b6e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937 485195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2937485195
Directory	/workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3084450029
Short name	T975
Test name
Test status
Simulation time	24730605392 ps
CPU time	1767.23 seconds
Started	Apr 23 03:53:08 PM PDT 24
Finished	Apr 23 04:22:37 PM PDT 24
Peak memory	600636 kb
Host	smart-b2a66a4b-67ac-4270-bf1e-2718c73f0bd5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308 4450029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.3084450029
Directory	/workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2489637025
Short name	T1194
Test name
Test status
Simulation time	13842164664 ps
CPU time	1260.11 seconds
Started	Apr 23 03:51:58 PM PDT 24
Finished	Apr 23 04:12:59 PM PDT 24
Peak memory	601320 kb
Host	smart-7784597a-4f3f-4b85-9807-293640de607c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2489637025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2489637025
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1565981130
Short name	T106
Test name
Test status
Simulation time	19488985394 ps
CPU time	1485.11 seconds
Started	Apr 23 03:55:40 PM PDT 24
Finished	Apr 23 04:20:26 PM PDT 24
Peak memory	601880 kb
Host	smart-ad793874-502e-48d8-aa38-8e9949111e35
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1565981130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1565981130
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1768233845
Short name	T931
Test name
Test status
Simulation time	7037041422 ps
CPU time	739.57 seconds
Started	Apr 23 03:53:53 PM PDT 24
Finished	Apr 23 04:06:13 PM PDT 24
Peak memory	600744 kb
Host	smart-65075f48-51ad-440e-9fde-5085ae740716
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768233845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1768233845
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.780732716
Short name	T979
Test name
Test status
Simulation time	7516025470 ps
CPU time	471.58 seconds
Started	Apr 23 03:53:30 PM PDT 24
Finished	Apr 23 04:01:24 PM PDT 24
Peak memory	608256 kb
Host	smart-401bff81-a610-4b01-b639-996e07838805
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=780732716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.780732716
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.411586146
Short name	T149
Test name
Test status
Simulation time	8944751384 ps
CPU time	395.55 seconds
Started	Apr 23 03:51:45 PM PDT 24
Finished	Apr 23 03:58:21 PM PDT 24
Peak memory	600648 kb
Host	smart-0c7e3e06-54ef-4bbd-88b2-ce91b1f5a3fb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411586146 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.411586146
Directory	/workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2231206964
Short name	T958
Test name
Test status
Simulation time	13209971251 ps
CPU time	1575.69 seconds
Started	Apr 23 03:53:36 PM PDT 24
Finished	Apr 23 04:19:54 PM PDT 24
Peak memory	602004 kb
Host	smart-8338421c-5b72-4cab-9ce5-eb7841e1e66f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231206964 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2231206964
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.814687097
Short name	T637
Test name
Test status
Simulation time	6341135447 ps
CPU time	710.94 seconds
Started	Apr 23 03:51:15 PM PDT 24
Finished	Apr 23 04:03:06 PM PDT 24
Peak memory	600684 kb
Host	smart-984d4cbe-3f14-4148-af4c-d4c3e1a76cc5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814687097 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.814687097
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3112824388
Short name	T1005
Test name
Test status
Simulation time	27304974230 ps
CPU time	1845.35 seconds
Started	Apr 23 03:51:42 PM PDT 24
Finished	Apr 23 04:22:28 PM PDT 24
Peak memory	602320 kb
Host	smart-d2fbd78a-3bb5-4fb0-b540-ecb7f1d9d255
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3112824388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3112824388
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2859075841
Short name	T629
Test name
Test status
Simulation time	3074162462 ps
CPU time	265 seconds
Started	Apr 23 03:54:01 PM PDT 24
Finished	Apr 23 03:58:26 PM PDT 24
Peak memory	599916 kb
Host	smart-4d3055f4-e756-4194-beb2-6be12801521f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859075841 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.2859075841
Directory	/workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3930298457
Short name	T245
Test name
Test status
Simulation time	5309209130 ps
CPU time	484.24 seconds
Started	Apr 23 03:52:20 PM PDT 24
Finished	Apr 23 04:00:25 PM PDT 24
Peak memory	607068 kb
Host	smart-ab7492dc-add9-4108-ae77-f6bc43a35031
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3930298457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3930298457
Directory	/workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.666030627
Short name	T352
Test name
Test status
Simulation time	5374557720 ps
CPU time	331.96 seconds
Started	Apr 23 03:54:17 PM PDT 24
Finished	Apr 23 03:59:50 PM PDT 24
Peak memory	600460 kb
Host	smart-37af51f5-9f6d-4cd8-887b-b5c25a1b9dc7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=666030627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.666030627
Directory	/workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1129310473
Short name	T915
Test name
Test status
Simulation time	5240525984 ps
CPU time	447.75 seconds
Started	Apr 23 04:03:07 PM PDT 24
Finished	Apr 23 04:10:35 PM PDT 24
Peak memory	600372 kb
Host	smart-6437aed4-f16b-4850-9531-f5c47e3432e6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129310473 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.1129310473
Directory	/workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2843485437
Short name	T1145
Test name
Test status
Simulation time	8540569220 ps
CPU time	970.38 seconds
Started	Apr 23 03:51:42 PM PDT 24
Finished	Apr 23 04:07:53 PM PDT 24
Peak memory	600776 kb
Host	smart-a3e83605-4391-4c11-a3d4-6824a54c33e1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843485437 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2843485437
Directory	/workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3781568039
Short name	T911
Test name
Test status
Simulation time	4423055900 ps
CPU time	421.09 seconds
Started	Apr 23 03:52:56 PM PDT 24
Finished	Apr 23 03:59:58 PM PDT 24
Peak memory	599320 kb
Host	smart-fd10d0d3-ddae-4cde-bdd3-281fea6d62bf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781568039 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3781568039
Directory	/workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1653351613
Short name	T259
Test name
Test status
Simulation time	5055764260 ps
CPU time	333.65 seconds
Started	Apr 23 04:01:52 PM PDT 24
Finished	Apr 23 04:07:26 PM PDT 24
Peak memory	600408 kb
Host	smart-105f077f-1afb-4704-a76a-244741eee793
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653351613 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.1653351613
Directory	/workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4291139979
Short name	T856
Test name
Test status
Simulation time	4787516328 ps
CPU time	390.8 seconds
Started	Apr 23 03:53:10 PM PDT 24
Finished	Apr 23 03:59:42 PM PDT 24
Peak memory	600308 kb
Host	smart-c41c5264-defd-450c-8523-f23f089b1143
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429 1139979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.4291139979
Directory	/workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.27389009
Short name	T1136
Test name
Test status
Simulation time	9929849572 ps
CPU time	461.69 seconds
Started	Apr 23 03:55:18 PM PDT 24
Finished	Apr 23 04:03:01 PM PDT 24
Peak memory	600788 kb
Host	smart-bb9a62eb-ebed-4f20-8763-6b1ed1d7334a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27389009 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.27389009
Directory	/workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3099684861
Short name	T669
Test name
Test status
Simulation time	5269752860 ps
CPU time	576.12 seconds
Started	Apr 23 03:51:05 PM PDT 24
Finished	Apr 23 04:00:42 PM PDT 24
Peak memory	630088 kb
Host	smart-d61fb4f6-5728-4aaa-a51e-223123625bf3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3099684861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.3099684861
Directory	/workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3321542481
Short name	T914
Test name
Test status
Simulation time	3207352794 ps
CPU time	134.2 seconds
Started	Apr 23 04:02:30 PM PDT 24
Finished	Apr 23 04:04:45 PM PDT 24
Peak memory	599856 kb
Host	smart-6601ea64-b7fa-4705-b851-5a02789dc86a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321542481 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.3321542481
Directory	/workspace/0.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3758694724
Short name	T254
Test name
Test status
Simulation time	4494891354 ps
CPU time	265.8 seconds
Started	Apr 23 03:53:30 PM PDT 24
Finished	Apr 23 03:57:58 PM PDT 24
Peak memory	600348 kb
Host	smart-b1fd156f-30ae-4ae3-a7be-0f8d1e1f951e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758694724 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.3758694724
Directory	/workspace/0.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.305698288
Short name	T1035
Test name
Test status
Simulation time	2812730956 ps
CPU time	154.23 seconds
Started	Apr 23 03:50:14 PM PDT 24
Finished	Apr 23 03:52:49 PM PDT 24
Peak memory	599916 kb
Host	smart-ebb0ff3b-cd16-47f9-9dd3-b15964e31889
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305698288 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.305698288
Directory	/workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2986892252
Short name	T182
Test name
Test status
Simulation time	3118699526 ps
CPU time	195.88 seconds
Started	Apr 23 03:53:32 PM PDT 24
Finished	Apr 23 03:56:50 PM PDT 24
Peak memory	600232 kb
Host	smart-bc324780-3075-45bc-87bd-057a4d2ecc4d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986892252 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2986892252
Directory	/workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3156409829
Short name	T1203
Test name
Test status
Simulation time	5063254952 ps
CPU time	958.7 seconds
Started	Apr 23 03:53:32 PM PDT 24
Finished	Apr 23 04:09:32 PM PDT 24
Peak memory	600268 kb
Host	smart-8f58311f-4484-41d7-bd23-0b5abe2d8e1a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3156409829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3156409829
Directory	/workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1636867400
Short name	T1189
Test name
Test status
Simulation time	3292261656 ps
CPU time	196.39 seconds
Started	Apr 23 04:02:05 PM PDT 24
Finished	Apr 23 04:05:22 PM PDT 24
Peak memory	600176 kb
Host	smart-ca57fe90-abe7-4788-85d1-acbf391fc07a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636867400 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.1636867400
Directory	/workspace/0.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_irq.4286704650
Short name	T60
Test name
Test status
Simulation time	3093407976 ps
CPU time	339.25 seconds
Started	Apr 23 03:54:22 PM PDT 24
Finished	Apr 23 04:00:01 PM PDT 24
Peak memory	599904 kb
Host	smart-6d819be1-6209-48cc-bf52-89ca57ed0ba0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286704650 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.4286704650
Directory	/workspace/0.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2509948982
Short name	T1157
Test name
Test status
Simulation time	2416205508 ps
CPU time	201.13 seconds
Started	Apr 23 04:01:26 PM PDT 24
Finished	Apr 23 04:04:48 PM PDT 24
Peak memory	600172 kb
Host	smart-10635ca6-64b7-419d-8468-c999ced499c9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509948982 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.2509948982
Directory	/workspace/0.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.4005654653
Short name	T1046
Test name
Test status
Simulation time	2685962904 ps
CPU time	231.48 seconds
Started	Apr 23 03:54:30 PM PDT 24
Finished	Apr 23 03:58:22 PM PDT 24
Peak memory	600548 kb
Host	smart-9016a763-cd01-48b8-8563-67f941e9b0d7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005654 653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.4005654653
Directory	/workspace/0.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3850317708
Short name	T1217
Test name
Test status
Simulation time	8750908072 ps
CPU time	1076.54 seconds
Started	Apr 23 03:50:17 PM PDT 24
Finished	Apr 23 04:08:14 PM PDT 24
Peak memory	600712 kb
Host	smart-152718de-6b14-42b1-b8f4-045ba634f6f3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850317708 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3850317708
Directory	/workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2977382048
Short name	T930
Test name
Test status
Simulation time	7106386566 ps
CPU time	610.12 seconds
Started	Apr 23 03:53:00 PM PDT 24
Finished	Apr 23 04:03:11 PM PDT 24
Peak memory	601504 kb
Host	smart-751257a6-9739-4a72-8150-e17f8930a198
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977382048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.2977382048
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4170399569
Short name	T986
Test name
Test status
Simulation time	7385354966 ps
CPU time	609.62 seconds
Started	Apr 23 03:54:51 PM PDT 24
Finished	Apr 23 04:05:01 PM PDT 24
Peak memory	601520 kb
Host	smart-51cd3e05-33f9-4a08-aec9-65c6438f9b32
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170399569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.4170399569
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.489098176
Short name	T1204
Test name
Test status
Simulation time	6816503455 ps
CPU time	551.21 seconds
Started	Apr 23 03:50:27 PM PDT 24
Finished	Apr 23 03:59:39 PM PDT 24
Peak memory	618136 kb
Host	smart-8d858e84-e66e-4341-84f5-1302ea4394a7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489098176 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.489098176
Directory	/workspace/0.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_tpm.530024320
Short name	T41
Test name
Test status
Simulation time	3425725587 ps
CPU time	329.32 seconds
Started	Apr 23 03:50:07 PM PDT 24
Finished	Apr 23 03:55:37 PM PDT 24
Peak memory	606632 kb
Host	smart-589d1748-e591-4c13-a727-f27b96f8b975
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530024320 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.530024320
Directory	/workspace/0.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3350232702
Short name	T180
Test name
Test status
Simulation time	4807876004 ps
CPU time	470.28 seconds
Started	Apr 23 03:56:50 PM PDT 24
Finished	Apr 23 04:04:41 PM PDT 24
Peak memory	600168 kb
Host	smart-1e301f7e-ffcb-4e74-a81a-74a3b002bd34
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350232702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.3350232702
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1853051796
Short name	T263
Test name
Test status
Simulation time	5526653992 ps
CPU time	535.12 seconds
Started	Apr 23 03:55:29 PM PDT 24
Finished	Apr 23 04:04:25 PM PDT 24
Peak memory	600824 kb
Host	smart-b33733f3-dd0d-46f5-9f5c-12cf13aab547
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853051796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1853051796
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.461354590
Short name	T264
Test name
Test status
Simulation time	5338965735 ps
CPU time	509.26 seconds
Started	Apr 23 03:54:24 PM PDT 24
Finished	Apr 23 04:02:54 PM PDT 24
Peak memory	600856 kb
Host	smart-9bf126ef-8356-4b5f-bb81-b62c835b7a19
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461354590 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.461354590
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4189367543
Short name	T848
Test name
Test status
Simulation time	3139847390 ps
CPU time	200.33 seconds
Started	Apr 23 04:01:45 PM PDT 24
Finished	Apr 23 04:05:06 PM PDT 24
Peak memory	599912 kb
Host	smart-6b573651-0078-4d39-b51e-7a8002a02bc2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189367543 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.4189367543
Directory	/workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2158465522
Short name	T1073
Test name
Test status
Simulation time	21172914672 ps
CPU time	3103.47 seconds
Started	Apr 23 03:52:08 PM PDT 24
Finished	Apr 23 04:43:53 PM PDT 24
Peak memory	600744 kb
Host	smart-9c08503e-1c15-4e57-8532-70aad016edd5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158465522 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2158465522
Directory	/workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3773980289
Short name	T193
Test name
Test status
Simulation time	4995605907 ps
CPU time	683.03 seconds
Started	Apr 23 03:54:07 PM PDT 24
Finished	Apr 23 04:05:33 PM PDT 24
Peak memory	604744 kb
Host	smart-3e28614a-e6c1-48be-b4b8-0e2185a128af
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773980289 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.3773980289
Directory	/workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3047981293
Short name	T1137
Test name
Test status
Simulation time	2750924530 ps
CPU time	356.82 seconds
Started	Apr 23 03:52:53 PM PDT 24
Finished	Apr 23 03:58:51 PM PDT 24
Peak memory	604176 kb
Host	smart-796dc0fa-3f2e-4ede-a61d-0b1e1e4b710d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047981293 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.3047981293
Directory	/workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.25016944
Short name	T21
Test name
Test status
Simulation time	21731036296 ps
CPU time	1892.23 seconds
Started	Apr 23 03:51:33 PM PDT 24
Finished	Apr 23 04:23:07 PM PDT 24
Peak memory	604792 kb
Host	smart-2bed4e9f-998f-4f13-b195-a6248983d3c4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25016944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.25016944
Directory	/workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.931660563
Short name	T38
Test name
Test status
Simulation time	5099741552 ps
CPU time	407.31 seconds
Started	Apr 23 03:52:15 PM PDT 24
Finished	Apr 23 03:59:04 PM PDT 24
Peak memory	600420 kb
Host	smart-7e9db876-224a-4d1e-b639-878038fa7c54
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931660563 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.931660563
Directory	/workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1987612420
Short name	T1212
Test name
Test status
Simulation time	13542745368 ps
CPU time	2682.65 seconds
Started	Apr 23 03:50:39 PM PDT 24
Finished	Apr 23 04:35:22 PM PDT 24
Peak memory	607500 kb
Host	smart-2b5a3e2a-31d6-499e-aa66-10d07b4b9514
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1987612420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1987612420
Directory	/workspace/0.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_smoketest.908532888
Short name	T846
Test name
Test status
Simulation time	2558223286 ps
CPU time	192.49 seconds
Started	Apr 23 04:02:42 PM PDT 24
Finished	Apr 23 04:05:55 PM PDT 24
Peak memory	599972 kb
Host	smart-c23e7b0a-dd30-4ed6-8c63-ffa08c37078e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908532888 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_uart_smoketest.908532888
Directory	/workspace/0.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx.3500776206
Short name	T866
Test name
Test status
Simulation time	3974699292 ps
CPU time	450.99 seconds
Started	Apr 23 03:49:46 PM PDT 24
Finished	Apr 23 03:57:18 PM PDT 24
Peak memory	607348 kb
Host	smart-3e300ade-83b4-45ae-b483-9a198bda760e
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500776206 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.3500776206
Directory	/workspace/0.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1287692153
Short name	T921
Test name
Test status
Simulation time	3729921880 ps
CPU time	428.33 seconds
Started	Apr 23 03:50:27 PM PDT 24
Finished	Apr 23 03:57:36 PM PDT 24
Peak memory	607508 kb
Host	smart-da483efb-8a4d-4f23-a3f5-5edfaaa500bb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287692153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.1287692153
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.730082249
Short name	T1076
Test name
Test status
Simulation time	4022522201 ps
CPU time	416.2 seconds
Started	Apr 23 03:51:08 PM PDT 24
Finished	Apr 23 03:58:05 PM PDT 24
Peak memory	607528 kb
Host	smart-5735cf20-0653-453c-8d71-e1c8188f2770
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730082249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.730082249
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2178428514
Short name	T196
Test name
Test status
Simulation time	4543567272 ps
CPU time	458.5 seconds
Started	Apr 23 03:50:30 PM PDT 24
Finished	Apr 23 03:58:10 PM PDT 24
Peak memory	608540 kb
Host	smart-e7b4eadb-ef0d-409f-a4d5-e43befd432f0
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178428514 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2178428514
Directory	/workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3782715492
Short name	T904
Test name
Test status
Simulation time	3855479272 ps
CPU time	433.97 seconds
Started	Apr 23 03:49:41 PM PDT 24
Finished	Apr 23 03:56:55 PM PDT 24
Peak memory	608480 kb
Host	smart-95c74fb8-c548-42d9-88a9-861d50e414db
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782715492 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3782715492
Directory	/workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2342629031
Short name	T372
Test name
Test status
Simulation time	3037345001 ps
CPU time	244.22 seconds
Started	Apr 23 03:53:30 PM PDT 24
Finished	Apr 23 03:57:37 PM PDT 24
Peak memory	600160 kb
Host	smart-4b635e52-5683-4530-9a33-8cf71f61e638
User	root
Command	/workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342629031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.2342629031
Directory	/workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_dpi.3859295215
Short name	T1139
Test name
Test status
Simulation time	12649474884 ps
CPU time	3026.12 seconds
Started	Apr 23 03:49:49 PM PDT 24
Finished	Apr 23 04:40:16 PM PDT 24
Peak memory	600280 kb
Host	smart-1d128471-8c16-418a-9b37-dd8a6847f79c
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3859295215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.3859295215
Directory	/workspace/0.chip_sw_usbdev_dpi/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2383357906
Short name	T23
Test name
Test status
Simulation time	31426885308 ps
CPU time	7002.24 seconds
Started	Apr 23 03:51:42 PM PDT 24
Finished	Apr 23 05:48:25 PM PDT 24
Peak memory	600172 kb
Host	smart-8f792e75-34e1-409d-b92d-1326a9d32468
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2383357906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2383357906
Directory	/workspace/0.chip_sw_usbdev_pincfg/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pullup.1779106235
Short name	T79
Test name
Test status
Simulation time	2309299880 ps
CPU time	232.2 seconds
Started	Apr 23 03:51:48 PM PDT 24
Finished	Apr 23 03:55:41 PM PDT 24
Peak memory	599868 kb
Host	smart-22827874-0089-4a32-b9e0-b98331191c1c
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779106235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.1779106235
Directory	/workspace/0.chip_sw_usbdev_pullup/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1569019657
Short name	T22
Test name
Test status
Simulation time	3222870272 ps
CPU time	457.89 seconds
Started	Apr 23 03:51:46 PM PDT 24
Finished	Apr 23 03:59:24 PM PDT 24
Peak memory	599964 kb
Host	smart-3cfb175b-950f-4f72-8279-e3558b917620
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156901965 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.1569019657
Directory	/workspace/0.chip_sw_usbdev_setuprx/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_vbus.2449972101
Short name	T847
Test name
Test status
Simulation time	2857521888 ps
CPU time	239.5 seconds
Started	Apr 23 03:50:31 PM PDT 24
Finished	Apr 23 03:54:31 PM PDT 24
Peak memory	599896 kb
Host	smart-f4a6679c-e509-49c3-90a1-10302b071e09
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449972101 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.2449972101
Directory	/workspace/0.chip_sw_usbdev_vbus/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_dev.444781591
Short name	T984
Test name
Test status
Simulation time	1975943532 ps
CPU time	115.08 seconds
Started	Apr 23 03:52:55 PM PDT 24
Finished	Apr 23 03:54:51 PM PDT 24
Peak memory	609040 kb
Host	smart-6c24e13e-1619-4b9d-adc3-65d162b8d940
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=444781591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.444781591
Directory	/workspace/0.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_prod.7749872
Short name	T648
Test name
Test status
Simulation time	3026407453 ps
CPU time	137.45 seconds
Started	Apr 23 03:54:21 PM PDT 24
Finished	Apr 23 03:56:38 PM PDT 24
Peak memory	609164 kb
Host	smart-fc313b2f-dd79-4fa6-bd49-621628166021
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7749872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.7749872
Directory	/workspace/0.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_rma.3776948030
Short name	T72
Test name
Test status
Simulation time	6812423466 ps
CPU time	513.77 seconds
Started	Apr 23 03:54:05 PM PDT 24
Finished	Apr 23 04:02:40 PM PDT 24
Peak memory	611464 kb
Host	smart-ce3cfb7e-f175-402e-93b1-7d7d009af015
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776948030 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3776948030
Directory	/workspace/0.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_testunlock0.3716832662
Short name	T73
Test name
Test status
Simulation time	8939546908 ps
CPU time	808.16 seconds
Started	Apr 23 03:54:45 PM PDT 24
Finished	Apr 23 04:08:14 PM PDT 24
Peak memory	618164 kb
Host	smart-bd57278c-2a02-4423-93da-b3c4c2d70f90
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716832662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.3716832662
Directory	/workspace/0.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1240285593
Short name	T256
Test name
Test status
Simulation time	79072680048 ps
CPU time	16159.9 seconds
Started	Apr 23 04:04:55 PM PDT 24
Finished	Apr 23 08:34:17 PM PDT 24
Peak memory	599688 kb
Host	smart-c890b7a1-e0b7-4c9a-b989-f79063d02a27
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_ flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240285593 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1240285593
Directory	/workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.699165873
Short name	T1053
Test name
Test status
Simulation time	77563072500 ps
CPU time	18791.8 seconds
Started	Apr 23 04:02:03 PM PDT 24
Finished	Apr 23 09:15:17 PM PDT 24
Peak memory	599464 kb
Host	smart-bbcfdd59-4a4b-4576-a6ce-5436de752514
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_b inary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0 :4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=699165873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.699165873
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1903323535
Short name	T45
Test name
Test status
Simulation time	80236101368 ps
CPU time	15963.7 seconds
Started	Apr 23 04:03:29 PM PDT 24
Finished	Apr 23 08:29:35 PM PDT 24
Peak memory	600460 kb
Host	smart-0baf900c-2bc0-429e-b263-5415802a4be6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903323535 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1903323535
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.347673249
Short name	T43
Test name
Test status
Simulation time	80202122715 ps
CPU time	15996.3 seconds
Started	Apr 23 04:04:23 PM PDT 24
Finished	Apr 23 08:31:00 PM PDT 24
Peak memory	600720 kb
Host	smart-f8efc823-5eb5-4bb4-bc53-0ff7ba1ab9a3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347673249 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.347673249
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_keymgr_functest.1900012538
Short name	T1169
Test name
Test status
Simulation time	5532773720 ps
CPU time	480.27 seconds
Started	Apr 23 04:01:15 PM PDT 24
Finished	Apr 23 04:09:16 PM PDT 24
Peak memory	600196 kb
Host	smart-306b692b-2e1d-4e12-872b-de707e743523
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900012538 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.1900012538
Directory	/workspace/0.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/0.rom_volatile_raw_unlock.2614371853
Short name	T610
Test name
Test status
Simulation time	2376911818 ps
CPU time	99.73 seconds
Started	Apr 23 04:01:35 PM PDT 24
Finished	Apr 23 04:03:16 PM PDT 24
Peak memory	606952 kb
Host	smart-32b9a852-4c79-4e2f-ad42-fe090893726e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614371853 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.2614371853
Directory	/workspace/0.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/1.chip_jtag_mem_access.2911576243
Short name	T232
Test name
Test status
Simulation time	13460553111 ps
CPU time	1217.97 seconds
Started	Apr 23 04:03:43 PM PDT 24
Finished	Apr 23 04:24:02 PM PDT 24
Peak memory	600960 kb
Host	smart-517c06a3-5f4f-46ad-bf73-66b25456e9fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911576243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.2 911576243
Directory	/workspace/1.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_10.592175651
Short name	T161
Test name
Test status
Simulation time	3630399720 ps
CPU time	498.79 seconds
Started	Apr 23 04:14:09 PM PDT 24
Finished	Apr 23 04:22:29 PM PDT 24
Peak memory	600124 kb
Host	smart-96c12a2e-5c67-430b-a24c-9fadcd03e93c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592175651 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.592175651
Directory	/workspace/1.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2748816068
Short name	T53
Test name
Test status
Simulation time	4813680124 ps
CPU time	415.41 seconds
Started	Apr 23 04:11:03 PM PDT 24
Finished	Apr 23 04:17:59 PM PDT 24
Peak memory	609472 kb
Host	smart-8b7d278e-6827-43e7-91e9-42b6cc6ab38f
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 748816068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2748816068
Directory	/workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/1.chip_sival_flash_info_access.2676641871
Short name	T333
Test name
Test status
Simulation time	2727162064 ps
CPU time	185.6 seconds
Started	Apr 23 04:03:19 PM PDT 24
Finished	Apr 23 04:06:26 PM PDT 24
Peak memory	599948 kb
Host	smart-c45e95a5-6a37-4174-aa87-83b56ede2c69
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2676641871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.2676641871
Directory	/workspace/1.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1332337326
Short name	T1045
Test name
Test status
Simulation time	18461998824 ps
CPU time	529.77 seconds
Started	Apr 23 04:08:00 PM PDT 24
Finished	Apr 23 04:16:50 PM PDT 24
Peak memory	608448 kb
Host	smart-b7b1e3de-3332-42de-ac7a-b17d6815fa34
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1332337326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1332337326
Directory	/workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc.496413944
Short name	T1199
Test name
Test status
Simulation time	2765755992 ps
CPU time	315.29 seconds
Started	Apr 23 04:07:39 PM PDT 24
Finished	Apr 23 04:12:55 PM PDT 24
Peak memory	599928 kb
Host	smart-cae80323-1527-407b-b8c5-8ff5329858d9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496413944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.496413944
Directory	/workspace/1.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2110806689
Short name	T941
Test name
Test status
Simulation time	2981726231 ps
CPU time	192.46 seconds
Started	Apr 23 04:06:54 PM PDT 24
Finished	Apr 23 04:10:07 PM PDT 24
Peak memory	599936 kb
Host	smart-5f44eaf6-3d0a-4b58-b38f-49f53751ac0a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110 806689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2110806689
Directory	/workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4050813466
Short name	T1125
Test name
Test status
Simulation time	3694344639 ps
CPU time	237.17 seconds
Started	Apr 23 04:11:50 PM PDT 24
Finished	Apr 23 04:15:47 PM PDT 24
Peak memory	599940 kb
Host	smart-58aacd69-e244-4d5c-9640-dc93e4555d3c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050813466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.4050813466
Directory	/workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_entropy.812600200
Short name	T1026
Test name
Test status
Simulation time	3167445888 ps
CPU time	259.19 seconds
Started	Apr 23 04:07:28 PM PDT 24
Finished	Apr 23 04:11:48 PM PDT 24
Peak memory	600128 kb
Host	smart-a2149c16-aef0-43e4-bb19-88d77bef1ac4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812600200 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.812600200
Directory	/workspace/1.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_idle.1436104064
Short name	T1088
Test name
Test status
Simulation time	2468854420 ps
CPU time	198.96 seconds
Started	Apr 23 04:08:01 PM PDT 24
Finished	Apr 23 04:11:20 PM PDT 24
Peak memory	599896 kb
Host	smart-b2566d70-e43c-4bc7-9d5f-527acd228711
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436104064 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.1436104064
Directory	/workspace/1.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_masking_off.4000972883
Short name	T1210
Test name
Test status
Simulation time	2877203881 ps
CPU time	291.48 seconds
Started	Apr 23 04:07:08 PM PDT 24
Finished	Apr 23 04:12:00 PM PDT 24
Peak memory	599940 kb
Host	smart-d765534b-6ade-443d-bf1e-b4091a4d394b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000972883 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.4000972883
Directory	/workspace/1.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_smoketest.822747118
Short name	T1102
Test name
Test status
Simulation time	3336250648 ps
CPU time	323.72 seconds
Started	Apr 23 04:17:57 PM PDT 24
Finished	Apr 23 04:23:21 PM PDT 24
Peak memory	599852 kb
Host	smart-da7d285d-b3a7-48d1-9c94-9e68165868b9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822747118 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.822747118
Directory	/workspace/1.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3421184496
Short name	T1107
Test name
Test status
Simulation time	3130536318 ps
CPU time	240.13 seconds
Started	Apr 23 04:08:13 PM PDT 24
Finished	Apr 23 04:12:14 PM PDT 24
Peak memory	600764 kb
Host	smart-d24a8359-0ba3-4f4f-a70a-06f717576ff0
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3421184496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3421184496
Directory	/workspace/1.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3060335731
Short name	T961
Test name
Test status
Simulation time	4767547656 ps
CPU time	558.99 seconds
Started	Apr 23 04:08:00 PM PDT 24
Finished	Apr 23 04:17:20 PM PDT 24
Peak memory	607496 kb
Host	smart-0ac2705d-2834-4f44-acc9-7be87184581f
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3060335731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.3060335731
Directory	/workspace/1.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1149973714
Short name	T888
Test name
Test status
Simulation time	8673006264 ps
CPU time	1665.16 seconds
Started	Apr 23 04:09:06 PM PDT 24
Finished	Apr 23 04:36:52 PM PDT 24
Peak memory	601212 kb
Host	smart-f6471a23-2821-4605-b55f-8b9c05c3a6f1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1149973714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.1149973714
Directory	/workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3708372571
Short name	T1097
Test name
Test status
Simulation time	7849596398 ps
CPU time	1329.02 seconds
Started	Apr 23 04:09:06 PM PDT 24
Finished	Apr 23 04:31:16 PM PDT 24
Peak memory	600212 kb
Host	smart-c6d97de3-84a1-434d-99a8-58d34fe59058
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708372571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.3708372571
Directory	/workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1847269452
Short name	T987
Test name
Test status
Simulation time	3552871788 ps
CPU time	289.73 seconds
Started	Apr 23 04:08:44 PM PDT 24
Finished	Apr 23 04:13:35 PM PDT 24
Peak memory	599996 kb
Host	smart-046b479f-06e0-4b3c-85d3-1f8ea0e5ac2c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1847269452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1847269452
Directory	/workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.291012743
Short name	T990
Test name
Test status
Simulation time	254293050246 ps
CPU time	12647.9 seconds
Started	Apr 23 04:08:50 PM PDT 24
Finished	Apr 23 07:39:40 PM PDT 24
Peak memory	601548 kb
Host	smart-624ca84f-e9ab-407d-b661-3a3c14013ab2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=291012743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.291012743
Directory	/workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_irq.1927284500
Short name	T843
Test name
Test status
Simulation time	3796481400 ps
CPU time	327.22 seconds
Started	Apr 23 04:06:37 PM PDT 24
Finished	Apr 23 04:12:04 PM PDT 24
Peak memory	599884 kb
Host	smart-91367d8b-e48a-4adf-8fde-b3d1c77c2274
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927284500 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1927284500
Directory	/workspace/1.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1255407437
Short name	T893
Test name
Test status
Simulation time	6450337930 ps
CPU time	396.74 seconds
Started	Apr 23 04:08:20 PM PDT 24
Finished	Apr 23 04:14:57 PM PDT 24
Peak memory	600316 kb
Host	smart-f202f8e5-c909-4818-99a3-91b5b39f0eea
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1255407437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1255407437
Directory	/workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3753231436
Short name	T910
Test name
Test status
Simulation time	3078694584 ps
CPU time	256.54 seconds
Started	Apr 23 04:14:03 PM PDT 24
Finished	Apr 23 04:18:20 PM PDT 24
Peak memory	599912 kb
Host	smart-f2677bec-3a3b-48bc-9fd0-265fdceb6d00
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753231436 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.3753231436
Directory	/workspace/1.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.810910266
Short name	T1211
Test name
Test status
Simulation time	10069920540 ps
CPU time	1186.33 seconds
Started	Apr 23 04:08:46 PM PDT 24
Finished	Apr 23 04:28:33 PM PDT 24
Peak memory	600400 kb
Host	smart-35cf0360-57a6-4d85-89ed-cd70f8036352
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 810910266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.810910266
Directory	/workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3151345181
Short name	T324
Test name
Test status
Simulation time	5321714000 ps
CPU time	491.32 seconds
Started	Apr 23 04:10:13 PM PDT 24
Finished	Apr 23 04:18:25 PM PDT 24
Peak memory	600516 kb
Host	smart-f2ae7bb1-c2a1-43ea-b3e1-b956fac42c64
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3151345181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.3151345181
Directory	/workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.387984821
Short name	T671
Test name
Test status
Simulation time	7202968624 ps
CPU time	909.14 seconds
Started	Apr 23 04:11:26 PM PDT 24
Finished	Apr 23 04:26:35 PM PDT 24
Peak memory	606856 kb
Host	smart-88bb1087-80c7-44e7-9764-9dbe17246fca
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387984821 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.387984821
Directory	/workspace/1.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2164715005
Short name	T1106
Test name
Test status
Simulation time	4704311839 ps
CPU time	375.55 seconds
Started	Apr 23 04:10:41 PM PDT 24
Finished	Apr 23 04:16:57 PM PDT 24
Peak memory	611720 kb
Host	smart-f4d4616f-15e7-4da8-960b-6091985613de
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2164715005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2164715005
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2742953273
Short name	T920
Test name
Test status
Simulation time	4584445600 ps
CPU time	635.28 seconds
Started	Apr 23 04:15:02 PM PDT 24
Finished	Apr 23 04:25:38 PM PDT 24
Peak memory	604188 kb
Host	smart-c50e71bd-c426-4380-8ac0-a6ac2331fd44
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742953273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2742953273
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3561616092
Short name	T127
Test name
Test status
Simulation time	3916982120 ps
CPU time	533.31 seconds
Started	Apr 23 04:09:44 PM PDT 24
Finished	Apr 23 04:18:38 PM PDT 24
Peak memory	604160 kb
Host	smart-d136bdbf-e226-4261-9489-701a140ae06a
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561616092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3561616092
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1851309101
Short name	T863
Test name
Test status
Simulation time	4108886368 ps
CPU time	558.67 seconds
Started	Apr 23 04:14:39 PM PDT 24
Finished	Apr 23 04:23:58 PM PDT 24
Peak memory	604176 kb
Host	smart-9233de24-7e4d-4fec-872c-adc3038ff445
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851309101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1851309101
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1785133671
Short name	T294
Test name
Test status
Simulation time	4461996610 ps
CPU time	467.45 seconds
Started	Apr 23 04:10:03 PM PDT 24
Finished	Apr 23 04:17:51 PM PDT 24
Peak memory	604144 kb
Host	smart-df29b668-a6be-4076-be87-a93fb506eadf
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785133671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1785133671
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2860277786
Short name	T391
Test name
Test status
Simulation time	5127374980 ps
CPU time	669.83 seconds
Started	Apr 23 04:16:37 PM PDT 24
Finished	Apr 23 04:27:48 PM PDT 24
Peak memory	604224 kb
Host	smart-bd425f5f-4fdf-41eb-bec8-e70edbfcc4fc
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860277786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2860277786
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4249823539
Short name	T126
Test name
Test status
Simulation time	4918098900 ps
CPU time	617.52 seconds
Started	Apr 23 04:15:06 PM PDT 24
Finished	Apr 23 04:25:25 PM PDT 24
Peak memory	604204 kb
Host	smart-b21c5d2f-2b51-4d22-8890-af05a9b490b5
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249823539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4249823539
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3264278801
Short name	T1214
Test name
Test status
Simulation time	3251355492 ps
CPU time	238.73 seconds
Started	Apr 23 04:10:49 PM PDT 24
Finished	Apr 23 04:14:48 PM PDT 24
Peak memory	599880 kb
Host	smart-5f420bfc-364d-4325-a06e-2b2db46b3f37
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264278801 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.3264278801
Directory	/workspace/1.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3383326855
Short name	T831
Test name
Test status
Simulation time	3339378848 ps
CPU time	505.44 seconds
Started	Apr 23 04:12:25 PM PDT 24
Finished	Apr 23 04:20:52 PM PDT 24
Peak memory	600172 kb
Host	smart-52ecaec0-e977-4bae-a101-f9e58e31150a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383326855 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.3383326855
Directory	/workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3543598202
Short name	T881
Test name
Test status
Simulation time	2430549113 ps
CPU time	159.23 seconds
Started	Apr 23 04:12:23 PM PDT 24
Finished	Apr 23 04:15:02 PM PDT 24
Peak memory	600152 kb
Host	smart-949b05ff-545f-47e5-b364-45ffa44cb180
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543598202 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.3543598202
Directory	/workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2933438687
Short name	T860
Test name
Test status
Simulation time	4874342590 ps
CPU time	466.11 seconds
Started	Apr 23 04:14:44 PM PDT 24
Finished	Apr 23 04:22:31 PM PDT 24
Peak memory	600260 kb
Host	smart-c08ce7a1-862c-4dcd-aedb-cc52949215ac
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933438687 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2933438687
Directory	/workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2959938116
Short name	T1198
Test name
Test status
Simulation time	4941604896 ps
CPU time	399.77 seconds
Started	Apr 23 04:10:01 PM PDT 24
Finished	Apr 23 04:16:42 PM PDT 24
Peak memory	600292 kb
Host	smart-d16b7249-1447-4559-83b0-68e0d1a111c2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959938116 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2959938116
Directory	/workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1305285188
Short name	T844
Test name
Test status
Simulation time	5422900000 ps
CPU time	337.6 seconds
Started	Apr 23 04:14:10 PM PDT 24
Finished	Apr 23 04:19:48 PM PDT 24
Peak memory	600312 kb
Host	smart-df10e205-df3b-40e1-9c8f-0fa7203bd93d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305285188 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.1305285188
Directory	/workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3939308274
Short name	T912
Test name
Test status
Simulation time	4342261042 ps
CPU time	345.69 seconds
Started	Apr 23 04:09:44 PM PDT 24
Finished	Apr 23 04:15:30 PM PDT 24
Peak memory	600352 kb
Host	smart-ffbb33a0-33d1-4a41-b128-c3e7f3e4bacd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939308274 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.3939308274
Directory	/workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3261374227
Short name	T367
Test name
Test status
Simulation time	12530992790 ps
CPU time	1401.19 seconds
Started	Apr 23 04:10:14 PM PDT 24
Finished	Apr 23 04:33:36 PM PDT 24
Peak memory	600388 kb
Host	smart-12c949f1-53d0-4079-96b8-d0075af7a7f5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261374227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3261374227
Directory	/workspace/1.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2681844649
Short name	T670
Test name
Test status
Simulation time	3889886846 ps
CPU time	439.99 seconds
Started	Apr 23 04:10:24 PM PDT 24
Finished	Apr 23 04:17:45 PM PDT 24
Peak memory	599924 kb
Host	smart-7e3a9a9a-c656-48de-97a3-484a8d2fe842
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681844649 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2681844649
Directory	/workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2401799077
Short name	T1095
Test name
Test status
Simulation time	4590713660 ps
CPU time	592.49 seconds
Started	Apr 23 04:10:08 PM PDT 24
Finished	Apr 23 04:20:01 PM PDT 24
Peak memory	600260 kb
Host	smart-165686ef-765d-462f-a467-041d311bcc4b
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401799077 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2401799077
Directory	/workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1757983656
Short name	T834
Test name
Test status
Simulation time	2582203276 ps
CPU time	194.19 seconds
Started	Apr 23 04:14:13 PM PDT 24
Finished	Apr 23 04:17:27 PM PDT 24
Peak memory	599876 kb
Host	smart-8e7ea0df-b15d-4bbf-ac9a-69f02bc10fd1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757983656 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1757983656
Directory	/workspace/1.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3309401344
Short name	T1013
Test name
Test status
Simulation time	7906241444 ps
CPU time	1989.29 seconds
Started	Apr 23 04:09:09 PM PDT 24
Finished	Apr 23 04:42:19 PM PDT 24
Peak memory	600328 kb
Host	smart-f50f8735-5b32-4c32-ae53-e2cbf76e82f9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309401344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.3309401344
Directory	/workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3477669904
Short name	T954
Test name
Test status
Simulation time	18645028313 ps
CPU time	3559.82 seconds
Started	Apr 23 04:11:26 PM PDT 24
Finished	Apr 23 05:10:47 PM PDT 24
Peak memory	600504 kb
Host	smart-bb54b3eb-944c-4514-945d-21e91445148a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477669904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _csrng_edn_concurrency_reduced_freq.3477669904
Directory	/workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.713254188
Short name	T97
Test name
Test status
Simulation time	4271746000 ps
CPU time	555.91 seconds
Started	Apr 23 04:09:28 PM PDT 24
Finished	Apr 23 04:18:44 PM PDT 24
Peak memory	600408 kb
Host	smart-49eb949e-8f20-4e22-9dbd-f8ddb4969189
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71325 4188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.713254188
Directory	/workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_kat_test.961227112
Short name	T1025
Test name
Test status
Simulation time	3115619136 ps
CPU time	287.79 seconds
Started	Apr 23 04:09:40 PM PDT 24
Finished	Apr 23 04:14:28 PM PDT 24
Peak memory	600132 kb
Host	smart-22e23daa-941a-4364-bae4-14fda86e410f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961227112 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.961227112
Directory	/workspace/1.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_smoketest.3795046388
Short name	T396
Test name
Test status
Simulation time	2869279632 ps
CPU time	209.76 seconds
Started	Apr 23 04:14:00 PM PDT 24
Finished	Apr 23 04:17:30 PM PDT 24
Peak memory	599852 kb
Host	smart-29cdd4c5-55c2-430d-9ade-b0393442f1d8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795046388 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.3795046388
Directory	/workspace/1.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.748579460
Short name	T1055
Test name
Test status
Simulation time	5973476432 ps
CPU time	738.69 seconds
Started	Apr 23 04:02:48 PM PDT 24
Finished	Apr 23 04:15:07 PM PDT 24
Peak memory	600572 kb
Host	smart-06e4dd84-10cb-4278-88ea-855169789b0a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=748579460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.748579460
Directory	/workspace/1.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_boot_mode.3997164945
Short name	T617
Test name
Test status
Simulation time	3010288964 ps
CPU time	505.22 seconds
Started	Apr 23 04:09:07 PM PDT 24
Finished	Apr 23 04:17:33 PM PDT 24
Peak memory	600228 kb
Host	smart-786669a4-001e-4618-b204-85eff48e90ca
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997164945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.3997164945
Directory	/workspace/1.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.909927416
Short name	T952
Test name
Test status
Simulation time	4859514824 ps
CPU time	706.17 seconds
Started	Apr 23 04:08:52 PM PDT 24
Finished	Apr 23 04:20:38 PM PDT 24
Peak memory	600444 kb
Host	smart-844d7ac7-e329-4887-ab2e-9d1c259108ea
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=909927416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.909927416
Directory	/workspace/1.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.485385214
Short name	T221
Test name
Test status
Simulation time	5946304261 ps
CPU time	798.82 seconds
Started	Apr 23 04:09:14 PM PDT 24
Finished	Apr 23 04:22:33 PM PDT 24
Peak memory	600360 kb
Host	smart-294cb7e6-184b-49a3-9bec-52e55de6fcf1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485385214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.485385214
Directory	/workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_kat.3814394695
Short name	T355
Test name
Test status
Simulation time	3807666952 ps
CPU time	511.21 seconds
Started	Apr 23 04:08:42 PM PDT 24
Finished	Apr 23 04:17:13 PM PDT 24
Peak memory	606096 kb
Host	smart-baaa9a9d-e3c6-4e62-9db6-c4c4e134fc1b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814394695 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3814394695
Directory	/workspace/1.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_sw_mode.2812586381
Short name	T614
Test name
Test status
Simulation time	9415535330 ps
CPU time	1928.48 seconds
Started	Apr 23 04:09:09 PM PDT 24
Finished	Apr 23 04:41:18 PM PDT 24
Peak memory	600176 kb
Host	smart-6c11ee38-0763-419e-8cbb-a5ac764c0930
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812586381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.2812586381
Directory	/workspace/1.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3861406459
Short name	T838
Test name
Test status
Simulation time	2807833492 ps
CPU time	157.57 seconds
Started	Apr 23 04:08:41 PM PDT 24
Finished	Apr 23 04:11:19 PM PDT 24
Peak memory	599948 kb
Host	smart-21bc5b19-f5bc-45d3-8d48-596a473f5eaf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38 61406459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.3861406459
Directory	/workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.33912782
Short name	T311
Test name
Test status
Simulation time	7450325416 ps
CPU time	1602.7 seconds
Started	Apr 23 04:08:58 PM PDT 24
Finished	Apr 23 04:35:41 PM PDT 24
Peak memory	600364 kb
Host	smart-9b554dfb-e34d-4c7f-a680-aa2225cb440d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=33912782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.33912782
Directory	/workspace/1.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1598571664
Short name	T868
Test name
Test status
Simulation time	2462507418 ps
CPU time	241.77 seconds
Started	Apr 23 04:08:54 PM PDT 24
Finished	Apr 23 04:12:57 PM PDT 24
Peak memory	600212 kb
Host	smart-ee8ef75d-35ce-4feb-a66b-a8a909e79b7d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598571664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1598571664
Directory	/workspace/1.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1156410326
Short name	T1152
Test name
Test status
Simulation time	3201542888 ps
CPU time	349.71 seconds
Started	Apr 23 04:13:59 PM PDT 24
Finished	Apr 23 04:19:50 PM PDT 24
Peak memory	599952 kb
Host	smart-4681c889-bb99-4903-a6af-2a153213b915
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1156410326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.1156410326
Directory	/workspace/1.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_example_concurrency.2269588208
Short name	T899
Test name
Test status
Simulation time	2757662284 ps
CPU time	323.71 seconds
Started	Apr 23 04:03:31 PM PDT 24
Finished	Apr 23 04:08:55 PM PDT 24
Peak memory	599920 kb
Host	smart-f40c63d2-63b4-4c83-8de9-a33acad0e269
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269588208 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.2269588208
Directory	/workspace/1.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/1.chip_sw_example_flash.596847158
Short name	T900
Test name
Test status
Simulation time	2996540114 ps
CPU time	332.66 seconds
Started	Apr 23 04:02:59 PM PDT 24
Finished	Apr 23 04:08:32 PM PDT 24
Peak memory	600220 kb
Host	smart-c9205709-2755-4798-b5b5-de2a6645fd20
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596847158 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.596847158
Directory	/workspace/1.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/1.chip_sw_example_manufacturer.10303383
Short name	T1032
Test name
Test status
Simulation time	2328410662 ps
CPU time	213.53 seconds
Started	Apr 23 04:02:56 PM PDT 24
Finished	Apr 23 04:06:30 PM PDT 24
Peak memory	599300 kb
Host	smart-45a42a1b-a5a0-4c0b-a275-052258aae925
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10303383 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_example_manufacturer.10303383
Directory	/workspace/1.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/1.chip_sw_example_rom.2414404709
Short name	T1082
Test name
Test status
Simulation time	2143476456 ps
CPU time	111.02 seconds
Started	Apr 23 04:01:50 PM PDT 24
Finished	Apr 23 04:03:41 PM PDT 24
Peak memory	598372 kb
Host	smart-65ce107e-24a0-4a5c-8874-85480f1cb544
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414404709 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.2414404709
Directory	/workspace/1.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2422117905
Short name	T156
Test name
Test status
Simulation time	57511796143 ps
CPU time	10689.5 seconds
Started	Apr 23 04:03:49 PM PDT 24
Finished	Apr 23 07:02:00 PM PDT 24
Peak memory	615872 kb
Host	smart-ee0adfb8-9f2b-4281-87e1-089885234a9f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2422117905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.2422117905
Directory	/workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_crash_alert.3239979358
Short name	T835
Test name
Test status
Simulation time	5116045432 ps
CPU time	634.5 seconds
Started	Apr 23 04:14:03 PM PDT 24
Finished	Apr 23 04:24:39 PM PDT 24
Peak memory	601644 kb
Host	smart-e7329b27-5c52-43ed-8108-961423441dba
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3239979358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3239979358
Directory	/workspace/1.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3448648276
Short name	T401
Test name
Test status
Simulation time	5916719912 ps
CPU time	960.84 seconds
Started	Apr 23 04:05:29 PM PDT 24
Finished	Apr 23 04:21:30 PM PDT 24
Peak memory	600192 kb
Host	smart-6b34d801-6e35-4d58-b3e9-0d707094e6c7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448648276 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.3448648276
Directory	/workspace/1.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1491095704
Short name	T1060
Test name
Test status
Simulation time	5859983557 ps
CPU time	1065.12 seconds
Started	Apr 23 04:05:02 PM PDT 24
Finished	Apr 23 04:22:48 PM PDT 24
Peak memory	600244 kb
Host	smart-696b3ece-5458-4ee4-b77d-29305e601720
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491095704 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1491095704
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3171004721
Short name	T121
Test name
Test status
Simulation time	7700213825 ps
CPU time	995.21 seconds
Started	Apr 23 04:11:02 PM PDT 24
Finished	Apr 23 04:27:37 PM PDT 24
Peak memory	600144 kb
Host	smart-47dbd91f-0ad3-4c3b-a6c9-bd7b5885f4a7
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171004721 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3171004721
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3351621598
Short name	T370
Test name
Test status
Simulation time	5460318512 ps
CPU time	878.3 seconds
Started	Apr 23 04:04:22 PM PDT 24
Finished	Apr 23 04:19:01 PM PDT 24
Peak memory	600224 kb
Host	smart-fad9f9ef-61cf-49c0-8eda-819e0ffa6831
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351621598 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3351621598
Directory	/workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1598848020
Short name	T1062
Test name
Test status
Simulation time	3989681176 ps
CPU time	286.56 seconds
Started	Apr 23 04:06:10 PM PDT 24
Finished	Apr 23 04:10:57 PM PDT 24
Peak memory	599936 kb
Host	smart-56ea8f96-4f7c-4a5a-8235-5d1b7e135c5e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598848020 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1598848020
Directory	/workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1651518008
Short name	T217
Test name
Test status
Simulation time	4722515040 ps
CPU time	374.62 seconds
Started	Apr 23 04:05:10 PM PDT 24
Finished	Apr 23 04:11:25 PM PDT 24
Peak memory	600504 kb
Host	smart-f5d8f209-6814-46be-913c-14df029038fd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16 51518008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1651518008
Directory	/workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1619127324
Short name	T988
Test name
Test status
Simulation time	6029154094 ps
CPU time	1017.4 seconds
Started	Apr 23 04:12:52 PM PDT 24
Finished	Apr 23 04:29:50 PM PDT 24
Peak memory	600216 kb
Host	smart-da48956c-ca57-485b-ae99-ddc0e7e9ebe6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619127324 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.1619127324
Directory	/workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1261845369
Short name	T1126
Test name
Test status
Simulation time	4586560216 ps
CPU time	555.35 seconds
Started	Apr 23 04:05:11 PM PDT 24
Finished	Apr 23 04:14:27 PM PDT 24
Peak memory	600300 kb
Host	smart-888a63a4-cc1f-4186-8835-1f8ed143592b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261845369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1261845369
Directory	/workspace/1.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.112320638
Short name	T332
Test name
Test status
Simulation time	4190669862 ps
CPU time	571.34 seconds
Started	Apr 23 04:06:04 PM PDT 24
Finished	Apr 23 04:15:35 PM PDT 24
Peak memory	600052 kb
Host	smart-f5b8a953-c3e7-49e0-ad93-09c7390b3865
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=112320638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.112320638
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2383683487
Short name	T306
Test name
Test status
Simulation time	4443712001 ps
CPU time	677.09 seconds
Started	Apr 23 04:11:37 PM PDT 24
Finished	Apr 23 04:22:54 PM PDT 24
Peak memory	600200 kb
Host	smart-40648f0a-2d09-4e78-b523-e2eba48f59f5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2383683487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2383683487
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_init.3009620210
Short name	T1165
Test name
Test status
Simulation time	25383364850 ps
CPU time	2311.08 seconds
Started	Apr 23 04:06:29 PM PDT 24
Finished	Apr 23 04:45:01 PM PDT 24
Peak memory	607296 kb
Host	smart-c3d2e78f-08e1-4377-ace0-82f3decd79b1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009620210 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3009620210
Directory	/workspace/1.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2961336285
Short name	T962
Test name
Test status
Simulation time	2532323560 ps
CPU time	198.15 seconds
Started	Apr 23 04:17:11 PM PDT 24
Finished	Apr 23 04:20:31 PM PDT 24
Peak memory	599992 kb
Host	smart-93a901d7-0603-48d5-ad2e-d40e1b1d9ee7
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2961336285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.2961336285
Directory	/workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_gpio_smoketest.2135972587
Short name	T966
Test name
Test status
Simulation time	2791778984 ps
CPU time	211.75 seconds
Started	Apr 23 04:14:00 PM PDT 24
Finished	Apr 23 04:17:32 PM PDT 24
Peak memory	600252 kb
Host	smart-c7f061ba-b81e-4132-89d1-c188b6564da3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135972587 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.2135972587
Directory	/workspace/1.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3315949277
Short name	T1216
Test name
Test status
Simulation time	2969261800 ps
CPU time	310.31 seconds
Started	Apr 23 04:09:55 PM PDT 24
Finished	Apr 23 04:15:05 PM PDT 24
Peak memory	599932 kb
Host	smart-b601deb5-3796-4dd4-a017-11a7513bf4f4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315949277 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.3315949277
Directory	/workspace/1.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.407194338
Short name	T335
Test name
Test status
Simulation time	3216023311 ps
CPU time	257.13 seconds
Started	Apr 23 04:08:53 PM PDT 24
Finished	Apr 23 04:13:10 PM PDT 24
Peak memory	599980 kb
Host	smart-e53b97ec-4a52-40d9-aaf8-20c3cca40084
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407194338 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.407194338
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3109535900
Short name	T388
Test name
Test status
Simulation time	2549290547 ps
CPU time	235.78 seconds
Started	Apr 23 04:11:35 PM PDT 24
Finished	Apr 23 04:15:31 PM PDT 24
Peak memory	599956 kb
Host	smart-e476d2c0-3c5d-4f67-9a73-32f6c8d3c3e1
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109535900 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.3109535900
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1951316050
Short name	T842
Test name
Test status
Simulation time	3711646656 ps
CPU time	336.3 seconds
Started	Apr 23 04:13:57 PM PDT 24
Finished	Apr 23 04:19:33 PM PDT 24
Peak memory	599860 kb
Host	smart-b2f15681-212b-43b2-ba95-01bb13e24f83
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951316050 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.1951316050
Directory	/workspace/1.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2123701549
Short name	T361
Test name
Test status
Simulation time	4581411180 ps
CPU time	538.06 seconds
Started	Apr 23 04:04:28 PM PDT 24
Finished	Apr 23 04:13:27 PM PDT 24
Peak memory	600600 kb
Host	smart-d7fa3e3a-cd8d-4589-8e71-3bec573dcf96
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123701549 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2123701549
Directory	/workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3001283484
Short name	T194
Test name
Test status
Simulation time	5464886340 ps
CPU time	778.12 seconds
Started	Apr 23 04:03:48 PM PDT 24
Finished	Apr 23 04:16:47 PM PDT 24
Peak memory	600320 kb
Host	smart-75d545cf-fa9b-49b9-a8df-347eb3d03914
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001283484 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.3001283484
Directory	/workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4210336069
Short name	T197
Test name
Test status
Simulation time	4513800696 ps
CPU time	759.47 seconds
Started	Apr 23 04:03:59 PM PDT 24
Finished	Apr 23 04:16:40 PM PDT 24
Peak memory	600272 kb
Host	smart-6f266ede-977d-4e02-a08c-3d434df33ab2
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210336069 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.4210336069
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.328394394
Short name	T317
Test name
Test status
Simulation time	4386601210 ps
CPU time	609.16 seconds
Started	Apr 23 04:04:31 PM PDT 24
Finished	Apr 23 04:14:41 PM PDT 24
Peak memory	600236 kb
Host	smart-e517bc3a-3256-43b7-889b-03e08769c701
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328394394 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.328394394
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1667144849
Short name	T1084
Test name
Test status
Simulation time	64487944020 ps
CPU time	12844.9 seconds
Started	Apr 23 04:04:26 PM PDT 24
Finished	Apr 23 07:38:32 PM PDT 24
Peak memory	615804 kb
Host	smart-570a4ace-c390-4f9d-87a2-9108d2b6fcb2
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1667144849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1667144849
Directory	/workspace/1.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1161225779
Short name	T211
Test name
Test status
Simulation time	3717699860 ps
CPU time	454.61 seconds
Started	Apr 23 04:08:36 PM PDT 24
Finished	Apr 23 04:16:11 PM PDT 24
Peak memory	606216 kb
Host	smart-ec8f6af4-15f8-4bd7-8b0e-89726596b28c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161 225779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1161225779
Directory	/workspace/1.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1190982013
Short name	T1111
Test name
Test status
Simulation time	3481725905 ps
CPU time	347.21 seconds
Started	Apr 23 04:10:44 PM PDT 24
Finished	Apr 23 04:16:32 PM PDT 24
Peak memory	606548 kb
Host	smart-14df6ce6-9ecf-4833-aa66-138897c23bac
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1190982013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1190982013
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1300748780
Short name	T1092
Test name
Test status
Simulation time	4740975879 ps
CPU time	514.07 seconds
Started	Apr 23 04:12:42 PM PDT 24
Finished	Apr 23 04:21:16 PM PDT 24
Peak memory	607216 kb
Host	smart-f188e540-a03d-416f-b550-fe534ab07dae
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1300748780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1300748780
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2015276543
Short name	T872
Test name
Test status
Simulation time	3110750794 ps
CPU time	353.33 seconds
Started	Apr 23 04:09:35 PM PDT 24
Finished	Apr 23 04:15:29 PM PDT 24
Peak memory	607524 kb
Host	smart-96cc087e-268c-4150-9ad9-af856e67f28f
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2015276543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2015276543
Directory	/workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.83254107
Short name	T207
Test name
Test status
Simulation time	3743850820 ps
CPU time	394.77 seconds
Started	Apr 23 04:09:44 PM PDT 24
Finished	Apr 23 04:16:20 PM PDT 24
Peak memory	601056 kb
Host	smart-154ebace-a2b5-466c-8f8b-885a2a417ba2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832541 07 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.83254107
Directory	/workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.970336501
Short name	T951
Test name
Test status
Simulation time	4935714890 ps
CPU time	591.54 seconds
Started	Apr 23 04:09:25 PM PDT 24
Finished	Apr 23 04:19:17 PM PDT 24
Peak memory	600904 kb
Host	smart-aca0f02b-dea5-4fe3-8e29-9622d2cb32f6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97033 6501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.970336501
Directory	/workspace/1.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1387889948
Short name	T208
Test name
Test status
Simulation time	14296729578 ps
CPU time	3524.21 seconds
Started	Apr 23 04:10:41 PM PDT 24
Finished	Apr 23 05:09:26 PM PDT 24
Peak memory	600432 kb
Host	smart-36614fb4-35be-41bb-9f48-c6b59e6f9e9e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13878 89948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.1387889948
Directory	/workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_app_rom.1050777479
Short name	T1038
Test name
Test status
Simulation time	2321066000 ps
CPU time	153.92 seconds
Started	Apr 23 04:10:14 PM PDT 24
Finished	Apr 23 04:12:49 PM PDT 24
Peak memory	600180 kb
Host	smart-7c165094-8a23-408c-8d49-f7778f653a06
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050777479 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.1050777479
Directory	/workspace/1.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_idle.869747399
Short name	T877
Test name
Test status
Simulation time	2625088126 ps
CPU time	319.68 seconds
Started	Apr 23 04:09:32 PM PDT 24
Finished	Apr 23 04:14:53 PM PDT 24
Peak memory	599896 kb
Host	smart-fb13671c-6dcb-4b29-aa16-b50786b9f42c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869747399 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_idle.869747399
Directory	/workspace/1.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3386598734
Short name	T1112
Test name
Test status
Simulation time	3269128938 ps
CPU time	231.31 seconds
Started	Apr 23 04:10:37 PM PDT 24
Finished	Apr 23 04:14:29 PM PDT 24
Peak memory	599916 kb
Host	smart-b015fcfe-bd62-4718-b1c0-c24287d36f85
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386598734 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3386598734
Directory	/workspace/1.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2152363044
Short name	T1155
Test name
Test status
Simulation time	3813910056 ps
CPU time	251.25 seconds
Started	Apr 23 04:09:07 PM PDT 24
Finished	Apr 23 04:13:18 PM PDT 24
Peak memory	599864 kb
Host	smart-bb02f69f-c97b-4fd7-8732-af502d30e2e5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152363044 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.2152363044
Directory	/workspace/1.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3621030525
Short name	T246
Test name
Test status
Simulation time	3171426910 ps
CPU time	276.35 seconds
Started	Apr 23 04:10:36 PM PDT 24
Finished	Apr 23 04:15:13 PM PDT 24
Peak memory	599988 kb
Host	smart-d0b56b93-18c2-44ac-bded-ba0bc4126520
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621030525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.3621030525
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2131625843
Short name	T1036
Test name
Test status
Simulation time	3791877632 ps
CPU time	262.37 seconds
Started	Apr 23 04:13:07 PM PDT 24
Finished	Apr 23 04:17:30 PM PDT 24
Peak memory	599820 kb
Host	smart-1dd9e133-09d5-444e-99f3-c9e8683dd307
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21316258 43 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2131625843
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_smoketest.3224693621
Short name	T1141
Test name
Test status
Simulation time	2881099492 ps
CPU time	332.12 seconds
Started	Apr 23 04:14:31 PM PDT 24
Finished	Apr 23 04:20:04 PM PDT 24
Peak memory	599928 kb
Host	smart-cf81ef74-868e-4023-850b-a9671fbe42f1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224693621 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.3224693621
Directory	/workspace/1.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1659323573
Short name	T950
Test name
Test status
Simulation time	3366806118 ps
CPU time	302.74 seconds
Started	Apr 23 04:05:23 PM PDT 24
Finished	Apr 23 04:10:26 PM PDT 24
Peak memory	600204 kb
Host	smart-21e2b5f2-2df1-4a7e-9cc0-ff5ce276a657
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659323573 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.1659323573
Directory	/workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3945367890
Short name	T178
Test name
Test status
Simulation time	2713883864 ps
CPU time	193.2 seconds
Started	Apr 23 04:05:29 PM PDT 24
Finished	Apr 23 04:08:43 PM PDT 24
Peak memory	612464 kb
Host	smart-fe8890a0-7c43-42c3-a0c4-b572731efdea
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453678 90 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3945367890
Directory	/workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.242780653
Short name	T1057
Test name
Test status
Simulation time	5098969288 ps
CPU time	349.97 seconds
Started	Apr 23 04:07:02 PM PDT 24
Finished	Apr 23 04:12:52 PM PDT 24
Peak memory	611740 kb
Host	smart-d664254b-e987-4580-ab80-6572bf8f0041
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242780653 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.242780653
Directory	/workspace/1.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.303906167
Short name	T249
Test name
Test status
Simulation time	2689469074 ps
CPU time	102.03 seconds
Started	Apr 23 04:05:31 PM PDT 24
Finished	Apr 23 04:07:13 PM PDT 24
Peak memory	606868 kb
Host	smart-80afa365-2213-4078-bc1e-2df370e961f2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=303906167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.303906167
Directory	/workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2778789652
Short name	T1161
Test name
Test status
Simulation time	2609742572 ps
CPU time	103.96 seconds
Started	Apr 23 04:06:55 PM PDT 24
Finished	Apr 23 04:08:39 PM PDT 24
Peak memory	606960 kb
Host	smart-febf4783-c09d-4fff-b48c-25657e0f7f70
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778789652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2778789652
Directory	/workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1541130383
Short name	T1128
Test name
Test status
Simulation time	49399582420 ps
CPU time	5040.64 seconds
Started	Apr 23 04:04:43 PM PDT 24
Finished	Apr 23 05:28:44 PM PDT 24
Peak memory	607636 kb
Host	smart-bd187eef-9507-440e-83ab-22e54cda14a0
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541130383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.1541130383
Directory	/workspace/1.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.42764199
Short name	T219
Test name
Test status
Simulation time	47968627320 ps
CPU time	5324.91 seconds
Started	Apr 23 04:06:20 PM PDT 24
Finished	Apr 23 05:35:06 PM PDT 24
Peak memory	609712 kb
Host	smart-c3a978a2-fe88-4b00-b062-a14898f0d0d1
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42764199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_prod.42764199
Directory	/workspace/1.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.4037763847
Short name	T913
Test name
Test status
Simulation time	10333873415 ps
CPU time	868.81 seconds
Started	Apr 23 04:05:13 PM PDT 24
Finished	Apr 23 04:19:44 PM PDT 24
Peak memory	607532 kb
Host	smart-2b72c202-8a41-4d77-ba22-f305bb01f894
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037763847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.4037763847
Directory	/workspace/1.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1534732190
Short name	T1051
Test name
Test status
Simulation time	49385359851 ps
CPU time	5048.9 seconds
Started	Apr 23 04:06:44 PM PDT 24
Finished	Apr 23 05:30:54 PM PDT 24
Peak memory	607672 kb
Host	smart-0ef31c3f-ba59-4b87-85f1-de1081fb3206
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534732190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1534732190
Directory	/workspace/1.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3360067441
Short name	T168
Test name
Test status
Simulation time	20681904111 ps
CPU time	2142.14 seconds
Started	Apr 23 04:06:42 PM PDT 24
Finished	Apr 23 04:42:26 PM PDT 24
Peak memory	606576 kb
Host	smart-464c8ff0-3cf0-485f-bb36-6a3fc66548a2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3360067441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.3360067441
Directory	/workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2128924107
Short name	T1147
Test name
Test status
Simulation time	16756113246 ps
CPU time	3818.84 seconds
Started	Apr 23 04:08:57 PM PDT 24
Finished	Apr 23 05:12:36 PM PDT 24
Peak memory	600356 kb
Host	smart-64f41fcf-da6f-4710-9761-d4676b776e23
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2128924107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.2128924107
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3272989163
Short name	T891
Test name
Test status
Simulation time	18959744899 ps
CPU time	3712.67 seconds
Started	Apr 23 04:06:56 PM PDT 24
Finished	Apr 23 05:08:50 PM PDT 24
Peak memory	600336 kb
Host	smart-8790970e-0d81-40d8-a5b6-27ca8172311c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3272989163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3272989163
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3130629359
Short name	T1133
Test name
Test status
Simulation time	3372479100 ps
CPU time	413.53 seconds
Started	Apr 23 04:07:03 PM PDT 24
Finished	Apr 23 04:13:57 PM PDT 24
Peak memory	599864 kb
Host	smart-ca14c2ac-bc50-4d4b-b760-710f8140a2e1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130629359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3130629359
Directory	/workspace/1.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_randomness.2813321726
Short name	T392
Test name
Test status
Simulation time	6040795324 ps
CPU time	1175.94 seconds
Started	Apr 23 04:08:03 PM PDT 24
Finished	Apr 23 04:27:40 PM PDT 24
Peak memory	600428 kb
Host	smart-2ec457af-e27a-49ac-851f-13fbe23f91e2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2813321726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2813321726
Directory	/workspace/1.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_smoketest.3988329772
Short name	T1065
Test name
Test status
Simulation time	7996905146 ps
CPU time	1766.61 seconds
Started	Apr 23 04:13:41 PM PDT 24
Finished	Apr 23 04:43:09 PM PDT 24
Peak memory	600260 kb
Host	smart-2a517043-6764-4537-b09d-aebba810f68f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988329772 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.3988329772
Directory	/workspace/1.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3175883541
Short name	T1096
Test name
Test status
Simulation time	7588307480 ps
CPU time	1327.58 seconds
Started	Apr 23 04:06:19 PM PDT 24
Finished	Apr 23 04:28:28 PM PDT 24
Peak memory	600520 kb
Host	smart-79aa7bc1-4ca9-4705-998b-ab922da5d1da
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3175883541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3175883541
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3280919124
Short name	T357
Test name
Test status
Simulation time	8480814974 ps
CPU time	1030.9 seconds
Started	Apr 23 04:06:35 PM PDT 24
Finished	Apr 23 04:23:47 PM PDT 24
Peak memory	600292 kb
Host	smart-40d9984b-af9f-4cd3-adfa-14a624c3adb0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3280919124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3280919124
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3871045216
Short name	T940
Test name
Test status
Simulation time	6908488640 ps
CPU time	1312.58 seconds
Started	Apr 23 04:05:36 PM PDT 24
Finished	Apr 23 04:27:30 PM PDT 24
Peak memory	600532 kb
Host	smart-e96b3e3d-4785-4626-b95c-6fe633db2bb6
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3871045216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3871045216
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1856483562
Short name	T865
Test name
Test status
Simulation time	5093710208 ps
CPU time	677.55 seconds
Started	Apr 23 04:07:09 PM PDT 24
Finished	Apr 23 04:18:27 PM PDT 24
Peak memory	600204 kb
Host	smart-38b10dda-2bde-4e1a-87d0-720488070385
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1856483562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1856483562
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.699425082
Short name	T158
Test name
Test status
Simulation time	2371470320 ps
CPU time	166.51 seconds
Started	Apr 23 04:13:23 PM PDT 24
Finished	Apr 23 04:16:10 PM PDT 24
Peak memory	599888 kb
Host	smart-2b8ae160-da2a-43d4-84da-c428c50b2fef
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699425082 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_otp_ctrl_smoketest.699425082
Directory	/workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_plic_sw_irq.1167977683
Short name	T233
Test name
Test status
Simulation time	3193919808 ps
CPU time	241.15 seconds
Started	Apr 23 04:10:03 PM PDT 24
Finished	Apr 23 04:14:04 PM PDT 24
Peak memory	599892 kb
Host	smart-a93de336-fb88-41f5-a9b7-1a2dc4cabbd6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167977683 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.1167977683
Directory	/workspace/1.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_power_idle_load.3190362202
Short name	T889
Test name
Test status
Simulation time	4102463584 ps
CPU time	603.91 seconds
Started	Apr 23 04:12:12 PM PDT 24
Finished	Apr 23 04:22:16 PM PDT 24
Peak memory	600320 kb
Host	smart-2b5f3a27-7e68-4711-a9ba-1379333c26f9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190362202 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3190362202
Directory	/workspace/1.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3412533908
Short name	T1218
Test name
Test status
Simulation time	13691057098 ps
CPU time	1671.43 seconds
Started	Apr 23 04:06:39 PM PDT 24
Finished	Apr 23 04:34:31 PM PDT 24
Peak memory	602212 kb
Host	smart-0f745db8-569b-4ced-b30e-d5f64a021bfe
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412 533908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3412533908
Directory	/workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.449261437
Short name	T226
Test name
Test status
Simulation time	28416204940 ps
CPU time	2338.91 seconds
Started	Apr 23 04:09:01 PM PDT 24
Finished	Apr 23 04:48:00 PM PDT 24
Peak memory	600444 kb
Host	smart-98303822-2351-4aeb-be73-d2c34b483010
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449 261437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.449261437
Directory	/workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.658176735
Short name	T907
Test name
Test status
Simulation time	17396238383 ps
CPU time	1598.92 seconds
Started	Apr 23 04:07:15 PM PDT 24
Finished	Apr 23 04:33:54 PM PDT 24
Peak memory	602016 kb
Host	smart-366f3f8b-0bea-4688-97e0-4e497389aad2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=658176735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.658176735
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.442706231
Short name	T935
Test name
Test status
Simulation time	6735533494 ps
CPU time	628.85 seconds
Started	Apr 23 04:06:30 PM PDT 24
Finished	Apr 23 04:17:00 PM PDT 24
Peak memory	600444 kb
Host	smart-041d8dfb-b610-42ff-a84a-caed55899c13
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442706231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.442706231
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.976421112
Short name	T295
Test name
Test status
Simulation time	6358735840 ps
CPU time	506.69 seconds
Started	Apr 23 04:05:40 PM PDT 24
Finished	Apr 23 04:14:07 PM PDT 24
Peak memory	606868 kb
Host	smart-d0bb4098-956a-4b55-b263-e9f320bafcde
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=976421112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.976421112
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2708000791
Short name	T1142
Test name
Test status
Simulation time	3431400668 ps
CPU time	364.16 seconds
Started	Apr 23 04:06:35 PM PDT 24
Finished	Apr 23 04:12:40 PM PDT 24
Peak memory	606860 kb
Host	smart-13c2af6a-fc3c-41d9-b38d-07355618cd46
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2708000791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.2708000791
Directory	/workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2331202362
Short name	T343
Test name
Test status
Simulation time	12512894027 ps
CPU time	996.12 seconds
Started	Apr 23 04:05:58 PM PDT 24
Finished	Apr 23 04:22:34 PM PDT 24
Peak memory	601352 kb
Host	smart-73c8b69d-d0d6-4e9f-a313-318f8575d201
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331202362 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2331202362
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2736964842
Short name	T374
Test name
Test status
Simulation time	7410038262 ps
CPU time	365.19 seconds
Started	Apr 23 04:11:24 PM PDT 24
Finished	Apr 23 04:17:30 PM PDT 24
Peak memory	600600 kb
Host	smart-7516d564-d9c3-40fc-9431-e6d8c71809ed
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736964842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2736964842
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3730829933
Short name	T6
Test name
Test status
Simulation time	5504539605 ps
CPU time	519.52 seconds
Started	Apr 23 04:06:00 PM PDT 24
Finished	Apr 23 04:14:40 PM PDT 24
Peak memory	600588 kb
Host	smart-d20aca4b-dbe1-4024-8abc-7b35bd780cc0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730829933 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3730829933
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1241842405
Short name	T18
Test name
Test status
Simulation time	17350544020 ps
CPU time	1236.02 seconds
Started	Apr 23 04:11:58 PM PDT 24
Finished	Apr 23 04:32:35 PM PDT 24
Peak memory	600820 kb
Host	smart-b2115343-2858-41b5-84c4-908b0254dfb8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1241842405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1241842405
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.500362578
Short name	T1068
Test name
Test status
Simulation time	39259869602 ps
CPU time	3158.6 seconds
Started	Apr 23 04:06:50 PM PDT 24
Finished	Apr 23 04:59:30 PM PDT 24
Peak memory	601840 kb
Host	smart-3030106c-4e9d-42b2-bc38-a04c26389aba
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500362578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.500362578
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.563580319
Short name	T627
Test name
Test status
Simulation time	2765452078 ps
CPU time	223.76 seconds
Started	Apr 23 04:05:59 PM PDT 24
Finished	Apr 23 04:09:43 PM PDT 24
Peak memory	599900 kb
Host	smart-89cac584-9c31-4cd7-8b93-33827721c256
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563580319 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.563580319
Directory	/workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1599597437
Short name	T1094
Test name
Test status
Simulation time	4522226480 ps
CPU time	384.02 seconds
Started	Apr 23 04:06:03 PM PDT 24
Finished	Apr 23 04:12:27 PM PDT 24
Peak memory	607364 kb
Host	smart-499910d0-5319-4480-9131-88a9c59d1746
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1599597437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1599597437
Directory	/workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2175774156
Short name	T138
Test name
Test status
Simulation time	4778779972 ps
CPU time	415.66 seconds
Started	Apr 23 04:10:28 PM PDT 24
Finished	Apr 23 04:17:24 PM PDT 24
Peak memory	600004 kb
Host	smart-bdf84a66-7d27-4ebe-ad7f-82ce1a7f2380
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21757741 56 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2175774156
Directory	/workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3027973243
Short name	T968
Test name
Test status
Simulation time	5188222320 ps
CPU time	338.24 seconds
Started	Apr 23 04:11:40 PM PDT 24
Finished	Apr 23 04:17:19 PM PDT 24
Peak memory	600280 kb
Host	smart-decfc638-7c9a-47bb-ba72-3cfea5e1fe55
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3027973243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.3027973243
Directory	/workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.759958732
Short name	T886
Test name
Test status
Simulation time	5435542364 ps
CPU time	512.58 seconds
Started	Apr 23 04:13:20 PM PDT 24
Finished	Apr 23 04:21:53 PM PDT 24
Peak memory	600408 kb
Host	smart-4632e077-d6d3-45de-8754-f61b3586c795
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759958732 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.759958732
Directory	/workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3386483910
Short name	T1176
Test name
Test status
Simulation time	7714942280 ps
CPU time	1232.84 seconds
Started	Apr 23 04:06:00 PM PDT 24
Finished	Apr 23 04:26:33 PM PDT 24
Peak memory	600540 kb
Host	smart-ed968f59-6b9c-4d99-b90e-76dc3868c897
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386483910 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.3386483910
Directory	/workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.906184419
Short name	T365
Test name
Test status
Simulation time	5165413496 ps
CPU time	552.76 seconds
Started	Apr 23 04:07:31 PM PDT 24
Finished	Apr 23 04:16:44 PM PDT 24
Peak memory	600336 kb
Host	smart-a4a7c99e-a52a-4893-a33d-a70560d9e0fe
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906184419 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.906184419
Directory	/workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.482181456
Short name	T80
Test name
Test status
Simulation time	5895731012 ps
CPU time	408.93 seconds
Started	Apr 23 04:14:09 PM PDT 24
Finished	Apr 23 04:20:59 PM PDT 24
Peak memory	600296 kb
Host	smart-225ce35b-e3c3-4039-a6ad-bce898997014
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482181456 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.482181456
Directory	/workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.311514307
Short name	T885
Test name
Test status
Simulation time	3703311960 ps
CPU time	417.82 seconds
Started	Apr 23 04:06:58 PM PDT 24
Finished	Apr 23 04:13:58 PM PDT 24
Peak memory	599220 kb
Host	smart-cdbe04d0-8b96-4e8b-9841-5c2e4a6ce494
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311 514307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.311514307
Directory	/workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3292395271
Short name	T250
Test name
Test status
Simulation time	9391221669 ps
CPU time	491.53 seconds
Started	Apr 23 04:09:42 PM PDT 24
Finished	Apr 23 04:17:54 PM PDT 24
Peak memory	600492 kb
Host	smart-6e1b168b-290c-4983-8747-0ebef8bbf746
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292395271 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.3292395271
Directory	/workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.835719028
Short name	T240
Test name
Test status
Simulation time	5456719616 ps
CPU time	755.19 seconds
Started	Apr 23 04:08:49 PM PDT 24
Finished	Apr 23 04:21:25 PM PDT 24
Peak memory	600248 kb
Host	smart-67472810-8c4e-45bf-b4df-1d0d2bed66bc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835719028 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_rstmgr_cpu_info.835719028
Directory	/workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3875417710
Short name	T924
Test name
Test status
Simulation time	4663619158 ps
CPU time	474.86 seconds
Started	Apr 23 04:02:44 PM PDT 24
Finished	Apr 23 04:10:40 PM PDT 24
Peak memory	631460 kb
Host	smart-2a67a901-dbe4-46ec-a5db-919eaec9433d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3875417710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.3875417710
Directory	/workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1561372259
Short name	T1113
Test name
Test status
Simulation time	3071675732 ps
CPU time	201.66 seconds
Started	Apr 23 04:14:21 PM PDT 24
Finished	Apr 23 04:17:43 PM PDT 24
Peak memory	600208 kb
Host	smart-b4c80e3c-9a06-4d8d-adca-cf25ab53d83d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561372259 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.1561372259
Directory	/workspace/1.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1351917010
Short name	T1148
Test name
Test status
Simulation time	3982397296 ps
CPU time	423.81 seconds
Started	Apr 23 04:08:49 PM PDT 24
Finished	Apr 23 04:15:54 PM PDT 24
Peak memory	600032 kb
Host	smart-432ca70f-44fd-4918-9cd0-decb1a0fd0e0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351917010 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.1351917010
Directory	/workspace/1.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3815793003
Short name	T1103
Test name
Test status
Simulation time	2354123518 ps
CPU time	258.49 seconds
Started	Apr 23 04:05:57 PM PDT 24
Finished	Apr 23 04:10:16 PM PDT 24
Peak memory	599884 kb
Host	smart-9b43a882-39f7-4cd0-816d-ec3f5cd0b417
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815793003 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.3815793003
Directory	/workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3227798854
Short name	T277
Test name
Test status
Simulation time	2196472132 ps
CPU time	286.65 seconds
Started	Apr 23 04:13:57 PM PDT 24
Finished	Apr 23 04:18:45 PM PDT 24
Peak memory	599904 kb
Host	smart-545c2dbc-1001-4516-980c-d7999a65db00
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3227798854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.3227798854
Directory	/workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3898907566
Short name	T276
Test name
Test status
Simulation time	2493762745 ps
CPU time	152.28 seconds
Started	Apr 23 04:11:13 PM PDT 24
Finished	Apr 23 04:13:46 PM PDT 24
Peak memory	600012 kb
Host	smart-45de4749-2710-41c4-8362-4f92502fc578
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898907566 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.3898907566
Directory	/workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2389503725
Short name	T1087
Test name
Test status
Simulation time	2214691730 ps
CPU time	127.16 seconds
Started	Apr 23 04:10:54 PM PDT 24
Finished	Apr 23 04:13:02 PM PDT 24
Peak memory	635676 kb
Host	smart-14bfcaac-adbf-404a-aadb-360eea5f57fa
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389503725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.2389503725
Directory	/workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1351529020
Short name	T639
Test name
Test status
Simulation time	4915474180 ps
CPU time	726.56 seconds
Started	Apr 23 04:07:28 PM PDT 24
Finished	Apr 23 04:19:35 PM PDT 24
Peak memory	600240 kb
Host	smart-077608bc-31f4-42fb-a4ad-834a99ce4557
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13515 29020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1351529020
Directory	/workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.112210993
Short name	T867
Test name
Test status
Simulation time	5163766308 ps
CPU time	794.91 seconds
Started	Apr 23 04:08:03 PM PDT 24
Finished	Apr 23 04:21:19 PM PDT 24
Peak memory	600148 kb
Host	smart-e9f8737b-2479-4839-83bf-9ce46a6b92c6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=112210993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.112210993
Directory	/workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1605389102
Short name	T76
Test name
Test status
Simulation time	6030849072 ps
CPU time	659.23 seconds
Started	Apr 23 04:12:18 PM PDT 24
Finished	Apr 23 04:23:18 PM PDT 24
Peak memory	606304 kb
Host	smart-0676091e-e330-4998-b92a-cd043409fa3b
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605389102 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1605389102
Directory	/workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1871518195
Short name	T75
Test name
Test status
Simulation time	5171630534 ps
CPU time	589.23 seconds
Started	Apr 23 04:12:30 PM PDT 24
Finished	Apr 23 04:22:20 PM PDT 24
Peak memory	608448 kb
Host	smart-a6e5e099-cff7-42b8-8663-02613422fb3e
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187151 8195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1871518195
Directory	/workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1727846553
Short name	T1020
Test name
Test status
Simulation time	3206286024 ps
CPU time	197.08 seconds
Started	Apr 23 04:15:02 PM PDT 24
Finished	Apr 23 04:18:19 PM PDT 24
Peak memory	599912 kb
Host	smart-e52c0a95-44a7-47e6-9394-3ee9b24c1463
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727846553 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.1727846553
Directory	/workspace/1.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_irq.3587731344
Short name	T1028
Test name
Test status
Simulation time	2487093124 ps
CPU time	187.04 seconds
Started	Apr 23 04:07:25 PM PDT 24
Finished	Apr 23 04:10:33 PM PDT 24
Peak memory	599876 kb
Host	smart-0267b0ca-d973-4790-b5d6-8c5587e5b899
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587731344 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.3587731344
Directory	/workspace/1.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2772274989
Short name	T956
Test name
Test status
Simulation time	2672455880 ps
CPU time	224.88 seconds
Started	Apr 23 04:13:42 PM PDT 24
Finished	Apr 23 04:17:28 PM PDT 24
Peak memory	599844 kb
Host	smart-114eeded-102b-43a1-871c-f8982d34280a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772274989 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2772274989
Directory	/workspace/1.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1524362359
Short name	T147
Test name
Test status
Simulation time	2826546459 ps
CPU time	259.24 seconds
Started	Apr 23 04:10:25 PM PDT 24
Finished	Apr 23 04:14:45 PM PDT 24
Peak memory	600508 kb
Host	smart-774b74b2-102c-492d-8abe-17f1ba9920e6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524362 359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1524362359
Directory	/workspace/1.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1086100815
Short name	T55
Test name
Test status
Simulation time	3667389558 ps
CPU time	230.28 seconds
Started	Apr 23 04:03:25 PM PDT 24
Finished	Apr 23 04:07:16 PM PDT 24
Peak memory	600352 kb
Host	smart-ce83a1be-f9e5-426d-bcaa-f692700ce80b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086100815 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.1086100815
Directory	/workspace/1.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1413405548
Short name	T1207
Test name
Test status
Simulation time	9244633032 ps
CPU time	1568.56 seconds
Started	Apr 23 04:04:55 PM PDT 24
Finished	Apr 23 04:31:04 PM PDT 24
Peak memory	600676 kb
Host	smart-e7a33292-f677-4fcf-a7ce-28bc2d4b161c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413405548 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1413405548
Directory	/workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3727597721
Short name	T997
Test name
Test status
Simulation time	7997063528 ps
CPU time	442.86 seconds
Started	Apr 23 04:10:14 PM PDT 24
Finished	Apr 23 04:17:37 PM PDT 24
Peak memory	601472 kb
Host	smart-9a0d4f23-82f7-4786-8c67-7a026d6e614f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727597721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.3727597721
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1495531264
Short name	T957
Test name
Test status
Simulation time	7074540002 ps
CPU time	632.98 seconds
Started	Apr 23 04:08:52 PM PDT 24
Finished	Apr 23 04:19:26 PM PDT 24
Peak memory	601532 kb
Host	smart-c59d9339-72b9-4e2f-8173-34faea309ba5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495531264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1495531264
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1327382153
Short name	T1034
Test name
Test status
Simulation time	6630179422 ps
CPU time	632.98 seconds
Started	Apr 23 04:05:46 PM PDT 24
Finished	Apr 23 04:16:20 PM PDT 24
Peak memory	617684 kb
Host	smart-6413e73f-455b-40ba-ba68-4c2fad76bab6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327382153 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1327382153
Directory	/workspace/1.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.619967976
Short name	T11
Test name
Test status
Simulation time	4564396257 ps
CPU time	357.36 seconds
Started	Apr 23 04:03:47 PM PDT 24
Finished	Apr 23 04:09:45 PM PDT 24
Peak memory	617172 kb
Host	smart-08a85ed6-8b8d-4048-aad9-aa091be7ea8f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619967976 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.619967976
Directory	/workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_tpm.4091909030
Short name	T42
Test name
Test status
Simulation time	3707504487 ps
CPU time	292.78 seconds
Started	Apr 23 04:04:10 PM PDT 24
Finished	Apr 23 04:09:04 PM PDT 24
Peak memory	609560 kb
Host	smart-dbeecaae-bce2-4cd6-a1cd-97fd234f865a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091909030 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.4091909030
Directory	/workspace/1.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1505064194
Short name	T35
Test name
Test status
Simulation time	3263930698 ps
CPU time	251.86 seconds
Started	Apr 23 04:03:45 PM PDT 24
Finished	Apr 23 04:07:58 PM PDT 24
Peak memory	599936 kb
Host	smart-f5df31ec-bc48-479d-b5d8-f7179b37951e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505064194 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1505064194
Directory	/workspace/1.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2081063418
Short name	T280
Test name
Test status
Simulation time	9816095355 ps
CPU time	1093.72 seconds
Started	Apr 23 04:10:06 PM PDT 24
Finished	Apr 23 04:28:21 PM PDT 24
Peak memory	600620 kb
Host	smart-b21dfbdd-593c-4cf7-8831-8e7c39f52382
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081063418 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.2081063418
Directory	/workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2545059133
Short name	T181
Test name
Test status
Simulation time	4002703146 ps
CPU time	514.62 seconds
Started	Apr 23 04:10:01 PM PDT 24
Finished	Apr 23 04:18:36 PM PDT 24
Peak memory	600464 kb
Host	smart-621ae6f9-e72a-4f67-8d6e-a736e6a15a98
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545059133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.2545059133
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2041355414
Short name	T503
Test name
Test status
Simulation time	5007467725 ps
CPU time	650.23 seconds
Started	Apr 23 04:12:23 PM PDT 24
Finished	Apr 23 04:23:14 PM PDT 24
Peak memory	600428 kb
Host	smart-d23e0797-fdd8-444c-9489-2b9528d0e00e
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041355414 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2041355414
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.388346223
Short name	T841
Test name
Test status
Simulation time	2196925280 ps
CPU time	169.87 seconds
Started	Apr 23 04:14:39 PM PDT 24
Finished	Apr 23 04:17:29 PM PDT 24
Peak memory	600200 kb
Host	smart-14858ab8-834c-410b-95c5-fa9f72ba067b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388346223 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sram_ctrl_smoketest.388346223
Directory	/workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.784646347
Short name	T647
Test name
Test status
Simulation time	20486896933 ps
CPU time	2813.16 seconds
Started	Apr 23 04:06:36 PM PDT 24
Finished	Apr 23 04:53:30 PM PDT 24
Peak memory	600692 kb
Host	smart-0e37e03e-d8c4-451e-8548-5dc65dc34b30
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784646347 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.784646347
Directory	/workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2377198920
Short name	T1180
Test name
Test status
Simulation time	4206242385 ps
CPU time	522.71 seconds
Started	Apr 23 04:07:11 PM PDT 24
Finished	Apr 23 04:15:56 PM PDT 24
Peak memory	604540 kb
Host	smart-57ca4e0c-e326-4e40-a2f2-3d58708b2b4f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377198920 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.2377198920
Directory	/workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2474108696
Short name	T192
Test name
Test status
Simulation time	3131593607 ps
CPU time	252.67 seconds
Started	Apr 23 04:07:17 PM PDT 24
Finished	Apr 23 04:11:32 PM PDT 24
Peak memory	603436 kb
Host	smart-cedb71c7-2c0a-4ffe-8f11-64cdca1fd9c1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474108696 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.2474108696
Directory	/workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3901129646
Short name	T39
Test name
Test status
Simulation time	4734143900 ps
CPU time	417.56 seconds
Started	Apr 23 04:07:07 PM PDT 24
Finished	Apr 23 04:14:06 PM PDT 24
Peak memory	600432 kb
Host	smart-6c957691-28e9-4076-9c74-d7a0997ac701
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901129646 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3901129646
Directory	/workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.819289534
Short name	T1054
Test name
Test status
Simulation time	8568290780 ps
CPU time	1927.67 seconds
Started	Apr 23 04:05:31 PM PDT 24
Finished	Apr 23 04:37:40 PM PDT 24
Peak memory	607548 kb
Host	smart-31cdfe4b-b55f-4fff-bfdf-56cfc1aa6f9b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=819289534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.819289534
Directory	/workspace/1.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_smoketest.3263589204
Short name	T896
Test name
Test status
Simulation time	2840267306 ps
CPU time	225.46 seconds
Started	Apr 23 04:14:52 PM PDT 24
Finished	Apr 23 04:18:38 PM PDT 24
Peak memory	600036 kb
Host	smart-43d8590f-4be9-4d76-86a3-16662b04b832
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263589204 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.3263589204
Directory	/workspace/1.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx.2245121205
Short name	T202
Test name
Test status
Simulation time	4335079970 ps
CPU time	599.59 seconds
Started	Apr 23 04:04:16 PM PDT 24
Finished	Apr 23 04:14:16 PM PDT 24
Peak memory	607452 kb
Host	smart-095fcf24-0be4-4e2e-a0c4-a08c46e1790d
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245121205 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.2245121205
Directory	/workspace/1.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2204464182
Short name	T1027
Test name
Test status
Simulation time	13268065944 ps
CPU time	3026.02 seconds
Started	Apr 23 04:03:30 PM PDT 24
Finished	Apr 23 04:53:57 PM PDT 24
Peak memory	607492 kb
Host	smart-47c86e3b-db91-4aa5-9625-1228bf81f838
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204464182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.2204464182
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.89274891
Short name	T1179
Test name
Test status
Simulation time	4978601585 ps
CPU time	698.45 seconds
Started	Apr 23 04:04:25 PM PDT 24
Finished	Apr 23 04:16:05 PM PDT 24
Peak memory	607544 kb
Host	smart-0a03a799-cb6b-4a49-8903-96b128d9e0a6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89274891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_bau drate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_a lt_clk_freq_low_speed.89274891
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1579338791
Short name	T928
Test name
Test status
Simulation time	3998834304 ps
CPU time	579.06 seconds
Started	Apr 23 04:03:35 PM PDT 24
Finished	Apr 23 04:13:15 PM PDT 24
Peak memory	607440 kb
Host	smart-8873fa73-9aa0-49c2-b578-da4d241ffc3c
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579338791 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1579338791
Directory	/workspace/1.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1589058200
Short name	T883
Test name
Test status
Simulation time	4486636176 ps
CPU time	514.47 seconds
Started	Apr 23 04:03:20 PM PDT 24
Finished	Apr 23 04:11:55 PM PDT 24
Peak memory	608548 kb
Host	smart-ce610aa5-8b7e-447d-8eec-e9d93e8d7494
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589058200 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1589058200
Directory	/workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.556841982
Short name	T15
Test name
Test status
Simulation time	4431337432 ps
CPU time	626.36 seconds
Started	Apr 23 04:05:00 PM PDT 24
Finished	Apr 23 04:15:27 PM PDT 24
Peak memory	607376 kb
Host	smart-f3d26027-dfc7-4f8e-a5aa-29270df33ee5
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556841982 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.556841982
Directory	/workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_dev.3825904879
Short name	T996
Test name
Test status
Simulation time	11578073286 ps
CPU time	1324.22 seconds
Started	Apr 23 04:10:23 PM PDT 24
Finished	Apr 23 04:32:28 PM PDT 24
Peak memory	609948 kb
Host	smart-98b74b11-fe37-4276-add8-95e49010bed3
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3825904879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.3825904879
Directory	/workspace/1.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_prod.771003498
Short name	T905
Test name
Test status
Simulation time	6777529189 ps
CPU time	560.32 seconds
Started	Apr 23 04:10:55 PM PDT 24
Finished	Apr 23 04:20:15 PM PDT 24
Peak memory	610264 kb
Host	smart-8ae80426-0352-4078-abc9-ab6acfd38a53
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771003498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.771003498
Directory	/workspace/1.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_testunlock0.2617019396
Short name	T3
Test name
Test status
Simulation time	5728450136 ps
CPU time	474.25 seconds
Started	Apr 23 04:11:00 PM PDT 24
Finished	Apr 23 04:18:55 PM PDT 24
Peak memory	617016 kb
Host	smart-77539327-45c6-46da-98e3-973c46055332
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617019396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.2617019396
Directory	/workspace/1.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3088253011
Short name	T1031
Test name
Test status
Simulation time	79096068237 ps
CPU time	15916.1 seconds
Started	Apr 23 04:16:10 PM PDT 24
Finished	Apr 23 08:41:28 PM PDT 24
Peak memory	600628 kb
Host	smart-988d59b4-f2df-4bc5-8e31-d1d7f349d2e0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_ flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088253011 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_test_unlocked0.3088253011
Directory	/workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/1.rom_keymgr_functest.981648145
Short name	T1008
Test name
Test status
Simulation time	4767606290 ps
CPU time	507 seconds
Started	Apr 23 04:18:11 PM PDT 24
Finished	Apr 23 04:26:39 PM PDT 24
Peak memory	600460 kb
Host	smart-58f513e6-ee67-4955-a218-8e9d19d7f53a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981648145 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.981648145
Directory	/workspace/1.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/1.rom_volatile_raw_unlock.4083383180
Short name	T609
Test name
Test status
Simulation time	1959174261 ps
CPU time	96.52 seconds
Started	Apr 23 04:13:25 PM PDT 24
Finished	Apr 23 04:15:02 PM PDT 24
Peak memory	606928 kb
Host	smart-42fde4b3-6d81-45fb-ac2e-805956e1b980
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083383180 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.4083383180
Directory	/workspace/1.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1690474594
Short name	T1080
Test name
Test status
Simulation time	3607695424 ps
CPU time	437.89 seconds
Started	Apr 23 04:27:49 PM PDT 24
Finished	Apr 23 04:35:07 PM PDT 24
Peak memory	606820 kb
Host	smart-2682d721-de81-408f-ba95-1dbd8a1b6296
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690474594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1690474594
Directory	/workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1065522375
Short name	T1208
Test name
Test status
Simulation time	5474295992 ps
CPU time	431.98 seconds
Started	Apr 23 04:29:24 PM PDT 24
Finished	Apr 23 04:36:36 PM PDT 24
Peak memory	612656 kb
Host	smart-c8661952-9252-47f3-af83-7918443c69c6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065522375 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.1065522375
Directory	/workspace/10.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1063034403
Short name	T983
Test name
Test status
Simulation time	4017667840 ps
CPU time	687.92 seconds
Started	Apr 23 04:28:03 PM PDT 24
Finished	Apr 23 04:39:32 PM PDT 24
Peak memory	607416 kb
Host	smart-ab71a6f7-0d33-4b6a-9b5d-b2c78cc3378b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1063034403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.1063034403
Directory	/workspace/10.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1380019396
Short name	T666
Test name
Test status
Simulation time	3514097538 ps
CPU time	388.51 seconds
Started	Apr 23 04:28:23 PM PDT 24
Finished	Apr 23 04:34:53 PM PDT 24
Peak memory	633384 kb
Host	smart-04417cc0-deaf-40d1-9cbf-d80c8c6ea6cd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380019396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1380019396
Directory	/workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.4208713290
Short name	T1114
Test name
Test status
Simulation time	4839288362 ps
CPU time	521.77 seconds
Started	Apr 23 04:27:18 PM PDT 24
Finished	Apr 23 04:36:01 PM PDT 24
Peak memory	611696 kb
Host	smart-3d7aed01-de34-4133-b7d2-ded985c3532d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208713290 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.4208713290
Directory	/workspace/11.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1680981763
Short name	T1200
Test name
Test status
Simulation time	8469333324 ps
CPU time	1539.46 seconds
Started	Apr 23 04:28:16 PM PDT 24
Finished	Apr 23 04:53:57 PM PDT 24
Peak memory	607380 kb
Host	smart-2287fe14-c30b-4c93-9f7b-bf2336a87654
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1680981763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1680981763
Directory	/workspace/11.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.613972114
Short name	T380
Test name
Test status
Simulation time	9079901865 ps
CPU time	805.62 seconds
Started	Apr 23 04:28:33 PM PDT 24
Finished	Apr 23 04:41:59 PM PDT 24
Peak memory	611684 kb
Host	smart-6b679655-8d9d-48f6-8fda-46a5507e76e4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613972114 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.613972114
Directory	/workspace/12.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.233688566
Short name	T325
Test name
Test status
Simulation time	8345037688 ps
CPU time	1500.89 seconds
Started	Apr 23 04:30:04 PM PDT 24
Finished	Apr 23 04:55:06 PM PDT 24
Peak memory	607448 kb
Host	smart-fbe3ba73-3db8-4ba4-8020-e970ad1a180d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=233688566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.233688566
Directory	/workspace/12.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.792063064
Short name	T892
Test name
Test status
Simulation time	9050690229 ps
CPU time	907.79 seconds
Started	Apr 23 04:29:27 PM PDT 24
Finished	Apr 23 04:44:36 PM PDT 24
Peak memory	611748 kb
Host	smart-54105586-ca16-4c80-b23f-9942757cb942
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792063064 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.792063064
Directory	/workspace/13.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3112072547
Short name	T1191
Test name
Test status
Simulation time	7086951827 ps
CPU time	667.25 seconds
Started	Apr 23 04:29:27 PM PDT 24
Finished	Apr 23 04:40:35 PM PDT 24
Peak memory	611680 kb
Host	smart-ee7328a8-a8fe-45fa-bfe6-a3b56c21f79a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112072547 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.3112072547
Directory	/workspace/14.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.636652430
Short name	T195
Test name
Test status
Simulation time	13160711316 ps
CPU time	2390.69 seconds
Started	Apr 23 04:27:30 PM PDT 24
Finished	Apr 23 05:07:21 PM PDT 24
Peak memory	607516 kb
Host	smart-5f01069f-c83b-4eae-ad67-62709d4f7954
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=636652430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.636652430
Directory	/workspace/14.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1337039396
Short name	T876
Test name
Test status
Simulation time	3627184200 ps
CPU time	267.6 seconds
Started	Apr 23 04:28:26 PM PDT 24
Finished	Apr 23 04:32:53 PM PDT 24
Peak memory	606872 kb
Host	smart-e1401e00-c27b-40ac-b0f6-ec6827073052
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337039396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1337039396
Directory	/workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/15.chip_sw_all_escalation_resets.417342254
Short name	T713
Test name
Test status
Simulation time	5296180500 ps
CPU time	469.57 seconds
Started	Apr 23 04:27:05 PM PDT 24
Finished	Apr 23 04:34:54 PM PDT 24
Peak memory	634524 kb
Host	smart-bc797103-efda-4d7e-9806-0b453f7b60af
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 417342254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.417342254
Directory	/workspace/15.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1808479479
Short name	T878
Test name
Test status
Simulation time	12975946590 ps
CPU time	2090.37 seconds
Started	Apr 23 04:30:54 PM PDT 24
Finished	Apr 23 05:05:45 PM PDT 24
Peak memory	607552 kb
Host	smart-cbb1f4fb-e831-40f0-bf5b-f02fb03b3dd7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1808479479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1808479479
Directory	/workspace/15.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.303486062
Short name	T1167
Test name
Test status
Simulation time	12672314246 ps
CPU time	2445.82 seconds
Started	Apr 23 04:29:16 PM PDT 24
Finished	Apr 23 05:10:02 PM PDT 24
Peak memory	607388 kb
Host	smart-68937ea2-eb13-4b20-97d6-b2ac2c1a2fbd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=303486062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.303486062
Directory	/workspace/16.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3610816004
Short name	T200
Test name
Test status
Simulation time	3393158250 ps
CPU time	552.69 seconds
Started	Apr 23 04:28:38 PM PDT 24
Finished	Apr 23 04:37:51 PM PDT 24
Peak memory	607484 kb
Host	smart-68194606-4ec1-460e-86b5-58cf0853d880
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3610816004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.3610816004
Directory	/workspace/17.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2912606633
Short name	T1202
Test name
Test status
Simulation time	8294155576 ps
CPU time	1225.79 seconds
Started	Apr 23 04:29:11 PM PDT 24
Finished	Apr 23 04:49:38 PM PDT 24
Peak memory	607556 kb
Host	smart-95e92c09-1bea-4ba6-8a58-d47bba50105e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2912606633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.2912606633
Directory	/workspace/18.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/19.chip_sw_all_escalation_resets.4294300448
Short name	T243
Test name
Test status
Simulation time	5271092440 ps
CPU time	591.8 seconds
Started	Apr 23 04:28:12 PM PDT 24
Finished	Apr 23 04:38:04 PM PDT 24
Peak memory	636684 kb
Host	smart-9cea7e5b-0f50-4788-b814-1b96f5168952
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4294300448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.4294300448
Directory	/workspace/19.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3700931531
Short name	T112
Test name
Test status
Simulation time	3826513798 ps
CPU time	633.77 seconds
Started	Apr 23 04:27:59 PM PDT 24
Finished	Apr 23 04:38:33 PM PDT 24
Peak memory	607444 kb
Host	smart-1c31a776-df17-408d-859f-e131c952640c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3700931531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3700931531
Directory	/workspace/19.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_jtag_mem_access.3101742441
Short name	T406
Test name
Test status
Simulation time	13555249908 ps
CPU time	1490.74 seconds
Started	Apr 23 04:16:36 PM PDT 24
Finished	Apr 23 04:41:27 PM PDT 24
Peak memory	592768 kb
Host	smart-6734f81d-155e-4295-abb3-dc47f222d251
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101742441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.3 101742441
Directory	/workspace/2.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2798238977
Short name	T373
Test name
Test status
Simulation time	4893869512 ps
CPU time	328.37 seconds
Started	Apr 23 04:24:12 PM PDT 24
Finished	Apr 23 04:29:41 PM PDT 24
Peak memory	609476 kb
Host	smart-2392dd4c-681a-453f-885c-15692fad4745
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 798238977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2798238977
Directory	/workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/2.chip_sival_flash_info_access.4145786810
Short name	T1006
Test name
Test status
Simulation time	3136909030 ps
CPU time	250.97 seconds
Started	Apr 23 04:14:14 PM PDT 24
Finished	Apr 23 04:18:25 PM PDT 24
Peak memory	599964 kb
Host	smart-b3086333-89ce-4349-8fb4-b91a580ac120
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4145786810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.4145786810
Directory	/workspace/2.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1924740362
Short name	T340
Test name
Test status
Simulation time	18618788298 ps
CPU time	573.33 seconds
Started	Apr 23 04:20:04 PM PDT 24
Finished	Apr 23 04:29:40 PM PDT 24
Peak memory	607532 kb
Host	smart-df23942c-2dbf-4ccc-b6ac-83c76d23ca4c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1924740362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1924740362
Directory	/workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc.2552951133
Short name	T1047
Test name
Test status
Simulation time	2625591268 ps
CPU time	321.08 seconds
Started	Apr 23 04:23:25 PM PDT 24
Finished	Apr 23 04:28:47 PM PDT 24
Peak memory	600180 kb
Host	smart-dbbc9979-2268-4642-9be2-1246cd9401cc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552951133 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.2552951133
Directory	/workspace/2.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3965796141
Short name	T1019
Test name
Test status
Simulation time	2684781638 ps
CPU time	305.23 seconds
Started	Apr 23 04:20:18 PM PDT 24
Finished	Apr 23 04:25:24 PM PDT 24
Peak memory	599916 kb
Host	smart-261b6c4a-0ce7-44d2-8899-c19b27a87dd2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965 796141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.3965796141
Directory	/workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.4110300964
Short name	T873
Test name
Test status
Simulation time	3438371014 ps
CPU time	214.81 seconds
Started	Apr 23 04:23:26 PM PDT 24
Finished	Apr 23 04:27:01 PM PDT 24
Peak memory	599892 kb
Host	smart-3e54b907-859a-42f5-8431-2f02305cf768
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110300964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.4110300964
Directory	/workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_entropy.611513214
Short name	T849
Test name
Test status
Simulation time	2410425800 ps
CPU time	239.09 seconds
Started	Apr 23 04:22:16 PM PDT 24
Finished	Apr 23 04:26:16 PM PDT 24
Peak memory	599916 kb
Host	smart-eebe8642-43ba-479c-83e9-287ac9de4781
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611513214 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.611513214
Directory	/workspace/2.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_idle.3153354809
Short name	T949
Test name
Test status
Simulation time	2463790748 ps
CPU time	245.3 seconds
Started	Apr 23 04:21:18 PM PDT 24
Finished	Apr 23 04:25:25 PM PDT 24
Peak memory	600192 kb
Host	smart-41977c1f-6dab-4875-a9b8-d21c86ebecdc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153354809 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.3153354809
Directory	/workspace/2.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_masking_off.2480027046
Short name	T1070
Test name
Test status
Simulation time	2612258048 ps
CPU time	348.28 seconds
Started	Apr 23 04:20:25 PM PDT 24
Finished	Apr 23 04:26:14 PM PDT 24
Peak memory	600164 kb
Host	smart-68471123-b50d-4085-9ddd-cecfc4feb4d0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480027046 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2480027046
Directory	/workspace/2.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_smoketest.3617302542
Short name	T985
Test name
Test status
Simulation time	2688143880 ps
CPU time	260.79 seconds
Started	Apr 23 04:28:50 PM PDT 24
Finished	Apr 23 04:33:12 PM PDT 24
Peak memory	599856 kb
Host	smart-b15694e4-4a3a-42cb-89e4-213c3ab0bdab
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617302542 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.3617302542
Directory	/workspace/2.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2440484481
Short name	T938
Test name
Test status
Simulation time	2933401829 ps
CPU time	306.05 seconds
Started	Apr 23 04:20:29 PM PDT 24
Finished	Apr 23 04:25:35 PM PDT 24
Peak memory	600276 kb
Host	smart-559a9608-74ad-49ae-8499-c11cdd49a654
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2440484481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.2440484481
Directory	/workspace/2.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1218370355
Short name	T74
Test name
Test status
Simulation time	5613330992 ps
CPU time	582.48 seconds
Started	Apr 23 04:21:30 PM PDT 24
Finished	Apr 23 04:31:16 PM PDT 24
Peak memory	607492 kb
Host	smart-ea9c265e-b236-4ef9-8e59-1a04795a201e
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1218370355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1218370355
Directory	/workspace/2.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.318869397
Short name	T1089
Test name
Test status
Simulation time	6633084216 ps
CPU time	1513.87 seconds
Started	Apr 23 04:21:02 PM PDT 24
Finished	Apr 23 04:46:16 PM PDT 24
Peak memory	601208 kb
Host	smart-a126117f-0cc9-4713-9a74-16358e71ffc3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=318869397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.318869397
Directory	/workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2911972850
Short name	T1011
Test name
Test status
Simulation time	8752189952 ps
CPU time	1607.63 seconds
Started	Apr 23 04:21:12 PM PDT 24
Finished	Apr 23 04:48:00 PM PDT 24
Peak memory	600176 kb
Host	smart-5b2f570b-821e-4ac6-807e-18eb84f07f04
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911972850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2911972850
Directory	/workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1450289521
Short name	T88
Test name
Test status
Simulation time	10361031556 ps
CPU time	1155.03 seconds
Started	Apr 23 04:21:30 PM PDT 24
Finished	Apr 23 04:40:48 PM PDT 24
Peak memory	601764 kb
Host	smart-30722320-aebe-4d06-a542-d404e9a65348
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450289521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.1450289521
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3229846329
Short name	T282
Test name
Test status
Simulation time	4010191196 ps
CPU time	382.11 seconds
Started	Apr 23 04:20:32 PM PDT 24
Finished	Apr 23 04:26:54 PM PDT 24
Peak memory	599916 kb
Host	smart-ea23b412-1d20-436e-926c-97cf16e463fc
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3229846329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3229846329
Directory	/workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2283725716
Short name	T1197
Test name
Test status
Simulation time	255837968104 ps
CPU time	13896.9 seconds
Started	Apr 23 04:20:38 PM PDT 24
Finished	Apr 23 08:12:17 PM PDT 24
Peak memory	600508 kb
Host	smart-dfe3bfd9-bc07-49d2-ac59-c9d375a81ad8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283725716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2283725716
Directory	/workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_test.1915915524
Short name	T227
Test name
Test status
Simulation time	2915610208 ps
CPU time	360.08 seconds
Started	Apr 23 04:21:57 PM PDT 24
Finished	Apr 23 04:27:58 PM PDT 24
Peak memory	599936 kb
Host	smart-41d58c76-d503-48fb-9b03-8f96f414674f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915915524 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.1915915524
Directory	/workspace/2.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_irq.803010928
Short name	T1184
Test name
Test status
Simulation time	4033784760 ps
CPU time	362.17 seconds
Started	Apr 23 04:20:35 PM PDT 24
Finished	Apr 23 04:26:37 PM PDT 24
Peak memory	599888 kb
Host	smart-0a3f086e-1ebf-4f2d-b0a9-53b8c5b19add
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803010928 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.803010928
Directory	/workspace/2.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2423627848
Short name	T271
Test name
Test status
Simulation time	7380069520 ps
CPU time	452.24 seconds
Started	Apr 23 04:19:05 PM PDT 24
Finished	Apr 23 04:26:38 PM PDT 24
Peak memory	600496 kb
Host	smart-ca73d473-4ff4-4117-b1db-421d5b6747f7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2423627848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2423627848
Directory	/workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1034378530
Short name	T1081
Test name
Test status
Simulation time	2569086092 ps
CPU time	258.79 seconds
Started	Apr 23 04:26:15 PM PDT 24
Finished	Apr 23 04:30:34 PM PDT 24
Peak memory	600152 kb
Host	smart-e54ca5f5-98c5-4f27-abfe-683826cda452
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034378530 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.1034378530
Directory	/workspace/2.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3427530597
Short name	T382
Test name
Test status
Simulation time	9371360104 ps
CPU time	1007.85 seconds
Started	Apr 23 04:19:40 PM PDT 24
Finished	Apr 23 04:36:28 PM PDT 24
Peak memory	600432 kb
Host	smart-1f56a8e0-b577-47c4-a1a4-38263c408c11
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3427530597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.3427530597
Directory	/workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2403363485
Short name	T1124
Test name
Test status
Simulation time	5925697440 ps
CPU time	566.83 seconds
Started	Apr 23 04:20:40 PM PDT 24
Finished	Apr 23 04:30:07 PM PDT 24
Peak memory	600420 kb
Host	smart-7442a14c-1da2-44ca-9415-0332b3947d74
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2403363485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.2403363485
Directory	/workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.479111225
Short name	T1058
Test name
Test status
Simulation time	7363767100 ps
CPU time	911.93 seconds
Started	Apr 23 04:23:44 PM PDT 24
Finished	Apr 23 04:38:57 PM PDT 24
Peak memory	606544 kb
Host	smart-2f30290b-3307-4d6d-a2ac-622ab73ae106
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479111225 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.479111225
Directory	/workspace/2.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3406050235
Short name	T68
Test name
Test status
Simulation time	5334775712 ps
CPU time	404.38 seconds
Started	Apr 23 04:23:05 PM PDT 24
Finished	Apr 23 04:29:51 PM PDT 24
Peak memory	612648 kb
Host	smart-46ca6b6c-ea42-4b66-a802-d2ea94eb87c2
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3406050235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.3406050235
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.444124949
Short name	T1101
Test name
Test status
Simulation time	4203779820 ps
CPU time	650.79 seconds
Started	Apr 23 04:24:21 PM PDT 24
Finished	Apr 23 04:35:12 PM PDT 24
Peak memory	604284 kb
Host	smart-67b0e82d-4dac-40ee-b653-e1fc14f7d907
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444124949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.444124949
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2831850945
Short name	T1171
Test name
Test status
Simulation time	4211941088 ps
CPU time	644.2 seconds
Started	Apr 23 04:24:29 PM PDT 24
Finished	Apr 23 04:35:14 PM PDT 24
Peak memory	604264 kb
Host	smart-0bb32de8-d090-445b-906c-b76c3c725ba6
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831850945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2831850945
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4212994122
Short name	T1183
Test name
Test status
Simulation time	4284724976 ps
CPU time	752.22 seconds
Started	Apr 23 04:23:20 PM PDT 24
Finished	Apr 23 04:35:53 PM PDT 24
Peak memory	604252 kb
Host	smart-8b27cc00-acd1-4738-872f-155bc4b455bb
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212994122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4212994122
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3073324528
Short name	T1116
Test name
Test status
Simulation time	5143616180 ps
CPU time	684.03 seconds
Started	Apr 23 04:25:00 PM PDT 24
Finished	Apr 23 04:36:25 PM PDT 24
Peak memory	604232 kb
Host	smart-4770d7aa-06ce-4471-b46f-e7ba8ce77685
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073324528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3073324528
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3125064395
Short name	T1170
Test name
Test status
Simulation time	5275287968 ps
CPU time	548.4 seconds
Started	Apr 23 04:23:09 PM PDT 24
Finished	Apr 23 04:32:18 PM PDT 24
Peak memory	604320 kb
Host	smart-bf331187-59e6-46c2-b6a4-5911211cc732
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125064395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3125064395
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2742480712
Short name	T1022
Test name
Test status
Simulation time	5042967390 ps
CPU time	584.52 seconds
Started	Apr 23 04:24:40 PM PDT 24
Finished	Apr 23 04:34:26 PM PDT 24
Peak memory	604244 kb
Host	smart-ca33986f-fd9c-4738-a77a-a47f35ebd943
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742480712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2742480712
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3220818551
Short name	T906
Test name
Test status
Simulation time	2636020348 ps
CPU time	277.18 seconds
Started	Apr 23 04:23:06 PM PDT 24
Finished	Apr 23 04:27:44 PM PDT 24
Peak memory	600184 kb
Host	smart-35d87462-2f38-4d4c-b3d8-4019370a7f3d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220818551 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.3220818551
Directory	/workspace/2.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2398903438
Short name	T383
Test name
Test status
Simulation time	3367042580 ps
CPU time	396.07 seconds
Started	Apr 23 04:24:29 PM PDT 24
Finished	Apr 23 04:31:06 PM PDT 24
Peak memory	599944 kb
Host	smart-d73244ec-3c92-4811-9d0b-aac221c1ac6d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398903438 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.2398903438
Directory	/workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4148751039
Short name	T967
Test name
Test status
Simulation time	2233238739 ps
CPU time	181.72 seconds
Started	Apr 23 04:24:52 PM PDT 24
Finished	Apr 23 04:27:55 PM PDT 24
Peak memory	599944 kb
Host	smart-0cfa88c2-9a3f-4fdd-9e52-08cabaa69d9b
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148751039 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.4148751039
Directory	/workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.373149996
Short name	T1099
Test name
Test status
Simulation time	4506545260 ps
CPU time	548.31 seconds
Started	Apr 23 04:23:41 PM PDT 24
Finished	Apr 23 04:32:50 PM PDT 24
Peak memory	600292 kb
Host	smart-335c2073-0ce3-4146-bb50-15764801c152
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373149996 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.373149996
Directory	/workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2356594841
Short name	T1135
Test name
Test status
Simulation time	4630852472 ps
CPU time	555.59 seconds
Started	Apr 23 04:23:48 PM PDT 24
Finished	Apr 23 04:33:04 PM PDT 24
Peak memory	600168 kb
Host	smart-58f6e428-aa64-4aad-bc35-612c87720285
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356594841 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2356594841
Directory	/workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2518789960
Short name	T908
Test name
Test status
Simulation time	5296239400 ps
CPU time	448.72 seconds
Started	Apr 23 04:24:19 PM PDT 24
Finished	Apr 23 04:31:48 PM PDT 24
Peak memory	600388 kb
Host	smart-407a7ef9-1335-4f2d-a9c1-afdb83802dd9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518789960 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.2518789960
Directory	/workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.949965196
Short name	T225
Test name
Test status
Simulation time	4696851910 ps
CPU time	446.25 seconds
Started	Apr 23 04:24:16 PM PDT 24
Finished	Apr 23 04:31:43 PM PDT 24
Peak memory	600316 kb
Host	smart-3f033161-0a43-4000-9f3b-9759b310ae93
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949965196 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.949965196
Directory	/workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.876900330
Short name	T895
Test name
Test status
Simulation time	11564752828 ps
CPU time	1600.2 seconds
Started	Apr 23 04:27:55 PM PDT 24
Finished	Apr 23 04:54:35 PM PDT 24
Peak memory	601388 kb
Host	smart-ca0f3e74-cf68-4d3b-a7e9-441e30d0ffcf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876900330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.876900330
Directory	/workspace/2.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2171156634
Short name	T1123
Test name
Test status
Simulation time	4041326564 ps
CPU time	435.72 seconds
Started	Apr 23 04:24:07 PM PDT 24
Finished	Apr 23 04:31:24 PM PDT 24
Peak memory	599920 kb
Host	smart-b8c01e44-0ce4-4698-9203-84b659de43f1
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171156634 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2171156634
Directory	/workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.4077130894
Short name	T970
Test name
Test status
Simulation time	4568436216 ps
CPU time	814.06 seconds
Started	Apr 23 04:23:56 PM PDT 24
Finished	Apr 23 04:37:32 PM PDT 24
Peak memory	600276 kb
Host	smart-ed4355d8-9165-4cc3-ae23-a271be0afb9d
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077130894 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.4077130894
Directory	/workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3947261551
Short name	T98
Test name
Test status
Simulation time	2794017850 ps
CPU time	177.16 seconds
Started	Apr 23 04:25:19 PM PDT 24
Finished	Apr 23 04:28:16 PM PDT 24
Peak memory	599900 kb
Host	smart-afbcc408-ef3d-4c8b-afc1-c4e8ecbd459c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947261551 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.3947261551
Directory	/workspace/2.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1843705324
Short name	T1187
Test name
Test status
Simulation time	13579353952 ps
CPU time	3172.09 seconds
Started	Apr 23 04:21:40 PM PDT 24
Finished	Apr 23 05:14:33 PM PDT 24
Peak memory	600328 kb
Host	smart-8fa942df-b9fd-4ad5-90c2-c001208068d2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843705324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1843705324
Directory	/workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1773619234
Short name	T118
Test name
Test status
Simulation time	20299325930 ps
CPU time	3637.66 seconds
Started	Apr 23 04:25:23 PM PDT 24
Finished	Apr 23 05:26:02 PM PDT 24
Peak memory	600320 kb
Host	smart-e6e9330d-812a-47df-9b9d-bb6ee7594382
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773619234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _csrng_edn_concurrency_reduced_freq.1773619234
Directory	/workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2284966254
Short name	T187
Test name
Test status
Simulation time	5576922596 ps
CPU time	766.45 seconds
Started	Apr 23 04:22:22 PM PDT 24
Finished	Apr 23 04:35:09 PM PDT 24
Peak memory	600696 kb
Host	smart-1294c7a6-2cff-4e00-85df-5fe7bf867150
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22849 66254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.2284966254
Directory	/workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_kat_test.2409937307
Short name	T929
Test name
Test status
Simulation time	2809195880 ps
CPU time	276.72 seconds
Started	Apr 23 04:21:47 PM PDT 24
Finished	Apr 23 04:26:25 PM PDT 24
Peak memory	599856 kb
Host	smart-e969485d-4856-4e75-a811-5e3c4be1f11b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409937307 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.2409937307
Directory	/workspace/2.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3001857436
Short name	T1048
Test name
Test status
Simulation time	5869350070 ps
CPU time	669.89 seconds
Started	Apr 23 04:21:06 PM PDT 24
Finished	Apr 23 04:32:16 PM PDT 24
Peak memory	600780 kb
Host	smart-fbda87b1-5602-4dab-a6aa-24c094390a18
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001857436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.3001857436
Directory	/workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_smoketest.1311379321
Short name	T853
Test name
Test status
Simulation time	2340729424 ps
CPU time	201.55 seconds
Started	Apr 23 04:26:54 PM PDT 24
Finished	Apr 23 04:30:16 PM PDT 24
Peak memory	599832 kb
Host	smart-efe62b32-0ee6-47f3-8bc0-a072f35fb63b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311379321 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.1311379321
Directory	/workspace/2.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.208748113
Short name	T261
Test name
Test status
Simulation time	5680318468 ps
CPU time	602.75 seconds
Started	Apr 23 04:14:03 PM PDT 24
Finished	Apr 23 04:24:07 PM PDT 24
Peak memory	600760 kb
Host	smart-a5aadbc2-7028-49f9-95a8-5f2cf7033398
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=208748113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.208748113
Directory	/workspace/2.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_auto_mode.2433364696
Short name	T130
Test name
Test status
Simulation time	4787700530 ps
CPU time	1003.14 seconds
Started	Apr 23 04:21:17 PM PDT 24
Finished	Apr 23 04:38:01 PM PDT 24
Peak memory	600448 kb
Host	smart-4288bc5a-3699-471d-ab57-3a2efcddfb43
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433364696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.2433364696
Directory	/workspace/2.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_boot_mode.4292600418
Short name	T238
Test name
Test status
Simulation time	3071300200 ps
CPU time	539.4 seconds
Started	Apr 23 04:22:15 PM PDT 24
Finished	Apr 23 04:31:14 PM PDT 24
Peak memory	600012 kb
Host	smart-b1d6bc68-ddfb-4f88-a86d-0bc4514c6981
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292600418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.4292600418
Directory	/workspace/2.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.486039108
Short name	T220
Test name
Test status
Simulation time	5935586320 ps
CPU time	1234.76 seconds
Started	Apr 23 04:21:40 PM PDT 24
Finished	Apr 23 04:42:16 PM PDT 24
Peak memory	600416 kb
Host	smart-92d70a2a-104e-4918-8daf-d20d5cc5594c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=486039108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.486039108
Directory	/workspace/2.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2191515523
Short name	T1052
Test name
Test status
Simulation time	5517778829 ps
CPU time	1167.46 seconds
Started	Apr 23 04:22:05 PM PDT 24
Finished	Apr 23 04:41:33 PM PDT 24
Peak memory	600348 kb
Host	smart-9b1c9cc6-dfcc-4d92-a213-af953a894899
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191515523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2191515523
Directory	/workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_kat.1509037601
Short name	T1012
Test name
Test status
Simulation time	3165234160 ps
CPU time	616.64 seconds
Started	Apr 23 04:21:44 PM PDT 24
Finished	Apr 23 04:32:02 PM PDT 24
Peak memory	606132 kb
Host	smart-1fb47fea-2cff-4897-bffb-54cb86517fe9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509037601 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.1509037601
Directory	/workspace/2.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_sw_mode.3605426984
Short name	T903
Test name
Test status
Simulation time	5617900106 ps
CPU time	1022.77 seconds
Started	Apr 23 04:21:15 PM PDT 24
Finished	Apr 23 04:38:19 PM PDT 24
Peak memory	600172 kb
Host	smart-ca3280b9-8f95-4873-bd4c-bc916d3930fe
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605426984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.3605426984
Directory	/workspace/2.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2725261009
Short name	T833
Test name
Test status
Simulation time	3081465208 ps
CPU time	209.46 seconds
Started	Apr 23 04:21:58 PM PDT 24
Finished	Apr 23 04:25:28 PM PDT 24
Peak memory	599928 kb
Host	smart-eb717f3f-4c89-422a-9f2f-77790324763b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27 25261009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2725261009
Directory	/workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2471860222
Short name	T310
Test name
Test status
Simulation time	5642446510 ps
CPU time	1368.06 seconds
Started	Apr 23 04:22:53 PM PDT 24
Finished	Apr 23 04:45:42 PM PDT 24
Peak memory	600328 kb
Host	smart-f2fa3195-ea1e-4990-80de-b616695fbfae
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2471860222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2471860222
Directory	/workspace/2.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2268268957
Short name	T944
Test name
Test status
Simulation time	2631385076 ps
CPU time	202.55 seconds
Started	Apr 23 04:21:39 PM PDT 24
Finished	Apr 23 04:25:02 PM PDT 24
Peak memory	599952 kb
Host	smart-ac056765-77ba-4694-8fad-e72f870d38b9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268268957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2268268957
Directory	/workspace/2.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1114246939
Short name	T1215
Test name
Test status
Simulation time	3213473916 ps
CPU time	504.58 seconds
Started	Apr 23 04:27:19 PM PDT 24
Finished	Apr 23 04:35:44 PM PDT 24
Peak memory	600196 kb
Host	smart-e77a1f68-df8c-402a-8445-9ad59715bc31
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1114246939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.1114246939
Directory	/workspace/2.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_example_concurrency.4050390138
Short name	T1177
Test name
Test status
Simulation time	2581028798 ps
CPU time	197.02 seconds
Started	Apr 23 04:19:40 PM PDT 24
Finished	Apr 23 04:22:57 PM PDT 24
Peak memory	600144 kb
Host	smart-2dfcb959-f50f-40b5-86ab-a75fc660dd53
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050390138 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.4050390138
Directory	/workspace/2.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/2.chip_sw_example_flash.3001973825
Short name	T1190
Test name
Test status
Simulation time	3229841024 ps
CPU time	167.85 seconds
Started	Apr 23 04:14:40 PM PDT 24
Finished	Apr 23 04:17:28 PM PDT 24
Peak memory	600124 kb
Host	smart-ff8b83e2-8399-46c5-81b9-86fa39b36fce
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001973825 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.3001973825
Directory	/workspace/2.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/2.chip_sw_example_manufacturer.2391946405
Short name	T898
Test name
Test status
Simulation time	2674709772 ps
CPU time	156.62 seconds
Started	Apr 23 04:14:43 PM PDT 24
Finished	Apr 23 04:17:20 PM PDT 24
Peak memory	599876 kb
Host	smart-e9bab58a-6031-40bd-aa11-1a4b16a97312
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391946405 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2391946405
Directory	/workspace/2.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/2.chip_sw_example_rom.2108196132
Short name	T963
Test name
Test status
Simulation time	2272943580 ps
CPU time	117.68 seconds
Started	Apr 23 04:13:55 PM PDT 24
Finished	Apr 23 04:15:53 PM PDT 24
Peak memory	599812 kb
Host	smart-dacc3eca-ccaa-4272-bc4a-3adc5ca5026d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108196132 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.2108196132
Directory	/workspace/2.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.4219168
Short name	T157
Test name
Test status
Simulation time	59854164200 ps
CPU time	11529.4 seconds
Started	Apr 23 04:15:38 PM PDT 24
Finished	Apr 23 07:27:49 PM PDT 24
Peak memory	615848 kb
Host	smart-6ffbc03b-dab0-4b92-9409-87b77045a3a5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=4219168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.4219168
Directory	/workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_crash_alert.3989132742
Short name	T1140
Test name
Test status
Simulation time	3857103272 ps
CPU time	551.07 seconds
Started	Apr 23 04:24:31 PM PDT 24
Finished	Apr 23 04:33:42 PM PDT 24
Peak memory	600904 kb
Host	smart-3cc9882c-1c8f-41a9-91aa-3e8c9489e206
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3989132742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.3989132742
Directory	/workspace/2.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.3330867095
Short name	T1146
Test name
Test status
Simulation time	6047420122 ps
CPU time	1133.73 seconds
Started	Apr 23 04:15:22 PM PDT 24
Finished	Apr 23 04:34:17 PM PDT 24
Peak memory	600204 kb
Host	smart-0f5da8de-9865-4586-a145-8e20f02902d6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330867095 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.3330867095
Directory	/workspace/2.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2991287527
Short name	T897
Test name
Test status
Simulation time	6616567357 ps
CPU time	1078.38 seconds
Started	Apr 23 04:15:16 PM PDT 24
Finished	Apr 23 04:33:15 PM PDT 24
Peak memory	600220 kb
Host	smart-13d344b8-50ff-4e24-83d0-9e50be32735c
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991287527 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2991287527
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4035786339
Short name	T91
Test name
Test status
Simulation time	7140586931 ps
CPU time	1048.38 seconds
Started	Apr 23 04:25:03 PM PDT 24
Finished	Apr 23 04:42:34 PM PDT 24
Peak memory	600172 kb
Host	smart-55fcfec0-9cef-4de8-8d2b-5a3d245cf8f0
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035786339 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4035786339
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3121717947
Short name	T909
Test name
Test status
Simulation time	4796146006 ps
CPU time	1163.12 seconds
Started	Apr 23 04:15:59 PM PDT 24
Finished	Apr 23 04:35:22 PM PDT 24
Peak memory	600272 kb
Host	smart-e716288c-9440-4eb1-ac49-79fb9c10dc81
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121717947 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.3121717947
Directory	/workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3987480989
Short name	T1175
Test name
Test status
Simulation time	3214334550 ps
CPU time	382.45 seconds
Started	Apr 23 04:18:18 PM PDT 24
Finished	Apr 23 04:24:41 PM PDT 24
Peak memory	600252 kb
Host	smart-66e5ab50-3baf-4258-934e-b4c6949dfe8d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987480989 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.3987480989
Directory	/workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.974325576
Short name	T218
Test name
Test status
Simulation time	3643591243 ps
CPU time	345.73 seconds
Started	Apr 23 04:15:06 PM PDT 24
Finished	Apr 23 04:20:53 PM PDT 24
Peak memory	600224 kb
Host	smart-0e14707f-3af8-4a1f-b716-80ef47ac18ed
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97 4325576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.974325576
Directory	/workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2733555260
Short name	T943
Test name
Test status
Simulation time	5258974708 ps
CPU time	792.75 seconds
Started	Apr 23 04:24:40 PM PDT 24
Finished	Apr 23 04:37:53 PM PDT 24
Peak memory	600144 kb
Host	smart-06193b4c-c580-4854-a383-fd3baab15947
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733555260 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.2733555260
Directory	/workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3326360944
Short name	T302
Test name
Test status
Simulation time	4167736038 ps
CPU time	532.02 seconds
Started	Apr 23 04:15:16 PM PDT 24
Finished	Apr 23 04:24:09 PM PDT 24
Peak memory	599992 kb
Host	smart-7bc4286d-0de7-429b-949e-2c17267f9c6d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326360944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.3326360944
Directory	/workspace/2.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.203482920
Short name	T305
Test name
Test status
Simulation time	3558233899 ps
CPU time	576.13 seconds
Started	Apr 23 04:15:48 PM PDT 24
Finished	Apr 23 04:25:25 PM PDT 24
Peak memory	600060 kb
Host	smart-588e8649-4c49-40f5-ace4-bdfd4c1b4ae9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=203482920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.203482920
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1221855575
Short name	T301
Test name
Test status
Simulation time	4244619816 ps
CPU time	662.13 seconds
Started	Apr 23 04:25:35 PM PDT 24
Finished	Apr 23 04:36:38 PM PDT 24
Peak memory	600228 kb
Host	smart-3af91243-b01a-41fc-9c32-b190d11536bf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1221855575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1221855575
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_init.29238027
Short name	T213
Test name
Test status
Simulation time	24005348035 ps
CPU time	2178.1 seconds
Started	Apr 23 04:16:09 PM PDT 24
Finished	Apr 23 04:52:28 PM PDT 24
Peak memory	605292 kb
Host	smart-22cd2cbb-98ab-4b01-973b-a784ac4f440e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29238027 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.29238027
Directory	/workspace/2.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.4127539529
Short name	T1174
Test name
Test status
Simulation time	23792619329 ps
CPU time	1759.16 seconds
Started	Apr 23 04:24:08 PM PDT 24
Finished	Apr 23 04:53:29 PM PDT 24
Peak memory	604600 kb
Host	smart-c661a058-225d-4ecc-b048-38ddb13b0f5c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4127539529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.4127539529
Directory	/workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.563710052
Short name	T1075
Test name
Test status
Simulation time	2552868910 ps
CPU time	271.67 seconds
Started	Apr 23 04:30:18 PM PDT 24
Finished	Apr 23 04:34:50 PM PDT 24
Peak memory	599932 kb
Host	smart-a735000a-0cfd-49a6-ac23-d51399131c02
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=563710052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.563710052
Directory	/workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_gpio_smoketest.208112803
Short name	T25
Test name
Test status
Simulation time	3274423864 ps
CPU time	331.41 seconds
Started	Apr 23 04:26:47 PM PDT 24
Finished	Apr 23 04:32:20 PM PDT 24
Peak memory	600248 kb
Host	smart-0bc42b4a-b8be-46bb-8b7b-a45828c40ae5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208112803 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_gpio_smoketest.208112803
Directory	/workspace/2.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc.3088393319
Short name	T304
Test name
Test status
Simulation time	3442699854 ps
CPU time	266.86 seconds
Started	Apr 23 04:21:23 PM PDT 24
Finished	Apr 23 04:25:50 PM PDT 24
Peak memory	600204 kb
Host	smart-d1382c4b-2923-4154-9e56-92feea33b4b2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088393319 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.3088393319
Directory	/workspace/2.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2271014548
Short name	T108
Test name
Test status
Simulation time	2947772058 ps
CPU time	360.07 seconds
Started	Apr 23 04:23:25 PM PDT 24
Finished	Apr 23 04:29:26 PM PDT 24
Peak memory	599916 kb
Host	smart-d56cd619-b500-4431-85c1-4ec7e8ab2f98
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271014548 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.2271014548
Directory	/workspace/2.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3177524849
Short name	T345
Test name
Test status
Simulation time	2584781635 ps
CPU time	302.52 seconds
Started	Apr 23 04:21:52 PM PDT 24
Finished	Apr 23 04:26:55 PM PDT 24
Peak memory	599900 kb
Host	smart-d77d94a3-5323-4d4b-97c2-b08e90c4fad9
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177524849 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.3177524849
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1465178897
Short name	T869
Test name
Test status
Simulation time	3058116742 ps
CPU time	276.29 seconds
Started	Apr 23 04:25:28 PM PDT 24
Finished	Apr 23 04:30:05 PM PDT 24
Peak memory	600196 kb
Host	smart-b76f55c1-f777-4fd8-823a-937996c8cdd8
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465178897 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.1465178897
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_smoketest.2663524636
Short name	T1134
Test name
Test status
Simulation time	3773341598 ps
CPU time	320.08 seconds
Started	Apr 23 04:27:09 PM PDT 24
Finished	Apr 23 04:32:29 PM PDT 24
Peak memory	599904 kb
Host	smart-d1cbca20-67f8-4ab1-8715-a397b939bc3a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663524636 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2663524636
Directory	/workspace/2.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1111840784
Short name	T198
Test name
Test status
Simulation time	3815353764 ps
CPU time	558.73 seconds
Started	Apr 23 04:15:27 PM PDT 24
Finished	Apr 23 04:24:47 PM PDT 24
Peak memory	600636 kb
Host	smart-b201ed42-4197-410d-a283-989fd9420df6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111840784 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1111840784
Directory	/workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3427774895
Short name	T1205
Test name
Test status
Simulation time	5547887720 ps
CPU time	1023.84 seconds
Started	Apr 23 04:17:17 PM PDT 24
Finished	Apr 23 04:34:22 PM PDT 24
Peak memory	600308 kb
Host	smart-202683c5-6441-4e72-8794-dc5fea5623c1
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427774895 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.3427774895
Directory	/workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.4203886527
Short name	T314
Test name
Test status
Simulation time	4969458040 ps
CPU time	823.12 seconds
Started	Apr 23 04:15:30 PM PDT 24
Finished	Apr 23 04:29:14 PM PDT 24
Peak memory	600296 kb
Host	smart-98af621c-dd4a-4e85-a667-eb84d920c5a2
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203886527 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.4203886527
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4029130293
Short name	T327
Test name
Test status
Simulation time	5129881612 ps
CPU time	753.09 seconds
Started	Apr 23 04:16:26 PM PDT 24
Finished	Apr 23 04:29:00 PM PDT 24
Peak memory	600188 kb
Host	smart-bc4c4b81-399b-4a32-bfd1-766376d49af5
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029130293 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.4029130293
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1870582776
Short name	T199
Test name
Test status
Simulation time	63472397162 ps
CPU time	12118 seconds
Started	Apr 23 04:15:14 PM PDT 24
Finished	Apr 23 07:37:14 PM PDT 24
Peak memory	615804 kb
Host	smart-655eca45-5918-44a7-8b67-fc6e9292b701
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1870582776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.1870582776
Directory	/workspace/2.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2210991706
Short name	T861
Test name
Test status
Simulation time	3964486360 ps
CPU time	447.98 seconds
Started	Apr 23 04:21:52 PM PDT 24
Finished	Apr 23 04:29:21 PM PDT 24
Peak memory	607596 kb
Host	smart-06e3685b-5c8a-436d-b6ab-2bc757109961
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210 991706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2210991706
Directory	/workspace/2.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2063723704
Short name	T1149
Test name
Test status
Simulation time	4099372843 ps
CPU time	382.81 seconds
Started	Apr 23 04:21:50 PM PDT 24
Finished	Apr 23 04:28:13 PM PDT 24
Peak memory	607508 kb
Host	smart-9c32ca91-df8c-423e-8a3d-659fa53f7e49
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2063723704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2063723704
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3177475273
Short name	T1162
Test name
Test status
Simulation time	5117796406 ps
CPU time	481.75 seconds
Started	Apr 23 04:24:51 PM PDT 24
Finished	Apr 23 04:32:53 PM PDT 24
Peak memory	607564 kb
Host	smart-beebcefe-1f96-46ee-8478-e6104dc87115
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3177475273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3177475273
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.946607461
Short name	T107
Test name
Test status
Simulation time	4468339168 ps
CPU time	515.61 seconds
Started	Apr 23 04:22:41 PM PDT 24
Finished	Apr 23 04:31:18 PM PDT 24
Peak memory	607596 kb
Host	smart-59c1a6bf-19a0-45d0-b5d7-24a65ca0bb7d
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=946607461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.946607461
Directory	/workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2043840843
Short name	T1050
Test name
Test status
Simulation time	4646954130 ps
CPU time	586.37 seconds
Started	Apr 23 04:23:27 PM PDT 24
Finished	Apr 23 04:33:14 PM PDT 24
Peak memory	600968 kb
Host	smart-feb4d655-8aa1-49ca-a641-36d31a0b869d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20438 40843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.2043840843
Directory	/workspace/2.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2795397144
Short name	T210
Test name
Test status
Simulation time	13045968388 ps
CPU time	3538.67 seconds
Started	Apr 23 04:23:26 PM PDT 24
Finished	Apr 23 05:22:26 PM PDT 24
Peak memory	600628 kb
Host	smart-f41d99d7-cc83-4957-a54f-1fd5d9dd9f0e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27953 97144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2795397144
Directory	/workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_app_rom.3793827775
Short name	T90
Test name
Test status
Simulation time	3297093672 ps
CPU time	273.56 seconds
Started	Apr 23 04:22:39 PM PDT 24
Finished	Apr 23 04:27:14 PM PDT 24
Peak memory	599908 kb
Host	smart-7bb3d240-5c97-4756-9d39-c5f8acf69eca
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793827775 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.3793827775
Directory	/workspace/2.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_entropy.1504776438
Short name	T1122
Test name
Test status
Simulation time	2795191708 ps
CPU time	183.69 seconds
Started	Apr 23 04:16:59 PM PDT 24
Finished	Apr 23 04:20:03 PM PDT 24
Peak memory	600152 kb
Host	smart-ad43ba4d-9f87-48ed-97e2-65f2ee6efe29
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504776438 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.1504776438
Directory	/workspace/2.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_idle.1131362188
Short name	T1049
Test name
Test status
Simulation time	3300218546 ps
CPU time	213.78 seconds
Started	Apr 23 04:23:16 PM PDT 24
Finished	Apr 23 04:26:50 PM PDT 24
Peak memory	600192 kb
Host	smart-c53a8ae6-2994-4c64-8005-1d771d1d4b69
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131362188 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1131362188
Directory	/workspace/2.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2102391992
Short name	T1009
Test name
Test status
Simulation time	2247483000 ps
CPU time	237.92 seconds
Started	Apr 23 04:22:39 PM PDT 24
Finished	Apr 23 04:26:37 PM PDT 24
Peak memory	599916 kb
Host	smart-7bd82df0-c631-4b1a-aa5f-7436e9cd04b5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102391992 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.2102391992
Directory	/workspace/2.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1858035433
Short name	T1150
Test name
Test status
Simulation time	2600772504 ps
CPU time	226.19 seconds
Started	Apr 23 04:22:16 PM PDT 24
Finished	Apr 23 04:26:02 PM PDT 24
Peak memory	599924 kb
Host	smart-1cb80703-70f8-44e3-be92-f6745682ebd7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858035433 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.1858035433
Directory	/workspace/2.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.708698833
Short name	T879
Test name
Test status
Simulation time	2976095182 ps
CPU time	274.28 seconds
Started	Apr 23 04:22:27 PM PDT 24
Finished	Apr 23 04:27:02 PM PDT 24
Peak memory	599924 kb
Host	smart-d0f7fc53-eefb-4478-99a4-740604a50410
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708698833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.708698833
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.107267808
Short name	T292
Test name
Test status
Simulation time	3589459525 ps
CPU time	317.33 seconds
Started	Apr 23 04:24:39 PM PDT 24
Finished	Apr 23 04:29:57 PM PDT 24
Peak memory	600180 kb
Host	smart-e20abe5a-914a-484c-bc38-97e2385aef7a
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10726780 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.107267808
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_smoketest.684808102
Short name	T412
Test name
Test status
Simulation time	3310880434 ps
CPU time	291.37 seconds
Started	Apr 23 04:25:41 PM PDT 24
Finished	Apr 23 04:30:33 PM PDT 24
Peak memory	600172 kb
Host	smart-9b23ea14-2f16-4112-bfbf-5512c3c69c88
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684808102 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_smoketest.684808102
Directory	/workspace/2.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2230471218
Short name	T1209
Test name
Test status
Simulation time	2400153560 ps
CPU time	279.7 seconds
Started	Apr 23 04:17:04 PM PDT 24
Finished	Apr 23 04:21:44 PM PDT 24
Peak memory	600172 kb
Host	smart-d6edaffc-590e-4da1-9c57-6d8d7b488828
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230471218 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.2230471218
Directory	/workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.135684549
Short name	T1042
Test name
Test status
Simulation time	10320510818 ps
CPU time	781.9 seconds
Started	Apr 23 04:16:07 PM PDT 24
Finished	Apr 23 04:29:09 PM PDT 24
Peak memory	612628 kb
Host	smart-d6d1b548-d8fd-4f74-a953-64d3f57e2235
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135684549 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.135684549
Directory	/workspace/2.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1862264853
Short name	T248
Test name
Test status
Simulation time	2789408038 ps
CPU time	92.93 seconds
Started	Apr 23 04:17:03 PM PDT 24
Finished	Apr 23 04:18:37 PM PDT 24
Peak memory	606980 kb
Host	smart-20033792-a7c7-47f0-9f09-6ab44d5d51d3
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1862264853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1862264853
Directory	/workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3215918743
Short name	T1023
Test name
Test status
Simulation time	2715561616 ps
CPU time	118.53 seconds
Started	Apr 23 04:19:17 PM PDT 24
Finished	Apr 23 04:21:16 PM PDT 24
Peak memory	606900 kb
Host	smart-568790a3-b858-4550-a06b-4e8e926d36b3
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215918743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3215918743
Directory	/workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2613301584
Short name	T216
Test name
Test status
Simulation time	48174490539 ps
CPU time	4925.68 seconds
Started	Apr 23 04:17:23 PM PDT 24
Finished	Apr 23 05:39:30 PM PDT 24
Peak memory	607684 kb
Host	smart-d2372df5-de3f-4818-9ea2-7499db7597ce
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613301584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.2613301584
Directory	/workspace/2.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1984043045
Short name	T358
Test name
Test status
Simulation time	9913462088 ps
CPU time	879.09 seconds
Started	Apr 23 04:17:03 PM PDT 24
Finished	Apr 23 04:31:43 PM PDT 24
Peak memory	608584 kb
Host	smart-4c9dc8b2-a08e-413e-9ee2-4b92ab77fd7c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984043045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1984043045
Directory	/workspace/2.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2615989336
Short name	T1115
Test name
Test status
Simulation time	45630678345 ps
CPU time	5823.44 seconds
Started	Apr 23 04:20:04 PM PDT 24
Finished	Apr 23 05:57:09 PM PDT 24
Peak memory	608636 kb
Host	smart-1cca1606-a41b-47c2-ada6-b48618e557b4
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615989336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.2615989336
Directory	/workspace/2.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3111769093
Short name	T171
Test name
Test status
Simulation time	28419468174 ps
CPU time	2517.23 seconds
Started	Apr 23 04:16:53 PM PDT 24
Finished	Apr 23 04:58:51 PM PDT 24
Peak memory	608636 kb
Host	smart-cce3f0ed-eb3a-4fa2-921c-6a6016cfa096
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3111769093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.3111769093
Directory	/workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3376418002
Short name	T133
Test name
Test status
Simulation time	16972640112 ps
CPU time	3447.1 seconds
Started	Apr 23 04:22:35 PM PDT 24
Finished	Apr 23 05:20:04 PM PDT 24
Peak memory	600376 kb
Host	smart-2754da9b-7f84-4c41-9834-1a61969d4410
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3376418002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3376418002
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.924524212
Short name	T120
Test name
Test status
Simulation time	18853953215 ps
CPU time	3294.43 seconds
Started	Apr 23 04:19:40 PM PDT 24
Finished	Apr 23 05:14:35 PM PDT 24
Peak memory	600332 kb
Host	smart-760ea166-97d2-42ff-813b-662f7aa1bcbb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=924524212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.924524212
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3445788473
Short name	T611
Test name
Test status
Simulation time	24814205404 ps
CPU time	3352.53 seconds
Started	Apr 23 04:23:56 PM PDT 24
Finished	Apr 23 05:19:50 PM PDT 24
Peak memory	600288 kb
Host	smart-a90e6434-fcf5-407b-9c37-1ffcdabc10ee
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445788473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3445788473
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3194142357
Short name	T262
Test name
Test status
Simulation time	3549693304 ps
CPU time	498.12 seconds
Started	Apr 23 04:20:04 PM PDT 24
Finished	Apr 23 04:28:22 PM PDT 24
Peak memory	600188 kb
Host	smart-90c89195-7151-42d2-9c17-86ecf4904cc8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194142357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.3194142357
Directory	/workspace/2.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_randomness.498023932
Short name	T955
Test name
Test status
Simulation time	5517406700 ps
CPU time	866.1 seconds
Started	Apr 23 04:19:06 PM PDT 24
Finished	Apr 23 04:33:33 PM PDT 24
Peak memory	600316 kb
Host	smart-db2b2fea-aa80-4fd6-b88f-2178c41e1ae4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=498023932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.498023932
Directory	/workspace/2.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_smoketest.909429153
Short name	T155
Test name
Test status
Simulation time	10792673532 ps
CPU time	2580.86 seconds
Started	Apr 23 04:29:01 PM PDT 24
Finished	Apr 23 05:12:03 PM PDT 24
Peak memory	600360 kb
Host	smart-1820b89e-0e66-4250-8782-26452188509f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909429153 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_smoketest.909429153
Directory	/workspace/2.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.552970386
Short name	T1086
Test name
Test status
Simulation time	8445605408 ps
CPU time	1477.19 seconds
Started	Apr 23 04:17:17 PM PDT 24
Finished	Apr 23 04:41:54 PM PDT 24
Peak memory	601532 kb
Host	smart-4b6376fb-be95-4c7c-9292-da745ef44ff5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=552970386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.552970386
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3346529552
Short name	T922
Test name
Test status
Simulation time	9638057400 ps
CPU time	1415.63 seconds
Started	Apr 23 04:16:22 PM PDT 24
Finished	Apr 23 04:39:59 PM PDT 24
Peak memory	600304 kb
Host	smart-198e73c5-8927-427c-ad96-a110e65903a9
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3346529552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.3346529552
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4134755103
Short name	T937
Test name
Test status
Simulation time	7443124060 ps
CPU time	1281.01 seconds
Started	Apr 23 04:16:40 PM PDT 24
Finished	Apr 23 04:38:01 PM PDT 24
Peak memory	600524 kb
Host	smart-a684a667-0332-4195-ba32-3c6af5f2f266
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4134755103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.4134755103
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3497973625
Short name	T977
Test name
Test status
Simulation time	4193654486 ps
CPU time	672.42 seconds
Started	Apr 23 04:16:42 PM PDT 24
Finished	Apr 23 04:27:55 PM PDT 24
Peak memory	599908 kb
Host	smart-a35ce557-5c09-4d37-85c0-c28f4ceede07
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3497973625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3497973625
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.661740629
Short name	T953
Test name
Test status
Simulation time	2198436480 ps
CPU time	213.55 seconds
Started	Apr 23 04:27:20 PM PDT 24
Finished	Apr 23 04:30:54 PM PDT 24
Peak memory	599888 kb
Host	smart-64105278-1ba5-41ea-8d9e-798c98bd61b3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661740629 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_otp_ctrl_smoketest.661740629
Directory	/workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pattgen_ios.1074859982
Short name	T321
Test name
Test status
Simulation time	3134070356 ps
CPU time	228.87 seconds
Started	Apr 23 04:15:34 PM PDT 24
Finished	Apr 23 04:19:24 PM PDT 24
Peak memory	600128 kb
Host	smart-b82cafed-9f52-4871-8737-6c3595dec37c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074859982 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.1074859982
Directory	/workspace/2.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/2.chip_sw_plic_sw_irq.2052497545
Short name	T630
Test name
Test status
Simulation time	2393777724 ps
CPU time	251.95 seconds
Started	Apr 23 04:24:12 PM PDT 24
Finished	Apr 23 04:28:24 PM PDT 24
Peak memory	599892 kb
Host	smart-ff171190-fdf2-478d-8620-a99b5f8fdfbb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052497545 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.2052497545
Directory	/workspace/2.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_power_idle_load.4070746468
Short name	T159
Test name
Test status
Simulation time	3873716200 ps
CPU time	769.84 seconds
Started	Apr 23 04:25:31 PM PDT 24
Finished	Apr 23 04:38:21 PM PDT 24
Peak memory	600256 kb
Host	smart-d2e555f2-1860-412e-8c8b-024e85b8a1f3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070746468 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.4070746468
Directory	/workspace/2.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/2.chip_sw_power_sleep_load.4025133162
Short name	T635
Test name
Test status
Simulation time	4649716360 ps
CPU time	320.25 seconds
Started	Apr 23 04:26:25 PM PDT 24
Finished	Apr 23 04:31:45 PM PDT 24
Peak memory	600396 kb
Host	smart-728b79ec-37cc-46c9-bba1-05b9634a8c1e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025133162 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.4025133162
Directory	/workspace/2.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.717846966
Short name	T499
Test name
Test status
Simulation time	13627304068 ps
CPU time	1713.47 seconds
Started	Apr 23 04:19:26 PM PDT 24
Finished	Apr 23 04:48:00 PM PDT 24
Peak memory	601256 kb
Host	smart-4610267c-7c70-4794-a4bb-5688dec566f6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7178 46966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.717846966
Directory	/workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.4099551518
Short name	T971
Test name
Test status
Simulation time	22391993991 ps
CPU time	2262.36 seconds
Started	Apr 23 04:23:21 PM PDT 24
Finished	Apr 23 05:01:04 PM PDT 24
Peak memory	600440 kb
Host	smart-60b9033c-e0d4-48b5-a9b5-89f6d4078baf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409 9551518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.4099551518
Directory	/workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.825099608
Short name	T959
Test name
Test status
Simulation time	16609522696 ps
CPU time	1292.4 seconds
Started	Apr 23 04:19:53 PM PDT 24
Finished	Apr 23 04:41:26 PM PDT 24
Peak memory	601328 kb
Host	smart-61b75a92-4bec-4cd8-b5f8-9be478a19fb6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=825099608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.825099608
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3574245690
Short name	T375
Test name
Test status
Simulation time	20219534000 ps
CPU time	1370.44 seconds
Started	Apr 23 04:25:11 PM PDT 24
Finished	Apr 23 04:48:03 PM PDT 24
Peak memory	600876 kb
Host	smart-f8ac263f-3906-4771-8046-5e3bd1a4d994
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3574245690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3574245690
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1507007255
Short name	T1130
Test name
Test status
Simulation time	7494254480 ps
CPU time	507.17 seconds
Started	Apr 23 04:17:30 PM PDT 24
Finished	Apr 23 04:25:58 PM PDT 24
Peak memory	600676 kb
Host	smart-0849eb67-0b85-443e-86ac-738475bd85fe
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507007255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.1507007255
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1950498445
Short name	T395
Test name
Test status
Simulation time	5377774206 ps
CPU time	496.96 seconds
Started	Apr 23 04:17:47 PM PDT 24
Finished	Apr 23 04:26:04 PM PDT 24
Peak memory	606864 kb
Host	smart-be351d78-1a56-49cc-b453-fdd6c1a072b8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1950498445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1950498445
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2273844551
Short name	T974
Test name
Test status
Simulation time	9374074248 ps
CPU time	502.58 seconds
Started	Apr 23 04:18:57 PM PDT 24
Finished	Apr 23 04:27:20 PM PDT 24
Peak memory	600644 kb
Host	smart-8f436e47-da5d-443b-b8f4-551cf99493ed
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273844551 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2273844551
Directory	/workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.356403211
Short name	T1059
Test name
Test status
Simulation time	4611301556 ps
CPU time	418.5 seconds
Started	Apr 23 04:17:17 PM PDT 24
Finished	Apr 23 04:24:16 PM PDT 24
Peak memory	606760 kb
Host	smart-2fff1f31-4d22-4c2d-8920-dedf523f635c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=356403211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.356403211
Directory	/workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1576035136
Short name	T1206
Test name
Test status
Simulation time	12094375223 ps
CPU time	1691.39 seconds
Started	Apr 23 04:19:45 PM PDT 24
Finished	Apr 23 04:47:56 PM PDT 24
Peak memory	601348 kb
Host	smart-4020552b-2556-4fa6-9363-6c021cefad98
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576035136 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1576035136
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4139699884
Short name	T1078
Test name
Test status
Simulation time	6674930800 ps
CPU time	626.26 seconds
Started	Apr 23 04:20:10 PM PDT 24
Finished	Apr 23 04:30:37 PM PDT 24
Peak memory	600672 kb
Host	smart-62af6640-64be-4803-89d8-4d0c329f4899
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139699884 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.4139699884
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.101175976
Short name	T50
Test name
Test status
Simulation time	21637672626 ps
CPU time	1509.26 seconds
Started	Apr 23 04:25:07 PM PDT 24
Finished	Apr 23 04:50:16 PM PDT 24
Peak memory	601588 kb
Host	smart-c086498c-de4c-4d9f-b128-44a58881c939
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=101175976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.101175976
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.809981376
Short name	T965
Test name
Test status
Simulation time	36512000586 ps
CPU time	3706.76 seconds
Started	Apr 23 04:18:04 PM PDT 24
Finished	Apr 23 05:19:51 PM PDT 24
Peak memory	603340 kb
Host	smart-df892593-7653-49e8-8427-daae5edd1192
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809981376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.809981376
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3789840483
Short name	T628
Test name
Test status
Simulation time	2811417170 ps
CPU time	296.88 seconds
Started	Apr 23 04:18:28 PM PDT 24
Finished	Apr 23 04:23:25 PM PDT 24
Peak memory	599932 kb
Host	smart-887d14fd-dcb6-4983-b63b-cb3af048c4e9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789840483 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.3789840483
Directory	/workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3215160394
Short name	T874
Test name
Test status
Simulation time	6779193526 ps
CPU time	403.78 seconds
Started	Apr 23 04:20:16 PM PDT 24
Finished	Apr 23 04:27:00 PM PDT 24
Peak memory	606332 kb
Host	smart-3e524ce0-08b5-4739-bcd1-cdafb15f1b89
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3215160394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.3215160394
Directory	/workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1149447402
Short name	T137
Test name
Test status
Simulation time	5693953320 ps
CPU time	632.28 seconds
Started	Apr 23 04:24:42 PM PDT 24
Finished	Apr 23 04:35:15 PM PDT 24
Peak memory	600016 kb
Host	smart-ec16a663-7cd9-4496-bd92-c74b7ac8dbf1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11494474 02 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1149447402
Directory	/workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3786350108
Short name	T134
Test name
Test status
Simulation time	4391918120 ps
CPU time	461.28 seconds
Started	Apr 23 04:25:06 PM PDT 24
Finished	Apr 23 04:32:48 PM PDT 24
Peak memory	600516 kb
Host	smart-f44983f1-dcf3-429a-ad16-0a7c61fe9f43
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3786350108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3786350108
Directory	/workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3773179845
Short name	T851
Test name
Test status
Simulation time	6325360456 ps
CPU time	472.94 seconds
Started	Apr 23 04:25:13 PM PDT 24
Finished	Apr 23 04:33:06 PM PDT 24
Peak memory	600444 kb
Host	smart-4b8af103-d3c1-4ca6-8ac2-e49bbd1fe302
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773179845 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.3773179845
Directory	/workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2480683238
Short name	T638
Test name
Test status
Simulation time	8008935000 ps
CPU time	1123.41 seconds
Started	Apr 23 04:18:56 PM PDT 24
Finished	Apr 23 04:37:40 PM PDT 24
Peak memory	600796 kb
Host	smart-68d4239e-9296-4ce4-9f9a-ccaae5acbbf5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480683238 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.2480683238
Directory	/workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2105876840
Short name	T1185
Test name
Test status
Simulation time	4712772752 ps
CPU time	318.98 seconds
Started	Apr 23 04:20:20 PM PDT 24
Finished	Apr 23 04:25:39 PM PDT 24
Peak memory	598588 kb
Host	smart-f966d2b9-1494-462c-be2b-9eedb8458719
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105876840 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2105876840
Directory	/workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.808648394
Short name	T992
Test name
Test status
Simulation time	5010870014 ps
CPU time	318.22 seconds
Started	Apr 23 04:25:52 PM PDT 24
Finished	Apr 23 04:31:11 PM PDT 24
Peak memory	600356 kb
Host	smart-b5e03afa-5115-41e1-98e1-46331fc15542
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808648394 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.808648394
Directory	/workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2223577681
Short name	T994
Test name
Test status
Simulation time	5595100640 ps
CPU time	540.78 seconds
Started	Apr 23 04:20:44 PM PDT 24
Finished	Apr 23 04:29:45 PM PDT 24
Peak memory	600324 kb
Host	smart-5bb31be7-831a-4590-ac2f-74548017c6ae
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222 3577681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.2223577681
Directory	/workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4189335231
Short name	T4
Test name
Test status
Simulation time	8843718732 ps
CPU time	543 seconds
Started	Apr 23 04:23:45 PM PDT 24
Finished	Apr 23 04:32:49 PM PDT 24
Peak memory	600344 kb
Host	smart-cd5c91e7-a611-439a-9e15-bc139c9bafb7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189335231 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.4189335231
Directory	/workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2822519889
Short name	T297
Test name
Test status
Simulation time	10569416766 ps
CPU time	1675.53 seconds
Started	Apr 23 04:19:02 PM PDT 24
Finished	Apr 23 04:46:58 PM PDT 24
Peak memory	601708 kb
Host	smart-4355b60d-0fc7-49b3-926b-7df8e3715195
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2822519889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.2822519889
Directory	/workspace/2.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1878382572
Short name	T239
Test name
Test status
Simulation time	7206754008 ps
CPU time	970.74 seconds
Started	Apr 23 04:17:30 PM PDT 24
Finished	Apr 23 04:33:42 PM PDT 24
Peak memory	600208 kb
Host	smart-ea77f2b0-e6a1-4697-8740-d57c4d9596f2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878382572 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1878382572
Directory	/workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.746203900
Short name	T338
Test name
Test status
Simulation time	5757971492 ps
CPU time	678.64 seconds
Started	Apr 23 04:14:58 PM PDT 24
Finished	Apr 23 04:26:17 PM PDT 24
Peak memory	632488 kb
Host	smart-d53b8047-cf41-4665-8b3c-d747e278edca
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 746203900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.746203900
Directory	/workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.121601149
Short name	T836
Test name
Test status
Simulation time	2310502550 ps
CPU time	245.81 seconds
Started	Apr 23 04:27:45 PM PDT 24
Finished	Apr 23 04:31:53 PM PDT 24
Peak memory	599872 kb
Host	smart-e3980df1-d832-483c-ab2e-55f650a554a9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121601149 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_rstmgr_smoketest.121601149
Directory	/workspace/2.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.851324328
Short name	T1037
Test name
Test status
Simulation time	4621870328 ps
CPU time	460.63 seconds
Started	Apr 23 04:19:46 PM PDT 24
Finished	Apr 23 04:27:27 PM PDT 24
Peak memory	600280 kb
Host	smart-8a05288c-434c-4e4a-aaaa-74f20b6ebd93
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851324328 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rstmgr_sw_req.851324328
Directory	/workspace/2.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3958500108
Short name	T257
Test name
Test status
Simulation time	2343486720 ps
CPU time	197.83 seconds
Started	Apr 23 04:17:55 PM PDT 24
Finished	Apr 23 04:21:13 PM PDT 24
Peak memory	600216 kb
Host	smart-e6043782-e8e8-40ee-8cd9-21ce564527d7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958500108 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3958500108
Directory	/workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.249098607
Short name	T183
Test name
Test status
Simulation time	2665518334 ps
CPU time	232.53 seconds
Started	Apr 23 04:24:25 PM PDT 24
Finished	Apr 23 04:28:18 PM PDT 24
Peak memory	600148 kb
Host	smart-0bdd6ce7-c8e7-4936-8311-df0bf238690d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=249098607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.249098607
Directory	/workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1182430350
Short name	T278
Test name
Test status
Simulation time	3081740246 ps
CPU time	273.14 seconds
Started	Apr 23 04:25:42 PM PDT 24
Finished	Apr 23 04:30:16 PM PDT 24
Peak memory	600292 kb
Host	smart-724fddec-36a5-44a2-9c18-6ae9c48ad41b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182430350 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1182430350
Directory	/workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1123847704
Short name	T498
Test name
Test status
Simulation time	4962453338 ps
CPU time	903.42 seconds
Started	Apr 23 04:20:02 PM PDT 24
Finished	Apr 23 04:35:06 PM PDT 24
Peak memory	600220 kb
Host	smart-25a3aa54-57fa-4176-99dc-f7ad1b633475
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11238 47704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.1123847704
Directory	/workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.964202291
Short name	T1159
Test name
Test status
Simulation time	5430226496 ps
CPU time	843.71 seconds
Started	Apr 23 04:19:03 PM PDT 24
Finished	Apr 23 04:33:08 PM PDT 24
Peak memory	600272 kb
Host	smart-d1029aa7-e15c-4b10-8793-e597b41026c6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=964202291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.964202291
Directory	/workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3425527855
Short name	T606
Test name
Test status
Simulation time	6001143718 ps
CPU time	577.75 seconds
Started	Apr 23 04:24:10 PM PDT 24
Finished	Apr 23 04:33:49 PM PDT 24
Peak memory	606296 kb
Host	smart-390ca115-b53c-4d2d-be46-44ebbf7b0d4b
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425527855 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.3425527855
Directory	/workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.835360015
Short name	T237
Test name
Test status
Simulation time	4685385420 ps
CPU time	452.9 seconds
Started	Apr 23 04:25:38 PM PDT 24
Finished	Apr 23 04:33:12 PM PDT 24
Peak memory	609576 kb
Host	smart-35399491-dffe-44ec-9f48-5823a143b55a
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835360 015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.835360015
Directory	/workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1620499487
Short name	T1010
Test name
Test status
Simulation time	2367276386 ps
CPU time	251.21 seconds
Started	Apr 23 04:26:06 PM PDT 24
Finished	Apr 23 04:30:18 PM PDT 24
Peak memory	600204 kb
Host	smart-85c5f359-17de-415d-ae70-371a32681e58
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620499487 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.1620499487
Directory	/workspace/2.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_irq.2359038729
Short name	T1104
Test name
Test status
Simulation time	3045892234 ps
CPU time	146.58 seconds
Started	Apr 23 04:20:20 PM PDT 24
Finished	Apr 23 04:22:47 PM PDT 24
Peak memory	599152 kb
Host	smart-d32e9837-b09d-4a38-8fd6-b706f8d342af
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359038729 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.2359038729
Directory	/workspace/2.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.69153996
Short name	T1056
Test name
Test status
Simulation time	2957386550 ps
CPU time	178.19 seconds
Started	Apr 23 04:26:47 PM PDT 24
Finished	Apr 23 04:29:46 PM PDT 24
Peak memory	599824 kb
Host	smart-2325ffdc-5218-4815-b3d0-ab860f5fa66d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69153996 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_timer_smoketest.69153996
Directory	/workspace/2.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1015516043
Short name	T100
Test name
Test status
Simulation time	7870534386 ps
CPU time	1163.87 seconds
Started	Apr 23 04:23:48 PM PDT 24
Finished	Apr 23 04:43:12 PM PDT 24
Peak memory	600376 kb
Host	smart-d45b62e7-7118-4fad-b2bc-da066e559bdb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10155160 43 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.1015516043
Directory	/workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3589689434
Short name	T1018
Test name
Test status
Simulation time	2523069639 ps
CPU time	232.43 seconds
Started	Apr 23 04:23:51 PM PDT 24
Finished	Apr 23 04:27:44 PM PDT 24
Peak memory	600572 kb
Host	smart-bbbfc996-f66c-4ed9-952c-37f3d808b1cb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589689 434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3589689434
Directory	/workspace/2.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2635011861
Short name	T57
Test name
Test status
Simulation time	3962573090 ps
CPU time	286.7 seconds
Started	Apr 23 04:14:34 PM PDT 24
Finished	Apr 23 04:19:21 PM PDT 24
Peak memory	600336 kb
Host	smart-a4f3e112-231e-475a-b2f2-ddd6e9a5a988
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635011861 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.2635011861
Directory	/workspace/2.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2184187675
Short name	T51
Test name
Test status
Simulation time	3235890876 ps
CPU time	280.81 seconds
Started	Apr 23 04:15:56 PM PDT 24
Finished	Apr 23 04:20:38 PM PDT 24
Peak memory	600240 kb
Host	smart-604351bb-44d9-40cd-8d1e-fea9b80a7675
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184187675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.2184187675
Directory	/workspace/2.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4011068405
Short name	T1131
Test name
Test status
Simulation time	8896484826 ps
CPU time	1379.37 seconds
Started	Apr 23 04:15:29 PM PDT 24
Finished	Apr 23 04:38:29 PM PDT 24
Peak memory	600696 kb
Host	smart-83098fdd-f9c1-4190-8e9a-a3ae8e00c050
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011068405 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.4011068405
Directory	/workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2793771579
Short name	T128
Test name
Test status
Simulation time	6658128128 ps
CPU time	672.5 seconds
Started	Apr 23 04:23:51 PM PDT 24
Finished	Apr 23 04:35:05 PM PDT 24
Peak memory	601496 kb
Host	smart-b78a1426-42c1-4678-beea-8ea5c6d3e41c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793771579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.2793771579
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1182426599
Short name	T1000
Test name
Test status
Simulation time	6255169400 ps
CPU time	510.21 seconds
Started	Apr 23 04:23:38 PM PDT 24
Finished	Apr 23 04:32:10 PM PDT 24
Peak memory	601480 kb
Host	smart-2b2cd332-225f-41de-ab69-fb1dda294d45
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182426599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.1182426599
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.686695121
Short name	T12
Test name
Test status
Simulation time	4931382012 ps
CPU time	477.06 seconds
Started	Apr 23 04:15:46 PM PDT 24
Finished	Apr 23 04:23:44 PM PDT 24
Peak memory	617720 kb
Host	smart-2dcdbe72-dae2-41f3-8af3-92011c26ea53
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686695121 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.686695121
Directory	/workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_tpm.3484666536
Short name	T40
Test name
Test status
Simulation time	3051066537 ps
CPU time	327.81 seconds
Started	Apr 23 04:15:04 PM PDT 24
Finished	Apr 23 04:20:32 PM PDT 24
Peak memory	607580 kb
Host	smart-734b1747-43f5-4526-ae70-ba0f1ec190ae
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484666536 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.3484666536
Directory	/workspace/2.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.962027705
Short name	T33
Test name
Test status
Simulation time	3266015834 ps
CPU time	284.01 seconds
Started	Apr 23 04:15:09 PM PDT 24
Finished	Apr 23 04:19:54 PM PDT 24
Peak memory	600356 kb
Host	smart-206d9790-b66d-4c11-9d40-7a5eefa9215e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962027705 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.962027705
Directory	/workspace/2.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1342213921
Short name	T279
Test name
Test status
Simulation time	7299991423 ps
CPU time	757.8 seconds
Started	Apr 23 04:22:41 PM PDT 24
Finished	Apr 23 04:35:20 PM PDT 24
Peak memory	600280 kb
Host	smart-ba6cfb17-b407-4415-a84f-c7dd3b939ba8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342213921 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1342213921
Directory	/workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1849990048
Short name	T1129
Test name
Test status
Simulation time	4999727546 ps
CPU time	439.41 seconds
Started	Apr 23 04:22:25 PM PDT 24
Finished	Apr 23 04:29:45 PM PDT 24
Peak memory	600920 kb
Host	smart-ba60d376-78d4-42a4-8cfd-73afb09d16be
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849990048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.1849990048
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.518202131
Short name	T1143
Test name
Test status
Simulation time	4775701696 ps
CPU time	563.28 seconds
Started	Apr 23 04:23:48 PM PDT 24
Finished	Apr 23 04:33:12 PM PDT 24
Peak memory	600816 kb
Host	smart-9fa0e8dc-7541-4211-9f51-656c063583f2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518202131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.518202131
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2158392329
Short name	T123
Test name
Test status
Simulation time	4422113718 ps
CPU time	532.27 seconds
Started	Apr 23 04:25:59 PM PDT 24
Finished	Apr 23 04:34:52 PM PDT 24
Peak memory	600676 kb
Host	smart-d6ef80e4-df2d-4ede-9906-2a27d96786b7
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158392329 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2158392329
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.329771508
Short name	T1033
Test name
Test status
Simulation time	3510258068 ps
CPU time	315.5 seconds
Started	Apr 23 04:27:41 PM PDT 24
Finished	Apr 23 04:32:57 PM PDT 24
Peak memory	600192 kb
Host	smart-83003af7-d602-467f-9562-b9c3e3d4f474
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329771508 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sram_ctrl_smoketest.329771508
Directory	/workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1660684219
Short name	T646
Test name
Test status
Simulation time	20535198361 ps
CPU time	3485.85 seconds
Started	Apr 23 04:20:36 PM PDT 24
Finished	Apr 23 05:18:43 PM PDT 24
Peak memory	600464 kb
Host	smart-b241c2cd-2716-4c75-8ac7-2c002bddd0a2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660684219 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.1660684219
Directory	/workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.352494995
Short name	T331
Test name
Test status
Simulation time	4134691286 ps
CPU time	597.28 seconds
Started	Apr 23 04:19:51 PM PDT 24
Finished	Apr 23 04:29:50 PM PDT 24
Peak memory	604016 kb
Host	smart-341ac1b8-d372-42ff-afca-663f972461a5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352494995 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.352494995
Directory	/workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.94647850
Short name	T20
Test name
Test status
Simulation time	22420396188 ps
CPU time	1659.75 seconds
Started	Apr 23 04:19:21 PM PDT 24
Finished	Apr 23 04:47:01 PM PDT 24
Peak memory	605044 kb
Host	smart-8dd37234-94ec-47b3-89c9-9a2fe5c77c96
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94647850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.94647850
Directory	/workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1375042895
Short name	T857
Test name
Test status
Simulation time	4025212130 ps
CPU time	598.36 seconds
Started	Apr 23 04:15:12 PM PDT 24
Finished	Apr 23 04:25:11 PM PDT 24
Peak memory	607532 kb
Host	smart-5dac337f-c30c-4799-aee8-e6c330a76c23
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1375042895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1375042895
Directory	/workspace/2.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_smoketest.723593233
Short name	T642
Test name
Test status
Simulation time	2230064142 ps
CPU time	225.2 seconds
Started	Apr 23 04:27:10 PM PDT 24
Finished	Apr 23 04:30:56 PM PDT 24
Peak memory	599988 kb
Host	smart-b7d3f2b1-5689-425e-967a-8930407191ca
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723593233 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_uart_smoketest.723593233
Directory	/workspace/2.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx.1521679973
Short name	T1109
Test name
Test status
Simulation time	3981041996 ps
CPU time	603.14 seconds
Started	Apr 23 04:16:21 PM PDT 24
Finished	Apr 23 04:26:25 PM PDT 24
Peak memory	608532 kb
Host	smart-8d66ed9d-380e-4f62-ad13-18d4a6c84a1b
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521679973 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.1521679973
Directory	/workspace/2.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2320359484
Short name	T381
Test name
Test status
Simulation time	8356129960 ps
CPU time	1746.79 seconds
Started	Apr 23 04:14:55 PM PDT 24
Finished	Apr 23 04:44:02 PM PDT 24
Peak memory	607536 kb
Host	smart-0a114bbc-a872-4af9-b224-d94139179535
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320359484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.2320359484
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3246258831
Short name	T1164
Test name
Test status
Simulation time	4479806665 ps
CPU time	643.51 seconds
Started	Apr 23 04:15:43 PM PDT 24
Finished	Apr 23 04:26:27 PM PDT 24
Peak memory	607532 kb
Host	smart-dcf07c32-4f6f-43e7-a246-a0b747b88ead
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246258831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3246258831
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1915464367
Short name	T1186
Test name
Test status
Simulation time	3758010938 ps
CPU time	683.53 seconds
Started	Apr 23 04:14:36 PM PDT 24
Finished	Apr 23 04:26:00 PM PDT 24
Peak memory	608576 kb
Host	smart-59468e51-6bc3-4fa2-81db-20c86b05547c
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915464367 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1915464367
Directory	/workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.760395328
Short name	T390
Test name
Test status
Simulation time	3701982712 ps
CPU time	560.85 seconds
Started	Apr 23 04:15:03 PM PDT 24
Finished	Apr 23 04:24:25 PM PDT 24
Peak memory	608540 kb
Host	smart-2c6968c9-943f-462b-b8e9-fa550678e9c9
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760395328 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.760395328
Directory	/workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1644463978
Short name	T839
Test name
Test status
Simulation time	4332104792 ps
CPU time	494.36 seconds
Started	Apr 23 04:14:37 PM PDT 24
Finished	Apr 23 04:22:52 PM PDT 24
Peak memory	608500 kb
Host	smart-2b28d47c-19e3-4732-8100-30fbf3e4c521
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644463978 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1644463978
Directory	/workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_dev.454780961
Short name	T397
Test name
Test status
Simulation time	10171864715 ps
CPU time	1105.6 seconds
Started	Apr 23 04:23:05 PM PDT 24
Finished	Apr 23 04:41:31 PM PDT 24
Peak memory	608804 kb
Host	smart-26d3e752-3295-47d9-82aa-08560d7d98e1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=454780961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.454780961
Directory	/workspace/2.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_prod.3000407485
Short name	T982
Test name
Test status
Simulation time	7829330346 ps
CPU time	721.17 seconds
Started	Apr 23 04:24:41 PM PDT 24
Finished	Apr 23 04:36:43 PM PDT 24
Peak memory	608840 kb
Host	smart-e96bc225-9f0f-4bc4-80e7-a6a04dd9776b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000407485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.3000407485
Directory	/workspace/2.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_rma.3823001005
Short name	T1120
Test name
Test status
Simulation time	5537971889 ps
CPU time	451.48 seconds
Started	Apr 23 04:24:46 PM PDT 24
Finished	Apr 23 04:32:18 PM PDT 24
Peak memory	619188 kb
Host	smart-df3044e3-2a58-48db-a1f5-252ae55b7cef
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823001005 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.3823001005
Directory	/workspace/2.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2691502854
Short name	T1196
Test name
Test status
Simulation time	3417051740 ps
CPU time	223.66 seconds
Started	Apr 23 04:24:28 PM PDT 24
Finished	Apr 23 04:28:12 PM PDT 24
Peak memory	618132 kb
Host	smart-4f94b9d3-a7e9-4ef2-adff-a6627020d2ee
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2691502854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.2691502854
Directory	/workspace/2.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.455959986
Short name	T47
Test name
Test status
Simulation time	79246461421 ps
CPU time	18096 seconds
Started	Apr 23 04:29:15 PM PDT 24
Finished	Apr 23 09:30:53 PM PDT 24
Peak memory	600736 kb
Host	smart-7d753ae5-e0b8-484d-a417-990f956682f1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_ flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455959986 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_test_unlocked0.455959986
Directory	/workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/2.rom_keymgr_functest.1674026974
Short name	T939
Test name
Test status
Simulation time	5343252400 ps
CPU time	595.47 seconds
Started	Apr 23 04:28:34 PM PDT 24
Finished	Apr 23 04:38:31 PM PDT 24
Peak memory	600224 kb
Host	smart-6b589607-0587-4cf1-a1dd-4b123997c958
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674026974 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.1674026974
Directory	/workspace/2.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/2.rom_volatile_raw_unlock.1032478813
Short name	T1002
Test name
Test status
Simulation time	2130496161 ps
CPU time	104.76 seconds
Started	Apr 23 04:26:01 PM PDT 24
Finished	Apr 23 04:27:46 PM PDT 24
Peak memory	607852 kb
Host	smart-509eb163-f362-4d52-8c29-325db0d2177b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032478813 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.1032478813
Directory	/workspace/2.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/22.chip_sw_all_escalation_resets.4096234781
Short name	T744
Test name
Test status
Simulation time	5268709970 ps
CPU time	533.99 seconds
Started	Apr 23 04:28:17 PM PDT 24
Finished	Apr 23 04:37:12 PM PDT 24
Peak memory	637532 kb
Host	smart-ee64e4d9-e5d6-4f8e-a501-637e117a0d7b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4096234781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.4096234781
Directory	/workspace/22.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/23.chip_sw_all_escalation_resets.1677261455
Short name	T1014
Test name
Test status
Simulation time	5033373220 ps
CPU time	585.34 seconds
Started	Apr 23 04:27:25 PM PDT 24
Finished	Apr 23 04:37:11 PM PDT 24
Peak memory	634628 kb
Host	smart-98337a0d-f9ec-4e9a-aa69-a210f0064758
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1677261455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.1677261455
Directory	/workspace/23.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2158537450
Short name	T283
Test name
Test status
Simulation time	3623529356 ps
CPU time	383.08 seconds
Started	Apr 23 04:31:55 PM PDT 24
Finished	Apr 23 04:38:18 PM PDT 24
Peak memory	634296 kb
Host	smart-cf78a042-d1a9-4059-9263-d7af38584c60
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158537450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2158537450
Directory	/workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2940105218
Short name	T737
Test name
Test status
Simulation time	4786172232 ps
CPU time	628.8 seconds
Started	Apr 23 04:28:09 PM PDT 24
Finished	Apr 23 04:38:38 PM PDT 24
Peak memory	637520 kb
Host	smart-1d33d55b-031e-4b1e-8750-7b46f565f8ab
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2940105218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.2940105218
Directory	/workspace/26.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3113316710
Short name	T228
Test name
Test status
Simulation time	3653209654 ps
CPU time	260.93 seconds
Started	Apr 23 04:29:13 PM PDT 24
Finished	Apr 23 04:33:34 PM PDT 24
Peak memory	633332 kb
Host	smart-5974ecbb-dae3-4ff4-a8c8-fd9f00f5cc50
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113316710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3113316710
Directory	/workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2193959709
Short name	T690
Test name
Test status
Simulation time	5073633030 ps
CPU time	638.27 seconds
Started	Apr 23 04:30:00 PM PDT 24
Finished	Apr 23 04:40:39 PM PDT 24
Peak memory	635776 kb
Host	smart-1da294b7-a8fb-4d4f-acda-0e2047f7597a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2193959709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2193959709
Directory	/workspace/27.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3426579641
Short name	T651
Test name
Test status
Simulation time	6186324866 ps
CPU time	640.32 seconds
Started	Apr 23 04:30:44 PM PDT 24
Finished	Apr 23 04:41:25 PM PDT 24
Peak memory	637436 kb
Host	smart-cc249098-29d3-4899-b4e4-0ef8c75d1e49
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3426579641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3426579641
Directory	/workspace/29.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3475031780
Short name	T1178
Test name
Test status
Simulation time	3081666024 ps
CPU time	396.94 seconds
Started	Apr 23 04:25:57 PM PDT 24
Finished	Apr 23 04:32:34 PM PDT 24
Peak memory	635268 kb
Host	smart-351f9de1-80eb-42e8-9961-cd34acc4410d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475031780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.3475031780
Directory	/workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4210422116
Short name	T293
Test name
Test status
Simulation time	7378461706 ps
CPU time	444.27 seconds
Started	Apr 23 04:25:24 PM PDT 24
Finished	Apr 23 04:32:49 PM PDT 24
Peak memory	600240 kb
Host	smart-7cb4d9e0-93ca-4fa9-a2bc-3ab511a9e61a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4210422116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4210422116
Directory	/workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.4202475951
Short name	T251
Test name
Test status
Simulation time	5044684858 ps
CPU time	719.32 seconds
Started	Apr 23 04:28:03 PM PDT 24
Finished	Apr 23 04:40:04 PM PDT 24
Peak memory	600864 kb
Host	smart-bff8c66a-efd7-45aa-b9b3-75422187cb8a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4202475951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.4202475951
Directory	/workspace/3.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.742033453
Short name	T125
Test name
Test status
Simulation time	10963548116 ps
CPU time	993.83 seconds
Started	Apr 23 04:27:15 PM PDT 24
Finished	Apr 23 04:43:49 PM PDT 24
Peak memory	611720 kb
Host	smart-6db973e5-38df-4d46-a33d-04610c0f2a40
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742033453 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.742033453
Directory	/workspace/3.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.296391611
Short name	T140
Test name
Test status
Simulation time	6286015728 ps
CPU time	743.23 seconds
Started	Apr 23 04:26:18 PM PDT 24
Finished	Apr 23 04:38:42 PM PDT 24
Peak memory	600336 kb
Host	smart-0d540474-8087-4aff-b4a1-e240cb7a11c8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29639161 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.296391611
Directory	/workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2749379796
Short name	T1074
Test name
Test status
Simulation time	8638617870 ps
CPU time	2050.81 seconds
Started	Apr 23 04:31:05 PM PDT 24
Finished	Apr 23 05:05:17 PM PDT 24
Peak memory	607544 kb
Host	smart-de4cbb6e-2dbf-421f-b14e-27c08fee1387
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2749379796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.2749379796
Directory	/workspace/3.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx.1790754349
Short name	T871
Test name
Test status
Simulation time	3915260220 ps
CPU time	545.92 seconds
Started	Apr 23 04:27:10 PM PDT 24
Finished	Apr 23 04:36:16 PM PDT 24
Peak memory	608472 kb
Host	smart-d3c96c1e-84cc-499e-85ea-8f7849b03bb7
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790754349 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1790754349
Directory	/workspace/3.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.546800106
Short name	T999
Test name
Test status
Simulation time	8419687925 ps
CPU time	1173.19 seconds
Started	Apr 23 04:31:02 PM PDT 24
Finished	Apr 23 04:50:36 PM PDT 24
Peak memory	607548 kb
Host	smart-5d41c468-dd83-43ac-9269-db1611fcd5a0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546800106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.546800106
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1655318766
Short name	T1044
Test name
Test status
Simulation time	4283508352 ps
CPU time	610.17 seconds
Started	Apr 23 04:25:41 PM PDT 24
Finished	Apr 23 04:35:52 PM PDT 24
Peak memory	608500 kb
Host	smart-6048513c-1b4c-46ce-a622-a20406869851
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655318766 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.1655318766
Directory	/workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3451528564
Short name	T360
Test name
Test status
Simulation time	4255562068 ps
CPU time	715.54 seconds
Started	Apr 23 04:26:35 PM PDT 24
Finished	Apr 23 04:38:31 PM PDT 24
Peak memory	608512 kb
Host	smart-722856d2-bc9c-43f3-8981-68cd82ff52f8
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451528564 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.3451528564
Directory	/workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1979126433
Short name	T1127
Test name
Test status
Simulation time	4120727750 ps
CPU time	652.52 seconds
Started	Apr 23 04:25:28 PM PDT 24
Finished	Apr 23 04:36:21 PM PDT 24
Peak memory	608528 kb
Host	smart-ee111852-0fd0-4348-a652-2dc37f7ae46e
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979126433 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.1979126433
Directory	/workspace/3.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_dev.2133086643
Short name	T1061
Test name
Test status
Simulation time	9559080105 ps
CPU time	930.33 seconds
Started	Apr 23 04:26:55 PM PDT 24
Finished	Apr 23 04:42:27 PM PDT 24
Peak memory	610284 kb
Host	smart-339c0d8c-7d9a-4b7c-a2c1-08019ab72ea7
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2133086643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.2133086643
Directory	/workspace/3.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_prod.1338029294
Short name	T78
Test name
Test status
Simulation time	11671600051 ps
CPU time	1007.52 seconds
Started	Apr 23 04:25:18 PM PDT 24
Finished	Apr 23 04:42:06 PM PDT 24
Peak memory	610308 kb
Host	smart-2c15d307-3fc7-40c5-aa21-032c995c3114
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338029294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1338029294
Directory	/workspace/3.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_rma.2433807879
Short name	T884
Test name
Test status
Simulation time	2809510425 ps
CPU time	179.88 seconds
Started	Apr 23 04:26:14 PM PDT 24
Finished	Apr 23 04:29:15 PM PDT 24
Peak memory	610936 kb
Host	smart-ec7fe1f2-ada0-44a8-bfda-aabecab7fd63
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433807879 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2433807879
Directory	/workspace/3.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_testunlock0.3493714330
Short name	T1144
Test name
Test status
Simulation time	2917557183 ps
CPU time	234.62 seconds
Started	Apr 23 04:25:14 PM PDT 24
Finished	Apr 23 04:29:10 PM PDT 24
Peak memory	610956 kb
Host	smart-d49dc33d-c6ce-4519-a759-920889563e80
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493714330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.3493714330
Directory	/workspace/3.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/30.chip_sw_all_escalation_resets.3602311067
Short name	T691
Test name
Test status
Simulation time	5356926950 ps
CPU time	521.85 seconds
Started	Apr 23 04:28:53 PM PDT 24
Finished	Apr 23 04:37:36 PM PDT 24
Peak memory	635880 kb
Host	smart-9bad40cc-d989-4bae-9456-4039436d86ba
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3602311067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.3602311067
Directory	/workspace/30.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/32.chip_sw_all_escalation_resets.521851412
Short name	T1108
Test name
Test status
Simulation time	4361265284 ps
CPU time	575.26 seconds
Started	Apr 23 04:31:21 PM PDT 24
Finished	Apr 23 04:40:57 PM PDT 24
Peak memory	636776 kb
Host	smart-1fd05e5a-4500-4767-8f00-bf2e6ac655bf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 521851412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.521851412
Directory	/workspace/32.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.251554054
Short name	T268
Test name
Test status
Simulation time	4349774818 ps
CPU time	322.75 seconds
Started	Apr 23 04:31:22 PM PDT 24
Finished	Apr 23 04:36:45 PM PDT 24
Peak memory	635672 kb
Host	smart-3b5b69b7-9ecb-4917-9ee5-ab0a2a6c7df2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251554054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_s w_alert_handler_lpg_sleep_mode_alerts.251554054
Directory	/workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/33.chip_sw_all_escalation_resets.3078125663
Short name	T242
Test name
Test status
Simulation time	4464723890 ps
CPU time	798.52 seconds
Started	Apr 23 04:30:28 PM PDT 24
Finished	Apr 23 04:43:47 PM PDT 24
Peak memory	636492 kb
Host	smart-c2aaeb26-4895-4c43-a33a-cb84a6d0fcc9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3078125663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.3078125663
Directory	/workspace/33.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/34.chip_sw_all_escalation_resets.938987418
Short name	T723
Test name
Test status
Simulation time	4510294200 ps
CPU time	513.29 seconds
Started	Apr 23 04:30:20 PM PDT 24
Finished	Apr 23 04:38:54 PM PDT 24
Peak memory	635932 kb
Host	smart-1cbaa3ae-0efe-42b2-9cd2-7b32312c72ff
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 938987418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.938987418
Directory	/workspace/34.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3888387222
Short name	T736
Test name
Test status
Simulation time	3257051212 ps
CPU time	345.18 seconds
Started	Apr 23 04:29:31 PM PDT 24
Finished	Apr 23 04:35:17 PM PDT 24
Peak memory	633524 kb
Host	smart-868521a1-ed6e-49da-a2c9-e3855dcc7a85
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888387222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3888387222
Directory	/workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3254065528
Short name	T901
Test name
Test status
Simulation time	3544829312 ps
CPU time	398.14 seconds
Started	Apr 23 04:28:59 PM PDT 24
Finished	Apr 23 04:35:38 PM PDT 24
Peak memory	606904 kb
Host	smart-6c6b928d-5ee5-4766-abab-2a3e175586ba
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254065528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3254065528
Directory	/workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/37.chip_sw_all_escalation_resets.1335506972
Short name	T337
Test name
Test status
Simulation time	4272288440 ps
CPU time	500.86 seconds
Started	Apr 23 04:31:17 PM PDT 24
Finished	Apr 23 04:39:38 PM PDT 24
Peak memory	634516 kb
Host	smart-7338ef13-698e-456f-aa9c-3e522f2ccc27
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1335506972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.1335506972
Directory	/workspace/37.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1535037119
Short name	T729
Test name
Test status
Simulation time	5815597136 ps
CPU time	587.34 seconds
Started	Apr 23 04:30:45 PM PDT 24
Finished	Apr 23 04:40:32 PM PDT 24
Peak memory	636416 kb
Host	smart-73fa1331-995b-4e10-9bb3-6758f8d0555a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1535037119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1535037119
Directory	/workspace/38.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1950067289
Short name	T164
Test name
Test status
Simulation time	3500428032 ps
CPU time	417.7 seconds
Started	Apr 23 04:30:44 PM PDT 24
Finished	Apr 23 04:37:42 PM PDT 24
Peak memory	633360 kb
Host	smart-e85f0a21-92f8-456e-888c-4950f040e7c0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950067289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1950067289
Directory	/workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/39.chip_sw_all_escalation_resets.120737656
Short name	T748
Test name
Test status
Simulation time	5469095528 ps
CPU time	639.21 seconds
Started	Apr 23 04:29:28 PM PDT 24
Finished	Apr 23 04:40:08 PM PDT 24
Peak memory	635612 kb
Host	smart-0203d31f-6f0a-48da-93ce-968ff8f74d6b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 120737656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.120737656
Directory	/workspace/39.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2797619270
Short name	T732
Test name
Test status
Simulation time	3170507708 ps
CPU time	352.8 seconds
Started	Apr 23 04:28:28 PM PDT 24
Finished	Apr 23 04:34:21 PM PDT 24
Peak memory	635356 kb
Host	smart-5ecb3ddb-dd79-44e2-803d-943520312965
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797619270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.2797619270
Directory	/workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2912212134
Short name	T384
Test name
Test status
Simulation time	4301291652 ps
CPU time	629.68 seconds
Started	Apr 23 04:28:18 PM PDT 24
Finished	Apr 23 04:38:48 PM PDT 24
Peak memory	636512 kb
Host	smart-c16d768c-b631-48ed-b2dc-1b722ef46d56
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2912212134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2912212134
Directory	/workspace/4.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4055349538
Short name	T1007
Test name
Test status
Simulation time	6361369646 ps
CPU time	396.91 seconds
Started	Apr 23 04:26:55 PM PDT 24
Finished	Apr 23 04:33:32 PM PDT 24
Peak memory	600444 kb
Host	smart-342804fe-b54c-4d49-a1b0-5ac7153af3f3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4055349538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4055349538
Directory	/workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1151756288
Short name	T222
Test name
Test status
Simulation time	6819402664 ps
CPU time	564.8 seconds
Started	Apr 23 04:26:21 PM PDT 24
Finished	Apr 23 04:35:46 PM PDT 24
Peak memory	601840 kb
Host	smart-6560b83c-cf10-4a50-a397-b09b9813a9d9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1151756288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.1151756288
Directory	/workspace/4.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1119378592
Short name	T1100
Test name
Test status
Simulation time	5955243887 ps
CPU time	483.81 seconds
Started	Apr 23 04:29:03 PM PDT 24
Finished	Apr 23 04:37:08 PM PDT 24
Peak memory	611736 kb
Host	smart-d78ca079-8686-4098-a04b-0ccb4bd0c8a9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119378592 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.1119378592
Directory	/workspace/4.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3975102041
Short name	T142
Test name
Test status
Simulation time	8774138232 ps
CPU time	969.05 seconds
Started	Apr 23 04:29:02 PM PDT 24
Finished	Apr 23 04:45:12 PM PDT 24
Peak memory	600324 kb
Host	smart-0be7455c-a28e-410c-945f-7ba7d760c6a1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39751020 41 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.3975102041
Directory	/workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2636595527
Short name	T1040
Test name
Test status
Simulation time	12991341186 ps
CPU time	2404.48 seconds
Started	Apr 23 04:26:21 PM PDT 24
Finished	Apr 23 05:06:26 PM PDT 24
Peak memory	607532 kb
Host	smart-55a08ada-92cb-4bcb-8143-f529adccc939
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2636595527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2636595527
Directory	/workspace/4.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx.2171209456
Short name	T890
Test name
Test status
Simulation time	4279037570 ps
CPU time	528.15 seconds
Started	Apr 23 04:28:19 PM PDT 24
Finished	Apr 23 04:37:07 PM PDT 24
Peak memory	608520 kb
Host	smart-eb7b0645-4b13-4ece-8cc0-5d1d0f8ed781
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171209456 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2171209456
Directory	/workspace/4.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3323925048
Short name	T14
Test name
Test status
Simulation time	7768215186 ps
CPU time	1493.42 seconds
Started	Apr 23 04:27:26 PM PDT 24
Finished	Apr 23 04:52:20 PM PDT 24
Peak memory	607500 kb
Host	smart-d25930f6-6c62-4a98-9855-199141ca35d0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323925048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.3323925048
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4089107678
Short name	T854
Test name
Test status
Simulation time	8410495200 ps
CPU time	1423.25 seconds
Started	Apr 23 04:27:06 PM PDT 24
Finished	Apr 23 04:50:50 PM PDT 24
Peak memory	615744 kb
Host	smart-e74f7aca-00a3-4b2f-af35-68c3fb64c513
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089107678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4089107678
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3790562616
Short name	T1163
Test name
Test status
Simulation time	4690497152 ps
CPU time	628.8 seconds
Started	Apr 23 04:26:31 PM PDT 24
Finished	Apr 23 04:37:00 PM PDT 24
Peak memory	608552 kb
Host	smart-8d31391e-e7e2-41f2-884d-215365e8f683
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790562616 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3790562616
Directory	/workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1606343438
Short name	T1017
Test name
Test status
Simulation time	4574889940 ps
CPU time	517.24 seconds
Started	Apr 23 04:28:59 PM PDT 24
Finished	Apr 23 04:37:37 PM PDT 24
Peak memory	608564 kb
Host	smart-c6b3c847-e2bd-4ac1-8066-b9abbe982cca
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606343438 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1606343438
Directory	/workspace/4.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3722734496
Short name	T927
Test name
Test status
Simulation time	4585296244 ps
CPU time	580.17 seconds
Started	Apr 23 04:26:26 PM PDT 24
Finished	Apr 23 04:36:06 PM PDT 24
Peak memory	608536 kb
Host	smart-3f2067a5-1797-47fb-9d6b-8fe2a5a81ca0
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722734496 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.3722734496
Directory	/workspace/4.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_dev.3038093774
Short name	T969
Test name
Test status
Simulation time	3812438326 ps
CPU time	330.47 seconds
Started	Apr 23 04:26:17 PM PDT 24
Finished	Apr 23 04:31:48 PM PDT 24
Peak memory	609476 kb
Host	smart-f1ca45a7-cebd-4bd2-90e9-e00d451757c7
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3038093774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3038093774
Directory	/workspace/4.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_prod.1874432157
Short name	T995
Test name
Test status
Simulation time	4704489392 ps
CPU time	346.18 seconds
Started	Apr 23 04:28:21 PM PDT 24
Finished	Apr 23 04:34:07 PM PDT 24
Peak memory	619180 kb
Host	smart-dea44634-e5ce-4020-8796-26c1dfd43c7b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874432157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.1874432157
Directory	/workspace/4.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_rma.1199613250
Short name	T77
Test name
Test status
Simulation time	1974502422 ps
CPU time	111.57 seconds
Started	Apr 23 04:26:13 PM PDT 24
Finished	Apr 23 04:28:04 PM PDT 24
Peak memory	610504 kb
Host	smart-e8ec6b69-7e62-4852-a8b3-02d7733e109c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199613250 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.1199613250
Directory	/workspace/4.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_testunlock0.1759858559
Short name	T980
Test name
Test status
Simulation time	2704024656 ps
CPU time	174.65 seconds
Started	Apr 23 04:27:35 PM PDT 24
Finished	Apr 23 04:30:30 PM PDT 24
Peak memory	609108 kb
Host	smart-709878d5-2c6b-4ec7-837d-c44b38654d84
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759858559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.1759858559
Directory	/workspace/4.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/40.chip_sw_all_escalation_resets.412342648
Short name	T724
Test name
Test status
Simulation time	4906852604 ps
CPU time	509.94 seconds
Started	Apr 23 04:30:56 PM PDT 24
Finished	Apr 23 04:39:26 PM PDT 24
Peak memory	636704 kb
Host	smart-0f91ff21-5f1b-4458-b353-81ce682eca22
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 412342648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.412342648
Directory	/workspace/40.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1393934209
Short name	T750
Test name
Test status
Simulation time	3586473220 ps
CPU time	431.07 seconds
Started	Apr 23 04:30:41 PM PDT 24
Finished	Apr 23 04:37:52 PM PDT 24
Peak memory	635452 kb
Host	smart-9dbf44eb-bb2f-4830-84c2-010024fc09a7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393934209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1393934209
Directory	/workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/41.chip_sw_all_escalation_resets.3448173768
Short name	T104
Test name
Test status
Simulation time	4415038088 ps
CPU time	558.01 seconds
Started	Apr 23 04:32:10 PM PDT 24
Finished	Apr 23 04:41:29 PM PDT 24
Peak memory	636400 kb
Host	smart-21d4a507-a496-4509-8ae4-a5b29d6ee307
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3448173768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.3448173768
Directory	/workspace/41.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3330046636
Short name	T674
Test name
Test status
Simulation time	3171179680 ps
CPU time	577.69 seconds
Started	Apr 23 04:33:09 PM PDT 24
Finished	Apr 23 04:42:47 PM PDT 24
Peak memory	633504 kb
Host	smart-40fa8813-5432-414e-aaea-324bd935fed1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330046636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3330046636
Directory	/workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3307502182
Short name	T336
Test name
Test status
Simulation time	5794207256 ps
CPU time	714.61 seconds
Started	Apr 23 04:31:59 PM PDT 24
Finished	Apr 23 04:43:54 PM PDT 24
Peak memory	600684 kb
Host	smart-fbd55016-06d5-4365-81af-a0fdd688f3bd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3307502182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.3307502182
Directory	/workspace/42.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2802150554
Short name	T658
Test name
Test status
Simulation time	5649302404 ps
CPU time	552.86 seconds
Started	Apr 23 04:32:33 PM PDT 24
Finished	Apr 23 04:41:46 PM PDT 24
Peak memory	635712 kb
Host	smart-85ff14c2-98a4-4ac8-997d-c10e1902a8f4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2802150554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.2802150554
Directory	/workspace/43.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2855125977
Short name	T96
Test name
Test status
Simulation time	4308368256 ps
CPU time	429.65 seconds
Started	Apr 23 04:32:13 PM PDT 24
Finished	Apr 23 04:39:24 PM PDT 24
Peak memory	633680 kb
Host	smart-366d3e23-21ff-4f73-8100-7858c6e64855
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855125977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2855125977
Directory	/workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.108908157
Short name	T704
Test name
Test status
Simulation time	3469431384 ps
CPU time	503.94 seconds
Started	Apr 23 04:32:07 PM PDT 24
Finished	Apr 23 04:40:32 PM PDT 24
Peak memory	635356 kb
Host	smart-05f4374d-e9b6-4023-8b29-387a56a35962
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108908157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_s w_alert_handler_lpg_sleep_mode_alerts.108908157
Directory	/workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2547098604
Short name	T170
Test name
Test status
Simulation time	5651606558 ps
CPU time	641.47 seconds
Started	Apr 23 04:33:10 PM PDT 24
Finished	Apr 23 04:43:52 PM PDT 24
Peak memory	606728 kb
Host	smart-1694b2af-a217-433d-bc03-047ca2fc69ed
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2547098604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2547098604
Directory	/workspace/47.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3200429258
Short name	T1160
Test name
Test status
Simulation time	3684704328 ps
CPU time	385.63 seconds
Started	Apr 23 04:31:03 PM PDT 24
Finished	Apr 23 04:37:29 PM PDT 24
Peak memory	635464 kb
Host	smart-453f05d1-dfc7-4a45-a1e5-adeb5dd09abf
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200429258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3200429258
Directory	/workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/48.chip_sw_all_escalation_resets.2871552824
Short name	T703
Test name
Test status
Simulation time	4584822092 ps
CPU time	544.51 seconds
Started	Apr 23 04:32:41 PM PDT 24
Finished	Apr 23 04:41:46 PM PDT 24
Peak memory	634596 kb
Host	smart-3ce2dca1-b555-41cc-b504-67cdbfe906b4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2871552824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2871552824
Directory	/workspace/48.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1950434987
Short name	T695
Test name
Test status
Simulation time	3491754344 ps
CPU time	405.69 seconds
Started	Apr 23 04:30:35 PM PDT 24
Finished	Apr 23 04:37:21 PM PDT 24
Peak memory	633696 kb
Host	smart-255f442c-701b-4e93-83bf-3a37328f5dbe
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950434987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1950434987
Directory	/workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3201563678
Short name	T109
Test name
Test status
Simulation time	5689225262 ps
CPU time	779.1 seconds
Started	Apr 23 04:33:08 PM PDT 24
Finished	Apr 23 04:46:08 PM PDT 24
Peak memory	635752 kb
Host	smart-b1e74574-1f87-439f-9c9d-680eeb67dc34
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3201563678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.3201563678
Directory	/workspace/49.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/5.chip_sw_all_escalation_resets.870059838
Short name	T649
Test name
Test status
Simulation time	5767132460 ps
CPU time	699.9 seconds
Started	Apr 23 04:28:17 PM PDT 24
Finished	Apr 23 04:39:58 PM PDT 24
Peak memory	634644 kb
Host	smart-8be4eaf1-a37a-45b4-93ec-6283213b3b3f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 870059838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.870059838
Directory	/workspace/5.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1117450241
Short name	T260
Test name
Test status
Simulation time	5592968088 ps
CPU time	684.89 seconds
Started	Apr 23 04:28:16 PM PDT 24
Finished	Apr 23 04:39:42 PM PDT 24
Peak memory	600840 kb
Host	smart-238b3ac0-98dd-4356-bf98-fa18a5712295
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1117450241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.1117450241
Directory	/workspace/5.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2604113901
Short name	T858
Test name
Test status
Simulation time	5178286121 ps
CPU time	391.01 seconds
Started	Apr 23 04:26:21 PM PDT 24
Finished	Apr 23 04:32:52 PM PDT 24
Peak memory	612744 kb
Host	smart-65c565d4-82cc-4a37-8dac-43d3ab47137f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604113901 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.2604113901
Directory	/workspace/5.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1374783010
Short name	T312
Test name
Test status
Simulation time	8107934098 ps
CPU time	1546.67 seconds
Started	Apr 23 04:28:25 PM PDT 24
Finished	Apr 23 04:54:12 PM PDT 24
Peak memory	607516 kb
Host	smart-cfe51c3a-cdb4-41c5-a757-fb66903d00a2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1374783010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.1374783010
Directory	/workspace/5.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/50.chip_sw_all_escalation_resets.3247655403
Short name	T738
Test name
Test status
Simulation time	5599828866 ps
CPU time	730.18 seconds
Started	Apr 23 04:30:12 PM PDT 24
Finished	Apr 23 04:42:23 PM PDT 24
Peak memory	637624 kb
Host	smart-16b85aec-fac7-4265-8fe2-77d77e071938
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3247655403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.3247655403
Directory	/workspace/50.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.229489280
Short name	T267
Test name
Test status
Simulation time	3993652728 ps
CPU time	334.01 seconds
Started	Apr 23 04:30:30 PM PDT 24
Finished	Apr 23 04:36:04 PM PDT 24
Peak memory	633276 kb
Host	smart-0c2cb593-1c49-4ff3-84a8-d8b5c0ac2f85
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229489280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.229489280
Directory	/workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.4087852066
Short name	T665
Test name
Test status
Simulation time	3763954980 ps
CPU time	289.95 seconds
Started	Apr 23 04:30:27 PM PDT 24
Finished	Apr 23 04:35:17 PM PDT 24
Peak memory	608820 kb
Host	smart-f88b82ba-5300-46a6-8238-a718f50bcea2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087852066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4087852066
Directory	/workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1176955382
Short name	T328
Test name
Test status
Simulation time	5673710568 ps
CPU time	570 seconds
Started	Apr 23 04:33:16 PM PDT 24
Finished	Apr 23 04:42:46 PM PDT 24
Peak memory	634720 kb
Host	smart-037da45d-1f55-4fa7-a76b-44f55dc76650
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1176955382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.1176955382
Directory	/workspace/52.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/53.chip_sw_all_escalation_resets.603841974
Short name	T322
Test name
Test status
Simulation time	4959862952 ps
CPU time	741.22 seconds
Started	Apr 23 04:30:37 PM PDT 24
Finished	Apr 23 04:42:58 PM PDT 24
Peak memory	635856 kb
Host	smart-737f26d8-3440-4629-bcbb-42dc0deb221c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 603841974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.603841974
Directory	/workspace/53.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3563022380
Short name	T751
Test name
Test status
Simulation time	4586430052 ps
CPU time	429.56 seconds
Started	Apr 23 04:32:29 PM PDT 24
Finished	Apr 23 04:39:39 PM PDT 24
Peak memory	633700 kb
Host	smart-d322802f-2f88-4dfb-b574-be6d3f059cb6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563022380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3563022380
Directory	/workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/54.chip_sw_all_escalation_resets.54809679
Short name	T747
Test name
Test status
Simulation time	4751005488 ps
CPU time	515.54 seconds
Started	Apr 23 04:30:32 PM PDT 24
Finished	Apr 23 04:39:08 PM PDT 24
Peak memory	636428 kb
Host	smart-6d8c2233-b289-4bef-8bd1-20eb5184e590
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 54809679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.54809679
Directory	/workspace/54.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2350536747
Short name	T679
Test name
Test status
Simulation time	3342010464 ps
CPU time	379.56 seconds
Started	Apr 23 04:30:44 PM PDT 24
Finished	Apr 23 04:37:04 PM PDT 24
Peak memory	635316 kb
Host	smart-7895a515-cfb7-4f67-9cb9-0cc1a039d096
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350536747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2350536747
Directory	/workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/56.chip_sw_all_escalation_resets.4188552896
Short name	T686
Test name
Test status
Simulation time	4176972960 ps
CPU time	435.15 seconds
Started	Apr 23 04:31:01 PM PDT 24
Finished	Apr 23 04:38:17 PM PDT 24
Peak memory	635424 kb
Host	smart-e2350d85-5fd5-4c70-855f-ba719ed83aaf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4188552896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.4188552896
Directory	/workspace/56.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1442419689
Short name	T731
Test name
Test status
Simulation time	4515924412 ps
CPU time	360.73 seconds
Started	Apr 23 04:31:32 PM PDT 24
Finished	Apr 23 04:37:33 PM PDT 24
Peak memory	633880 kb
Host	smart-46ea119b-f263-4007-97ba-02852d99f4e8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442419689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1442419689
Directory	/workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/57.chip_sw_all_escalation_resets.1734081409
Short name	T680
Test name
Test status
Simulation time	5145350748 ps
CPU time	595.5 seconds
Started	Apr 23 04:31:46 PM PDT 24
Finished	Apr 23 04:41:42 PM PDT 24
Peak memory	635508 kb
Host	smart-bf6d5f90-f869-4a3f-b602-fa02b67c9063
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1734081409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.1734081409
Directory	/workspace/57.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3645143719
Short name	T1154
Test name
Test status
Simulation time	3900569720 ps
CPU time	439.95 seconds
Started	Apr 23 04:31:22 PM PDT 24
Finished	Apr 23 04:38:42 PM PDT 24
Peak memory	633300 kb
Host	smart-b8288cc7-a484-40ae-8cbb-b4a11f213808
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645143719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3645143719
Directory	/workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/58.chip_sw_all_escalation_resets.477001892
Short name	T394
Test name
Test status
Simulation time	5833716280 ps
CPU time	664.63 seconds
Started	Apr 23 04:34:20 PM PDT 24
Finished	Apr 23 04:45:25 PM PDT 24
Peak memory	635544 kb
Host	smart-ad79ef4c-52d3-41f1-b006-c525d8cb80cf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 477001892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.477001892
Directory	/workspace/58.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4102090563
Short name	T93
Test name
Test status
Simulation time	3027182552 ps
CPU time	337.34 seconds
Started	Apr 23 04:32:53 PM PDT 24
Finished	Apr 23 04:38:30 PM PDT 24
Peak memory	634708 kb
Host	smart-b0a85f52-3dde-4c2b-8a9d-9cbe2b04264c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102090563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4102090563
Directory	/workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1882030773
Short name	T933
Test name
Test status
Simulation time	5567448860 ps
CPU time	593.2 seconds
Started	Apr 23 04:31:04 PM PDT 24
Finished	Apr 23 04:40:57 PM PDT 24
Peak memory	636452 kb
Host	smart-6a5a1825-e321-4041-a95c-dee480f27229
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1882030773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.1882030773
Directory	/workspace/59.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3688754667
Short name	T362
Test name
Test status
Simulation time	4632831256 ps
CPU time	559.55 seconds
Started	Apr 23 04:27:15 PM PDT 24
Finished	Apr 23 04:36:35 PM PDT 24
Peak memory	635620 kb
Host	smart-782b4ef6-608f-4096-a5f0-fac794377ca4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688754667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3688754667
Directory	/workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3671424764
Short name	T864
Test name
Test status
Simulation time	6493285488 ps
CPU time	376.15 seconds
Started	Apr 23 04:28:27 PM PDT 24
Finished	Apr 23 04:34:43 PM PDT 24
Peak memory	610732 kb
Host	smart-a5aa2646-81c0-4638-a3b9-0f5c6646aaf6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671424764 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.3671424764
Directory	/workspace/6.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1124459787
Short name	T189
Test name
Test status
Simulation time	13031487192 ps
CPU time	2724.13 seconds
Started	Apr 23 04:27:32 PM PDT 24
Finished	Apr 23 05:12:57 PM PDT 24
Peak memory	607516 kb
Host	smart-db2b3951-9957-4a9f-976f-eb9acb13c1e5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1124459787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1124459787
Directory	/workspace/6.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/60.chip_sw_all_escalation_resets.1725839943
Short name	T725
Test name
Test status
Simulation time	5145943520 ps
CPU time	740.82 seconds
Started	Apr 23 04:31:26 PM PDT 24
Finished	Apr 23 04:43:48 PM PDT 24
Peak memory	637396 kb
Host	smart-7090b739-62be-423b-a95c-324782f6fb88
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1725839943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.1725839943
Directory	/workspace/60.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.401969489
Short name	T288
Test name
Test status
Simulation time	3984699848 ps
CPU time	497.12 seconds
Started	Apr 23 04:35:19 PM PDT 24
Finished	Apr 23 04:43:36 PM PDT 24
Peak memory	634192 kb
Host	smart-8719f92f-ce90-482b-9855-a0a73d437767
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401969489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_s w_alert_handler_lpg_sleep_mode_alerts.401969489
Directory	/workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3239546169
Short name	T289
Test name
Test status
Simulation time	3670151816 ps
CPU time	441.45 seconds
Started	Apr 23 04:31:48 PM PDT 24
Finished	Apr 23 04:39:10 PM PDT 24
Peak memory	634196 kb
Host	smart-2e0046e0-6458-4fbb-877d-314fc7743979
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239546169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3239546169
Directory	/workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/63.chip_sw_all_escalation_resets.881828445
Short name	T269
Test name
Test status
Simulation time	5913786568 ps
CPU time	595.51 seconds
Started	Apr 23 04:31:01 PM PDT 24
Finished	Apr 23 04:40:57 PM PDT 24
Peak memory	635644 kb
Host	smart-eb443d1d-79b5-4a6a-9129-d24ff08279fd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 881828445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.881828445
Directory	/workspace/63.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/64.chip_sw_all_escalation_resets.1950743943
Short name	T103
Test name
Test status
Simulation time	6482437240 ps
CPU time	739.01 seconds
Started	Apr 23 04:35:18 PM PDT 24
Finished	Apr 23 04:47:37 PM PDT 24
Peak memory	635800 kb
Host	smart-e5432cae-d654-4543-bd0c-9bfa6539ea1c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1950743943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.1950743943
Directory	/workspace/64.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828533230
Short name	T653
Test name
Test status
Simulation time	3574365800 ps
CPU time	459.04 seconds
Started	Apr 23 04:35:09 PM PDT 24
Finished	Apr 23 04:42:49 PM PDT 24
Peak memory	635368 kb
Host	smart-32e3345c-5a21-4914-ac29-ba7a21ce2237
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828533230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2828533230
Directory	/workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/66.chip_sw_all_escalation_resets.3681538567
Short name	T329
Test name
Test status
Simulation time	4619075012 ps
CPU time	749.76 seconds
Started	Apr 23 04:34:23 PM PDT 24
Finished	Apr 23 04:46:54 PM PDT 24
Peak memory	635536 kb
Host	smart-d1d6b414-391f-49d3-a417-ca14d51d04d4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3681538567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.3681538567
Directory	/workspace/66.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238325542
Short name	T711
Test name
Test status
Simulation time	3750432744 ps
CPU time	343.88 seconds
Started	Apr 23 04:32:31 PM PDT 24
Finished	Apr 23 04:38:15 PM PDT 24
Peak memory	635340 kb
Host	smart-27451e5c-034e-4865-9958-80df01dfd292
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238325542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3238325542
Directory	/workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/67.chip_sw_all_escalation_resets.4210166057
Short name	T330
Test name
Test status
Simulation time	4912611800 ps
CPU time	670.66 seconds
Started	Apr 23 04:32:16 PM PDT 24
Finished	Apr 23 04:43:27 PM PDT 24
Peak memory	637900 kb
Host	smart-1298b7de-7fdf-41e3-bbc5-c1806b1bd837
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4210166057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.4210166057
Directory	/workspace/67.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2594993776
Short name	T1172
Test name
Test status
Simulation time	3924105368 ps
CPU time	424.86 seconds
Started	Apr 23 04:32:16 PM PDT 24
Finished	Apr 23 04:39:21 PM PDT 24
Peak memory	633220 kb
Host	smart-b76728f9-00ea-4c14-a202-4e6f9b56ca10
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594993776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2594993776
Directory	/workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/69.chip_sw_all_escalation_resets.2676006804
Short name	T699
Test name
Test status
Simulation time	4461285800 ps
CPU time	531.8 seconds
Started	Apr 23 04:33:11 PM PDT 24
Finished	Apr 23 04:42:03 PM PDT 24
Peak memory	637672 kb
Host	smart-f6c5e81b-c034-4331-a704-6be3d6a30b13
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2676006804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.2676006804
Directory	/workspace/69.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/7.chip_sw_all_escalation_resets.2872847499
Short name	T284
Test name
Test status
Simulation time	4695423926 ps
CPU time	645.5 seconds
Started	Apr 23 04:28:52 PM PDT 24
Finished	Apr 23 04:39:38 PM PDT 24
Peak memory	637764 kb
Host	smart-a33892f8-141a-41f2-ae64-0bb02e8a8329
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2872847499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2872847499
Directory	/workspace/7.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2877453330
Short name	T1072
Test name
Test status
Simulation time	7155622977 ps
CPU time	564.98 seconds
Started	Apr 23 04:26:27 PM PDT 24
Finished	Apr 23 04:35:53 PM PDT 24
Peak memory	612692 kb
Host	smart-2221feda-f7ae-40ad-bd4d-2d89f9e125ac
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877453330 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2877453330
Directory	/workspace/7.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2564792484
Short name	T1066
Test name
Test status
Simulation time	4954156840 ps
CPU time	604.99 seconds
Started	Apr 23 04:29:01 PM PDT 24
Finished	Apr 23 04:39:06 PM PDT 24
Peak memory	607488 kb
Host	smart-56a68a82-cf24-4115-911c-9b6478769384
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2564792484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2564792484
Directory	/workspace/7.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/70.chip_sw_all_escalation_resets.613329672
Short name	T746
Test name
Test status
Simulation time	5043334970 ps
CPU time	560.71 seconds
Started	Apr 23 04:32:02 PM PDT 24
Finished	Apr 23 04:41:23 PM PDT 24
Peak memory	635524 kb
Host	smart-36f6830f-1bd2-4bb7-9552-2e6219f2df0c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 613329672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.613329672
Directory	/workspace/70.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2185456361
Short name	T94
Test name
Test status
Simulation time	3769415752 ps
CPU time	377.54 seconds
Started	Apr 23 04:31:57 PM PDT 24
Finished	Apr 23 04:38:15 PM PDT 24
Peak memory	634540 kb
Host	smart-4bd1cd65-b527-4001-918f-c34cbfd6704a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185456361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2185456361
Directory	/workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/71.chip_sw_all_escalation_resets.902987867
Short name	T870
Test name
Test status
Simulation time	4801196810 ps
CPU time	587.22 seconds
Started	Apr 23 04:36:11 PM PDT 24
Finished	Apr 23 04:45:59 PM PDT 24
Peak memory	608744 kb
Host	smart-32820e9c-aacf-476d-9226-71638a5832c7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 902987867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.902987867
Directory	/workspace/71.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/72.chip_sw_all_escalation_resets.679373310
Short name	T654
Test name
Test status
Simulation time	4715298836 ps
CPU time	607.14 seconds
Started	Apr 23 04:32:10 PM PDT 24
Finished	Apr 23 04:42:18 PM PDT 24
Peak memory	637608 kb
Host	smart-6960f986-e69b-4554-9926-df8b2937dd4c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 679373310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.679373310
Directory	/workspace/72.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1745128909
Short name	T722
Test name
Test status
Simulation time	3693583424 ps
CPU time	367.98 seconds
Started	Apr 23 04:33:39 PM PDT 24
Finished	Apr 23 04:39:48 PM PDT 24
Peak memory	633640 kb
Host	smart-d74c0c62-fc71-4469-9bd5-7afcb0f5ef91
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745128909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1745128909
Directory	/workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/74.chip_sw_all_escalation_resets.1985353989
Short name	T717
Test name
Test status
Simulation time	6235711506 ps
CPU time	683.44 seconds
Started	Apr 23 04:31:05 PM PDT 24
Finished	Apr 23 04:42:29 PM PDT 24
Peak memory	635544 kb
Host	smart-b08dcbb2-3f04-4bb2-a365-b0f964bec084
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1985353989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1985353989
Directory	/workspace/74.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1204111325
Short name	T709
Test name
Test status
Simulation time	3559130680 ps
CPU time	399.58 seconds
Started	Apr 23 04:37:37 PM PDT 24
Finished	Apr 23 04:44:17 PM PDT 24
Peak memory	635500 kb
Host	smart-3161ab8a-fa23-46ba-b889-f88cd303908e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204111325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1204111325
Directory	/workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/75.chip_sw_all_escalation_resets.3992115950
Short name	T697
Test name
Test status
Simulation time	4807969180 ps
CPU time	558.64 seconds
Started	Apr 23 04:33:13 PM PDT 24
Finished	Apr 23 04:42:33 PM PDT 24
Peak memory	635812 kb
Host	smart-d8d1f676-e90b-4e2d-8a04-071ba412bc98
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3992115950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.3992115950
Directory	/workspace/75.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1848037085
Short name	T727
Test name
Test status
Simulation time	3540510732 ps
CPU time	312 seconds
Started	Apr 23 04:36:58 PM PDT 24
Finished	Apr 23 04:42:10 PM PDT 24
Peak memory	633300 kb
Host	smart-d4b020c0-9c1a-4f34-a4f3-313a11486273
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848037085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1848037085
Directory	/workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/76.chip_sw_all_escalation_resets.1302092986
Short name	T735
Test name
Test status
Simulation time	4626294630 ps
CPU time	564.92 seconds
Started	Apr 23 04:37:08 PM PDT 24
Finished	Apr 23 04:46:34 PM PDT 24
Peak memory	635592 kb
Host	smart-e3d12d50-0b6b-4aa2-afdc-160908466c18
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1302092986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1302092986
Directory	/workspace/76.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/77.chip_sw_all_escalation_resets.1994997520
Short name	T720
Test name
Test status
Simulation time	4240339400 ps
CPU time	640.91 seconds
Started	Apr 23 04:36:56 PM PDT 24
Finished	Apr 23 04:47:38 PM PDT 24
Peak memory	634288 kb
Host	smart-9d3b3e0f-614f-40d1-918a-f856009bf9c4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1994997520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1994997520
Directory	/workspace/77.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3231991920
Short name	T662
Test name
Test status
Simulation time	3610974270 ps
CPU time	334.61 seconds
Started	Apr 23 04:33:37 PM PDT 24
Finished	Apr 23 04:39:12 PM PDT 24
Peak memory	633476 kb
Host	smart-08a75281-d05e-4831-a932-943ea62702bc
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231991920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3231991920
Directory	/workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1960906832
Short name	T694
Test name
Test status
Simulation time	4204761564 ps
CPU time	551.06 seconds
Started	Apr 23 04:32:55 PM PDT 24
Finished	Apr 23 04:42:07 PM PDT 24
Peak memory	634600 kb
Host	smart-300ee1f1-4ed9-4819-8973-648df942d448
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1960906832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1960906832
Directory	/workspace/78.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2991265457
Short name	T989
Test name
Test status
Simulation time	3042404072 ps
CPU time	397.44 seconds
Started	Apr 23 04:31:45 PM PDT 24
Finished	Apr 23 04:38:23 PM PDT 24
Peak memory	633352 kb
Host	smart-426e98fe-ca52-47c3-ad7a-055a725c81a1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991265457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2991265457
Directory	/workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1598074245
Short name	T398
Test name
Test status
Simulation time	4856479022 ps
CPU time	705.69 seconds
Started	Apr 23 04:31:43 PM PDT 24
Finished	Apr 23 04:43:29 PM PDT 24
Peak memory	635772 kb
Host	smart-68c1fa4e-3ea8-42f8-966e-9a07c6eca04a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1598074245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1598074245
Directory	/workspace/79.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1570876830
Short name	T682
Test name
Test status
Simulation time	3820125120 ps
CPU time	378.54 seconds
Started	Apr 23 04:26:56 PM PDT 24
Finished	Apr 23 04:33:15 PM PDT 24
Peak memory	633384 kb
Host	smart-21627f23-8df3-4c30-b94a-fa1df205e3a1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570876830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.1570876830
Directory	/workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1005605302
Short name	T923
Test name
Test status
Simulation time	3354244908 ps
CPU time	503.24 seconds
Started	Apr 23 04:29:01 PM PDT 24
Finished	Apr 23 04:37:25 PM PDT 24
Peak memory	607484 kb
Host	smart-75583e67-1ade-4231-82f1-951cca768831
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1005605302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.1005605302
Directory	/workspace/8.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.663088579
Short name	T659
Test name
Test status
Simulation time	4438518352 ps
CPU time	351.31 seconds
Started	Apr 23 04:33:06 PM PDT 24
Finished	Apr 23 04:38:58 PM PDT 24
Peak memory	633776 kb
Host	smart-e3eceec1-26a1-43db-8b65-0fe697ae1b6f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663088579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s w_alert_handler_lpg_sleep_mode_alerts.663088579
Directory	/workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/80.chip_sw_all_escalation_resets.102383282
Short name	T706
Test name
Test status
Simulation time	6009072668 ps
CPU time	651.75 seconds
Started	Apr 23 04:35:54 PM PDT 24
Finished	Apr 23 04:46:46 PM PDT 24
Peak memory	635696 kb
Host	smart-5a71ff98-2495-4cd5-94a2-5de9fe3c1973
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 102383282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.102383282
Directory	/workspace/80.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2429521875
Short name	T678
Test name
Test status
Simulation time	3293467756 ps
CPU time	274.62 seconds
Started	Apr 23 04:33:02 PM PDT 24
Finished	Apr 23 04:37:37 PM PDT 24
Peak memory	633428 kb
Host	smart-cfe74846-8efc-4ab2-911f-05609489184b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429521875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2429521875
Directory	/workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3000338181
Short name	T169
Test name
Test status
Simulation time	5249626192 ps
CPU time	521.06 seconds
Started	Apr 23 04:33:06 PM PDT 24
Finished	Apr 23 04:41:48 PM PDT 24
Peak memory	606776 kb
Host	smart-2ae8e1c1-eec0-4fe3-bfe1-754042be3381
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3000338181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3000338181
Directory	/workspace/81.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2972735925
Short name	T229
Test name
Test status
Simulation time	4198776744 ps
CPU time	331.39 seconds
Started	Apr 23 04:33:36 PM PDT 24
Finished	Apr 23 04:39:08 PM PDT 24
Peak memory	633376 kb
Host	smart-69410ac1-eae3-4de7-8107-2534b6f85fea
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972735925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2972735925
Directory	/workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3514881626
Short name	T400
Test name
Test status
Simulation time	4206547032 ps
CPU time	347.15 seconds
Started	Apr 23 04:32:49 PM PDT 24
Finished	Apr 23 04:38:37 PM PDT 24
Peak memory	633316 kb
Host	smart-8d384b52-35ac-4b83-a0ce-f4f6b820dfd8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514881626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3514881626
Directory	/workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/83.chip_sw_all_escalation_resets.2413113675
Short name	T684
Test name
Test status
Simulation time	4794740136 ps
CPU time	555.38 seconds
Started	Apr 23 04:31:35 PM PDT 24
Finished	Apr 23 04:40:51 PM PDT 24
Peak memory	635536 kb
Host	smart-1eee8521-6314-4579-832d-916ddeebfad3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2413113675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.2413113675
Directory	/workspace/83.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1808415202
Short name	T672
Test name
Test status
Simulation time	3504640622 ps
CPU time	336.07 seconds
Started	Apr 23 04:38:43 PM PDT 24
Finished	Apr 23 04:44:20 PM PDT 24
Peak memory	633272 kb
Host	smart-00de870c-cf4a-491a-8d72-7993f4e65de6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808415202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1808415202
Directory	/workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/84.chip_sw_all_escalation_resets.3599671775
Short name	T688
Test name
Test status
Simulation time	6440256024 ps
CPU time	526.27 seconds
Started	Apr 23 04:33:34 PM PDT 24
Finished	Apr 23 04:42:21 PM PDT 24
Peak memory	635592 kb
Host	smart-fc78a845-788a-4262-ade0-e919ac3f2ddc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3599671775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3599671775
Directory	/workspace/84.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1356723818
Short name	T719
Test name
Test status
Simulation time	3914173768 ps
CPU time	377.5 seconds
Started	Apr 23 04:32:38 PM PDT 24
Finished	Apr 23 04:38:56 PM PDT 24
Peak memory	635556 kb
Host	smart-14e0d9a8-899a-4408-bf15-d82926e8db89
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356723818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1356723818
Directory	/workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.244625262
Short name	T716
Test name
Test status
Simulation time	4049376656 ps
CPU time	379.04 seconds
Started	Apr 23 04:32:27 PM PDT 24
Finished	Apr 23 04:38:46 PM PDT 24
Peak memory	635240 kb
Host	smart-3db80d89-271f-4fd4-9be3-8b6364055273
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244625262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_s w_alert_handler_lpg_sleep_mode_alerts.244625262
Directory	/workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/86.chip_sw_all_escalation_resets.1821632277
Short name	T681
Test name
Test status
Simulation time	4917865424 ps
CPU time	521.12 seconds
Started	Apr 23 04:31:37 PM PDT 24
Finished	Apr 23 04:40:18 PM PDT 24
Peak memory	635600 kb
Host	smart-b8cb7d1b-3350-45e5-a96b-ce5235eecba3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1821632277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.1821632277
Directory	/workspace/86.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.476549646
Short name	T287
Test name
Test status
Simulation time	3682597240 ps
CPU time	322.06 seconds
Started	Apr 23 04:33:18 PM PDT 24
Finished	Apr 23 04:38:41 PM PDT 24
Peak memory	634144 kb
Host	smart-887725ad-2fff-4a04-b34d-231676ed8db3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476549646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.476549646
Directory	/workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3565994203
Short name	T241
Test name
Test status
Simulation time	4952820664 ps
CPU time	604.21 seconds
Started	Apr 23 04:32:13 PM PDT 24
Finished	Apr 23 04:42:18 PM PDT 24
Peak memory	636256 kb
Host	smart-380b736f-0bd4-4be3-a06e-5d8a429462a5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3565994203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.3565994203
Directory	/workspace/87.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2756254041
Short name	T693
Test name
Test status
Simulation time	3237403468 ps
CPU time	337.23 seconds
Started	Apr 23 04:32:22 PM PDT 24
Finished	Apr 23 04:37:59 PM PDT 24
Peak memory	633632 kb
Host	smart-b9e3d575-7087-4318-b485-9c8e10656333
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756254041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2756254041
Directory	/workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/88.chip_sw_all_escalation_resets.2599948826
Short name	T700
Test name
Test status
Simulation time	5066774770 ps
CPU time	588 seconds
Started	Apr 23 04:32:48 PM PDT 24
Finished	Apr 23 04:42:37 PM PDT 24
Peak memory	634720 kb
Host	smart-8c382d9e-e0bb-4124-94d1-bc1dc5a9cffd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2599948826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.2599948826
Directory	/workspace/88.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/89.chip_sw_all_escalation_resets.1365108938
Short name	T675
Test name
Test status
Simulation time	5985836328 ps
CPU time	711.4 seconds
Started	Apr 23 04:32:28 PM PDT 24
Finished	Apr 23 04:44:20 PM PDT 24
Peak memory	635548 kb
Host	smart-ba44cb24-221d-40b2-a361-374c9afd24c4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1365108938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1365108938
Directory	/workspace/89.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1054038136
Short name	T701
Test name
Test status
Simulation time	3596332024 ps
CPU time	316.62 seconds
Started	Apr 23 04:28:18 PM PDT 24
Finished	Apr 23 04:33:35 PM PDT 24
Peak memory	633600 kb
Host	smart-68841388-27a7-42a6-a948-cc291174b12e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054038136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.1054038136
Directory	/workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/9.chip_sw_all_escalation_resets.446472133
Short name	T1192
Test name
Test status
Simulation time	4668001310 ps
CPU time	557.49 seconds
Started	Apr 23 04:28:49 PM PDT 24
Finished	Apr 23 04:38:07 PM PDT 24
Peak memory	635960 kb
Host	smart-67f48b3f-71b4-405d-9d70-6c35e5560df2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 446472133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.446472133
Directory	/workspace/9.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2620416921
Short name	T1166
Test name
Test status
Simulation time	9940487492 ps
CPU time	656.67 seconds
Started	Apr 23 04:28:48 PM PDT 24
Finished	Apr 23 04:39:46 PM PDT 24
Peak memory	611752 kb
Host	smart-b5ac38d1-60c8-4226-9bb7-f28c2043d217
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620416921 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.2620416921
Directory	/workspace/9.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3067000475
Short name	T258
Test name
Test status
Simulation time	8498534152 ps
CPU time	1571.33 seconds
Started	Apr 23 04:28:49 PM PDT 24
Finished	Apr 23 04:55:01 PM PDT 24
Peak memory	607456 kb
Host	smart-4459bdd5-24a5-4dc7-8274-67521271909e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3067000475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3067000475
Directory	/workspace/9.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3831315905
Short name	T273
Test name
Test status
Simulation time	5758596640 ps
CPU time	648.52 seconds
Started	Apr 23 04:32:40 PM PDT 24
Finished	Apr 23 04:43:29 PM PDT 24
Peak memory	606708 kb
Host	smart-8141f56f-a313-4e0e-a3ef-ecb6be331c2e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3831315905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3831315905
Directory	/workspace/90.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1432638633
Short name	T932
Test name
Test status
Simulation time	4200437800 ps
CPU time	564.05 seconds
Started	Apr 23 04:32:39 PM PDT 24
Finished	Apr 23 04:42:04 PM PDT 24
Peak memory	636464 kb
Host	smart-ed1ea615-5aa0-4e62-85c8-0faa3465ebe3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1432638633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.1432638633
Directory	/workspace/91.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2395712830
Short name	T726
Test name
Test status
Simulation time	4412346696 ps
CPU time	535.93 seconds
Started	Apr 23 04:34:09 PM PDT 24
Finished	Apr 23 04:43:05 PM PDT 24
Peak memory	635656 kb
Host	smart-ed748cf5-cb25-4c1d-8f70-41c26feaa41e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2395712830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2395712830
Directory	/workspace/92.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/93.chip_sw_all_escalation_resets.1556082462
Short name	T274
Test name
Test status
Simulation time	4473246624 ps
CPU time	529.63 seconds
Started	Apr 23 04:32:54 PM PDT 24
Finished	Apr 23 04:41:44 PM PDT 24
Peak memory	635644 kb
Host	smart-893f0f6e-a016-413a-b7c1-cc7e6f4a4f88
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1556082462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.1556082462
Directory	/workspace/93.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/94.chip_sw_all_escalation_resets.3797800597
Short name	T743
Test name
Test status
Simulation time	5004021734 ps
CPU time	585.28 seconds
Started	Apr 23 04:37:39 PM PDT 24
Finished	Apr 23 04:47:25 PM PDT 24
Peak memory	634508 kb
Host	smart-597c1f8a-3fb6-41f0-949f-210be9b960e7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3797800597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.3797800597
Directory	/workspace/94.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2178182138
Short name	T663
Test name
Test status
Simulation time	4456300258 ps
CPU time	507.96 seconds
Started	Apr 23 04:32:55 PM PDT 24
Finished	Apr 23 04:41:23 PM PDT 24
Peak memory	635568 kb
Host	smart-993deef0-eab3-4cfb-83ca-9992106d31fb
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2178182138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2178182138
Directory	/workspace/95.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/96.chip_sw_all_escalation_resets.863482999
Short name	T619
Test name
Test status
Simulation time	5479156756 ps
CPU time	690.33 seconds
Started	Apr 23 04:32:56 PM PDT 24
Finished	Apr 23 04:44:27 PM PDT 24
Peak memory	601380 kb
Host	smart-542e0aad-4197-4172-b397-c94f89b8cfe8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 863482999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.863482999
Directory	/workspace/96.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/97.chip_sw_all_escalation_resets.2483835885
Short name	T386
Test name
Test status
Simulation time	5223767712 ps
CPU time	731.2 seconds
Started	Apr 23 04:33:21 PM PDT 24
Finished	Apr 23 04:45:33 PM PDT 24
Peak memory	635568 kb
Host	smart-9e5cc339-3bd9-4354-82fd-e6ef9227ff8c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2483835885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.2483835885
Directory	/workspace/97.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/99.chip_sw_all_escalation_resets.3003198019
Short name	T1079
Test name
Test status
Simulation time	5067181908 ps
CPU time	443.01 seconds
Started	Apr 23 04:36:03 PM PDT 24
Finished	Apr 23 04:43:26 PM PDT 24
Peak memory	606728 kb
Host	smart-99811e2b-a7c4-49a9-b5cc-686e7b0ffd7a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3003198019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3003198019
Directory	/workspace/99.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2789086550
Short name	T645
Test name
Test status
Simulation time	4322308015 ps
CPU time	271.01 seconds
Started	Apr 23 04:25:38 PM PDT 24
Finished	Apr 23 04:30:10 PM PDT 24
Peak memory	635220 kb
Host	smart-c8dc563f-567b-458e-87bd-4c49efe42938
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789086550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.2789086550
Directory	/workspace/0.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.858610949
Short name	T30
Test name
Test status
Simulation time	5405453488 ps
CPU time	280.32 seconds
Started	Apr 23 04:25:50 PM PDT 24
Finished	Apr 23 04:30:31 PM PDT 24
Peak memory	636620 kb
Host	smart-9026c350-e381-4347-a788-acae9b6daeaa
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858610949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 1.chip_padctrl_attributes.858610949
Directory	/workspace/1.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.35651055
Short name	T2799
Test name
Test status
Simulation time	5069688040 ps
CPU time	280.91 seconds
Started	Apr 23 04:25:59 PM PDT 24
Finished	Apr 23 04:30:40 PM PDT 24
Peak memory	636960 kb
Host	smart-a8c6084d-72ce-4782-90d9-e41351e06ee4
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35651055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 2.chip_padctrl_attributes.35651055
Directory	/workspace/2.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3183999799
Short name	T2800
Test name
Test status
Simulation time	4748290343 ps
CPU time	349.11 seconds
Started	Apr 23 04:25:47 PM PDT 24
Finished	Apr 23 04:31:36 PM PDT 24
Peak memory	638044 kb
Host	smart-2282e170-b57e-4985-8313-00a3169b1a0d
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183999799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.3183999799
Directory	/workspace/4.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2074662544
Short name	T644
Test name
Test status
Simulation time	4189662075 ps
CPU time	262.69 seconds
Started	Apr 23 04:25:42 PM PDT 24
Finished	Apr 23 04:30:05 PM PDT 24
Peak memory	638072 kb
Host	smart-a65a508c-52f7-44a0-ba34-e09909dd387c
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074662544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.2074662544
Directory	/workspace/5.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3030938053
Short name	T36
Test name
Test status
Simulation time	4698994216 ps
CPU time	274.38 seconds
Started	Apr 23 04:25:54 PM PDT 24
Finished	Apr 23 04:30:29 PM PDT 24
Peak memory	638056 kb
Host	smart-3059c118-f49f-45c3-b204-4e653a485d5c
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030938053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.3030938053
Directory	/workspace/6.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2432755227
Short name	T29
Test name
Test status
Simulation time	4448985670 ps
CPU time	365.16 seconds
Started	Apr 23 04:26:07 PM PDT 24
Finished	Apr 23 04:32:12 PM PDT 24
Peak memory	637392 kb
Host	smart-f480453e-adaa-4dbe-ac8a-f1e62259c2a0
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432755227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.2432755227
Directory	/workspace/7.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3312009108
Short name	T2797
Test name
Test status
Simulation time	5117607558 ps
CPU time	337.65 seconds
Started	Apr 23 04:25:45 PM PDT 24
Finished	Apr 23 04:31:23 PM PDT 24
Peak memory	638028 kb
Host	smart-96acf60a-bb0b-43dd-b83b-681ca3f579b5
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312009108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.3312009108
Directory	/workspace/8.chip_padctrl_attributes/latest