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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.00 95.29 93.69 95.62 94.41 97.38 99.59


Total test records in report: 2800
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T1121 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3483825702 Apr 23 03:52:54 PM PDT 24 Apr 23 03:57:13 PM PDT 24 2920116773 ps
T712 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3910494045 Apr 23 04:29:20 PM PDT 24 Apr 23 04:36:51 PM PDT 24 3735622496 ps
T1122 /workspace/coverage/default/2.chip_sw_kmac_entropy.1504776438 Apr 23 04:16:59 PM PDT 24 Apr 23 04:20:03 PM PDT 24 2795191708 ps
T1123 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2171156634 Apr 23 04:24:07 PM PDT 24 Apr 23 04:31:24 PM PDT 24 4041326564 ps
T1124 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2403363485 Apr 23 04:20:40 PM PDT 24 Apr 23 04:30:07 PM PDT 24 5925697440 ps
T157 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.4219168 Apr 23 04:15:38 PM PDT 24 Apr 23 07:27:49 PM PDT 24 59854164200 ps
T139 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1227169991 Apr 23 04:10:04 PM PDT 24 Apr 23 04:19:33 PM PDT 24 5548915420 ps
T640 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1405813216 Apr 23 03:52:34 PM PDT 24 Apr 23 04:03:37 PM PDT 24 4661816840 ps
T1125 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4050813466 Apr 23 04:11:50 PM PDT 24 Apr 23 04:15:47 PM PDT 24 3694344639 ps
T1126 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1261845369 Apr 23 04:05:11 PM PDT 24 Apr 23 04:14:27 PM PDT 24 4586560216 ps
T1127 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1979126433 Apr 23 04:25:28 PM PDT 24 Apr 23 04:36:21 PM PDT 24 4120727750 ps
T1128 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1541130383 Apr 23 04:04:43 PM PDT 24 Apr 23 05:28:44 PM PDT 24 49399582420 ps
T1129 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1849990048 Apr 23 04:22:25 PM PDT 24 Apr 23 04:29:45 PM PDT 24 4999727546 ps
T1130 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1507007255 Apr 23 04:17:30 PM PDT 24 Apr 23 04:25:58 PM PDT 24 7494254480 ps
T1131 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4011068405 Apr 23 04:15:29 PM PDT 24 Apr 23 04:38:29 PM PDT 24 8896484826 ps
T650 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.906431928 Apr 23 04:31:58 PM PDT 24 Apr 23 04:39:25 PM PDT 24 4009156088 ps
T1132 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2233073990 Apr 23 03:53:23 PM PDT 24 Apr 23 04:02:08 PM PDT 24 5043942248 ps
T1133 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3130629359 Apr 23 04:07:03 PM PDT 24 Apr 23 04:13:57 PM PDT 24 3372479100 ps
T244 /workspace/coverage/default/11.chip_sw_all_escalation_resets.661241937 Apr 23 04:28:57 PM PDT 24 Apr 23 04:40:32 PM PDT 24 5505077982 ps
T1134 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2663524636 Apr 23 04:27:09 PM PDT 24 Apr 23 04:32:29 PM PDT 24 3773341598 ps
T140 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.296391611 Apr 23 04:26:18 PM PDT 24 Apr 23 04:38:42 PM PDT 24 6286015728 ps
T95 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770713062 Apr 23 04:30:23 PM PDT 24 Apr 23 04:36:00 PM PDT 24 2823955400 ps
T1135 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2356594841 Apr 23 04:23:48 PM PDT 24 Apr 23 04:33:04 PM PDT 24 4630852472 ps
T1136 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.27389009 Apr 23 03:55:18 PM PDT 24 Apr 23 04:03:01 PM PDT 24 9929849572 ps
T1137 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3047981293 Apr 23 03:52:53 PM PDT 24 Apr 23 03:58:51 PM PDT 24 2750924530 ps
T1138 /workspace/coverage/default/0.chip_sival_flash_info_access.1326822180 Apr 23 03:50:12 PM PDT 24 Apr 23 03:53:59 PM PDT 24 2553763710 ps
T1139 /workspace/coverage/default/0.chip_sw_usbdev_dpi.3859295215 Apr 23 03:49:49 PM PDT 24 Apr 23 04:40:16 PM PDT 24 12649474884 ps
T1140 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3989132742 Apr 23 04:24:31 PM PDT 24 Apr 23 04:33:42 PM PDT 24 3857103272 ps
T1141 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3224693621 Apr 23 04:14:31 PM PDT 24 Apr 23 04:20:04 PM PDT 24 2881099492 ps
T741 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020330562 Apr 23 04:36:43 PM PDT 24 Apr 23 04:45:00 PM PDT 24 3676717560 ps
T1142 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2708000791 Apr 23 04:06:35 PM PDT 24 Apr 23 04:12:40 PM PDT 24 3431400668 ps
T1143 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.518202131 Apr 23 04:23:48 PM PDT 24 Apr 23 04:33:12 PM PDT 24 4775701696 ps
T714 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4282789989 Apr 23 04:28:12 PM PDT 24 Apr 23 04:34:52 PM PDT 24 3485062144 ps
T738 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3247655403 Apr 23 04:30:12 PM PDT 24 Apr 23 04:42:23 PM PDT 24 5599828866 ps
T1144 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3493714330 Apr 23 04:25:14 PM PDT 24 Apr 23 04:29:10 PM PDT 24 2917557183 ps
T615 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3780442541 Apr 23 03:53:08 PM PDT 24 Apr 23 04:01:17 PM PDT 24 2739391220 ps
T1145 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2843485437 Apr 23 03:51:42 PM PDT 24 Apr 23 04:07:53 PM PDT 24 8540569220 ps
T700 /workspace/coverage/default/88.chip_sw_all_escalation_resets.2599948826 Apr 23 04:32:48 PM PDT 24 Apr 23 04:42:37 PM PDT 24 5066774770 ps
T1146 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3330867095 Apr 23 04:15:22 PM PDT 24 Apr 23 04:34:17 PM PDT 24 6047420122 ps
T1147 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2128924107 Apr 23 04:08:57 PM PDT 24 Apr 23 05:12:36 PM PDT 24 16756113246 ps
T118 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1773619234 Apr 23 04:25:23 PM PDT 24 Apr 23 05:26:02 PM PDT 24 20299325930 ps
T1148 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1351917010 Apr 23 04:08:49 PM PDT 24 Apr 23 04:15:54 PM PDT 24 3982397296 ps
T315 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1975858012 Apr 23 03:52:03 PM PDT 24 Apr 23 04:04:18 PM PDT 24 5513728962 ps
T1149 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2063723704 Apr 23 04:21:50 PM PDT 24 Apr 23 04:28:13 PM PDT 24 4099372843 ps
T1150 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1858035433 Apr 23 04:22:16 PM PDT 24 Apr 23 04:26:02 PM PDT 24 2600772504 ps
T1151 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1443562046 Apr 23 04:08:52 PM PDT 24 Apr 23 04:17:14 PM PDT 24 3663773608 ps
T1152 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1156410326 Apr 23 04:13:59 PM PDT 24 Apr 23 04:19:50 PM PDT 24 3201542888 ps
T1153 /workspace/coverage/default/0.chip_sw_kmac_app_rom.391056555 Apr 23 03:53:01 PM PDT 24 Apr 23 03:56:14 PM PDT 24 2905909560 ps
T707 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607150158 Apr 23 04:29:59 PM PDT 24 Apr 23 04:39:32 PM PDT 24 4234662528 ps
T629 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2859075841 Apr 23 03:54:01 PM PDT 24 Apr 23 03:58:26 PM PDT 24 3074162462 ps
T1154 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3645143719 Apr 23 04:31:22 PM PDT 24 Apr 23 04:38:42 PM PDT 24 3900569720 ps
T1155 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2152363044 Apr 23 04:09:07 PM PDT 24 Apr 23 04:13:18 PM PDT 24 3813910056 ps
T1156 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1033263818 Apr 23 03:55:52 PM PDT 24 Apr 23 03:59:56 PM PDT 24 2969252187 ps
T1157 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2509948982 Apr 23 04:01:26 PM PDT 24 Apr 23 04:04:48 PM PDT 24 2416205508 ps
T655 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.445782987 Apr 23 04:32:57 PM PDT 24 Apr 23 04:39:16 PM PDT 24 4324460280 ps
T42 /workspace/coverage/default/1.chip_sw_spi_device_tpm.4091909030 Apr 23 04:04:10 PM PDT 24 Apr 23 04:09:04 PM PDT 24 3707504487 ps
T269 /workspace/coverage/default/63.chip_sw_all_escalation_resets.881828445 Apr 23 04:31:01 PM PDT 24 Apr 23 04:40:57 PM PDT 24 5913786568 ps
T1158 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.4240992434 Apr 23 04:28:22 PM PDT 24 Apr 23 04:35:45 PM PDT 24 3900463784 ps
T327 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4029130293 Apr 23 04:16:26 PM PDT 24 Apr 23 04:29:00 PM PDT 24 5129881612 ps
T280 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2081063418 Apr 23 04:10:06 PM PDT 24 Apr 23 04:28:21 PM PDT 24 9816095355 ps
T1159 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.964202291 Apr 23 04:19:03 PM PDT 24 Apr 23 04:33:08 PM PDT 24 5430226496 ps
T1160 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3200429258 Apr 23 04:31:03 PM PDT 24 Apr 23 04:37:29 PM PDT 24 3684704328 ps
T1161 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2778789652 Apr 23 04:06:55 PM PDT 24 Apr 23 04:08:39 PM PDT 24 2609742572 ps
T1162 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3177475273 Apr 23 04:24:51 PM PDT 24 Apr 23 04:32:53 PM PDT 24 5117796406 ps
T289 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3239546169 Apr 23 04:31:48 PM PDT 24 Apr 23 04:39:10 PM PDT 24 3670151816 ps
T717 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1985353989 Apr 23 04:31:05 PM PDT 24 Apr 23 04:42:29 PM PDT 24 6235711506 ps
T1163 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3790562616 Apr 23 04:26:31 PM PDT 24 Apr 23 04:37:00 PM PDT 24 4690497152 ps
T1164 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3246258831 Apr 23 04:15:43 PM PDT 24 Apr 23 04:26:27 PM PDT 24 4479806665 ps
T1165 /workspace/coverage/default/1.chip_sw_flash_init.3009620210 Apr 23 04:06:29 PM PDT 24 Apr 23 04:45:01 PM PDT 24 25383364850 ps
T1166 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2620416921 Apr 23 04:28:48 PM PDT 24 Apr 23 04:39:46 PM PDT 24 9940487492 ps
T374 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2736964842 Apr 23 04:11:24 PM PDT 24 Apr 23 04:17:30 PM PDT 24 7410038262 ps
T1167 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.303486062 Apr 23 04:29:16 PM PDT 24 Apr 23 05:10:02 PM PDT 24 12672314246 ps
T73 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3716832662 Apr 23 03:54:45 PM PDT 24 Apr 23 04:08:14 PM PDT 24 8939546908 ps
T1168 /workspace/coverage/default/2.chip_sw_all_escalation_resets.2764823654 Apr 23 04:14:56 PM PDT 24 Apr 23 04:26:08 PM PDT 24 5901136148 ps
T375 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3574245690 Apr 23 04:25:11 PM PDT 24 Apr 23 04:48:03 PM PDT 24 20219534000 ps
T1169 /workspace/coverage/default/0.rom_keymgr_functest.1900012538 Apr 23 04:01:15 PM PDT 24 Apr 23 04:09:16 PM PDT 24 5532773720 ps
T1170 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3125064395 Apr 23 04:23:09 PM PDT 24 Apr 23 04:32:18 PM PDT 24 5275287968 ps
T1171 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2831850945 Apr 23 04:24:29 PM PDT 24 Apr 23 04:35:14 PM PDT 24 4211941088 ps
T1172 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2594993776 Apr 23 04:32:16 PM PDT 24 Apr 23 04:39:21 PM PDT 24 3924105368 ps
T1173 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.661892807 Apr 23 03:52:53 PM PDT 24 Apr 23 03:55:58 PM PDT 24 2602905500 ps
T731 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1442419689 Apr 23 04:31:32 PM PDT 24 Apr 23 04:37:33 PM PDT 24 4515924412 ps
T1174 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.4127539529 Apr 23 04:24:08 PM PDT 24 Apr 23 04:53:29 PM PDT 24 23792619329 ps
T307 /workspace/coverage/default/2.chip_plic_all_irqs_0.3713998389 Apr 23 04:24:28 PM PDT 24 Apr 23 04:46:33 PM PDT 24 6699391424 ps
T1175 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3987480989 Apr 23 04:18:18 PM PDT 24 Apr 23 04:24:41 PM PDT 24 3214334550 ps
T1176 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3386483910 Apr 23 04:06:00 PM PDT 24 Apr 23 04:26:33 PM PDT 24 7714942280 ps
T1177 /workspace/coverage/default/2.chip_sw_example_concurrency.4050390138 Apr 23 04:19:40 PM PDT 24 Apr 23 04:22:57 PM PDT 24 2581028798 ps
T1178 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3475031780 Apr 23 04:25:57 PM PDT 24 Apr 23 04:32:34 PM PDT 24 3081666024 ps
T1179 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.89274891 Apr 23 04:04:25 PM PDT 24 Apr 23 04:16:05 PM PDT 24 4978601585 ps
T278 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1182430350 Apr 23 04:25:42 PM PDT 24 Apr 23 04:30:16 PM PDT 24 3081740246 ps
T1180 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2377198920 Apr 23 04:07:11 PM PDT 24 Apr 23 04:15:56 PM PDT 24 4206242385 ps
T713 /workspace/coverage/default/15.chip_sw_all_escalation_resets.417342254 Apr 23 04:27:05 PM PDT 24 Apr 23 04:34:54 PM PDT 24 5296180500 ps
T308 /workspace/coverage/default/0.chip_plic_all_irqs_0.4054021963 Apr 23 03:55:58 PM PDT 24 Apr 23 04:09:39 PM PDT 24 6365622126 ps
T1181 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1722751215 Apr 23 03:53:37 PM PDT 24 Apr 23 03:59:18 PM PDT 24 3178452008 ps
T682 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1570876830 Apr 23 04:26:56 PM PDT 24 Apr 23 04:33:15 PM PDT 24 3820125120 ps
T1182 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2043179003 Apr 23 03:55:05 PM PDT 24 Apr 23 04:54:46 PM PDT 24 13434508912 ps
T1183 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4212994122 Apr 23 04:23:20 PM PDT 24 Apr 23 04:35:53 PM PDT 24 4284724976 ps
T617 /workspace/coverage/default/1.chip_sw_edn_boot_mode.3997164945 Apr 23 04:09:07 PM PDT 24 Apr 23 04:17:33 PM PDT 24 3010288964 ps
T1184 /workspace/coverage/default/2.chip_sw_aon_timer_irq.803010928 Apr 23 04:20:35 PM PDT 24 Apr 23 04:26:37 PM PDT 24 4033784760 ps
T1185 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2105876840 Apr 23 04:20:20 PM PDT 24 Apr 23 04:25:39 PM PDT 24 4712772752 ps
T1186 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1915464367 Apr 23 04:14:36 PM PDT 24 Apr 23 04:26:00 PM PDT 24 3758010938 ps
T612 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.305160896 Apr 23 03:54:12 PM PDT 24 Apr 23 04:57:52 PM PDT 24 24624782788 ps
T1187 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1843705324 Apr 23 04:21:40 PM PDT 24 Apr 23 05:14:33 PM PDT 24 13579353952 ps
T1188 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3565804316 Apr 23 03:52:02 PM PDT 24 Apr 23 03:59:49 PM PDT 24 5611565340 ps
T683 /workspace/coverage/default/28.chip_sw_all_escalation_resets.3048587514 Apr 23 04:29:06 PM PDT 24 Apr 23 04:40:52 PM PDT 24 4134595532 ps
T1189 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1636867400 Apr 23 04:02:05 PM PDT 24 Apr 23 04:05:22 PM PDT 24 3292261656 ps
T1190 /workspace/coverage/default/2.chip_sw_example_flash.3001973825 Apr 23 04:14:40 PM PDT 24 Apr 23 04:17:28 PM PDT 24 3229841024 ps
T710 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2157433369 Apr 23 04:31:19 PM PDT 24 Apr 23 04:39:13 PM PDT 24 4369683264 ps
T1191 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3112072547 Apr 23 04:29:27 PM PDT 24 Apr 23 04:40:35 PM PDT 24 7086951827 ps
T344 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3014217012 Apr 23 03:51:01 PM PDT 24 Apr 23 04:00:17 PM PDT 24 4450022549 ps
T210 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2795397144 Apr 23 04:23:26 PM PDT 24 Apr 23 05:22:26 PM PDT 24 13045968388 ps
T1192 /workspace/coverage/default/9.chip_sw_all_escalation_resets.446472133 Apr 23 04:28:49 PM PDT 24 Apr 23 04:38:07 PM PDT 24 4668001310 ps
T1193 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.298734665 Apr 23 03:52:22 PM PDT 24 Apr 23 03:55:44 PM PDT 24 2148804859 ps
T1194 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2489637025 Apr 23 03:51:58 PM PDT 24 Apr 23 04:12:59 PM PDT 24 13842164664 ps
T1195 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.634357870 Apr 23 03:54:22 PM PDT 24 Apr 23 03:59:19 PM PDT 24 3412963770 ps
T729 /workspace/coverage/default/38.chip_sw_all_escalation_resets.1535037119 Apr 23 04:30:45 PM PDT 24 Apr 23 04:40:32 PM PDT 24 5815597136 ps
T1196 /workspace/coverage/default/2.chip_tap_straps_testunlock0.2691502854 Apr 23 04:24:28 PM PDT 24 Apr 23 04:28:12 PM PDT 24 3417051740 ps
T1197 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2283725716 Apr 23 04:20:38 PM PDT 24 Apr 23 08:12:17 PM PDT 24 255837968104 ps
T298 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.167668277 Apr 23 04:05:37 PM PDT 24 Apr 23 04:37:07 PM PDT 24 13464684200 ps
T1198 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2959938116 Apr 23 04:10:01 PM PDT 24 Apr 23 04:16:42 PM PDT 24 4941604896 ps
T1199 /workspace/coverage/default/1.chip_sw_aes_enc.496413944 Apr 23 04:07:39 PM PDT 24 Apr 23 04:12:55 PM PDT 24 2765755992 ps
T688 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3599671775 Apr 23 04:33:34 PM PDT 24 Apr 23 04:42:21 PM PDT 24 6440256024 ps
T1200 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1680981763 Apr 23 04:28:16 PM PDT 24 Apr 23 04:53:57 PM PDT 24 8469333324 ps
T1201 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3573740867 Apr 23 03:52:27 PM PDT 24 Apr 23 04:01:49 PM PDT 24 4204377172 ps
T1202 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2912606633 Apr 23 04:29:11 PM PDT 24 Apr 23 04:49:38 PM PDT 24 8294155576 ps
T1203 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3156409829 Apr 23 03:53:32 PM PDT 24 Apr 23 04:09:32 PM PDT 24 5063254952 ps
T689 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3869306139 Apr 23 04:30:57 PM PDT 24 Apr 23 04:37:42 PM PDT 24 3652218550 ps
T1204 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.489098176 Apr 23 03:50:27 PM PDT 24 Apr 23 03:59:39 PM PDT 24 6816503455 ps
T1205 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3427774895 Apr 23 04:17:17 PM PDT 24 Apr 23 04:34:22 PM PDT 24 5547887720 ps
T1206 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1576035136 Apr 23 04:19:45 PM PDT 24 Apr 23 04:47:56 PM PDT 24 12094375223 ps
T659 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.663088579 Apr 23 04:33:06 PM PDT 24 Apr 23 04:38:58 PM PDT 24 4438518352 ps
T1207 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1413405548 Apr 23 04:04:55 PM PDT 24 Apr 23 04:31:04 PM PDT 24 9244633032 ps
T1208 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1065522375 Apr 23 04:29:24 PM PDT 24 Apr 23 04:36:36 PM PDT 24 5474295992 ps
T1209 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2230471218 Apr 23 04:17:04 PM PDT 24 Apr 23 04:21:44 PM PDT 24 2400153560 ps
T739 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119868347 Apr 23 04:31:43 PM PDT 24 Apr 23 04:38:21 PM PDT 24 4160900372 ps
T742 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3450270123 Apr 23 04:31:51 PM PDT 24 Apr 23 04:38:49 PM PDT 24 3133048612 ps
T1210 /workspace/coverage/default/1.chip_sw_aes_masking_off.4000972883 Apr 23 04:07:08 PM PDT 24 Apr 23 04:12:00 PM PDT 24 2877203881 ps
T1211 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.810910266 Apr 23 04:08:46 PM PDT 24 Apr 23 04:28:33 PM PDT 24 10069920540 ps
T1212 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1987612420 Apr 23 03:50:39 PM PDT 24 Apr 23 04:35:22 PM PDT 24 13542745368 ps
T1213 /workspace/coverage/default/0.chip_sw_example_manufacturer.1904393644 Apr 23 03:51:48 PM PDT 24 Apr 23 03:55:21 PM PDT 24 2650976666 ps
T227 /workspace/coverage/default/2.chip_sw_alert_test.1915915524 Apr 23 04:21:57 PM PDT 24 Apr 23 04:27:58 PM PDT 24 2915610208 ps
T1214 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3264278801 Apr 23 04:10:49 PM PDT 24 Apr 23 04:14:48 PM PDT 24 3251355492 ps
T1215 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1114246939 Apr 23 04:27:19 PM PDT 24 Apr 23 04:35:44 PM PDT 24 3213473916 ps
T57 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2635011861 Apr 23 04:14:34 PM PDT 24 Apr 23 04:19:21 PM PDT 24 3962573090 ps
T281 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2673299448 Apr 23 03:54:53 PM PDT 24 Apr 23 04:02:44 PM PDT 24 5979052175 ps
T1216 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3315949277 Apr 23 04:09:55 PM PDT 24 Apr 23 04:15:05 PM PDT 24 2969261800 ps
T1217 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3850317708 Apr 23 03:50:17 PM PDT 24 Apr 23 04:08:14 PM PDT 24 8750908072 ps
T1218 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3412533908 Apr 23 04:06:39 PM PDT 24 Apr 23 04:34:31 PM PDT 24 13691057098 ps
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T1219 /workspace/coverage/default/12.chip_sw_all_escalation_resets.3916846455 Apr 23 04:28:59 PM PDT 24 Apr 23 04:39:54 PM PDT 24 5483205660 ps
T749 /workspace/coverage/default/20.chip_sw_all_escalation_resets.138820280 Apr 23 04:28:36 PM PDT 24 Apr 23 04:41:11 PM PDT 24 5091108040 ps
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T83 /workspace/coverage/cover_reg_top/90.xbar_access_same_device.3173278164 Apr 23 04:49:28 PM PDT 24 Apr 23 04:51:23 PM PDT 24 2270867007 ps
T85 /workspace/coverage/cover_reg_top/39.xbar_error_random.2302780229 Apr 23 04:41:32 PM PDT 24 Apr 23 04:42:08 PM PDT 24 1099498250 ps
T86 /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.609677492 Apr 23 04:49:02 PM PDT 24 Apr 23 05:07:58 PM PDT 24 101072235910 ps
T501 /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.294875808 Apr 23 04:44:06 PM PDT 24 Apr 23 05:13:52 PM PDT 24 103052451956 ps
T231 /workspace/coverage/cover_reg_top/89.xbar_error_random.2399744940 Apr 23 04:49:19 PM PDT 24 Apr 23 04:50:18 PM PDT 24 1838196860 ps
T415 /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1300484675 Apr 23 04:36:20 PM PDT 24 Apr 23 04:37:04 PM PDT 24 506252997 ps
T403 /workspace/coverage/cover_reg_top/57.xbar_access_same_device.2432682167 Apr 23 04:44:05 PM PDT 24 Apr 23 04:45:51 PM PDT 24 2203256778 ps
T416 /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.845694830 Apr 23 04:38:57 PM PDT 24 Apr 23 04:39:17 PM PDT 24 161767867 ps
T510 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.475338925 Apr 23 04:44:13 PM PDT 24 Apr 23 04:48:29 PM PDT 24 831066523 ps
T677 /workspace/coverage/cover_reg_top/83.xbar_access_same_device.112666118 Apr 23 04:48:18 PM PDT 24 Apr 23 04:49:01 PM PDT 24 1100969301 ps
T504 /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3854141005 Apr 23 04:34:56 PM PDT 24 Apr 23 04:42:18 PM PDT 24 6633198630 ps
T512 /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.484895898 Apr 23 04:48:47 PM PDT 24 Apr 23 04:50:26 PM PDT 24 8693046865 ps
T509 /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.264612583 Apr 23 04:36:31 PM PDT 24 Apr 23 04:36:52 PM PDT 24 158180945 ps
T404 /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.4063539346 Apr 23 04:48:47 PM PDT 24 Apr 23 04:49:13 PM PDT 24 286427768 ps
T505 /workspace/coverage/cover_reg_top/87.xbar_error_random.3138330020 Apr 23 04:48:57 PM PDT 24 Apr 23 04:49:36 PM PDT 24 429107951 ps
T491 /workspace/coverage/cover_reg_top/51.xbar_random.3024673893 Apr 23 04:43:21 PM PDT 24 Apr 23 04:44:00 PM PDT 24 931295427 ps
T405 /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.3179673881 Apr 23 04:39:58 PM PDT 24 Apr 23 04:59:43 PM PDT 24 60367074828 ps
T502 /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2911361271 Apr 23 04:33:52 PM PDT 24 Apr 23 04:38:59 PM PDT 24 9618036267 ps
T1220 /workspace/coverage/cover_reg_top/72.xbar_error_random.693715528 Apr 23 04:46:35 PM PDT 24 Apr 23 04:46:44 PM PDT 24 140795330 ps
T393 /workspace/coverage/cover_reg_top/59.xbar_random.4048147101 Apr 23 04:44:25 PM PDT 24 Apr 23 04:45:10 PM PDT 24 505868197 ps
T506 /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3443286967 Apr 23 04:40:43 PM PDT 24 Apr 23 04:41:09 PM PDT 24 568587408 ps
T143 /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1552317933 Apr 23 04:29:18 PM PDT 24 Apr 23 04:33:59 PM PDT 24 4066681313 ps
T1221 /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.4002200458 Apr 23 04:50:17 PM PDT 24 Apr 23 04:50:23 PM PDT 24 42264533 ps
T507 /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.3922271755 Apr 23 04:40:00 PM PDT 24 Apr 23 04:40:20 PM PDT 24 380828424 ps
T464 /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.4203353466 Apr 23 04:31:18 PM PDT 24 Apr 23 04:31:33 PM PDT 24 111458538 ps
T151 /workspace/coverage/cover_reg_top/4.chip_csr_rw.3133491307 Apr 23 04:31:05 PM PDT 24 Apr 23 04:41:29 PM PDT 24 5736468258 ps
T508 /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1270084001 Apr 23 04:44:51 PM PDT 24 Apr 23 04:52:52 PM PDT 24 4113812297 ps
T511 /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2656982268 Apr 23 04:32:46 PM PDT 24 Apr 23 04:37:35 PM PDT 24 7409433719 ps
T570 /workspace/coverage/cover_reg_top/77.xbar_same_source.3838608356 Apr 23 04:47:19 PM PDT 24 Apr 23 04:47:41 PM PDT 24 629285602 ps
T542 /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2141753814 Apr 23 04:33:29 PM PDT 24 Apr 23 04:34:08 PM PDT 24 398450970 ps
T621 /workspace/coverage/cover_reg_top/78.xbar_smoke.1488449021 Apr 23 04:47:22 PM PDT 24 Apr 23 04:47:29 PM PDT 24 48754958 ps
T429 /workspace/coverage/cover_reg_top/6.xbar_random.3728457391 Apr 23 04:31:57 PM PDT 24 Apr 23 04:32:58 PM PDT 24 1431378778 ps
T445 /workspace/coverage/cover_reg_top/76.xbar_stress_all.132261605 Apr 23 04:47:14 PM PDT 24 Apr 23 04:52:57 PM PDT 24 8777427578 ps
T450 /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1664042040 Apr 23 04:47:14 PM PDT 24 Apr 23 04:47:44 PM PDT 24 281161807 ps
T152 /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2498550004 Apr 23 04:32:51 PM PDT 24 Apr 23 05:31:14 PM PDT 24 31224966179 ps
T466 /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1327809143 Apr 23 04:48:44 PM PDT 24 Apr 23 04:58:28 PM PDT 24 31885687161 ps
T618 /workspace/coverage/cover_reg_top/12.chip_tl_errors.2768716118 Apr 23 04:34:32 PM PDT 24 Apr 23 04:36:07 PM PDT 24 3141775352 ps
T757 /workspace/coverage/cover_reg_top/34.xbar_access_same_device.2798723386 Apr 23 04:40:28 PM PDT 24 Apr 23 04:41:30 PM PDT 24 751607411 ps
T556 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.662258549 Apr 23 04:49:15 PM PDT 24 Apr 23 04:53:57 PM PDT 24 7873353042 ps
T561 /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3162303213 Apr 23 04:44:49 PM PDT 24 Apr 23 04:44:56 PM PDT 24 50894191 ps
T1222 /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2968130297 Apr 23 04:41:59 PM PDT 24 Apr 23 04:42:06 PM PDT 24 36424648 ps
T1223 /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3985551800 Apr 23 04:32:10 PM PDT 24 Apr 23 04:32:22 PM PDT 24 182950333 ps
T830 /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3212338813 Apr 23 04:47:38 PM PDT 24 Apr 23 04:49:14 PM PDT 24 8688295360 ps
T568 /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1375835391 Apr 23 04:47:53 PM PDT 24 Apr 23 04:49:19 PM PDT 24 7240785773 ps
T569 /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.3452547353 Apr 23 04:44:33 PM PDT 24 Apr 23 04:46:04 PM PDT 24 8577847878 ps
T541 /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3627130626 Apr 23 04:44:24 PM PDT 24 Apr 23 04:51:27 PM PDT 24 22807873593 ps
T431 /workspace/coverage/cover_reg_top/81.xbar_access_same_device.759946822 Apr 23 04:47:57 PM PDT 24 Apr 23 04:49:42 PM PDT 24 2755535232 ps
T620 /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1770167455 Apr 23 04:41:04 PM PDT 24 Apr 23 05:04:28 PM PDT 24 76368039360 ps
T537 /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.502684284 Apr 23 04:44:47 PM PDT 24 Apr 23 04:45:05 PM PDT 24 156215689 ps
T439 /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.1362705294 Apr 23 04:49:25 PM PDT 24 Apr 23 04:49:46 PM PDT 24 459997065 ps
T778 /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1790488837 Apr 23 04:46:36 PM PDT 24 Apr 23 05:07:12 PM PDT 24 70806868377 ps
T552 /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.3531292583 Apr 23 04:39:48 PM PDT 24 Apr 23 04:41:40 PM PDT 24 6427271952 ps
T809 /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2593090571 Apr 23 04:49:45 PM PDT 24 Apr 23 04:50:37 PM PDT 24 136495531 ps
T538 /workspace/coverage/cover_reg_top/14.xbar_random.3200461771 Apr 23 04:35:34 PM PDT 24 Apr 23 04:36:11 PM PDT 24 410725991 ps
T447 /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3190283350 Apr 23 04:42:15 PM PDT 24 Apr 23 04:49:53 PM PDT 24 24578332135 ps
T600 /workspace/coverage/cover_reg_top/51.xbar_smoke.2161822567 Apr 23 04:43:14 PM PDT 24 Apr 23 04:43:21 PM PDT 24 39318961 ps
T442 /workspace/coverage/cover_reg_top/18.xbar_stress_all.3243093415 Apr 23 04:37:06 PM PDT 24 Apr 23 04:42:40 PM PDT 24 9942028442 ps
T763 /workspace/coverage/cover_reg_top/17.xbar_access_same_device.3382567657 Apr 23 04:36:40 PM PDT 24 Apr 23 04:38:27 PM PDT 24 1316285150 ps
T434 /workspace/coverage/cover_reg_top/67.xbar_stress_all.2501903319 Apr 23 04:45:48 PM PDT 24 Apr 23 04:50:49 PM PDT 24 3403085764 ps
T764 /workspace/coverage/cover_reg_top/87.xbar_access_same_device.1168889616 Apr 23 04:49:00 PM PDT 24 Apr 23 04:50:07 PM PDT 24 1566568402 ps
T790 /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.864660188 Apr 23 04:40:43 PM PDT 24 Apr 23 04:49:17 PM PDT 24 29863129559 ps
T547 /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.2402443127 Apr 23 04:49:04 PM PDT 24 Apr 23 04:50:00 PM PDT 24 642246173 ps
T814 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2823563954 Apr 23 04:45:40 PM PDT 24 Apr 23 04:46:56 PM PDT 24 215898259 ps
T1224 /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3625038419 Apr 23 04:42:25 PM PDT 24 Apr 23 04:42:32 PM PDT 24 49428465 ps
T525 /workspace/coverage/cover_reg_top/11.chip_tl_errors.168295439 Apr 23 04:34:07 PM PDT 24 Apr 23 04:37:48 PM PDT 24 3410506997 ps
T1225 /workspace/coverage/cover_reg_top/41.xbar_smoke.680531287 Apr 23 04:41:41 PM PDT 24 Apr 23 04:41:50 PM PDT 24 173671252 ps
T641 /workspace/coverage/cover_reg_top/84.xbar_access_same_device.724448827 Apr 23 04:48:28 PM PDT 24 Apr 23 04:49:00 PM PDT 24 647469722 ps
T788 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2316609701 Apr 23 04:35:52 PM PDT 24 Apr 23 04:40:20 PM PDT 24 2700586806 ps
T773 /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.2297464720 Apr 23 04:39:39 PM PDT 24 Apr 23 04:44:56 PM PDT 24 3431642059 ps
T1226 /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.2942205004 Apr 23 04:49:03 PM PDT 24 Apr 23 04:50:38 PM PDT 24 8898660963 ps
T1227 /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3109940527 Apr 23 04:49:14 PM PDT 24 Apr 23 04:50:29 PM PDT 24 4287707656 ps
T521 /workspace/coverage/cover_reg_top/27.chip_tl_errors.3278281831 Apr 23 04:39:07 PM PDT 24 Apr 23 04:42:55 PM PDT 24 3442711130 ps
T417 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2446796274 Apr 23 04:41:58 PM PDT 24 Apr 23 04:45:45 PM PDT 24 1681189387 ps
T1228 /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.208951994 Apr 23 04:37:33 PM PDT 24 Apr 23 04:38:32 PM PDT 24 5128907469 ps
T599 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.484283329 Apr 23 04:35:30 PM PDT 24 Apr 23 04:43:13 PM PDT 24 5107955194 ps
T554 /workspace/coverage/cover_reg_top/5.xbar_random.1581481350 Apr 23 04:31:21 PM PDT 24 Apr 23 04:32:14 PM PDT 24 553386252 ps
T485 /workspace/coverage/cover_reg_top/10.xbar_stress_all.3633712074 Apr 23 04:34:02 PM PDT 24 Apr 23 04:35:27 PM PDT 24 1750154709 ps
T459 /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1655921218 Apr 23 04:49:36 PM PDT 24 Apr 23 04:49:43 PM PDT 24 54488538 ps
T1229 /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3308041905 Apr 23 04:31:17 PM PDT 24 Apr 23 04:31:24 PM PDT 24 36538585 ps
T793 /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3561409016 Apr 23 04:47:36 PM PDT 24 Apr 23 04:50:56 PM PDT 24 11018244703 ps
T573 /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1935282496 Apr 23 04:40:13 PM PDT 24 Apr 23 04:40:22 PM PDT 24 49909741 ps
T1230 /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1187893764 Apr 23 04:46:07 PM PDT 24 Apr 23 04:46:13 PM PDT 24 45212250 ps
T779 /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3035787886 Apr 23 04:42:09 PM PDT 24 Apr 23 04:48:22 PM PDT 24 5580378565 ps
T1231 /workspace/coverage/cover_reg_top/67.xbar_smoke.713837710 Apr 23 04:45:42 PM PDT 24 Apr 23 04:45:49 PM PDT 24 49978822 ps
T776 /workspace/coverage/cover_reg_top/91.xbar_access_same_device.4166530712 Apr 23 04:49:40 PM PDT 24 Apr 23 04:50:21 PM PDT 24 846817553 ps
T765 /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2748613152 Apr 23 04:50:25 PM PDT 24 Apr 23 05:16:30 PM PDT 24 90414773160 ps
T153 /workspace/coverage/cover_reg_top/14.chip_csr_rw.1152208667 Apr 23 04:35:48 PM PDT 24 Apr 23 04:46:20 PM PDT 24 6297379465 ps
T1232 /workspace/coverage/cover_reg_top/70.xbar_stress_all.2569019472 Apr 23 04:46:15 PM PDT 24 Apr 23 04:46:34 PM PDT 24 199333654 ps
T1233 /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.4079998915 Apr 23 04:44:57 PM PDT 24 Apr 23 04:46:04 PM PDT 24 6282495295 ps
T604 /workspace/coverage/cover_reg_top/54.xbar_stress_all.776014880 Apr 23 04:43:49 PM PDT 24 Apr 23 04:46:44 PM PDT 24 4309141782 ps
T558 /workspace/coverage/cover_reg_top/85.xbar_error_random.414933696 Apr 23 04:48:43 PM PDT 24 Apr 23 04:49:08 PM PDT 24 255009566 ps
T566 /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3524901958 Apr 23 04:49:41 PM PDT 24 Apr 23 04:50:27 PM PDT 24 951715440 ps
T1234 /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.845352263 Apr 23 04:38:35 PM PDT 24 Apr 23 04:38:41 PM PDT 24 41243146 ps
T1235 /workspace/coverage/cover_reg_top/21.xbar_error_random.2905447335 Apr 23 04:37:52 PM PDT 24 Apr 23 04:38:31 PM PDT 24 913768251 ps
T1236 /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2017062956 Apr 23 04:31:22 PM PDT 24 Apr 23 04:32:39 PM PDT 24 4161380397 ps
T812 /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1910919807 Apr 23 04:48:06 PM PDT 24 Apr 23 04:50:10 PM PDT 24 592080023 ps
T348 /workspace/coverage/cover_reg_top/7.chip_csr_rw.1284503282 Apr 23 04:32:48 PM PDT 24 Apr 23 04:36:44 PM PDT 24 3913933022 ps
T1237 /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.569610634 Apr 23 04:45:18 PM PDT 24 Apr 23 04:46:44 PM PDT 24 4682888615 ps
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