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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.34 95.50 94.59 95.66 95.37 97.38 99.57


Total test records in report: 2792
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T50 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3555191964 Apr 28 04:10:50 PM PDT 24 Apr 28 04:19:29 PM PDT 24 3641824600 ps
T146 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2503424108 Apr 28 03:52:47 PM PDT 24 Apr 28 05:03:08 PM PDT 24 17270593680 ps
T893 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1741292957 Apr 28 03:53:58 PM PDT 24 Apr 28 04:15:56 PM PDT 24 5520672488 ps
T85 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.4234613422 Apr 28 04:09:01 PM PDT 24 Apr 28 04:29:37 PM PDT 24 11949844900 ps
T69 /workspace/coverage/default/2.chip_tap_straps_rma.592261336 Apr 28 04:10:29 PM PDT 24 Apr 28 04:18:36 PM PDT 24 5386453939 ps
T894 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.501687448 Apr 28 03:58:18 PM PDT 24 Apr 28 04:03:35 PM PDT 24 2600285620 ps
T757 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.743130288 Apr 28 04:16:34 PM PDT 24 Apr 28 04:23:14 PM PDT 24 4118234452 ps
T384 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.518476304 Apr 28 03:54:49 PM PDT 24 Apr 28 04:15:00 PM PDT 24 5601420696 ps
T895 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2905502022 Apr 28 04:00:31 PM PDT 24 Apr 28 04:04:42 PM PDT 24 2442491776 ps
T100 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2008341118 Apr 28 04:13:13 PM PDT 24 Apr 28 04:20:27 PM PDT 24 7701276520 ps
T896 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1799128793 Apr 28 04:09:37 PM PDT 24 Apr 28 04:14:59 PM PDT 24 3548811369 ps
T321 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3200093533 Apr 28 03:51:22 PM PDT 24 Apr 28 03:57:01 PM PDT 24 2968659192 ps
T86 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2763610875 Apr 28 04:21:05 PM PDT 24 Apr 28 04:27:02 PM PDT 24 3851765040 ps
T897 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1411586332 Apr 28 04:08:51 PM PDT 24 Apr 28 04:12:43 PM PDT 24 2859339168 ps
T159 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.787373586 Apr 28 03:50:44 PM PDT 24 Apr 28 05:24:00 PM PDT 24 49632453360 ps
T358 /workspace/coverage/default/0.chip_sw_edn_auto_mode.3014811876 Apr 28 03:55:16 PM PDT 24 Apr 28 04:14:58 PM PDT 24 5380031376 ps
T7 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2209207576 Apr 28 03:50:20 PM PDT 24 Apr 28 03:54:17 PM PDT 24 2508989878 ps
T898 /workspace/coverage/default/0.chip_sw_otbn_smoketest.562299213 Apr 28 03:57:16 PM PDT 24 Apr 28 04:29:27 PM PDT 24 9481622984 ps
T301 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1617463188 Apr 28 03:50:54 PM PDT 24 Apr 28 04:02:15 PM PDT 24 5689919704 ps
T899 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.184238112 Apr 28 03:56:13 PM PDT 24 Apr 28 04:13:29 PM PDT 24 5788444860 ps
T792 /workspace/coverage/default/37.chip_sw_all_escalation_resets.4238889783 Apr 28 04:17:06 PM PDT 24 Apr 28 04:28:19 PM PDT 24 6101996268 ps
T186 /workspace/coverage/default/2.chip_sw_power_sleep_load.2909329199 Apr 28 04:11:03 PM PDT 24 Apr 28 04:18:12 PM PDT 24 4020421468 ps
T748 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3073604335 Apr 28 04:16:39 PM PDT 24 Apr 28 04:23:48 PM PDT 24 3712873892 ps
T160 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2242931313 Apr 28 03:51:08 PM PDT 24 Apr 28 04:06:01 PM PDT 24 9322607716 ps
T900 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3838829094 Apr 28 03:51:01 PM PDT 24 Apr 28 04:22:30 PM PDT 24 34164487816 ps
T901 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4087877111 Apr 28 03:53:08 PM PDT 24 Apr 28 04:05:26 PM PDT 24 4410235592 ps
T664 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3756362344 Apr 28 04:19:52 PM PDT 24 Apr 28 04:33:37 PM PDT 24 4668869520 ps
T902 /workspace/coverage/default/2.chip_sw_example_flash.3053120282 Apr 28 04:05:02 PM PDT 24 Apr 28 04:08:51 PM PDT 24 2898308924 ps
T903 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2008568100 Apr 28 03:53:20 PM PDT 24 Apr 28 04:09:54 PM PDT 24 8820565936 ps
T904 /workspace/coverage/default/0.chip_sw_aes_enc.1509330731 Apr 28 03:52:16 PM PDT 24 Apr 28 03:55:53 PM PDT 24 2307636510 ps
T317 /workspace/coverage/default/83.chip_sw_all_escalation_resets.3095967253 Apr 28 04:22:34 PM PDT 24 Apr 28 04:33:10 PM PDT 24 6373490936 ps
T783 /workspace/coverage/default/25.chip_sw_all_escalation_resets.713709090 Apr 28 04:16:29 PM PDT 24 Apr 28 04:26:33 PM PDT 24 5850624970 ps
T753 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1520901160 Apr 28 04:21:06 PM PDT 24 Apr 28 04:26:46 PM PDT 24 3098804628 ps
T240 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2790024318 Apr 28 04:02:07 PM PDT 24 Apr 28 04:11:52 PM PDT 24 4286834168 ps
T219 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2356417258 Apr 28 03:58:56 PM PDT 24 Apr 28 05:24:09 PM PDT 24 49042425174 ps
T756 /workspace/coverage/default/80.chip_sw_all_escalation_resets.3538755609 Apr 28 04:21:20 PM PDT 24 Apr 28 04:34:19 PM PDT 24 5057446744 ps
T655 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3828060794 Apr 28 03:56:12 PM PDT 24 Apr 28 04:06:59 PM PDT 24 5813077172 ps
T905 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2605848649 Apr 28 03:58:08 PM PDT 24 Apr 28 04:02:39 PM PDT 24 3254677810 ps
T158 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3616739791 Apr 28 04:13:08 PM PDT 24 Apr 28 04:21:04 PM PDT 24 4859499812 ps
T906 /workspace/coverage/default/3.chip_tap_straps_rma.3434286244 Apr 28 04:18:16 PM PDT 24 Apr 28 04:26:04 PM PDT 24 4768991203 ps
T777 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3569941925 Apr 28 04:18:10 PM PDT 24 Apr 28 04:23:48 PM PDT 24 3893358916 ps
T311 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1918973625 Apr 28 04:15:04 PM PDT 24 Apr 28 04:46:17 PM PDT 24 8959648376 ps
T175 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1454789245 Apr 28 03:56:36 PM PDT 24 Apr 28 05:29:42 PM PDT 24 43210209164 ps
T147 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.223646211 Apr 28 03:55:18 PM PDT 24 Apr 28 07:00:22 PM PDT 24 57187073685 ps
T700 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3735818876 Apr 28 04:24:28 PM PDT 24 Apr 28 04:38:10 PM PDT 24 6152243702 ps
T212 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3330164661 Apr 28 04:09:40 PM PDT 24 Apr 28 05:15:17 PM PDT 24 11650667252 ps
T73 /workspace/coverage/default/0.chip_sw_usbdev_pullup.370409883 Apr 28 03:52:29 PM PDT 24 Apr 28 03:58:10 PM PDT 24 3030298298 ps
T907 /workspace/coverage/default/1.chip_sw_kmac_smoketest.836741232 Apr 28 04:04:29 PM PDT 24 Apr 28 04:09:07 PM PDT 24 2415812298 ps
T908 /workspace/coverage/default/1.chip_sw_example_rom.30504917 Apr 28 03:55:39 PM PDT 24 Apr 28 03:57:25 PM PDT 24 2368621520 ps
T11 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3710847411 Apr 28 03:56:57 PM PDT 24 Apr 28 04:10:28 PM PDT 24 8009239292 ps
T213 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1313152609 Apr 28 04:00:17 PM PDT 24 Apr 28 05:28:02 PM PDT 24 15570377092 ps
T128 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2069643535 Apr 28 03:55:47 PM PDT 24 Apr 28 04:03:40 PM PDT 24 4920283312 ps
T909 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1662994037 Apr 28 04:02:05 PM PDT 24 Apr 28 04:14:49 PM PDT 24 8589749620 ps
T910 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2934981256 Apr 28 03:56:45 PM PDT 24 Apr 28 04:18:00 PM PDT 24 9562784416 ps
T911 /workspace/coverage/default/1.chip_sw_aes_entropy.3372738322 Apr 28 03:58:09 PM PDT 24 Apr 28 04:02:58 PM PDT 24 3171600210 ps
T132 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1594171899 Apr 28 03:53:45 PM PDT 24 Apr 28 04:11:16 PM PDT 24 5530088500 ps
T695 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1277184195 Apr 28 03:53:10 PM PDT 24 Apr 28 04:33:33 PM PDT 24 26132526213 ps
T912 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.807389259 Apr 28 04:09:30 PM PDT 24 Apr 28 04:19:02 PM PDT 24 4926012950 ps
T913 /workspace/coverage/default/0.chip_sw_power_idle_load.2909764 Apr 28 03:55:10 PM PDT 24 Apr 28 04:06:45 PM PDT 24 3831459964 ps
T914 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3678515999 Apr 28 04:06:11 PM PDT 24 Apr 28 04:09:59 PM PDT 24 2707883718 ps
T915 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1599786933 Apr 28 04:12:25 PM PDT 24 Apr 28 04:20:12 PM PDT 24 4873541752 ps
T916 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2221510011 Apr 28 04:11:27 PM PDT 24 Apr 28 04:19:53 PM PDT 24 3263908828 ps
T917 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.415576785 Apr 28 04:01:47 PM PDT 24 Apr 28 04:13:08 PM PDT 24 3381951182 ps
T288 /workspace/coverage/default/2.chip_plic_all_irqs_0.840581375 Apr 28 04:09:42 PM PDT 24 Apr 28 04:28:45 PM PDT 24 5670695410 ps
T259 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1347060412 Apr 28 03:54:11 PM PDT 24 Apr 28 04:03:04 PM PDT 24 3434840688 ps
T754 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3229814878 Apr 28 04:22:31 PM PDT 24 Apr 28 04:30:17 PM PDT 24 4296261586 ps
T918 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2205240349 Apr 28 03:59:32 PM PDT 24 Apr 28 04:07:08 PM PDT 24 6434010504 ps
T919 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.13708964 Apr 28 04:05:06 PM PDT 24 Apr 28 04:32:24 PM PDT 24 8705441548 ps
T920 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3715994658 Apr 28 03:52:17 PM PDT 24 Apr 28 04:03:06 PM PDT 24 7230950680 ps
T307 /workspace/coverage/default/0.chip_sw_pattgen_ios.3022445543 Apr 28 03:51:12 PM PDT 24 Apr 28 03:54:52 PM PDT 24 3002811594 ps
T921 /workspace/coverage/default/0.chip_sw_kmac_smoketest.4075180759 Apr 28 03:54:29 PM PDT 24 Apr 28 03:59:28 PM PDT 24 3634212732 ps
T12 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2687536673 Apr 28 04:05:37 PM PDT 24 Apr 28 04:11:01 PM PDT 24 3431867794 ps
T922 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3599229197 Apr 28 04:12:15 PM PDT 24 Apr 28 04:17:32 PM PDT 24 3278169744 ps
T793 /workspace/coverage/default/2.chip_sw_all_escalation_resets.832689189 Apr 28 04:04:33 PM PDT 24 Apr 28 04:16:46 PM PDT 24 6031659578 ps
T923 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4161805043 Apr 28 03:53:39 PM PDT 24 Apr 28 04:05:44 PM PDT 24 5749188360 ps
T324 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1317505531 Apr 28 04:04:42 PM PDT 24 Apr 28 04:08:59 PM PDT 24 2714095941 ps
T71 /workspace/coverage/default/4.chip_tap_straps_rma.4151423392 Apr 28 04:19:21 PM PDT 24 Apr 28 04:21:45 PM PDT 24 2287667021 ps
T737 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3213683000 Apr 28 04:14:08 PM PDT 24 Apr 28 04:20:48 PM PDT 24 3901273476 ps
T292 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3412005005 Apr 28 04:11:58 PM PDT 24 Apr 28 04:26:58 PM PDT 24 5102894933 ps
T733 /workspace/coverage/default/19.chip_sw_all_escalation_resets.707442736 Apr 28 04:15:27 PM PDT 24 Apr 28 04:25:35 PM PDT 24 5365417510 ps
T742 /workspace/coverage/default/51.chip_sw_all_escalation_resets.3940636609 Apr 28 04:20:13 PM PDT 24 Apr 28 04:31:18 PM PDT 24 5422155356 ps
T924 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1974549280 Apr 28 03:54:11 PM PDT 24 Apr 28 04:03:10 PM PDT 24 5690721650 ps
T665 /workspace/coverage/default/13.chip_sw_all_escalation_resets.903063650 Apr 28 04:24:36 PM PDT 24 Apr 28 04:33:57 PM PDT 24 4514529800 ps
T215 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2829075303 Apr 28 03:55:54 PM PDT 24 Apr 28 05:37:06 PM PDT 24 48774388563 ps
T282 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2925055137 Apr 28 04:21:44 PM PDT 24 Apr 28 04:29:32 PM PDT 24 4528013550 ps
T218 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.493673410 Apr 28 04:10:15 PM PDT 24 Apr 28 05:42:27 PM PDT 24 47322524784 ps
T472 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2096591510 Apr 28 03:52:10 PM PDT 24 Apr 28 04:07:26 PM PDT 24 4860396880 ps
T714 /workspace/coverage/default/39.chip_sw_all_escalation_resets.1710137804 Apr 28 04:17:51 PM PDT 24 Apr 28 04:28:43 PM PDT 24 5948339320 ps
T925 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3282403550 Apr 28 04:19:41 PM PDT 24 Apr 28 04:28:02 PM PDT 24 3869486614 ps
T926 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.4014836414 Apr 28 04:14:19 PM PDT 24 Apr 28 04:29:01 PM PDT 24 3901196620 ps
T927 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2783804193 Apr 28 04:10:52 PM PDT 24 Apr 28 04:31:00 PM PDT 24 13369814425 ps
T23 /workspace/coverage/default/0.chip_sw_gpio.345331516 Apr 28 03:50:37 PM PDT 24 Apr 28 03:57:36 PM PDT 24 3859244600 ps
T928 /workspace/coverage/default/0.chip_sw_csrng_kat_test.2712527128 Apr 28 03:51:50 PM PDT 24 Apr 28 03:56:56 PM PDT 24 2741193036 ps
T784 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2510681212 Apr 28 04:20:37 PM PDT 24 Apr 28 04:30:55 PM PDT 24 3628019984 ps
T332 /workspace/coverage/default/45.chip_sw_all_escalation_resets.2919194109 Apr 28 04:18:41 PM PDT 24 Apr 28 04:28:11 PM PDT 24 5491753386 ps
T336 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.893201158 Apr 28 03:52:39 PM PDT 24 Apr 28 04:00:17 PM PDT 24 6131866680 ps
T337 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.54833388 Apr 28 04:10:46 PM PDT 24 Apr 28 04:31:27 PM PDT 24 9118445840 ps
T338 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1267500796 Apr 28 04:03:57 PM PDT 24 Apr 28 04:07:10 PM PDT 24 2423644910 ps
T339 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.934408570 Apr 28 04:14:40 PM PDT 24 Apr 28 04:20:51 PM PDT 24 3857339576 ps
T340 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2864702076 Apr 28 03:58:53 PM PDT 24 Apr 28 04:02:57 PM PDT 24 2508818570 ps
T341 /workspace/coverage/default/96.chip_sw_all_escalation_resets.3710168718 Apr 28 04:25:28 PM PDT 24 Apr 28 04:38:56 PM PDT 24 6698340544 ps
T342 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3982188813 Apr 28 03:57:41 PM PDT 24 Apr 28 04:15:46 PM PDT 24 5699971940 ps
T343 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1470636819 Apr 28 04:21:56 PM PDT 24 Apr 28 04:30:02 PM PDT 24 3569721926 ps
T344 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.803189212 Apr 28 04:05:23 PM PDT 24 Apr 28 04:11:42 PM PDT 24 4993026296 ps
T289 /workspace/coverage/default/2.chip_plic_all_irqs_20.1464996593 Apr 28 04:11:29 PM PDT 24 Apr 28 04:25:20 PM PDT 24 4690259198 ps
T250 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1557369663 Apr 28 04:00:06 PM PDT 24 Apr 28 04:08:56 PM PDT 24 8742169320 ps
T929 /workspace/coverage/default/94.chip_sw_all_escalation_resets.2172979734 Apr 28 04:22:33 PM PDT 24 Apr 28 04:36:17 PM PDT 24 5182679092 ps
T24 /workspace/coverage/default/2.chip_sw_gpio_smoketest.3985155200 Apr 28 04:12:26 PM PDT 24 Apr 28 04:16:52 PM PDT 24 3423218963 ps
T930 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1278121878 Apr 28 04:04:11 PM PDT 24 Apr 28 04:21:52 PM PDT 24 5563130936 ps
T799 /workspace/coverage/default/52.chip_sw_all_escalation_resets.318426814 Apr 28 04:18:15 PM PDT 24 Apr 28 04:32:27 PM PDT 24 5589597780 ps
T772 /workspace/coverage/default/0.chip_sw_all_escalation_resets.466469307 Apr 28 03:51:06 PM PDT 24 Apr 28 04:02:57 PM PDT 24 6085368264 ps
T931 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1386872947 Apr 28 04:21:36 PM PDT 24 Apr 28 04:38:10 PM PDT 24 11071491104 ps
T932 /workspace/coverage/default/1.chip_sw_uart_smoketest.1083804490 Apr 28 04:04:54 PM PDT 24 Apr 28 04:10:33 PM PDT 24 3072529112 ps
T933 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.428344378 Apr 28 04:08:53 PM PDT 24 Apr 28 04:12:14 PM PDT 24 2149758800 ps
T345 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2668475755 Apr 28 03:55:29 PM PDT 24 Apr 28 03:58:02 PM PDT 24 2646011796 ps
T789 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2001364882 Apr 28 04:19:19 PM PDT 24 Apr 28 04:26:06 PM PDT 24 3677581072 ps
T934 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3594107860 Apr 28 04:10:56 PM PDT 24 Apr 28 04:14:23 PM PDT 24 2609486936 ps
T935 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.955002418 Apr 28 03:51:48 PM PDT 24 Apr 28 04:02:42 PM PDT 24 18368161996 ps
T287 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4202310752 Apr 28 04:02:21 PM PDT 24 Apr 28 04:38:44 PM PDT 24 13499325464 ps
T936 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2292022140 Apr 28 03:57:41 PM PDT 24 Apr 28 04:06:50 PM PDT 24 5243162738 ps
T231 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.533060735 Apr 28 04:16:47 PM PDT 24 Apr 28 04:23:44 PM PDT 24 3371610656 ps
T232 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2920763955 Apr 28 04:20:55 PM PDT 24 Apr 28 04:28:04 PM PDT 24 3837969068 ps
T937 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4156520483 Apr 28 03:58:59 PM PDT 24 Apr 28 04:30:13 PM PDT 24 7701512240 ps
T938 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1618831733 Apr 28 04:00:50 PM PDT 24 Apr 28 04:09:41 PM PDT 24 6662400120 ps
T939 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3177563183 Apr 28 03:52:19 PM PDT 24 Apr 28 04:03:11 PM PDT 24 4567216042 ps
T701 /workspace/coverage/default/49.chip_sw_all_escalation_resets.3908707807 Apr 28 04:19:48 PM PDT 24 Apr 28 04:34:36 PM PDT 24 5177869394 ps
T940 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1593185104 Apr 28 04:07:10 PM PDT 24 Apr 28 05:12:14 PM PDT 24 35115087050 ps
T761 /workspace/coverage/default/1.chip_sw_all_escalation_resets.4219166971 Apr 28 03:56:47 PM PDT 24 Apr 28 04:05:46 PM PDT 24 4333087432 ps
T941 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2569343525 Apr 28 03:53:19 PM PDT 24 Apr 28 04:03:15 PM PDT 24 5155782812 ps
T942 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3426734984 Apr 28 04:11:29 PM PDT 24 Apr 28 04:22:46 PM PDT 24 7115768340 ps
T943 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3617464385 Apr 28 04:01:26 PM PDT 24 Apr 28 04:05:18 PM PDT 24 2919112358 ps
T239 /workspace/coverage/default/0.chip_sw_rv_timer_irq.2905465896 Apr 28 03:52:18 PM PDT 24 Apr 28 03:56:18 PM PDT 24 2855512926 ps
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