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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.34 95.50 94.59 95.66 95.37 97.38 99.57


Total test records in report: 2792
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T2510 /workspace/coverage/cover_reg_top/22.xbar_access_same_device.2845615004 Apr 28 04:36:23 PM PDT 24 Apr 28 04:36:43 PM PDT 24 249896420 ps
T2511 /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.533887984 Apr 28 04:45:14 PM PDT 24 Apr 28 04:45:59 PM PDT 24 928394761 ps
T2512 /workspace/coverage/cover_reg_top/4.xbar_smoke.2845499249 Apr 28 04:31:44 PM PDT 24 Apr 28 04:31:53 PM PDT 24 151127107 ps
T2513 /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2874035992 Apr 28 04:49:02 PM PDT 24 Apr 28 04:50:47 PM PDT 24 221146395 ps
T2514 /workspace/coverage/cover_reg_top/18.chip_tl_errors.4293266693 Apr 28 04:35:08 PM PDT 24 Apr 28 04:41:10 PM PDT 24 3808296225 ps
T2515 /workspace/coverage/cover_reg_top/1.xbar_random.1298934633 Apr 28 04:31:37 PM PDT 24 Apr 28 04:31:50 PM PDT 24 108518775 ps
T2516 /workspace/coverage/cover_reg_top/68.xbar_error_random.2023711981 Apr 28 04:45:25 PM PDT 24 Apr 28 04:46:15 PM PDT 24 1533495012 ps
T2517 /workspace/coverage/cover_reg_top/99.xbar_same_source.1723344785 Apr 28 04:50:33 PM PDT 24 Apr 28 04:50:41 PM PDT 24 43206868 ps
T2518 /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1211815329 Apr 28 04:37:04 PM PDT 24 Apr 28 04:51:37 PM PDT 24 78621295308 ps
T2519 /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2950581172 Apr 28 04:42:14 PM PDT 24 Apr 28 04:43:43 PM PDT 24 7956496973 ps
T2520 /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3847576332 Apr 28 04:35:28 PM PDT 24 Apr 28 04:36:49 PM PDT 24 4497197995 ps
T2521 /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.473553106 Apr 28 04:33:34 PM PDT 24 Apr 28 04:33:41 PM PDT 24 45903085 ps
T2522 /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.3103220056 Apr 28 04:50:03 PM PDT 24 Apr 28 04:50:30 PM PDT 24 536934231 ps
T2523 /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1946702701 Apr 28 04:36:52 PM PDT 24 Apr 28 04:40:08 PM PDT 24 17281128962 ps
T2524 /workspace/coverage/cover_reg_top/20.xbar_access_same_device.1591818431 Apr 28 04:35:45 PM PDT 24 Apr 28 04:36:10 PM PDT 24 260548154 ps
T2525 /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1504013451 Apr 28 04:38:39 PM PDT 24 Apr 28 04:40:29 PM PDT 24 5604618685 ps
T2526 /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.85355225 Apr 28 04:31:47 PM PDT 24 Apr 28 04:33:30 PM PDT 24 6060896928 ps
T2527 /workspace/coverage/cover_reg_top/93.xbar_same_source.739034185 Apr 28 04:49:34 PM PDT 24 Apr 28 04:50:49 PM PDT 24 2349679160 ps
T2528 /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.3127280728 Apr 28 04:42:30 PM PDT 24 Apr 28 04:43:27 PM PDT 24 1482513691 ps
T2529 /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1203134812 Apr 28 04:32:46 PM PDT 24 Apr 28 04:33:13 PM PDT 24 581439530 ps
T2530 /workspace/coverage/cover_reg_top/74.xbar_access_same_device.1986616342 Apr 28 04:46:18 PM PDT 24 Apr 28 04:47:00 PM PDT 24 583031686 ps
T2531 /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1232902574 Apr 28 04:47:57 PM PDT 24 Apr 28 04:48:05 PM PDT 24 53798076 ps
T2532 /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.267243798 Apr 28 04:42:10 PM PDT 24 Apr 28 04:43:07 PM PDT 24 141281800 ps
T2533 /workspace/coverage/cover_reg_top/9.chip_tl_errors.3438351901 Apr 28 04:32:49 PM PDT 24 Apr 28 04:34:30 PM PDT 24 2717502635 ps
T2534 /workspace/coverage/cover_reg_top/96.xbar_error_random.2263153142 Apr 28 04:50:00 PM PDT 24 Apr 28 04:50:08 PM PDT 24 55792975 ps
T2535 /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3657573716 Apr 28 04:39:33 PM PDT 24 Apr 28 04:40:46 PM PDT 24 4130261959 ps
T2536 /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1269193313 Apr 28 04:35:14 PM PDT 24 Apr 28 04:36:30 PM PDT 24 6587716958 ps
T2537 /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2044247117 Apr 28 04:38:00 PM PDT 24 Apr 28 04:38:28 PM PDT 24 472864886 ps
T2538 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2221465126 Apr 28 04:36:57 PM PDT 24 Apr 28 04:46:18 PM PDT 24 4416134884 ps
T2539 /workspace/coverage/cover_reg_top/19.xbar_random.2881208677 Apr 28 04:35:24 PM PDT 24 Apr 28 04:36:25 PM PDT 24 1400694554 ps
T2540 /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.323442799 Apr 28 04:41:26 PM PDT 24 Apr 28 04:42:42 PM PDT 24 1881505806 ps
T2541 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.3767956546 Apr 28 04:35:39 PM PDT 24 Apr 28 04:48:06 PM PDT 24 11298605944 ps
T2542 /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3050156180 Apr 28 04:33:33 PM PDT 24 Apr 28 04:38:37 PM PDT 24 7752753641 ps
T2543 /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3796168990 Apr 28 04:47:54 PM PDT 24 Apr 28 05:02:36 PM PDT 24 77234505616 ps
T2544 /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3148846063 Apr 28 04:41:44 PM PDT 24 Apr 28 04:48:19 PM PDT 24 22401087855 ps
T2545 /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.1070261581 Apr 28 04:36:23 PM PDT 24 Apr 28 04:37:19 PM PDT 24 4406537984 ps
T2546 /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.477103292 Apr 28 04:49:55 PM PDT 24 Apr 28 05:07:54 PM PDT 24 64983797859 ps
T2547 /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2553686053 Apr 28 04:37:10 PM PDT 24 Apr 28 05:04:28 PM PDT 24 89096352291 ps
T2548 /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.11129896 Apr 28 04:48:58 PM PDT 24 Apr 28 04:50:35 PM PDT 24 9240866929 ps
T2549 /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.3678299746 Apr 28 04:32:10 PM PDT 24 Apr 28 04:37:09 PM PDT 24 16220807091 ps
T2550 /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2756522778 Apr 28 04:48:48 PM PDT 24 Apr 28 04:48:56 PM PDT 24 53118337 ps
T2551 /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2454401157 Apr 28 04:41:59 PM PDT 24 Apr 28 04:43:13 PM PDT 24 619190843 ps
T2552 /workspace/coverage/cover_reg_top/3.xbar_stress_all.3293453537 Apr 28 04:31:52 PM PDT 24 Apr 28 04:33:00 PM PDT 24 732088378 ps
T2553 /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.626365058 Apr 28 04:42:34 PM PDT 24 Apr 28 04:46:19 PM PDT 24 2439532297 ps
T2554 /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1820399894 Apr 28 04:39:29 PM PDT 24 Apr 28 04:39:36 PM PDT 24 46538599 ps
T2555 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.1852288337 Apr 28 04:45:09 PM PDT 24 Apr 28 04:51:48 PM PDT 24 4467240382 ps
T2556 /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1610480170 Apr 28 04:31:33 PM PDT 24 Apr 28 04:35:32 PM PDT 24 6473781067 ps
T2557 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3846861619 Apr 28 04:38:32 PM PDT 24 Apr 28 04:42:27 PM PDT 24 838735114 ps
T2558 /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.2660950754 Apr 28 04:44:35 PM PDT 24 Apr 28 04:45:06 PM PDT 24 669732489 ps
T2559 /workspace/coverage/cover_reg_top/25.xbar_error_random.517178855 Apr 28 04:37:10 PM PDT 24 Apr 28 04:38:43 PM PDT 24 2382142662 ps
T2560 /workspace/coverage/cover_reg_top/20.xbar_random.1931590230 Apr 28 04:35:45 PM PDT 24 Apr 28 04:35:53 PM PDT 24 91288611 ps
T2561 /workspace/coverage/cover_reg_top/46.xbar_random.3861932315 Apr 28 04:41:10 PM PDT 24 Apr 28 04:41:19 PM PDT 24 67207591 ps
T2562 /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.9119454 Apr 28 04:39:53 PM PDT 24 Apr 28 04:40:00 PM PDT 24 43369994 ps
T2563 /workspace/coverage/cover_reg_top/31.xbar_random.1032490659 Apr 28 04:38:20 PM PDT 24 Apr 28 04:39:40 PM PDT 24 2210231734 ps
T2564 /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1669294553 Apr 28 04:48:18 PM PDT 24 Apr 28 04:50:30 PM PDT 24 7339288159 ps
T2565 /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.2130523961 Apr 28 04:47:21 PM PDT 24 Apr 28 04:47:34 PM PDT 24 123903594 ps
T2566 /workspace/coverage/cover_reg_top/30.xbar_random.1624816350 Apr 28 04:38:07 PM PDT 24 Apr 28 04:38:15 PM PDT 24 105727547 ps
T687 /workspace/coverage/cover_reg_top/17.chip_tl_errors.3009609886 Apr 28 04:34:50 PM PDT 24 Apr 28 04:39:35 PM PDT 24 3392619442 ps
T2567 /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3106795973 Apr 28 04:48:37 PM PDT 24 Apr 28 04:48:44 PM PDT 24 55544503 ps
T2568 /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1933015902 Apr 28 04:31:36 PM PDT 24 Apr 28 05:23:45 PM PDT 24 30904365404 ps
T2569 /workspace/coverage/cover_reg_top/82.xbar_same_source.243155753 Apr 28 04:47:43 PM PDT 24 Apr 28 04:48:16 PM PDT 24 400216599 ps
T2570 /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1946493167 Apr 28 04:43:24 PM PDT 24 Apr 28 04:43:59 PM PDT 24 756920745 ps
T2571 /workspace/coverage/cover_reg_top/72.xbar_smoke.3528146011 Apr 28 04:45:48 PM PDT 24 Apr 28 04:45:56 PM PDT 24 52630926 ps
T2572 /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.3461957929 Apr 28 04:46:27 PM PDT 24 Apr 28 04:46:33 PM PDT 24 51361870 ps
T2573 /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1550544606 Apr 28 04:34:04 PM PDT 24 Apr 28 04:35:02 PM PDT 24 3372240248 ps
T2574 /workspace/coverage/cover_reg_top/45.xbar_error_random.2620817313 Apr 28 04:41:05 PM PDT 24 Apr 28 04:42:16 PM PDT 24 2117682844 ps
T2575 /workspace/coverage/cover_reg_top/32.xbar_stress_all.3117411595 Apr 28 04:38:37 PM PDT 24 Apr 28 04:42:04 PM PDT 24 4547034083 ps
T2576 /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3950131221 Apr 28 04:50:38 PM PDT 24 Apr 28 04:57:48 PM PDT 24 6839517479 ps
T2577 /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.250472881 Apr 28 04:31:28 PM PDT 24 Apr 28 05:44:54 PM PDT 24 43183259915 ps
T2578 /workspace/coverage/cover_reg_top/27.xbar_smoke.3885757090 Apr 28 04:37:35 PM PDT 24 Apr 28 04:37:42 PM PDT 24 53887786 ps
T2579 /workspace/coverage/cover_reg_top/20.xbar_smoke.645766954 Apr 28 04:35:43 PM PDT 24 Apr 28 04:35:51 PM PDT 24 45431848 ps
T2580 /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.4050757143 Apr 28 04:50:12 PM PDT 24 Apr 28 04:52:02 PM PDT 24 5690626844 ps
T2581 /workspace/coverage/cover_reg_top/39.xbar_access_same_device.604888812 Apr 28 04:39:56 PM PDT 24 Apr 28 04:40:35 PM PDT 24 714588575 ps
T2582 /workspace/coverage/cover_reg_top/62.xbar_access_same_device.2084454477 Apr 28 04:44:17 PM PDT 24 Apr 28 04:45:06 PM PDT 24 1202305230 ps
T2583 /workspace/coverage/cover_reg_top/19.chip_csr_rw.2740758898 Apr 28 04:35:37 PM PDT 24 Apr 28 04:41:56 PM PDT 24 4289209806 ps
T2584 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3285019821 Apr 28 04:34:14 PM PDT 24 Apr 28 04:41:54 PM PDT 24 7843298826 ps
T2585 /workspace/coverage/cover_reg_top/32.xbar_error_random.2652842916 Apr 28 04:38:37 PM PDT 24 Apr 28 04:39:20 PM PDT 24 439698279 ps
T2586 /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.1078725098 Apr 28 04:46:04 PM PDT 24 Apr 28 04:58:18 PM PDT 24 17634639357 ps
T2587 /workspace/coverage/cover_reg_top/95.xbar_random.1064581767 Apr 28 04:49:47 PM PDT 24 Apr 28 04:51:16 PM PDT 24 2289636406 ps
T2588 /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1831935621 Apr 28 04:42:14 PM PDT 24 Apr 28 04:42:21 PM PDT 24 43093927 ps
T2589 /workspace/coverage/cover_reg_top/85.xbar_random.1183029812 Apr 28 04:48:05 PM PDT 24 Apr 28 04:48:26 PM PDT 24 200690943 ps
T2590 /workspace/coverage/cover_reg_top/86.xbar_random.3240832550 Apr 28 04:48:18 PM PDT 24 Apr 28 04:48:48 PM PDT 24 303621291 ps
T2591 /workspace/coverage/cover_reg_top/16.xbar_smoke.827423678 Apr 28 04:34:44 PM PDT 24 Apr 28 04:34:51 PM PDT 24 44378209 ps
T2592 /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.438314811 Apr 28 04:31:51 PM PDT 24 Apr 28 04:33:31 PM PDT 24 5299600475 ps
T2593 /workspace/coverage/cover_reg_top/67.xbar_random.3287928061 Apr 28 04:44:57 PM PDT 24 Apr 28 04:45:45 PM PDT 24 526296291 ps
T2594 /workspace/coverage/cover_reg_top/51.xbar_access_same_device.864740459 Apr 28 04:42:05 PM PDT 24 Apr 28 04:44:28 PM PDT 24 3043822061 ps
T2595 /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.2473564215 Apr 28 04:31:44 PM PDT 24 Apr 28 04:43:49 PM PDT 24 5734947555 ps
T2596 /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1253135148 Apr 28 04:40:12 PM PDT 24 Apr 28 04:40:37 PM PDT 24 273199690 ps
T2597 /workspace/coverage/cover_reg_top/10.xbar_access_same_device.4258406654 Apr 28 04:33:05 PM PDT 24 Apr 28 04:34:29 PM PDT 24 1858969964 ps
T2598 /workspace/coverage/cover_reg_top/49.xbar_access_same_device.935661691 Apr 28 04:41:45 PM PDT 24 Apr 28 04:44:15 PM PDT 24 3276160649 ps
T2599 /workspace/coverage/cover_reg_top/26.xbar_stress_all.2437494576 Apr 28 04:37:31 PM PDT 24 Apr 28 04:39:20 PM PDT 24 1048490144 ps
T2600 /workspace/coverage/cover_reg_top/90.xbar_error_random.2818869301 Apr 28 04:49:03 PM PDT 24 Apr 28 04:49:25 PM PDT 24 523881385 ps
T2601 /workspace/coverage/cover_reg_top/52.xbar_stress_all.259288362 Apr 28 04:42:24 PM PDT 24 Apr 28 04:43:18 PM PDT 24 658388040 ps
T2602 /workspace/coverage/cover_reg_top/64.xbar_random.2421528878 Apr 28 04:44:26 PM PDT 24 Apr 28 04:44:41 PM PDT 24 349700044 ps
T2603 /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.722676658 Apr 28 04:35:00 PM PDT 24 Apr 28 04:47:24 PM PDT 24 13412866672 ps
T2604 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2925990223 Apr 28 04:34:33 PM PDT 24 Apr 28 04:35:11 PM PDT 24 96277012 ps
T2605 /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.4101783167 Apr 28 04:50:01 PM PDT 24 Apr 28 04:50:13 PM PDT 24 82598635 ps
T2606 /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3769982493 Apr 28 04:49:07 PM PDT 24 Apr 28 04:50:50 PM PDT 24 5996679359 ps
T2607 /workspace/coverage/cover_reg_top/0.xbar_random.540264235 Apr 28 04:31:34 PM PDT 24 Apr 28 04:32:06 PM PDT 24 351021627 ps
T2608 /workspace/coverage/cover_reg_top/42.xbar_access_same_device.1304001966 Apr 28 04:40:31 PM PDT 24 Apr 28 04:41:00 PM PDT 24 584336179 ps
T2609 /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.2659275494 Apr 28 04:31:43 PM PDT 24 Apr 28 04:33:29 PM PDT 24 9300508519 ps
T2610 /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.3459537841 Apr 28 04:45:41 PM PDT 24 Apr 28 04:48:54 PM PDT 24 5529787318 ps
T2611 /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1426129248 Apr 28 04:50:04 PM PDT 24 Apr 28 04:51:08 PM PDT 24 6226675830 ps
T2612 /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.4069346270 Apr 28 04:31:41 PM PDT 24 Apr 28 04:33:01 PM PDT 24 3994270472 ps
T2613 /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.3195735027 Apr 28 04:32:08 PM PDT 24 Apr 28 04:32:23 PM PDT 24 231924997 ps
T2614 /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.1519469858 Apr 28 04:39:29 PM PDT 24 Apr 28 04:40:53 PM PDT 24 113421618 ps
T2615 /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.1675482383 Apr 28 04:40:16 PM PDT 24 Apr 28 04:44:57 PM PDT 24 3424964309 ps
T598 /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.1281223567 Apr 28 04:49:51 PM PDT 24 Apr 28 04:55:32 PM PDT 24 8671146797 ps
T2616 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3738968007 Apr 28 04:35:16 PM PDT 24 Apr 28 04:37:44 PM PDT 24 3918339472 ps
T2617 /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.2661297930 Apr 28 04:41:02 PM PDT 24 Apr 28 04:41:46 PM PDT 24 916489097 ps
T2618 /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.2454281163 Apr 28 04:48:43 PM PDT 24 Apr 28 04:48:59 PM PDT 24 185617536 ps
T2619 /workspace/coverage/cover_reg_top/65.xbar_error_random.2372611010 Apr 28 04:44:43 PM PDT 24 Apr 28 04:46:26 PM PDT 24 2494631024 ps
T2620 /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.4107433909 Apr 28 04:43:03 PM PDT 24 Apr 28 04:43:29 PM PDT 24 527911503 ps
T2621 /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3141668766 Apr 28 04:44:34 PM PDT 24 Apr 28 04:44:48 PM PDT 24 92119353 ps
T2622 /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.176437353 Apr 28 04:43:32 PM PDT 24 Apr 28 04:58:18 PM PDT 24 45292185017 ps
T2623 /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.368713345 Apr 28 04:32:59 PM PDT 24 Apr 28 04:33:38 PM PDT 24 717421978 ps
T2624 /workspace/coverage/cover_reg_top/23.xbar_same_source.2241939586 Apr 28 04:36:40 PM PDT 24 Apr 28 04:37:08 PM PDT 24 757016064 ps
T2625 /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.843776819 Apr 28 04:31:55 PM PDT 24 Apr 28 04:32:15 PM PDT 24 154409994 ps
T2626 /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.2710164013 Apr 28 04:31:53 PM PDT 24 Apr 28 04:32:56 PM PDT 24 5636943021 ps
T2627 /workspace/coverage/cover_reg_top/74.xbar_error_random.4266302350 Apr 28 04:46:21 PM PDT 24 Apr 28 04:46:33 PM PDT 24 101664072 ps
T2628 /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1458127794 Apr 28 04:41:56 PM PDT 24 Apr 28 04:51:47 PM PDT 24 57711616003 ps
T2629 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3650358699 Apr 28 04:48:48 PM PDT 24 Apr 28 04:52:06 PM PDT 24 4240610775 ps
T2630 /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.343145167 Apr 28 04:36:36 PM PDT 24 Apr 28 04:50:14 PM PDT 24 65930850762 ps
T2631 /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.2836521642 Apr 28 04:50:22 PM PDT 24 Apr 28 04:51:05 PM PDT 24 981017770 ps
T2632 /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.857679493 Apr 28 04:45:37 PM PDT 24 Apr 28 04:57:46 PM PDT 24 36576419474 ps
T2633 /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1021887025 Apr 28 04:45:16 PM PDT 24 Apr 28 05:12:08 PM PDT 24 92433298978 ps
T2634 /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2007668108 Apr 28 04:34:59 PM PDT 24 Apr 28 04:35:58 PM PDT 24 1257672440 ps
T2635 /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.503696574 Apr 28 04:35:16 PM PDT 24 Apr 28 04:35:27 PM PDT 24 206004505 ps
T2636 /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.418489653 Apr 28 04:33:49 PM PDT 24 Apr 28 04:33:55 PM PDT 24 19771114 ps
T2637 /workspace/coverage/cover_reg_top/96.xbar_access_same_device.1671540800 Apr 28 04:49:55 PM PDT 24 Apr 28 04:52:12 PM PDT 24 3016852059 ps
T136 /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3502909198 Apr 28 04:31:42 PM PDT 24 Apr 28 04:37:27 PM PDT 24 6029847349 ps
T2638 /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.1801952205 Apr 28 04:31:49 PM PDT 24 Apr 28 05:10:17 PM PDT 24 126824469487 ps
T2639 /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.2908931916 Apr 28 04:43:57 PM PDT 24 Apr 28 04:44:32 PM PDT 24 369349824 ps
T2640 /workspace/coverage/cover_reg_top/25.xbar_random.511512733 Apr 28 04:37:00 PM PDT 24 Apr 28 04:37:32 PM PDT 24 677408217 ps
T2641 /workspace/coverage/cover_reg_top/3.chip_tl_errors.1618891636 Apr 28 04:31:42 PM PDT 24 Apr 28 04:37:40 PM PDT 24 4079409440 ps
T2642 /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.1740650600 Apr 28 04:45:45 PM PDT 24 Apr 28 04:46:20 PM PDT 24 321909281 ps
T2643 /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3068550033 Apr 28 04:33:21 PM PDT 24 Apr 28 04:34:49 PM PDT 24 7925068378 ps
T2644 /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1604595663 Apr 28 04:31:30 PM PDT 24 Apr 28 04:31:37 PM PDT 24 47327696 ps
T2645 /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.909791422 Apr 28 04:46:04 PM PDT 24 Apr 28 04:46:11 PM PDT 24 45782993 ps
T2646 /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1210167359 Apr 28 04:39:08 PM PDT 24 Apr 28 04:39:47 PM PDT 24 421009290 ps
T2647 /workspace/coverage/cover_reg_top/56.xbar_random.2186121923 Apr 28 04:42:58 PM PDT 24 Apr 28 04:43:53 PM PDT 24 1357631965 ps
T2648 /workspace/coverage/cover_reg_top/82.xbar_error_random.1740081111 Apr 28 04:47:41 PM PDT 24 Apr 28 04:48:14 PM PDT 24 389827962 ps
T2649 /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3686106207 Apr 28 04:49:31 PM PDT 24 Apr 28 04:56:03 PM PDT 24 21411331520 ps
T2650 /workspace/coverage/cover_reg_top/10.chip_tl_errors.3049622467 Apr 28 04:33:01 PM PDT 24 Apr 28 04:36:55 PM PDT 24 3508886242 ps
T2651 /workspace/coverage/cover_reg_top/61.xbar_stress_all.105934428 Apr 28 04:44:08 PM PDT 24 Apr 28 04:48:45 PM PDT 24 7218379878 ps
T2652 /workspace/coverage/cover_reg_top/7.chip_csr_rw.2807180261 Apr 28 04:32:15 PM PDT 24 Apr 28 04:38:42 PM PDT 24 4244305687 ps
T2653 /workspace/coverage/cover_reg_top/47.xbar_same_source.2330259444 Apr 28 04:41:22 PM PDT 24 Apr 28 04:41:50 PM PDT 24 317391485 ps
T2654 /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1287548092 Apr 28 04:40:26 PM PDT 24 Apr 28 04:44:18 PM PDT 24 2831136549 ps
T2655 /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.1536727262 Apr 28 04:39:41 PM PDT 24 Apr 28 04:55:03 PM PDT 24 49403629077 ps
T2656 /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1110007064 Apr 28 04:42:53 PM PDT 24 Apr 28 04:43:53 PM PDT 24 638090761 ps
T2657 /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1244312871 Apr 28 04:32:33 PM PDT 24 Apr 28 04:47:54 PM PDT 24 52372968367 ps
T2658 /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.2706272733 Apr 28 04:31:43 PM PDT 24 Apr 28 04:36:32 PM PDT 24 3223666137 ps
T2659 /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.88812460 Apr 28 04:42:08 PM PDT 24 Apr 28 04:46:51 PM PDT 24 6826048247 ps
T2660 /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.2783741672 Apr 28 04:42:59 PM PDT 24 Apr 28 04:44:12 PM PDT 24 6644906631 ps
T2661 /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.3140546866 Apr 28 04:31:53 PM PDT 24 Apr 28 05:01:07 PM PDT 24 14514811997 ps
T2662 /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2273799737 Apr 28 04:40:39 PM PDT 24 Apr 28 04:41:57 PM PDT 24 4268036979 ps
T2663 /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3796792257 Apr 28 04:31:38 PM PDT 24 Apr 28 04:31:46 PM PDT 24 53521207 ps
T2664 /workspace/coverage/cover_reg_top/69.xbar_error_random.2476145831 Apr 28 04:45:29 PM PDT 24 Apr 28 04:45:53 PM PDT 24 237911102 ps
T2665 /workspace/coverage/cover_reg_top/25.chip_tl_errors.4260753873 Apr 28 04:37:00 PM PDT 24 Apr 28 04:41:06 PM PDT 24 3419658650 ps
T2666 /workspace/coverage/cover_reg_top/62.xbar_stress_all.3684247382 Apr 28 04:44:18 PM PDT 24 Apr 28 04:46:27 PM PDT 24 1382011327 ps
T2667 /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.21334704 Apr 28 04:45:10 PM PDT 24 Apr 28 04:46:19 PM PDT 24 5856712238 ps
T2668 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3114431439 Apr 28 04:42:48 PM PDT 24 Apr 28 04:46:37 PM PDT 24 1758071780 ps
T2669 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1925295920 Apr 28 04:47:05 PM PDT 24 Apr 28 04:49:31 PM PDT 24 258518598 ps
T2670 /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3043015773 Apr 28 04:40:42 PM PDT 24 Apr 28 04:41:35 PM PDT 24 568768978 ps
T2671 /workspace/coverage/cover_reg_top/86.xbar_error_random.955607999 Apr 28 04:48:25 PM PDT 24 Apr 28 04:49:14 PM PDT 24 1373274201 ps
T2672 /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.4236932860 Apr 28 04:50:28 PM PDT 24 Apr 28 05:08:30 PM PDT 24 96400683210 ps
T2673 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1602617122 Apr 28 04:38:42 PM PDT 24 Apr 28 04:43:29 PM PDT 24 761320659 ps
T2674 /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1678881255 Apr 28 04:41:43 PM PDT 24 Apr 28 04:43:32 PM PDT 24 9441881467 ps
T2675 /workspace/coverage/cover_reg_top/75.xbar_access_same_device.1507920180 Apr 28 04:46:30 PM PDT 24 Apr 28 04:48:18 PM PDT 24 2107128760 ps
T2676 /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.4027302380 Apr 28 04:31:44 PM PDT 24 Apr 28 04:32:36 PM PDT 24 1157056000 ps
T2677 /workspace/coverage/cover_reg_top/69.xbar_stress_all.1162442866 Apr 28 04:45:27 PM PDT 24 Apr 28 04:49:48 PM PDT 24 5423500629 ps
T2678 /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1400906524 Apr 28 04:31:29 PM PDT 24 Apr 28 04:32:34 PM PDT 24 628533578 ps
T2679 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.2748425434 Apr 28 04:42:51 PM PDT 24 Apr 28 04:45:55 PM PDT 24 3962421938 ps
T2680 /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1239586344 Apr 28 04:39:45 PM PDT 24 Apr 28 04:40:10 PM PDT 24 99369377 ps
T2681 /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3053671537 Apr 28 04:39:07 PM PDT 24 Apr 28 04:45:58 PM PDT 24 2394385016 ps
T2682 /workspace/coverage/cover_reg_top/63.xbar_stress_all.4137255623 Apr 28 04:44:21 PM PDT 24 Apr 28 04:48:11 PM PDT 24 2673281426 ps
T131 /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4021722173 Apr 28 04:31:31 PM PDT 24 Apr 28 04:36:26 PM PDT 24 4296147000 ps
T2683 /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4025021433 Apr 28 04:33:54 PM PDT 24 Apr 28 04:34:30 PM PDT 24 301843553 ps
T2684 /workspace/coverage/cover_reg_top/52.xbar_smoke.3464456909 Apr 28 04:42:08 PM PDT 24 Apr 28 04:42:16 PM PDT 24 149954027 ps
T2685 /workspace/coverage/cover_reg_top/93.xbar_random.677304177 Apr 28 04:49:29 PM PDT 24 Apr 28 04:49:59 PM PDT 24 290875088 ps
T2686 /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3422052092 Apr 28 04:40:47 PM PDT 24 Apr 28 04:42:02 PM PDT 24 127582701 ps
T2687 /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1260650269 Apr 28 04:48:55 PM PDT 24 Apr 28 04:49:21 PM PDT 24 579953661 ps
T2688 /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2581369815 Apr 28 04:33:01 PM PDT 24 Apr 28 04:36:56 PM PDT 24 1754610208 ps
T2689 /workspace/coverage/cover_reg_top/78.xbar_same_source.944562197 Apr 28 04:47:01 PM PDT 24 Apr 28 04:48:17 PM PDT 24 2390076841 ps
T2690 /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1407874739 Apr 28 04:44:23 PM PDT 24 Apr 28 04:44:43 PM PDT 24 108155925 ps
T2691 /workspace/coverage/cover_reg_top/50.xbar_random.3498082887 Apr 28 04:41:55 PM PDT 24 Apr 28 04:42:32 PM PDT 24 943293832 ps
T2692 /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2599968338 Apr 28 04:43:07 PM PDT 24 Apr 28 04:43:13 PM PDT 24 37809609 ps
T2693 /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3340937331 Apr 28 04:50:31 PM PDT 24 Apr 28 05:00:28 PM PDT 24 59755630006 ps
T2694 /workspace/coverage/cover_reg_top/83.xbar_same_source.1243960323 Apr 28 04:47:56 PM PDT 24 Apr 28 04:48:09 PM PDT 24 271495108 ps
T2695 /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.3723097942 Apr 28 04:39:18 PM PDT 24 Apr 28 05:01:50 PM PDT 24 107920393615 ps
T2696 /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.166030289 Apr 28 04:34:09 PM PDT 24 Apr 28 04:35:16 PM PDT 24 1291221777 ps
T2697 /workspace/coverage/cover_reg_top/41.xbar_stress_all.178586051 Apr 28 04:40:23 PM PDT 24 Apr 28 04:46:22 PM PDT 24 7806835300 ps
T2698 /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.733566215 Apr 28 04:48:06 PM PDT 24 Apr 28 04:49:27 PM PDT 24 4601221365 ps
T2699 /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.23923458 Apr 28 04:49:36 PM PDT 24 Apr 28 04:50:32 PM PDT 24 209305707 ps
T2700 /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.625163779 Apr 28 04:36:44 PM PDT 24 Apr 28 04:40:36 PM PDT 24 6137643950 ps
T2701 /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1398015496 Apr 28 04:32:10 PM PDT 24 Apr 28 04:59:01 PM PDT 24 90704870138 ps
T2702 /workspace/coverage/cover_reg_top/76.xbar_smoke.2593274892 Apr 28 04:46:36 PM PDT 24 Apr 28 04:46:43 PM PDT 24 47362921 ps
T2703 /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1666968558 Apr 28 04:46:11 PM PDT 24 Apr 28 04:46:17 PM PDT 24 19331060 ps
T2704 /workspace/coverage/cover_reg_top/13.chip_tl_errors.2188079885 Apr 28 04:33:54 PM PDT 24 Apr 28 04:39:54 PM PDT 24 4372133659 ps
T2705 /workspace/coverage/cover_reg_top/73.xbar_error_random.2785008705 Apr 28 04:46:10 PM PDT 24 Apr 28 04:46:28 PM PDT 24 401950189 ps
T2706 /workspace/coverage/cover_reg_top/37.xbar_same_source.4103629559 Apr 28 04:39:33 PM PDT 24 Apr 28 04:40:39 PM PDT 24 2014277785 ps
T2707 /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.606979158 Apr 28 04:38:14 PM PDT 24 Apr 28 04:45:36 PM PDT 24 25045865187 ps
T2708 /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1423527514 Apr 28 04:42:23 PM PDT 24 Apr 28 04:42:31 PM PDT 24 129611789 ps
T2709 /workspace/coverage/cover_reg_top/16.xbar_stress_all.60578370 Apr 28 04:34:48 PM PDT 24 Apr 28 04:40:09 PM PDT 24 7710963790 ps
T2710 /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.1173186640 Apr 28 04:43:15 PM PDT 24 Apr 28 05:00:14 PM PDT 24 52478876187 ps
T2711 /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.121112525 Apr 28 04:43:16 PM PDT 24 Apr 28 04:44:59 PM PDT 24 5313498717 ps
T2712 /workspace/coverage/cover_reg_top/85.xbar_access_same_device.770882748 Apr 28 04:48:07 PM PDT 24 Apr 28 04:50:06 PM PDT 24 2681715056 ps
T2713 /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1811560436 Apr 28 04:50:13 PM PDT 24 Apr 28 04:51:09 PM PDT 24 1432056843 ps
T2714 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1622495062 Apr 28 04:31:54 PM PDT 24 Apr 28 04:35:06 PM PDT 24 1343716151 ps
T2715 /workspace/coverage/cover_reg_top/26.xbar_same_source.2994207641 Apr 28 04:37:25 PM PDT 24 Apr 28 04:38:41 PM PDT 24 2628294138 ps
T2716 /workspace/coverage/cover_reg_top/32.xbar_same_source.2431344837 Apr 28 04:38:40 PM PDT 24 Apr 28 04:38:53 PM PDT 24 120224388 ps
T2717 /workspace/coverage/cover_reg_top/2.chip_tl_errors.3781544642 Apr 28 04:31:37 PM PDT 24 Apr 28 04:35:39 PM PDT 24 3423557220 ps
T2718 /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.91277454 Apr 28 04:48:03 PM PDT 24 Apr 28 05:03:21 PM PDT 24 52875557056 ps
T2719 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2974126883 Apr 28 04:43:04 PM PDT 24 Apr 28 04:49:25 PM PDT 24 1854139260 ps
T2720 /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1782621730 Apr 28 04:40:13 PM PDT 24 Apr 28 04:41:23 PM PDT 24 3890444769 ps
T2721 /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.617098822 Apr 28 04:34:08 PM PDT 24 Apr 28 04:34:36 PM PDT 24 1618510159 ps
T2722 /workspace/coverage/cover_reg_top/62.xbar_same_source.1351987004 Apr 28 04:44:12 PM PDT 24 Apr 28 04:45:34 PM PDT 24 2614926852 ps
T2723 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2145439343 Apr 28 04:47:22 PM PDT 24 Apr 28 04:54:35 PM PDT 24 8859815681 ps
T2724 /workspace/coverage/cover_reg_top/7.xbar_access_same_device.1763672220 Apr 28 04:32:11 PM PDT 24 Apr 28 04:33:08 PM PDT 24 710121649 ps
T2725 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.195272435 Apr 28 04:34:14 PM PDT 24 Apr 28 04:38:12 PM PDT 24 5815874321 ps
T2726 /workspace/coverage/cover_reg_top/62.xbar_error_random.2038454519 Apr 28 04:44:16 PM PDT 24 Apr 28 04:45:34 PM PDT 24 2059256026 ps
T2727 /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.1304067699 Apr 28 04:38:34 PM PDT 24 Apr 28 04:38:41 PM PDT 24 35555612 ps
T2728 /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.1443906195 Apr 28 04:45:25 PM PDT 24 Apr 28 04:45:52 PM PDT 24 358204843 ps
T2729 /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.951303137 Apr 28 04:47:17 PM PDT 24 Apr 28 04:47:53 PM PDT 24 3629289834 ps
T2730 /workspace/coverage/cover_reg_top/1.xbar_error_random.3330746854 Apr 28 04:31:42 PM PDT 24 Apr 28 04:32:00 PM PDT 24 407754342 ps
T2731 /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.139880227 Apr 28 04:39:29 PM PDT 24 Apr 28 04:40:02 PM PDT 24 257635988 ps
T2732 /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.396217214 Apr 28 04:38:17 PM PDT 24 Apr 28 04:38:24 PM PDT 24 42752282 ps
T2733 /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1154729214 Apr 28 04:39:41 PM PDT 24 Apr 28 04:40:44 PM PDT 24 3491726887 ps
T2734 /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.3829389343 Apr 28 04:40:40 PM PDT 24 Apr 28 05:18:28 PM PDT 24 131541252275 ps
T2735 /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.1969453349 Apr 28 04:43:53 PM PDT 24 Apr 28 04:45:23 PM PDT 24 1055230281 ps
T2736 /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.712067911 Apr 28 04:34:41 PM PDT 24 Apr 28 04:48:51 PM PDT 24 75454038521 ps
T2737 /workspace/coverage/cover_reg_top/51.xbar_smoke.613516182 Apr 28 04:42:03 PM PDT 24 Apr 28 04:42:12 PM PDT 24 184584180 ps
T2738 /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3202830874 Apr 28 04:48:26 PM PDT 24 Apr 28 04:48:36 PM PDT 24 161596564 ps
T2739 /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.889925884 Apr 28 04:47:04 PM PDT 24 Apr 28 04:47:58 PM PDT 24 1316274819 ps
T2740 /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1740172267 Apr 28 04:40:47 PM PDT 24 Apr 28 05:07:38 PM PDT 24 92509631315 ps
T2741 /workspace/coverage/cover_reg_top/15.xbar_random.2804840759 Apr 28 04:34:24 PM PDT 24 Apr 28 04:35:04 PM PDT 24 396193106 ps
T2742 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2803621295 Apr 28 04:40:55 PM PDT 24 Apr 28 04:47:45 PM PDT 24 2813353044 ps
T2743 /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2375380392 Apr 28 04:37:47 PM PDT 24 Apr 28 04:37:53 PM PDT 24 41064959 ps
T2744 /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1323722518 Apr 28 04:46:33 PM PDT 24 Apr 28 04:59:53 PM PDT 24 42891977808 ps
T2745 /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1700484949 Apr 28 04:44:22 PM PDT 24 Apr 28 04:44:49 PM PDT 24 657829672 ps
T2746 /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.847464916 Apr 28 04:46:16 PM PDT 24 Apr 28 04:58:34 PM PDT 24 71714047118 ps
T2747 /workspace/coverage/cover_reg_top/49.xbar_same_source.3407743552 Apr 28 04:41:44 PM PDT 24 Apr 28 04:42:20 PM PDT 24 387122839 ps
T2748 /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3233121858 Apr 28 04:46:59 PM PDT 24 Apr 28 04:58:57 PM PDT 24 39901283482 ps
T2749 /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3767555352 Apr 28 04:49:13 PM PDT 24 Apr 28 04:54:34 PM PDT 24 25346156488 ps
T334 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3858022182 Apr 28 04:31:45 PM PDT 24 Apr 28 04:37:07 PM PDT 24 5686418987 ps
T2750 /workspace/coverage/cover_reg_top/69.xbar_smoke.1266971773 Apr 28 04:45:19 PM PDT 24 Apr 28 04:45:28 PM PDT 24 208507268 ps
T2751 /workspace/coverage/cover_reg_top/26.chip_tl_errors.610301205 Apr 28 04:37:18 PM PDT 24 Apr 28 04:40:39 PM PDT 24 2829230942 ps
T2752 /workspace/coverage/cover_reg_top/66.xbar_stress_all.2906083201 Apr 28 04:44:58 PM PDT 24 Apr 28 04:51:44 PM PDT 24 4840260122 ps
T2753 /workspace/coverage/cover_reg_top/28.xbar_random.2099824802 Apr 28 04:37:48 PM PDT 24 Apr 28 04:38:30 PM PDT 24 417874231 ps
T2754 /workspace/coverage/cover_reg_top/20.xbar_error_random.351847114 Apr 28 04:35:49 PM PDT 24 Apr 28 04:36:42 PM PDT 24 564526307 ps
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