Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.34 95.50 94.59 95.66 95.37 97.38 99.57


Total test records in report: 2792
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html
T1154 /workspace/coverage/default/1.chip_sw_rv_timer_irq.233937238 Apr 28 03:59:04 PM PDT 24 Apr 28 04:03:23 PM PDT 24 3055007964 ps
T1155 /workspace/coverage/default/0.chip_sw_example_concurrency.416332815 Apr 28 03:50:25 PM PDT 24 Apr 28 03:53:57 PM PDT 24 2270540080 ps
T322 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3096411240 Apr 28 03:51:52 PM PDT 24 Apr 28 03:57:42 PM PDT 24 3526960318 ps
T1156 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1595574015 Apr 28 04:05:53 PM PDT 24 Apr 28 05:41:38 PM PDT 24 47569882273 ps
T1157 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3161120645 Apr 28 03:53:17 PM PDT 24 Apr 28 04:03:11 PM PDT 24 4941520560 ps
T237 /workspace/coverage/default/1.chip_sw_power_sleep_load.3599852731 Apr 28 04:03:24 PM PDT 24 Apr 28 04:08:56 PM PDT 24 4209750862 ps
T1158 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2758439499 Apr 28 03:52:04 PM PDT 24 Apr 28 04:25:55 PM PDT 24 9142592496 ps
T1159 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2416759356 Apr 28 03:51:07 PM PDT 24 Apr 28 03:55:36 PM PDT 24 3702908119 ps
T1160 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1358562461 Apr 28 04:10:10 PM PDT 24 Apr 28 04:19:05 PM PDT 24 3602916072 ps
T1161 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1126099146 Apr 28 04:14:54 PM PDT 24 Apr 28 04:43:07 PM PDT 24 7351318440 ps
T1162 /workspace/coverage/default/0.chip_tap_straps_prod.3228326948 Apr 28 03:53:03 PM PDT 24 Apr 28 03:55:26 PM PDT 24 2755019440 ps
T1163 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2112008779 Apr 28 03:56:22 PM PDT 24 Apr 28 03:59:35 PM PDT 24 3144112220 ps
T1164 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2429339589 Apr 28 04:05:22 PM PDT 24 Apr 28 07:19:49 PM PDT 24 58038106524 ps
T738 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3994445717 Apr 28 04:20:16 PM PDT 24 Apr 28 04:27:12 PM PDT 24 3754609400 ps
T1165 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1476929122 Apr 28 04:23:59 PM PDT 24 Apr 28 04:32:29 PM PDT 24 5842782516 ps
T1166 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3608163807 Apr 28 04:01:56 PM PDT 24 Apr 28 04:07:41 PM PDT 24 5738180056 ps
T1167 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1720880476 Apr 28 04:10:08 PM PDT 24 Apr 28 04:18:32 PM PDT 24 10097881010 ps
T1168 /workspace/coverage/default/2.chip_sw_rv_timer_irq.3829934960 Apr 28 04:08:29 PM PDT 24 Apr 28 04:13:17 PM PDT 24 3460175484 ps
T1169 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2932432001 Apr 28 03:51:05 PM PDT 24 Apr 28 04:04:49 PM PDT 24 4416380448 ps
T1170 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2963485320 Apr 28 03:54:32 PM PDT 24 Apr 28 04:06:28 PM PDT 24 4873731240 ps
T134 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3150250267 Apr 28 04:05:43 PM PDT 24 Apr 28 04:15:08 PM PDT 24 4354672970 ps
T1171 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1770779443 Apr 28 03:55:17 PM PDT 24 Apr 28 04:36:53 PM PDT 24 23829520268 ps
T1172 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.585091893 Apr 28 03:51:07 PM PDT 24 Apr 28 03:53:17 PM PDT 24 3057965226 ps
T1173 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2887639207 Apr 28 04:09:44 PM PDT 24 Apr 28 04:17:59 PM PDT 24 4268516784 ps
T1174 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.307793477 Apr 28 04:12:31 PM PDT 24 Apr 28 04:16:40 PM PDT 24 2915939767 ps
T1175 /workspace/coverage/default/2.chip_sw_uart_smoketest.2591525863 Apr 28 04:12:03 PM PDT 24 Apr 28 04:17:39 PM PDT 24 2867522406 ps
T1176 /workspace/coverage/default/4.chip_tap_straps_dev.2219996721 Apr 28 04:13:04 PM PDT 24 Apr 28 04:16:24 PM PDT 24 3040931150 ps
T1177 /workspace/coverage/default/0.chip_sw_flash_crash_alert.1498477034 Apr 28 03:55:59 PM PDT 24 Apr 28 04:07:43 PM PDT 24 4954956980 ps
T1178 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3807285939 Apr 28 03:51:07 PM PDT 24 Apr 28 04:05:45 PM PDT 24 5970867232 ps
T1179 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3992736570 Apr 28 04:21:33 PM PDT 24 Apr 28 04:50:54 PM PDT 24 8536030648 ps
T1180 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3183262033 Apr 28 03:58:08 PM PDT 24 Apr 28 04:23:51 PM PDT 24 11150671160 ps
T1181 /workspace/coverage/default/0.chip_sw_kmac_idle.2467024791 Apr 28 03:52:34 PM PDT 24 Apr 28 03:56:57 PM PDT 24 2511242740 ps
T1182 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2847407821 Apr 28 04:08:25 PM PDT 24 Apr 28 04:20:24 PM PDT 24 4682596316 ps
T1183 /workspace/coverage/default/2.chip_sw_example_manufacturer.1149050608 Apr 28 04:05:19 PM PDT 24 Apr 28 04:09:27 PM PDT 24 3128967868 ps
T657 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1847013732 Apr 28 04:10:02 PM PDT 24 Apr 28 04:22:26 PM PDT 24 5585695895 ps
T1184 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3407668990 Apr 28 03:54:03 PM PDT 24 Apr 28 04:05:44 PM PDT 24 8747444740 ps
T252 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2930242007 Apr 28 04:13:01 PM PDT 24 Apr 28 04:26:18 PM PDT 24 4990128198 ps
T1185 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2201880980 Apr 28 04:08:00 PM PDT 24 Apr 28 04:19:05 PM PDT 24 6221404488 ps
T241 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.447597971 Apr 28 04:11:07 PM PDT 24 Apr 28 04:19:10 PM PDT 24 4308597062 ps
T1186 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3727743300 Apr 28 04:15:58 PM PDT 24 Apr 28 04:25:12 PM PDT 24 3246168984 ps
T1187 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.922871922 Apr 28 04:14:13 PM PDT 24 Apr 28 04:26:55 PM PDT 24 4363620557 ps
T678 /workspace/coverage/default/0.chip_sw_plic_sw_irq.840182855 Apr 28 03:53:48 PM PDT 24 Apr 28 03:58:14 PM PDT 24 2757218280 ps
T1188 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2885024846 Apr 28 03:59:25 PM PDT 24 Apr 28 04:57:28 PM PDT 24 32474923364 ps
T744 /workspace/coverage/default/60.chip_sw_all_escalation_resets.136761003 Apr 28 04:22:42 PM PDT 24 Apr 28 04:35:32 PM PDT 24 5126203360 ps
T1189 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3634281624 Apr 28 03:55:20 PM PDT 24 Apr 28 04:04:57 PM PDT 24 4021249604 ps
T52 /workspace/coverage/default/0.chip_jtag_csr_rw.3398484815 Apr 28 03:45:21 PM PDT 24 Apr 28 04:22:12 PM PDT 24 19262091443 ps
T1190 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2371972977 Apr 28 03:57:25 PM PDT 24 Apr 28 04:01:42 PM PDT 24 2894617428 ps
T1191 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3443543641 Apr 28 04:00:18 PM PDT 24 Apr 28 04:05:10 PM PDT 24 2759199538 ps
T1192 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1749012803 Apr 28 03:55:36 PM PDT 24 Apr 28 04:09:17 PM PDT 24 7119016112 ps
T1193 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1302618731 Apr 28 04:13:50 PM PDT 24 Apr 28 04:24:03 PM PDT 24 3610645176 ps
T1194 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1249796375 Apr 28 03:56:53 PM PDT 24 Apr 28 04:07:56 PM PDT 24 4128546136 ps
T1195 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1716223163 Apr 28 04:08:12 PM PDT 24 Apr 28 05:06:39 PM PDT 24 20390271014 ps
T724 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3359186640 Apr 28 04:23:29 PM PDT 24 Apr 28 04:30:55 PM PDT 24 3559651680 ps
T1196 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.885245068 Apr 28 04:11:15 PM PDT 24 Apr 28 04:21:14 PM PDT 24 3464916406 ps
T1197 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2728254690 Apr 28 03:54:39 PM PDT 24 Apr 28 04:45:11 PM PDT 24 10663187296 ps
T1198 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2030819889 Apr 28 03:56:41 PM PDT 24 Apr 28 04:20:34 PM PDT 24 7453572352 ps
T725 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3986071979 Apr 28 04:20:31 PM PDT 24 Apr 28 04:27:40 PM PDT 24 3226056728 ps
T1199 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2736408972 Apr 28 03:52:54 PM PDT 24 Apr 28 03:59:18 PM PDT 24 4051399304 ps
T1200 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.558201710 Apr 28 04:05:36 PM PDT 24 Apr 28 04:32:50 PM PDT 24 8667542450 ps
T1201 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.839920798 Apr 28 03:52:51 PM PDT 24 Apr 28 03:59:34 PM PDT 24 3510536932 ps
T1202 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3522012197 Apr 28 03:55:31 PM PDT 24 Apr 28 04:06:52 PM PDT 24 4451570980 ps
T1203 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.912325889 Apr 28 03:56:43 PM PDT 24 Apr 28 03:59:59 PM PDT 24 2883721880 ps
T800 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2927766801 Apr 28 04:19:53 PM PDT 24 Apr 28 04:29:12 PM PDT 24 5547904330 ps
T1204 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1359621138 Apr 28 04:06:07 PM PDT 24 Apr 28 04:10:42 PM PDT 24 2767273632 ps
T1205 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1876467872 Apr 28 04:08:15 PM PDT 24 Apr 28 04:22:37 PM PDT 24 10525820924 ps
T1206 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2358810367 Apr 28 03:55:13 PM PDT 24 Apr 28 03:58:49 PM PDT 24 2303903999 ps
T1207 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3652564511 Apr 28 04:10:56 PM PDT 24 Apr 28 04:20:31 PM PDT 24 4073784210 ps
T273 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.767737236 Apr 28 04:01:58 PM PDT 24 Apr 28 04:06:21 PM PDT 24 2545259504 ps
T1208 /workspace/coverage/default/29.chip_sw_all_escalation_resets.604322613 Apr 28 04:17:15 PM PDT 24 Apr 28 04:26:30 PM PDT 24 5114691540 ps
T1209 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2677700643 Apr 28 04:04:36 PM PDT 24 Apr 28 04:15:37 PM PDT 24 6118934896 ps
T1210 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.4263582260 Apr 28 03:52:41 PM PDT 24 Apr 28 04:03:35 PM PDT 24 5179600304 ps
T1211 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.793210870 Apr 28 04:09:24 PM PDT 24 Apr 28 04:13:16 PM PDT 24 3785850944 ps
T1212 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3108405200 Apr 28 03:55:27 PM PDT 24 Apr 28 04:06:46 PM PDT 24 4170847350 ps
T1213 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3213700352 Apr 28 04:10:07 PM PDT 24 Apr 28 04:17:23 PM PDT 24 3673336280 ps
T1214 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3364874026 Apr 28 04:08:25 PM PDT 24 Apr 28 05:32:21 PM PDT 24 49481587352 ps
T781 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.714214473 Apr 28 04:20:34 PM PDT 24 Apr 28 04:27:19 PM PDT 24 3761821544 ps
T1215 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4203829523 Apr 28 04:20:38 PM PDT 24 Apr 28 04:27:34 PM PDT 24 3737600138 ps
T736 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.149835545 Apr 28 04:17:30 PM PDT 24 Apr 28 04:24:31 PM PDT 24 3581405288 ps
T1216 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3554458865 Apr 28 04:07:10 PM PDT 24 Apr 28 04:19:06 PM PDT 24 3715399064 ps
T718 /workspace/coverage/default/22.chip_sw_all_escalation_resets.3213327976 Apr 28 04:16:03 PM PDT 24 Apr 28 04:30:20 PM PDT 24 5147243150 ps
T1217 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.924594982 Apr 28 03:55:47 PM PDT 24 Apr 28 03:59:07 PM PDT 24 2229594168 ps
T347 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2680529127 Apr 28 03:56:11 PM PDT 24 Apr 28 04:08:38 PM PDT 24 4507550000 ps
T1218 /workspace/coverage/default/4.chip_tap_straps_prod.1979770889 Apr 28 04:19:40 PM PDT 24 Apr 28 04:21:59 PM PDT 24 2698481204 ps
T1219 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3435234876 Apr 28 04:06:19 PM PDT 24 Apr 28 04:16:11 PM PDT 24 5185659692 ps
T726 /workspace/coverage/default/36.chip_sw_all_escalation_resets.2428283637 Apr 28 04:17:38 PM PDT 24 Apr 28 04:29:40 PM PDT 24 5459985120 ps
T1220 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1782243832 Apr 28 03:53:10 PM PDT 24 Apr 28 04:03:35 PM PDT 24 4458033390 ps
T728 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2450166602 Apr 28 04:19:29 PM PDT 24 Apr 28 04:31:27 PM PDT 24 4648332788 ps
T1221 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2765467350 Apr 28 03:51:25 PM PDT 24 Apr 28 03:53:09 PM PDT 24 1793019154 ps
T1222 /workspace/coverage/default/0.chip_sw_kmac_app_rom.2739125099 Apr 28 03:52:12 PM PDT 24 Apr 28 03:56:22 PM PDT 24 2996732598 ps
T790 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3008064220 Apr 28 04:21:39 PM PDT 24 Apr 28 04:29:44 PM PDT 24 4187318612 ps
T244 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.175457691 Apr 28 03:55:57 PM PDT 24 Apr 28 04:04:41 PM PDT 24 5824110242 ps
T1223 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.408781991 Apr 28 03:56:29 PM PDT 24 Apr 28 04:07:48 PM PDT 24 3998151366 ps
T1224 /workspace/coverage/default/1.chip_tap_straps_testunlock0.4136472942 Apr 28 04:02:19 PM PDT 24 Apr 28 04:10:00 PM PDT 24 4908259477 ps
T274 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3254506856 Apr 28 04:02:25 PM PDT 24 Apr 28 04:06:08 PM PDT 24 2726241211 ps
T371 /workspace/coverage/default/2.chip_jtag_mem_access.3742721287 Apr 28 04:03:18 PM PDT 24 Apr 28 04:29:18 PM PDT 24 13098444260 ps
T1225 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3881242724 Apr 28 03:53:35 PM PDT 24 Apr 28 04:04:09 PM PDT 24 4579566192 ps
T1226 /workspace/coverage/default/1.chip_sw_aon_timer_irq.3469214456 Apr 28 03:58:25 PM PDT 24 Apr 28 04:04:32 PM PDT 24 3397685226 ps
T729 /workspace/coverage/default/62.chip_sw_all_escalation_resets.3145335539 Apr 28 04:20:23 PM PDT 24 Apr 28 04:32:52 PM PDT 24 5417063336 ps
T92 /workspace/coverage/default/31.chip_sw_all_escalation_resets.1262411594 Apr 28 04:18:19 PM PDT 24 Apr 28 04:31:20 PM PDT 24 4483965576 ps
T1227 /workspace/coverage/default/2.chip_sw_csrng_kat_test.2558534872 Apr 28 04:12:50 PM PDT 24 Apr 28 04:16:30 PM PDT 24 2346150680 ps
T1228 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2779713775 Apr 28 04:09:37 PM PDT 24 Apr 28 04:34:11 PM PDT 24 13442652648 ps
T26 /workspace/coverage/default/1.chip_sw_gpio.2235439897 Apr 28 03:55:19 PM PDT 24 Apr 28 04:03:28 PM PDT 24 3732369000 ps
T1229 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3379411655 Apr 28 04:03:00 PM PDT 24 Apr 28 04:38:34 PM PDT 24 22292716055 ps
T1230 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1638458093 Apr 28 03:54:02 PM PDT 24 Apr 28 04:01:01 PM PDT 24 3649384100 ps
T1231 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2098527382 Apr 28 03:52:10 PM PDT 24 Apr 28 04:12:42 PM PDT 24 6093358145 ps
T1232 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.150268316 Apr 28 04:14:23 PM PDT 24 Apr 28 04:44:19 PM PDT 24 8114602641 ps
T1233 /workspace/coverage/default/1.chip_sw_plic_sw_irq.2529580656 Apr 28 04:01:34 PM PDT 24 Apr 28 04:04:55 PM PDT 24 2455431650 ps
T1234 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.672923418 Apr 28 03:57:08 PM PDT 24 Apr 28 04:16:55 PM PDT 24 12378217108 ps
T1235 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3348241577 Apr 28 04:00:54 PM PDT 24 Apr 28 04:47:35 PM PDT 24 23071250779 ps
T1236 /workspace/coverage/default/0.chip_sw_csrng_smoketest.1734015686 Apr 28 03:55:27 PM PDT 24 Apr 28 03:59:02 PM PDT 24 2898260564 ps
T1237 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.4014845892 Apr 28 03:56:38 PM PDT 24 Apr 28 04:02:24 PM PDT 24 4258514712 ps
T1238 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4167088223 Apr 28 03:57:08 PM PDT 24 Apr 28 04:02:14 PM PDT 24 3383436190 ps
T1239 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2155488055 Apr 28 03:53:59 PM PDT 24 Apr 28 05:00:09 PM PDT 24 19559791223 ps
T54 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2435322051 Apr 28 04:06:34 PM PDT 24 Apr 28 04:12:45 PM PDT 24 3610359648 ps
T735 /workspace/coverage/default/21.chip_sw_all_escalation_resets.3514311889 Apr 28 04:16:05 PM PDT 24 Apr 28 04:29:28 PM PDT 24 5609568588 ps
T1240 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1014107854 Apr 28 04:19:04 PM PDT 24 Apr 28 04:26:01 PM PDT 24 4983413774 ps
T1241 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.149302592 Apr 28 04:06:44 PM PDT 24 Apr 28 04:30:00 PM PDT 24 13150432235 ps
T1242 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1781972151 Apr 28 04:09:43 PM PDT 24 Apr 28 04:14:14 PM PDT 24 2384101798 ps
T1243 /workspace/coverage/default/2.chip_tap_straps_prod.239575231 Apr 28 04:10:16 PM PDT 24 Apr 28 04:13:12 PM PDT 24 2473905579 ps
T1244 /workspace/coverage/default/92.chip_sw_all_escalation_resets.2200239760 Apr 28 04:22:24 PM PDT 24 Apr 28 04:32:28 PM PDT 24 4245839856 ps
T690 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2240397186 Apr 28 04:10:38 PM PDT 24 Apr 28 04:37:52 PM PDT 24 18615472782 ps
T1245 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.234162341 Apr 28 04:12:34 PM PDT 24 Apr 28 04:23:29 PM PDT 24 4210170310 ps
T55 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3929960737 Apr 28 03:53:18 PM PDT 24 Apr 28 04:00:08 PM PDT 24 4102035448 ps
T152 /workspace/coverage/default/1.chip_plic_all_irqs_10.3410145365 Apr 28 04:00:15 PM PDT 24 Apr 28 04:09:25 PM PDT 24 3291847620 ps
T1246 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1255095438 Apr 28 04:20:11 PM PDT 24 Apr 28 04:25:27 PM PDT 24 2816534032 ps
T1247 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2775968131 Apr 28 03:52:03 PM PDT 24 Apr 28 04:02:37 PM PDT 24 5685112940 ps
T1248 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1477605666 Apr 28 04:12:08 PM PDT 24 Apr 28 04:17:36 PM PDT 24 2876925660 ps
T1249 /workspace/coverage/default/2.chip_sw_aon_timer_irq.716266370 Apr 28 04:07:59 PM PDT 24 Apr 28 04:13:59 PM PDT 24 3029801174 ps
T1250 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3947770807 Apr 28 03:53:19 PM PDT 24 Apr 28 03:57:36 PM PDT 24 2906478964 ps
T1251 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1900979082 Apr 28 03:56:17 PM PDT 24 Apr 28 04:08:19 PM PDT 24 3942747588 ps
T1252 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3021234127 Apr 28 04:08:31 PM PDT 24 Apr 28 04:17:24 PM PDT 24 4719329813 ps
T1253 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072009371 Apr 28 04:14:02 PM PDT 24 Apr 28 04:21:02 PM PDT 24 3765796982 ps
T155 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.843143043 Apr 28 04:09:56 PM PDT 24 Apr 28 04:14:04 PM PDT 24 3142914499 ps
T1254 /workspace/coverage/default/1.chip_sw_otbn_smoketest.720487427 Apr 28 04:03:51 PM PDT 24 Apr 28 04:32:23 PM PDT 24 8108051296 ps
T335 /workspace/coverage/default/2.chip_sw_alert_test.2471595960 Apr 28 04:09:42 PM PDT 24 Apr 28 04:14:31 PM PDT 24 3358928828 ps
T1255 /workspace/coverage/default/2.chip_sw_aes_masking_off.3305819683 Apr 28 04:10:39 PM PDT 24 Apr 28 04:17:18 PM PDT 24 3001497292 ps
T1256 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1563303705 Apr 28 04:04:01 PM PDT 24 Apr 28 04:07:44 PM PDT 24 3105429448 ps
T1257 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.385055449 Apr 28 03:50:54 PM PDT 24 Apr 28 04:00:35 PM PDT 24 4370027268 ps
T201 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3043451565 Apr 28 03:56:42 PM PDT 24 Apr 28 04:06:36 PM PDT 24 4222164325 ps
T1258 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3363706521 Apr 28 04:08:36 PM PDT 24 Apr 28 04:12:01 PM PDT 24 2588665037 ps
T1259 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.792468314 Apr 28 03:52:33 PM PDT 24 Apr 28 07:16:49 PM PDT 24 255231788344 ps
T767 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1739872247 Apr 28 04:17:37 PM PDT 24 Apr 28 04:25:35 PM PDT 24 3578954944 ps
T76 /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.507161143 Apr 28 04:49:18 PM PDT 24 Apr 28 04:55:16 PM PDT 24 19629404155 ps
T77 /workspace/coverage/cover_reg_top/79.xbar_error_random.3351831865 Apr 28 04:47:22 PM PDT 24 Apr 28 04:48:12 PM PDT 24 598769934 ps
T78 /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.651535284 Apr 28 04:36:42 PM PDT 24 Apr 28 04:37:11 PM PDT 24 249764530 ps
T233 /workspace/coverage/cover_reg_top/0.xbar_smoke.3958546068 Apr 28 04:31:30 PM PDT 24 Apr 28 04:31:38 PM PDT 24 130420175 ps
T234 /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3562016748 Apr 28 04:33:05 PM PDT 24 Apr 28 04:43:56 PM PDT 24 35664438583 ps
T350 /workspace/coverage/cover_reg_top/77.xbar_same_source.993526303 Apr 28 04:46:51 PM PDT 24 Apr 28 04:47:55 PM PDT 24 2153486395 ps
T488 /workspace/coverage/cover_reg_top/91.xbar_smoke.2729985339 Apr 28 04:49:05 PM PDT 24 Apr 28 04:49:11 PM PDT 24 47752371 ps
T476 /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.1864967991 Apr 28 04:38:35 PM PDT 24 Apr 28 04:48:45 PM PDT 24 54078151610 ps
T471 /workspace/coverage/cover_reg_top/48.xbar_stress_all.2574715435 Apr 28 04:41:40 PM PDT 24 Apr 28 04:44:50 PM PDT 24 3821876395 ps
T489 /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.2984728868 Apr 28 04:48:48 PM PDT 24 Apr 28 04:50:22 PM PDT 24 5284882597 ps
T235 /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2316081522 Apr 28 04:34:22 PM PDT 24 Apr 28 04:36:07 PM PDT 24 9676769355 ps
T484 /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1786248079 Apr 28 04:33:14 PM PDT 24 Apr 28 04:35:44 PM PDT 24 351471878 ps
T475 /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.4254496124 Apr 28 04:38:12 PM PDT 24 Apr 28 04:38:35 PM PDT 24 173712649 ps
T487 /workspace/coverage/cover_reg_top/95.xbar_same_source.2933740354 Apr 28 04:49:52 PM PDT 24 Apr 28 04:50:07 PM PDT 24 160491157 ps
T495 /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1989979545 Apr 28 04:34:40 PM PDT 24 Apr 28 04:36:02 PM PDT 24 4633466585 ps
T480 /workspace/coverage/cover_reg_top/33.xbar_same_source.1739921082 Apr 28 04:39:01 PM PDT 24 Apr 28 04:40:12 PM PDT 24 2273310597 ps
T831 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2426453247 Apr 28 04:38:18 PM PDT 24 Apr 28 04:38:50 PM PDT 24 14611509 ps
T493 /workspace/coverage/cover_reg_top/33.xbar_smoke.406043862 Apr 28 04:38:48 PM PDT 24 Apr 28 04:38:58 PM PDT 24 224936076 ps
T478 /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.494610110 Apr 28 04:34:56 PM PDT 24 Apr 28 04:47:57 PM PDT 24 42098344594 ps
T486 /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.1082834682 Apr 28 04:43:16 PM PDT 24 Apr 28 04:44:46 PM PDT 24 8336207760 ps
T485 /workspace/coverage/cover_reg_top/96.xbar_same_source.1308980468 Apr 28 04:50:01 PM PDT 24 Apr 28 04:50:28 PM PDT 24 866071729 ps
T494 /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.4098945501 Apr 28 04:47:20 PM PDT 24 Apr 28 04:48:58 PM PDT 24 5559043673 ps
T367 /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.1190274752 Apr 28 04:40:20 PM PDT 24 Apr 28 05:01:00 PM PDT 24 70176001473 ps
T385 /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.4134442564 Apr 28 04:44:44 PM PDT 24 Apr 28 04:44:57 PM PDT 24 247017000 ps
T497 /workspace/coverage/cover_reg_top/81.xbar_smoke.34190516 Apr 28 04:47:26 PM PDT 24 Apr 28 04:47:34 PM PDT 24 147214069 ps
T386 /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.209802788 Apr 28 04:49:35 PM PDT 24 Apr 28 04:58:37 PM PDT 24 17353964527 ps
T461 /workspace/coverage/cover_reg_top/58.xbar_same_source.2333941029 Apr 28 04:43:24 PM PDT 24 Apr 28 04:43:59 PM PDT 24 1094276770 ps
T481 /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.764707244 Apr 28 04:42:12 PM PDT 24 Apr 28 04:48:27 PM PDT 24 22125571687 ps
T483 /workspace/coverage/cover_reg_top/28.xbar_same_source.618501832 Apr 28 04:37:58 PM PDT 24 Apr 28 04:38:12 PM PDT 24 134016509 ps
T479 /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.2192039336 Apr 28 04:44:54 PM PDT 24 Apr 28 04:55:44 PM PDT 24 36331822425 ps
T498 /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.1561540286 Apr 28 04:40:56 PM PDT 24 Apr 28 04:42:18 PM PDT 24 7595408706 ps
T499 /workspace/coverage/cover_reg_top/90.xbar_access_same_device.3312423130 Apr 28 04:49:03 PM PDT 24 Apr 28 04:49:46 PM PDT 24 943798756 ps
T496 /workspace/coverage/cover_reg_top/10.xbar_random.943729775 Apr 28 04:33:04 PM PDT 24 Apr 28 04:33:17 PM PDT 24 104963070 ps
T477 /workspace/coverage/cover_reg_top/22.chip_tl_errors.3505582345 Apr 28 04:36:20 PM PDT 24 Apr 28 04:39:49 PM PDT 24 3140795144 ps
T649 /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1406586623 Apr 28 04:46:43 PM PDT 24 Apr 28 04:46:56 PM PDT 24 209112536 ps
T561 /workspace/coverage/cover_reg_top/23.xbar_smoke.2519892664 Apr 28 04:36:33 PM PDT 24 Apr 28 04:36:40 PM PDT 24 46741755 ps
T490 /workspace/coverage/cover_reg_top/84.xbar_access_same_device.2090430633 Apr 28 04:48:01 PM PDT 24 Apr 28 04:48:26 PM PDT 24 298753676 ps
T482 /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.793851080 Apr 28 04:34:54 PM PDT 24 Apr 28 04:48:42 PM PDT 24 71556103190 ps
T599 /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.1985621179 Apr 28 04:43:34 PM PDT 24 Apr 28 04:43:49 PM PDT 24 124647458 ps
T491 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3414519022 Apr 28 04:33:59 PM PDT 24 Apr 28 04:43:22 PM PDT 24 4187450570 ps
T589 /workspace/coverage/cover_reg_top/17.xbar_same_source.4086253922 Apr 28 04:34:54 PM PDT 24 Apr 28 04:35:40 PM PDT 24 1301517223 ps
T525 /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.3600375180 Apr 28 04:49:49 PM PDT 24 Apr 28 04:50:02 PM PDT 24 104835810 ps
T363 /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.4244695293 Apr 28 04:45:45 PM PDT 24 Apr 28 04:46:35 PM PDT 24 586012282 ps
T492 /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1860438892 Apr 28 04:40:52 PM PDT 24 Apr 28 05:28:41 PM PDT 24 160184472475 ps
T549 /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1307541120 Apr 28 04:46:51 PM PDT 24 Apr 28 04:47:20 PM PDT 24 221888358 ps
T586 /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3347502496 Apr 28 04:43:44 PM PDT 24 Apr 28 04:50:39 PM PDT 24 39434112872 ps
T523 /workspace/coverage/cover_reg_top/72.xbar_same_source.2236529106 Apr 28 04:45:57 PM PDT 24 Apr 28 04:46:29 PM PDT 24 932600756 ps
T390 /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.3764371757 Apr 28 04:44:56 PM PDT 24 Apr 28 04:45:16 PM PDT 24 172757668 ps
T470 /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.2693261685 Apr 28 04:31:50 PM PDT 24 Apr 28 04:31:57 PM PDT 24 44552128 ps
T364 /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1895425407 Apr 28 04:48:01 PM PDT 24 Apr 28 04:49:27 PM PDT 24 8103065491 ps
T402 /workspace/coverage/cover_reg_top/88.xbar_stress_all.605128213 Apr 28 04:48:45 PM PDT 24 Apr 28 04:50:50 PM PDT 24 3765698975 ps
T366 /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.699206914 Apr 28 04:39:56 PM PDT 24 Apr 28 05:15:12 PM PDT 24 111201323566 ps
T419 /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1375241579 Apr 28 04:42:25 PM PDT 24 Apr 28 04:48:08 PM PDT 24 2794747205 ps
T698 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3893714200 Apr 28 04:45:54 PM PDT 24 Apr 28 04:46:47 PM PDT 24 493757048 ps
T429 /workspace/coverage/cover_reg_top/12.xbar_smoke.2971008146 Apr 28 04:33:38 PM PDT 24 Apr 28 04:33:48 PM PDT 24 192402679 ps
T1260 /workspace/coverage/cover_reg_top/46.xbar_smoke.3252100585 Apr 28 04:41:07 PM PDT 24 Apr 28 04:41:17 PM PDT 24 189509416 ps
T564 /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.1495827431 Apr 28 04:44:24 PM PDT 24 Apr 28 04:45:12 PM PDT 24 1109648823 ps
T414 /workspace/coverage/cover_reg_top/27.xbar_random.1895851401 Apr 28 04:37:44 PM PDT 24 Apr 28 04:38:25 PM PDT 24 1195895351 ps
T539 /workspace/coverage/cover_reg_top/11.xbar_stress_all.900872406 Apr 28 04:33:26 PM PDT 24 Apr 28 04:34:36 PM PDT 24 755950628 ps
T614 /workspace/coverage/cover_reg_top/43.xbar_smoke.1457544846 Apr 28 04:40:36 PM PDT 24 Apr 28 04:40:44 PM PDT 24 48922274 ps
T810 /workspace/coverage/cover_reg_top/12.xbar_access_same_device.3932322301 Apr 28 04:33:38 PM PDT 24 Apr 28 04:35:30 PM PDT 24 1327743525 ps
T666 /workspace/coverage/cover_reg_top/92.xbar_smoke.1009531329 Apr 28 04:49:10 PM PDT 24 Apr 28 04:49:18 PM PDT 24 180736826 ps
T1261 /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2722672752 Apr 28 04:37:43 PM PDT 24 Apr 28 04:37:54 PM PDT 24 139244277 ps
T801 /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3026017637 Apr 28 04:45:44 PM PDT 24 Apr 28 04:46:28 PM PDT 24 865325257 ps
T647 /workspace/coverage/cover_reg_top/66.xbar_error_random.1841006142 Apr 28 04:44:54 PM PDT 24 Apr 28 04:46:24 PM PDT 24 2384519674 ps
T510 /workspace/coverage/cover_reg_top/65.xbar_random.2551808505 Apr 28 04:44:37 PM PDT 24 Apr 28 04:45:54 PM PDT 24 1819897533 ps
T1262 /workspace/coverage/cover_reg_top/65.xbar_smoke.279285283 Apr 28 04:44:34 PM PDT 24 Apr 28 04:44:43 PM PDT 24 173266198 ps
T597 /workspace/coverage/cover_reg_top/43.xbar_random.3791971066 Apr 28 04:40:42 PM PDT 24 Apr 28 04:41:15 PM PDT 24 847023499 ps
T513 /workspace/coverage/cover_reg_top/17.xbar_random.3765794785 Apr 28 04:34:55 PM PDT 24 Apr 28 04:35:51 PM PDT 24 1397603878 ps
T648 /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.331703969 Apr 28 04:37:55 PM PDT 24 Apr 28 04:40:29 PM PDT 24 1904294174 ps
T412 /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.462137748 Apr 28 04:42:27 PM PDT 24 Apr 28 04:57:53 PM PDT 24 82353069733 ps
T1263 /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.3758772564 Apr 28 04:39:38 PM PDT 24 Apr 28 04:39:44 PM PDT 24 45359995 ps
T692 /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1478011411 Apr 28 04:48:13 PM PDT 24 Apr 28 04:48:21 PM PDT 24 52942540 ps
T389 /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.1951745995 Apr 28 04:42:51 PM PDT 24 Apr 28 04:49:40 PM PDT 24 22210658875 ps
T667 /workspace/coverage/cover_reg_top/5.xbar_access_same_device.2401745894 Apr 28 04:31:53 PM PDT 24 Apr 28 04:33:18 PM PDT 24 1718951381 ps
T582 /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.867687607 Apr 28 04:38:00 PM PDT 24 Apr 28 04:39:21 PM PDT 24 7852123212 ps
T825 /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1744792164 Apr 28 04:47:42 PM PDT 24 Apr 28 04:58:32 PM PDT 24 37428498156 ps
T566 /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3722469335 Apr 28 04:48:05 PM PDT 24 Apr 28 04:48:24 PM PDT 24 161667211 ps
T455 /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.3822245915 Apr 28 04:45:40 PM PDT 24 Apr 28 04:48:34 PM PDT 24 15502687636 ps
T652 /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2505803133 Apr 28 04:48:11 PM PDT 24 Apr 28 04:48:55 PM PDT 24 918633623 ps
T593 /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2651929446 Apr 28 04:35:43 PM PDT 24 Apr 28 04:35:50 PM PDT 24 45923869 ps
T400 /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.1856243300 Apr 28 04:48:05 PM PDT 24 Apr 28 04:48:56 PM PDT 24 529326125 ps
T1264 /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.405896275 Apr 28 04:45:40 PM PDT 24 Apr 28 04:46:02 PM PDT 24 174691730 ps
T500 /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.841446908 Apr 28 04:31:43 PM PDT 24 Apr 28 04:41:19 PM PDT 24 5652184447 ps
T1265 /workspace/coverage/cover_reg_top/79.xbar_smoke.440459818 Apr 28 04:47:04 PM PDT 24 Apr 28 04:47:12 PM PDT 24 140307542 ps
T142 /workspace/coverage/cover_reg_top/1.chip_csr_rw.212830260 Apr 28 04:31:39 PM PDT 24 Apr 28 04:38:06 PM PDT 24 4559066337 ps
T392 /workspace/coverage/cover_reg_top/46.xbar_access_same_device.1594121686 Apr 28 04:41:13 PM PDT 24 Apr 28 04:42:28 PM PDT 24 789764999 ps
T1266 /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.4156839380 Apr 28 04:45:47 PM PDT 24 Apr 28 04:46:11 PM PDT 24 508860583 ps
T530 /workspace/coverage/cover_reg_top/29.xbar_random.3558027805 Apr 28 04:38:01 PM PDT 24 Apr 28 04:38:32 PM PDT 24 296372187 ps
T1267 /workspace/coverage/cover_reg_top/38.xbar_smoke.1716706127 Apr 28 04:39:36 PM PDT 24 Apr 28 04:39:43 PM PDT 24 52824608 ps
T1268 /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2463636333 Apr 28 04:43:03 PM PDT 24 Apr 28 04:43:25 PM PDT 24 152630459 ps
T1269 /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2794123933 Apr 28 04:36:56 PM PDT 24 Apr 28 04:37:13 PM PDT 24 108413246 ps
T588 /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.2699453424 Apr 28 04:44:13 PM PDT 24 Apr 28 04:53:56 PM PDT 24 53760360010 ps
T456 /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.3727493547 Apr 28 04:48:41 PM PDT 24 Apr 28 04:50:16 PM PDT 24 8871325833 ps
T691 /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.1465013653 Apr 28 04:49:42 PM PDT 24 Apr 28 04:51:36 PM PDT 24 6177454682 ps
T388 /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1973149072 Apr 28 04:38:52 PM PDT 24 Apr 28 05:21:28 PM PDT 24 140090067165 ps
T143 /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3285682161 Apr 28 04:31:57 PM PDT 24 Apr 28 05:28:53 PM PDT 24 32537476228 ps
T579 /workspace/coverage/cover_reg_top/86.xbar_same_source.2599729699 Apr 28 04:48:25 PM PDT 24 Apr 28 04:49:04 PM PDT 24 1125885113 ps
T453 /workspace/coverage/cover_reg_top/89.xbar_same_source.2358282176 Apr 28 04:48:51 PM PDT 24 Apr 28 04:49:43 PM PDT 24 1554143048 ps
T391 /workspace/coverage/cover_reg_top/45.xbar_stress_all.122801661 Apr 28 04:41:06 PM PDT 24 Apr 28 04:53:35 PM PDT 24 17765909551 ps
T501 /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3183357383 Apr 28 04:39:16 PM PDT 24 Apr 28 04:57:04 PM PDT 24 63477422223 ps
T653 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2121139652 Apr 28 04:47:53 PM PDT 24 Apr 28 04:48:43 PM PDT 24 610033070 ps
T1270 /workspace/coverage/cover_reg_top/44.xbar_error_random.3524028575 Apr 28 04:40:53 PM PDT 24 Apr 28 04:41:11 PM PDT 24 170822055 ps
T451 /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.25943039 Apr 28 04:48:58 PM PDT 24 Apr 28 04:49:05 PM PDT 24 34582022 ps
T584 /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.2542179339 Apr 28 04:39:41 PM PDT 24 Apr 28 04:39:51 PM PDT 24 55616153 ps
T1271 /workspace/coverage/cover_reg_top/98.xbar_random.872528882 Apr 28 04:50:23 PM PDT 24 Apr 28 04:50:30 PM PDT 24 34560800 ps
T613 /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1908406358 Apr 28 04:31:54 PM PDT 24 Apr 28 04:49:24 PM PDT 24 55209889643 ps
T650 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.2591109488 Apr 28 04:45:29 PM PDT 24 Apr 28 04:47:05 PM PDT 24 1240634128 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%