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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.34 95.50 94.59 95.66 95.37 97.38 99.57


Total test records in report: 2792
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T1003 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1848308540 Apr 28 04:02:34 PM PDT 24 Apr 28 04:12:13 PM PDT 24 4284142948 ps
T133 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3949260068 Apr 28 04:10:07 PM PDT 24 Apr 28 04:23:21 PM PDT 24 6132018984 ps
T1004 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3421013624 Apr 28 04:14:43 PM PDT 24 Apr 28 04:26:11 PM PDT 24 6801303708 ps
T740 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2111139190 Apr 28 04:20:06 PM PDT 24 Apr 28 04:26:41 PM PDT 24 3422324808 ps
T1005 /workspace/coverage/default/2.chip_sw_aes_entropy.1660305794 Apr 28 04:08:45 PM PDT 24 Apr 28 04:12:40 PM PDT 24 2722958360 ps
T1006 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.669095747 Apr 28 03:58:39 PM PDT 24 Apr 28 04:03:18 PM PDT 24 2845632853 ps
T1007 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2411656024 Apr 28 04:11:30 PM PDT 24 Apr 28 04:17:18 PM PDT 24 2695508678 ps
T216 /workspace/coverage/default/1.chip_sw_flash_init.2667568384 Apr 28 03:54:06 PM PDT 24 Apr 28 04:37:15 PM PDT 24 20760920478 ps
T1008 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.419476118 Apr 28 04:13:41 PM PDT 24 Apr 28 04:30:20 PM PDT 24 10065182082 ps
T21 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3608259611 Apr 28 03:57:37 PM PDT 24 Apr 28 04:30:52 PM PDT 24 24224114508 ps
T1009 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1988235777 Apr 28 03:52:23 PM PDT 24 Apr 28 03:55:37 PM PDT 24 2636645030 ps
T746 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.288569700 Apr 28 04:21:19 PM PDT 24 Apr 28 04:29:56 PM PDT 24 3707719944 ps
T1010 /workspace/coverage/default/0.chip_sw_example_flash.411077250 Apr 28 03:52:34 PM PDT 24 Apr 28 03:56:42 PM PDT 24 2770543666 ps
T1011 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2522442710 Apr 28 03:57:17 PM PDT 24 Apr 28 04:16:09 PM PDT 24 7163408900 ps
T775 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.951473772 Apr 28 04:19:06 PM PDT 24 Apr 28 04:25:07 PM PDT 24 3400865750 ps
T1012 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4275426585 Apr 28 04:12:39 PM PDT 24 Apr 28 04:18:52 PM PDT 24 4128793348 ps
T1013 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2966761294 Apr 28 04:04:25 PM PDT 24 Apr 28 04:09:53 PM PDT 24 3121388096 ps
T1014 /workspace/coverage/default/2.chip_sw_kmac_smoketest.4177950292 Apr 28 04:11:27 PM PDT 24 Apr 28 04:17:56 PM PDT 24 2765008496 ps
T1015 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4138894861 Apr 28 03:58:29 PM PDT 24 Apr 28 04:03:44 PM PDT 24 2727220070 ps
T1016 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1658355475 Apr 28 03:54:38 PM PDT 24 Apr 28 04:00:13 PM PDT 24 3662650545 ps
T1017 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3917783627 Apr 28 03:56:07 PM PDT 24 Apr 28 04:58:38 PM PDT 24 37105606344 ps
T743 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2456693839 Apr 28 04:21:29 PM PDT 24 Apr 28 04:33:40 PM PDT 24 5346608714 ps
T34 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3258611551 Apr 28 03:55:58 PM PDT 24 Apr 28 03:59:25 PM PDT 24 2715663872 ps
T249 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3111554690 Apr 28 03:57:04 PM PDT 24 Apr 28 03:59:52 PM PDT 24 3615637675 ps
T713 /workspace/coverage/default/55.chip_sw_all_escalation_resets.2942869651 Apr 28 04:19:16 PM PDT 24 Apr 28 04:32:37 PM PDT 24 5715145368 ps
T1018 /workspace/coverage/default/0.chip_sw_edn_kat.685450061 Apr 28 03:54:02 PM PDT 24 Apr 28 04:03:26 PM PDT 24 3508821784 ps
T1019 /workspace/coverage/default/2.chip_sw_edn_sw_mode.4014332022 Apr 28 04:09:14 PM PDT 24 Apr 28 04:48:58 PM PDT 24 9903816856 ps
T741 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.938062708 Apr 28 04:15:58 PM PDT 24 Apr 28 04:25:34 PM PDT 24 3958801310 ps
T1020 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.219317790 Apr 28 04:09:02 PM PDT 24 Apr 28 04:21:31 PM PDT 24 7269974792 ps
T1021 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3664458509 Apr 28 04:09:47 PM PDT 24 Apr 28 04:16:06 PM PDT 24 4087093040 ps
T660 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.852226619 Apr 28 04:06:29 PM PDT 24 Apr 28 04:08:19 PM PDT 24 1735505526 ps
T199 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1490957576 Apr 28 03:51:40 PM PDT 24 Apr 28 04:00:02 PM PDT 24 4989019813 ps
T140 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3652261567 Apr 28 03:53:43 PM PDT 24 Apr 28 03:56:30 PM PDT 24 2543368455 ps
T656 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2729177528 Apr 28 04:02:45 PM PDT 24 Apr 28 04:09:43 PM PDT 24 5407785014 ps
T1022 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3174510388 Apr 28 04:08:47 PM PDT 24 Apr 28 04:25:20 PM PDT 24 9307050944 ps
T758 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.107193096 Apr 28 04:19:47 PM PDT 24 Apr 28 04:26:46 PM PDT 24 3760008970 ps
T644 /workspace/coverage/default/1.chip_sw_edn_boot_mode.1970887946 Apr 28 03:57:07 PM PDT 24 Apr 28 04:06:58 PM PDT 24 3523664540 ps
T1023 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1604446388 Apr 28 03:56:20 PM PDT 24 Apr 28 04:02:27 PM PDT 24 3867851830 ps
T1024 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2679746016 Apr 28 04:07:47 PM PDT 24 Apr 28 04:17:07 PM PDT 24 5733800706 ps
T1025 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3252786903 Apr 28 04:15:50 PM PDT 24 Apr 28 04:20:05 PM PDT 24 3055187720 ps
T641 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1271994113 Apr 28 04:11:02 PM PDT 24 Apr 28 06:20:11 PM PDT 24 36019275001 ps
T227 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1097415781 Apr 28 04:02:55 PM PDT 24 Apr 28 04:06:24 PM PDT 24 2597816684 ps
T1026 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.572730178 Apr 28 04:03:50 PM PDT 24 Apr 28 04:11:21 PM PDT 24 4484767556 ps
T295 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3694765116 Apr 28 04:07:19 PM PDT 24 Apr 28 04:20:23 PM PDT 24 4060998949 ps
T1027 /workspace/coverage/default/1.chip_sw_aes_idle.3028249238 Apr 28 03:57:08 PM PDT 24 Apr 28 04:00:15 PM PDT 24 2834897780 ps
T1028 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1522668630 Apr 28 03:56:45 PM PDT 24 Apr 28 04:04:26 PM PDT 24 4353791656 ps
T1029 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.162331804 Apr 28 03:57:07 PM PDT 24 Apr 28 04:03:35 PM PDT 24 5028003600 ps
T276 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1192504624 Apr 28 04:12:19 PM PDT 24 Apr 28 04:23:03 PM PDT 24 8875566686 ps
T1030 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.386294163 Apr 28 04:06:10 PM PDT 24 Apr 28 04:16:19 PM PDT 24 3647244240 ps
T1031 /workspace/coverage/default/1.chip_sw_kmac_entropy.1931035262 Apr 28 03:57:52 PM PDT 24 Apr 28 04:03:17 PM PDT 24 2903282780 ps
T776 /workspace/coverage/default/26.chip_sw_all_escalation_resets.4294911211 Apr 28 04:17:23 PM PDT 24 Apr 28 04:26:08 PM PDT 24 4776362240 ps
T765 /workspace/coverage/default/84.chip_sw_all_escalation_resets.825371309 Apr 28 04:22:54 PM PDT 24 Apr 28 04:37:29 PM PDT 24 5486312496 ps
T661 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3057493917 Apr 28 03:57:07 PM PDT 24 Apr 28 03:58:48 PM PDT 24 2182337018 ps
T1032 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2730593485 Apr 28 03:59:44 PM PDT 24 Apr 28 04:09:40 PM PDT 24 5363459684 ps
T721 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3976882768 Apr 28 04:14:15 PM PDT 24 Apr 28 04:26:18 PM PDT 24 5786719454 ps
T1033 /workspace/coverage/default/2.chip_tap_straps_testunlock0.2155617757 Apr 28 04:11:34 PM PDT 24 Apr 28 04:18:36 PM PDT 24 4803542621 ps
T1034 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.433305940 Apr 28 04:02:38 PM PDT 24 Apr 28 04:12:04 PM PDT 24 3380814456 ps
T1035 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1357757004 Apr 28 03:56:32 PM PDT 24 Apr 28 04:15:05 PM PDT 24 6009803856 ps
T1036 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3675707781 Apr 28 04:20:59 PM PDT 24 Apr 28 04:32:08 PM PDT 24 6250988520 ps
T706 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.889181585 Apr 28 04:21:34 PM PDT 24 Apr 28 04:29:09 PM PDT 24 3684183360 ps
T1037 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.732484407 Apr 28 04:17:42 PM PDT 24 Apr 28 04:25:03 PM PDT 24 4254565024 ps
T346 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3208398877 Apr 28 04:12:06 PM PDT 24 Apr 28 04:14:03 PM PDT 24 2608358008 ps
T715 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1755557752 Apr 28 04:18:44 PM PDT 24 Apr 28 04:27:26 PM PDT 24 4017158620 ps
T727 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2673406129 Apr 28 04:16:10 PM PDT 24 Apr 28 04:23:45 PM PDT 24 4405144656 ps
T1038 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2641017481 Apr 28 04:11:28 PM PDT 24 Apr 28 04:20:12 PM PDT 24 4660300416 ps
T1039 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3879172108 Apr 28 03:58:56 PM PDT 24 Apr 28 05:14:28 PM PDT 24 16993492944 ps
T1040 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3628492715 Apr 28 04:20:36 PM PDT 24 Apr 28 04:29:06 PM PDT 24 4133839288 ps
T798 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2336080624 Apr 28 04:22:20 PM PDT 24 Apr 28 04:28:18 PM PDT 24 3789963990 ps
T1041 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.470628636 Apr 28 04:14:06 PM PDT 24 Apr 28 04:41:51 PM PDT 24 8195726400 ps
T209 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3387912748 Apr 28 04:09:58 PM PDT 24 Apr 28 04:17:37 PM PDT 24 4175014430 ps
T1042 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2181913122 Apr 28 04:24:34 PM PDT 24 Apr 28 04:38:44 PM PDT 24 11949349278 ps
T750 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382252016 Apr 28 04:16:21 PM PDT 24 Apr 28 04:24:45 PM PDT 24 3801438744 ps
T662 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.4151416605 Apr 28 04:01:58 PM PDT 24 Apr 28 04:04:05 PM PDT 24 2656337765 ps
T1043 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4233011478 Apr 28 04:09:19 PM PDT 24 Apr 28 04:24:42 PM PDT 24 5764438657 ps
T1044 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2504417908 Apr 28 04:15:27 PM PDT 24 Apr 28 04:32:09 PM PDT 24 9140518408 ps
T1045 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3706031888 Apr 28 04:21:46 PM PDT 24 Apr 28 04:35:41 PM PDT 24 6289988200 ps
T74 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.264156886 Apr 28 03:55:11 PM PDT 24 Apr 28 04:04:27 PM PDT 24 3750776136 ps
T677 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3460560066 Apr 28 03:58:13 PM PDT 24 Apr 28 04:02:52 PM PDT 24 2706962928 ps
T304 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2337727328 Apr 28 03:51:29 PM PDT 24 Apr 28 04:07:24 PM PDT 24 5327977942 ps
T264 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2855661905 Apr 28 03:51:49 PM PDT 24 Apr 28 04:02:21 PM PDT 24 5841870242 ps
T1046 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1847295143 Apr 28 03:53:34 PM PDT 24 Apr 28 03:58:40 PM PDT 24 3116230907 ps
T1047 /workspace/coverage/default/1.chip_sw_csrng_kat_test.959141347 Apr 28 03:58:44 PM PDT 24 Apr 28 04:02:25 PM PDT 24 2297063598 ps
T732 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2076023900 Apr 28 04:15:40 PM PDT 24 Apr 28 04:23:48 PM PDT 24 4149278688 ps
T1048 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.651581461 Apr 28 04:14:22 PM PDT 24 Apr 28 04:21:37 PM PDT 24 4250301323 ps
T1049 /workspace/coverage/default/0.chip_sw_aes_idle.2447706797 Apr 28 03:51:54 PM PDT 24 Apr 28 03:56:53 PM PDT 24 2944645370 ps
T1050 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2005368953 Apr 28 03:51:15 PM PDT 24 Apr 28 04:17:40 PM PDT 24 12042231806 ps
T200 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4200298441 Apr 28 04:07:09 PM PDT 24 Apr 28 04:16:29 PM PDT 24 4439561253 ps
T759 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1325201894 Apr 28 04:18:58 PM PDT 24 Apr 28 04:24:59 PM PDT 24 3587656378 ps
T1051 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2485224084 Apr 28 03:58:42 PM PDT 24 Apr 28 04:08:10 PM PDT 24 5887802904 ps
T1052 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3759780018 Apr 28 04:07:55 PM PDT 24 Apr 28 05:15:46 PM PDT 24 18481309548 ps
T722 /workspace/coverage/default/89.chip_sw_all_escalation_resets.1351086106 Apr 28 04:22:23 PM PDT 24 Apr 28 04:31:13 PM PDT 24 4553440406 ps
T42 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3927326833 Apr 28 04:01:15 PM PDT 24 Apr 28 08:29:41 PM PDT 24 79650909624 ps
T787 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1137116839 Apr 28 04:23:03 PM PDT 24 Apr 28 04:32:33 PM PDT 24 4916170746 ps
T1053 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3033300803 Apr 28 03:52:23 PM PDT 24 Apr 28 04:19:37 PM PDT 24 15631668959 ps
T473 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.185808453 Apr 28 04:09:29 PM PDT 24 Apr 28 04:26:18 PM PDT 24 4654329558 ps
T36 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2094954600 Apr 28 04:08:16 PM PDT 24 Apr 28 04:15:47 PM PDT 24 4245738146 ps
T1054 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3587260530 Apr 28 04:10:04 PM PDT 24 Apr 28 04:15:57 PM PDT 24 4888282106 ps
T172 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3394807887 Apr 28 04:12:58 PM PDT 24 Apr 28 04:17:47 PM PDT 24 3239984360 ps
T779 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3179059835 Apr 28 04:18:02 PM PDT 24 Apr 28 04:24:59 PM PDT 24 3348649816 ps
T1055 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.360409734 Apr 28 04:11:02 PM PDT 24 Apr 28 04:23:27 PM PDT 24 4867835682 ps
T1056 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2427125020 Apr 28 04:06:36 PM PDT 24 Apr 28 04:56:32 PM PDT 24 25528911632 ps
T1057 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3844043287 Apr 28 03:53:32 PM PDT 24 Apr 28 04:42:01 PM PDT 24 24508223289 ps
T1058 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1587228035 Apr 28 03:56:47 PM PDT 24 Apr 28 04:15:44 PM PDT 24 14627823594 ps
T308 /workspace/coverage/default/2.chip_sw_pattgen_ios.3269044248 Apr 28 04:06:10 PM PDT 24 Apr 28 04:09:16 PM PDT 24 2124800000 ps
T1059 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3983185093 Apr 28 04:08:00 PM PDT 24 Apr 28 04:16:08 PM PDT 24 4021873366 ps
T1060 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.877439741 Apr 28 04:14:26 PM PDT 24 Apr 28 04:59:05 PM PDT 24 12966401948 ps
T1061 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2838057422 Apr 28 04:12:23 PM PDT 24 Apr 28 04:22:08 PM PDT 24 4580766404 ps
T151 /workspace/coverage/default/2.chip_plic_all_irqs_10.2002125031 Apr 28 04:10:12 PM PDT 24 Apr 28 04:21:33 PM PDT 24 4398977416 ps
T1062 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.708253214 Apr 28 03:53:33 PM PDT 24 Apr 28 03:59:22 PM PDT 24 3256349868 ps
T365 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3391414327 Apr 28 03:53:26 PM PDT 24 Apr 28 04:01:02 PM PDT 24 4700318964 ps
T1063 /workspace/coverage/default/0.chip_sw_kmac_entropy.1506151605 Apr 28 03:49:49 PM PDT 24 Apr 28 03:53:18 PM PDT 24 2618870276 ps
T1064 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.344990289 Apr 28 04:01:50 PM PDT 24 Apr 28 04:04:53 PM PDT 24 2638764605 ps
T769 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761993751 Apr 28 04:20:38 PM PDT 24 Apr 28 04:26:42 PM PDT 24 3631259218 ps
T794 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1142219749 Apr 28 04:21:41 PM PDT 24 Apr 28 04:30:56 PM PDT 24 4060551062 ps
T1065 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3397677498 Apr 28 04:01:22 PM PDT 24 Apr 28 05:45:40 PM PDT 24 49699127752 ps
T694 /workspace/coverage/default/1.chip_sw_pattgen_ios.2181385121 Apr 28 03:57:46 PM PDT 24 Apr 28 04:02:46 PM PDT 24 3222865748 ps
T788 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3840795739 Apr 28 04:20:33 PM PDT 24 Apr 28 04:31:49 PM PDT 24 4733683488 ps
T1066 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1444447133 Apr 28 04:02:10 PM PDT 24 Apr 28 04:05:50 PM PDT 24 2678308253 ps
T1067 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.358761358 Apr 28 04:09:30 PM PDT 24 Apr 28 04:16:44 PM PDT 24 4726963194 ps
T1068 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3012873593 Apr 28 04:13:08 PM PDT 24 Apr 28 04:17:59 PM PDT 24 3205222312 ps
T1069 /workspace/coverage/default/35.chip_sw_all_escalation_resets.832642523 Apr 28 04:17:45 PM PDT 24 Apr 28 04:25:23 PM PDT 24 4466776664 ps
T786 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770532072 Apr 28 04:18:02 PM PDT 24 Apr 28 04:24:27 PM PDT 24 3432853200 ps
T1070 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2914793397 Apr 28 04:07:51 PM PDT 24 Apr 28 04:16:55 PM PDT 24 4602650268 ps
T734 /workspace/coverage/default/42.chip_sw_all_escalation_resets.2638024909 Apr 28 04:18:39 PM PDT 24 Apr 28 04:30:33 PM PDT 24 5888229848 ps
T270 /workspace/coverage/default/87.chip_sw_all_escalation_resets.4147102211 Apr 28 04:23:37 PM PDT 24 Apr 28 04:35:09 PM PDT 24 5044164200 ps
T1071 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.316629656 Apr 28 03:58:55 PM PDT 24 Apr 28 04:03:03 PM PDT 24 2664781361 ps
T37 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2281508008 Apr 28 03:59:33 PM PDT 24 Apr 28 04:05:51 PM PDT 24 5573078458 ps
T217 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2632202368 Apr 28 03:55:35 PM PDT 24 Apr 28 05:36:33 PM PDT 24 48276931526 ps
T1072 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.822490858 Apr 28 04:09:27 PM PDT 24 Apr 28 05:10:26 PM PDT 24 15490575750 ps
T53 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2828252798 Apr 28 03:55:30 PM PDT 24 Apr 28 04:01:44 PM PDT 24 3740501192 ps
T1073 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.4273477153 Apr 28 03:53:22 PM PDT 24 Apr 28 03:57:55 PM PDT 24 2779614104 ps
T25 /workspace/coverage/default/2.chip_sw_gpio.927690367 Apr 28 04:06:22 PM PDT 24 Apr 28 04:15:50 PM PDT 24 4711165218 ps
T1074 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3066483991 Apr 28 04:19:53 PM PDT 24 Apr 28 04:30:39 PM PDT 24 3996826340 ps
T1075 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.317660675 Apr 28 04:15:37 PM PDT 24 Apr 28 04:26:14 PM PDT 24 4696022760 ps
T1076 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.827481150 Apr 28 04:14:55 PM PDT 24 Apr 28 04:22:24 PM PDT 24 4966757020 ps
T771 /workspace/coverage/default/67.chip_sw_all_escalation_resets.1085877011 Apr 28 04:19:45 PM PDT 24 Apr 28 04:33:41 PM PDT 24 6674848152 ps
T1077 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2831440553 Apr 28 04:13:35 PM PDT 24 Apr 28 04:27:37 PM PDT 24 8831516692 ps
T1078 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.491128235 Apr 28 04:04:05 PM PDT 24 Apr 28 04:08:19 PM PDT 24 3307808780 ps
T1079 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2459508355 Apr 28 04:08:49 PM PDT 24 Apr 28 04:46:28 PM PDT 24 31351819498 ps
T1080 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2053046273 Apr 28 04:12:21 PM PDT 24 Apr 28 04:23:39 PM PDT 24 5212155550 ps
T1081 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2054339995 Apr 28 04:07:38 PM PDT 24 Apr 28 04:15:58 PM PDT 24 6636686126 ps
T1082 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.821777609 Apr 28 04:11:09 PM PDT 24 Apr 28 04:19:25 PM PDT 24 2880790536 ps
T333 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2257008053 Apr 28 04:19:39 PM PDT 24 Apr 28 04:26:26 PM PDT 24 4013667280 ps
T1083 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.155615451 Apr 28 03:53:32 PM PDT 24 Apr 28 03:59:46 PM PDT 24 4879344143 ps
T1084 /workspace/coverage/default/1.chip_sw_otbn_randomness.1848422802 Apr 28 03:57:59 PM PDT 24 Apr 28 04:14:58 PM PDT 24 5268075740 ps
T1085 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2705346433 Apr 28 04:14:52 PM PDT 24 Apr 28 04:30:17 PM PDT 24 11781171549 ps
T236 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3595389592 Apr 28 04:11:53 PM PDT 24 Apr 28 04:17:26 PM PDT 24 3465160154 ps
T791 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2755255736 Apr 28 04:17:20 PM PDT 24 Apr 28 04:25:48 PM PDT 24 3711536024 ps
T1086 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3072268645 Apr 28 04:07:04 PM PDT 24 Apr 28 04:13:43 PM PDT 24 8104053778 ps
T290 /workspace/coverage/default/1.chip_plic_all_irqs_0.3408698745 Apr 28 04:00:56 PM PDT 24 Apr 28 04:20:51 PM PDT 24 6900935846 ps
T1087 /workspace/coverage/default/2.chip_sw_example_concurrency.2255340929 Apr 28 04:06:28 PM PDT 24 Apr 28 04:10:23 PM PDT 24 2486273710 ps
T296 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2663379419 Apr 28 03:56:53 PM PDT 24 Apr 28 04:07:43 PM PDT 24 3995600260 ps
T1088 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3936586179 Apr 28 03:53:43 PM PDT 24 Apr 28 04:18:38 PM PDT 24 6748247892 ps
T1089 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3115839670 Apr 28 04:02:33 PM PDT 24 Apr 28 04:13:19 PM PDT 24 5058552020 ps
T1090 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1122730760 Apr 28 03:57:59 PM PDT 24 Apr 28 04:16:00 PM PDT 24 4992133526 ps
T1091 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3569830878 Apr 28 04:06:46 PM PDT 24 Apr 28 04:32:29 PM PDT 24 7685750316 ps
T696 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1023172946 Apr 28 04:09:41 PM PDT 24 Apr 28 04:37:09 PM PDT 24 22569910052 ps
T145 /workspace/coverage/default/0.chip_sw_usbdev_dpi.441101933 Apr 28 03:50:27 PM PDT 24 Apr 28 04:41:27 PM PDT 24 11785733480 ps
T1092 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3369728889 Apr 28 03:56:46 PM PDT 24 Apr 28 04:01:19 PM PDT 24 2842962926 ps
T1093 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3457812884 Apr 28 04:16:36 PM PDT 24 Apr 28 04:21:29 PM PDT 24 2813838694 ps
T1094 /workspace/coverage/default/0.chip_sw_example_manufacturer.3133129381 Apr 28 03:51:45 PM PDT 24 Apr 28 03:55:43 PM PDT 24 2797112938 ps
T1095 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3632551460 Apr 28 04:09:05 PM PDT 24 Apr 28 04:33:11 PM PDT 24 12512573684 ps
T1096 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3408157708 Apr 28 04:23:01 PM PDT 24 Apr 28 04:29:06 PM PDT 24 3324379112 ps
T1097 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1181533280 Apr 28 03:52:59 PM PDT 24 Apr 28 04:04:59 PM PDT 24 4082922440 ps
T1098 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.491788052 Apr 28 04:13:40 PM PDT 24 Apr 28 04:24:45 PM PDT 24 4006794718 ps
T57 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.120583654 Apr 28 03:51:41 PM PDT 24 Apr 28 03:55:36 PM PDT 24 2999285672 ps
T1099 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2261547603 Apr 28 04:08:42 PM PDT 24 Apr 28 04:14:42 PM PDT 24 4067362864 ps
T63 /workspace/coverage/default/1.chip_jtag_csr_rw.4172594394 Apr 28 03:54:26 PM PDT 24 Apr 28 04:32:23 PM PDT 24 18324019792 ps
T766 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1507272844 Apr 28 04:20:44 PM PDT 24 Apr 28 04:34:32 PM PDT 24 4769040460 ps
T313 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2644834955 Apr 28 03:59:52 PM PDT 24 Apr 28 04:04:35 PM PDT 24 2692673298 ps
T1100 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1484035205 Apr 28 04:01:35 PM PDT 24 Apr 28 04:10:04 PM PDT 24 4277355000 ps
T1101 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2924239678 Apr 28 03:53:23 PM PDT 24 Apr 28 04:07:18 PM PDT 24 8674278416 ps
T1102 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.716996215 Apr 28 03:52:56 PM PDT 24 Apr 28 04:01:57 PM PDT 24 6110431091 ps
T75 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1208753055 Apr 28 03:52:18 PM PDT 24 Apr 28 06:05:48 PM PDT 24 31062342100 ps
T1103 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.73052618 Apr 28 04:11:04 PM PDT 24 Apr 28 04:17:07 PM PDT 24 3450878193 ps
T1104 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3841633610 Apr 28 03:59:31 PM PDT 24 Apr 28 04:05:11 PM PDT 24 5254607528 ps
T1105 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3030278295 Apr 28 04:14:18 PM PDT 24 Apr 28 04:24:58 PM PDT 24 4078962368 ps
T785 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4010851674 Apr 28 04:21:39 PM PDT 24 Apr 28 04:28:47 PM PDT 24 3432772470 ps
T1106 /workspace/coverage/default/7.chip_sw_all_escalation_resets.4051432351 Apr 28 04:13:38 PM PDT 24 Apr 28 04:26:12 PM PDT 24 5128606600 ps
T474 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4148926000 Apr 28 04:00:13 PM PDT 24 Apr 28 04:08:22 PM PDT 24 4727917528 ps
T1107 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1250668796 Apr 28 04:23:03 PM PDT 24 Apr 28 04:36:48 PM PDT 24 9538404100 ps
T1108 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3410812954 Apr 28 03:54:50 PM PDT 24 Apr 28 04:04:24 PM PDT 24 4974199340 ps
T1109 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.68190619 Apr 28 03:53:51 PM PDT 24 Apr 28 04:10:27 PM PDT 24 7353005840 ps
T1110 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2043524194 Apr 28 04:06:26 PM PDT 24 Apr 28 04:16:22 PM PDT 24 4046459132 ps
T747 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2971034674 Apr 28 04:14:57 PM PDT 24 Apr 28 04:21:17 PM PDT 24 3675973960 ps
T1111 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.789513971 Apr 28 04:00:29 PM PDT 24 Apr 28 04:08:51 PM PDT 24 4800268660 ps
T663 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.488816562 Apr 28 03:51:13 PM PDT 24 Apr 28 03:53:07 PM PDT 24 2542790259 ps
T1112 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1633304456 Apr 28 04:03:14 PM PDT 24 Apr 28 04:14:28 PM PDT 24 4972417827 ps
T1113 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383994946 Apr 28 04:20:00 PM PDT 24 Apr 28 04:26:13 PM PDT 24 3451808672 ps
T1114 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1124797198 Apr 28 04:17:12 PM PDT 24 Apr 28 04:25:40 PM PDT 24 4010171246 ps
T1115 /workspace/coverage/default/2.chip_sw_csrng_smoketest.462703638 Apr 28 04:11:39 PM PDT 24 Apr 28 04:15:48 PM PDT 24 2484414200 ps
T130 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1912647966 Apr 28 04:00:27 PM PDT 24 Apr 28 04:09:19 PM PDT 24 5311949560 ps
T1116 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3450881491 Apr 28 03:52:17 PM PDT 24 Apr 28 04:08:06 PM PDT 24 5460110576 ps
T243 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1004360662 Apr 28 04:09:34 PM PDT 24 Apr 28 04:18:32 PM PDT 24 5651465560 ps
T359 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3047923834 Apr 28 04:03:21 PM PDT 24 Apr 28 04:12:17 PM PDT 24 7825642228 ps
T1117 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.320825251 Apr 28 03:55:52 PM PDT 24 Apr 28 04:08:32 PM PDT 24 9822335335 ps
T1118 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.710855505 Apr 28 03:56:34 PM PDT 24 Apr 28 04:10:13 PM PDT 24 9126231440 ps
T1119 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2919769372 Apr 28 03:51:49 PM PDT 24 Apr 28 04:01:44 PM PDT 24 4632562536 ps
T300 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.952719612 Apr 28 04:10:35 PM PDT 24 Apr 28 04:42:48 PM PDT 24 7235283552 ps
T369 /workspace/coverage/default/2.chip_sw_kmac_app_rom.841765083 Apr 28 04:08:57 PM PDT 24 Apr 28 04:12:30 PM PDT 24 2760626362 ps
T1120 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.15771788 Apr 28 04:15:29 PM PDT 24 Apr 28 04:23:30 PM PDT 24 5679891396 ps
T645 /workspace/coverage/default/2.chip_sw_edn_boot_mode.546263755 Apr 28 04:09:16 PM PDT 24 Apr 28 04:18:19 PM PDT 24 2792265052 ps
T305 /workspace/coverage/default/1.chip_plic_all_irqs_20.4094128302 Apr 28 04:00:09 PM PDT 24 Apr 28 04:13:58 PM PDT 24 4215932896 ps
T1121 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3918264797 Apr 28 04:06:03 PM PDT 24 Apr 28 04:14:26 PM PDT 24 4691707951 ps
T723 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115671532 Apr 28 04:22:26 PM PDT 24 Apr 28 04:30:00 PM PDT 24 4191028456 ps
T1122 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.4205505654 Apr 28 03:58:18 PM PDT 24 Apr 28 04:10:17 PM PDT 24 7292918675 ps
T1123 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3882340777 Apr 28 03:56:55 PM PDT 24 Apr 28 04:20:42 PM PDT 24 8166110094 ps
T1124 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1155744827 Apr 28 04:07:03 PM PDT 24 Apr 28 04:11:15 PM PDT 24 2809151931 ps
T1125 /workspace/coverage/default/0.chip_sw_power_sleep_load.1797361380 Apr 28 03:54:23 PM PDT 24 Apr 28 04:04:33 PM PDT 24 9295285120 ps
T1126 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3504108295 Apr 28 04:08:36 PM PDT 24 Apr 28 04:14:18 PM PDT 24 3151153216 ps
T297 /workspace/coverage/default/0.chip_plic_all_irqs_0.3340592892 Apr 28 03:54:02 PM PDT 24 Apr 28 04:13:23 PM PDT 24 6439063362 ps
T1127 /workspace/coverage/default/1.chip_sw_aes_masking_off.4053860577 Apr 28 03:58:36 PM PDT 24 Apr 28 04:03:39 PM PDT 24 2891102775 ps
T1128 /workspace/coverage/default/81.chip_sw_all_escalation_resets.1740460079 Apr 28 04:23:20 PM PDT 24 Apr 28 04:34:38 PM PDT 24 4894707162 ps
T1129 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2168403791 Apr 28 03:59:41 PM PDT 24 Apr 28 04:08:13 PM PDT 24 5675004281 ps
T697 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1989731726 Apr 28 03:53:56 PM PDT 24 Apr 28 04:25:11 PM PDT 24 21057420786 ps
T1130 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.864331531 Apr 28 04:01:41 PM PDT 24 Apr 28 04:07:44 PM PDT 24 3135271480 ps
T1131 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2178939814 Apr 28 04:13:18 PM PDT 24 Apr 28 04:26:32 PM PDT 24 4122901620 ps
T1132 /workspace/coverage/default/0.chip_sw_otbn_randomness.2131124666 Apr 28 03:52:40 PM PDT 24 Apr 28 04:08:32 PM PDT 24 5827171384 ps
T1133 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2064353869 Apr 28 03:53:42 PM PDT 24 Apr 28 04:14:51 PM PDT 24 8455468836 ps
T312 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4124772074 Apr 28 03:58:45 PM PDT 24 Apr 28 04:11:50 PM PDT 24 4718653120 ps
T1134 /workspace/coverage/default/1.chip_sw_aes_enc.1952930684 Apr 28 03:58:20 PM PDT 24 Apr 28 04:03:54 PM PDT 24 2798428680 ps
T272 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1712916451 Apr 28 03:53:32 PM PDT 24 Apr 28 03:58:01 PM PDT 24 3040226787 ps
T1135 /workspace/coverage/default/0.chip_sw_hmac_enc.298674053 Apr 28 03:54:08 PM PDT 24 Apr 28 03:58:12 PM PDT 24 3409027304 ps
T1136 /workspace/coverage/default/2.chip_sw_uart_tx_rx.2753519054 Apr 28 04:06:34 PM PDT 24 Apr 28 04:19:11 PM PDT 24 4108954626 ps
T348 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3368571596 Apr 28 03:56:33 PM PDT 24 Apr 28 04:12:24 PM PDT 24 6051930586 ps
T1137 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3705266335 Apr 28 04:05:48 PM PDT 24 Apr 28 04:11:38 PM PDT 24 3207988854 ps
T1138 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3843975866 Apr 28 04:03:08 PM PDT 24 Apr 28 04:14:43 PM PDT 24 4548643604 ps
T1139 /workspace/coverage/default/1.rom_keymgr_functest.3018611977 Apr 28 04:05:24 PM PDT 24 Apr 28 04:14:07 PM PDT 24 4235776008 ps
T1140 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3658482954 Apr 28 04:01:07 PM PDT 24 Apr 28 04:08:25 PM PDT 24 6578229773 ps
T154 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3694047488 Apr 28 04:01:57 PM PDT 24 Apr 28 04:07:16 PM PDT 24 2694262140 ps
T1141 /workspace/coverage/default/1.chip_tap_straps_rma.1172650890 Apr 28 04:02:16 PM PDT 24 Apr 28 04:07:50 PM PDT 24 5322311363 ps
T91 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3180838802 Apr 28 04:14:19 PM PDT 24 Apr 28 04:21:13 PM PDT 24 3873701588 ps
T1142 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4182818333 Apr 28 04:21:45 PM PDT 24 Apr 28 04:28:48 PM PDT 24 3560715160 ps
T658 /workspace/coverage/default/2.chip_tap_straps_dev.2202953954 Apr 28 04:12:09 PM PDT 24 Apr 28 04:24:04 PM PDT 24 7187058252 ps
T1143 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3071155127 Apr 28 04:14:23 PM PDT 24 Apr 28 04:26:16 PM PDT 24 8180580789 ps
T1144 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.208078345 Apr 28 04:01:44 PM PDT 24 Apr 28 04:11:14 PM PDT 24 4165967210 ps
T1145 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2967511584 Apr 28 03:56:12 PM PDT 24 Apr 28 04:00:45 PM PDT 24 2508264660 ps
T764 /workspace/coverage/default/79.chip_sw_all_escalation_resets.1316953444 Apr 28 04:21:44 PM PDT 24 Apr 28 04:32:59 PM PDT 24 5896193176 ps
T795 /workspace/coverage/default/95.chip_sw_all_escalation_resets.1573768740 Apr 28 04:22:56 PM PDT 24 Apr 28 04:36:01 PM PDT 24 5146189556 ps
T780 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4016603637 Apr 28 04:17:52 PM PDT 24 Apr 28 04:23:51 PM PDT 24 3332161480 ps
T1146 /workspace/coverage/default/2.chip_sw_hmac_smoketest.4026789853 Apr 28 04:16:13 PM PDT 24 Apr 28 04:23:26 PM PDT 24 3499803940 ps
T43 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.255571493 Apr 28 04:00:37 PM PDT 24 Apr 29 12:38:21 AM PDT 24 152851275611 ps
T1147 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3640301255 Apr 28 03:53:01 PM PDT 24 Apr 28 05:17:31 PM PDT 24 24007457952 ps
T1148 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1272937751 Apr 28 04:07:12 PM PDT 24 Apr 28 04:25:58 PM PDT 24 8202482782 ps
T1149 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.989133977 Apr 28 04:01:18 PM PDT 24 Apr 28 04:13:18 PM PDT 24 4592381414 ps
T1150 /workspace/coverage/default/2.chip_sw_aes_smoketest.895130952 Apr 28 04:11:58 PM PDT 24 Apr 28 04:16:34 PM PDT 24 2359695288 ps
T1151 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.503540168 Apr 28 04:15:25 PM PDT 24 Apr 28 04:50:18 PM PDT 24 8388011836 ps
T1152 /workspace/coverage/default/0.chip_sw_uart_smoketest.2547339565 Apr 28 03:56:46 PM PDT 24 Apr 28 04:02:13 PM PDT 24 3343174596 ps
T306 /workspace/coverage/default/0.chip_plic_all_irqs_20.2195796255 Apr 28 03:54:08 PM PDT 24 Apr 28 04:07:23 PM PDT 24 4503703060 ps
T1153 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3931604874 Apr 28 03:51:04 PM PDT 24 Apr 28 04:11:15 PM PDT 24 7715435670 ps
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