Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	117305554	127775	0	0
DstReqKnown_A	1495963	1312941	0	0
SrcAckBusyChk_A	117305554	317	0	0
SrcBusyKnown_A	117305554	116636875	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	127775	0	0
T48	241461	356	0	0
T50	0	741	0	0
T138	0	330	0	0
T139	0	244	0	0
T140	0	788	0	0
T141	0	2506	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	715	0	0
T378	0	852	0	0
T382	0	426	0	0
T383	0	404	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495963	1312941	0	0
T1	1813	1647	0	0
T2	11297	11007	0	0
T3	1055	890	0	0
T55	637	474	0	0
T59	587	426	0	0
T81	696	532	0	0
T82	731	566	0	0
T83	521	357	0	0
T84	925	763	0	0
T85	871	707	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	317	0	0
T48	241461	1	0	0
T50	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	7	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	2	0	0
T378	0	2	0	0
T382	0	1	0	0
T383	0	1	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	116636875	0	0
T1	127911	127292	0	0
T2	130403	130233	0	0
T3	66480	66105	0	0
T55	41133	40794	0	0
T59	42411	41930	0	0
T81	53532	53103	0	0
T82	55357	54649	0	0
T83	35625	35012	0	0
T84	84331	83824	0	0
T85	55566	55178	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T146

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	117305554	108038	0	0
DstReqKnown_A	1495963	1312941	0	0
SrcAckBusyChk_A	117305554	269	0	0
SrcBusyKnown_A	117305554	116636875	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	108038	0	0
T48	241461	323	0	0
T50	0	812	0	0
T138	0	265	0	0
T139	0	272	0	0
T140	0	936	0	0
T141	0	1659	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	713	0	0
T378	0	858	0	0
T382	0	481	0	0
T383	0	404	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495963	1312941	0	0
T1	1813	1647	0	0
T2	11297	11007	0	0
T3	1055	890	0	0
T55	637	474	0	0
T59	587	426	0	0
T81	696	532	0	0
T82	731	566	0	0
T83	521	357	0	0
T84	925	763	0	0
T85	871	707	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	269	0	0
T48	241461	1	0	0
T50	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	5	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	2	0	0
T378	0	2	0	0
T382	0	1	0	0
T383	0	1	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	116636875	0	0
T1	127911	127292	0	0
T2	130403	130233	0	0
T3	66480	66105	0	0
T55	41133	40794	0	0
T59	42411	41930	0	0
T81	53532	53103	0	0
T82	55357	54649	0	0
T83	35625	35012	0	0
T84	84331	83824	0	0
T85	55566	55178	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T71

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	117305554	115671	0	0
DstReqKnown_A	1495963	1312941	0	0
SrcAckBusyChk_A	117305554	287	0	0
SrcBusyKnown_A	117305554	116636875	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	115671	0	0
T48	241461	276	0	0
T50	0	645	0	0
T138	0	304	0	0
T139	0	322	0	0
T140	0	893	0	0
T141	0	3022	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	734	0	0
T378	0	838	0	0
T382	0	386	0	0
T383	0	432	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495963	1312941	0	0
T1	1813	1647	0	0
T2	11297	11007	0	0
T3	1055	890	0	0
T55	637	474	0	0
T59	587	426	0	0
T81	696	532	0	0
T82	731	566	0	0
T83	521	357	0	0
T84	925	763	0	0
T85	871	707	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	287	0	0
T48	241461	1	0	0
T50	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	8	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	2	0	0
T378	0	2	0	0
T382	0	1	0	0
T383	0	1	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	116636875	0	0
T1	127911	127292	0	0
T2	130403	130233	0	0
T3	66480	66105	0	0
T55	41133	40794	0	0
T59	42411	41930	0	0
T81	53532	53103	0	0
T82	55357	54649	0	0
T83	35625	35012	0	0
T84	84331	83824	0	0
T85	55566	55178	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	117305554	116767	0	0
DstReqKnown_A	1495963	1312941	0	0
SrcAckBusyChk_A	117305554	290	0	0
SrcBusyKnown_A	117305554	116636875	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	116767	0	0
T48	241461	302	0	0
T50	0	667	0	0
T138	0	242	0	0
T139	0	251	0	0
T140	0	805	0	0
T141	0	2139	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	781	0	0
T378	0	816	0	0
T382	0	415	0	0
T383	0	366	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495963	1312941	0	0
T1	1813	1647	0	0
T2	11297	11007	0	0
T3	1055	890	0	0
T55	637	474	0	0
T59	587	426	0	0
T81	696	532	0	0
T82	731	566	0	0
T83	521	357	0	0
T84	925	763	0	0
T85	871	707	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	290	0	0
T48	241461	1	0	0
T50	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	6	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	2	0	0
T378	0	2	0	0
T382	0	1	0	0
T383	0	1	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	116636875	0	0
T1	127911	127292	0	0
T2	130403	130233	0	0
T3	66480	66105	0	0
T55	41133	40794	0	0
T59	42411	41930	0	0
T81	53532	53103	0	0
T82	55357	54649	0	0
T83	35625	35012	0	0
T84	84331	83824	0	0
T85	55566	55178	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	117305554	107948	0	0
DstReqKnown_A	1495963	1312941	0	0
SrcAckBusyChk_A	117305554	270	0	0
SrcBusyKnown_A	117305554	116636875	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	107948	0	0
T48	241461	332	0	0
T50	0	696	0	0
T138	0	344	0	0
T139	0	360	0	0
T140	0	888	0	0
T141	0	1759	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	759	0	0
T378	0	852	0	0
T382	0	365	0	0
T383	0	416	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495963	1312941	0	0
T1	1813	1647	0	0
T2	11297	11007	0	0
T3	1055	890	0	0
T55	637	474	0	0
T59	587	426	0	0
T81	696	532	0	0
T82	731	566	0	0
T83	521	357	0	0
T84	925	763	0	0
T85	871	707	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	270	0	0
T48	241461	1	0	0
T50	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	5	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	2	0	0
T378	0	2	0	0
T382	0	1	0	0
T383	0	1	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	116636875	0	0
T1	127911	127292	0	0
T2	130403	130233	0	0
T3	66480	66105	0	0
T55	41133	40794	0	0
T59	42411	41930	0	0
T81	53532	53103	0	0
T82	55357	54649	0	0
T83	35625	35012	0	0
T84	84331	83824	0	0
T85	55566	55178	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T138

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T48,T50,T138
1	1	Covered	T48,T50,T138

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T48,T50,T138
0	0	1	Covered	T48,T50,T138
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	117305554	99236	0	0
DstReqKnown_A	1495963	1312941	0	0
SrcAckBusyChk_A	117305554	248	0	0
SrcBusyKnown_A	117305554	116636875	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	99236	0	0
T48	241461	280	0	0
T50	0	736	0	0
T138	0	302	0	0
T139	0	296	0	0
T140	0	829	0	0
T141	0	1371	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	750	0	0
T378	0	779	0	0
T382	0	399	0	0
T383	0	443	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495963	1312941	0	0
T1	1813	1647	0	0
T2	11297	11007	0	0
T3	1055	890	0	0
T55	637	474	0	0
T59	587	426	0	0
T81	696	532	0	0
T82	731	566	0	0
T83	521	357	0	0
T84	925	763	0	0
T85	871	707	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	248	0	0
T48	241461	1	0	0
T50	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	4	0	0
T283	36594	0	0	0
T287	44039	0	0	0
T288	10911	0	0	0
T289	44428	0	0	0
T290	90226	0	0	0
T377	0	2	0	0
T378	0	2	0	0
T382	0	1	0	0
T383	0	1	0	0
T385	44928	0	0	0
T386	98224	0	0	0
T387	36650	0	0	0
T388	20353	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	116636875	0	0
T1	127911	127292	0	0
T2	130403	130233	0	0
T3	66480	66105	0	0
T55	41133	40794	0	0
T59	42411	41930	0	0
T81	53532	53103	0	0
T82	55357	54649	0	0
T83	35625	35012	0	0
T84	84331	83824	0	0
T85	55566	55178	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T15,T13,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T13,T16
1	1	Covered	T15,T13,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T13,T47
1	0	Covered	T15,T13,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T13,T16
1	1	Covered	T15,T13,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T13,T47

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T15,T13,T16
0	0	1	Covered	T15,T13,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T15,T13,T16
0	0	1	Covered	T15,T13,T47
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	117305554	137906	0	0
DstReqKnown_A	1495963	1312941	0	0
SrcAckBusyChk_A	117305554	289	0	0
SrcBusyKnown_A	117305554	116636875	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	137906	0	0
T9	64118	0	0	0
T13	0	942	0	0
T15	143424	1543	0	0
T16	0	791	0	0
T24	0	891	0	0
T45	48351	0	0	0
T46	45130	0	0	0
T48	0	245	0	0
T52	0	1356	0	0
T67	283322	0	0	0
T89	0	789	0	0
T97	0	670	0	0
T98	0	702	0	0
T99	109031	0	0	0
T100	62645	0	0	0
T101	41870	0	0	0
T102	24224	0	0	0
T103	89284	0	0	0
T381	0	783	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495963	1312941	0	0
T1	1813	1647	0	0
T2	11297	11007	0	0
T3	1055	890	0	0
T55	637	474	0	0
T59	587	426	0	0
T81	696	532	0	0
T82	731	566	0	0
T83	521	357	0	0
T84	925	763	0	0
T85	871	707	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	289	0	0
T9	64118	0	0	0
T13	0	3	0	0
T15	143424	4	0	0
T16	0	2	0	0
T24	0	2	0	0
T45	48351	0	0	0
T46	45130	0	0	0
T48	0	1	0	0
T52	0	4	0	0
T67	283322	0	0	0
T89	0	2	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	109031	0	0	0
T100	62645	0	0	0
T101	41870	0	0	0
T102	24224	0	0	0
T103	89284	0	0	0
T381	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117305554	116636875	0	0
T1	127911	127292	0	0
T2	130403	130233	0	0
T3	66480	66105	0	0
T55	41133	40794	0	0
T59	42411	41930	0	0
T81	53532	53103	0	0
T82	55357	54649	0	0
T83	35625	35012	0	0
T84	84331	83824	0	0
T85	55566	55178	0	0