Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_4_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_5_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_6_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_7_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_wkup_cause_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T52,T53,T122
1	1	Covered	T326,T135,T360

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T326,T135,T360
1	1	Covered	T52,T53,T122

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1440435	273	0	0
SrcPulseCheck_M	111382661	273	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	273	0	0
T52	3598	1	0	0
T53	0	1	0	0
T135	0	19	0	0
T136	0	1	0	0
T296	667	0	0	0
T326	0	3	0	0
T327	0	5	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	444	0	0	0
T364	822	0	0	0
T365	2486	0	0	0
T366	462	0	0	0
T367	532	0	0	0
T368	1169	0	0	0
T369	513	0	0	0
T370	990	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	273	0	0
T52	402741	1	0	0
T53	0	1	0	0
T135	0	19	0	0
T136	0	1	0	0
T296	52115	0	0	0
T326	0	3	0	0
T327	0	5	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	26129	0	0	0
T364	69481	0	0	0
T365	273931	0	0	0
T366	30018	0	0	0
T367	26760	0	0	0
T368	100620	0	0	0
T369	25909	0	0	0
T370	49774	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T52,T53,T122
1	1	Covered	T326,T135,T360

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T326,T135,T360
1	1	Covered	T52,T53,T122

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111382661	273	0	0
SrcPulseCheck_M	1440435	273	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	273	0	0
T52	402741	1	0	0
T53	0	1	0	0
T135	0	19	0	0
T136	0	1	0	0
T296	52115	0	0	0
T326	0	3	0	0
T327	0	5	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	26129	0	0	0
T364	69481	0	0	0
T365	273931	0	0	0
T366	30018	0	0	0
T367	26760	0	0	0
T368	100620	0	0	0
T369	25909	0	0	0
T370	49774	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	273	0	0
T52	3598	1	0	0
T53	0	1	0	0
T135	0	19	0	0
T136	0	1	0	0
T296	667	0	0	0
T326	0	3	0	0
T327	0	5	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	444	0	0	0
T364	822	0	0	0
T365	2486	0	0	0
T366	462	0	0	0
T367	532	0	0	0
T368	1169	0	0	0
T369	513	0	0	0
T370	990	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T52,T53,T122
1	1	Covered	T326,T135,T360

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T326,T135,T360
1	1	Covered	T52,T53,T122

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1440435	290	0	0
SrcPulseCheck_M	111382661	290	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	290	0	0
T52	3598	1	0	0
T53	0	1	0	0
T135	0	21	0	0
T136	0	1	0	0
T296	667	0	0	0
T326	0	9	0	0
T327	0	11	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	444	0	0	0
T364	822	0	0	0
T365	2486	0	0	0
T366	462	0	0	0
T367	532	0	0	0
T368	1169	0	0	0
T369	513	0	0	0
T370	990	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	290	0	0
T52	402741	1	0	0
T53	0	1	0	0
T135	0	21	0	0
T136	0	1	0	0
T296	52115	0	0	0
T326	0	9	0	0
T327	0	11	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	26129	0	0	0
T364	69481	0	0	0
T365	273931	0	0	0
T366	30018	0	0	0
T367	26760	0	0	0
T368	100620	0	0	0
T369	25909	0	0	0
T370	49774	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T52,T53,T122
1	1	Covered	T326,T135,T360

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T326,T135,T360
1	1	Covered	T52,T53,T122

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111382661	290	0	0
SrcPulseCheck_M	1440435	290	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	290	0	0
T52	402741	1	0	0
T53	0	1	0	0
T135	0	21	0	0
T136	0	1	0	0
T296	52115	0	0	0
T326	0	9	0	0
T327	0	11	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	26129	0	0	0
T364	69481	0	0	0
T365	273931	0	0	0
T366	30018	0	0	0
T367	26760	0	0	0
T368	100620	0	0	0
T369	25909	0	0	0
T370	49774	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	290	0	0
T52	3598	1	0	0
T53	0	1	0	0
T135	0	21	0	0
T136	0	1	0	0
T296	667	0	0	0
T326	0	9	0	0
T327	0	11	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	444	0	0	0
T364	822	0	0	0
T365	2486	0	0	0
T366	462	0	0	0
T367	532	0	0	0
T368	1169	0	0	0
T369	513	0	0	0
T370	990	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T52,T53,T122
1	1	Covered	T326,T135,T360

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T326,T135,T360
1	1	Covered	T52,T53,T122

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1440435	293	0	0
SrcPulseCheck_M	111382661	293	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	293	0	0
T52	3598	1	0	0
T53	0	1	0	0
T135	0	13	0	0
T136	0	1	0	0
T296	667	0	0	0
T326	0	2	0	0
T327	0	17	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	444	0	0	0
T364	822	0	0	0
T365	2486	0	0	0
T366	462	0	0	0
T367	532	0	0	0
T368	1169	0	0	0
T369	513	0	0	0
T370	990	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	293	0	0
T52	402741	1	0	0
T53	0	1	0	0
T135	0	13	0	0
T136	0	1	0	0
T296	52115	0	0	0
T326	0	2	0	0
T327	0	17	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	26129	0	0	0
T364	69481	0	0	0
T365	273931	0	0	0
T366	30018	0	0	0
T367	26760	0	0	0
T368	100620	0	0	0
T369	25909	0	0	0
T370	49774	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T52,T53,T122
1	1	Covered	T326,T135,T360

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T326,T135,T360
1	1	Covered	T52,T53,T122

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111382661	293	0	0
SrcPulseCheck_M	1440435	293	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	293	0	0
T52	402741	1	0	0
T53	0	1	0	0
T135	0	13	0	0
T136	0	1	0	0
T296	52115	0	0	0
T326	0	2	0	0
T327	0	17	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	26129	0	0	0
T364	69481	0	0	0
T365	273931	0	0	0
T366	30018	0	0	0
T367	26760	0	0	0
T368	100620	0	0	0
T369	25909	0	0	0
T370	49774	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	293	0	0
T52	3598	1	0	0
T53	0	1	0	0
T135	0	13	0	0
T136	0	1	0	0
T296	667	0	0	0
T326	0	2	0	0
T327	0	17	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	444	0	0	0
T364	822	0	0	0
T365	2486	0	0	0
T366	462	0	0	0
T367	532	0	0	0
T368	1169	0	0	0
T369	513	0	0	0
T370	990	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T52,T53,T122
1	1	Covered	T326,T135,T360

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T326,T135,T360
1	1	Covered	T52,T53,T122

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1440435	251	0	0
SrcPulseCheck_M	111382661	251	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	251	0	0
T52	3598	1	0	0
T53	0	1	0	0
T135	0	9	0	0
T136	0	1	0	0
T296	667	0	0	0
T326	0	2	0	0
T327	0	11	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	444	0	0	0
T364	822	0	0	0
T365	2486	0	0	0
T366	462	0	0	0
T367	532	0	0	0
T368	1169	0	0	0
T369	513	0	0	0
T370	990	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	251	0	0
T52	402741	1	0	0
T53	0	1	0	0
T135	0	9	0	0
T136	0	1	0	0
T296	52115	0	0	0
T326	0	2	0	0
T327	0	11	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	26129	0	0	0
T364	69481	0	0	0
T365	273931	0	0	0
T366	30018	0	0	0
T367	26760	0	0	0
T368	100620	0	0	0
T369	25909	0	0	0
T370	49774	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T52,T53,T122
1	1	Covered	T326,T135,T360

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T326,T135,T360
1	1	Covered	T52,T53,T122

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111382661	251	0	0
SrcPulseCheck_M	1440435	251	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	251	0	0
T52	402741	1	0	0
T53	0	1	0	0
T135	0	9	0	0
T136	0	1	0	0
T296	52115	0	0	0
T326	0	2	0	0
T327	0	11	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	26129	0	0	0
T364	69481	0	0	0
T365	273931	0	0	0
T366	30018	0	0	0
T367	26760	0	0	0
T368	100620	0	0	0
T369	25909	0	0	0
T370	49774	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	251	0	0
T52	3598	1	0	0
T53	0	1	0	0
T135	0	9	0	0
T136	0	1	0	0
T296	667	0	0	0
T326	0	2	0	0
T327	0	11	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	444	0	0	0
T364	822	0	0	0
T365	2486	0	0	0
T366	462	0	0	0
T367	532	0	0	0
T368	1169	0	0	0
T369	513	0	0	0
T370	990	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T52,T53,T122
1	1	Covered	T326,T135,T360

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T326,T135,T360
1	1	Covered	T52,T53,T122

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1440435	294	0	0
SrcPulseCheck_M	111382661	294	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	294	0	0
T52	3598	1	0	0
T53	0	1	0	0
T135	0	16	0	0
T136	0	1	0	0
T296	667	0	0	0
T326	0	7	0	0
T327	0	5	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	444	0	0	0
T364	822	0	0	0
T365	2486	0	0	0
T366	462	0	0	0
T367	532	0	0	0
T368	1169	0	0	0
T369	513	0	0	0
T370	990	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	294	0	0
T52	402741	1	0	0
T53	0	1	0	0
T135	0	16	0	0
T136	0	1	0	0
T296	52115	0	0	0
T326	0	7	0	0
T327	0	5	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	26129	0	0	0
T364	69481	0	0	0
T365	273931	0	0	0
T366	30018	0	0	0
T367	26760	0	0	0
T368	100620	0	0	0
T369	25909	0	0	0
T370	49774	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T52,T53,T122
1	1	Covered	T326,T135,T360

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T122
1	0	Covered	T326,T135,T360
1	1	Covered	T52,T53,T122

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111382661	294	0	0
SrcPulseCheck_M	1440435	294	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	294	0	0
T52	402741	1	0	0
T53	0	1	0	0
T135	0	16	0	0
T136	0	1	0	0
T296	52115	0	0	0
T326	0	7	0	0
T327	0	5	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	26129	0	0	0
T364	69481	0	0	0
T365	273931	0	0	0
T366	30018	0	0	0
T367	26760	0	0	0
T368	100620	0	0	0
T369	25909	0	0	0
T370	49774	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	294	0	0
T52	3598	1	0	0
T53	0	1	0	0
T135	0	16	0	0
T136	0	1	0	0
T296	667	0	0	0
T326	0	7	0	0
T327	0	5	0	0
T328	0	1	0	0
T329	0	1	0	0
T360	0	2	0	0
T361	0	2	0	0
T363	444	0	0	0
T364	822	0	0	0
T365	2486	0	0	0
T366	462	0	0	0
T367	532	0	0	0
T368	1169	0	0	0
T369	513	0	0	0
T370	990	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T18,T19
1	0	Covered	T27,T18,T19
1	1	Covered	T27,T18,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T18,T19
1	0	Covered	T27,T18,T19
1	1	Covered	T27,T18,T19

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1440435	352	0	0
SrcPulseCheck_M	111382661	355	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1440435	352	0	0
T18	3763	4	0	0
T19	0	4	0	0
T22	3937	0	0	0
T27	458	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	5	0	0
T58	0	4	0	0
T92	912	0	0	0
T93	438	0	0	0
T94	1030	0	0	0
T95	831	0	0	0
T96	0	2	0	0
T97	0	2	0	0
T281	985	0	0	0
T331	567	0	0	0
T359	0	2	0	0
T362	1482	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	111382661	355	0	0
T18	178181	4	0	0
T19	0	4	0	0
T22	419969	0	0	0
T27	25619	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	6	0	0
T58	0	4	0	0
T92	63281	0	0	0
T93	22202	0	0	0
T94	83181	0	0	0
T95	58480	0	0	0
T96	0	2	0	0
T97	0	2	0	0
T281	63163	0	0	0
T331	38415	0	0	0
T359	0	2	0	0
T362	143675	0	0	0