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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.37 95.32 93.65 91.81 94.46 97.38 99.58


Total test records in report: 2801
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T885 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.4164117228 May 23 04:07:12 PM PDT 24 May 23 04:11:02 PM PDT 24 2461900874 ps
T296 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.576074585 May 23 04:04:03 PM PDT 24 May 23 04:16:26 PM PDT 24 4618650107 ps
T328 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2438451378 May 23 04:01:05 PM PDT 24 May 23 04:12:19 PM PDT 24 4979320325 ps
T207 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1878644903 May 23 04:02:25 PM PDT 24 May 23 04:18:44 PM PDT 24 7415788312 ps
T886 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2940302535 May 23 04:01:57 PM PDT 24 May 23 04:06:38 PM PDT 24 3126985981 ps
T640 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2620748155 May 23 04:20:23 PM PDT 24 May 23 04:27:36 PM PDT 24 3696961982 ps
T887 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1591661178 May 23 04:02:57 PM PDT 24 May 23 05:20:38 PM PDT 24 18456005934 ps
T888 /workspace/coverage/default/0.rom_e2e_asm_init_prod.2869215727 May 23 04:07:17 PM PDT 24 May 23 05:10:25 PM PDT 24 14072228541 ps
T220 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3494594302 May 23 04:05:37 PM PDT 24 May 23 04:14:21 PM PDT 24 4785134248 ps
T10 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2293507153 May 23 03:59:00 PM PDT 24 May 23 04:12:18 PM PDT 24 7287343882 ps
T889 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1638616339 May 23 04:05:08 PM PDT 24 May 23 05:06:35 PM PDT 24 18188590537 ps
T693 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303802127 May 23 04:23:24 PM PDT 24 May 23 04:29:25 PM PDT 24 3578297020 ps
T629 /workspace/coverage/default/2.chip_sw_edn_kat.3093932990 May 23 04:09:41 PM PDT 24 May 23 04:19:54 PM PDT 24 3041321780 ps
T57 /workspace/coverage/default/1.chip_jtag_csr_rw.2142632257 May 23 03:49:15 PM PDT 24 May 23 03:53:12 PM PDT 24 3549944350 ps
T147 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.460015308 May 23 04:01:44 PM PDT 24 May 23 04:11:48 PM PDT 24 4031144176 ps
T210 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3773270284 May 23 04:05:28 PM PDT 24 May 23 04:25:23 PM PDT 24 8293546340 ps
T300 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.274720297 May 23 04:02:53 PM PDT 24 May 23 04:21:44 PM PDT 24 5780479714 ps
T890 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.551135842 May 23 03:58:20 PM PDT 24 May 23 04:04:08 PM PDT 24 6557455640 ps
T891 /workspace/coverage/default/1.chip_sw_aes_entropy.2071358020 May 23 04:08:03 PM PDT 24 May 23 04:12:54 PM PDT 24 2871344050 ps
T892 /workspace/coverage/default/0.chip_sw_kmac_idle.2968444946 May 23 04:06:55 PM PDT 24 May 23 04:11:39 PM PDT 24 2769277752 ps
T64 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4131810956 May 23 04:04:29 PM PDT 24 May 23 04:10:33 PM PDT 24 4838212568 ps
T893 /workspace/coverage/default/2.chip_sw_example_concurrency.4284577543 May 23 04:08:09 PM PDT 24 May 23 04:12:28 PM PDT 24 2998591352 ps
T308 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1608703328 May 23 04:17:35 PM PDT 24 May 23 05:01:09 PM PDT 24 13243764648 ps
T208 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2267595840 May 23 04:04:00 PM PDT 24 May 23 04:28:29 PM PDT 24 7527987816 ps
T48 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2954189339 May 23 04:04:21 PM PDT 24 May 23 04:09:19 PM PDT 24 3931779480 ps
T667 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1165459476 May 23 04:19:15 PM PDT 24 May 23 04:26:04 PM PDT 24 3304936806 ps
T682 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.374723407 May 23 04:21:42 PM PDT 24 May 23 04:28:44 PM PDT 24 3739391310 ps
T20 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.192636031 May 23 04:03:07 PM PDT 24 May 23 04:32:43 PM PDT 24 23184152310 ps
T252 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3423429185 May 23 04:03:38 PM PDT 24 May 23 05:04:50 PM PDT 24 13590519778 ps
T106 /workspace/coverage/default/2.chip_sw_gpio_smoketest.370304491 May 23 04:15:32 PM PDT 24 May 23 04:21:06 PM PDT 24 2948818178 ps
T181 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3656740600 May 23 04:05:19 PM PDT 24 May 23 04:27:07 PM PDT 24 7570383208 ps
T72 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3706769731 May 23 03:58:13 PM PDT 24 May 23 04:25:06 PM PDT 24 13203973236 ps
T894 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2174221746 May 23 04:14:46 PM PDT 24 May 23 04:17:57 PM PDT 24 2960629552 ps
T895 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1593100753 May 23 04:15:30 PM PDT 24 May 23 04:21:08 PM PDT 24 2898377884 ps
T896 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4143174928 May 23 04:04:49 PM PDT 24 May 23 04:15:31 PM PDT 24 4640211984 ps
T897 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2367755189 May 23 04:05:16 PM PDT 24 May 23 04:10:24 PM PDT 24 3043094776 ps
T318 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.722390175 May 23 04:00:26 PM PDT 24 May 23 04:11:33 PM PDT 24 4117173380 ps
T11 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3882793752 May 23 04:02:47 PM PDT 24 May 23 04:09:46 PM PDT 24 4194465305 ps
T680 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1811897850 May 23 04:21:22 PM PDT 24 May 23 04:29:24 PM PDT 24 3955433288 ps
T898 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2675717274 May 23 03:59:58 PM PDT 24 May 23 04:24:49 PM PDT 24 6828759366 ps
T899 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1306630642 May 23 04:08:05 PM PDT 24 May 23 05:05:22 PM PDT 24 13526297621 ps
T690 /workspace/coverage/default/38.chip_sw_all_escalation_resets.88582952 May 23 04:20:19 PM PDT 24 May 23 04:30:32 PM PDT 24 5676174520 ps
T160 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3115143111 May 23 04:12:34 PM PDT 24 May 23 04:22:06 PM PDT 24 4102287130 ps
T900 /workspace/coverage/default/0.chip_sw_aes_entropy.4049777822 May 23 04:00:30 PM PDT 24 May 23 04:04:39 PM PDT 24 2999682600 ps
T326 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4106250449 May 23 04:00:25 PM PDT 24 May 23 04:51:01 PM PDT 24 33076982686 ps
T733 /workspace/coverage/default/17.chip_sw_all_escalation_resets.640127031 May 23 04:17:43 PM PDT 24 May 23 04:26:00 PM PDT 24 5187383886 ps
T901 /workspace/coverage/default/0.rom_keymgr_functest.778818179 May 23 04:01:40 PM PDT 24 May 23 04:12:05 PM PDT 24 5499303560 ps
T902 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2364786777 May 23 04:02:41 PM PDT 24 May 23 04:07:47 PM PDT 24 3651947226 ps
T903 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4263312463 May 23 04:02:55 PM PDT 24 May 23 04:07:06 PM PDT 24 2750836271 ps
T681 /workspace/coverage/default/6.chip_sw_all_escalation_resets.1706398501 May 23 04:17:01 PM PDT 24 May 23 04:27:31 PM PDT 24 4941236852 ps
T262 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1184351149 May 23 04:01:04 PM PDT 24 May 23 04:09:33 PM PDT 24 3799636878 ps
T79 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3765242324 May 23 04:22:44 PM PDT 24 May 23 04:32:50 PM PDT 24 4097941452 ps
T695 /workspace/coverage/default/44.chip_sw_all_escalation_resets.745723469 May 23 04:25:06 PM PDT 24 May 23 04:33:02 PM PDT 24 3769894070 ps
T904 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2804673394 May 23 04:02:52 PM PDT 24 May 23 04:09:17 PM PDT 24 6173847000 ps
T905 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.641992992 May 23 04:01:27 PM PDT 24 May 23 04:08:06 PM PDT 24 4337660460 ps
T136 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1681054602 May 23 04:01:55 PM PDT 24 May 23 04:06:41 PM PDT 24 2793046352 ps
T363 /workspace/coverage/default/52.chip_sw_all_escalation_resets.2278953722 May 23 04:21:17 PM PDT 24 May 23 04:31:27 PM PDT 24 5258641272 ps
T364 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3095107654 May 23 03:57:35 PM PDT 24 May 23 04:02:33 PM PDT 24 2495523804 ps
T365 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2478845709 May 23 04:24:41 PM PDT 24 May 23 04:32:11 PM PDT 24 4361301624 ps
T366 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1996643180 May 23 03:57:55 PM PDT 24 May 23 04:06:43 PM PDT 24 6023261188 ps
T320 /workspace/coverage/default/1.chip_sw_hmac_enc.3122686403 May 23 04:01:38 PM PDT 24 May 23 04:07:00 PM PDT 24 3399973640 ps
T209 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1852491872 May 23 03:59:28 PM PDT 24 May 23 04:18:21 PM PDT 24 5851086448 ps
T367 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2249728103 May 23 04:04:08 PM PDT 24 May 23 04:07:46 PM PDT 24 2785029084 ps
T368 /workspace/coverage/default/4.chip_tap_straps_prod.4281675152 May 23 04:16:12 PM PDT 24 May 23 04:49:20 PM PDT 24 17937215903 ps
T38 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1494630293 May 23 04:01:51 PM PDT 24 May 23 04:07:54 PM PDT 24 3328395864 ps
T906 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.448382768 May 23 04:02:34 PM PDT 24 May 23 04:12:14 PM PDT 24 4119598908 ps
T907 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1824895923 May 23 04:05:33 PM PDT 24 May 23 04:19:25 PM PDT 24 9625567658 ps
T908 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2361851693 May 23 04:18:07 PM PDT 24 May 23 04:30:54 PM PDT 24 3824801300 ps
T739 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.799422278 May 23 04:20:55 PM PDT 24 May 23 04:27:52 PM PDT 24 3658943404 ps
T909 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2793084165 May 23 04:03:16 PM PDT 24 May 23 04:13:59 PM PDT 24 3934883012 ps
T910 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4060920250 May 23 04:04:14 PM PDT 24 May 23 04:16:14 PM PDT 24 4958024060 ps
T911 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1306990566 May 23 04:19:23 PM PDT 24 May 23 04:33:14 PM PDT 24 4026716984 ps
T371 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.940740112 May 23 04:12:16 PM PDT 24 May 23 04:30:46 PM PDT 24 13039256920 ps
T221 /workspace/coverage/default/24.chip_sw_all_escalation_resets.749805605 May 23 04:20:01 PM PDT 24 May 23 04:30:21 PM PDT 24 6397442960 ps
T263 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1084279346 May 23 04:15:23 PM PDT 24 May 23 04:23:46 PM PDT 24 5360736100 ps
T912 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.735721278 May 23 04:06:41 PM PDT 24 May 23 05:09:30 PM PDT 24 13743382333 ps
T913 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3738218597 May 23 04:21:07 PM PDT 24 May 23 05:15:23 PM PDT 24 15049152645 ps
T264 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2470011257 May 23 04:01:13 PM PDT 24 May 23 04:10:43 PM PDT 24 4909579792 ps
T914 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2560130757 May 23 04:03:56 PM PDT 24 May 23 04:26:48 PM PDT 24 5546832364 ps
T915 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3949457056 May 23 04:03:55 PM PDT 24 May 23 04:13:19 PM PDT 24 4050026950 ps
T916 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.570894298 May 23 04:03:15 PM PDT 24 May 23 04:11:18 PM PDT 24 4426639612 ps
T917 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2812503304 May 23 04:05:04 PM PDT 24 May 23 04:11:23 PM PDT 24 3714912365 ps
T713 /workspace/coverage/default/85.chip_sw_all_escalation_resets.807356901 May 23 04:22:30 PM PDT 24 May 23 04:35:29 PM PDT 24 5136097720 ps
T918 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1276621290 May 23 04:02:03 PM PDT 24 May 23 04:09:56 PM PDT 24 4155537560 ps
T919 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1857811683 May 23 04:01:18 PM PDT 24 May 23 04:05:32 PM PDT 24 2766805904 ps
T182 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1698410492 May 23 04:00:50 PM PDT 24 May 23 04:25:06 PM PDT 24 6962826364 ps
T920 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.776544266 May 23 04:02:56 PM PDT 24 May 23 04:10:12 PM PDT 24 6054823176 ps
T921 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3414358208 May 23 04:10:59 PM PDT 24 May 23 04:14:16 PM PDT 24 2856800168 ps
T236 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2959386975 May 23 04:03:30 PM PDT 24 May 23 04:24:53 PM PDT 24 4744210044 ps
T294 /workspace/coverage/default/2.chip_plic_all_irqs_0.1407665699 May 23 04:15:56 PM PDT 24 May 23 04:37:24 PM PDT 24 6258685600 ps
T119 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.350443515 May 23 04:02:08 PM PDT 24 May 23 04:10:14 PM PDT 24 7209706240 ps
T763 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2043788141 May 23 04:22:57 PM PDT 24 May 23 04:30:20 PM PDT 24 4058541648 ps
T659 /workspace/coverage/default/0.chip_sw_power_sleep_load.576205499 May 23 03:58:29 PM PDT 24 May 23 04:07:12 PM PDT 24 10397297000 ps
T321 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1086754600 May 23 04:05:10 PM PDT 24 May 23 04:09:29 PM PDT 24 2968966253 ps
T922 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4269936033 May 23 04:00:07 PM PDT 24 May 23 04:26:20 PM PDT 24 10096463354 ps
T923 /workspace/coverage/default/0.chip_sw_aes_smoketest.1253839568 May 23 04:02:41 PM PDT 24 May 23 04:07:37 PM PDT 24 2959045918 ps
T216 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3102156468 May 23 04:01:34 PM PDT 24 May 23 04:28:10 PM PDT 24 21102636635 ps
T313 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3873226002 May 23 04:15:41 PM PDT 24 May 23 04:47:43 PM PDT 24 13468640435 ps
T74 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.4263209544 May 23 04:09:30 PM PDT 24 May 23 04:33:00 PM PDT 24 11448961678 ps
T761 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3773929248 May 23 04:22:24 PM PDT 24 May 23 04:27:58 PM PDT 24 3783463160 ps
T649 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3219475458 May 23 04:02:39 PM PDT 24 May 23 04:07:31 PM PDT 24 3531277396 ps
T728 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3948213560 May 23 04:18:27 PM PDT 24 May 23 04:26:49 PM PDT 24 4113011112 ps
T924 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.345151405 May 23 04:12:01 PM PDT 24 May 23 04:22:01 PM PDT 24 4836756108 ps
T925 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2930608104 May 23 04:04:00 PM PDT 24 May 23 04:10:11 PM PDT 24 3139037390 ps
T740 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077296702 May 23 04:24:10 PM PDT 24 May 23 04:30:32 PM PDT 24 3865649800 ps
T926 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1799473288 May 23 04:12:16 PM PDT 24 May 23 04:19:32 PM PDT 24 4341169584 ps
T301 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.4185133778 May 23 04:10:44 PM PDT 24 May 23 04:31:18 PM PDT 24 5737035356 ps
T413 /workspace/coverage/default/0.chip_sw_edn_boot_mode.1467788552 May 23 04:02:45 PM PDT 24 May 23 04:12:19 PM PDT 24 3087697800 ps
T927 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1009643843 May 23 03:58:02 PM PDT 24 May 23 04:07:02 PM PDT 24 4356732458 ps
T331 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3602500275 May 23 04:16:03 PM PDT 24 May 23 04:22:25 PM PDT 24 5246161000 ps
T278 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.793505807 May 23 04:21:33 PM PDT 24 May 23 04:27:13 PM PDT 24 3853161226 ps
T137 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.4294658692 May 23 04:02:52 PM PDT 24 May 23 04:05:53 PM PDT 24 2346599494 ps
T120 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.988276682 May 23 04:15:10 PM PDT 24 May 23 04:36:51 PM PDT 24 21037463480 ps
T282 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1543005885 May 23 04:18:38 PM PDT 24 May 23 04:23:54 PM PDT 24 3612818696 ps
T283 /workspace/coverage/default/31.chip_sw_all_escalation_resets.213155711 May 23 04:21:13 PM PDT 24 May 23 04:27:52 PM PDT 24 5261255200 ps
T65 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2030937896 May 23 04:13:54 PM PDT 24 May 23 04:21:36 PM PDT 24 3354213864 ps
T284 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3312442062 May 23 04:17:26 PM PDT 24 May 23 04:28:48 PM PDT 24 7305738000 ps
T285 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2211749604 May 23 04:03:43 PM PDT 24 May 23 04:08:40 PM PDT 24 2747403940 ps
T286 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.822756373 May 23 04:01:56 PM PDT 24 May 23 04:51:34 PM PDT 24 12210629176 ps
T287 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3323548143 May 23 04:07:19 PM PDT 24 May 23 04:17:37 PM PDT 24 3258506520 ps
T750 /workspace/coverage/default/1.chip_sw_all_escalation_resets.47863125 May 23 04:02:27 PM PDT 24 May 23 04:13:48 PM PDT 24 5863265340 ps
T757 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.61819090 May 23 04:23:18 PM PDT 24 May 23 04:29:27 PM PDT 24 3629124080 ps
T928 /workspace/coverage/default/1.chip_sw_csrng_kat_test.278608294 May 23 04:08:01 PM PDT 24 May 23 04:11:26 PM PDT 24 2728690832 ps
T929 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2725554934 May 23 04:18:24 PM PDT 24 May 23 04:52:56 PM PDT 24 8371229004 ps
T734 /workspace/coverage/default/11.chip_sw_all_escalation_resets.2245390006 May 23 04:20:13 PM PDT 24 May 23 04:30:34 PM PDT 24 5595115552 ps
T265 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.167486053 May 23 04:12:00 PM PDT 24 May 23 04:23:49 PM PDT 24 5587362238 ps
T58 /workspace/coverage/default/2.chip_jtag_csr_rw.781737101 May 23 04:06:10 PM PDT 24 May 23 04:36:42 PM PDT 24 18076070447 ps
T930 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4043603352 May 23 04:03:56 PM PDT 24 May 23 04:23:57 PM PDT 24 9123415952 ps
T222 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1301266375 May 23 04:07:02 PM PDT 24 May 23 04:29:09 PM PDT 24 12131660050 ps
T140 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3129784484 May 23 04:03:31 PM PDT 24 May 23 04:45:54 PM PDT 24 14070846269 ps
T931 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4105749299 May 23 04:02:51 PM PDT 24 May 23 04:07:12 PM PDT 24 3222169000 ps
T932 /workspace/coverage/default/0.chip_sw_aes_enc.165385007 May 23 03:58:56 PM PDT 24 May 23 04:03:27 PM PDT 24 2798572482 ps
T933 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1618842141 May 23 04:13:46 PM PDT 24 May 23 04:24:00 PM PDT 24 5253260870 ps
T322 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.365896873 May 23 04:04:57 PM PDT 24 May 23 04:15:36 PM PDT 24 4337129128 ps
T193 /workspace/coverage/default/0.chip_sw_gpio_smoketest.166915889 May 23 04:01:10 PM PDT 24 May 23 04:05:43 PM PDT 24 2748387739 ps
T625 /workspace/coverage/default/0.chip_sw_edn_auto_mode.362864892 May 23 04:06:10 PM PDT 24 May 23 04:29:42 PM PDT 24 5474688700 ps
T36 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2398642181 May 23 04:06:07 PM PDT 24 May 23 04:13:22 PM PDT 24 5227448716 ps
T934 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4019418929 May 23 04:05:06 PM PDT 24 May 23 05:42:08 PM PDT 24 22377862832 ps
T935 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2878685567 May 23 04:13:54 PM PDT 24 May 23 04:23:47 PM PDT 24 5235477030 ps
T936 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.906019548 May 23 04:14:20 PM PDT 24 May 23 04:26:58 PM PDT 24 4055067982 ps
T110 /workspace/coverage/default/98.chip_sw_all_escalation_resets.720291515 May 23 04:25:22 PM PDT 24 May 23 04:35:53 PM PDT 24 4815529624 ps
T937 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3419170827 May 23 04:18:28 PM PDT 24 May 23 04:25:49 PM PDT 24 4210179008 ps
T938 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1046077642 May 23 04:04:20 PM PDT 24 May 23 05:05:09 PM PDT 24 14522890368 ps
T939 /workspace/coverage/default/4.chip_tap_straps_dev.3777265177 May 23 04:17:38 PM PDT 24 May 23 04:30:29 PM PDT 24 6996852440 ps
T12 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2921210009 May 23 03:59:55 PM PDT 24 May 23 04:04:45 PM PDT 24 2711346756 ps
T940 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2785079346 May 23 04:04:19 PM PDT 24 May 23 04:12:35 PM PDT 24 4014390387 ps
T941 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2367684397 May 23 04:21:06 PM PDT 24 May 23 04:29:01 PM PDT 24 3863067210 ps
T686 /workspace/coverage/default/71.chip_sw_all_escalation_resets.1007041117 May 23 04:21:43 PM PDT 24 May 23 04:33:30 PM PDT 24 4472521240 ps
T238 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3245217716 May 23 04:00:50 PM PDT 24 May 23 04:13:25 PM PDT 24 5226566200 ps
T377 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3309042807 May 23 04:01:34 PM PDT 24 May 23 04:05:15 PM PDT 24 3145055438 ps
T699 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.894910953 May 23 04:21:39 PM PDT 24 May 23 04:27:28 PM PDT 24 3307391950 ps
T758 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.958632931 May 23 04:20:59 PM PDT 24 May 23 04:29:04 PM PDT 24 3594483406 ps
T332 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3025979725 May 23 04:04:21 PM PDT 24 May 23 04:11:51 PM PDT 24 5300523000 ps
T215 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2495927119 May 23 04:00:19 PM PDT 24 May 23 04:41:00 PM PDT 24 23208348798 ps
T731 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3264778844 May 23 04:21:47 PM PDT 24 May 23 04:28:51 PM PDT 24 4300198072 ps
T769 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2622909359 May 23 04:22:26 PM PDT 24 May 23 04:29:16 PM PDT 24 3831003636 ps
T751 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3129949206 May 23 04:22:23 PM PDT 24 May 23 04:32:55 PM PDT 24 5322334082 ps
T702 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2803751018 May 23 04:22:23 PM PDT 24 May 23 04:30:38 PM PDT 24 5836214076 ps
T942 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2342803778 May 23 04:18:53 PM PDT 24 May 23 04:29:33 PM PDT 24 3911230440 ps
T943 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2244836203 May 23 04:11:50 PM PDT 24 May 23 04:16:52 PM PDT 24 3060364108 ps
T944 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1368227618 May 23 04:00:22 PM PDT 24 May 23 04:06:27 PM PDT 24 3343125316 ps
T945 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1652080670 May 23 04:16:59 PM PDT 24 May 23 04:53:50 PM PDT 24 13978021558 ps
T21 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1901724043 May 23 03:57:49 PM PDT 24 May 23 04:23:46 PM PDT 24 20461027802 ps
T253 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3015090979 May 23 03:59:47 PM PDT 24 May 23 04:12:30 PM PDT 24 6490900000 ps
T50 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3585629789 May 23 04:00:24 PM PDT 24 May 23 04:07:08 PM PDT 24 3758099864 ps
T255 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3065453946 May 23 04:16:15 PM PDT 24 May 23 04:23:03 PM PDT 24 3640058412 ps
T256 /workspace/coverage/default/1.chip_sw_otbn_randomness.128209050 May 23 04:04:52 PM PDT 24 May 23 04:20:37 PM PDT 24 5735854612 ps
T183 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.375201276 May 23 04:11:16 PM PDT 24 May 23 04:34:10 PM PDT 24 6544395732 ps
T213 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.4150952855 May 23 04:14:45 PM PDT 24 May 23 05:21:38 PM PDT 24 17213530832 ps
T257 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.211340581 May 23 04:02:13 PM PDT 24 May 23 04:06:28 PM PDT 24 2031496365 ps
T258 /workspace/coverage/default/2.chip_sw_aon_timer_irq.512305448 May 23 04:00:26 PM PDT 24 May 23 04:06:58 PM PDT 24 4105206308 ps
T121 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1412783538 May 23 04:00:45 PM PDT 24 May 23 04:39:39 PM PDT 24 21989386252 ps
T259 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.360877601 May 23 04:17:25 PM PDT 24 May 23 04:25:10 PM PDT 24 4101465592 ps
T946 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3518733027 May 23 04:03:55 PM PDT 24 May 23 04:07:48 PM PDT 24 2660247075 ps
T947 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.179733464 May 23 04:20:35 PM PDT 24 May 23 04:27:16 PM PDT 24 3309964210 ps
T948 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1422647323 May 23 04:05:13 PM PDT 24 May 23 04:26:38 PM PDT 24 9176325050 ps
T227 /workspace/coverage/default/0.chip_jtag_mem_access.3584959203 May 23 03:48:19 PM PDT 24 May 23 04:12:58 PM PDT 24 13557167998 ps
T949 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1644713726 May 23 04:07:57 PM PDT 24 May 23 04:36:00 PM PDT 24 12888166564 ps
T950 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.456784279 May 23 04:12:45 PM PDT 24 May 23 04:23:57 PM PDT 24 3437580360 ps
T951 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2793242109 May 23 04:06:49 PM PDT 24 May 23 05:15:00 PM PDT 24 14374840880 ps
T952 /workspace/coverage/default/0.chip_sw_aes_idle.1587541514 May 23 04:04:54 PM PDT 24 May 23 04:08:16 PM PDT 24 2492660000 ps
T378 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1090936718 May 23 04:14:45 PM PDT 24 May 23 04:25:49 PM PDT 24 9452232097 ps
T752 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3276336701 May 23 04:21:45 PM PDT 24 May 23 04:28:25 PM PDT 24 3532886920 ps
T953 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.334422084 May 23 04:03:38 PM PDT 24 May 23 04:13:20 PM PDT 24 3042525256 ps
T229 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3142377379 May 23 04:12:28 PM PDT 24 May 23 04:17:03 PM PDT 24 2972953440 ps
T954 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1245668943 May 23 04:01:31 PM PDT 24 May 23 04:32:09 PM PDT 24 18618950594 ps
T230 /workspace/coverage/default/1.chip_sw_power_sleep_load.179062278 May 23 04:02:33 PM PDT 24 May 23 04:08:51 PM PDT 24 3765521384 ps
T746 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1184461018 May 23 04:20:14 PM PDT 24 May 23 04:26:58 PM PDT 24 3055506094 ps
T737 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2959182226 May 23 04:21:35 PM PDT 24 May 23 04:27:56 PM PDT 24 3570675578 ps
T955 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3440145988 May 23 04:01:45 PM PDT 24 May 23 04:07:36 PM PDT 24 3279742079 ps
T68 /workspace/coverage/default/0.chip_tap_straps_testunlock0.2043053122 May 23 04:05:33 PM PDT 24 May 23 04:08:03 PM PDT 24 2799639447 ps
T742 /workspace/coverage/default/50.chip_sw_all_escalation_resets.1596704138 May 23 04:22:23 PM PDT 24 May 23 04:32:27 PM PDT 24 4317170800 ps
T7 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1426819794 May 23 03:59:48 PM PDT 24 May 23 04:04:35 PM PDT 24 3109648344 ps
T710 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.956148464 May 23 04:22:27 PM PDT 24 May 23 04:27:33 PM PDT 24 3664885160 ps
T956 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.420202962 May 23 04:00:00 PM PDT 24 May 23 04:06:37 PM PDT 24 5119423966 ps
T957 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1108190877 May 23 04:00:52 PM PDT 24 May 23 04:07:31 PM PDT 24 6455576277 ps
T958 /workspace/coverage/default/2.chip_sw_example_manufacturer.3715980800 May 23 04:08:20 PM PDT 24 May 23 04:12:29 PM PDT 24 2683046784 ps
T959 /workspace/coverage/default/0.chip_sw_example_concurrency.4234552421 May 23 03:59:31 PM PDT 24 May 23 04:03:53 PM PDT 24 2687742920 ps
T683 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2742618785 May 23 04:20:11 PM PDT 24 May 23 04:28:19 PM PDT 24 3378234950 ps
T631 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.551254269 May 23 04:00:30 PM PDT 24 May 23 04:30:05 PM PDT 24 13075551400 ps
T960 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.472251912 May 23 04:14:05 PM PDT 24 May 23 05:14:40 PM PDT 24 13529077928 ps
T327 /workspace/coverage/default/1.chip_sw_aon_timer_irq.517931584 May 23 04:03:39 PM PDT 24 May 23 04:12:15 PM PDT 24 4280163518 ps
T8 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.483849848 May 23 04:07:51 PM PDT 24 May 23 04:12:23 PM PDT 24 3119516693 ps
T961 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2368108211 May 23 03:58:38 PM PDT 24 May 23 04:09:10 PM PDT 24 4207605956 ps
T962 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.2395661044 May 23 04:08:17 PM PDT 24 May 23 04:12:03 PM PDT 24 2521592151 ps
T963 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1674322464 May 23 04:05:49 PM PDT 24 May 23 04:19:07 PM PDT 24 8649974120 ps
T964 /workspace/coverage/default/0.chip_sw_csrng_kat_test.1452030145 May 23 03:57:53 PM PDT 24 May 23 04:01:18 PM PDT 24 2919131000 ps
T9 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1310959582 May 23 04:05:42 PM PDT 24 May 23 04:12:17 PM PDT 24 3316604480 ps
T965 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503069383 May 23 04:19:54 PM PDT 24 May 23 04:25:47 PM PDT 24 3645020140 ps
T771 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4190811626 May 23 04:23:34 PM PDT 24 May 23 04:31:01 PM PDT 24 3816718506 ps
T276 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.882578700 May 23 04:04:17 PM PDT 24 May 23 04:16:23 PM PDT 24 8826214146 ps
T966 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1126471566 May 23 04:02:58 PM PDT 24 May 23 04:31:22 PM PDT 24 7360996472 ps
T650 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3102069481 May 23 03:59:51 PM PDT 24 May 23 04:05:03 PM PDT 24 2848259492 ps
T627 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2889273998 May 23 04:10:14 PM PDT 24 May 23 04:19:57 PM PDT 24 2971506050 ps
T203 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3278216887 May 23 03:59:33 PM PDT 24 May 23 04:59:41 PM PDT 24 19921716318 ps
T967 /workspace/coverage/default/2.chip_sw_edn_sw_mode.10728355 May 23 04:09:50 PM PDT 24 May 23 04:38:30 PM PDT 24 8384883524 ps
T968 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1687979131 May 23 03:58:19 PM PDT 24 May 23 04:09:04 PM PDT 24 5086347496 ps
T969 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4133798021 May 23 04:02:29 PM PDT 24 May 23 04:06:59 PM PDT 24 2478941160 ps
T970 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2675053214 May 23 04:06:25 PM PDT 24 May 23 04:15:23 PM PDT 24 8129128835 ps
T971 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2740275954 May 23 04:08:44 PM PDT 24 May 23 04:13:40 PM PDT 24 2279936300 ps
T972 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3962069763 May 23 04:13:38 PM PDT 24 May 23 04:24:28 PM PDT 24 4432277544 ps
T973 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1517337575 May 23 04:02:37 PM PDT 24 May 23 04:11:55 PM PDT 24 7089745325 ps
T974 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.129158176 May 23 04:16:29 PM PDT 24 May 23 04:29:56 PM PDT 24 4443240848 ps
T753 /workspace/coverage/default/68.chip_sw_all_escalation_resets.1300968896 May 23 04:20:42 PM PDT 24 May 23 04:31:29 PM PDT 24 4799453230 ps
T975 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.432947535 May 23 04:09:40 PM PDT 24 May 23 04:14:57 PM PDT 24 4995582328 ps
T676 /workspace/coverage/default/37.chip_sw_all_escalation_resets.2133365788 May 23 04:20:19 PM PDT 24 May 23 04:30:55 PM PDT 24 5911615068 ps
T976 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1048425846 May 23 04:11:56 PM PDT 24 May 23 04:17:11 PM PDT 24 2959161795 ps
T977 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2460042664 May 23 04:03:48 PM PDT 24 May 23 04:24:33 PM PDT 24 6537579660 ps
T978 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1062293472 May 23 04:06:28 PM PDT 24 May 23 05:03:55 PM PDT 24 17714047108 ps
T979 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2216172604 May 23 04:04:19 PM PDT 24 May 23 04:11:59 PM PDT 24 4233592297 ps
T310 /workspace/coverage/default/1.chip_sw_pattgen_ios.885396064 May 23 04:02:10 PM PDT 24 May 23 04:06:30 PM PDT 24 2883715746 ps
T980 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4249950125 May 23 04:15:40 PM PDT 24 May 23 04:40:00 PM PDT 24 9535433977 ps
T670 /workspace/coverage/default/15.chip_sw_all_escalation_resets.686978525 May 23 04:19:58 PM PDT 24 May 23 04:31:56 PM PDT 24 4402719452 ps
T333 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161839504 May 23 04:22:57 PM PDT 24 May 23 04:30:37 PM PDT 24 4459807460 ps
T336 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.962633037 May 23 04:07:04 PM PDT 24 May 23 04:17:51 PM PDT 24 5125433352 ps
T337 /workspace/coverage/default/0.chip_sw_example_rom.825167493 May 23 03:56:19 PM PDT 24 May 23 03:58:39 PM PDT 24 2577688140 ps
T338 /workspace/coverage/default/2.chip_sw_aes_masking_off.2107899377 May 23 04:05:59 PM PDT 24 May 23 04:11:28 PM PDT 24 2669878554 ps
T339 /workspace/coverage/default/2.chip_sw_power_sleep_load.1030291858 May 23 04:15:16 PM PDT 24 May 23 04:23:38 PM PDT 24 10526520056 ps
T340 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1236746618 May 23 03:59:11 PM PDT 24 May 23 04:06:56 PM PDT 24 3744413432 ps
T341 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.135472643 May 23 04:07:28 PM PDT 24 May 23 04:30:48 PM PDT 24 7070866172 ps
T342 /workspace/coverage/default/1.chip_sw_edn_kat.1622211971 May 23 04:03:22 PM PDT 24 May 23 04:15:10 PM PDT 24 3638777624 ps
T343 /workspace/coverage/default/2.chip_sw_aes_smoketest.654424858 May 23 04:18:08 PM PDT 24 May 23 04:23:01 PM PDT 24 3448489712 ps
T344 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.229246014 May 23 04:00:18 PM PDT 24 May 23 04:20:10 PM PDT 24 6245381815 ps
T323 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.973541849 May 23 04:04:44 PM PDT 24 May 23 04:14:00 PM PDT 24 3236065256 ps
T981 /workspace/coverage/default/2.chip_sw_all_escalation_resets.4032250612 May 23 03:59:32 PM PDT 24 May 23 04:05:42 PM PDT 24 3674953380 ps
T723 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2193125086 May 23 04:19:28 PM PDT 24 May 23 04:27:16 PM PDT 24 3534593464 ps
T982 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1693795441 May 23 04:15:26 PM PDT 24 May 23 04:21:08 PM PDT 24 2804754940 ps
T720 /workspace/coverage/default/61.chip_sw_all_escalation_resets.375000730 May 23 04:22:26 PM PDT 24 May 23 04:30:23 PM PDT 24 5821543250 ps
T668 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2639546369 May 23 04:18:24 PM PDT 24 May 23 04:30:37 PM PDT 24 5671117684 ps
T983 /workspace/coverage/default/1.chip_sw_gpio_smoketest.4227399458 May 23 04:05:34 PM PDT 24 May 23 04:09:51 PM PDT 24 2862617732 ps
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