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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.37 95.32 93.65 91.81 94.46 97.38 99.58


Total test records in report: 2801
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T1147 /workspace/coverage/default/0.chip_sw_example_flash.891040083 May 23 03:58:56 PM PDT 24 May 23 04:02:57 PM PDT 24 2451209150 ps
T1148 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3617769657 May 23 04:23:30 PM PDT 24 May 23 04:30:46 PM PDT 24 4044889670 ps
T359 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2034522568 May 23 04:01:51 PM PDT 24 May 23 04:19:17 PM PDT 24 4984912040 ps
T1149 /workspace/coverage/default/1.chip_sw_power_idle_load.3354309583 May 23 04:00:55 PM PDT 24 May 23 04:12:33 PM PDT 24 4451217038 ps
T1150 /workspace/coverage/default/2.chip_sw_otbn_smoketest.950878745 May 23 04:17:20 PM PDT 24 May 23 04:54:06 PM PDT 24 10930513456 ps
T1151 /workspace/coverage/default/1.chip_sw_aes_smoketest.1752964207 May 23 04:06:47 PM PDT 24 May 23 04:11:20 PM PDT 24 3259172294 ps
T1152 /workspace/coverage/default/0.chip_sw_aes_masking_off.970259786 May 23 03:59:05 PM PDT 24 May 23 04:03:54 PM PDT 24 2633532247 ps
T1153 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4284041131 May 23 04:07:05 PM PDT 24 May 23 04:10:36 PM PDT 24 3224201600 ps
T191 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3883342431 May 23 03:58:36 PM PDT 24 May 23 04:02:20 PM PDT 24 2612411548 ps
T1154 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.852846586 May 23 04:10:03 PM PDT 24 May 23 05:23:28 PM PDT 24 18674966096 ps
T1155 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.630656130 May 23 04:06:51 PM PDT 24 May 23 04:13:46 PM PDT 24 4140017377 ps
T697 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3121923348 May 23 04:22:13 PM PDT 24 May 23 04:30:12 PM PDT 24 3819707968 ps
T1156 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2247542509 May 23 04:04:33 PM PDT 24 May 23 04:11:44 PM PDT 24 5035929864 ps
T1157 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2290713910 May 23 04:08:13 PM PDT 24 May 23 04:18:41 PM PDT 24 3769647348 ps
T1158 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3131468164 May 23 04:16:01 PM PDT 24 May 23 04:26:54 PM PDT 24 7857940911 ps
T1159 /workspace/coverage/default/2.chip_tap_straps_dev.54444557 May 23 04:13:10 PM PDT 24 May 23 04:16:08 PM PDT 24 3185535438 ps
T1160 /workspace/coverage/default/1.chip_tap_straps_rma.2832778850 May 23 04:01:59 PM PDT 24 May 23 04:05:55 PM PDT 24 2388604963 ps
T1161 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2009191423 May 23 04:18:57 PM PDT 24 May 23 04:27:06 PM PDT 24 3264090410 ps
T1162 /workspace/coverage/default/1.rom_e2e_shutdown_output.3827975182 May 23 04:11:03 PM PDT 24 May 23 05:03:27 PM PDT 24 27489855224 ps
T715 /workspace/coverage/default/76.chip_sw_all_escalation_resets.1402218052 May 23 04:21:37 PM PDT 24 May 23 04:32:09 PM PDT 24 5200940858 ps
T1163 /workspace/coverage/default/12.chip_sw_all_escalation_resets.2513965380 May 23 04:24:11 PM PDT 24 May 23 04:37:27 PM PDT 24 5619863664 ps
T1164 /workspace/coverage/default/2.chip_sw_csrng_smoketest.838189580 May 23 04:15:32 PM PDT 24 May 23 04:20:27 PM PDT 24 3293725880 ps
T1165 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2870693297 May 23 04:00:31 PM PDT 24 May 23 04:04:39 PM PDT 24 2979384530 ps
T1166 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.4032379136 May 23 04:04:16 PM PDT 24 May 23 05:09:23 PM PDT 24 13779113346 ps
T1167 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3945633156 May 23 04:02:35 PM PDT 24 May 23 04:10:25 PM PDT 24 3381288970 ps
T1168 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4176993772 May 23 03:59:30 PM PDT 24 May 23 04:20:10 PM PDT 24 8152533032 ps
T1169 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2372539069 May 23 04:02:13 PM PDT 24 May 23 04:15:11 PM PDT 24 4313086688 ps
T188 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3138601684 May 23 03:57:53 PM PDT 24 May 23 04:05:35 PM PDT 24 4875070000 ps
T643 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1777248560 May 23 04:20:57 PM PDT 24 May 23 04:30:47 PM PDT 24 4440858008 ps
T281 /workspace/coverage/default/47.chip_sw_all_escalation_resets.2016607234 May 23 04:20:42 PM PDT 24 May 23 04:28:58 PM PDT 24 5276737418 ps
T335 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1159343040 May 23 04:22:33 PM PDT 24 May 23 04:34:48 PM PDT 24 5299940664 ps
T630 /workspace/coverage/default/1.chip_sw_edn_boot_mode.471732212 May 23 04:03:26 PM PDT 24 May 23 04:11:01 PM PDT 24 2696937320 ps
T736 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2410091318 May 23 04:22:35 PM PDT 24 May 23 04:35:06 PM PDT 24 5138442822 ps
T700 /workspace/coverage/default/51.chip_sw_all_escalation_resets.61150651 May 23 04:21:54 PM PDT 24 May 23 04:34:48 PM PDT 24 5510355050 ps
T1170 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2539269872 May 23 04:01:40 PM PDT 24 May 23 04:05:03 PM PDT 24 2242044530 ps
T1171 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4190399542 May 23 04:05:36 PM PDT 24 May 23 04:12:32 PM PDT 24 4591912802 ps
T1172 /workspace/coverage/default/0.chip_tap_straps_rma.123695079 May 23 04:05:08 PM PDT 24 May 23 04:07:45 PM PDT 24 2897725580 ps
T242 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1302848154 May 23 04:24:48 PM PDT 24 May 23 04:37:51 PM PDT 24 5536402522 ps
T1173 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3376144949 May 23 04:18:35 PM PDT 24 May 23 05:09:09 PM PDT 24 11214175012 ps
T330 /workspace/coverage/default/2.chip_sw_hmac_enc.2199620172 May 23 04:11:13 PM PDT 24 May 23 04:15:38 PM PDT 24 2899736348 ps
T1174 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3646290389 May 23 04:26:57 PM PDT 24 May 23 04:33:31 PM PDT 24 3828638240 ps
T1175 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1993731134 May 23 04:00:32 PM PDT 24 May 23 04:07:13 PM PDT 24 2782976104 ps
T101 /workspace/coverage/default/0.chip_sw_usbdev_pullup.3396689363 May 23 03:59:07 PM PDT 24 May 23 04:03:33 PM PDT 24 3429160180 ps
T1176 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2703969538 May 23 04:08:10 PM PDT 24 May 23 04:12:02 PM PDT 24 2250638248 ps
T1177 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.4219159767 May 23 04:15:44 PM PDT 24 May 23 04:20:18 PM PDT 24 2333789012 ps
T1178 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3581975180 May 23 04:02:05 PM PDT 24 May 23 04:08:22 PM PDT 24 4412512612 ps
T1179 /workspace/coverage/default/0.chip_sw_example_manufacturer.164448810 May 23 03:57:49 PM PDT 24 May 23 04:01:45 PM PDT 24 2661909570 ps
T128 /workspace/coverage/default/2.chip_plic_all_irqs_10.1240087721 May 23 04:12:48 PM PDT 24 May 23 04:23:05 PM PDT 24 3875079744 ps
T1180 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3712982903 May 23 04:16:40 PM PDT 24 May 23 04:20:11 PM PDT 24 2698394308 ps
T1181 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3015664617 May 23 04:18:42 PM PDT 24 May 23 04:38:56 PM PDT 24 5076313496 ps
T1182 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2706758176 May 23 04:02:07 PM PDT 24 May 23 04:07:49 PM PDT 24 3137759818 ps
T412 /workspace/coverage/default/2.chip_jtag_mem_access.883882250 May 23 04:06:10 PM PDT 24 May 23 04:29:04 PM PDT 24 13220024712 ps
T1183 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2169825154 May 23 04:10:57 PM PDT 24 May 23 04:27:00 PM PDT 24 6068635784 ps
T1184 /workspace/coverage/default/0.chip_sw_kmac_smoketest.2896933041 May 23 04:01:35 PM PDT 24 May 23 04:05:48 PM PDT 24 2792031880 ps
T1185 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3547153594 May 23 04:04:12 PM PDT 24 May 23 04:12:55 PM PDT 24 6548864296 ps
T1186 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2293658308 May 23 04:00:40 PM PDT 24 May 23 04:21:19 PM PDT 24 11572148010 ps
T1187 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.321640644 May 23 04:01:05 PM PDT 24 May 23 04:13:12 PM PDT 24 5368317760 ps
T1188 /workspace/coverage/default/0.rom_e2e_smoke.691611166 May 23 04:03:48 PM PDT 24 May 23 04:59:02 PM PDT 24 14025785998 ps
T1189 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2958937086 May 23 04:01:47 PM PDT 24 May 23 04:09:05 PM PDT 24 3638875270 ps
T1190 /workspace/coverage/default/1.chip_sival_flash_info_access.3525012564 May 23 04:01:12 PM PDT 24 May 23 04:07:21 PM PDT 24 3841134696 ps
T1191 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.470998121 May 23 04:15:30 PM PDT 24 May 23 04:29:50 PM PDT 24 3930734100 ps
T1192 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1698894847 May 23 04:07:43 PM PDT 24 May 23 04:17:59 PM PDT 24 4019548084 ps
T1193 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1904454247 May 23 04:02:20 PM PDT 24 May 23 04:15:11 PM PDT 24 3580876080 ps
T1194 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2273141568 May 23 04:07:40 PM PDT 24 May 23 05:03:43 PM PDT 24 14566830190 ps
T1195 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1300802558 May 23 04:04:20 PM PDT 24 May 23 04:15:52 PM PDT 24 4317771294 ps
T1196 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.4138604911 May 23 04:16:37 PM PDT 24 May 23 04:28:43 PM PDT 24 5131063850 ps
T270 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3744796210 May 23 04:05:37 PM PDT 24 May 23 04:11:27 PM PDT 24 3156586000 ps
T1197 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3389581158 May 23 04:14:01 PM PDT 24 May 23 05:11:06 PM PDT 24 14535679722 ps
T1198 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3567992970 May 23 04:07:59 PM PDT 24 May 23 05:15:44 PM PDT 24 15758112400 ps
T1199 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4109380483 May 23 04:02:36 PM PDT 24 May 23 04:09:47 PM PDT 24 4027914138 ps
T1200 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238605309 May 23 04:21:31 PM PDT 24 May 23 04:28:29 PM PDT 24 2927335190 ps
T1201 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3532989608 May 23 04:17:25 PM PDT 24 May 23 05:00:15 PM PDT 24 13872711816 ps
T1202 /workspace/coverage/default/1.chip_sw_example_rom.141428899 May 23 04:00:14 PM PDT 24 May 23 04:02:06 PM PDT 24 2223238680 ps
T1203 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3900951031 May 23 04:04:30 PM PDT 24 May 23 04:22:59 PM PDT 24 6733030040 ps
T1204 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4122155600 May 23 04:04:15 PM PDT 24 May 23 04:45:55 PM PDT 24 23058041368 ps
T1205 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3512767807 May 23 04:00:51 PM PDT 24 May 23 04:07:29 PM PDT 24 4452157248 ps
T1206 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3706821817 May 23 04:00:22 PM PDT 24 May 23 04:09:06 PM PDT 24 5227090968 ps
T1207 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2846523324 May 23 04:03:20 PM PDT 24 May 23 04:22:44 PM PDT 24 5807208340 ps
T95 /workspace/coverage/default/1.chip_sw_alert_test.3593596188 May 23 04:02:59 PM PDT 24 May 23 04:08:11 PM PDT 24 2930896024 ps
T27 /workspace/coverage/default/2.chip_sw_gpio.895639054 May 23 04:00:52 PM PDT 24 May 23 04:08:23 PM PDT 24 4036943500 ps
T254 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2968168028 May 23 04:21:51 PM PDT 24 May 23 04:33:42 PM PDT 24 4852311918 ps
T1208 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2402926460 May 23 04:03:01 PM PDT 24 May 23 04:10:46 PM PDT 24 4578144364 ps
T1209 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1400236582 May 23 04:05:49 PM PDT 24 May 23 05:42:16 PM PDT 24 21473692946 ps
T745 /workspace/coverage/default/75.chip_sw_all_escalation_resets.861500641 May 23 04:21:43 PM PDT 24 May 23 04:34:26 PM PDT 24 4420464600 ps
T129 /workspace/coverage/default/0.chip_plic_all_irqs_10.3459474082 May 23 04:03:11 PM PDT 24 May 23 04:12:08 PM PDT 24 3239372800 ps
T111 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626547579 May 23 04:22:55 PM PDT 24 May 23 04:31:11 PM PDT 24 3904317142 ps
T755 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3165736955 May 23 04:19:54 PM PDT 24 May 23 04:30:32 PM PDT 24 4697709564 ps
T762 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3569808005 May 23 04:22:35 PM PDT 24 May 23 04:32:14 PM PDT 24 5026585816 ps
T1210 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3019226180 May 23 04:24:07 PM PDT 24 May 23 04:30:12 PM PDT 24 4192292036 ps
T1211 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1351141538 May 23 04:03:28 PM PDT 24 May 23 04:07:45 PM PDT 24 2898278326 ps
T1212 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1153954554 May 23 04:24:48 PM PDT 24 May 23 04:32:34 PM PDT 24 3292258460 ps
T1213 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3857755842 May 23 04:05:39 PM PDT 24 May 23 04:51:47 PM PDT 24 10908572498 ps
T1214 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1141262946 May 23 04:04:30 PM PDT 24 May 23 04:19:27 PM PDT 24 7123546340 ps
T1215 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2341274541 May 23 04:05:03 PM PDT 24 May 23 04:22:27 PM PDT 24 5772650982 ps
T1216 /workspace/coverage/default/1.rom_e2e_asm_init_dev.3361158144 May 23 04:07:42 PM PDT 24 May 23 05:05:47 PM PDT 24 14429201103 ps
T718 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3074748928 May 23 04:18:13 PM PDT 24 May 23 04:24:40 PM PDT 24 3460652096 ps
T726 /workspace/coverage/default/83.chip_sw_all_escalation_resets.591480204 May 23 04:21:54 PM PDT 24 May 23 04:30:46 PM PDT 24 4550754568 ps
T1217 /workspace/coverage/default/73.chip_sw_all_escalation_resets.4050158501 May 23 04:22:11 PM PDT 24 May 23 04:32:55 PM PDT 24 6293710218 ps
T1218 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1153883203 May 23 04:08:45 PM PDT 24 May 23 04:15:49 PM PDT 24 4818069560 ps
T1219 /workspace/coverage/default/3.chip_sw_uart_tx_rx.285480996 May 23 04:18:13 PM PDT 24 May 23 04:30:03 PM PDT 24 4214384672 ps
T1220 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.84507021 May 23 04:25:38 PM PDT 24 May 23 04:32:11 PM PDT 24 3354504562 ps
T96 /workspace/coverage/default/0.chip_sw_alert_test.1189015975 May 23 03:58:05 PM PDT 24 May 23 04:03:07 PM PDT 24 3019705520 ps
T1221 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3386001870 May 23 04:07:02 PM PDT 24 May 23 04:16:56 PM PDT 24 18579908026 ps
T268 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1512605558 May 23 04:21:16 PM PDT 24 May 23 04:28:47 PM PDT 24 4285592364 ps
T1222 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1987922782 May 23 04:17:33 PM PDT 24 May 23 04:27:30 PM PDT 24 3766326944 ps
T1223 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1547096707 May 23 04:00:32 PM PDT 24 May 23 04:40:35 PM PDT 24 22818991558 ps
T360 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1932340268 May 23 04:00:58 PM PDT 24 May 23 04:15:39 PM PDT 24 5153399400 ps
T1224 /workspace/coverage/default/2.chip_sw_flash_crash_alert.585215991 May 23 04:16:02 PM PDT 24 May 23 04:26:27 PM PDT 24 5255557380 ps
T1225 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1198815107 May 23 04:07:18 PM PDT 24 May 23 07:13:34 PM PDT 24 255247116380 ps
T130 /workspace/coverage/default/1.chip_plic_all_irqs_10.2977574961 May 23 04:03:09 PM PDT 24 May 23 04:12:51 PM PDT 24 3746732542 ps
T1226 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.214163811 May 23 04:17:57 PM PDT 24 May 23 04:27:43 PM PDT 24 3250833510 ps
T1227 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3424571253 May 23 04:06:38 PM PDT 24 May 23 04:11:02 PM PDT 24 3825053042 ps
T1228 /workspace/coverage/default/4.chip_sw_uart_tx_rx.4089337965 May 23 04:16:16 PM PDT 24 May 23 04:25:06 PM PDT 24 4705896920 ps
T743 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2048511566 May 23 04:22:40 PM PDT 24 May 23 04:30:27 PM PDT 24 3201865312 ps
T663 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2629165411 May 23 04:00:58 PM PDT 24 May 23 04:16:04 PM PDT 24 4673969920 ps
T1229 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2090579658 May 23 04:12:27 PM PDT 24 May 23 04:18:03 PM PDT 24 3120449080 ps
T1230 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3914866454 May 23 04:03:45 PM PDT 24 May 23 04:09:14 PM PDT 24 3303487442 ps
T1231 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3014010680 May 23 04:17:39 PM PDT 24 May 23 04:24:46 PM PDT 24 5815332456 ps
T1232 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3229492450 May 23 03:59:07 PM PDT 24 May 23 04:08:20 PM PDT 24 3492761400 ps
T307 /workspace/coverage/default/2.chip_plic_all_irqs_20.3005768110 May 23 04:12:00 PM PDT 24 May 23 04:23:06 PM PDT 24 4350138360 ps
T112 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.860094906 May 23 04:25:07 PM PDT 24 May 23 04:32:26 PM PDT 24 3744770392 ps
T747 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3140326182 May 23 04:22:14 PM PDT 24 May 23 04:27:55 PM PDT 24 3302783304 ps
T1233 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1286162563 May 23 04:01:02 PM PDT 24 May 23 04:08:37 PM PDT 24 4147585600 ps
T1234 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3461798782 May 23 04:18:06 PM PDT 24 May 23 04:23:01 PM PDT 24 3181422227 ps
T1235 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3165179927 May 23 04:00:51 PM PDT 24 May 23 04:10:42 PM PDT 24 4470886428 ps
T1236 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.574039736 May 23 04:04:16 PM PDT 24 May 23 04:15:37 PM PDT 24 4219002629 ps
T153 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3103193064 May 23 04:05:28 PM PDT 24 May 23 04:13:47 PM PDT 24 4978239576 ps
T703 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3652336931 May 23 04:20:48 PM PDT 24 May 23 04:31:44 PM PDT 24 5229641800 ps
T1237 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3579914107 May 23 04:19:50 PM PDT 24 May 23 04:25:14 PM PDT 24 3702674612 ps
T1238 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3574992411 May 23 04:04:06 PM PDT 24 May 23 04:07:08 PM PDT 24 2398922030 ps
T39 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1053752670 May 23 04:05:12 PM PDT 24 May 23 04:11:33 PM PDT 24 3065852118 ps
T1239 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3257490953 May 23 04:02:59 PM PDT 24 May 23 05:00:24 PM PDT 24 17563247406 ps
T51 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1649430142 May 23 04:05:09 PM PDT 24 May 23 04:10:57 PM PDT 24 6076059480 ps
T388 /workspace/coverage/default/29.chip_sw_all_escalation_resets.762506747 May 23 04:21:10 PM PDT 24 May 23 04:32:27 PM PDT 24 4258428820 ps
T212 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.956880757 May 23 04:05:28 PM PDT 24 May 23 04:36:29 PM PDT 24 8396296018 ps
T389 /workspace/coverage/default/28.chip_sw_all_escalation_resets.3011194919 May 23 04:20:24 PM PDT 24 May 23 04:30:59 PM PDT 24 4716850800 ps
T390 /workspace/coverage/default/2.chip_sw_kmac_app_rom.4144801375 May 23 04:12:04 PM PDT 24 May 23 04:15:17 PM PDT 24 2519597996 ps
T391 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2948541834 May 23 04:21:58 PM PDT 24 May 23 04:31:35 PM PDT 24 5112163088 ps
T392 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.810819117 May 23 04:05:00 PM PDT 24 May 23 04:09:34 PM PDT 24 2540170328 ps
T393 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2334845035 May 23 04:06:52 PM PDT 24 May 23 04:11:14 PM PDT 24 2312510024 ps
T314 /workspace/coverage/default/0.chip_sw_pattgen_ios.3980125009 May 23 04:01:08 PM PDT 24 May 23 04:05:26 PM PDT 24 3145589880 ps
T394 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.576278307 May 23 04:01:51 PM PDT 24 May 23 04:10:12 PM PDT 24 5039699756 ps
T243 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3641231876 May 23 04:18:29 PM PDT 24 May 23 04:27:20 PM PDT 24 5715081086 ps
T28 /workspace/coverage/default/0.chip_sw_gpio.3055459656 May 23 04:03:32 PM PDT 24 May 23 04:12:36 PM PDT 24 4150470092 ps
T1240 /workspace/coverage/default/1.rom_e2e_asm_init_prod.868831819 May 23 04:12:18 PM PDT 24 May 23 05:10:21 PM PDT 24 14258530514 ps
T297 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.953605861 May 23 04:15:35 PM PDT 24 May 23 04:26:13 PM PDT 24 4516680271 ps
T1241 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2317279962 May 23 04:19:43 PM PDT 24 May 23 04:26:09 PM PDT 24 4002132712 ps
T764 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.416406359 May 23 04:21:07 PM PDT 24 May 23 04:29:00 PM PDT 24 4109026504 ps
T289 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1073382315 May 23 04:04:40 PM PDT 24 May 23 04:34:45 PM PDT 24 9776848388 ps
T271 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.551875955 May 23 04:14:16 PM PDT 24 May 23 04:19:03 PM PDT 24 2954111522 ps
T1242 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3061069867 May 23 04:09:35 PM PDT 24 May 23 04:13:18 PM PDT 24 2669756948 ps
T54 /workspace/coverage/cover_reg_top/3.xbar_smoke.4194819877 May 23 04:18:54 PM PDT 24 May 23 04:19:08 PM PDT 24 258433857 ps
T55 /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.1886433639 May 23 04:32:12 PM PDT 24 May 23 04:32:36 PM PDT 24 520675026 ps
T56 /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.3559350004 May 23 04:39:52 PM PDT 24 May 23 04:41:10 PM PDT 24 6633056714 ps
T59 /workspace/coverage/cover_reg_top/75.xbar_stress_all.3500981224 May 23 04:36:49 PM PDT 24 May 23 04:43:41 PM PDT 24 10761245364 ps
T103 /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2277932941 May 23 04:32:13 PM PDT 24 May 23 04:49:40 PM PDT 24 95187847578 ps
T507 /workspace/coverage/cover_reg_top/33.xbar_smoke.1136961388 May 23 04:30:00 PM PDT 24 May 23 04:30:10 PM PDT 24 125389635 ps
T491 /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.1084976896 May 23 04:30:14 PM PDT 24 May 23 04:30:33 PM PDT 24 117561903 ps
T405 /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.4255396473 May 23 04:26:39 PM PDT 24 May 23 04:27:25 PM PDT 24 475767611 ps
T225 /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2737573075 May 23 04:31:54 PM PDT 24 May 23 04:32:37 PM PDT 24 338842694 ps
T226 /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3300922800 May 23 04:32:35 PM PDT 24 May 23 04:33:00 PM PDT 24 158641599 ps
T414 /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.1576035188 May 23 04:40:26 PM PDT 24 May 23 04:42:15 PM PDT 24 1212945170 ps
T166 /workspace/coverage/cover_reg_top/9.chip_csr_rw.143097028 May 23 04:23:14 PM PDT 24 May 23 04:29:37 PM PDT 24 3986673654 ps
T642 /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3310573634 May 23 04:16:57 PM PDT 24 May 23 04:27:17 PM PDT 24 5742020653 ps
T497 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2573805765 May 23 04:35:32 PM PDT 24 May 23 04:37:40 PM PDT 24 1566750620 ps
T560 /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1834921508 May 23 04:37:32 PM PDT 24 May 23 04:39:17 PM PDT 24 9224238177 ps
T511 /workspace/coverage/cover_reg_top/97.xbar_random.3729256977 May 23 04:40:11 PM PDT 24 May 23 04:40:36 PM PDT 24 594225758 ps
T509 /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3665775719 May 23 04:36:53 PM PDT 24 May 23 04:41:03 PM PDT 24 708186987 ps
T403 /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2952138042 May 23 04:35:46 PM PDT 24 May 23 04:40:51 PM PDT 24 16303794246 ps
T510 /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2156315377 May 23 04:37:58 PM PDT 24 May 23 04:39:22 PM PDT 24 7429326462 ps
T508 /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1399878488 May 23 04:38:11 PM PDT 24 May 23 04:40:03 PM PDT 24 6077408588 ps
T503 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.407020006 May 23 04:33:38 PM PDT 24 May 23 04:34:30 PM PDT 24 287043934 ps
T406 /workspace/coverage/cover_reg_top/3.xbar_same_source.1382544792 May 23 04:19:20 PM PDT 24 May 23 04:19:45 PM PDT 24 241973820 ps
T493 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3548647248 May 23 04:35:23 PM PDT 24 May 23 04:37:39 PM PDT 24 1541686303 ps
T501 /workspace/coverage/cover_reg_top/42.xbar_random.1603182981 May 23 04:31:52 PM PDT 24 May 23 04:33:16 PM PDT 24 2169976354 ps
T797 /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2146797571 May 23 04:30:15 PM PDT 24 May 23 04:31:55 PM PDT 24 5391067966 ps
T502 /workspace/coverage/cover_reg_top/3.xbar_error_random.2045652046 May 23 04:20:12 PM PDT 24 May 23 04:21:32 PM PDT 24 2035010254 ps
T514 /workspace/coverage/cover_reg_top/62.xbar_access_same_device.3175309386 May 23 04:34:51 PM PDT 24 May 23 04:35:53 PM PDT 24 1581848643 ps
T513 /workspace/coverage/cover_reg_top/87.xbar_smoke.2087381317 May 23 04:38:22 PM PDT 24 May 23 04:38:30 PM PDT 24 150942228 ps
T498 /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.3446587408 May 23 04:26:58 PM PDT 24 May 23 04:27:27 PM PDT 24 573756548 ps
T494 /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3115811540 May 23 04:27:11 PM PDT 24 May 23 04:57:12 PM PDT 24 97746672944 ps
T644 /workspace/coverage/cover_reg_top/85.xbar_access_same_device.1948376912 May 23 04:38:10 PM PDT 24 May 23 04:39:22 PM PDT 24 1543268323 ps
T404 /workspace/coverage/cover_reg_top/74.xbar_smoke.3154992845 May 23 04:36:30 PM PDT 24 May 23 04:36:40 PM PDT 24 154620809 ps
T495 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1725447947 May 23 04:17:44 PM PDT 24 May 23 04:21:12 PM PDT 24 544219120 ps
T1243 /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.622481065 May 23 04:30:03 PM PDT 24 May 23 04:30:11 PM PDT 24 58495524 ps
T499 /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1508220198 May 23 04:30:01 PM PDT 24 May 23 04:31:02 PM PDT 24 3238297460 ps
T496 /workspace/coverage/cover_reg_top/1.xbar_random.2751562152 May 23 04:16:53 PM PDT 24 May 23 04:17:30 PM PDT 24 958666549 ps
T504 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.840417840 May 23 04:29:46 PM PDT 24 May 23 04:34:53 PM PDT 24 8616082141 ps
T512 /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3613917852 May 23 04:33:48 PM PDT 24 May 23 04:35:33 PM PDT 24 2968564206 ps
T505 /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1246313642 May 23 04:36:57 PM PDT 24 May 23 04:54:22 PM PDT 24 19591426382 ps
T521 /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1163194768 May 23 04:35:20 PM PDT 24 May 23 04:36:19 PM PDT 24 1141893667 ps
T636 /workspace/coverage/cover_reg_top/79.xbar_error_random.2353717780 May 23 04:37:30 PM PDT 24 May 23 04:37:55 PM PDT 24 263890299 ps
T571 /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.4155284154 May 23 04:39:03 PM PDT 24 May 23 04:41:51 PM PDT 24 9561822586 ps
T1244 /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1716806690 May 23 04:37:27 PM PDT 24 May 23 04:38:49 PM PDT 24 4583957008 ps
T506 /workspace/coverage/cover_reg_top/85.xbar_error_random.4172934543 May 23 04:38:16 PM PDT 24 May 23 04:39:47 PM PDT 24 2333502351 ps
T666 /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.120310546 May 23 04:28:30 PM PDT 24 May 23 04:29:40 PM PDT 24 1923735037 ps
T350 /workspace/coverage/cover_reg_top/1.chip_csr_rw.2563939759 May 23 04:17:34 PM PDT 24 May 23 04:29:20 PM PDT 24 5995446342 ps
T1245 /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1577062234 May 23 04:39:53 PM PDT 24 May 23 04:40:03 PM PDT 24 58044957 ps
T796 /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2583148758 May 23 04:39:56 PM PDT 24 May 23 04:43:59 PM PDT 24 3361646695 ps
T1246 /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2697775725 May 23 04:28:46 PM PDT 24 May 23 04:29:20 PM PDT 24 260605194 ps
T1247 /workspace/coverage/cover_reg_top/40.xbar_smoke.739183469 May 23 04:31:30 PM PDT 24 May 23 04:31:40 PM PDT 24 168765738 ps
T585 /workspace/coverage/cover_reg_top/55.xbar_smoke.4017396840 May 23 04:33:36 PM PDT 24 May 23 04:33:42 PM PDT 24 38024917 ps
T500 /workspace/coverage/cover_reg_top/13.xbar_stress_all.2534032990 May 23 04:24:45 PM PDT 24 May 23 04:29:18 PM PDT 24 2751113491 ps
T1248 /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.897416169 May 23 04:32:42 PM PDT 24 May 23 04:32:49 PM PDT 24 39827860 ps
T556 /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.1548017051 May 23 04:34:34 PM PDT 24 May 23 04:35:01 PM PDT 24 251637118 ps
T542 /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3289649554 May 23 04:24:02 PM PDT 24 May 23 04:30:37 PM PDT 24 21911027947 ps
T429 /workspace/coverage/cover_reg_top/32.xbar_same_source.3110903309 May 23 04:30:03 PM PDT 24 May 23 04:30:59 PM PDT 24 1600974250 ps
T533 /workspace/coverage/cover_reg_top/73.xbar_smoke.2182878412 May 23 04:36:17 PM PDT 24 May 23 04:36:26 PM PDT 24 141023929 ps
T772 /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3340239020 May 23 04:39:39 PM PDT 24 May 23 04:41:53 PM PDT 24 2791805686 ps
T1249 /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.1265792402 May 23 04:31:49 PM PDT 24 May 23 04:33:09 PM PDT 24 6980696477 ps
T427 /workspace/coverage/cover_reg_top/40.xbar_stress_all.137139545 May 23 04:31:29 PM PDT 24 May 23 04:32:37 PM PDT 24 1700683326 ps
T1250 /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3235496169 May 23 04:35:48 PM PDT 24 May 23 04:36:37 PM PDT 24 1054435360 ps
T385 /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2553042542 May 23 04:33:20 PM PDT 24 May 23 04:33:41 PM PDT 24 386333490 ps
T384 /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.4116230283 May 23 04:31:57 PM PDT 24 May 23 04:32:12 PM PDT 24 109275740 ps
T488 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4019343868 May 23 04:24:55 PM PDT 24 May 23 04:25:42 PM PDT 24 101733413 ps
T528 /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1823461930 May 23 04:33:22 PM PDT 24 May 23 04:34:50 PM PDT 24 4956039909 ps
T802 /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.4027105377 May 23 04:26:03 PM PDT 24 May 23 04:28:59 PM PDT 24 718759217 ps
T623 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1718691401 May 23 04:31:50 PM PDT 24 May 23 04:35:07 PM PDT 24 3316602165 ps
T515 /workspace/coverage/cover_reg_top/8.chip_tl_errors.4231648606 May 23 04:22:19 PM PDT 24 May 23 04:28:20 PM PDT 24 3692517620 ps
T386 /workspace/coverage/cover_reg_top/77.xbar_stress_all.2648923907 May 23 04:37:12 PM PDT 24 May 23 04:43:46 PM PDT 24 8819736405 ps
T1251 /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.964969145 May 23 04:34:18 PM PDT 24 May 23 04:35:36 PM PDT 24 7360646309 ps
T1252 /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.745298650 May 23 04:37:49 PM PDT 24 May 23 04:38:28 PM PDT 24 801062358 ps
T634 /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.2718503125 May 23 04:27:49 PM PDT 24 May 23 04:31:22 PM PDT 24 4709600455 ps
T1253 /workspace/coverage/cover_reg_top/95.xbar_error_random.3249452934 May 23 04:39:54 PM PDT 24 May 23 04:40:22 PM PDT 24 614792733 ps
T786 /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3815334677 May 23 04:24:20 PM PDT 24 May 23 04:29:48 PM PDT 24 17366237966 ps
T574 /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.1903753032 May 23 04:35:48 PM PDT 24 May 23 04:36:42 PM PDT 24 606829086 ps
T781 /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3572318654 May 23 04:33:49 PM PDT 24 May 23 04:58:39 PM PDT 24 84462315831 ps
T545 /workspace/coverage/cover_reg_top/14.xbar_same_source.2727500773 May 23 04:25:11 PM PDT 24 May 23 04:25:44 PM PDT 24 364039898 ps
T598 /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.1533772279 May 23 04:35:34 PM PDT 24 May 23 04:36:58 PM PDT 24 7336825651 ps
T523 /workspace/coverage/cover_reg_top/2.xbar_same_source.2089953245 May 23 04:18:24 PM PDT 24 May 23 04:19:16 PM PDT 24 597928591 ps
T1254 /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.4072701782 May 23 04:31:35 PM PDT 24 May 23 04:32:26 PM PDT 24 1218776618 ps
T1255 /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3194120159 May 23 04:34:04 PM PDT 24 May 23 04:34:24 PM PDT 24 352776822 ps
T780 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.612446124 May 23 04:24:58 PM PDT 24 May 23 04:29:01 PM PDT 24 2485912220 ps
T1256 /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.80984485 May 23 04:36:02 PM PDT 24 May 23 04:37:52 PM PDT 24 10462326471 ps
T558 /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.438539523 May 23 04:40:22 PM PDT 24 May 23 04:51:56 PM PDT 24 41036303805 ps
T449 /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.595459531 May 23 04:22:34 PM PDT 24 May 23 04:23:19 PM PDT 24 383738334 ps
T430 /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2327124587 May 23 04:31:16 PM PDT 24 May 23 04:35:43 PM PDT 24 691070598 ps
T782 /workspace/coverage/cover_reg_top/44.xbar_access_same_device.1814396765 May 23 04:32:13 PM PDT 24 May 23 04:34:04 PM PDT 24 2507150114 ps
T540 /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.516641257 May 23 04:40:09 PM PDT 24 May 23 04:40:22 PM PDT 24 95854838 ps
T1257 /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.4228165354 May 23 04:27:11 PM PDT 24 May 23 04:28:45 PM PDT 24 8761594631 ps
T553 /workspace/coverage/cover_reg_top/35.xbar_random.2859186863 May 23 04:30:28 PM PDT 24 May 23 04:30:52 PM PDT 24 477059386 ps
T778 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3776814128 May 23 04:37:31 PM PDT 24 May 23 04:42:30 PM PDT 24 3774922961 ps
T779 /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2908245412 May 23 04:32:36 PM PDT 24 May 23 04:54:41 PM PDT 24 72702946601 ps
T1258 /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1290767871 May 23 04:36:19 PM PDT 24 May 23 04:36:59 PM PDT 24 782002080 ps
T544 /workspace/coverage/cover_reg_top/48.xbar_smoke.3028563849 May 23 04:32:34 PM PDT 24 May 23 04:32:42 PM PDT 24 50942628 ps
T554 /workspace/coverage/cover_reg_top/80.xbar_stress_all.1982660577 May 23 04:37:31 PM PDT 24 May 23 04:37:56 PM PDT 24 669809055 ps
T596 /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3947191078 May 23 04:28:50 PM PDT 24 May 23 04:41:44 PM PDT 24 16572845016 ps
T517 /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.1329970570 May 23 04:39:06 PM PDT 24 May 23 04:44:42 PM PDT 24 4807350984 ps
T535 /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.712856318 May 23 04:34:10 PM PDT 24 May 23 04:51:17 PM PDT 24 95249993835 ps
T476 /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.592690483 May 23 04:39:05 PM PDT 24 May 23 04:46:16 PM PDT 24 39185022682 ps
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