Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.37	95.32	93.65	91.81		94.46	97.38	99.58

Total test records in report: 2801

T2756	/workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2558331595	May 23 04:35:06 PM PDT 24	May 23 04:35:14 PM PDT 24	42930233 ps
T2757	/workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.2910156464	May 23 04:29:47 PM PDT 24	May 23 04:29:55 PM PDT 24	49438736 ps
T2758	/workspace/coverage/cover_reg_top/12.xbar_random.483792654	May 23 04:24:20 PM PDT 24	May 23 04:25:27 PM PDT 24	1629482044 ps
T2759	/workspace/coverage/cover_reg_top/61.xbar_random_large_delays.388277176	May 23 04:34:30 PM PDT 24	May 23 04:45:27 PM PDT 24	58982690404 ps
T2760	/workspace/coverage/cover_reg_top/76.xbar_error_random.3126320351	May 23 04:36:50 PM PDT 24	May 23 04:37:37 PM PDT 24	502711321 ps
T2761	/workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3335463466	May 23 04:38:24 PM PDT 24	May 23 05:04:13 PM PDT 24	87870079620 ps
T2762	/workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.1352745953	May 23 04:31:12 PM PDT 24	May 23 04:31:53 PM PDT 24	423304879 ps
T2763	/workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.651299686	May 23 04:31:14 PM PDT 24	May 23 04:31:25 PM PDT 24	66484393 ps
T2764	/workspace/coverage/cover_reg_top/96.xbar_smoke.2362163590	May 23 04:39:58 PM PDT 24	May 23 04:40:06 PM PDT 24	54359543 ps
T2765	/workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2928182986	May 23 04:40:09 PM PDT 24	May 23 04:40:37 PM PDT 24	632572635 ps
T2766	/workspace/coverage/cover_reg_top/34.xbar_same_source.4196854399	May 23 04:30:19 PM PDT 24	May 23 04:30:48 PM PDT 24	329167532 ps
T2767	/workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2403219359	May 23 04:32:40 PM PDT 24	May 23 05:13:11 PM PDT 24	145405004913 ps
T2768	/workspace/coverage/cover_reg_top/33.xbar_access_same_device.2546299085	May 23 04:30:13 PM PDT 24	May 23 04:31:15 PM PDT 24	1318413319 ps
T2769	/workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1018869376	May 23 04:31:14 PM PDT 24	May 23 04:32:01 PM PDT 24	1095283874 ps
T2770	/workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3666377237	May 23 04:30:13 PM PDT 24	May 23 04:31:52 PM PDT 24	9224628909 ps
T2771	/workspace/coverage/cover_reg_top/60.xbar_same_source.3370736882	May 23 04:34:18 PM PDT 24	May 23 04:34:54 PM PDT 24	489315147 ps
T2772	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1486345448	May 23 04:35:26 PM PDT 24	May 23 04:42:39 PM PDT 24	10920912221 ps
T2773	/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.310927891	May 23 04:24:14 PM PDT 24	May 23 04:31:54 PM PDT 24	24254576737 ps
T2774	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1849772106	May 23 04:38:50 PM PDT 24	May 23 04:41:46 PM PDT 24	586484586 ps
T2775	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.106286573	May 23 04:39:02 PM PDT 24	May 23 04:40:39 PM PDT 24	905753118 ps
T2776	/workspace/coverage/cover_reg_top/19.xbar_smoke.2982567175	May 23 04:26:59 PM PDT 24	May 23 04:27:10 PM PDT 24	183966963 ps
T2777	/workspace/coverage/cover_reg_top/2.chip_csr_rw.3661548635	May 23 04:18:42 PM PDT 24	May 23 04:24:32 PM PDT 24	4288750801 ps
T2778	/workspace/coverage/cover_reg_top/38.xbar_stress_all.3610741849	May 23 04:31:17 PM PDT 24	May 23 04:40:53 PM PDT 24	14053145934 ps
T2779	/workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.3629500746	May 23 04:31:30 PM PDT 24	May 23 04:57:30 PM PDT 24	83648682747 ps
T2780	/workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1533404805	May 23 04:40:24 PM PDT 24	May 23 04:40:36 PM PDT 24	100242947 ps
T2781	/workspace/coverage/cover_reg_top/77.xbar_same_source.145577980	May 23 04:37:10 PM PDT 24	May 23 04:37:39 PM PDT 24	818804668 ps
T2782	/workspace/coverage/cover_reg_top/16.xbar_access_same_device.1560322251	May 23 04:25:40 PM PDT 24	May 23 04:27:11 PM PDT 24	2101295821 ps
T2783	/workspace/coverage/cover_reg_top/66.xbar_random.2214109876	May 23 04:35:23 PM PDT 24	May 23 04:35:41 PM PDT 24	381313613 ps
T2784	/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.624362522	May 23 04:17:08 PM PDT 24	May 23 04:18:02 PM PDT 24	873718441 ps
T2785	/workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1555428962	May 23 04:32:11 PM PDT 24	May 23 04:33:38 PM PDT 24	4799686360 ps
T2786	/workspace/coverage/cover_reg_top/7.chip_tl_errors.2896131015	May 23 04:21:45 PM PDT 24	May 23 04:25:20 PM PDT 24	3463759825 ps
T2787	/workspace/coverage/cover_reg_top/25.xbar_random_large_delays.226054774	May 23 04:28:29 PM PDT 24	May 23 04:48:00 PM PDT 24	103212566620 ps
T2788	/workspace/coverage/cover_reg_top/11.xbar_same_source.2644133027	May 23 04:23:48 PM PDT 24	May 23 04:24:14 PM PDT 24	641497379 ps
T2789	/workspace/coverage/cover_reg_top/59.xbar_smoke.829051699	May 23 04:34:03 PM PDT 24	May 23 04:34:10 PM PDT 24	45670103 ps
T2790	/workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2153610516	May 23 04:29:48 PM PDT 24	May 23 04:38:16 PM PDT 24	30091640380 ps
T2791	/workspace/coverage/cover_reg_top/59.xbar_stress_all.1730586103	May 23 04:34:17 PM PDT 24	May 23 04:35:13 PM PDT 24	1315373044 ps
T2792	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3409929162	May 23 04:26:59 PM PDT 24	May 23 04:32:29 PM PDT 24	3694168156 ps
T2793	/workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.691483114	May 23 04:37:11 PM PDT 24	May 23 04:37:44 PM PDT 24	665223988 ps
T2794	/workspace/coverage/cover_reg_top/0.xbar_random.766194878	May 23 04:15:45 PM PDT 24	May 23 04:16:36 PM PDT 24	460134740 ps
T2795	/workspace/coverage/cover_reg_top/35.xbar_error_random.3918863418	May 23 04:30:28 PM PDT 24	May 23 04:30:40 PM PDT 24	192460522 ps
T2796	/workspace/coverage/cover_reg_top/82.xbar_error_random.2085830580	May 23 04:37:49 PM PDT 24	May 23 04:38:10 PM PDT 24	480736143 ps
T29	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1397637387	May 23 04:40:38 PM PDT 24	May 23 04:44:03 PM PDT 24	4390706640 ps
T30	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2689315356	May 23 04:40:37 PM PDT 24	May 23 04:45:47 PM PDT 24	5777940747 ps
T31	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2419360816	May 23 04:40:35 PM PDT 24	May 23 04:45:01 PM PDT 24	4074999610 ps
T189	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3529844471	May 23 04:40:41 PM PDT 24	May 23 04:45:01 PM PDT 24	5146819965 ps
T195	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4147739081	May 23 04:40:42 PM PDT 24	May 23 04:44:08 PM PDT 24	4404230390 ps
T2797	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3219509846	May 23 04:40:42 PM PDT 24	May 23 04:45:03 PM PDT 24	5519822164 ps
T2798	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3358628330	May 23 04:40:35 PM PDT 24	May 23 04:44:43 PM PDT 24	4835996180 ps
T2799	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1597389820	May 23 04:40:35 PM PDT 24	May 23 04:43:46 PM PDT 24	4564350064 ps
T2800	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2606616335	May 23 04:40:35 PM PDT 24	May 23 04:45:09 PM PDT 24	5691365858 ps
T2801	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1552525248	May 23 04:40:34 PM PDT 24	May 23 04:44:04 PM PDT 24	4846133745 ps

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2873554504
Short name	T16
Test name
Test status
Simulation time	19148998056 ps
CPU time	1549.91 seconds
Started	May 23 04:02:05 PM PDT 24
Finished	May 23 04:27:57 PM PDT 24
Peak memory	603372 kb
Host	smart-81dd5d12-9c3d-4691-a504-565eb8c29bf5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2873554504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2873554504
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/cover_reg_top/9.chip_csr_rw.143097028
Short name	T166
Test name
Test status
Simulation time	3986673654 ps
CPU time	381.95 seconds
Started	May 23 04:23:14 PM PDT 24
Finished	May 23 04:29:37 PM PDT 24
Peak memory	590796 kb
Host	smart-f8658f7b-aad5-4e28-8757-0bd8b39415a6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143097028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.143097028
Directory	/workspace/9.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all.3500981224
Short name	T59
Test name
Test status
Simulation time	10761245364 ps
CPU time	410.71 seconds
Started	May 23 04:36:49 PM PDT 24
Finished	May 23 04:43:41 PM PDT 24
Peak memory	573060 kb
Host	smart-abdaf206-3bdc-4adf-900b-99a302dd7827
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500981224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.3500981224
Directory	/workspace/75.xbar_stress_all/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_0.3894903522
Short name	T290
Test name
Test status
Simulation time	5492307956 ps
CPU time	1258.26 seconds
Started	May 23 04:04:54 PM PDT 24
Finished	May 23 04:25:54 PM PDT 24
Peak memory	601656 kb
Host	smart-c3daf749-abdb-4d41-8015-e6f873ecb7fd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894903522 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.3894903522
Directory	/workspace/0.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1824903246
Short name	T426
Test name
Test status
Simulation time	137256611844 ps
CPU time	2291.17 seconds
Started	May 23 04:40:09 PM PDT 24
Finished	May 23 05:18:21 PM PDT 24
Peak memory	572060 kb
Host	smart-46062231-66cc-45dc-a9eb-daa2cfdab3dc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824903246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.1824903246
Directory	/workspace/97.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1397637387
Short name	T29
Test name
Test status
Simulation time	4390706640 ps
CPU time	204.84 seconds
Started	May 23 04:40:38 PM PDT 24
Finished	May 23 04:44:03 PM PDT 24
Peak memory	638584 kb
Host	smart-a74b0a8a-b6f3-4cec-b113-c1e9ea971b9c
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397637387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.1397637387
Directory	/workspace/7.chip_padctrl_attributes/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3523587267
Short name	T775
Test name
Test status
Simulation time	128484864326 ps
CPU time	2221.11 seconds
Started	May 23 04:31:35 PM PDT 24
Finished	May 23 05:08:37 PM PDT 24
Peak memory	572060 kb
Host	smart-5fadae81-13f9-4d4a-8e68-66d6bd253c0c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523587267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.3523587267
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_test.2149314313
Short name	T63
Test name
Test status
Simulation time	3243175872 ps
CPU time	337.53 seconds
Started	May 23 04:08:39 PM PDT 24
Finished	May 23 04:14:17 PM PDT 24
Peak memory	601676 kb
Host	smart-00e02e56-bc87-4b08-9491-b8b210884618
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149314313 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.2149314313
Directory	/workspace/2.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2666937944
Short name	T206
Test name
Test status
Simulation time	15126977472 ps
CPU time	3434.02 seconds
Started	May 23 04:03:44 PM PDT 24
Finished	May 23 05:01:00 PM PDT 24
Peak memory	603624 kb
Host	smart-4bbe9a69-8762-4dcb-bd22-86b30cc8ef16
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26669 37944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2666937944
Directory	/workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3115811540
Short name	T494
Test name
Test status
Simulation time	97746672944 ps
CPU time	1799.74 seconds
Started	May 23 04:27:11 PM PDT 24
Finished	May 23 04:57:12 PM PDT 24
Peak memory	572072 kb
Host	smart-3e4ded0a-7b04-4bc0-a204-efb2f22ebc43
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115811540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.3115811540
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/13.chip_sw_all_escalation_resets.862476878
Short name	T76
Test name
Test status
Simulation time	4218184472 ps
CPU time	651.66 seconds
Started	May 23 04:19:50 PM PDT 24
Finished	May 23 04:30:43 PM PDT 24
Peak memory	638372 kb
Host	smart-67827c93-c6b8-4356-a767-8b61314f260e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 862476878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.862476878
Directory	/workspace/13.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3795641848
Short name	T801
Test name
Test status
Simulation time	121687037292 ps
CPU time	2043.98 seconds
Started	May 23 04:34:47 PM PDT 24
Finished	May 23 05:08:53 PM PDT 24
Peak memory	572076 kb
Host	smart-f60ef67d-f632-4f11-8bd0-940e68f27c73
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795641848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.3795641848
Directory	/workspace/63.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.483849848
Short name	T8
Test name
Test status
Simulation time	3119516693 ps
CPU time	271.03 seconds
Started	May 23 04:07:51 PM PDT 24
Finished	May 23 04:12:23 PM PDT 24
Peak memory	601624 kb
Host	smart-ff914860-8097-426e-b513-70ded41e501f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4838 49848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.483849848
Directory	/workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1559252318
Short name	T422
Test name
Test status
Simulation time	5049852115 ps
CPU time	640.56 seconds
Started	May 23 04:39:23 PM PDT 24
Finished	May 23 04:50:06 PM PDT 24
Peak memory	573032 kb
Host	smart-77d4de6e-6c6e-442c-9b09-ca1625d949d4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559252318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.1559252318
Directory	/workspace/92.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.rom_e2e_smoke.3856444739
Short name	T41
Test name
Test status
Simulation time	14658761074 ps
CPU time	3073.83 seconds
Started	May 23 04:20:00 PM PDT 24
Finished	May 23 05:11:16 PM PDT 24
Peak memory	601892 kb
Host	smart-0b705b4a-4b41-4e90-abcc-8773a28c9b58
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3856444739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.3856444739
Directory	/workspace/2.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3744796210
Short name	T270
Test name
Test status
Simulation time	3156586000 ps
CPU time	348.85 seconds
Started	May 23 04:05:37 PM PDT 24
Finished	May 23 04:11:27 PM PDT 24
Peak memory	601368 kb
Host	smart-80a05e0d-7198-478c-bdee-8855dc1ffa33
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3744796210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.3744796210
Directory	/workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/1.chip_sw_gpio.259875779
Short name	T13
Test name
Test status
Simulation time	3768053506 ps
CPU time	423.17 seconds
Started	May 23 04:04:46 PM PDT 24
Finished	May 23 04:11:50 PM PDT 24
Peak memory	601808 kb
Host	smart-7ed4aa9e-b0f5-4942-b431-b8400130c01f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259875779 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_gpio.259875779
Directory	/workspace/1.chip_sw_gpio/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_20.2217770736
Short name	T291
Test name
Test status
Simulation time	4421450824 ps
CPU time	859.53 seconds
Started	May 23 04:07:07 PM PDT 24
Finished	May 23 04:21:28 PM PDT 24
Peak memory	601916 kb
Host	smart-a91496df-1992-4612-ad18-670f8025f937
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217770736 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.2217770736
Directory	/workspace/0.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1955773589
Short name	T60
Test name
Test status
Simulation time	7652215100 ps
CPU time	1006.53 seconds
Started	May 23 04:04:51 PM PDT 24
Finished	May 23 04:21:40 PM PDT 24
Peak memory	603612 kb
Host	smart-af4e85e7-42b7-434e-81fc-e52955c51f68
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955773589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.1955773589
Directory	/workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2977847365
Short name	T411
Test name
Test status
Simulation time	150088578998 ps
CPU time	2564.6 seconds
Started	May 23 04:35:33 PM PDT 24
Finished	May 23 05:18:19 PM PDT 24
Peak memory	571980 kb
Host	smart-8877d5d6-b5df-43d6-860a-5070845120b8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977847365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.2977847365
Directory	/workspace/67.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2573805765
Short name	T497
Test name
Test status
Simulation time	1566750620 ps
CPU time	126.23 seconds
Started	May 23 04:35:32 PM PDT 24
Finished	May 23 04:37:40 PM PDT 24
Peak memory	571908 kb
Host	smart-26b1c60a-bd80-4262-a354-5be99da719d7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573805765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.2573805765
Directory	/workspace/68.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.3995729415
Short name	T614
Test name
Test status
Simulation time	111135810564 ps
CPU time	1854.95 seconds
Started	May 23 04:28:01 PM PDT 24
Finished	May 23 04:58:57 PM PDT 24
Peak memory	572048 kb
Host	smart-f1d59f6c-517e-4e20-9792-c435a926d0be
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995729415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.3995729415
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1624316524
Short name	T149
Test name
Test status
Simulation time	5147650738 ps
CPU time	495.71 seconds
Started	May 23 04:16:12 PM PDT 24
Finished	May 23 04:24:30 PM PDT 24
Peak memory	601548 kb
Host	smart-b97a3c4a-f83c-4b1f-a66c-ed823525639a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16243165 24 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1624316524
Directory	/workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/cover_reg_top/26.chip_tl_errors.1357107413
Short name	T525
Test name
Test status
Simulation time	5947875650 ps
CPU time	649.8 seconds
Started	May 23 04:28:50 PM PDT 24
Finished	May 23 04:39:41 PM PDT 24
Peak memory	594952 kb
Host	smart-514b0ac8-1059-4819-b585-8764e1c6255f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357107413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.1357107413
Directory	/workspace/26.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.2434868277
Short name	T167
Test name
Test status
Simulation time	16776755674 ps
CPU time	2312.43 seconds
Started	May 23 04:22:56 PM PDT 24
Finished	May 23 05:01:29 PM PDT 24
Peak memory	586688 kb
Host	smart-c048a70e-de2c-48ff-98dc-dfa851fc320a
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434868277 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.2434868277
Directory	/workspace/9.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_randomness.1573110144
Short name	T93
Test name
Test status
Simulation time	5777546318 ps
CPU time	1046.04 seconds
Started	May 23 04:02:30 PM PDT 24
Finished	May 23 04:19:58 PM PDT 24
Peak memory	601864 kb
Host	smart-2dd4eca5-3baf-4b65-9a88-7ad989b0521d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1573110144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.1573110144
Directory	/workspace/0.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3882793752
Short name	T11
Test name
Test status
Simulation time	4194465305 ps
CPU time	417.75 seconds
Started	May 23 04:02:47 PM PDT 24
Finished	May 23 04:09:46 PM PDT 24
Peak memory	619508 kb
Host	smart-701b543d-bef8-4583-8d6b-b041875731e9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882793752 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.3882793752
Directory	/workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_init.2792154745
Short name	T88
Test name
Test status
Simulation time	17886347944 ps
CPU time	2130.23 seconds
Started	May 23 04:06:00 PM PDT 24
Finished	May 23 04:41:33 PM PDT 24
Peak memory	605968 kb
Host	smart-923d2cd3-acff-44cf-b7ec-618cbb9351d1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792154745 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.2792154745
Directory	/workspace/1.chip_sw_flash_init/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.4051604158
Short name	T454
Test name
Test status
Simulation time	91431680220 ps
CPU time	1652.3 seconds
Started	May 23 04:34:31 PM PDT 24
Finished	May 23 05:02:05 PM PDT 24
Peak memory	572040 kb
Host	smart-f5aeb7d8-4a53-4605-ba56-50e3f5facba5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051604158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.4051604158
Directory	/workspace/61.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3624618845
Short name	T73
Test name
Test status
Simulation time	6208933006 ps
CPU time	639.57 seconds
Started	May 23 03:59:57 PM PDT 24
Finished	May 23 04:10:39 PM PDT 24
Peak memory	603944 kb
Host	smart-5c25323a-ea29-4c60-9c77-fa4aaf26a1cb
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3624618845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3624618845
Directory	/workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_10.3459474082
Short name	T129
Test name
Test status
Simulation time	3239372800 ps
CPU time	535.08 seconds
Started	May 23 04:03:11 PM PDT 24
Finished	May 23 04:12:08 PM PDT 24
Peak memory	601708 kb
Host	smart-0aad2b55-19b5-4635-ae7d-188cb62580fa
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459474082 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.3459474082
Directory	/workspace/0.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1637093159
Short name	T32
Test name
Test status
Simulation time	5341443136 ps
CPU time	633.48 seconds
Started	May 23 04:00:35 PM PDT 24
Finished	May 23 04:11:10 PM PDT 24
Peak memory	611308 kb
Host	smart-83ab585c-e687-48e7-aa0c-540a1a89573f
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163709 3159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1637093159
Directory	/workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1426819794
Short name	T7
Test name
Test status
Simulation time	3109648344 ps
CPU time	285.89 seconds
Started	May 23 03:59:48 PM PDT 24
Finished	May 23 04:04:35 PM PDT 24
Peak memory	601784 kb
Host	smart-84714198-9dae-4f89-bd51-98fc47f58d0b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426 819794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1426819794
Directory	/workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2277932941
Short name	T103
Test name
Test status
Simulation time	95187847578 ps
CPU time	1046.04 seconds
Started	May 23 04:32:13 PM PDT 24
Finished	May 23 04:49:40 PM PDT 24
Peak memory	572048 kb
Host	smart-a1c09ae1-e9a3-4cdf-af31-b24b733662e4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277932941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2277932941
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3222374171
Short name	T151
Test name
Test status
Simulation time	8731770784 ps
CPU time	1122.34 seconds
Started	May 23 04:05:38 PM PDT 24
Finished	May 23 04:24:21 PM PDT 24
Peak memory	602172 kb
Host	smart-b18969db-caad-4bdd-b815-92f30c118a6f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32223741 71 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.3222374171
Directory	/workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3706769731
Short name	T72
Test name
Test status
Simulation time	13203973236 ps
CPU time	1611.37 seconds
Started	May 23 03:58:13 PM PDT 24
Finished	May 23 04:25:06 PM PDT 24
Peak memory	603156 kb
Host	smart-89e6a249-754d-4c90-b244-050c33edb46b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706769731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.3706769731
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.610196086
Short name	T132
Test name
Test status
Simulation time	4912683654 ps
CPU time	615.84 seconds
Started	May 23 04:14:39 PM PDT 24
Finished	May 23 04:24:57 PM PDT 24
Peak memory	602984 kb
Host	smart-d8d28e4d-7338-4515-88ae-e352cb3ad0e6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610196086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.610196086
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3687602362
Short name	T1737
Test name
Test status
Simulation time	142263871860 ps
CPU time	2506.51 seconds
Started	May 23 04:40:23 PM PDT 24
Finished	May 23 05:22:10 PM PDT 24
Peak memory	572064 kb
Host	smart-d9222759-9ae2-4b36-8911-7cecd614abc9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687602362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.3687602362
Directory	/workspace/98.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4269958974
Short name	T114
Test name
Test status
Simulation time	3762617080 ps
CPU time	379.09 seconds
Started	May 23 04:23:03 PM PDT 24
Finished	May 23 04:29:23 PM PDT 24
Peak memory	637488 kb
Host	smart-9ca38989-0526-4d8b-b6ed-54567a527c30
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269958974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4269958974
Directory	/workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1310959582
Short name	T9
Test name
Test status
Simulation time	3316604480 ps
CPU time	392.97 seconds
Started	May 23 04:05:42 PM PDT 24
Finished	May 23 04:12:17 PM PDT 24
Peak memory	602068 kb
Host	smart-fb598446-2cfe-4239-bc5e-2949d530542f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310 959582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.1310959582
Directory	/workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2844099961
Short name	T83
Test name
Test status
Simulation time	8138874615 ps
CPU time	436.82 seconds
Started	May 23 04:16:50 PM PDT 24
Finished	May 23 04:24:08 PM PDT 24
Peak memory	583316 kb
Host	smart-be485a9b-f954-42d8-9d6d-cd737a56f5c3
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844099961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.2844099961
Directory	/workspace/1.chip_prim_tl_access/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1246313642
Short name	T505
Test name
Test status
Simulation time	19591426382 ps
CPU time	1044.36 seconds
Started	May 23 04:36:57 PM PDT 24
Finished	May 23 04:54:22 PM PDT 24
Peak memory	573120 kb
Host	smart-e661e9ba-4a4b-4302-b4bf-944b7580ea13
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246313642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.1246313642
Directory	/workspace/76.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3308590082
Short name	T348
Test name
Test status
Simulation time	30283263916 ps
CPU time	3147.03 seconds
Started	May 23 04:26:58 PM PDT 24
Finished	May 23 05:19:26 PM PDT 24
Peak memory	587088 kb
Host	smart-97467ce4-a065-4f3d-9bff-669e74d940eb
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308590082 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.3308590082
Directory	/workspace/19.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.259435498
Short name	T190
Test name
Test status
Simulation time	2249644891 ps
CPU time	243.19 seconds
Started	May 23 04:04:38 PM PDT 24
Finished	May 23 04:08:44 PM PDT 24
Peak memory	605888 kb
Host	smart-dfc47f67-fa88-4cfc-83ce-d9927bc3e738
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259435498 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.259435498
Directory	/workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3281288538
Short name	T26
Test name
Test status
Simulation time	4611191680 ps
CPU time	339.45 seconds
Started	May 23 04:06:36 PM PDT 24
Finished	May 23 04:12:16 PM PDT 24
Peak memory	602092 kb
Host	smart-7fde3c75-db60-4737-8f2c-497da84118ad
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281288538 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.3281288538
Directory	/workspace/2.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/cover_reg_top/21.chip_tl_errors.3669994334
Short name	T564
Test name
Test status
Simulation time	5092068300 ps
CPU time	528.24 seconds
Started	May 23 04:27:23 PM PDT 24
Finished	May 23 04:36:12 PM PDT 24
Peak memory	594048 kb
Host	smart-ca308b0c-0c9c-4191-b57a-5674968d4735
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669994334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.3669994334
Directory	/workspace/21.chip_tl_errors/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_sw_mode.638246850
Short name	T91
Test name
Test status
Simulation time	6520148120 ps
CPU time	1412.97 seconds
Started	May 23 04:00:54 PM PDT 24
Finished	May 23 04:24:28 PM PDT 24
Peak memory	601820 kb
Host	smart-47eee68f-3216-4272-862c-3ff4ec08fa7d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638246850 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.638246850
Directory	/workspace/0.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_testunlock0.1248950651
Short name	T43
Test name
Test status
Simulation time	5386438291 ps
CPU time	543.81 seconds
Started	May 23 04:12:52 PM PDT 24
Finished	May 23 04:21:57 PM PDT 24
Peak memory	620780 kb
Host	smart-38214ce5-3dc6-4092-a61d-a55d70d40b75
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248950651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.1248950651
Directory	/workspace/2.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/0.chip_sw_power_sleep_load.576205499
Short name	T659
Test name
Test status
Simulation time	10397297000 ps
CPU time	521.43 seconds
Started	May 23 03:58:29 PM PDT 24
Finished	May 23 04:07:12 PM PDT 24
Peak memory	602652 kb
Host	smart-13146b81-71c8-4bbf-beb2-c276f765662b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576205499 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.576205499
Directory	/workspace/0.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.649217039
Short name	T142
Test name
Test status
Simulation time	11897306441 ps
CPU time	2566.23 seconds
Started	May 23 04:05:34 PM PDT 24
Finished	May 23 04:48:21 PM PDT 24
Peak memory	602036 kb
Host	smart-87d6f1db-089e-4587-a0cf-c6c8cd4e2b13
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649217039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ csrng_edn_concurrency_reduced_freq.649217039
Directory	/workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3776814128
Short name	T778
Test name
Test status
Simulation time	3774922961 ps
CPU time	297.39 seconds
Started	May 23 04:37:31 PM PDT 24
Finished	May 23 04:42:30 PM PDT 24
Peak memory	572136 kb
Host	smart-f76142cc-0c64-4c75-87ae-cc45ac19658a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776814128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.3776814128
Directory	/workspace/79.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3861259435
Short name	T241
Test name
Test status
Simulation time	5268065050 ps
CPU time	470.21 seconds
Started	May 23 04:20:06 PM PDT 24
Finished	May 23 04:27:57 PM PDT 24
Peak memory	640072 kb
Host	smart-a9dffc03-6ba2-4993-bcfa-5ac76aa6d38f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3861259435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.3861259435
Directory	/workspace/20.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161839504
Short name	T333
Test name
Test status
Simulation time	4459807460 ps
CPU time	459.14 seconds
Started	May 23 04:22:57 PM PDT 24
Finished	May 23 04:30:37 PM PDT 24
Peak memory	637500 kb
Host	smart-c09f9aab-7317-4cde-a266-3d492b77c29c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161839504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4161839504
Directory	/workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3685444957
Short name	T108
Test name
Test status
Simulation time	5678669714 ps
CPU time	606.68 seconds
Started	May 23 04:18:21 PM PDT 24
Finished	May 23 04:28:28 PM PDT 24
Peak memory	639088 kb
Host	smart-fb8ecd3f-6393-4f9b-86f1-5446b16c7819
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3685444957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.3685444957
Directory	/workspace/14.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3017383363
Short name	T279
Test name
Test status
Simulation time	5155300256 ps
CPU time	616.12 seconds
Started	May 23 04:19:23 PM PDT 24
Finished	May 23 04:29:40 PM PDT 24
Peak memory	638880 kb
Host	smart-d94b3823-ab4f-473c-a7d0-4152828dee5b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3017383363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3017383363
Directory	/workspace/27.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3015090979
Short name	T253
Test name
Test status
Simulation time	6490900000 ps
CPU time	760.38 seconds
Started	May 23 03:59:47 PM PDT 24
Finished	May 23 04:12:30 PM PDT 24
Peak memory	602708 kb
Host	smart-42251249-0344-4f79-b1b7-da6a14d7a4f6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3015090979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.3015090979
Directory	/workspace/0.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3561387677
Short name	T4
Test name
Test status
Simulation time	8920088160 ps
CPU time	491.38 seconds
Started	May 23 04:06:02 PM PDT 24
Finished	May 23 04:14:15 PM PDT 24
Peak memory	602272 kb
Host	smart-8f1d87d8-3fe4-429c-9320-6e0a921681d7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561387677 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.3561387677
Directory	/workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1859129772
Short name	T14
Test name
Test status
Simulation time	8707761242 ps
CPU time	1714.68 seconds
Started	May 23 04:21:22 PM PDT 24
Finished	May 23 04:49:58 PM PDT 24
Peak memory	611172 kb
Host	smart-033f7e7b-1ba9-4d3f-ae24-032a214523f9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859129772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.1859129772
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_init.98729220
Short name	T89
Test name
Test status
Simulation time	20485222840 ps
CPU time	2253.53 seconds
Started	May 23 04:02:12 PM PDT 24
Finished	May 23 04:39:49 PM PDT 24
Peak memory	606972 kb
Host	smart-fe575529-544b-48cb-8d64-07c00273480d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98729220 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.98729220
Directory	/workspace/2.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_entropy.3886035478
Short name	T176
Test name
Test status
Simulation time	2772387960 ps
CPU time	224.19 seconds
Started	May 23 04:01:54 PM PDT 24
Finished	May 23 04:05:39 PM PDT 24
Peak memory	601460 kb
Host	smart-db135366-49d4-4f8c-87a4-2eef77355e66
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886035478 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.3886035478
Directory	/workspace/0.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_0.1349282527
Short name	T293
Test name
Test status
Simulation time	6367693888 ps
CPU time	1215.04 seconds
Started	May 23 04:02:31 PM PDT 24
Finished	May 23 04:22:49 PM PDT 24
Peak memory	601684 kb
Host	smart-3ac8217d-8e21-4691-b14b-fb211a16795d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349282527 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.1349282527
Directory	/workspace/1.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3235614084
Short name	T416
Test name
Test status
Simulation time	7454617308 ps
CPU time	482.08 seconds
Started	May 23 04:33:47 PM PDT 24
Finished	May 23 04:41:51 PM PDT 24
Peak memory	573052 kb
Host	smart-a66449c6-7879-4932-b111-48e0624c4727
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235614084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.3235614084
Directory	/workspace/55.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.51842972
Short name	T49
Test name
Test status
Simulation time	2948125200 ps
CPU time	271.36 seconds
Started	May 23 04:07:29 PM PDT 24
Finished	May 23 04:12:02 PM PDT 24
Peak memory	601900 kb
Host	smart-a7331e13-ce0c-4f99-8d51-8a2ac5cbc1f5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51842972 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.51842972
Directory	/workspace/1.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.349399659
Short name	T154
Test name
Test status
Simulation time	7927561960 ps
CPU time	409.03 seconds
Started	May 23 04:20:32 PM PDT 24
Finished	May 23 04:27:22 PM PDT 24
Peak memory	656572 kb
Host	smart-2e8c7fc3-c7d1-45d9-8231-a22cee0c7e1a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349399659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_re set.349399659
Directory	/workspace/4.chip_csr_hw_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1649430142
Short name	T51
Test name
Test status
Simulation time	6076059480 ps
CPU time	346.72 seconds
Started	May 23 04:05:09 PM PDT 24
Finished	May 23 04:10:57 PM PDT 24
Peak memory	602492 kb
Host	smart-59a44cc8-98df-4289-a3cd-f9df18115f2a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649430142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.1649430142
Directory	/workspace/2.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3219374004
Short name	T1032
Test name
Test status
Simulation time	3732361464 ps
CPU time	542.72 seconds
Started	May 23 04:01:02 PM PDT 24
Finished	May 23 04:10:06 PM PDT 24
Peak memory	611188 kb
Host	smart-186b5624-95a1-4830-b60e-abb7518a4c72
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3219374004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.3219374004
Directory	/workspace/0.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.252436163
Short name	T17
Test name
Test status
Simulation time	3678336264 ps
CPU time	524.82 seconds
Started	May 23 03:59:05 PM PDT 24
Finished	May 23 04:07:52 PM PDT 24
Peak memory	601524 kb
Host	smart-3efa7455-151c-421d-b409-7cf9baf5f8c1
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252436 163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.252436163
Directory	/workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3353211170
Short name	T45
Test name
Test status
Simulation time	3981209458 ps
CPU time	345.01 seconds
Started	May 23 04:14:14 PM PDT 24
Finished	May 23 04:20:00 PM PDT 24
Peak memory	611204 kb
Host	smart-cba7d9f8-6eaa-44fa-88b7-67fb33ccda34
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 353211170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3353211170
Directory	/workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.620620641
Short name	T462
Test name
Test status
Simulation time	4627847801 ps
CPU time	567.87 seconds
Started	May 23 04:36:52 PM PDT 24
Finished	May 23 04:46:22 PM PDT 24
Peak memory	572496 kb
Host	smart-63f38c25-3963-4dee-9fea-9cd61eee05e1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620620641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_ with_rand_reset.620620641
Directory	/workspace/75.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.72616821
Short name	T33
Test name
Test status
Simulation time	3207022568 ps
CPU time	295.4 seconds
Started	May 23 04:03:35 PM PDT 24
Finished	May 23 04:08:31 PM PDT 24
Peak memory	601760 kb
Host	smart-309ef376-0f44-4690-9a49-19fc0ed8fcc6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72616821 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.72616821
Directory	/workspace/2.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2559296032
Short name	T5
Test name
Test status
Simulation time	14061635073 ps
CPU time	3396.92 seconds
Started	May 23 04:07:26 PM PDT 24
Finished	May 23 05:04:04 PM PDT 24
Peak memory	601980 kb
Host	smart-31bcb37d-4622-48a3-a20b-7dbfd4fcbbf4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559296032 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2559296032
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

Test location	/workspace/coverage/cover_reg_top/20.chip_tl_errors.3817475537
Short name	T518
Test name
Test status
Simulation time	4138891048 ps
CPU time	478.76 seconds
Started	May 23 04:27:11 PM PDT 24
Finished	May 23 04:35:11 PM PDT 24
Peak memory	594076 kb
Host	smart-e32dd062-68f5-497c-bc4f-b7ecc84d9b80
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817475537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3817475537
Directory	/workspace/20.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3089078995
Short name	T1775
Test name
Test status
Simulation time	29446695548 ps
CPU time	3678.85 seconds
Started	May 23 04:23:37 PM PDT 24
Finished	May 23 05:24:57 PM PDT 24
Peak memory	586392 kb
Host	smart-5ad89514-2117-4cab-89d7-d8d8d5949a57
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089078995 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3089078995
Directory	/workspace/11.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_init.2464338865
Short name	T90
Test name
Test status
Simulation time	26317233390 ps
CPU time	2520.77 seconds
Started	May 23 03:57:31 PM PDT 24
Finished	May 23 04:39:34 PM PDT 24
Peak memory	606764 kb
Host	smart-8e73120b-c584-43b0-b2ec-03e23cad38ee
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464338865 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2464338865
Directory	/workspace/0.chip_sw_flash_init/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.999913731
Short name	T464
Test name
Test status
Simulation time	9910116681 ps
CPU time	665.19 seconds
Started	May 23 04:30:41 PM PDT 24
Finished	May 23 04:41:48 PM PDT 24
Peak memory	573088 kb
Host	smart-ba2782af-8b89-4405-a3bc-f2bbd01398b2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999913731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_ with_rand_reset.999913731
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.chip_jtag_csr_rw.781737101
Short name	T58
Test name
Test status
Simulation time	18076070447 ps
CPU time	1830.39 seconds
Started	May 23 04:06:10 PM PDT 24
Finished	May 23 04:36:42 PM PDT 24
Peak memory	596912 kb
Host	smart-1704a01e-14fc-4092-a329-62c2738d4633
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781737101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_jtag_csr_rw.781737101
Directory	/workspace/2.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_20.107586058
Short name	T299
Test name
Test status
Simulation time	4647899934 ps
CPU time	852.82 seconds
Started	May 23 04:01:51 PM PDT 24
Finished	May 23 04:16:06 PM PDT 24
Peak memory	601812 kb
Host	smart-c8900124-eb00-4b66-955a-9e865417c400
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107586058 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_20.107586058
Directory	/workspace/1.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all.24955066
Short name	T428
Test name
Test status
Simulation time	15769265142 ps
CPU time	590.89 seconds
Started	May 23 04:27:00 PM PDT 24
Finished	May 23 04:36:53 PM PDT 24
Peak memory	573060 kb
Host	smart-768ba4db-bde9-4f89-b556-76f5cf1bd9db
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24955066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.24955066
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_0.1407665699
Short name	T294
Test name
Test status
Simulation time	6258685600 ps
CPU time	1285.68 seconds
Started	May 23 04:15:56 PM PDT 24
Finished	May 23 04:37:24 PM PDT 24
Peak memory	601640 kb
Host	smart-ffa16a86-b22e-4b6a-8e54-36a8133e5d42
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407665699 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.1407665699
Directory	/workspace/2.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3675392687
Short name	T146
Test name
Test status
Simulation time	3906809400 ps
CPU time	590.68 seconds
Started	May 23 03:59:19 PM PDT 24
Finished	May 23 04:09:11 PM PDT 24
Peak memory	604888 kb
Host	smart-5269f702-9cfd-430a-88ed-aa0389ee4a4c
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675392687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3675392687
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3358628330
Short name	T2798
Test name
Test status
Simulation time	4835996180 ps
CPU time	247.42 seconds
Started	May 23 04:40:35 PM PDT 24
Finished	May 23 04:44:43 PM PDT 24
Peak memory	638744 kb
Host	smart-2fbe9718-a6d8-4b26-a244-fb507152311c
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358628330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.3358628330
Directory	/workspace/1.chip_padctrl_attributes/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2327124587
Short name	T430
Test name
Test status
Simulation time	691070598 ps
CPU time	265.86 seconds
Started	May 23 04:31:16 PM PDT 24
Finished	May 23 04:35:43 PM PDT 24
Peak memory	572900 kb
Host	smart-a67e83f9-f9d1-49fd-84b9-009f9586e804
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327124587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.2327124587
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1776492218
Short name	T157
Test name
Test status
Simulation time	5208973450 ps
CPU time	629.82 seconds
Started	May 23 04:17:25 PM PDT 24
Finished	May 23 04:27:56 PM PDT 24
Peak memory	602208 kb
Host	smart-7c7f5db3-447b-484c-bfca-5378630ac944
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17764922 18 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1776492218
Directory	/workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2136503062
Short name	T116
Test name
Test status
Simulation time	76827038228 ps
CPU time	13384.4 seconds
Started	May 23 03:59:04 PM PDT 24
Finished	May 23 07:42:11 PM PDT 24
Peak memory	622420 kb
Host	smart-3e0b0d39-1313-4b7c-81be-4001f0e6c290
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2136503062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.2136503062
Directory	/workspace/0.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.737205451
Short name	T2661
Test name
Test status
Simulation time	17307069072 ps
CPU time	951.16 seconds
Started	May 23 04:27:11 PM PDT 24
Finished	May 23 04:43:04 PM PDT 24
Peak memory	574076 kb
Host	smart-1c12baeb-5c73-44da-b99e-fe90b4ca9679
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737205451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_ with_rand_reset.737205451
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1629697674
Short name	T233
Test name
Test status
Simulation time	8849203025 ps
CPU time	1158.61 seconds
Started	May 23 04:02:44 PM PDT 24
Finished	May 23 04:22:04 PM PDT 24
Peak memory	602908 kb
Host	smart-d8b942e5-5f71-41a2-b6a2-0a4e16d75c37
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629697674 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1629697674
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.150682223
Short name	T138
Test name
Test status
Simulation time	18354977488 ps
CPU time	499.48 seconds
Started	May 23 04:00:52 PM PDT 24
Finished	May 23 04:09:15 PM PDT 24
Peak memory	609076 kb
Host	smart-46a701d4-d09e-492f-a38e-cdbd4599993a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=150682223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.150682223
Directory	/workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3102156468
Short name	T216
Test name
Test status
Simulation time	21102636635 ps
CPU time	1593.79 seconds
Started	May 23 04:01:34 PM PDT 24
Finished	May 23 04:28:10 PM PDT 24
Peak memory	607020 kb
Host	smart-d7c64768-6fec-4dfb-badd-be086204c15c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3102156468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3102156468
Directory	/workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/cover_reg_top/12.chip_tl_errors.3338501214
Short name	T565
Test name
Test status
Simulation time	4499165884 ps
CPU time	490.18 seconds
Started	May 23 04:24:01 PM PDT 24
Finished	May 23 04:32:12 PM PDT 24
Peak memory	602188 kb
Host	smart-5b5e07eb-f692-4ca5-b6f3-28075a74152e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338501214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.3338501214
Directory	/workspace/12.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.344315371
Short name	T155
Test name
Test status
Simulation time	7041460660 ps
CPU time	512.86 seconds
Started	May 23 04:17:33 PM PDT 24
Finished	May 23 04:26:07 PM PDT 24
Peak memory	655984 kb
Host	smart-97cc7e0b-6a85-4bb4-a5f1-1eea6f2402ae
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344315371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_re set.344315371
Directory	/workspace/1.chip_csr_hw_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2349711045
Short name	T277
Test name
Test status
Simulation time	8528006948 ps
CPU time	693.23 seconds
Started	May 23 04:06:15 PM PDT 24
Finished	May 23 04:17:50 PM PDT 24
Peak memory	602424 kb
Host	smart-95493e0a-7bdf-4b68-8a82-71c5bfa74bb7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349711045 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2349711045
Directory	/workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all.2476277547
Short name	T2084
Test name
Test status
Simulation time	3405897192 ps
CPU time	363.11 seconds
Started	May 23 04:20:34 PM PDT 24
Finished	May 23 04:26:38 PM PDT 24
Peak memory	573072 kb
Host	smart-5d1fab2e-d165-41a3-a6c2-9ad025af6dc6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476277547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2476277547
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1531762695
Short name	T295
Test name
Test status
Simulation time	4603023816 ps
CPU time	634.03 seconds
Started	May 23 04:01:38 PM PDT 24
Finished	May 23 04:12:14 PM PDT 24
Peak memory	601640 kb
Host	smart-b2be4246-245b-438a-9ae4-97f9a442b2f4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1531762695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1531762695
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_10.2977574961
Short name	T130
Test name
Test status
Simulation time	3746732542 ps
CPU time	579.76 seconds
Started	May 23 04:03:09 PM PDT 24
Finished	May 23 04:12:51 PM PDT 24
Peak memory	601436 kb
Host	smart-7e770d0c-40e2-4477-ba05-a3738e9488d3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977574961 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.2977574961
Directory	/workspace/1.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_20.3005768110
Short name	T307
Test name
Test status
Simulation time	4350138360 ps
CPU time	662.61 seconds
Started	May 23 04:12:00 PM PDT 24
Finished	May 23 04:23:06 PM PDT 24
Peak memory	601900 kb
Host	smart-a39e112d-873b-4f04-b871-4cdb8b597d12
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005768110 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.3005768110
Directory	/workspace/2.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1487780095
Short name	T457
Test name
Test status
Simulation time	4899241630 ps
CPU time	202.73 seconds
Started	May 23 04:37:36 PM PDT 24
Finished	May 23 04:41:00 PM PDT 24
Peak memory	572392 kb
Host	smart-b8e6e1ec-6ef9-4de3-b33f-17f0f67e4e56
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487780095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.1487780095
Directory	/workspace/79.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/78.chip_sw_all_escalation_resets.120483457
Short name	T113
Test name
Test status
Simulation time	4351789192 ps
CPU time	534.18 seconds
Started	May 23 04:22:31 PM PDT 24
Finished	May 23 04:31:26 PM PDT 24
Peak memory	640088 kb
Host	smart-52bbd3ad-ae8a-4cc5-835d-a83e70f54d0c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 120483457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.120483457
Directory	/workspace/78.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1878644903
Short name	T207
Test name
Test status
Simulation time	7415788312 ps
CPU time	977.74 seconds
Started	May 23 04:02:25 PM PDT 24
Finished	May 23 04:18:44 PM PDT 24
Peak memory	602868 kb
Host	smart-5a50062f-3687-47ec-9133-e3a2d573e040
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187864 4903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.1878644903
Directory	/workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.158295853
Short name	T836
Test name
Test status
Simulation time	582078602 ps
CPU time	333.43 seconds
Started	May 23 04:25:12 PM PDT 24
Finished	May 23 04:30:47 PM PDT 24
Peak memory	572788 kb
Host	smart-8f76b028-23ba-48c4-ac06-685d600a7135
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158295853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_ with_rand_reset.158295853
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1904741298
Short name	T820
Test name
Test status
Simulation time	625010309 ps
CPU time	185.68 seconds
Started	May 23 04:20:57 PM PDT 24
Finished	May 23 04:24:03 PM PDT 24
Peak memory	573016 kb
Host	smart-5ebcd99f-3823-4a60-a089-7eaab01897e1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904741298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.1904741298
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3665775719
Short name	T509
Test name
Test status
Simulation time	708186987 ps
CPU time	248.34 seconds
Started	May 23 04:36:53 PM PDT 24
Finished	May 23 04:41:03 PM PDT 24
Peak memory	572812 kb
Host	smart-22656bba-dbdd-4807-a3c2-7eb53a6d2eb7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665775719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.3665775719
Directory	/workspace/76.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.chip_jtag_mem_access.3584959203
Short name	T227
Test name
Test status
Simulation time	13557167998 ps
CPU time	1477.11 seconds
Started	May 23 03:48:19 PM PDT 24
Finished	May 23 04:12:58 PM PDT 24
Peak memory	604620 kb
Host	smart-bccb0969-4939-4410-8910-f72d5d77b36e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584959203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3 584959203
Directory	/workspace/0.chip_jtag_mem_access/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all.3546558256
Short name	T442
Test name
Test status
Simulation time	8608110251 ps
CPU time	346.91 seconds
Started	May 23 04:39:56 PM PDT 24
Finished	May 23 04:45:45 PM PDT 24
Peak memory	572012 kb
Host	smart-bc35aea3-c40c-4dfd-926e-3d3a2d5fdae6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546558256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.3546558256
Directory	/workspace/95.xbar_stress_all/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1126471566
Short name	T966
Test name
Test status
Simulation time	7360996472 ps
CPU time	1702.41 seconds
Started	May 23 04:02:58 PM PDT 24
Finished	May 23 04:31:22 PM PDT 24
Peak memory	611388 kb
Host	smart-ea2d6c5e-5400-4d91-a2f7-68716ca2c864
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1126471566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1126471566
Directory	/workspace/1.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_sw_gpio.895639054
Short name	T27
Test name
Test status
Simulation time	4036943500 ps
CPU time	448.38 seconds
Started	May 23 04:00:52 PM PDT 24
Finished	May 23 04:08:23 PM PDT 24
Peak memory	601800 kb
Host	smart-443a5d0f-ba1a-4251-bfe8-a0ac4db79ae1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895639054 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.895639054
Directory	/workspace/2.chip_sw_gpio/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2495927119
Short name	T215
Test name
Test status
Simulation time	23208348798 ps
CPU time	2438.82 seconds
Started	May 23 04:00:19 PM PDT 24
Finished	May 23 04:41:00 PM PDT 24
Peak memory	606068 kb
Host	smart-b78dea33-a893-452b-9d21-a27b63192c6a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2495927119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2495927119
Directory	/workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3278216887
Short name	T203
Test name
Test status
Simulation time	19921716318 ps
CPU time	3606.16 seconds
Started	May 23 03:59:33 PM PDT 24
Finished	May 23 04:59:41 PM PDT 24
Peak memory	601940 kb
Host	smart-a4357980-16ff-4d44-aab3-500eed7fb808
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278216887 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.3278216887
Directory	/workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_config_host.639193393
Short name	T22
Test name
Test status
Simulation time	8043947288 ps
CPU time	1890.65 seconds
Started	May 23 04:01:29 PM PDT 24
Finished	May 23 04:33:02 PM PDT 24
Peak memory	601880 kb
Host	smart-cc1d682c-e99a-46d4-a0e4-d151edc06ded
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63919 3393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.639193393
Directory	/workspace/0.chip_sw_usbdev_config_host/latest

Test location	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2172444230
Short name	T652
Test name
Test status
Simulation time	2566907928 ps
CPU time	207.08 seconds
Started	May 23 04:04:40 PM PDT 24
Finished	May 23 04:08:09 PM PDT 24
Peak memory	601444 kb
Host	smart-c492b03d-e0f5-4519-bfdd-07c6866d3c1a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172444230 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.2172444230
Directory	/workspace/0.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all.2534032990
Short name	T500
Test name
Test status
Simulation time	2751113491 ps
CPU time	272.07 seconds
Started	May 23 04:24:45 PM PDT 24
Finished	May 23 04:29:18 PM PDT 24
Peak memory	572872 kb
Host	smart-648151a6-7844-4959-9da7-043f8e4b0e7b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534032990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2534032990
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.400267195
Short name	T2292
Test name
Test status
Simulation time	47645299743 ps
CPU time	816.74 seconds
Started	May 23 04:25:26 PM PDT 24
Finished	May 23 04:39:04 PM PDT 24
Peak memory	572064 kb
Host	smart-0bdd9431-a9ed-4ee7-9e16-8e0d69edfb76
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400267195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.400267195
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.274720297
Short name	T300
Test name
Test status
Simulation time	5780479714 ps
CPU time	1130.2 seconds
Started	May 23 04:02:53 PM PDT 24
Finished	May 23 04:21:44 PM PDT 24
Peak memory	602116 kb
Host	smart-a955b435-794c-4a7c-a1c3-b49f37d079bc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=274720297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.274720297
Directory	/workspace/0.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.744864917
Short name	T288
Test name
Test status
Simulation time	12229308686 ps
CPU time	1767.89 seconds
Started	May 23 04:04:06 PM PDT 24
Finished	May 23 04:33:35 PM PDT 24
Peak memory	603688 kb
Host	smart-90d98b8b-f98f-4617-94c0-7086ad7fed8a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=744864917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.744864917
Directory	/workspace/1.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/2.chip_sw_pattgen_ios.2173078853
Short name	T311
Test name
Test status
Simulation time	3378181248 ps
CPU time	314.65 seconds
Started	May 23 04:00:29 PM PDT 24
Finished	May 23 04:05:45 PM PDT 24
Peak memory	602132 kb
Host	smart-18b0dbcb-270f-4afe-91a3-ef6aa02ef431
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173078853 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2173078853
Directory	/workspace/2.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_10.1240087721
Short name	T128
Test name
Test status
Simulation time	3875079744 ps
CPU time	615.47 seconds
Started	May 23 04:12:48 PM PDT 24
Finished	May 23 04:23:05 PM PDT 24
Peak memory	601416 kb
Host	smart-e16aacc7-7095-4f32-9cf5-8f09173c1296
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240087721 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.1240087721
Directory	/workspace/2.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3244636025
Short name	T823
Test name
Test status
Simulation time	7638877501 ps
CPU time	383.77 seconds
Started	May 23 04:28:04 PM PDT 24
Finished	May 23 04:34:29 PM PDT 24
Peak memory	574108 kb
Host	smart-10078560-cb6f-4146-8dca-906ccdc0848f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244636025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.3244636025
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1887971448
Short name	T798
Test name
Test status
Simulation time	3008274662 ps
CPU time	217.18 seconds
Started	May 23 04:30:02 PM PDT 24
Finished	May 23 04:33:40 PM PDT 24
Peak memory	573092 kb
Host	smart-275fd709-7c3e-4c4e-b0dc-0a5a8f189c4a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887971448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.1887971448
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1286162563
Short name	T1233
Test name
Test status
Simulation time	4147585600 ps
CPU time	453.49 seconds
Started	May 23 04:01:02 PM PDT 24
Finished	May 23 04:08:37 PM PDT 24
Peak memory	637628 kb
Host	smart-4b0e957a-ea98-447d-9e07-5ed23696b75f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286162563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.1286162563
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3576883230
Short name	T766
Test name
Test status
Simulation time	5314017552 ps
CPU time	627.48 seconds
Started	May 23 04:01:35 PM PDT 24
Finished	May 23 04:12:05 PM PDT 24
Peak memory	638564 kb
Host	smart-5315c7f6-2c15-4289-82ce-1ff0e45e3059
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3576883230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3576883230
Directory	/workspace/0.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113966134
Short name	T760
Test name
Test status
Simulation time	3334027928 ps
CPU time	433.34 seconds
Started	May 23 04:08:22 PM PDT 24
Finished	May 23 04:15:36 PM PDT 24
Peak memory	637356 kb
Host	smart-0368fd82-91ae-49fd-adde-0cc23f4518e8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113966134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.2113966134
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/1.chip_sw_all_escalation_resets.47863125
Short name	T750
Test name
Test status
Simulation time	5863265340 ps
CPU time	679.15 seconds
Started	May 23 04:02:27 PM PDT 24
Finished	May 23 04:13:48 PM PDT 24
Peak memory	638572 kb
Host	smart-e30c87b0-6a27-4f0b-adbe-5beeea7dcf3f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 47863125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.47863125
Directory	/workspace/1.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2245390006
Short name	T734
Test name
Test status
Simulation time	5595115552 ps
CPU time	619.09 seconds
Started	May 23 04:20:13 PM PDT 24
Finished	May 23 04:30:34 PM PDT 24
Peak memory	638896 kb
Host	smart-3be42823-7f9c-402c-9c79-aef6524eb91e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2245390006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.2245390006
Directory	/workspace/11.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3074748928
Short name	T718
Test name
Test status
Simulation time	3460652096 ps
CPU time	386.98 seconds
Started	May 23 04:18:13 PM PDT 24
Finished	May 23 04:24:40 PM PDT 24
Peak memory	637300 kb
Host	smart-7e860e07-a926-49f9-aa2c-b247e5eb38e9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074748928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3074748928
Directory	/workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2513965380
Short name	T1163
Test name
Test status
Simulation time	5619863664 ps
CPU time	794.33 seconds
Started	May 23 04:24:11 PM PDT 24
Finished	May 23 04:37:27 PM PDT 24
Peak memory	638572 kb
Host	smart-f2f05d5a-bc93-49ed-9d9c-3266837f5c35
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2513965380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2513965380
Directory	/workspace/12.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.219378043
Short name	T97
Test name
Test status
Simulation time	4343005360 ps
CPU time	366.33 seconds
Started	May 23 04:18:42 PM PDT 24
Finished	May 23 04:24:49 PM PDT 24
Peak memory	637852 kb
Host	smart-cc3c561e-63a5-4699-bc39-6fe40b49cd27
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219378043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_s w_alert_handler_lpg_sleep_mode_alerts.219378043
Directory	/workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/15.chip_sw_all_escalation_resets.686978525
Short name	T670
Test name
Test status
Simulation time	4402719452 ps
CPU time	716.68 seconds
Started	May 23 04:19:58 PM PDT 24
Finished	May 23 04:31:56 PM PDT 24
Peak memory	638624 kb
Host	smart-f891e567-0872-454e-afcb-0eed33caef14
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 686978525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.686978525
Directory	/workspace/15.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200487823
Short name	T727
Test name
Test status
Simulation time	3700535486 ps
CPU time	409.73 seconds
Started	May 23 04:21:25 PM PDT 24
Finished	May 23 04:28:16 PM PDT 24
Peak memory	637556 kb
Host	smart-c0b5cca0-609d-4cc8-b7dd-31bd8ea0199b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200487823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1200487823
Directory	/workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2639546369
Short name	T668
Test name
Test status
Simulation time	5671117684 ps
CPU time	732.04 seconds
Started	May 23 04:18:24 PM PDT 24
Finished	May 23 04:30:37 PM PDT 24
Peak memory	638780 kb
Host	smart-8a6a1100-0636-42aa-82e1-62aa7aabed00
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2639546369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2639546369
Directory	/workspace/16.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3243096540
Short name	T756
Test name
Test status
Simulation time	3344067324 ps
CPU time	530.16 seconds
Started	May 23 04:19:27 PM PDT 24
Finished	May 23 04:28:19 PM PDT 24
Peak memory	636424 kb
Host	smart-883c97c1-c1be-4f7f-a92b-af6822c1cdf4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243096540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3243096540
Directory	/workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/17.chip_sw_all_escalation_resets.640127031
Short name	T733
Test name
Test status
Simulation time	5187383886 ps
CPU time	496.11 seconds
Started	May 23 04:17:43 PM PDT 24
Finished	May 23 04:26:00 PM PDT 24
Peak memory	640024 kb
Host	smart-7431e502-9736-4a09-a6f4-b63dde7f0883
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 640127031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.640127031
Directory	/workspace/17.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2193125086
Short name	T723
Test name
Test status
Simulation time	3534593464 ps
CPU time	467.29 seconds
Started	May 23 04:19:28 PM PDT 24
Finished	May 23 04:27:16 PM PDT 24
Peak memory	637240 kb
Host	smart-3db913ed-40c0-41c7-b9f0-a0dd725ec0c2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193125086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2193125086
Directory	/workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/18.chip_sw_all_escalation_resets.643600518
Short name	T223
Test name
Test status
Simulation time	4556650156 ps
CPU time	643.48 seconds
Started	May 23 04:23:10 PM PDT 24
Finished	May 23 04:33:56 PM PDT 24
Peak memory	639660 kb
Host	smart-37c51a42-0566-490c-8a3f-7939ef4e88a4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 643600518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.643600518
Directory	/workspace/18.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/19.chip_sw_all_escalation_resets.3652336931
Short name	T703
Test name
Test status
Simulation time	5229641800 ps
CPU time	655.17 seconds
Started	May 23 04:20:48 PM PDT 24
Finished	May 23 04:31:44 PM PDT 24
Peak memory	638868 kb
Host	smart-9f2e3c51-ec70-4a8b-b031-923a518ae981
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3652336931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.3652336931
Directory	/workspace/19.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2104958772
Short name	T767
Test name
Test status
Simulation time	4000006776 ps
CPU time	328.15 seconds
Started	May 23 04:06:41 PM PDT 24
Finished	May 23 04:12:10 PM PDT 24
Peak memory	637468 kb
Host	smart-e66e3679-3301-43db-afed-e5e10b0619e7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104958772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.2104958772
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/2.chip_sw_all_escalation_resets.4032250612
Short name	T981
Test name
Test status
Simulation time	3674953380 ps
CPU time	369.15 seconds
Started	May 23 03:59:32 PM PDT 24
Finished	May 23 04:05:42 PM PDT 24
Peak memory	638852 kb
Host	smart-8a43b1f4-93e9-4796-8419-f3c15e45c23d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4032250612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.4032250612
Directory	/workspace/2.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.720614246
Short name	T1055
Test name
Test status
Simulation time	3616289232 ps
CPU time	407.15 seconds
Started	May 23 04:18:46 PM PDT 24
Finished	May 23 04:25:34 PM PDT 24
Peak memory	636448 kb
Host	smart-e8062310-13b2-40e6-b19c-5d2e478b6a7f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720614246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_s w_alert_handler_lpg_sleep_mode_alerts.720614246
Directory	/workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2317279962
Short name	T1241
Test name
Test status
Simulation time	4002132712 ps
CPU time	385.02 seconds
Started	May 23 04:19:43 PM PDT 24
Finished	May 23 04:26:09 PM PDT 24
Peak memory	637560 kb
Host	smart-6e93f377-eb31-4618-ad75-c00405b954b1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317279962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2317279962
Directory	/workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/22.chip_sw_all_escalation_resets.4245349686
Short name	T698
Test name
Test status
Simulation time	5994554680 ps
CPU time	719.58 seconds
Started	May 23 04:19:25 PM PDT 24
Finished	May 23 04:31:25 PM PDT 24
Peak memory	638684 kb
Host	smart-f1e83fff-8ba8-485c-bf77-145603543435
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4245349686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.4245349686
Directory	/workspace/22.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/24.chip_sw_all_escalation_resets.749805605
Short name	T221
Test name
Test status
Simulation time	6397442960 ps
CPU time	618.84 seconds
Started	May 23 04:20:01 PM PDT 24
Finished	May 23 04:30:21 PM PDT 24
Peak memory	638832 kb
Host	smart-b00e13d6-12ac-427e-8d20-cea4848dc58a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 749805605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.749805605
Directory	/workspace/24.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3165736955
Short name	T755
Test name
Test status
Simulation time	4697709564 ps
CPU time	635.61 seconds
Started	May 23 04:19:54 PM PDT 24
Finished	May 23 04:30:32 PM PDT 24
Peak memory	638672 kb
Host	smart-3b53290b-80dc-4c3d-831e-4477ceb18de8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3165736955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3165736955
Directory	/workspace/26.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2219590571
Short name	T712
Test name
Test status
Simulation time	3540236710 ps
CPU time	338.87 seconds
Started	May 23 04:20:35 PM PDT 24
Finished	May 23 04:26:15 PM PDT 24
Peak memory	637640 kb
Host	smart-d5b3e830-59b7-43f5-a5e6-191b71477fdb
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219590571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2219590571
Directory	/workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1811897850
Short name	T680
Test name
Test status
Simulation time	3955433288 ps
CPU time	481.41 seconds
Started	May 23 04:21:22 PM PDT 24
Finished	May 23 04:29:24 PM PDT 24
Peak memory	637156 kb
Host	smart-468a3bfc-3871-43cb-a8ab-958f97d87e57
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811897850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1811897850
Directory	/workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/29.chip_sw_all_escalation_resets.762506747
Short name	T388
Test name
Test status
Simulation time	4258428820 ps
CPU time	675.28 seconds
Started	May 23 04:21:10 PM PDT 24
Finished	May 23 04:32:27 PM PDT 24
Peak memory	638276 kb
Host	smart-8fbc123b-4ee4-4891-af8f-da2299ed0f42
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 762506747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.762506747
Directory	/workspace/29.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3065453946
Short name	T255
Test name
Test status
Simulation time	3640058412 ps
CPU time	406.89 seconds
Started	May 23 04:16:15 PM PDT 24
Finished	May 23 04:23:03 PM PDT 24
Peak memory	637648 kb
Host	smart-b59d7237-fa24-414b-ba3f-9a10b79d9807
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065453946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.3065453946
Directory	/workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/3.chip_sw_all_escalation_resets.142697273
Short name	T107
Test name
Test status
Simulation time	5964173024 ps
CPU time	727.85 seconds
Started	May 23 04:18:16 PM PDT 24
Finished	May 23 04:30:25 PM PDT 24
Peak memory	640428 kb
Host	smart-48b2b30a-7dc2-430a-9604-5b3883b04ca2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 142697273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.142697273
Directory	/workspace/3.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016091343
Short name	T744
Test name
Test status
Simulation time	3401283828 ps
CPU time	479.42 seconds
Started	May 23 04:18:40 PM PDT 24
Finished	May 23 04:26:41 PM PDT 24
Peak memory	637536 kb
Host	smart-c9720e91-522c-4c47-8cbc-b47e04ebcb24
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016091343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3016091343
Directory	/workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3264778844
Short name	T731
Test name
Test status
Simulation time	4300198072 ps
CPU time	422.26 seconds
Started	May 23 04:21:47 PM PDT 24
Finished	May 23 04:28:51 PM PDT 24
Peak memory	637852 kb
Host	smart-6240835f-985c-4eb1-b818-34a1eb2d0b46
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264778844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3264778844
Directory	/workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/32.chip_sw_all_escalation_resets.799567800
Short name	T316
Test name
Test status
Simulation time	6089663384 ps
CPU time	662.13 seconds
Started	May 23 04:20:58 PM PDT 24
Finished	May 23 04:32:00 PM PDT 24
Peak memory	638676 kb
Host	smart-46ac11c0-c0c7-4dab-80be-a0ee0d654a58
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 799567800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.799567800
Directory	/workspace/32.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/33.chip_sw_all_escalation_resets.3748596610
Short name	T722
Test name
Test status
Simulation time	5618211800 ps
CPU time	682.99 seconds
Started	May 23 04:20:31 PM PDT 24
Finished	May 23 04:31:55 PM PDT 24
Peak memory	638528 kb
Host	smart-e49604aa-8f73-42bb-b4e9-496a9b51847d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3748596610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.3748596610
Directory	/workspace/33.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2478845709
Short name	T365
Test name
Test status
Simulation time	4361301624 ps
CPU time	448.22 seconds
Started	May 23 04:24:41 PM PDT 24
Finished	May 23 04:32:11 PM PDT 24
Peak memory	636868 kb
Host	smart-dafac091-a4e0-4017-a7bf-387e6e5d438e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478845709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2478845709
Directory	/workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/34.chip_sw_all_escalation_resets.4254126550
Short name	T705
Test name
Test status
Simulation time	5264110490 ps
CPU time	643.57 seconds
Started	May 23 04:22:10 PM PDT 24
Finished	May 23 04:32:54 PM PDT 24
Peak memory	639124 kb
Host	smart-f99d1dc8-7194-4302-9404-c431900051ef
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4254126550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.4254126550
Directory	/workspace/34.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.131105338
Short name	T671
Test name
Test status
Simulation time	3613275116 ps
CPU time	413.85 seconds
Started	May 23 04:25:03 PM PDT 24
Finished	May 23 04:31:58 PM PDT 24
Peak memory	637492 kb
Host	smart-e65abaf9-f1be-485c-80c4-38969e5017a2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131105338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_s w_alert_handler_lpg_sleep_mode_alerts.131105338
Directory	/workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2048511566
Short name	T743
Test name
Test status
Simulation time	3201865312 ps
CPU time	466.21 seconds
Started	May 23 04:22:40 PM PDT 24
Finished	May 23 04:30:27 PM PDT 24
Peak memory	637420 kb
Host	smart-b7451f69-3f3b-47df-a58b-6383610842e8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048511566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.2048511566
Directory	/workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/4.chip_sw_all_escalation_resets.743227342
Short name	T674
Test name
Test status
Simulation time	6380675030 ps
CPU time	785.82 seconds
Started	May 23 04:17:10 PM PDT 24
Finished	May 23 04:30:17 PM PDT 24
Peak memory	639620 kb
Host	smart-47c2ae5f-bd4c-46b7-8277-055e3d4ee8ad
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 743227342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.743227342
Directory	/workspace/4.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1543005885
Short name	T282
Test name
Test status
Simulation time	3612818696 ps
CPU time	315.55 seconds
Started	May 23 04:18:38 PM PDT 24
Finished	May 23 04:23:54 PM PDT 24
Peak memory	637172 kb
Host	smart-0357fdf0-c5df-43d9-9a0e-fa1eb4a26c33
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543005885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1543005885
Directory	/workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2043788141
Short name	T763
Test name
Test status
Simulation time	4058541648 ps
CPU time	441.9 seconds
Started	May 23 04:22:57 PM PDT 24
Finished	May 23 04:30:20 PM PDT 24
Peak memory	637472 kb
Host	smart-476e76ff-c0d5-4504-a83f-0ce7ac543117
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043788141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2043788141
Directory	/workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3121923348
Short name	T697
Test name
Test status
Simulation time	3819707968 ps
CPU time	477.34 seconds
Started	May 23 04:22:13 PM PDT 24
Finished	May 23 04:30:12 PM PDT 24
Peak memory	636416 kb
Host	smart-87ded758-dbe8-4c55-a503-97a63f089f1d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121923348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3121923348
Directory	/workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.799422278
Short name	T739
Test name
Test status
Simulation time	3658943404 ps
CPU time	417.02 seconds
Started	May 23 04:20:55 PM PDT 24
Finished	May 23 04:27:52 PM PDT 24
Peak memory	637596 kb
Host	smart-63edcfa2-d394-4755-b5d8-d6135b659624
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799422278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_s w_alert_handler_lpg_sleep_mode_alerts.799422278
Directory	/workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/45.chip_sw_all_escalation_resets.4044839943
Short name	T379
Test name
Test status
Simulation time	5031754104 ps
CPU time	682.03 seconds
Started	May 23 04:21:56 PM PDT 24
Finished	May 23 04:33:19 PM PDT 24
Peak memory	638792 kb
Host	smart-fbc63f4c-f8ba-4661-9098-0f50ed96941b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4044839943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.4044839943
Directory	/workspace/45.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3228772512
Short name	T707
Test name
Test status
Simulation time	3480471200 ps
CPU time	341.72 seconds
Started	May 23 04:25:03 PM PDT 24
Finished	May 23 04:30:46 PM PDT 24
Peak memory	637476 kb
Host	smart-dfd4a608-7ded-463a-8e71-2f5f3e879470
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228772512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3228772512
Directory	/workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1674114023
Short name	T172
Test name
Test status
Simulation time	4858890316 ps
CPU time	495.71 seconds
Started	May 23 04:21:48 PM PDT 24
Finished	May 23 04:30:04 PM PDT 24
Peak memory	639496 kb
Host	smart-258135f2-3746-4ef0-b756-90b78cbea0a7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1674114023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.1674114023
Directory	/workspace/46.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.965878095
Short name	T714
Test name
Test status
Simulation time	3849859624 ps
CPU time	452.78 seconds
Started	May 23 04:20:06 PM PDT 24
Finished	May 23 04:27:40 PM PDT 24
Peak memory	637708 kb
Host	smart-7f919ff9-6fa6-4a82-8d6b-6fb81dc38b1e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965878095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_s w_alert_handler_lpg_sleep_mode_alerts.965878095
Directory	/workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.360877601
Short name	T259
Test name
Test status
Simulation time	4101465592 ps
CPU time	463.67 seconds
Started	May 23 04:17:25 PM PDT 24
Finished	May 23 04:25:10 PM PDT 24
Peak memory	637372 kb
Host	smart-6947207f-3f34-4aaf-b325-944ec98d3970
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360877601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.360877601
Directory	/workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3216744129
Short name	T685
Test name
Test status
Simulation time	3446182510 ps
CPU time	328.07 seconds
Started	May 23 04:22:25 PM PDT 24
Finished	May 23 04:27:54 PM PDT 24
Peak memory	637424 kb
Host	smart-0392cb9a-abca-4761-80e0-74cf3a247d37
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216744129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3216744129
Directory	/workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/54.chip_sw_all_escalation_resets.2747442509
Short name	T324
Test name
Test status
Simulation time	5714042650 ps
CPU time	671.4 seconds
Started	May 23 04:21:23 PM PDT 24
Finished	May 23 04:32:35 PM PDT 24
Peak memory	639464 kb
Host	smart-641eb307-52ef-4731-846b-ab663c87f5c1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2747442509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2747442509
Directory	/workspace/54.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/55.chip_sw_all_escalation_resets.70506814
Short name	T679
Test name
Test status
Simulation time	5650203824 ps
CPU time	598.45 seconds
Started	May 23 04:21:44 PM PDT 24
Finished	May 23 04:31:44 PM PDT 24
Peak memory	638912 kb
Host	smart-7248b0ca-750f-4e1f-849e-0a63b2f19558
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 70506814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.70506814
Directory	/workspace/55.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/56.chip_sw_all_escalation_resets.2410091318
Short name	T736
Test name
Test status
Simulation time	5138442822 ps
CPU time	749.22 seconds
Started	May 23 04:22:35 PM PDT 24
Finished	May 23 04:35:06 PM PDT 24
Peak memory	639740 kb
Host	smart-8d40e36c-8d79-48a4-85ef-91be49713e77
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2410091318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2410091318
Directory	/workspace/56.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/6.chip_sw_all_escalation_resets.1706398501
Short name	T681
Test name
Test status
Simulation time	4941236852 ps
CPU time	628.86 seconds
Started	May 23 04:17:01 PM PDT 24
Finished	May 23 04:27:31 PM PDT 24
Peak memory	638552 kb
Host	smart-3f26e89d-aaf5-4b38-b9e6-b5227f985723
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1706398501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1706398501
Directory	/workspace/6.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/60.chip_sw_all_escalation_resets.799456800
Short name	T687
Test name
Test status
Simulation time	4900667166 ps
CPU time	553.18 seconds
Started	May 23 04:24:38 PM PDT 24
Finished	May 23 04:33:53 PM PDT 24
Peak memory	639604 kb
Host	smart-8a654a49-d9a7-4bf7-b2d1-8b93e375b4c0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 799456800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.799456800
Directory	/workspace/60.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/63.chip_sw_all_escalation_resets.3325321178
Short name	T240
Test name
Test status
Simulation time	5850753816 ps
CPU time	577.18 seconds
Started	May 23 04:21:08 PM PDT 24
Finished	May 23 04:30:46 PM PDT 24
Peak memory	638640 kb
Host	smart-a808c81e-0714-42e0-b839-2362b24e537b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3325321178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.3325321178
Directory	/workspace/63.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1839004318
Short name	T677
Test name
Test status
Simulation time	3840919512 ps
CPU time	485.26 seconds
Started	May 23 04:21:10 PM PDT 24
Finished	May 23 04:29:17 PM PDT 24
Peak memory	637528 kb
Host	smart-f857bcfd-bcf7-4cbe-83c6-2e1d1b11ee72
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839004318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1839004318
Directory	/workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/66.chip_sw_all_escalation_resets.1159343040
Short name	T335
Test name
Test status
Simulation time	5299940664 ps
CPU time	734.07 seconds
Started	May 23 04:22:33 PM PDT 24
Finished	May 23 04:34:48 PM PDT 24
Peak memory	638584 kb
Host	smart-c09393e5-1a55-47f2-b0e3-177175405505
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1159343040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.1159343040
Directory	/workspace/66.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/7.chip_sw_all_escalation_resets.32999886
Short name	T266
Test name
Test status
Simulation time	6453691220 ps
CPU time	860.36 seconds
Started	May 23 04:17:27 PM PDT 24
Finished	May 23 04:31:48 PM PDT 24
Peak memory	639620 kb
Host	smart-559561d7-14ec-4913-8023-c26cc9ab248a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 32999886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.32999886
Directory	/workspace/7.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/70.chip_sw_all_escalation_resets.3509906873
Short name	T738
Test name
Test status
Simulation time	5675372590 ps
CPU time	727.35 seconds
Started	May 23 04:25:20 PM PDT 24
Finished	May 23 04:37:29 PM PDT 24
Peak memory	638736 kb
Host	smart-0f41f458-18e4-46b3-9368-aa63405f81c9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3509906873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.3509906873
Directory	/workspace/70.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/74.chip_sw_all_escalation_resets.1302848154
Short name	T242
Test name
Test status
Simulation time	5536402522 ps
CPU time	780.65 seconds
Started	May 23 04:24:48 PM PDT 24
Finished	May 23 04:37:51 PM PDT 24
Peak memory	638948 kb
Host	smart-bb51cb29-3908-42d0-9226-327e5eae7ff9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1302848154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1302848154
Directory	/workspace/74.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/75.chip_sw_all_escalation_resets.861500641
Short name	T745
Test name
Test status
Simulation time	4420464600 ps
CPU time	760.71 seconds
Started	May 23 04:21:43 PM PDT 24
Finished	May 23 04:34:26 PM PDT 24
Peak memory	638792 kb
Host	smart-8aed59e3-2918-4da3-bc06-d8a7a321a1b6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 861500641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.861500641
Directory	/workspace/75.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2220976048
Short name	T709
Test name
Test status
Simulation time	3229374620 ps
CPU time	392.95 seconds
Started	May 23 04:17:27 PM PDT 24
Finished	May 23 04:24:01 PM PDT 24
Peak memory	636796 kb
Host	smart-41437588-9c94-49f2-8926-4fd22c839f2e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220976048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.2220976048
Directory	/workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.61819090
Short name	T757
Test name
Test status
Simulation time	3629124080 ps
CPU time	367.54 seconds
Started	May 23 04:23:18 PM PDT 24
Finished	May 23 04:29:27 PM PDT 24
Peak memory	637336 kb
Host	smart-45decef9-9d23-4132-b05d-88b15060f21c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61819090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw _alert_handler_lpg_sleep_mode_alerts.61819090
Directory	/workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1491359011
Short name	T397
Test name
Test status
Simulation time	4823979668 ps
CPU time	613.84 seconds
Started	May 23 04:24:21 PM PDT 24
Finished	May 23 04:34:36 PM PDT 24
Peak memory	639880 kb
Host	smart-81d81779-eab8-4372-9d6f-b6148ef94643
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1491359011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1491359011
Directory	/workspace/82.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.956148464
Short name	T710
Test name
Test status
Simulation time	3664885160 ps
CPU time	304.54 seconds
Started	May 23 04:22:27 PM PDT 24
Finished	May 23 04:27:33 PM PDT 24
Peak memory	637444 kb
Host	smart-38f676ae-7b16-412d-ab0b-c16f071f015e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956148464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_s w_alert_handler_lpg_sleep_mode_alerts.956148464
Directory	/workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/83.chip_sw_all_escalation_resets.591480204
Short name	T726
Test name
Test status
Simulation time	4550754568 ps
CPU time	531.55 seconds
Started	May 23 04:21:54 PM PDT 24
Finished	May 23 04:30:46 PM PDT 24
Peak memory	638756 kb
Host	smart-c4722113-5807-4b3d-af17-41c90adde58c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 591480204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.591480204
Directory	/workspace/83.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1184461018
Short name	T746
Test name
Test status
Simulation time	3055506094 ps
CPU time	402.12 seconds
Started	May 23 04:20:14 PM PDT 24
Finished	May 23 04:26:58 PM PDT 24
Peak memory	637488 kb
Host	smart-4b4c4e4e-5f47-48dc-8278-0316f919d67b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184461018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.1184461018
Directory	/workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2142985657
Short name	T748
Test name
Test status
Simulation time	5963441440 ps
CPU time	682.46 seconds
Started	May 23 04:22:01 PM PDT 24
Finished	May 23 04:33:25 PM PDT 24
Peak memory	639112 kb
Host	smart-6aceee7c-103d-45ae-a2b0-aaac0e389ee6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2142985657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2142985657
Directory	/workspace/92.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3187963353
Short name	T77
Test name
Test status
Simulation time	5165412010 ps
CPU time	720.7 seconds
Started	May 23 04:22:07 PM PDT 24
Finished	May 23 04:34:08 PM PDT 24
Peak memory	639948 kb
Host	smart-080d0819-2189-4f72-bed4-7a4ce9265b3b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3187963353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.3187963353
Directory	/workspace/95.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2949820789
Short name	T351
Test name
Test status
Simulation time	80692675340 ps
CPU time	10585.8 seconds
Started	May 23 04:15:21 PM PDT 24
Finished	May 23 07:11:49 PM PDT 24
Peak memory	638464 kb
Host	smart-8af76666-2357-45d4-90de-f89bdf8a4969
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949820789 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.2949820789
Directory	/workspace/0.chip_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/15.chip_tl_errors.3147071241
Short name	T531
Test name
Test status
Simulation time	3894920510 ps
CPU time	413.11 seconds
Started	May 23 04:25:12 PM PDT 24
Finished	May 23 04:32:06 PM PDT 24
Peak memory	595128 kb
Host	smart-dcda0cb6-389a-4501-b65d-3cde2f05e25e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147071241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3147071241
Directory	/workspace/15.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_random_large_delays.1405094026
Short name	T473
Test name
Test status
Simulation time	116106491259 ps
CPU time	1273.96 seconds
Started	May 23 04:31:32 PM PDT 24
Finished	May 23 04:52:47 PM PDT 24
Peak memory	572000 kb
Host	smart-9e352600-6ac4-4971-8258-bd32de3b11ee
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405094026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1405094026
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.178249715
Short name	T306
Test name
Test status
Simulation time	4877291254 ps
CPU time	844.39 seconds
Started	May 23 04:00:34 PM PDT 24
Finished	May 23 04:14:41 PM PDT 24
Peak memory	602104 kb
Host	smart-41eec34d-2ac0-485c-8ced-9df9e1d324d7
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178249715 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.178249715
Directory	/workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3998818767
Short name	T162
Test name
Test status
Simulation time	6025002568 ps
CPU time	468.12 seconds
Started	May 23 04:04:55 PM PDT 24
Finished	May 23 04:12:46 PM PDT 24
Peak memory	602584 kb
Host	smart-9781cd1e-53a0-4c58-b9a0-0ccf0559c241
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3998818767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3998818767
Directory	/workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1932340268
Short name	T360
Test name
Test status
Simulation time	5153399400 ps
CPU time	878.58 seconds
Started	May 23 04:00:58 PM PDT 24
Finished	May 23 04:15:39 PM PDT 24
Peak memory	601832 kb
Host	smart-23ec208d-1ed8-473c-8b96-a5203feded8f
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932340268 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1932340268
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.925504286
Short name	T139
Test name
Test status
Simulation time	19103130562 ps
CPU time	2551.36 seconds
Started	May 23 04:14:49 PM PDT 24
Finished	May 23 04:57:22 PM PDT 24
Peak memory	603408 kb
Host	smart-25ff7c8d-a052-4c73-99cf-b55ca4b603de
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925504286 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.925504286
Directory	/workspace/2.chip_sw_ast_clk_rst_inputs/latest

Test location	/workspace/coverage/default/52.chip_sw_all_escalation_resets.2278953722
Short name	T363
Test name
Test status
Simulation time	5258641272 ps
CPU time	609.28 seconds
Started	May 23 04:21:17 PM PDT 24
Finished	May 23 04:31:27 PM PDT 24
Peak memory	603580 kb
Host	smart-24a712ae-7902-4f23-b895-20c2d02ddfb2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2278953722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.2278953722
Directory	/workspace/52.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3746095958
Short name	T148
Test name
Test status
Simulation time	6531500903 ps
CPU time	366.65 seconds
Started	May 23 03:59:49 PM PDT 24
Finished	May 23 04:05:57 PM PDT 24
Peak memory	602460 kb
Host	smart-b5077283-5baa-4763-bfb5-c21a382b9840
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746095958 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3746095958
Directory	/workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc.502059223
Short name	T1034
Test name
Test status
Simulation time	2361479136 ps
CPU time	286.27 seconds
Started	May 23 04:04:38 PM PDT 24
Finished	May 23 04:09:26 PM PDT 24
Peak memory	601536 kb
Host	smart-a6491ce1-0551-4d7d-b1b8-4f56323f3c60
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502059223 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.502059223
Directory	/workspace/0.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1227762901
Short name	T638
Test name
Test status
Simulation time	4351606733 ps
CPU time	537.38 seconds
Started	May 23 04:07:04 PM PDT 24
Finished	May 23 04:16:02 PM PDT 24
Peak memory	610184 kb
Host	smart-3323110d-bfb8-4aa1-8bd3-34b8b1ef076d
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227762901 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.1227762901
Directory	/workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_dev.2571417543
Short name	T92
Test name
Test status
Simulation time	15143661515 ps
CPU time	1686.18 seconds
Started	May 23 04:16:43 PM PDT 24
Finished	May 23 04:44:50 PM PDT 24
Peak memory	613612 kb
Host	smart-7d54b859-91c5-4ee3-bd3b-3f5f459d8812
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2571417543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.2571417543
Directory	/workspace/3.chip_tap_straps_dev/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4285304194
Short name	T372
Test name
Test status
Simulation time	74786054284 ps
CPU time	9872.48 seconds
Started	May 23 04:16:47 PM PDT 24
Finished	May 23 07:01:22 PM PDT 24
Peak memory	635260 kb
Host	smart-d6470ac4-a670-41eb-ab4d-59d024ed35b0
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285304194 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.4285304194
Directory	/workspace/1.chip_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all.3358473309
Short name	T1509
Test name
Test status
Simulation time	1161348233 ps
CPU time	115.84 seconds
Started	May 23 04:24:25 PM PDT 24
Finished	May 23 04:26:22 PM PDT 24
Peak memory	571900 kb
Host	smart-ff544b3d-5781-4d98-8124-5f92bf3abbf1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358473309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3358473309
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all.3722678119
Short name	T1926
Test name
Test status
Simulation time	909143987 ps
CPU time	80.32 seconds
Started	May 23 04:25:12 PM PDT 24
Finished	May 23 04:26:33 PM PDT 24
Peak memory	571868 kb
Host	smart-e63cefab-b4e3-415e-9705-9955f811c4d9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722678119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3722678119
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1550133640
Short name	T1854
Test name
Test status
Simulation time	548141414 ps
CPU time	51.92 seconds
Started	May 23 04:25:36 PM PDT 24
Finished	May 23 04:26:30 PM PDT 24
Peak memory	571716 kb
Host	smart-01f7b7a0-d5e7-4468-be81-385423589868
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550133640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.1550133640
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/29.chip_tl_errors.1298925275
Short name	T635
Test name
Test status
Simulation time	4618538530 ps
CPU time	556.93 seconds
Started	May 23 04:29:16 PM PDT 24
Finished	May 23 04:38:34 PM PDT 24
Peak memory	593992 kb
Host	smart-9b0c1bcf-0ccc-41ad-896b-f1f84b381b2d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298925275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1298925275
Directory	/workspace/29.chip_tl_errors/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.576074585
Short name	T296
Test name
Test status
Simulation time	4618650107 ps
CPU time	742.53 seconds
Started	May 23 04:04:03 PM PDT 24
Finished	May 23 04:16:26 PM PDT 24
Peak memory	601584 kb
Host	smart-f560eaf7-034b-4c7a-90bb-5d633b47d94f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=576074585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.576074585
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.85636251
Short name	T309
Test name
Test status
Simulation time	5642340520 ps
CPU time	817.68 seconds
Started	May 23 03:59:27 PM PDT 24
Finished	May 23 04:13:06 PM PDT 24
Peak memory	602068 kb
Host	smart-390fb750-3ede-4959-a41f-009fe4d4e233
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85636251 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.85636251
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1592184591
Short name	T158
Test name
Test status
Simulation time	3976091127 ps
CPU time	258.7 seconds
Started	May 23 04:19:33 PM PDT 24
Finished	May 23 04:23:53 PM PDT 24
Peak memory	655836 kb
Host	smart-8863019d-51bc-44f8-9340-06048050ed46
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592184591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.1592184591
Directory	/workspace/3.chip_csr_hw_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3357561356
Short name	T178
Test name
Test status
Simulation time	6700023712 ps
CPU time	1422.04 seconds
Started	May 23 04:00:43 PM PDT 24
Finished	May 23 04:24:27 PM PDT 24
Peak memory	602684 kb
Host	smart-1df90a30-8f2b-4389-bf2d-3f6651408e7a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3357561356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.3357561356
Directory	/workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3836928450
Short name	T624
Test name
Test status
Simulation time	24139217307 ps
CPU time	3723.65 seconds
Started	May 23 04:05:04 PM PDT 24
Finished	May 23 05:07:08 PM PDT 24
Peak memory	602036 kb
Host	smart-dbd39be5-1bb9-4221-9b9f-0c094b9d7f10
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836928450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3836928450
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.420202962
Short name	T956
Test name
Test status
Simulation time	5119423966 ps
CPU time	393.5 seconds
Started	May 23 04:00:00 PM PDT 24
Finished	May 23 04:06:37 PM PDT 24
Peak memory	608868 kb
Host	smart-37cbbe0c-208a-4cc0-a60b-e8ca0f022bbc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=420202962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.420202962
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2336058933
Short name	T217
Test name
Test status
Simulation time	19163981816 ps
CPU time	2052.56 seconds
Started	May 23 04:15:29 PM PDT 24
Finished	May 23 04:49:43 PM PDT 24
Peak memory	606080 kb
Host	smart-b2abce06-f4d5-46a9-919a-82a9093ddfab
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2336058933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2336058933
Directory	/workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2593209638
Short name	T1301
Test name
Test status
Simulation time	2124201056 ps
CPU time	187.69 seconds
Started	May 23 04:23:35 PM PDT 24
Finished	May 23 04:26:44 PM PDT 24
Peak memory	571940 kb
Host	smart-6800419f-5ed1-4245-ac78-e02fb191968a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593209638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2593209638
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/28.chip_tl_errors.322171505
Short name	T633
Test name
Test status
Simulation time	2937178856 ps
CPU time	188.35 seconds
Started	May 23 04:29:01 PM PDT 24
Finished	May 23 04:32:12 PM PDT 24
Peak memory	594068 kb
Host	smart-34e37f46-ca11-45ad-8131-b3acaa5d4f65
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322171505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.322171505
Directory	/workspace/28.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.561243545
Short name	T601
Test name
Test status
Simulation time	5164360354 ps
CPU time	221.7 seconds
Started	May 23 04:29:58 PM PDT 24
Finished	May 23 04:33:41 PM PDT 24
Peak memory	571980 kb
Host	smart-0e1788d6-3e81-4377-b5cc-e19b313a7ffd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561243545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.561243545
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2403925639
Short name	T646
Test name
Test status
Simulation time	18701502703 ps
CPU time	713.94 seconds
Started	May 23 04:32:54 PM PDT 24
Finished	May 23 04:44:49 PM PDT 24
Peak memory	573140 kb
Host	smart-cfcdee87-f6f4-47c2-9fed-d9297b9456a6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403925639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2403925639
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.3250033244
Short name	T647
Test name
Test status
Simulation time	1074597421 ps
CPU time	89.07 seconds
Started	May 23 04:34:19 PM PDT 24
Finished	May 23 04:35:49 PM PDT 24
Peak memory	571916 kb
Host	smart-07e624ee-dcb9-4821-a8d7-af4e71080aed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250033244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.3250033244
Directory	/workspace/60.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3904156562
Short name	T595
Test name
Test status
Simulation time	7600038059 ps
CPU time	758.62 seconds
Started	May 23 04:38:10 PM PDT 24
Finished	May 23 04:50:50 PM PDT 24
Peak memory	573060 kb
Host	smart-fbcfdd02-6a5d-48fe-a4d3-588c7863d218
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904156562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.3904156562
Directory	/workspace/83.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.466248332
Short name	T605
Test name
Test status
Simulation time	2254569484 ps
CPU time	232.46 seconds
Started	May 23 04:38:51 PM PDT 24
Finished	May 23 04:42:45 PM PDT 24
Peak memory	573148 kb
Host	smart-4b610bcb-0b3c-4863-9588-fc5d5c79c410
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466248332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.466248332
Directory	/workspace/89.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.4209095497
Short name	T648
Test name
Test status
Simulation time	691665319 ps
CPU time	30.4 seconds
Started	May 23 04:39:22 PM PDT 24
Finished	May 23 04:39:56 PM PDT 24
Peak memory	571792 kb
Host	smart-09ffd822-a85d-4d62-94f0-6500012994e9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209095497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.4209095497
Directory	/workspace/92.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/default/0.chip_sw_gpio.3055459656
Short name	T28
Test name
Test status
Simulation time	4150470092 ps
CPU time	541.8 seconds
Started	May 23 04:03:32 PM PDT 24
Finished	May 23 04:12:36 PM PDT 24
Peak memory	601620 kb
Host	smart-38f34f6c-7faa-41c0-ace6-c4dd4ecaff45
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055459656 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.3055459656
Directory	/workspace/0.chip_sw_gpio/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2629165411
Short name	T663
Test name
Test status
Simulation time	4673969920 ps
CPU time	903.17 seconds
Started	May 23 04:00:58 PM PDT 24
Finished	May 23 04:16:04 PM PDT 24
Peak memory	601864 kb
Host	smart-208cb83d-2480-408b-b106-0c634ea4ae4e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26291 65411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.2629165411
Directory	/workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_tpm.582223278
Short name	T2
Test name
Test status
Simulation time	3663603574 ps
CPU time	366.03 seconds
Started	May 23 04:01:54 PM PDT 24
Finished	May 23 04:08:01 PM PDT 24
Peak memory	610360 kb
Host	smart-beaa1237-3e97-463c-b049-bde1c0ce9390
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582223278 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.582223278
Directory	/workspace/0.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_irq.517931584
Short name	T327
Test name
Test status
Simulation time	4280163518 ps
CPU time	515.26 seconds
Started	May 23 04:03:39 PM PDT 24
Finished	May 23 04:12:15 PM PDT 24
Peak memory	601516 kb
Host	smart-ffd7e976-8603-4bbe-87c4-7f64b3987360
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517931584 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.517931584
Directory	/workspace/1.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2317051093
Short name	T355
Test name
Test status
Simulation time	1804766926 ps
CPU time	118.78 seconds
Started	May 23 04:02:58 PM PDT 24
Finished	May 23 04:04:58 PM PDT 24
Peak memory	633496 kb
Host	smart-28b3ad54-e382-4f2c-9542-84a5c7c5dbeb
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317051093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.2317051093
Directory	/workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_auto_mode.362864892
Short name	T625
Test name
Test status
Simulation time	5474688700 ps
CPU time	1409.34 seconds
Started	May 23 04:06:10 PM PDT 24
Finished	May 23 04:29:42 PM PDT 24
Peak memory	602052 kb
Host	smart-dfd00f05-e1e0-407e-95d4-cfe7016cc7cf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362864892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a uto_mode.362864892
Directory	/workspace/0.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1467788552
Short name	T413
Test name
Test status
Simulation time	3087697800 ps
CPU time	571.83 seconds
Started	May 23 04:02:45 PM PDT 24
Finished	May 23 04:12:19 PM PDT 24
Peak memory	601728 kb
Host	smart-1857a774-72c8-4c03-a736-ed4c4f670bbd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467788552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.1467788552
Directory	/workspace/0.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3548002757
Short name	T1009
Test name
Test status
Simulation time	6439502164 ps
CPU time	927.06 seconds
Started	May 23 04:04:45 PM PDT 24
Finished	May 23 04:20:13 PM PDT 24
Peak memory	602324 kb
Host	smart-3b460a61-5785-4d01-98a7-b42b66cdd891
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3548002757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.3548002757
Directory	/workspace/0.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3769172165
Short name	T354
Test name
Test status
Simulation time	22725520392 ps
CPU time	5444.92 seconds
Started	May 23 04:04:50 PM PDT 24
Finished	May 23 05:35:36 PM PDT 24
Peak memory	602096 kb
Host	smart-8fbf0de7-92e0-4ada-a27f-480a4939aa4f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3769172165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3769172165
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1135345746
Short name	T356
Test name
Test status
Simulation time	2623963260 ps
CPU time	177.93 seconds
Started	May 23 04:18:06 PM PDT 24
Finished	May 23 04:21:05 PM PDT 24
Peak memory	637484 kb
Host	smart-61615da2-9976-4d35-801a-fe6869bf1398
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135345746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.1135345746
Directory	/workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1889798864
Short name	T2166
Test name
Test status
Simulation time	9998319664 ps
CPU time	1284.37 seconds
Started	May 23 04:15:08 PM PDT 24
Finished	May 23 04:36:34 PM PDT 24
Peak memory	585784 kb
Host	smart-bb7a58e5-4dd1-4a01-bbfe-a9fbf86cd0bf
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889798864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.1889798864
Directory	/workspace/0.chip_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2171167310
Short name	T156
Test name
Test status
Simulation time	6614046152 ps
CPU time	520.21 seconds
Started	May 23 04:16:39 PM PDT 24
Finished	May 23 04:25:21 PM PDT 24
Peak memory	658368 kb
Host	smart-39a1ef5b-f828-4a55-b8be-1252eab42d57
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171167310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.2171167310
Directory	/workspace/0.chip_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_csr_rw.286908245
Short name	T2371
Test name
Test status
Simulation time	5256574804 ps
CPU time	555.96 seconds
Started	May 23 04:16:22 PM PDT 24
Finished	May 23 04:25:39 PM PDT 24
Peak memory	592640 kb
Host	smart-7bd8d4f8-7fda-4e3a-9754-bb7392b3c886
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286908245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.286908245
Directory	/workspace/0.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1189595204
Short name	T84
Test name
Test status
Simulation time	11644859480 ps
CPU time	573.12 seconds
Started	May 23 04:15:32 PM PDT 24
Finished	May 23 04:25:06 PM PDT 24
Peak memory	582460 kb
Host	smart-5eb5ab55-b254-40b3-a654-b66f7e4e4c32
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189595204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.1189595204
Directory	/workspace/0.chip_prim_tl_access/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.4256435874
Short name	T2310
Test name
Test status
Simulation time	13855986918 ps
CPU time	616.07 seconds
Started	May 23 04:16:51 PM PDT 24
Finished	May 23 04:27:08 PM PDT 24
Peak memory	585972 kb
Host	smart-b4f2eacf-67a5-45b3-8c93-ee9f15057abe
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256435874 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.4256435874
Directory	/workspace/0.chip_rv_dm_lc_disabled/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2248011224
Short name	T2311
Test name
Test status
Simulation time	31155478143 ps
CPU time	3541.06 seconds
Started	May 23 04:15:12 PM PDT 24
Finished	May 23 05:14:15 PM PDT 24
Peak memory	586960 kb
Host	smart-8086da09-0d58-4332-a9de-d694fff107aa
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248011224 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.2248011224
Directory	/workspace/0.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.chip_tl_errors.2107817671
Short name	T519
Test name
Test status
Simulation time	4125538332 ps
CPU time	387.17 seconds
Started	May 23 04:15:35 PM PDT 24
Finished	May 23 04:22:03 PM PDT 24
Peak memory	594092 kb
Host	smart-553f68bc-0508-49b7-9bd5-942761726f06
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107817671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2107817671
Directory	/workspace/0.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2814498407
Short name	T1786
Test name
Test status
Simulation time	1045923242 ps
CPU time	95.9 seconds
Started	May 23 04:15:51 PM PDT 24
Finished	May 23 04:17:28 PM PDT 24
Peak memory	571884 kb
Host	smart-04ba564a-d91e-4e33-a4a2-e3959c0a1fde
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814498407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 2814498407
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.105246627
Short name	T2740
Test name
Test status
Simulation time	37955757500 ps
CPU time	687.62 seconds
Started	May 23 04:15:55 PM PDT 24
Finished	May 23 04:27:23 PM PDT 24
Peak memory	572036 kb
Host	smart-ce4b3b15-0bf1-4c9d-9e9c-dee28472a8e0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105246627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_de vice_slow_rsp.105246627
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.996218295
Short name	T2182
Test name
Test status
Simulation time	128908087 ps
CPU time	19.97 seconds
Started	May 23 04:15:56 PM PDT 24
Finished	May 23 04:16:16 PM PDT 24
Peak memory	571832 kb
Host	smart-9335c953-6f98-4165-8734-98076f66776f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996218295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr. 996218295
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_error_random.1310827859
Short name	T1730
Test name
Test status
Simulation time	563099756 ps
CPU time	27.41 seconds
Started	May 23 04:16:11 PM PDT 24
Finished	May 23 04:16:40 PM PDT 24
Peak memory	571816 kb
Host	smart-92da6ee1-a915-49f9-a06a-62a6d01ab271
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310827859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1310827859
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_random.766194878
Short name	T2794
Test name
Test status
Simulation time	460134740 ps
CPU time	49.54 seconds
Started	May 23 04:15:45 PM PDT 24
Finished	May 23 04:16:36 PM PDT 24
Peak memory	571768 kb
Host	smart-b94e63df-8614-4a41-a596-63695ae9a37f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766194878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.766194878
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3698838623
Short name	T2415
Test name
Test status
Simulation time	11184671006 ps
CPU time	122.02 seconds
Started	May 23 04:15:55 PM PDT 24
Finished	May 23 04:17:58 PM PDT 24
Peak memory	563836 kb
Host	smart-4546fcc7-fd76-4c2e-a1ff-b7612c3a2653
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698838623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3698838623
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.817579843
Short name	T1710
Test name
Test status
Simulation time	35929976266 ps
CPU time	640.08 seconds
Started	May 23 04:16:01 PM PDT 24
Finished	May 23 04:26:43 PM PDT 24
Peak memory	572036 kb
Host	smart-002d2757-ef16-429f-93d6-73a8c2df96cc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817579843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.817579843
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2175809656
Short name	T1319
Test name
Test status
Simulation time	50584860 ps
CPU time	8.45 seconds
Started	May 23 04:15:43 PM PDT 24
Finished	May 23 04:15:53 PM PDT 24
Peak memory	563556 kb
Host	smart-e27071e7-52ab-4ca2-bbcf-099cdc17d3a5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175809656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.2175809656
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_same_source.2932534013
Short name	T1469
Test name
Test status
Simulation time	538959725 ps
CPU time	46.28 seconds
Started	May 23 04:16:02 PM PDT 24
Finished	May 23 04:16:51 PM PDT 24
Peak memory	571756 kb
Host	smart-e1fdd135-bf81-4426-a3a0-34632ddb2c39
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932534013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2932534013
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke.4150639784
Short name	T2132
Test name
Test status
Simulation time	199290857 ps
CPU time	10.22 seconds
Started	May 23 04:15:53 PM PDT 24
Finished	May 23 04:16:05 PM PDT 24
Peak memory	563528 kb
Host	smart-2691a1fd-4c64-4163-baa9-45ae953e09e9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150639784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4150639784
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.578585129
Short name	T1390
Test name
Test status
Simulation time	7833275806 ps
CPU time	87.66 seconds
Started	May 23 04:15:39 PM PDT 24
Finished	May 23 04:17:08 PM PDT 24
Peak memory	563728 kb
Host	smart-eac63208-6f50-4267-b5f4-deb8d36439e3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578585129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.578585129
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1062277198
Short name	T1448
Test name
Test status
Simulation time	6167926036 ps
CPU time	113.05 seconds
Started	May 23 04:15:48 PM PDT 24
Finished	May 23 04:17:42 PM PDT 24
Peak memory	563796 kb
Host	smart-e795a880-d2f1-444b-9900-a13741940466
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062277198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1062277198
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3843712209
Short name	T2045
Test name
Test status
Simulation time	37884802 ps
CPU time	6.47 seconds
Started	May 23 04:15:41 PM PDT 24
Finished	May 23 04:15:48 PM PDT 24
Peak memory	563524 kb
Host	smart-bb1c1da1-baa6-4ed9-b0e3-95d75ddb17fd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843712209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3843712209
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all.687980370
Short name	T485
Test name
Test status
Simulation time	12129102662 ps
CPU time	573.76 seconds
Started	May 23 04:16:04 PM PDT 24
Finished	May 23 04:25:39 PM PDT 24
Peak memory	572040 kb
Host	smart-9a9de972-c085-4d8e-96fc-36b4659fed59
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687980370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.687980370
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3507338880
Short name	T1532
Test name
Test status
Simulation time	1524035283 ps
CPU time	129.32 seconds
Started	May 23 04:16:08 PM PDT 24
Finished	May 23 04:18:18 PM PDT 24
Peak memory	571896 kb
Host	smart-fe2b185d-a3fc-4fcc-af0c-02706eda7eb4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507338880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3507338880
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3996903114
Short name	T2469
Test name
Test status
Simulation time	2415379136 ps
CPU time	420.4 seconds
Started	May 23 04:16:37 PM PDT 24
Finished	May 23 04:23:38 PM PDT 24
Peak memory	573080 kb
Host	smart-8b4f79bb-fc3f-4ea9-b9b6-1fa8063afaec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996903114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.3996903114
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1725447947
Short name	T495
Test name
Test status
Simulation time	544219120 ps
CPU time	203.68 seconds
Started	May 23 04:17:44 PM PDT 24
Finished	May 23 04:21:12 PM PDT 24
Peak memory	573024 kb
Host	smart-dfc1c4c5-cfb1-4c2f-9117-5c54c0df31da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725447947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.1725447947
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.974990058
Short name	T2109
Test name
Test status
Simulation time	258812689 ps
CPU time	33.21 seconds
Started	May 23 04:15:54 PM PDT 24
Finished	May 23 04:16:28 PM PDT 24
Peak memory	571884 kb
Host	smart-f1ef979c-8d2a-4f27-9169-e5e743a417b4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974990058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.974990058
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3310573634
Short name	T642
Test name
Test status
Simulation time	5742020653 ps
CPU time	618.17 seconds
Started	May 23 04:16:57 PM PDT 24
Finished	May 23 04:27:17 PM PDT 24
Peak memory	585776 kb
Host	smart-3f14795e-3c2d-4406-991f-b9ac4787c9fb
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310573634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.3310573634
Directory	/workspace/1.chip_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_csr_rw.2563939759
Short name	T350
Test name
Test status
Simulation time	5995446342 ps
CPU time	703.43 seconds
Started	May 23 04:17:34 PM PDT 24
Finished	May 23 04:29:20 PM PDT 24
Peak memory	592024 kb
Host	smart-560ee722-1dab-468c-8c42-7b2076d4db4e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563939759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.2563939759
Directory	/workspace/1.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1717649053
Short name	T2474
Test name
Test status
Simulation time	11070852818 ps
CPU time	448.92 seconds
Started	May 23 04:16:46 PM PDT 24
Finished	May 23 04:24:16 PM PDT 24
Peak memory	586164 kb
Host	smart-1db13077-eda6-4ad7-825e-1fca95785a40
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717649053 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.1717649053
Directory	/workspace/1.chip_rv_dm_lc_disabled/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3297563588
Short name	T2725
Test name
Test status
Simulation time	29698070658 ps
CPU time	3745.55 seconds
Started	May 23 04:16:39 PM PDT 24
Finished	May 23 05:19:06 PM PDT 24
Peak memory	587116 kb
Host	smart-76ee70ba-39a2-4d0a-89a9-f5e720eefee8
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297563588 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.3297563588
Directory	/workspace/1.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.chip_tl_errors.3502238437
Short name	T1893
Test name
Test status
Simulation time	3295328212 ps
CPU time	246.65 seconds
Started	May 23 04:16:59 PM PDT 24
Finished	May 23 04:21:07 PM PDT 24
Peak memory	601380 kb
Host	smart-7945b284-54f5-4d4d-b902-112ed8e08fae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502238437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3502238437
Directory	/workspace/1.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_access_same_device.4247313696
Short name	T1674
Test name
Test status
Simulation time	533629151 ps
CPU time	36.99 seconds
Started	May 23 04:16:59 PM PDT 24
Finished	May 23 04:17:36 PM PDT 24
Peak memory	571832 kb
Host	smart-ad668b9e-e547-499e-a18e-7e460e4f33f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247313696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 4247313696
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1447448600
Short name	T2523
Test name
Test status
Simulation time	130207440915 ps
CPU time	2310.81 seconds
Started	May 23 04:17:17 PM PDT 24
Finished	May 23 04:55:49 PM PDT 24
Peak memory	572056 kb
Host	smart-e7245b11-5123-4ba4-99aa-441faaad0c47
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447448600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.1447448600
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3264527559
Short name	T1654
Test name
Test status
Simulation time	1556030137 ps
CPU time	79.97 seconds
Started	May 23 04:17:38 PM PDT 24
Finished	May 23 04:18:59 PM PDT 24
Peak memory	571808 kb
Host	smart-604b0d45-1d1b-4112-bb91-b265d0b5b22a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264527559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .3264527559
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_error_random.2897478128
Short name	T1294
Test name
Test status
Simulation time	980368509 ps
CPU time	47.86 seconds
Started	May 23 04:17:20 PM PDT 24
Finished	May 23 04:18:09 PM PDT 24
Peak memory	571804 kb
Host	smart-becd1359-b9fc-493c-ba5e-9e4caade0a96
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897478128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2897478128
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_random.2751562152
Short name	T496
Test name
Test status
Simulation time	958666549 ps
CPU time	35.37 seconds
Started	May 23 04:16:53 PM PDT 24
Finished	May 23 04:17:30 PM PDT 24
Peak memory	571820 kb
Host	smart-3935058b-2f21-4592-9aed-cbb3726ac69e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751562152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.2751562152
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2137707852
Short name	T1490
Test name
Test status
Simulation time	75130668019 ps
CPU time	910.77 seconds
Started	May 23 04:17:51 PM PDT 24
Finished	May 23 04:33:04 PM PDT 24
Peak memory	571968 kb
Host	smart-3b78fd5a-1ef9-4a4c-a858-7a9b8174fe8d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137707852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2137707852
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.655849515
Short name	T1888
Test name
Test status
Simulation time	33291233929 ps
CPU time	543.94 seconds
Started	May 23 04:16:49 PM PDT 24
Finished	May 23 04:25:54 PM PDT 24
Peak memory	572060 kb
Host	smart-9e1287bc-b132-457d-8edd-0b1562e426b1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655849515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.655849515
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1986739967
Short name	T2730
Test name
Test status
Simulation time	192006293 ps
CPU time	25.33 seconds
Started	May 23 04:17:44 PM PDT 24
Finished	May 23 04:18:10 PM PDT 24
Peak memory	571780 kb
Host	smart-bb8a5636-9fcf-45b8-ba9f-a74d669a4962
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986739967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.1986739967
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_same_source.3893422858
Short name	T2170
Test name
Test status
Simulation time	1970085298 ps
CPU time	72.35 seconds
Started	May 23 04:17:01 PM PDT 24
Finished	May 23 04:18:14 PM PDT 24
Peak memory	571800 kb
Host	smart-6b68f6c1-ced7-40d8-ae2b-0d7709fadc01
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893422858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3893422858
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke.3011127058
Short name	T1446
Test name
Test status
Simulation time	246159645 ps
CPU time	11.38 seconds
Started	May 23 04:17:12 PM PDT 24
Finished	May 23 04:17:25 PM PDT 24
Peak memory	563536 kb
Host	smart-857ae2f7-cdfd-4006-ba9e-56ffcde0fb0d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011127058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3011127058
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1567953610
Short name	T1940
Test name
Test status
Simulation time	9345544289 ps
CPU time	127.35 seconds
Started	May 23 04:17:31 PM PDT 24
Finished	May 23 04:19:40 PM PDT 24
Peak memory	563780 kb
Host	smart-82bc9f7c-b26b-4d1a-ac64-8e0d105426ae
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567953610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1567953610
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.391093146
Short name	T2065
Test name
Test status
Simulation time	5838462005 ps
CPU time	124.15 seconds
Started	May 23 04:17:13 PM PDT 24
Finished	May 23 04:19:18 PM PDT 24
Peak memory	563808 kb
Host	smart-c259e1c4-53ce-41b0-8b6e-d1757f9234c3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391093146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.391093146
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4208286990
Short name	T1887
Test name
Test status
Simulation time	48857294 ps
CPU time	8 seconds
Started	May 23 04:16:56 PM PDT 24
Finished	May 23 04:17:05 PM PDT 24
Peak memory	563528 kb
Host	smart-b2db85b3-46b3-4577-b82a-a0a6ca1c1005
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208286990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .4208286990
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all.1844912301
Short name	T421
Test name
Test status
Simulation time	2820932328 ps
CPU time	311.45 seconds
Started	May 23 04:17:34 PM PDT 24
Finished	May 23 04:22:47 PM PDT 24
Peak memory	572952 kb
Host	smart-e2347046-cd3b-47cd-bdf3-e1c35b5e595b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844912301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1844912301
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.162999719
Short name	T1978
Test name
Test status
Simulation time	2660643296 ps
CPU time	132.11 seconds
Started	May 23 04:17:42 PM PDT 24
Finished	May 23 04:19:56 PM PDT 24
Peak memory	572044 kb
Host	smart-3b378a1c-ca9e-4126-bc15-ffaa5e15ed31
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162999719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.162999719
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1904398164
Short name	T2160
Test name
Test status
Simulation time	877420009 ps
CPU time	228.07 seconds
Started	May 23 04:17:24 PM PDT 24
Finished	May 23 04:21:13 PM PDT 24
Peak memory	572932 kb
Host	smart-dfa714b6-a40e-46d9-b2d5-9c6556203095
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904398164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.1904398164
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.65784871
Short name	T840
Test name
Test status
Simulation time	8823655439 ps
CPU time	531.55 seconds
Started	May 23 04:18:08 PM PDT 24
Finished	May 23 04:27:02 PM PDT 24
Peak memory	573120 kb
Host	smart-d43f9d2b-0bde-4a76-ade2-0a1e3794188d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65784871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_w ith_reset_error.65784871
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.624362522
Short name	T2784
Test name
Test status
Simulation time	873718441 ps
CPU time	52.35 seconds
Started	May 23 04:17:08 PM PDT 24
Finished	May 23 04:18:02 PM PDT 24
Peak memory	571832 kb
Host	smart-19c2b889-28ac-42c5-9cdc-88b301afb546
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624362522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.624362522
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/10.chip_csr_rw.2248547091
Short name	T2103
Test name
Test status
Simulation time	4340958600 ps
CPU time	365.07 seconds
Started	May 23 04:23:35 PM PDT 24
Finished	May 23 04:29:41 PM PDT 24
Peak memory	592788 kb
Host	smart-ea47a2d4-7383-4edf-9b0a-a5066dae2921
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248547091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2248547091
Directory	/workspace/10.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1743455378
Short name	T418
Test name
Test status
Simulation time	17472833191 ps
CPU time	2172.14 seconds
Started	May 23 04:23:14 PM PDT 24
Finished	May 23 04:59:28 PM PDT 24
Peak memory	586516 kb
Host	smart-53cccc5c-d2b1-4c8f-b0f0-e1980672737b
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743455378 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.1743455378
Directory	/workspace/10.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.chip_tl_errors.926496918
Short name	T612
Test name
Test status
Simulation time	3501283802 ps
CPU time	202.6 seconds
Started	May 23 04:23:11 PM PDT 24
Finished	May 23 04:26:35 PM PDT 24
Peak memory	594000 kb
Host	smart-29895787-5f5d-4c28-baf9-51c87ae27428
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926496918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.926496918
Directory	/workspace/10.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1660726372
Short name	T1788
Test name
Test status
Simulation time	886680924 ps
CPU time	77.22 seconds
Started	May 23 04:23:25 PM PDT 24
Finished	May 23 04:24:42 PM PDT 24
Peak memory	571864 kb
Host	smart-72a845bc-d033-4bff-8be9-dc27f70f1647
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660726372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .1660726372
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4230534078
Short name	T795
Test name
Test status
Simulation time	69043949613 ps
CPU time	1283 seconds
Started	May 23 04:23:21 PM PDT 24
Finished	May 23 04:44:45 PM PDT 24
Peak memory	572056 kb
Host	smart-8e14e3ef-a9e2-4236-8d0f-b491d0e99faa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230534078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.4230534078
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3648226549
Short name	T2107
Test name
Test status
Simulation time	113917640 ps
CPU time	17.35 seconds
Started	May 23 04:23:36 PM PDT 24
Finished	May 23 04:23:54 PM PDT 24
Peak memory	571804 kb
Host	smart-6cf85b23-9410-41c8-a6fc-819f4fd04a0a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648226549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.3648226549
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_error_random.2830696724
Short name	T1343
Test name
Test status
Simulation time	661262337 ps
CPU time	23.71 seconds
Started	May 23 04:23:22 PM PDT 24
Finished	May 23 04:23:47 PM PDT 24
Peak memory	571832 kb
Host	smart-6319a714-c3ad-45fa-a2fe-ab70cfb19793
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830696724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2830696724
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_random.4179846189
Short name	T1904
Test name
Test status
Simulation time	1229647440 ps
CPU time	52.81 seconds
Started	May 23 04:23:24 PM PDT 24
Finished	May 23 04:24:17 PM PDT 24
Peak memory	571748 kb
Host	smart-178117f7-16fb-4d12-a50f-c00ff9f0d7be
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179846189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.4179846189
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.272273084
Short name	T477
Test name
Test status
Simulation time	107441472038 ps
CPU time	1254.26 seconds
Started	May 23 04:23:26 PM PDT 24
Finished	May 23 04:44:21 PM PDT 24
Peak memory	572080 kb
Host	smart-65998446-84a4-4d62-92d6-607d775f7997
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272273084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.272273084
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2981102115
Short name	T2192
Test name
Test status
Simulation time	64702884722 ps
CPU time	1179.98 seconds
Started	May 23 04:23:34 PM PDT 24
Finished	May 23 04:43:15 PM PDT 24
Peak memory	572052 kb
Host	smart-f8ddd08f-fdaf-4352-941e-35066e994a8c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981102115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2981102115
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.353577467
Short name	T1966
Test name
Test status
Simulation time	405499361 ps
CPU time	46.72 seconds
Started	May 23 04:23:26 PM PDT 24
Finished	May 23 04:24:13 PM PDT 24
Peak memory	571856 kb
Host	smart-41085fdc-e800-4541-985d-e71e07670ab3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353577467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela ys.353577467
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_same_source.1781237684
Short name	T1643
Test name
Test status
Simulation time	1768061018 ps
CPU time	54.68 seconds
Started	May 23 04:23:21 PM PDT 24
Finished	May 23 04:24:16 PM PDT 24
Peak memory	571804 kb
Host	smart-026799a9-25fb-4329-a01d-908ea96ec14b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781237684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1781237684
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke.1226122976
Short name	T2502
Test name
Test status
Simulation time	234589112 ps
CPU time	10.28 seconds
Started	May 23 04:23:12 PM PDT 24
Finished	May 23 04:23:23 PM PDT 24
Peak memory	563532 kb
Host	smart-31f5870f-b5d7-4c0e-a5a1-3ac52f816c91
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226122976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1226122976
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3676008849
Short name	T2018
Test name
Test status
Simulation time	8025639271 ps
CPU time	84.15 seconds
Started	May 23 04:23:23 PM PDT 24
Finished	May 23 04:24:48 PM PDT 24
Peak memory	563772 kb
Host	smart-86d77925-86af-4710-9fdd-695b980b7db9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676008849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3676008849
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3278618100
Short name	T1619
Test name
Test status
Simulation time	4760233139 ps
CPU time	88.12 seconds
Started	May 23 04:23:25 PM PDT 24
Finished	May 23 04:24:54 PM PDT 24
Peak memory	563792 kb
Host	smart-7b2d6331-05af-464a-907e-b2badb17b452
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278618100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3278618100
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3593007473
Short name	T2004
Test name
Test status
Simulation time	55316836 ps
CPU time	8.16 seconds
Started	May 23 04:23:17 PM PDT 24
Finished	May 23 04:23:27 PM PDT 24
Peak memory	563460 kb
Host	smart-e7381cd3-216c-4af8-9277-0ee0276d35d2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593007473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.3593007473
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all.765334983
Short name	T1310
Test name
Test status
Simulation time	2462682916 ps
CPU time	114.13 seconds
Started	May 23 04:23:37 PM PDT 24
Finished	May 23 04:25:32 PM PDT 24
Peak memory	572020 kb
Host	smart-90ab04df-9592-4b0e-ad10-1d45c216cb89
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765334983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.765334983
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.323656211
Short name	T1972
Test name
Test status
Simulation time	1891054080 ps
CPU time	312.43 seconds
Started	May 23 04:23:35 PM PDT 24
Finished	May 23 04:28:49 PM PDT 24
Peak memory	572900 kb
Host	smart-e7502c20-8f91-4e6a-a7d6-7ea96d165294
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323656211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_ with_rand_reset.323656211
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3974068989
Short name	T2235
Test name
Test status
Simulation time	14781925399 ps
CPU time	804.89 seconds
Started	May 23 04:23:35 PM PDT 24
Finished	May 23 04:37:01 PM PDT 24
Peak memory	573132 kb
Host	smart-5a3df04c-d301-4b78-9fce-38c469144848
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974068989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.3974068989
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4051795048
Short name	T2205
Test name
Test status
Simulation time	290268504 ps
CPU time	35.79 seconds
Started	May 23 04:23:24 PM PDT 24
Finished	May 23 04:24:00 PM PDT 24
Peak memory	571880 kb
Host	smart-adb2b946-2a91-44f5-a993-2f126abc20ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051795048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.4051795048
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/11.chip_csr_rw.4084620716
Short name	T2578
Test name
Test status
Simulation time	6057258806 ps
CPU time	672.46 seconds
Started	May 23 04:23:59 PM PDT 24
Finished	May 23 04:35:13 PM PDT 24
Peak memory	592596 kb
Host	smart-c97ed600-9176-499c-b29d-84e6935b7814
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084620716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.4084620716
Directory	/workspace/11.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.chip_tl_errors.284566585
Short name	T551
Test name
Test status
Simulation time	2817723577 ps
CPU time	183.23 seconds
Started	May 23 04:23:35 PM PDT 24
Finished	May 23 04:26:40 PM PDT 24
Peak memory	594072 kb
Host	smart-e463965d-d187-4ac1-80c7-48321dd8d5c4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284566585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.284566585
Directory	/workspace/11.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3637074775
Short name	T1485
Test name
Test status
Simulation time	366668350 ps
CPU time	20.32 seconds
Started	May 23 04:23:48 PM PDT 24
Finished	May 23 04:24:10 PM PDT 24
Peak memory	571772 kb
Host	smart-53074e96-da75-4ba6-9764-73385bd657a0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637074775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .3637074775
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1655660575
Short name	T807
Test name
Test status
Simulation time	106089001161 ps
CPU time	1785.09 seconds
Started	May 23 04:23:48 PM PDT 24
Finished	May 23 04:53:35 PM PDT 24
Peak memory	572044 kb
Host	smart-747208a7-d489-4c23-a3e9-d4c86326a113
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655660575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.1655660575
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.644186410
Short name	T2258
Test name
Test status
Simulation time	652432195 ps
CPU time	31.05 seconds
Started	May 23 04:23:47 PM PDT 24
Finished	May 23 04:24:20 PM PDT 24
Peak memory	571796 kb
Host	smart-d0b0c2b7-0f56-45b3-8bf0-726293d3c844
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644186410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr .644186410
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_error_random.3252639224
Short name	T2366
Test name
Test status
Simulation time	69008932 ps
CPU time	9.5 seconds
Started	May 23 04:23:50 PM PDT 24
Finished	May 23 04:24:00 PM PDT 24
Peak memory	563624 kb
Host	smart-d264c2d9-185a-491b-9207-c8640d2ff80a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252639224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3252639224
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_random.1453489013
Short name	T1534
Test name
Test status
Simulation time	2011309952 ps
CPU time	81 seconds
Started	May 23 04:23:48 PM PDT 24
Finished	May 23 04:25:10 PM PDT 24
Peak memory	571840 kb
Host	smart-ef6dc59f-9877-4dae-920b-4f2559ef6ee4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453489013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1453489013
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.166237501
Short name	T1891
Test name
Test status
Simulation time	75065800326 ps
CPU time	892.35 seconds
Started	May 23 04:23:54 PM PDT 24
Finished	May 23 04:38:48 PM PDT 24
Peak memory	572028 kb
Host	smart-fd8ac999-2362-43d7-af92-850ae07f0480
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166237501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.166237501
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3289649554
Short name	T542
Test name
Test status
Simulation time	21911027947 ps
CPU time	393.87 seconds
Started	May 23 04:24:02 PM PDT 24
Finished	May 23 04:30:37 PM PDT 24
Peak memory	572072 kb
Host	smart-c7e5f298-35d5-42ba-8be8-88c57c6adef0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289649554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3289649554
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3653263435
Short name	T1360
Test name
Test status
Simulation time	199509779 ps
CPU time	22.28 seconds
Started	May 23 04:23:46 PM PDT 24
Finished	May 23 04:24:10 PM PDT 24
Peak memory	571792 kb
Host	smart-a9e984de-9259-434c-891d-c743b5ba97cf
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653263435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.3653263435
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_same_source.2644133027
Short name	T2788
Test name
Test status
Simulation time	641497379 ps
CPU time	24.97 seconds
Started	May 23 04:23:48 PM PDT 24
Finished	May 23 04:24:14 PM PDT 24
Peak memory	571768 kb
Host	smart-43289aed-ba90-45ef-8a0e-5ae716b12359
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644133027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2644133027
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke.361617328
Short name	T2231
Test name
Test status
Simulation time	54613375 ps
CPU time	7.25 seconds
Started	May 23 04:23:37 PM PDT 24
Finished	May 23 04:23:45 PM PDT 24
Peak memory	563544 kb
Host	smart-705fd965-8f2e-47f8-b4ba-b20b7f7a0481
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361617328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.361617328
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2422953226
Short name	T2104
Test name
Test status
Simulation time	10068733470 ps
CPU time	107.9 seconds
Started	May 23 04:23:50 PM PDT 24
Finished	May 23 04:25:38 PM PDT 24
Peak memory	563724 kb
Host	smart-18af634c-b216-4b20-9aa3-715b05d07e28
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422953226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2422953226
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1879298091
Short name	T1624
Test name
Test status
Simulation time	5157055117 ps
CPU time	93.77 seconds
Started	May 23 04:23:47 PM PDT 24
Finished	May 23 04:25:22 PM PDT 24
Peak memory	563800 kb
Host	smart-8a79859d-a611-4aa9-983b-fd55b84e61c5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879298091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1879298091
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4024774711
Short name	T2172
Test name
Test status
Simulation time	52245296 ps
CPU time	7.66 seconds
Started	May 23 04:23:36 PM PDT 24
Finished	May 23 04:23:45 PM PDT 24
Peak memory	563564 kb
Host	smart-bdff0849-8b45-4799-8b3d-c8717b203d55
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024774711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.4024774711
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all.2105406885
Short name	T2481
Test name
Test status
Simulation time	1180968091 ps
CPU time	115.47 seconds
Started	May 23 04:24:01 PM PDT 24
Finished	May 23 04:25:58 PM PDT 24
Peak memory	571980 kb
Host	smart-2b220335-2bed-47b0-8f29-f85a915e1b10
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105406885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2105406885
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2612668982
Short name	T1785
Test name
Test status
Simulation time	3846824186 ps
CPU time	171.32 seconds
Started	May 23 04:23:59 PM PDT 24
Finished	May 23 04:26:52 PM PDT 24
Peak memory	572040 kb
Host	smart-bf86bbbe-4c4c-4587-b4a6-17380fbc0ded
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612668982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2612668982
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1839338741
Short name	T2324
Test name
Test status
Simulation time	8610651 ps
CPU time	9.94 seconds
Started	May 23 04:24:06 PM PDT 24
Finished	May 23 04:24:16 PM PDT 24
Peak memory	563644 kb
Host	smart-22d53ef9-23f4-4479-a6c9-add28fbf91ec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839338741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.1839338741
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1510123446
Short name	T2519
Test name
Test status
Simulation time	271840276 ps
CPU time	80.68 seconds
Started	May 23 04:24:00 PM PDT 24
Finished	May 23 04:25:23 PM PDT 24
Peak memory	573212 kb
Host	smart-4d2ae731-e798-409c-9ab3-0ec3e06e27f2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510123446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.1510123446
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3018362576
Short name	T2332
Test name
Test status
Simulation time	1332625325 ps
CPU time	62.73 seconds
Started	May 23 04:23:47 PM PDT 24
Finished	May 23 04:24:51 PM PDT 24
Peak memory	571868 kb
Host	smart-b20b4cec-28b5-4dc3-b9d4-1bc13a1678b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018362576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3018362576
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/12.chip_csr_rw.2105915635
Short name	T2455
Test name
Test status
Simulation time	3864138255 ps
CPU time	358.64 seconds
Started	May 23 04:24:24 PM PDT 24
Finished	May 23 04:30:24 PM PDT 24
Peak memory	590940 kb
Host	smart-a2e6ce16-0e89-43db-a6ed-2b309f7ea38c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105915635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.2105915635
Directory	/workspace/12.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3565899380
Short name	T2226
Test name
Test status
Simulation time	26364593234 ps
CPU time	2985.01 seconds
Started	May 23 04:24:03 PM PDT 24
Finished	May 23 05:13:49 PM PDT 24
Peak memory	586868 kb
Host	smart-506398d0-cf05-4cfc-8dbb-8cb351c7b7f4
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565899380 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.3565899380
Directory	/workspace/12.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3304567418
Short name	T2701
Test name
Test status
Simulation time	1693966263 ps
CPU time	77.19 seconds
Started	May 23 04:24:24 PM PDT 24
Finished	May 23 04:25:43 PM PDT 24
Peak memory	571884 kb
Host	smart-87f6d943-b5f4-4c15-9b34-85a2182e21a3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304567418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .3304567418
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3815334677
Short name	T786
Test name
Test status
Simulation time	17366237966 ps
CPU time	327.71 seconds
Started	May 23 04:24:20 PM PDT 24
Finished	May 23 04:29:48 PM PDT 24
Peak memory	572028 kb
Host	smart-ffb9380f-c244-4226-919c-39c119deadb5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815334677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.3815334677
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1553494158
Short name	T1915
Test name
Test status
Simulation time	177656211 ps
CPU time	22.36 seconds
Started	May 23 04:24:17 PM PDT 24
Finished	May 23 04:24:40 PM PDT 24
Peak memory	571868 kb
Host	smart-ffb505cb-9160-4175-8f4a-3dfd62ee5bad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553494158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.1553494158
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_error_random.139667446
Short name	T1387
Test name
Test status
Simulation time	243803614 ps
CPU time	24.42 seconds
Started	May 23 04:24:14 PM PDT 24
Finished	May 23 04:24:39 PM PDT 24
Peak memory	571840 kb
Host	smart-e5652e39-dc69-4a93-9b6d-98468e54f69d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139667446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.139667446
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_random.483792654
Short name	T2758
Test name
Test status
Simulation time	1629482044 ps
CPU time	66.81 seconds
Started	May 23 04:24:20 PM PDT 24
Finished	May 23 04:25:27 PM PDT 24
Peak memory	571768 kb
Host	smart-1a7845f3-657c-43c8-8495-86e30cbacfec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483792654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.483792654
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2804701408
Short name	T467
Test name
Test status
Simulation time	55866691943 ps
CPU time	622.65 seconds
Started	May 23 04:24:17 PM PDT 24
Finished	May 23 04:34:40 PM PDT 24
Peak memory	571980 kb
Host	smart-b16c189c-9959-4a46-931e-6f072e893288
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804701408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2804701408
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.310927891
Short name	T2773
Test name
Test status
Simulation time	24254576737 ps
CPU time	459.7 seconds
Started	May 23 04:24:14 PM PDT 24
Finished	May 23 04:31:54 PM PDT 24
Peak memory	572044 kb
Host	smart-c568068f-a79b-4df9-bc6c-5d0c58da6615
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310927891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.310927891
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.124931398
Short name	T1866
Test name
Test status
Simulation time	430854849 ps
CPU time	41.72 seconds
Started	May 23 04:24:14 PM PDT 24
Finished	May 23 04:24:57 PM PDT 24
Peak memory	571760 kb
Host	smart-4ce67833-36e5-4106-8947-d244d2e7f67a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124931398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_dela ys.124931398
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_same_source.1485687407
Short name	T529
Test name
Test status
Simulation time	184409096 ps
CPU time	9.6 seconds
Started	May 23 04:24:20 PM PDT 24
Finished	May 23 04:24:30 PM PDT 24
Peak memory	563500 kb
Host	smart-e90eb269-ac2b-4453-a9ab-5f27f5a0612c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485687407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1485687407
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke.670142124
Short name	T1663
Test name
Test status
Simulation time	53096705 ps
CPU time	7.57 seconds
Started	May 23 04:24:00 PM PDT 24
Finished	May 23 04:24:09 PM PDT 24
Peak memory	563564 kb
Host	smart-6ddf7879-0c47-4659-885c-7d2bcad474d5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670142124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.670142124
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2238929792
Short name	T2544
Test name
Test status
Simulation time	7303006288 ps
CPU time	87.89 seconds
Started	May 23 04:24:07 PM PDT 24
Finished	May 23 04:25:36 PM PDT 24
Peak memory	563724 kb
Host	smart-da458ae7-3a26-41f4-a63d-f6918e0444ae
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238929792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2238929792
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1176935382
Short name	T2702
Test name
Test status
Simulation time	3912613666 ps
CPU time	70.05 seconds
Started	May 23 04:24:00 PM PDT 24
Finished	May 23 04:25:11 PM PDT 24
Peak memory	563772 kb
Host	smart-40f8dd37-edcf-43b3-a691-e4b000f8b24a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176935382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1176935382
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1489317386
Short name	T1327
Test name
Test status
Simulation time	58492794 ps
CPU time	7.57 seconds
Started	May 23 04:24:05 PM PDT 24
Finished	May 23 04:24:13 PM PDT 24
Peak memory	563556 kb
Host	smart-53d9723e-e285-4b27-a0c6-71e5b46d887c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489317386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.1489317386
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1769763863
Short name	T1405
Test name
Test status
Simulation time	3306054159 ps
CPU time	129.36 seconds
Started	May 23 04:24:15 PM PDT 24
Finished	May 23 04:26:25 PM PDT 24
Peak memory	571996 kb
Host	smart-235be530-bafe-432e-9042-21ca025d47d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769763863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1769763863
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2091775307
Short name	T821
Test name
Test status
Simulation time	5923613806 ps
CPU time	809.26 seconds
Started	May 23 04:24:17 PM PDT 24
Finished	May 23 04:37:48 PM PDT 24
Peak memory	573120 kb
Host	smart-2e51b3e6-40f0-4e4e-bd74-970f7fc09ab6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091775307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.2091775307
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1328204162
Short name	T2736
Test name
Test status
Simulation time	998302809 ps
CPU time	290.91 seconds
Started	May 23 04:24:13 PM PDT 24
Finished	May 23 04:29:05 PM PDT 24
Peak memory	573000 kb
Host	smart-78ccca78-499a-4139-b214-fa4c3acca760
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328204162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.1328204162
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2489297138
Short name	T1905
Test name
Test status
Simulation time	143512154 ps
CPU time	18.45 seconds
Started	May 23 04:24:24 PM PDT 24
Finished	May 23 04:24:44 PM PDT 24
Peak memory	571864 kb
Host	smart-81fed8c9-3b72-4614-9c26-9ab5c9a32bb3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489297138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2489297138
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/13.chip_csr_rw.2936764592
Short name	T2249
Test name
Test status
Simulation time	3717918988 ps
CPU time	326.95 seconds
Started	May 23 04:24:55 PM PDT 24
Finished	May 23 04:30:22 PM PDT 24
Peak memory	591428 kb
Host	smart-29022f61-481f-4485-aed8-3ec0e32ffc14
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936764592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.2936764592
Directory	/workspace/13.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3364683600
Short name	T2567
Test name
Test status
Simulation time	29557076854 ps
CPU time	3314.31 seconds
Started	May 23 04:24:32 PM PDT 24
Finished	May 23 05:19:48 PM PDT 24
Peak memory	586672 kb
Host	smart-54031204-43f6-4d7d-88d4-1b0dd4e24149
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364683600 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.3364683600
Directory	/workspace/13.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.chip_tl_errors.1393975801
Short name	T655
Test name
Test status
Simulation time	3406199192 ps
CPU time	248.46 seconds
Started	May 23 04:24:30 PM PDT 24
Finished	May 23 04:28:40 PM PDT 24
Peak memory	594072 kb
Host	smart-1b4da62c-1d37-4eb1-ad91-c4104e8e7cef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393975801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.1393975801
Directory	/workspace/13.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2151524664
Short name	T1306
Test name
Test status
Simulation time	2063168643 ps
CPU time	96.42 seconds
Started	May 23 04:24:48 PM PDT 24
Finished	May 23 04:26:26 PM PDT 24
Peak memory	571856 kb
Host	smart-c8f9c25e-a501-4c99-b160-7f4e6d33d07a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151524664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .2151524664
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.683335721
Short name	T2643
Test name
Test status
Simulation time	53520673971 ps
CPU time	940.71 seconds
Started	May 23 04:24:45 PM PDT 24
Finished	May 23 04:40:27 PM PDT 24
Peak memory	572028 kb
Host	smart-00cddf37-1c5f-43e9-8bab-6a0786425065
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683335721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_d evice_slow_rsp.683335721
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2502513390
Short name	T2441
Test name
Test status
Simulation time	1447414675 ps
CPU time	63.05 seconds
Started	May 23 04:24:46 PM PDT 24
Finished	May 23 04:25:51 PM PDT 24
Peak memory	571848 kb
Host	smart-6a95e6d7-499d-4be1-a735-fe690671d297
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502513390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.2502513390
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_error_random.2776940327
Short name	T1834
Test name
Test status
Simulation time	2332262164 ps
CPU time	92.25 seconds
Started	May 23 04:24:48 PM PDT 24
Finished	May 23 04:26:23 PM PDT 24
Peak memory	571976 kb
Host	smart-96ee3c6a-3787-42ae-bcba-1d3ef6e6e11b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776940327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2776940327
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_random.4111491964
Short name	T2071
Test name
Test status
Simulation time	358470797 ps
CPU time	38.79 seconds
Started	May 23 04:24:43 PM PDT 24
Finished	May 23 04:25:23 PM PDT 24
Peak memory	571812 kb
Host	smart-eba85be8-65bd-4f79-83e5-28e81df32d95
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111491964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.4111491964
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2049410153
Short name	T1590
Test name
Test status
Simulation time	81733381770 ps
CPU time	869.56 seconds
Started	May 23 04:24:45 PM PDT 24
Finished	May 23 04:39:16 PM PDT 24
Peak memory	571996 kb
Host	smart-194d19d3-c600-40b4-b615-7d9206c0537d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049410153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2049410153
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3948295467
Short name	T588
Test name
Test status
Simulation time	14804915783 ps
CPU time	261.01 seconds
Started	May 23 04:24:43 PM PDT 24
Finished	May 23 04:29:05 PM PDT 24
Peak memory	572056 kb
Host	smart-1f918928-026f-4927-af5a-15a7369565f7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948295467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3948295467
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3535838511
Short name	T2707
Test name
Test status
Simulation time	292502362 ps
CPU time	33.12 seconds
Started	May 23 04:24:44 PM PDT 24
Finished	May 23 04:25:19 PM PDT 24
Peak memory	571832 kb
Host	smart-320f6ef2-9891-432f-9c3f-cea57a5755c5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535838511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.3535838511
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_same_source.610075645
Short name	T591
Test name
Test status
Simulation time	821657938 ps
CPU time	30.04 seconds
Started	May 23 04:24:46 PM PDT 24
Finished	May 23 04:25:17 PM PDT 24
Peak memory	571860 kb
Host	smart-100056d8-c45a-4e08-9e11-01b5a0001e9c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610075645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.610075645
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke.1131469187
Short name	T2375
Test name
Test status
Simulation time	42597762 ps
CPU time	6.46 seconds
Started	May 23 04:24:30 PM PDT 24
Finished	May 23 04:24:38 PM PDT 24
Peak memory	563500 kb
Host	smart-4f6641cc-3daa-47a1-89d0-b0e7de70e46e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131469187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1131469187
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3149973013
Short name	T1332
Test name
Test status
Simulation time	7752675896 ps
CPU time	80.62 seconds
Started	May 23 04:24:47 PM PDT 24
Finished	May 23 04:26:09 PM PDT 24
Peak memory	563736 kb
Host	smart-69d5c653-6be7-4399-a949-c64780b601bf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149973013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3149973013
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.77291306
Short name	T2733
Test name
Test status
Simulation time	3456294197 ps
CPU time	66.21 seconds
Started	May 23 04:24:45 PM PDT 24
Finished	May 23 04:25:52 PM PDT 24
Peak memory	563760 kb
Host	smart-765153ce-917b-4dab-a311-a9261b6bf8bd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77291306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.77291306
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.32498708
Short name	T2577
Test name
Test status
Simulation time	51570806 ps
CPU time	7.47 seconds
Started	May 23 04:24:31 PM PDT 24
Finished	May 23 04:24:40 PM PDT 24
Peak memory	563476 kb
Host	smart-e4597209-3e99-456d-a791-9bb134f4e6d6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32498708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.32498708
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.612446124
Short name	T780
Test name
Test status
Simulation time	2485912220 ps
CPU time	242.68 seconds
Started	May 23 04:24:58 PM PDT 24
Finished	May 23 04:29:01 PM PDT 24
Peak memory	572080 kb
Host	smart-7b05b9b1-b0a7-41a0-9c3a-99d33c47439a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612446124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.612446124
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4019343868
Short name	T488
Test name
Test status
Simulation time	101733413 ps
CPU time	45.66 seconds
Started	May 23 04:24:55 PM PDT 24
Finished	May 23 04:25:42 PM PDT 24
Peak memory	572008 kb
Host	smart-50dbd480-0531-48e8-857f-80a00f6c8e69
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019343868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.4019343868
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3183390663
Short name	T1559
Test name
Test status
Simulation time	243726389 ps
CPU time	63.87 seconds
Started	May 23 04:24:57 PM PDT 24
Finished	May 23 04:26:02 PM PDT 24
Peak memory	571944 kb
Host	smart-a32a3a9f-2fbc-427f-9950-9d65057bfa50
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183390663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.3183390663
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.38654604
Short name	T2245
Test name
Test status
Simulation time	1084687038 ps
CPU time	49.3 seconds
Started	May 23 04:24:45 PM PDT 24
Finished	May 23 04:25:36 PM PDT 24
Peak memory	571852 kb
Host	smart-45e1c3c3-6f85-4122-b661-c7671f60060c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38654604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.38654604
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/14.chip_csr_rw.51049966
Short name	T2633
Test name
Test status
Simulation time	4153920232 ps
CPU time	301.82 seconds
Started	May 23 04:25:12 PM PDT 24
Finished	May 23 04:30:16 PM PDT 24
Peak memory	592828 kb
Host	smart-6aea8528-7f7a-4873-a2f4-6ec6d1dc5241
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51049966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.51049966
Directory	/workspace/14.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1930355669
Short name	T2309
Test name
Test status
Simulation time	17115439468 ps
CPU time	1888.1 seconds
Started	May 23 04:24:56 PM PDT 24
Finished	May 23 04:56:25 PM PDT 24
Peak memory	586528 kb
Host	smart-457f2014-02b1-4e15-8aa7-34758266541f
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930355669 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.1930355669
Directory	/workspace/14.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.chip_tl_errors.154097734
Short name	T526
Test name
Test status
Simulation time	3423005541 ps
CPU time	233.69 seconds
Started	May 23 04:25:01 PM PDT 24
Finished	May 23 04:28:56 PM PDT 24
Peak memory	594140 kb
Host	smart-d9077a18-6c45-4521-a468-52a0ef512331
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154097734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.154097734
Directory	/workspace/14.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2426602951
Short name	T2304
Test name
Test status
Simulation time	460146852 ps
CPU time	29.12 seconds
Started	May 23 04:25:11 PM PDT 24
Finished	May 23 04:25:41 PM PDT 24
Peak memory	571808 kb
Host	smart-e4c560a4-bac0-4b3a-b706-af45f64ecc81
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426602951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .2426602951
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.422085345
Short name	T777
Test name
Test status
Simulation time	120715913989 ps
CPU time	2043.07 seconds
Started	May 23 04:25:11 PM PDT 24
Finished	May 23 04:59:16 PM PDT 24
Peak memory	572064 kb
Host	smart-d3b03176-7572-466f-9f6a-974222ce8897
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422085345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_d evice_slow_rsp.422085345
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.4246906883
Short name	T1703
Test name
Test status
Simulation time	636895213 ps
CPU time	29.66 seconds
Started	May 23 04:25:12 PM PDT 24
Finished	May 23 04:25:43 PM PDT 24
Peak memory	571844 kb
Host	smart-3ba41122-2c5a-4b6d-977f-61b57b55f0b8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246906883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.4246906883
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_error_random.2777653481
Short name	T1681
Test name
Test status
Simulation time	1795743280 ps
CPU time	71.08 seconds
Started	May 23 04:25:12 PM PDT 24
Finished	May 23 04:26:25 PM PDT 24
Peak memory	571820 kb
Host	smart-957a5b4e-b88b-4a3c-80da-0e1889cd0f4a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777653481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2777653481
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_random.3481035043
Short name	T2032
Test name
Test status
Simulation time	319312471 ps
CPU time	31.86 seconds
Started	May 23 04:25:01 PM PDT 24
Finished	May 23 04:25:34 PM PDT 24
Peak memory	571768 kb
Host	smart-ea2e9542-acb1-4e0c-8a74-a71de5058384
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481035043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.3481035043
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1032224516
Short name	T408
Test name
Test status
Simulation time	43366448618 ps
CPU time	472.16 seconds
Started	May 23 04:25:13 PM PDT 24
Finished	May 23 04:33:06 PM PDT 24
Peak memory	572052 kb
Host	smart-a7cb2088-8cf8-4287-baef-644a7ee3eea8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032224516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1032224516
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3249619506
Short name	T2565
Test name
Test status
Simulation time	15367817392 ps
CPU time	299.49 seconds
Started	May 23 04:25:11 PM PDT 24
Finished	May 23 04:30:12 PM PDT 24
Peak memory	572000 kb
Host	smart-87ce3a5e-7f82-4f76-b8ca-48fff96be91a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249619506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3249619506
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.605890676
Short name	T2662
Test name
Test status
Simulation time	387450683 ps
CPU time	42.44 seconds
Started	May 23 04:25:11 PM PDT 24
Finished	May 23 04:25:55 PM PDT 24
Peak memory	571856 kb
Host	smart-a927b3d3-735c-4106-8c1d-c6a9692c6984
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605890676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_dela ys.605890676
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_same_source.2727500773
Short name	T545
Test name
Test status
Simulation time	364039898 ps
CPU time	31.52 seconds
Started	May 23 04:25:11 PM PDT 24
Finished	May 23 04:25:44 PM PDT 24
Peak memory	571764 kb
Host	smart-caef57cd-45ad-4053-a224-777ef1e045ef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727500773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2727500773
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke.3664609267
Short name	T1599
Test name
Test status
Simulation time	190075582 ps
CPU time	9.05 seconds
Started	May 23 04:24:57 PM PDT 24
Finished	May 23 04:25:06 PM PDT 24
Peak memory	563548 kb
Host	smart-ad8b206d-b6cd-4ef3-a742-52380a4823d5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664609267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3664609267
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.842815380
Short name	T1516
Test name
Test status
Simulation time	8435103223 ps
CPU time	85.87 seconds
Started	May 23 04:24:56 PM PDT 24
Finished	May 23 04:26:23 PM PDT 24
Peak memory	563732 kb
Host	smart-a9a0c28e-70a5-4eaa-9c8b-d2f6ddabfcfa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842815380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.842815380
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.266929562
Short name	T2659
Test name
Test status
Simulation time	5049640364 ps
CPU time	89.71 seconds
Started	May 23 04:24:56 PM PDT 24
Finished	May 23 04:26:27 PM PDT 24
Peak memory	563756 kb
Host	smart-8e43b8b5-54d1-4bae-aa2d-aaa990c29a2e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266929562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.266929562
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2549087585
Short name	T2527
Test name
Test status
Simulation time	50637781 ps
CPU time	6.97 seconds
Started	May 23 04:24:55 PM PDT 24
Finished	May 23 04:25:03 PM PDT 24
Peak memory	563516 kb
Host	smart-a4140058-3598-4cd7-aaed-1373658aedff
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549087585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.2549087585
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2637479459
Short name	T2273
Test name
Test status
Simulation time	182842150 ps
CPU time	16.31 seconds
Started	May 23 04:25:13 PM PDT 24
Finished	May 23 04:25:31 PM PDT 24
Peak memory	571840 kb
Host	smart-eb4710b8-4812-4b51-9261-d55d1cd060ad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637479459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2637479459
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2283943368
Short name	T1530
Test name
Test status
Simulation time	156662719 ps
CPU time	50.11 seconds
Started	May 23 04:25:12 PM PDT 24
Finished	May 23 04:26:03 PM PDT 24
Peak memory	572908 kb
Host	smart-84d2a591-4c6b-48a8-8930-07c024bd71a8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283943368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.2283943368
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1627262092
Short name	T2050
Test name
Test status
Simulation time	549255502 ps
CPU time	24.96 seconds
Started	May 23 04:25:12 PM PDT 24
Finished	May 23 04:25:38 PM PDT 24
Peak memory	571852 kb
Host	smart-66e3330c-3539-4d72-8980-f9f6240fc189
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627262092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1627262092
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/15.chip_csr_rw.3440763135
Short name	T2323
Test name
Test status
Simulation time	4418192360 ps
CPU time	312.77 seconds
Started	May 23 04:25:36 PM PDT 24
Finished	May 23 04:30:50 PM PDT 24
Peak memory	590988 kb
Host	smart-c2e30c95-2338-456c-a502-d071467f5d3a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440763135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.3440763135
Directory	/workspace/15.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1609091224
Short name	T349
Test name
Test status
Simulation time	17646479600 ps
CPU time	1554.07 seconds
Started	May 23 04:25:13 PM PDT 24
Finished	May 23 04:51:08 PM PDT 24
Peak memory	585940 kb
Host	smart-b54a0229-550e-48a7-b6e3-7a4bacf132b3
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609091224 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.1609091224
Directory	/workspace/15.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_access_same_device.2072202681
Short name	T2225
Test name
Test status
Simulation time	2833132462 ps
CPU time	141.74 seconds
Started	May 23 04:25:28 PM PDT 24
Finished	May 23 04:27:51 PM PDT 24
Peak memory	571904 kb
Host	smart-bb660498-8fb2-49b7-8c07-187be31c10da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072202681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .2072202681
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3834861339
Short name	T1555
Test name
Test status
Simulation time	52144671934 ps
CPU time	941.2 seconds
Started	May 23 04:25:28 PM PDT 24
Finished	May 23 04:41:10 PM PDT 24
Peak memory	572076 kb
Host	smart-b2226332-f219-49bb-8a75-f47a47c2b644
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834861339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3834861339
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.4293527160
Short name	T2340
Test name
Test status
Simulation time	390417245 ps
CPU time	20.94 seconds
Started	May 23 04:25:27 PM PDT 24
Finished	May 23 04:25:49 PM PDT 24
Peak memory	571812 kb
Host	smart-c58c16b5-d344-40e0-89d8-597c0da391a8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293527160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.4293527160
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_error_random.3416685362
Short name	T1686
Test name
Test status
Simulation time	443431292 ps
CPU time	20.21 seconds
Started	May 23 04:25:24 PM PDT 24
Finished	May 23 04:25:46 PM PDT 24
Peak memory	571772 kb
Host	smart-7f67f974-7116-42a8-be8d-88964f3b6809
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416685362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3416685362
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_random.3209183622
Short name	T1305
Test name
Test status
Simulation time	317768841 ps
CPU time	35.86 seconds
Started	May 23 04:25:24 PM PDT 24
Finished	May 23 04:26:02 PM PDT 24
Peak memory	571908 kb
Host	smart-779d45b9-58f2-402e-a41b-1d30969b4095
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209183622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3209183622
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2837804368
Short name	T1700
Test name
Test status
Simulation time	57478872261 ps
CPU time	634.11 seconds
Started	May 23 04:25:26 PM PDT 24
Finished	May 23 04:36:02 PM PDT 24
Peak memory	572032 kb
Host	smart-3e8ed9e9-c84e-47b2-9958-c1d795aaf9ce
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837804368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2837804368
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1668644199
Short name	T1492
Test name
Test status
Simulation time	470601956 ps
CPU time	47.1 seconds
Started	May 23 04:25:25 PM PDT 24
Finished	May 23 04:26:14 PM PDT 24
Peak memory	571804 kb
Host	smart-e558e8ee-dc2b-4fa4-b5cc-f063bf65b6e7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668644199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.1668644199
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_same_source.3684479933
Short name	T1937
Test name
Test status
Simulation time	1847209455 ps
CPU time	66.1 seconds
Started	May 23 04:25:28 PM PDT 24
Finished	May 23 04:26:35 PM PDT 24
Peak memory	571784 kb
Host	smart-2542ba7a-b056-4f2a-8c23-9ddd7fda554c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684479933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3684479933
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke.2978322263
Short name	T1571
Test name
Test status
Simulation time	47127936 ps
CPU time	6.86 seconds
Started	May 23 04:25:14 PM PDT 24
Finished	May 23 04:25:21 PM PDT 24
Peak memory	563560 kb
Host	smart-af7e6f14-5da0-479c-9a57-9d5ba119b6b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978322263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2978322263
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.4272556308
Short name	T1782
Test name
Test status
Simulation time	8590255774 ps
CPU time	100.47 seconds
Started	May 23 04:25:36 PM PDT 24
Finished	May 23 04:27:18 PM PDT 24
Peak memory	563828 kb
Host	smart-0670a8a3-107d-4cc2-ae44-fa3675b286fd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272556308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.4272556308
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1098558686
Short name	T1584
Test name
Test status
Simulation time	3669822349 ps
CPU time	68.38 seconds
Started	May 23 04:25:25 PM PDT 24
Finished	May 23 04:26:35 PM PDT 24
Peak memory	563760 kb
Host	smart-c7cef02d-4e19-4074-8b7d-027da6f5c080
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098558686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1098558686
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.447522623
Short name	T1764
Test name
Test status
Simulation time	51039572 ps
CPU time	7.11 seconds
Started	May 23 04:25:24 PM PDT 24
Finished	May 23 04:25:32 PM PDT 24
Peak memory	563556 kb
Host	smart-214f3eea-d8ef-4c37-aa49-6cbcb00077e4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447522623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays .447522623
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all.3301546819
Short name	T420
Test name
Test status
Simulation time	11089589962 ps
CPU time	455.72 seconds
Started	May 23 04:25:28 PM PDT 24
Finished	May 23 04:33:05 PM PDT 24
Peak memory	572988 kb
Host	smart-2fbeee76-f535-4cf2-ba31-c0ba78eea144
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301546819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3301546819
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.2536686476
Short name	T1872
Test name
Test status
Simulation time	1261065845 ps
CPU time	103.5 seconds
Started	May 23 04:25:25 PM PDT 24
Finished	May 23 04:27:10 PM PDT 24
Peak memory	571828 kb
Host	smart-2290ad03-e444-4181-9ef3-08a2f4a78d8e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536686476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2536686476
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.956484748
Short name	T2590
Test name
Test status
Simulation time	158273010 ps
CPU time	93.28 seconds
Started	May 23 04:25:25 PM PDT 24
Finished	May 23 04:27:00 PM PDT 24
Peak memory	573312 kb
Host	smart-17972585-3a35-4cf7-b7cf-59c3cd3d0112
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956484748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_ with_rand_reset.956484748
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1243197100
Short name	T2422
Test name
Test status
Simulation time	125175888 ps
CPU time	28.52 seconds
Started	May 23 04:25:36 PM PDT 24
Finished	May 23 04:26:07 PM PDT 24
Peak memory	571896 kb
Host	smart-7da2fbf0-20f2-45ad-86d6-88237bb15192
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243197100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.1243197100
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2665915431
Short name	T1500
Test name
Test status
Simulation time	332365642 ps
CPU time	42.2 seconds
Started	May 23 04:25:28 PM PDT 24
Finished	May 23 04:26:11 PM PDT 24
Peak memory	571876 kb
Host	smart-e0f19eeb-86db-48ab-b0c6-af4f793abbe6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665915431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2665915431
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/16.chip_csr_rw.3204573207
Short name	T2343
Test name
Test status
Simulation time	5385770825 ps
CPU time	604.32 seconds
Started	May 23 04:25:53 PM PDT 24
Finished	May 23 04:35:58 PM PDT 24
Peak memory	591152 kb
Host	smart-c76aea88-847e-4c95-a711-a9f74e4289b3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204573207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3204573207
Directory	/workspace/16.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2725567705
Short name	T2175
Test name
Test status
Simulation time	32487411359 ps
CPU time	3337.4 seconds
Started	May 23 04:25:43 PM PDT 24
Finished	May 23 05:21:21 PM PDT 24
Peak memory	587076 kb
Host	smart-a9e8f24b-76db-46a8-bb2c-e77ed7b076ac
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725567705 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.2725567705
Directory	/workspace/16.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.chip_tl_errors.1229309509
Short name	T632
Test name
Test status
Simulation time	4876377362 ps
CPU time	444.56 seconds
Started	May 23 04:25:38 PM PDT 24
Finished	May 23 04:33:04 PM PDT 24
Peak memory	594028 kb
Host	smart-999d1288-ba0a-4e4e-a552-bdedf5e3b4f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229309509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.1229309509
Directory	/workspace/16.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_access_same_device.1560322251
Short name	T2782
Test name
Test status
Simulation time	2101295821 ps
CPU time	89.92 seconds
Started	May 23 04:25:40 PM PDT 24
Finished	May 23 04:27:11 PM PDT 24
Peak memory	571868 kb
Host	smart-1a4b552c-e7dc-4453-bfe0-21a9f132d206
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560322251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .1560322251
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.4266093997
Short name	T1964
Test name
Test status
Simulation time	54135295416 ps
CPU time	1051.15 seconds
Started	May 23 04:25:37 PM PDT 24
Finished	May 23 04:43:11 PM PDT 24
Peak memory	572008 kb
Host	smart-7eedb3ca-72cd-4028-9aee-3875dda75afc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266093997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.4266093997
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.971340178
Short name	T2181
Test name
Test status
Simulation time	1312399875 ps
CPU time	61.86 seconds
Started	May 23 04:25:51 PM PDT 24
Finished	May 23 04:26:54 PM PDT 24
Peak memory	571800 kb
Host	smart-754df7af-5a70-4dcc-a5d4-91949f046661
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971340178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr .971340178
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_error_random.1060264160
Short name	T2096
Test name
Test status
Simulation time	2485114248 ps
CPU time	85.21 seconds
Started	May 23 04:26:03 PM PDT 24
Finished	May 23 04:27:30 PM PDT 24
Peak memory	571852 kb
Host	smart-b344c47b-845b-4eb4-bdc7-bebe1fd9d4d4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060264160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1060264160
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_random.2170676439
Short name	T2204
Test name
Test status
Simulation time	237524487 ps
CPU time	12.85 seconds
Started	May 23 04:25:39 PM PDT 24
Finished	May 23 04:25:54 PM PDT 24
Peak memory	563520 kb
Host	smart-42ae9e83-ca49-41d6-b340-85a339fae5f8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170676439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.2170676439
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2813985527
Short name	T620
Test name
Test status
Simulation time	28022590429 ps
CPU time	308.55 seconds
Started	May 23 04:25:37 PM PDT 24
Finished	May 23 04:30:48 PM PDT 24
Peak memory	571992 kb
Host	smart-aa331325-3230-432d-ace8-845cf78c0947
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813985527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2813985527
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1156723108
Short name	T2209
Test name
Test status
Simulation time	54949871181 ps
CPU time	998.53 seconds
Started	May 23 04:25:39 PM PDT 24
Finished	May 23 04:42:19 PM PDT 24
Peak memory	572032 kb
Host	smart-38de81c2-1e9b-419f-a203-74718e1f6fe9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156723108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1156723108
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_same_source.492944262
Short name	T1921
Test name
Test status
Simulation time	503669986 ps
CPU time	35.09 seconds
Started	May 23 04:26:03 PM PDT 24
Finished	May 23 04:26:40 PM PDT 24
Peak memory	571720 kb
Host	smart-6b8bc7fc-bd9b-47a1-ace2-7ba8a1d53cca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492944262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.492944262
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke.377305954
Short name	T1857
Test name
Test status
Simulation time	228218544 ps
CPU time	10.74 seconds
Started	May 23 04:25:37 PM PDT 24
Finished	May 23 04:25:50 PM PDT 24
Peak memory	563556 kb
Host	smart-9ead2d98-242f-447a-a385-e1a95b9919fb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377305954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.377305954
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2573523464
Short name	T2625
Test name
Test status
Simulation time	10442215935 ps
CPU time	109.6 seconds
Started	May 23 04:25:38 PM PDT 24
Finished	May 23 04:27:29 PM PDT 24
Peak memory	563796 kb
Host	smart-9c4d4e48-45f9-42e5-afdf-e8a4f8694a9a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573523464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2573523464
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.3465570170
Short name	T2732
Test name
Test status
Simulation time	5193779000 ps
CPU time	92.35 seconds
Started	May 23 04:25:39 PM PDT 24
Finished	May 23 04:27:13 PM PDT 24
Peak memory	563772 kb
Host	smart-112e6318-46de-479f-a00c-596cb09fa86e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465570170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3465570170
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.996695888
Short name	T1870
Test name
Test status
Simulation time	55402170 ps
CPU time	6.97 seconds
Started	May 23 04:25:35 PM PDT 24
Finished	May 23 04:25:44 PM PDT 24
Peak memory	563512 kb
Host	smart-69520815-a498-4d92-b6a3-d0de6a423800
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996695888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays .996695888
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all.2336508716
Short name	T2665
Test name
Test status
Simulation time	10007432319 ps
CPU time	444.11 seconds
Started	May 23 04:25:51 PM PDT 24
Finished	May 23 04:33:16 PM PDT 24
Peak memory	573024 kb
Host	smart-857a8e18-9c14-4fe5-b575-de9e72a7e447
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336508716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2336508716
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1272713093
Short name	T1824
Test name
Test status
Simulation time	4056287531 ps
CPU time	174.27 seconds
Started	May 23 04:25:53 PM PDT 24
Finished	May 23 04:28:49 PM PDT 24
Peak memory	572000 kb
Host	smart-7ce515c1-4df2-4e46-836e-ba990ce89a48
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272713093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1272713093
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.188611548
Short name	T2585
Test name
Test status
Simulation time	650558947 ps
CPU time	282.99 seconds
Started	May 23 04:25:53 PM PDT 24
Finished	May 23 04:30:37 PM PDT 24
Peak memory	573940 kb
Host	smart-e6fd1896-3535-4128-bfcb-daf63aded75d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188611548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_ with_rand_reset.188611548
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.4027105377
Short name	T802
Test name
Test status
Simulation time	718759217 ps
CPU time	174.99 seconds
Started	May 23 04:26:03 PM PDT 24
Finished	May 23 04:28:59 PM PDT 24
Peak memory	574956 kb
Host	smart-662bc671-6470-42c1-aab0-d5d7fd85868e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027105377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.4027105377
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.4023442464
Short name	T1582
Test name
Test status
Simulation time	542128405 ps
CPU time	27.72 seconds
Started	May 23 04:25:53 PM PDT 24
Finished	May 23 04:26:21 PM PDT 24
Peak memory	571816 kb
Host	smart-bced344b-5e13-446a-8d47-7ccf535f8a6f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023442464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.4023442464
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/17.chip_csr_rw.2414745393
Short name	T1761
Test name
Test status
Simulation time	5281393689 ps
CPU time	709.3 seconds
Started	May 23 04:26:18 PM PDT 24
Finished	May 23 04:38:09 PM PDT 24
Peak memory	591084 kb
Host	smart-7ddc5fe3-8ced-4dc8-86e3-6a26824bd67f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414745393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2414745393
Directory	/workspace/17.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1265467366
Short name	T381
Test name
Test status
Simulation time	14362616383 ps
CPU time	1572.7 seconds
Started	May 23 04:26:05 PM PDT 24
Finished	May 23 04:52:18 PM PDT 24
Peak memory	585864 kb
Host	smart-b58263a4-5301-4f81-8237-3e03d06674b0
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265467366 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1265467366
Directory	/workspace/17.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.chip_tl_errors.2537642434
Short name	T2156
Test name
Test status
Simulation time	2490354956 ps
CPU time	110.8 seconds
Started	May 23 04:26:20 PM PDT 24
Finished	May 23 04:28:13 PM PDT 24
Peak memory	594008 kb
Host	smart-d6ca11b6-e0d0-4b18-941f-99af0fc04685
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537642434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2537642434
Directory	/workspace/17.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_access_same_device.3690570367
Short name	T1944
Test name
Test status
Simulation time	2966819116 ps
CPU time	157.76 seconds
Started	May 23 04:26:04 PM PDT 24
Finished	May 23 04:28:43 PM PDT 24
Peak memory	571876 kb
Host	smart-2159241b-8eac-4491-824b-b619c136181d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690570367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .3690570367
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3308713548
Short name	T2350
Test name
Test status
Simulation time	137864217221 ps
CPU time	2053.46 seconds
Started	May 23 04:26:19 PM PDT 24
Finished	May 23 05:00:34 PM PDT 24
Peak memory	572012 kb
Host	smart-f8094406-bf17-4893-9601-ff2bb189ed81
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308713548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.3308713548
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.445048049
Short name	T2038
Test name
Test status
Simulation time	273731441 ps
CPU time	33.94 seconds
Started	May 23 04:26:20 PM PDT 24
Finished	May 23 04:26:55 PM PDT 24
Peak memory	571852 kb
Host	smart-a1c25a1a-d4d9-4d7b-8aaa-8a28dcbe4e4e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445048049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr .445048049
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_error_random.2300319377
Short name	T2338
Test name
Test status
Simulation time	1030107052 ps
CPU time	39.53 seconds
Started	May 23 04:26:20 PM PDT 24
Finished	May 23 04:27:01 PM PDT 24
Peak memory	571796 kb
Host	smart-41a4e441-cbf9-4319-a9ae-249cf262037a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300319377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2300319377
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_random.839457281
Short name	T613
Test name
Test status
Simulation time	163232646 ps
CPU time	18.82 seconds
Started	May 23 04:26:05 PM PDT 24
Finished	May 23 04:26:25 PM PDT 24
Peak memory	571800 kb
Host	smart-a0adabca-b444-4b96-8953-f74642164e24
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839457281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.839457281
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.4076285288
Short name	T1885
Test name
Test status
Simulation time	76270581436 ps
CPU time	785.63 seconds
Started	May 23 04:26:19 PM PDT 24
Finished	May 23 04:39:27 PM PDT 24
Peak memory	571960 kb
Host	smart-f1de0a9c-7aea-48b4-a694-a8081b464dbd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076285288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4076285288
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1458813155
Short name	T2012
Test name
Test status
Simulation time	41403239060 ps
CPU time	780.32 seconds
Started	May 23 04:26:05 PM PDT 24
Finished	May 23 04:39:06 PM PDT 24
Peak memory	572012 kb
Host	smart-466a6537-66c3-4415-8112-f433558e3916
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458813155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1458813155
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.1677678305
Short name	T2289
Test name
Test status
Simulation time	165432566 ps
CPU time	17.98 seconds
Started	May 23 04:26:04 PM PDT 24
Finished	May 23 04:26:23 PM PDT 24
Peak memory	571712 kb
Host	smart-b34f740d-17cb-4035-b57c-ff1c3a652565
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677678305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.1677678305
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_same_source.1787759209
Short name	T1613
Test name
Test status
Simulation time	1843452157 ps
CPU time	64.32 seconds
Started	May 23 04:26:19 PM PDT 24
Finished	May 23 04:27:26 PM PDT 24
Peak memory	571836 kb
Host	smart-43b975aa-05bf-4898-97f1-c437bb1efae6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787759209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1787759209
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke.2600779815
Short name	T1996
Test name
Test status
Simulation time	231040266 ps
CPU time	9.9 seconds
Started	May 23 04:26:05 PM PDT 24
Finished	May 23 04:26:16 PM PDT 24
Peak memory	563552 kb
Host	smart-0756c2cc-3473-4bf5-8e13-3c77146d247d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600779815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2600779815
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2203606128
Short name	T1465
Test name
Test status
Simulation time	11091603439 ps
CPU time	109.34 seconds
Started	May 23 04:26:19 PM PDT 24
Finished	May 23 04:28:10 PM PDT 24
Peak memory	563724 kb
Host	smart-40dab6c7-ab80-4ad5-8085-263d02f30d2e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203606128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2203606128
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3088869449
Short name	T1744
Test name
Test status
Simulation time	3236576234 ps
CPU time	56.08 seconds
Started	May 23 04:26:07 PM PDT 24
Finished	May 23 04:27:04 PM PDT 24
Peak memory	563740 kb
Host	smart-b0c6ea5e-7aa1-4d7f-9c08-db8421ada74f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088869449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3088869449
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.4030466458
Short name	T2234
Test name
Test status
Simulation time	39527178 ps
CPU time	5.72 seconds
Started	May 23 04:26:19 PM PDT 24
Finished	May 23 04:26:27 PM PDT 24
Peak memory	563448 kb
Host	smart-40028866-5744-4c97-8ef6-2b29dcf6da9b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030466458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.4030466458
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all.2408082506
Short name	T2046
Test name
Test status
Simulation time	1336100887 ps
CPU time	129.1 seconds
Started	May 23 04:26:18 PM PDT 24
Finished	May 23 04:28:29 PM PDT 24
Peak memory	571912 kb
Host	smart-835c6aad-7b5b-4015-97a7-e35e2600cdce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408082506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2408082506
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.208195546
Short name	T2039
Test name
Test status
Simulation time	578880985 ps
CPU time	23.69 seconds
Started	May 23 04:26:21 PM PDT 24
Finished	May 23 04:26:47 PM PDT 24
Peak memory	563680 kb
Host	smart-65925c34-2aaf-4767-b291-fdb85b32387e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208195546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.208195546
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.376901240
Short name	T1439
Test name
Test status
Simulation time	7848729777 ps
CPU time	560.34 seconds
Started	May 23 04:26:21 PM PDT 24
Finished	May 23 04:35:43 PM PDT 24
Peak memory	573072 kb
Host	smart-199fe432-bfe4-4f1d-b409-cbea8323a2c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376901240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_ with_rand_reset.376901240
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2269648144
Short name	T2007
Test name
Test status
Simulation time	110016315 ps
CPU time	63.83 seconds
Started	May 23 04:26:21 PM PDT 24
Finished	May 23 04:27:27 PM PDT 24
Peak memory	572068 kb
Host	smart-fc667ae8-c331-4212-84e5-f76b1d7d52e2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269648144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.2269648144
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.2033390841
Short name	T1992
Test name
Test status
Simulation time	368591775 ps
CPU time	19.27 seconds
Started	May 23 04:26:21 PM PDT 24
Finished	May 23 04:26:42 PM PDT 24
Peak memory	571832 kb
Host	smart-5bae70d3-2ee1-45d1-8254-9ecceb0f7eb5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033390841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2033390841
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/18.chip_csr_rw.1282635246
Short name	T2006
Test name
Test status
Simulation time	5711444737 ps
CPU time	514.45 seconds
Started	May 23 04:26:58 PM PDT 24
Finished	May 23 04:35:34 PM PDT 24
Peak memory	592528 kb
Host	smart-b55b8c90-6f97-47ae-8aef-b99809e8440b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282635246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.1282635246
Directory	/workspace/18.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.628825942
Short name	T352
Test name
Test status
Simulation time	14864354488 ps
CPU time	2056.42 seconds
Started	May 23 04:26:19 PM PDT 24
Finished	May 23 05:00:37 PM PDT 24
Peak memory	586416 kb
Host	smart-429211b6-f00a-44ad-9f61-52356b404e31
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628825942 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.chip_same_csr_outstanding.628825942
Directory	/workspace/18.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.chip_tl_errors.2508987825
Short name	T1906
Test name
Test status
Simulation time	3723564808 ps
CPU time	208.35 seconds
Started	May 23 04:26:19 PM PDT 24
Finished	May 23 04:29:49 PM PDT 24
Peak memory	602200 kb
Host	smart-7a8d8470-ae41-47e7-b998-88315b7de554
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508987825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.2508987825
Directory	/workspace/18.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_access_same_device.3633162801
Short name	T2610
Test name
Test status
Simulation time	1732895543 ps
CPU time	82.41 seconds
Started	May 23 04:26:38 PM PDT 24
Finished	May 23 04:28:01 PM PDT 24
Peak memory	571772 kb
Host	smart-1288ceb2-6564-44e7-bd3b-1f64cc5904c3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633162801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .3633162801
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2867114161
Short name	T2389
Test name
Test status
Simulation time	8924748366 ps
CPU time	150.1 seconds
Started	May 23 04:26:38 PM PDT 24
Finished	May 23 04:29:09 PM PDT 24
Peak memory	563828 kb
Host	smart-27a7963f-9ed8-4edc-8fb5-5db9da7796f8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867114161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.2867114161
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.505016913
Short name	T1806
Test name
Test status
Simulation time	104526380 ps
CPU time	14.4 seconds
Started	May 23 04:26:35 PM PDT 24
Finished	May 23 04:26:51 PM PDT 24
Peak memory	571856 kb
Host	smart-a34c540c-fb63-4d78-bcab-dd3735b90e4f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505016913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr .505016913
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_error_random.347146183
Short name	T1662
Test name
Test status
Simulation time	215560895 ps
CPU time	13.93 seconds
Started	May 23 04:26:37 PM PDT 24
Finished	May 23 04:26:52 PM PDT 24
Peak memory	563628 kb
Host	smart-d592da91-a72f-409e-ba78-30da24bbb287
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347146183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.347146183
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_random.1219762455
Short name	T1456
Test name
Test status
Simulation time	1673450365 ps
CPU time	68.95 seconds
Started	May 23 04:26:35 PM PDT 24
Finished	May 23 04:27:45 PM PDT 24
Peak memory	571844 kb
Host	smart-75b4e553-f96d-45c8-8705-b71a4f315147
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219762455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.1219762455
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_random_large_delays.3357548601
Short name	T2145
Test name
Test status
Simulation time	48708865847 ps
CPU time	525.62 seconds
Started	May 23 04:26:39 PM PDT 24
Finished	May 23 04:35:26 PM PDT 24
Peak memory	572048 kb
Host	smart-9b12b77c-dcce-4989-8a85-d3e2e62a1ef3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357548601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3357548601
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1693512147
Short name	T2669
Test name
Test status
Simulation time	32936689636 ps
CPU time	654.36 seconds
Started	May 23 04:26:36 PM PDT 24
Finished	May 23 04:37:32 PM PDT 24
Peak memory	572012 kb
Host	smart-2bb5e9fe-0988-4203-90d8-f44064c3280e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693512147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1693512147
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.4255396473
Short name	T405
Test name
Test status
Simulation time	475767611 ps
CPU time	44.98 seconds
Started	May 23 04:26:39 PM PDT 24
Finished	May 23 04:27:25 PM PDT 24
Peak memory	571776 kb
Host	smart-cc6a237b-2b83-4ad4-9050-f99d8f9f3cfd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255396473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.4255396473
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_same_source.61696255
Short name	T2751
Test name
Test status
Simulation time	239187135 ps
CPU time	18.29 seconds
Started	May 23 04:26:35 PM PDT 24
Finished	May 23 04:26:55 PM PDT 24
Peak memory	571836 kb
Host	smart-52c13ebe-dc35-41e7-a5d6-0d2bcaf8f3bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61696255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.61696255
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke.1159548699
Short name	T2529
Test name
Test status
Simulation time	165466245 ps
CPU time	8.52 seconds
Started	May 23 04:26:19 PM PDT 24
Finished	May 23 04:26:30 PM PDT 24
Peak memory	563512 kb
Host	smart-0da1cd23-104a-47c1-a321-97479c63205d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159548699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1159548699
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.626798841
Short name	T1337
Test name
Test status
Simulation time	9526965328 ps
CPU time	97.3 seconds
Started	May 23 04:26:22 PM PDT 24
Finished	May 23 04:28:02 PM PDT 24
Peak memory	563760 kb
Host	smart-178c2474-7083-466c-b2f9-8405d20e9f01
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626798841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.626798841
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3846477838
Short name	T1632
Test name
Test status
Simulation time	6706160768 ps
CPU time	118.83 seconds
Started	May 23 04:26:37 PM PDT 24
Finished	May 23 04:28:37 PM PDT 24
Peak memory	563788 kb
Host	smart-e5d60d97-3c16-4884-b0df-2c3ff23f0df6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846477838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3846477838
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1900942508
Short name	T1433
Test name
Test status
Simulation time	48894936 ps
CPU time	6.88 seconds
Started	May 23 04:26:19 PM PDT 24
Finished	May 23 04:26:28 PM PDT 24
Peak memory	563532 kb
Host	smart-500d7ce0-8032-4cd5-ad01-bd6eaae7787d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900942508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.1900942508
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all.2242535400
Short name	T2668
Test name
Test status
Simulation time	4392499474 ps
CPU time	389.77 seconds
Started	May 23 04:26:36 PM PDT 24
Finished	May 23 04:33:07 PM PDT 24
Peak memory	573096 kb
Host	smart-b5d298ab-9ab2-4df7-b373-d4c34615e598
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242535400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2242535400
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3409929162
Short name	T2792
Test name
Test status
Simulation time	3694168156 ps
CPU time	328.27 seconds
Started	May 23 04:26:59 PM PDT 24
Finished	May 23 04:32:29 PM PDT 24
Peak memory	572624 kb
Host	smart-94863d45-d11b-465d-80c7-9017f5bed7a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409929162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3409929162
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2101251153
Short name	T1648
Test name
Test status
Simulation time	10987502679 ps
CPU time	652.81 seconds
Started	May 23 04:26:37 PM PDT 24
Finished	May 23 04:37:30 PM PDT 24
Peak memory	573080 kb
Host	smart-cf0374c8-eb0d-46e1-a7db-0be484001c45
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101251153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.2101251153
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2420151201
Short name	T814
Test name
Test status
Simulation time	1941454107 ps
CPU time	274.39 seconds
Started	May 23 04:26:58 PM PDT 24
Finished	May 23 04:31:33 PM PDT 24
Peak memory	572992 kb
Host	smart-bd965254-2e67-4aeb-aee2-744ddc35f0f5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420151201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.2420151201
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.70610823
Short name	T1839
Test name
Test status
Simulation time	56149337 ps
CPU time	10.45 seconds
Started	May 23 04:26:40 PM PDT 24
Finished	May 23 04:26:51 PM PDT 24
Peak memory	563640 kb
Host	smart-581899d2-594d-468e-9a48-786a1637354b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70610823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.70610823
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/19.chip_csr_rw.771361729
Short name	T1920
Test name
Test status
Simulation time	3878869991 ps
CPU time	315.63 seconds
Started	May 23 04:27:09 PM PDT 24
Finished	May 23 04:32:26 PM PDT 24
Peak memory	590668 kb
Host	smart-62f777c7-e5f9-4c53-b047-652bcd224f3b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771361729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.771361729
Directory	/workspace/19.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.chip_tl_errors.4256670484
Short name	T1540
Test name
Test status
Simulation time	2506602590 ps
CPU time	91.99 seconds
Started	May 23 04:27:02 PM PDT 24
Finished	May 23 04:28:35 PM PDT 24
Peak memory	585856 kb
Host	smart-5702e602-34c9-47c3-85f0-718faa7ac270
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256670484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.4256670484
Directory	/workspace/19.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_access_same_device.887780621
Short name	T787
Test name
Test status
Simulation time	1982434888 ps
CPU time	91.76 seconds
Started	May 23 04:26:58 PM PDT 24
Finished	May 23 04:28:31 PM PDT 24
Peak memory	571852 kb
Host	smart-94b3df29-54d5-417b-95b2-87056162cedf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887780621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device. 887780621
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3922719108
Short name	T2581
Test name
Test status
Simulation time	120157726132 ps
CPU time	2005.95 seconds
Started	May 23 04:26:58 PM PDT 24
Finished	May 23 05:00:25 PM PDT 24
Peak memory	572044 kb
Host	smart-6f7024db-2be5-4954-81b6-438ff1487ab2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922719108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.3922719108
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.3691419154
Short name	T1457
Test name
Test status
Simulation time	921220352 ps
CPU time	42.28 seconds
Started	May 23 04:26:59 PM PDT 24
Finished	May 23 04:27:43 PM PDT 24
Peak memory	571824 kb
Host	smart-37d98eed-a791-4c52-b8c9-868a64ebb24f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691419154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.3691419154
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_error_random.2597173687
Short name	T2513
Test name
Test status
Simulation time	105666039 ps
CPU time	11.36 seconds
Started	May 23 04:27:01 PM PDT 24
Finished	May 23 04:27:13 PM PDT 24
Peak memory	571796 kb
Host	smart-5705ff23-db3c-4203-9687-44710b12912d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597173687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2597173687
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_random.350561710
Short name	T1383
Test name
Test status
Simulation time	416958981 ps
CPU time	40.97 seconds
Started	May 23 04:27:02 PM PDT 24
Finished	May 23 04:27:44 PM PDT 24
Peak memory	571744 kb
Host	smart-4a62da00-c2ef-433d-b513-6785c83ffc56
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350561710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.350561710
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_random_large_delays.260197657
Short name	T1668
Test name
Test status
Simulation time	24916349010 ps
CPU time	287.71 seconds
Started	May 23 04:26:58 PM PDT 24
Finished	May 23 04:31:47 PM PDT 24
Peak memory	572056 kb
Host	smart-64f217df-86b6-4510-9f32-9f7577275857
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260197657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.260197657
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2579740680
Short name	T2715
Test name
Test status
Simulation time	47016024895 ps
CPU time	837.17 seconds
Started	May 23 04:26:58 PM PDT 24
Finished	May 23 04:40:56 PM PDT 24
Peak memory	572028 kb
Host	smart-5ee14a27-4933-45cb-abb5-0dc5851a02f6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579740680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2579740680
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2417213119
Short name	T2480
Test name
Test status
Simulation time	296672694 ps
CPU time	27.21 seconds
Started	May 23 04:26:57 PM PDT 24
Finished	May 23 04:27:25 PM PDT 24
Peak memory	571768 kb
Host	smart-cde2932e-28dd-465b-b417-2bab8a768e83
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417213119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.2417213119
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_same_source.1166881139
Short name	T2497
Test name
Test status
Simulation time	1701495125 ps
CPU time	68.79 seconds
Started	May 23 04:26:59 PM PDT 24
Finished	May 23 04:28:10 PM PDT 24
Peak memory	571728 kb
Host	smart-c39e8828-99bd-4fee-9b0e-f4b17b9093b3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166881139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1166881139
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke.2982567175
Short name	T2776
Test name
Test status
Simulation time	183966963 ps
CPU time	9.82 seconds
Started	May 23 04:26:59 PM PDT 24
Finished	May 23 04:27:10 PM PDT 24
Peak memory	563548 kb
Host	smart-51676acf-ccbe-47db-aa7f-d4fa5311ea14
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982567175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2982567175
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.2825702254
Short name	T1462
Test name
Test status
Simulation time	6989802092 ps
CPU time	73.01 seconds
Started	May 23 04:26:59 PM PDT 24
Finished	May 23 04:28:13 PM PDT 24
Peak memory	563776 kb
Host	smart-b1d85704-e48e-49b3-91cb-67bf5f5ae00d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825702254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2825702254
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3093875466
Short name	T2459
Test name
Test status
Simulation time	6068317418 ps
CPU time	113.44 seconds
Started	May 23 04:26:58 PM PDT 24
Finished	May 23 04:28:53 PM PDT 24
Peak memory	563796 kb
Host	smart-f82724e6-3e56-4030-8e49-c7bfb2ac9d51
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093875466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3093875466
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.706920167
Short name	T1501
Test name
Test status
Simulation time	52927174 ps
CPU time	7.36 seconds
Started	May 23 04:26:59 PM PDT 24
Finished	May 23 04:27:08 PM PDT 24
Peak memory	563512 kb
Host	smart-ac1d8dbf-c912-4e66-9196-cde540073302
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706920167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays .706920167
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.4003476814
Short name	T2179
Test name
Test status
Simulation time	3242171515 ps
CPU time	302.61 seconds
Started	May 23 04:26:59 PM PDT 24
Finished	May 23 04:32:03 PM PDT 24
Peak memory	572040 kb
Host	smart-433f3599-907d-4eea-b4a5-9dff8316b015
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003476814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.4003476814
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2402370193
Short name	T2651
Test name
Test status
Simulation time	67029310 ps
CPU time	36.6 seconds
Started	May 23 04:26:59 PM PDT 24
Finished	May 23 04:27:37 PM PDT 24
Peak memory	563844 kb
Host	smart-32611b94-8f04-49e8-8371-bc773b2ddb86
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402370193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2402370193
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.661461522
Short name	T1709
Test name
Test status
Simulation time	1081356567 ps
CPU time	160.57 seconds
Started	May 23 04:27:10 PM PDT 24
Finished	May 23 04:29:51 PM PDT 24
Peak memory	572916 kb
Host	smart-965ac9e4-4ec3-4513-b2b0-0cbf76e12c5b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661461522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_reset_error.661461522
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.3446587408
Short name	T498
Test name
Test status
Simulation time	573756548 ps
CPU time	28.09 seconds
Started	May 23 04:26:58 PM PDT 24
Finished	May 23 04:27:27 PM PDT 24
Peak memory	571856 kb
Host	smart-a97dca81-0075-49f7-a4d9-681c02848f9c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446587408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3446587408
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1962794136
Short name	T2724
Test name
Test status
Simulation time	41207586640 ps
CPU time	3624.38 seconds
Started	May 23 04:17:26 PM PDT 24
Finished	May 23 05:17:52 PM PDT 24
Peak memory	586112 kb
Host	smart-0ecb3c46-e7f1-45d3-b1cf-41c52b413191
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962794136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.1962794136
Directory	/workspace/2.chip_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1997802710
Short name	T161
Test name
Test status
Simulation time	5172040689 ps
CPU time	273.72 seconds
Started	May 23 04:18:25 PM PDT 24
Finished	May 23 04:22:59 PM PDT 24
Peak memory	651824 kb
Host	smart-f90e6830-b59e-4afa-b9cd-ea0ab0bcee50
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997802710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.1997802710
Directory	/workspace/2.chip_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_csr_rw.3661548635
Short name	T2777
Test name
Test status
Simulation time	4288750801 ps
CPU time	348.69 seconds
Started	May 23 04:18:42 PM PDT 24
Finished	May 23 04:24:32 PM PDT 24
Peak memory	590488 kb
Host	smart-6afb7b95-0f46-4be3-817e-47adc3439381
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661548635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3661548635
Directory	/workspace/2.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3946396477
Short name	T2017
Test name
Test status
Simulation time	12760093618 ps
CPU time	570.82 seconds
Started	May 23 04:17:33 PM PDT 24
Finished	May 23 04:27:04 PM PDT 24
Peak memory	583156 kb
Host	smart-9626160d-99bc-44f6-b59b-33147435678e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946396477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3946396477
Directory	/workspace/2.chip_prim_tl_access/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.4195960628
Short name	T1549
Test name
Test status
Simulation time	9580078676 ps
CPU time	337.7 seconds
Started	May 23 04:17:52 PM PDT 24
Finished	May 23 04:23:31 PM PDT 24
Peak memory	585720 kb
Host	smart-d0fe6afa-a19d-499b-aea8-6d3148063463
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195960628 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.4195960628
Directory	/workspace/2.chip_rv_dm_lc_disabled/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.34238395
Short name	T2128
Test name
Test status
Simulation time	27630185643 ps
CPU time	3083.12 seconds
Started	May 23 04:17:44 PM PDT 24
Finished	May 23 05:09:08 PM PDT 24
Peak memory	586764 kb
Host	smart-acd76672-7218-47eb-a403-f4c5e915778b
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34238395 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.chip_same_csr_outstanding.34238395
Directory	/workspace/2.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.chip_tl_errors.1480452198
Short name	T2298
Test name
Test status
Simulation time	5353895424 ps
CPU time	488.3 seconds
Started	May 23 04:17:41 PM PDT 24
Finished	May 23 04:25:50 PM PDT 24
Peak memory	594180 kb
Host	smart-5ee59983-1368-4280-af08-5373ce61fd19
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480452198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.1480452198
Directory	/workspace/2.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_access_same_device.43582492
Short name	T1889
Test name
Test status
Simulation time	431657404 ps
CPU time	42.04 seconds
Started	May 23 04:19:12 PM PDT 24
Finished	May 23 04:19:56 PM PDT 24
Peak memory	571808 kb
Host	smart-06a38d09-b988-4a02-80e3-7afdd7a01041
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43582492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.43582492
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.463552078
Short name	T2681
Test name
Test status
Simulation time	32940228626 ps
CPU time	580.7 seconds
Started	May 23 04:19:27 PM PDT 24
Finished	May 23 04:29:09 PM PDT 24
Peak memory	572060 kb
Host	smart-8dac78ff-57e8-4e3c-a9fd-c59e11efa500
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463552078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_de vice_slow_rsp.463552078
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1736714880
Short name	T1367
Test name
Test status
Simulation time	862638917 ps
CPU time	45.74 seconds
Started	May 23 04:18:32 PM PDT 24
Finished	May 23 04:19:18 PM PDT 24
Peak memory	571812 kb
Host	smart-fdd1ae1c-0890-4a6f-858d-3986b94cfe6f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736714880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .1736714880
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_error_random.2844734540
Short name	T1554
Test name
Test status
Simulation time	1639252282 ps
CPU time	63.46 seconds
Started	May 23 04:18:26 PM PDT 24
Finished	May 23 04:19:31 PM PDT 24
Peak memory	571804 kb
Host	smart-c94f2c42-b1a6-4691-9d32-43732d7ffcbc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844734540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2844734540
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_random.3555909925
Short name	T2534
Test name
Test status
Simulation time	1998252968 ps
CPU time	89.7 seconds
Started	May 23 04:17:55 PM PDT 24
Finished	May 23 04:19:25 PM PDT 24
Peak memory	571776 kb
Host	smart-69f24ee5-26f4-4dce-97ce-75ef883017c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555909925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.3555909925
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_random_large_delays.1814359320
Short name	T1837
Test name
Test status
Simulation time	86032209348 ps
CPU time	949.84 seconds
Started	May 23 04:18:23 PM PDT 24
Finished	May 23 04:34:14 PM PDT 24
Peak memory	571984 kb
Host	smart-3770b01f-917d-448a-8f54-724b2ec9c295
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814359320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1814359320
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1272421061
Short name	T2064
Test name
Test status
Simulation time	40634261701 ps
CPU time	684.52 seconds
Started	May 23 04:18:09 PM PDT 24
Finished	May 23 04:29:34 PM PDT 24
Peak memory	572048 kb
Host	smart-a403768d-ad0b-4a53-96fb-257291aafa8e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272421061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1272421061
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.714664584
Short name	T2396
Test name
Test status
Simulation time	292832339 ps
CPU time	32.87 seconds
Started	May 23 04:18:19 PM PDT 24
Finished	May 23 04:18:53 PM PDT 24
Peak memory	571792 kb
Host	smart-30d07993-6986-44ed-95a0-2d1dce9851de
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714664584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delay s.714664584
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_same_source.2089953245
Short name	T523
Test name
Test status
Simulation time	597928591 ps
CPU time	51.39 seconds
Started	May 23 04:18:24 PM PDT 24
Finished	May 23 04:19:16 PM PDT 24
Peak memory	571820 kb
Host	smart-35c95883-e318-4f8c-95a4-77d0e3c2cd83
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089953245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2089953245
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke.2093959689
Short name	T2716
Test name
Test status
Simulation time	224257267 ps
CPU time	11.43 seconds
Started	May 23 04:17:49 PM PDT 24
Finished	May 23 04:18:02 PM PDT 24
Peak memory	563572 kb
Host	smart-21c5f48c-ae86-4e64-8f18-e6bdac0fc868
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093959689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2093959689
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.4293324535
Short name	T2014
Test name
Test status
Simulation time	10220256011 ps
CPU time	118.47 seconds
Started	May 23 04:19:19 PM PDT 24
Finished	May 23 04:21:19 PM PDT 24
Peak memory	563764 kb
Host	smart-5978cd8d-688e-443e-8334-45922f838902
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293324535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4293324535
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3729203122
Short name	T1846
Test name
Test status
Simulation time	6196895130 ps
CPU time	120.99 seconds
Started	May 23 04:18:12 PM PDT 24
Finished	May 23 04:20:14 PM PDT 24
Peak memory	563748 kb
Host	smart-2c815c9d-ff98-47b5-8f59-413f3625bbfa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729203122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3729203122
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1847886680
Short name	T2408
Test name
Test status
Simulation time	40961920 ps
CPU time	7.18 seconds
Started	May 23 04:18:00 PM PDT 24
Finished	May 23 04:18:08 PM PDT 24
Peak memory	563480 kb
Host	smart-c4a8d238-5d41-458c-aed6-028e149997ac
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847886680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .1847886680
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all.1092887115
Short name	T1807
Test name
Test status
Simulation time	4671029524 ps
CPU time	241.09 seconds
Started	May 23 04:18:36 PM PDT 24
Finished	May 23 04:22:38 PM PDT 24
Peak memory	571964 kb
Host	smart-9056140b-cdf9-416f-ae83-e2baa9a8e86b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092887115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1092887115
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1648191917
Short name	T2384
Test name
Test status
Simulation time	12265657072 ps
CPU time	523.14 seconds
Started	May 23 04:18:53 PM PDT 24
Finished	May 23 04:27:37 PM PDT 24
Peak memory	573140 kb
Host	smart-8c6eb9b4-f07a-4a08-862f-2b29ac5a583e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648191917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1648191917
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3224164720
Short name	T2498
Test name
Test status
Simulation time	3637981398 ps
CPU time	352.41 seconds
Started	May 23 04:18:27 PM PDT 24
Finished	May 23 04:24:20 PM PDT 24
Peak memory	572920 kb
Host	smart-020d2097-f810-4175-b8ad-75969cc6ce3f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224164720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.3224164720
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1542242332
Short name	T1585
Test name
Test status
Simulation time	1209234227 ps
CPU time	246.07 seconds
Started	May 23 04:18:54 PM PDT 24
Finished	May 23 04:23:02 PM PDT 24
Peak memory	575064 kb
Host	smart-3401f2d1-6805-4e10-853d-83c6fc65d112
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542242332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.1542242332
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.4267352959
Short name	T1971
Test name
Test status
Simulation time	1253653184 ps
CPU time	72.3 seconds
Started	May 23 04:18:46 PM PDT 24
Finished	May 23 04:20:00 PM PDT 24
Peak memory	571824 kb
Host	smart-39835ce9-38e1-46ea-a6cd-9548db892d04
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267352959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.4267352959
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_access_same_device.4072646246
Short name	T2575
Test name
Test status
Simulation time	425042030 ps
CPU time	39.49 seconds
Started	May 23 04:27:15 PM PDT 24
Finished	May 23 04:27:55 PM PDT 24
Peak memory	571832 kb
Host	smart-c930c6f1-38b4-458c-b01f-6c2e320a89a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072646246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .4072646246
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1978144885
Short name	T1850
Test name
Test status
Simulation time	1227258559 ps
CPU time	56.32 seconds
Started	May 23 04:27:15 PM PDT 24
Finished	May 23 04:28:13 PM PDT 24
Peak memory	571816 kb
Host	smart-10640987-6993-4c87-add7-e7cfd54f3644
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978144885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.1978144885
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_error_random.3902729619
Short name	T1592
Test name
Test status
Simulation time	153935013 ps
CPU time	16.11 seconds
Started	May 23 04:27:09 PM PDT 24
Finished	May 23 04:27:25 PM PDT 24
Peak memory	571816 kb
Host	smart-165bd0e0-8b73-4141-b988-cdb8875d6888
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902729619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3902729619
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_random.160064506
Short name	T1350
Test name
Test status
Simulation time	177907716 ps
CPU time	20.93 seconds
Started	May 23 04:27:07 PM PDT 24
Finished	May 23 04:27:29 PM PDT 24
Peak memory	571832 kb
Host	smart-7d601aa4-ed37-4ea2-bc6e-65acf7821079
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160064506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.160064506
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3382400846
Short name	T1520
Test name
Test status
Simulation time	39612663620 ps
CPU time	409.59 seconds
Started	May 23 04:27:11 PM PDT 24
Finished	May 23 04:34:01 PM PDT 24
Peak memory	572028 kb
Host	smart-44c8b97f-af6f-48ef-84ec-9266c0aab792
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382400846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3382400846
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.4228798293
Short name	T2063
Test name
Test status
Simulation time	64605897780 ps
CPU time	1198.44 seconds
Started	May 23 04:27:13 PM PDT 24
Finished	May 23 04:47:12 PM PDT 24
Peak memory	572052 kb
Host	smart-26af6e08-cfd5-4394-bd7e-d5b6757b5e55
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228798293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.4228798293
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1788332075
Short name	T2230
Test name
Test status
Simulation time	120460298 ps
CPU time	16.01 seconds
Started	May 23 04:27:07 PM PDT 24
Finished	May 23 04:27:24 PM PDT 24
Peak memory	571788 kb
Host	smart-86b77948-7072-41c3-a5a8-f023f48327f7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788332075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1788332075
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_same_source.2005469453
Short name	T546
Test name
Test status
Simulation time	581297371 ps
CPU time	49.67 seconds
Started	May 23 04:27:08 PM PDT 24
Finished	May 23 04:27:58 PM PDT 24
Peak memory	571788 kb
Host	smart-e6afab4e-3972-4e8d-8f64-d1756f6add2a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005469453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2005469453
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke.1454239147
Short name	T1445
Test name
Test status
Simulation time	41416293 ps
CPU time	6.47 seconds
Started	May 23 04:27:08 PM PDT 24
Finished	May 23 04:27:15 PM PDT 24
Peak memory	563496 kb
Host	smart-7226920c-f8c4-4815-b637-167f1d8ffa26
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454239147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1454239147
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.4228165354
Short name	T1257
Test name
Test status
Simulation time	8761594631 ps
CPU time	93.09 seconds
Started	May 23 04:27:11 PM PDT 24
Finished	May 23 04:28:45 PM PDT 24
Peak memory	563728 kb
Host	smart-68714df4-344e-401a-9613-67a31f2ff304
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228165354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.4228165354
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.3955413750
Short name	T2334
Test name
Test status
Simulation time	4736984639 ps
CPU time	85.72 seconds
Started	May 23 04:27:15 PM PDT 24
Finished	May 23 04:28:41 PM PDT 24
Peak memory	563808 kb
Host	smart-e9e6c112-b6b4-4480-a4f6-735ed549b302
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955413750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3955413750
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.4024309159
Short name	T1287
Test name
Test status
Simulation time	56156608 ps
CPU time	7.43 seconds
Started	May 23 04:27:11 PM PDT 24
Finished	May 23 04:27:20 PM PDT 24
Peak memory	563504 kb
Host	smart-26def597-0b2f-4397-a02c-838715b7a43f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024309159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.4024309159
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all.2910445930
Short name	T2176
Test name
Test status
Simulation time	3367111536 ps
CPU time	281.25 seconds
Started	May 23 04:27:13 PM PDT 24
Finished	May 23 04:31:55 PM PDT 24
Peak memory	572888 kb
Host	smart-874e7c87-a88d-4bc8-b74e-937b1f564501
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910445930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2910445930
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1545002334
Short name	T2117
Test name
Test status
Simulation time	9215976000 ps
CPU time	332.79 seconds
Started	May 23 04:27:11 PM PDT 24
Finished	May 23 04:32:45 PM PDT 24
Peak memory	571980 kb
Host	smart-2b287673-3491-474f-b000-1e58df39080f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545002334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1545002334
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2019908299
Short name	T2010
Test name
Test status
Simulation time	714138186 ps
CPU time	239.85 seconds
Started	May 23 04:27:22 PM PDT 24
Finished	May 23 04:31:23 PM PDT 24
Peak memory	573996 kb
Host	smart-5833459d-e363-4505-9d9a-910de974b362
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019908299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.2019908299
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.3994293545
Short name	T1726
Test name
Test status
Simulation time	1347797337 ps
CPU time	67.84 seconds
Started	May 23 04:27:10 PM PDT 24
Finished	May 23 04:28:19 PM PDT 24
Peak memory	571788 kb
Host	smart-d1db760f-2b55-4b43-82ca-08871093464b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994293545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3994293545
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_access_same_device.404379738
Short name	T800
Test name
Test status
Simulation time	3017619055 ps
CPU time	141.11 seconds
Started	May 23 04:27:23 PM PDT 24
Finished	May 23 04:29:45 PM PDT 24
Peak memory	571952 kb
Host	smart-5214701b-b2e2-4c75-960d-1353aced90a9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404379738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device. 404379738
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.437031716
Short name	T2621
Test name
Test status
Simulation time	11229242119 ps
CPU time	212.94 seconds
Started	May 23 04:27:22 PM PDT 24
Finished	May 23 04:30:56 PM PDT 24
Peak memory	572040 kb
Host	smart-34a3235a-9577-4d61-8fc0-8760b2eae4cc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437031716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_d evice_slow_rsp.437031716
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2375184058
Short name	T2508
Test name
Test status
Simulation time	313734768 ps
CPU time	37.3 seconds
Started	May 23 04:27:23 PM PDT 24
Finished	May 23 04:28:01 PM PDT 24
Peak memory	571800 kb
Host	smart-53a15271-f970-4d86-ac44-99396a0b0cd7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375184058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.2375184058
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_error_random.3630726946
Short name	T1421
Test name
Test status
Simulation time	565132872 ps
CPU time	21.12 seconds
Started	May 23 04:27:24 PM PDT 24
Finished	May 23 04:27:46 PM PDT 24
Peak memory	571812 kb
Host	smart-cd2f8237-a14f-4d0c-977e-bc8f6707170d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630726946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3630726946
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_random.3947264513
Short name	T1987
Test name
Test status
Simulation time	294741448 ps
CPU time	14.16 seconds
Started	May 23 04:27:23 PM PDT 24
Finished	May 23 04:27:38 PM PDT 24
Peak memory	563624 kb
Host	smart-d45a179f-84a5-4bd3-bf65-cb3a5a68fd88
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947264513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3947264513
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1931290799
Short name	T2738
Test name
Test status
Simulation time	97143583370 ps
CPU time	1059.09 seconds
Started	May 23 04:27:22 PM PDT 24
Finished	May 23 04:45:02 PM PDT 24
Peak memory	572000 kb
Host	smart-a0832ab4-ea15-4292-95ff-b8774ae48fa5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931290799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1931290799
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.1711431166
Short name	T607
Test name
Test status
Simulation time	38566819606 ps
CPU time	707.42 seconds
Started	May 23 04:27:23 PM PDT 24
Finished	May 23 04:39:11 PM PDT 24
Peak memory	572060 kb
Host	smart-0df36476-95ae-41f1-bd32-3fe86f5e2360
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711431166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1711431166
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.747129185
Short name	T1606
Test name
Test status
Simulation time	565984269 ps
CPU time	52.4 seconds
Started	May 23 04:27:24 PM PDT 24
Finished	May 23 04:28:18 PM PDT 24
Peak memory	571712 kb
Host	smart-60c9202f-b0ec-46d8-9fc4-c900ff3ad16a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747129185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_dela ys.747129185
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_same_source.1834383548
Short name	T1627
Test name
Test status
Simulation time	2186383275 ps
CPU time	63.43 seconds
Started	May 23 04:27:24 PM PDT 24
Finished	May 23 04:28:29 PM PDT 24
Peak memory	571964 kb
Host	smart-160409d5-c666-4729-b273-cf6603e42f80
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834383548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1834383548
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke.2032340385
Short name	T1476
Test name
Test status
Simulation time	245742512 ps
CPU time	10.68 seconds
Started	May 23 04:27:23 PM PDT 24
Finished	May 23 04:27:34 PM PDT 24
Peak memory	563512 kb
Host	smart-0ab668c7-f218-400f-a60d-8d1730bb4b82
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032340385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2032340385
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.3754997082
Short name	T2483
Test name
Test status
Simulation time	8209704887 ps
CPU time	92.68 seconds
Started	May 23 04:27:26 PM PDT 24
Finished	May 23 04:28:59 PM PDT 24
Peak memory	563748 kb
Host	smart-c26c32f2-3c8d-443c-ae60-9175ba8306ee
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754997082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3754997082
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3197557233
Short name	T2453
Test name
Test status
Simulation time	4676553793 ps
CPU time	84.85 seconds
Started	May 23 04:27:25 PM PDT 24
Finished	May 23 04:28:51 PM PDT 24
Peak memory	563744 kb
Host	smart-ac1f14ef-ad41-47eb-8661-a28823db1ac5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197557233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3197557233
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2515316553
Short name	T662
Test name
Test status
Simulation time	51649336 ps
CPU time	7.37 seconds
Started	May 23 04:27:22 PM PDT 24
Finished	May 23 04:27:30 PM PDT 24
Peak memory	563568 kb
Host	smart-3088f450-2ffb-4b97-9d4e-b83c96668650
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515316553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.2515316553
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all.3932175350
Short name	T440
Test name
Test status
Simulation time	12577403668 ps
CPU time	524.34 seconds
Started	May 23 04:27:34 PM PDT 24
Finished	May 23 04:36:19 PM PDT 24
Peak memory	571996 kb
Host	smart-f5c7e992-fc16-4591-a225-049ba597b931
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932175350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3932175350
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3958663306
Short name	T1605
Test name
Test status
Simulation time	1541359124 ps
CPU time	133.34 seconds
Started	May 23 04:27:37 PM PDT 24
Finished	May 23 04:29:51 PM PDT 24
Peak memory	571852 kb
Host	smart-01803167-9106-4178-9317-6a89827132c6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958663306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3958663306
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1406289027
Short name	T2190
Test name
Test status
Simulation time	302260713 ps
CPU time	117.79 seconds
Started	May 23 04:27:36 PM PDT 24
Finished	May 23 04:29:34 PM PDT 24
Peak memory	572296 kb
Host	smart-574941cf-f8a0-4366-aa32-351a346e781f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406289027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.1406289027
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3866806800
Short name	T1479
Test name
Test status
Simulation time	5377526086 ps
CPU time	729.96 seconds
Started	May 23 04:27:36 PM PDT 24
Finished	May 23 04:39:47 PM PDT 24
Peak memory	579088 kb
Host	smart-6354483e-1d65-4d64-baa4-e15f15915a68
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866806800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.3866806800
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3564878794
Short name	T1451
Test name
Test status
Simulation time	44854432 ps
CPU time	8.33 seconds
Started	May 23 04:27:25 PM PDT 24
Finished	May 23 04:27:34 PM PDT 24
Peak memory	563680 kb
Host	smart-698c5e79-c996-47bf-8e24-0e704493b6b2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564878794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3564878794
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/22.chip_tl_errors.328096880
Short name	T2365
Test name
Test status
Simulation time	3591092456 ps
CPU time	202.98 seconds
Started	May 23 04:27:35 PM PDT 24
Finished	May 23 04:30:59 PM PDT 24
Peak memory	585924 kb
Host	smart-3fe7f2ac-ffdc-4749-b003-4861b1c648c7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328096880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.328096880
Directory	/workspace/22.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_access_same_device.660426495
Short name	T2685
Test name
Test status
Simulation time	419141931 ps
CPU time	32.17 seconds
Started	May 23 04:27:38 PM PDT 24
Finished	May 23 04:28:11 PM PDT 24
Peak memory	571844 kb
Host	smart-188e6218-c762-4931-ac06-75bec6e383b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660426495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device. 660426495
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2515677779
Short name	T2674
Test name
Test status
Simulation time	18690820949 ps
CPU time	327.88 seconds
Started	May 23 04:27:35 PM PDT 24
Finished	May 23 04:33:04 PM PDT 24
Peak memory	571992 kb
Host	smart-e56b976a-0b6a-4ef4-b541-04c26214a6ff
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515677779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.2515677779
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1960375822
Short name	T2056
Test name
Test status
Simulation time	179324675 ps
CPU time	23.69 seconds
Started	May 23 04:27:49 PM PDT 24
Finished	May 23 04:28:14 PM PDT 24
Peak memory	571752 kb
Host	smart-36d92deb-4c5a-4aee-8388-b1ef88e775aa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960375822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1960375822
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_error_random.1795242436
Short name	T2584
Test name
Test status
Simulation time	794425324 ps
CPU time	36.63 seconds
Started	May 23 04:27:49 PM PDT 24
Finished	May 23 04:28:27 PM PDT 24
Peak memory	571796 kb
Host	smart-b88a9cd0-17c1-4abe-9f80-5269cb03b25d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795242436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1795242436
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_random.2634523283
Short name	T1450
Test name
Test status
Simulation time	771212830 ps
CPU time	31.99 seconds
Started	May 23 04:27:35 PM PDT 24
Finished	May 23 04:28:08 PM PDT 24
Peak memory	571820 kb
Host	smart-06ac6d99-879c-497a-8cbe-7e0266721952
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634523283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.2634523283
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_random_large_delays.928968442
Short name	T2660
Test name
Test status
Simulation time	10933684868 ps
CPU time	117.9 seconds
Started	May 23 04:27:37 PM PDT 24
Finished	May 23 04:29:36 PM PDT 24
Peak memory	563824 kb
Host	smart-acd24726-9596-49e0-b0fe-fd5915376688
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928968442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.928968442
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.904676371
Short name	T434
Test name
Test status
Simulation time	54483317797 ps
CPU time	1004.98 seconds
Started	May 23 04:27:38 PM PDT 24
Finished	May 23 04:44:24 PM PDT 24
Peak memory	572024 kb
Host	smart-ddb30f01-4e73-449f-b420-2bdf427250f8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904676371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.904676371
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.534828701
Short name	T2406
Test name
Test status
Simulation time	501625537 ps
CPU time	51.71 seconds
Started	May 23 04:27:36 PM PDT 24
Finished	May 23 04:28:28 PM PDT 24
Peak memory	571828 kb
Host	smart-aadce6a4-5cf8-4d0d-99ef-268c4d874c4c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534828701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_dela ys.534828701
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_same_source.628149503
Short name	T2360
Test name
Test status
Simulation time	275986484 ps
CPU time	23.48 seconds
Started	May 23 04:27:48 PM PDT 24
Finished	May 23 04:28:12 PM PDT 24
Peak memory	571748 kb
Host	smart-023a1bc4-f89a-4c04-8125-fb045b2656e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628149503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.628149503
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke.3402086521
Short name	T1652
Test name
Test status
Simulation time	266863443 ps
CPU time	12.38 seconds
Started	May 23 04:27:35 PM PDT 24
Finished	May 23 04:27:49 PM PDT 24
Peak memory	563528 kb
Host	smart-81c9eaf6-cd5f-4f74-baa2-4e36c08e718f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402086521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3402086521
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.930068922
Short name	T1960
Test name
Test status
Simulation time	11443604846 ps
CPU time	120.54 seconds
Started	May 23 04:27:36 PM PDT 24
Finished	May 23 04:29:37 PM PDT 24
Peak memory	563744 kb
Host	smart-1b5ca56a-1518-4702-9970-e8db7b5ba145
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930068922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.930068922
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.1292095893
Short name	T1524
Test name
Test status
Simulation time	4714427470 ps
CPU time	78.28 seconds
Started	May 23 04:27:39 PM PDT 24
Finished	May 23 04:28:58 PM PDT 24
Peak memory	563772 kb
Host	smart-c2d61f6f-6b63-48fa-9c0b-cb6e503a48a9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292095893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1292095893
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2058078341
Short name	T1690
Test name
Test status
Simulation time	49633285 ps
CPU time	6.69 seconds
Started	May 23 04:27:35 PM PDT 24
Finished	May 23 04:27:43 PM PDT 24
Peak memory	563488 kb
Host	smart-2c7f9406-75be-4a29-afb5-5f2a930874a0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058078341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.2058078341
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all.631387505
Short name	T2420
Test name
Test status
Simulation time	498733314 ps
CPU time	37.76 seconds
Started	May 23 04:27:50 PM PDT 24
Finished	May 23 04:28:29 PM PDT 24
Peak memory	571784 kb
Host	smart-77a05bb8-a465-47d0-b053-fb01f61bfb78
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631387505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.631387505
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.2718503125
Short name	T634
Test name
Test status
Simulation time	4709600455 ps
CPU time	211.24 seconds
Started	May 23 04:27:49 PM PDT 24
Finished	May 23 04:31:22 PM PDT 24
Peak memory	572068 kb
Host	smart-901830d5-c36c-485c-b6bc-6a7aec5f68d1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718503125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2718503125
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2951474091
Short name	T1318
Test name
Test status
Simulation time	211703494 ps
CPU time	78.3 seconds
Started	May 23 04:27:50 PM PDT 24
Finished	May 23 04:29:10 PM PDT 24
Peak memory	572048 kb
Host	smart-56deadcb-00e1-46ca-ac6f-1227e6b3f2ae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951474091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.2951474091
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3608487191
Short name	T1741
Test name
Test status
Simulation time	27318533 ps
CPU time	25.22 seconds
Started	May 23 04:27:50 PM PDT 24
Finished	May 23 04:28:16 PM PDT 24
Peak memory	571940 kb
Host	smart-4a16a336-1095-41c6-9064-2a916d86773b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608487191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3608487191
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3549043922
Short name	T1531
Test name
Test status
Simulation time	328873923 ps
CPU time	45.67 seconds
Started	May 23 04:27:49 PM PDT 24
Finished	May 23 04:28:36 PM PDT 24
Peak memory	571888 kb
Host	smart-086790d1-e811-4df6-8772-b47a528163f3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549043922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3549043922
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/23.chip_tl_errors.866393389
Short name	T2316
Test name
Test status
Simulation time	5130640280 ps
CPU time	366.58 seconds
Started	May 23 04:27:49 PM PDT 24
Finished	May 23 04:33:57 PM PDT 24
Peak memory	594096 kb
Host	smart-3802d3dd-f809-4255-a01e-0b10b3265599
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866393389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.866393389
Directory	/workspace/23.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_access_same_device.62844109
Short name	T2426
Test name
Test status
Simulation time	1525462652 ps
CPU time	72.29 seconds
Started	May 23 04:28:02 PM PDT 24
Finished	May 23 04:29:16 PM PDT 24
Peak memory	571824 kb
Host	smart-aa149342-9971-4857-a527-5769727d0e25
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62844109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.62844109
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.1880217266
Short name	T2705
Test name
Test status
Simulation time	157110428 ps
CPU time	19.96 seconds
Started	May 23 04:28:03 PM PDT 24
Finished	May 23 04:28:25 PM PDT 24
Peak memory	571784 kb
Host	smart-4f29dd57-90ac-46cf-9d55-9c30d443963b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880217266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.1880217266
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_error_random.2404265422
Short name	T1338
Test name
Test status
Simulation time	32208935 ps
CPU time	6.4 seconds
Started	May 23 04:28:01 PM PDT 24
Finished	May 23 04:28:09 PM PDT 24
Peak memory	563500 kb
Host	smart-5152c096-e14e-48bc-85c5-64cb639b0feb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404265422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2404265422
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_random.2818064605
Short name	T1828
Test name
Test status
Simulation time	239841646 ps
CPU time	23.48 seconds
Started	May 23 04:27:49 PM PDT 24
Finished	May 23 04:28:14 PM PDT 24
Peak memory	571776 kb
Host	smart-62212a08-09c0-4591-b935-c61acf64b52e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818064605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2818064605
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2536289755
Short name	T2499
Test name
Test status
Simulation time	22247096276 ps
CPU time	261.47 seconds
Started	May 23 04:28:02 PM PDT 24
Finished	May 23 04:32:25 PM PDT 24
Peak memory	572056 kb
Host	smart-a91a2498-ba3f-4664-b726-100b07f2f8db
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536289755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2536289755
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.1105707728
Short name	T559
Test name
Test status
Simulation time	57196376165 ps
CPU time	992.68 seconds
Started	May 23 04:28:02 PM PDT 24
Finished	May 23 04:44:35 PM PDT 24
Peak memory	572068 kb
Host	smart-5133c15c-d970-440b-ba0c-da2978aeda14
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105707728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1105707728
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.1929645498
Short name	T1912
Test name
Test status
Simulation time	612991482 ps
CPU time	56.54 seconds
Started	May 23 04:27:50 PM PDT 24
Finished	May 23 04:28:48 PM PDT 24
Peak memory	571800 kb
Host	smart-8d6aa7da-a215-400a-977b-e9380a253f42
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929645498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.1929645498
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_same_source.3126038485
Short name	T539
Test name
Test status
Simulation time	896307094 ps
CPU time	29.89 seconds
Started	May 23 04:28:02 PM PDT 24
Finished	May 23 04:28:33 PM PDT 24
Peak memory	571788 kb
Host	smart-ca493f3f-993e-42f1-868c-e0820796a537
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126038485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3126038485
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke.1462234308
Short name	T2356
Test name
Test status
Simulation time	154810714 ps
CPU time	8.67 seconds
Started	May 23 04:27:49 PM PDT 24
Finished	May 23 04:27:59 PM PDT 24
Peak memory	563528 kb
Host	smart-8984aeb0-b0b9-43e5-bffe-f1ef9dcee83f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462234308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1462234308
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2844473306
Short name	T2279
Test name
Test status
Simulation time	8842748195 ps
CPU time	100.37 seconds
Started	May 23 04:27:52 PM PDT 24
Finished	May 23 04:29:33 PM PDT 24
Peak memory	563788 kb
Host	smart-086c8b09-cd70-4773-b6d2-e5075ee03359
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844473306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2844473306
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2616518674
Short name	T1983
Test name
Test status
Simulation time	4147207626 ps
CPU time	75.84 seconds
Started	May 23 04:27:53 PM PDT 24
Finished	May 23 04:29:09 PM PDT 24
Peak memory	563736 kb
Host	smart-33ce4e83-5cfb-4508-84f3-4c5179f4c482
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616518674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2616518674
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3753374798
Short name	T2092
Test name
Test status
Simulation time	51711743 ps
CPU time	6.62 seconds
Started	May 23 04:27:49 PM PDT 24
Finished	May 23 04:27:57 PM PDT 24
Peak memory	563544 kb
Host	smart-4414356c-d509-4694-95f1-a86fb77fd733
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753374798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.3753374798
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all.3993864302
Short name	T584
Test name
Test status
Simulation time	10008214599 ps
CPU time	432.12 seconds
Started	May 23 04:28:02 PM PDT 24
Finished	May 23 04:35:16 PM PDT 24
Peak memory	572912 kb
Host	smart-6f401dd3-9398-49d4-b6e7-57a772f3944e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993864302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3993864302
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2371822179
Short name	T1683
Test name
Test status
Simulation time	175109295 ps
CPU time	23.19 seconds
Started	May 23 04:28:03 PM PDT 24
Finished	May 23 04:28:28 PM PDT 24
Peak memory	571824 kb
Host	smart-6248eb80-f594-48c3-8032-dc90aaf13772
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371822179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2371822179
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3223560980
Short name	T1394
Test name
Test status
Simulation time	308749156 ps
CPU time	110.54 seconds
Started	May 23 04:28:04 PM PDT 24
Finished	May 23 04:29:56 PM PDT 24
Peak memory	572912 kb
Host	smart-76e659ad-1d94-4896-adc8-1ffeeec7a069
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223560980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.3223560980
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.3811612417
Short name	T618
Test name
Test status
Simulation time	89375880 ps
CPU time	14.11 seconds
Started	May 23 04:28:02 PM PDT 24
Finished	May 23 04:28:17 PM PDT 24
Peak memory	571816 kb
Host	smart-352c3b33-8750-4400-916b-ed13cc8f7303
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811612417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3811612417
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/24.chip_tl_errors.1448199551
Short name	T656
Test name
Test status
Simulation time	3979536680 ps
CPU time	294.13 seconds
Started	May 23 04:28:02 PM PDT 24
Finished	May 23 04:32:57 PM PDT 24
Peak memory	594056 kb
Host	smart-e001b7bb-e645-4344-8e1f-aa38501516de
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448199551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.1448199551
Directory	/workspace/24.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_access_same_device.972473444
Short name	T2461
Test name
Test status
Simulation time	2506682385 ps
CPU time	101.43 seconds
Started	May 23 04:28:15 PM PDT 24
Finished	May 23 04:29:58 PM PDT 24
Peak memory	571964 kb
Host	smart-3ef6a678-0dfc-40f2-9495-958dd17b871f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972473444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device. 972473444
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2319566625
Short name	T2016
Test name
Test status
Simulation time	129061649169 ps
CPU time	2231.42 seconds
Started	May 23 04:28:15 PM PDT 24
Finished	May 23 05:05:28 PM PDT 24
Peak memory	572012 kb
Host	smart-68d9fcd2-5c0e-43e9-a1df-1de9447f8883
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319566625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.2319566625
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2763829204
Short name	T2628
Test name
Test status
Simulation time	71730126 ps
CPU time	10.56 seconds
Started	May 23 04:28:15 PM PDT 24
Finished	May 23 04:28:27 PM PDT 24
Peak memory	571792 kb
Host	smart-3c81297b-e4c2-444a-97cf-f56158b616eb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763829204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.2763829204
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_error_random.2786386012
Short name	T2219
Test name
Test status
Simulation time	298839806 ps
CPU time	30.45 seconds
Started	May 23 04:28:14 PM PDT 24
Finished	May 23 04:28:45 PM PDT 24
Peak memory	571736 kb
Host	smart-c48473fc-4385-4263-af14-7ee48c0615c3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786386012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2786386012
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_random.2279650826
Short name	T446
Test name
Test status
Simulation time	2343553746 ps
CPU time	100.16 seconds
Started	May 23 04:28:16 PM PDT 24
Finished	May 23 04:29:58 PM PDT 24
Peak memory	571940 kb
Host	smart-876287e4-a408-456e-874c-bc7665873690
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279650826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.2279650826
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_random_large_delays.2973836407
Short name	T443
Test name
Test status
Simulation time	6895726266 ps
CPU time	70.4 seconds
Started	May 23 04:28:16 PM PDT 24
Finished	May 23 04:29:28 PM PDT 24
Peak memory	563792 kb
Host	smart-64324b69-4427-4aff-a1f2-e3df070e8f88
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973836407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2973836407
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.3935227121
Short name	T1341
Test name
Test status
Simulation time	20201978529 ps
CPU time	351.98 seconds
Started	May 23 04:28:19 PM PDT 24
Finished	May 23 04:34:12 PM PDT 24
Peak memory	572072 kb
Host	smart-d97ce5bd-36be-4e93-817b-3a5eb7fc621c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935227121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3935227121
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.1384992392
Short name	T1823
Test name
Test status
Simulation time	531953042 ps
CPU time	51.89 seconds
Started	May 23 04:28:15 PM PDT 24
Finished	May 23 04:29:08 PM PDT 24
Peak memory	571856 kb
Host	smart-4cfabb05-59cb-458c-bb21-cdaa57e296c8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384992392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.1384992392
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_same_source.197777014
Short name	T1773
Test name
Test status
Simulation time	482259683 ps
CPU time	42.86 seconds
Started	May 23 04:28:17 PM PDT 24
Finished	May 23 04:29:02 PM PDT 24
Peak memory	571860 kb
Host	smart-96fedf54-be1e-4440-a6eb-ca7a71e486c2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197777014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.197777014
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke.1576179838
Short name	T1459
Test name
Test status
Simulation time	39700929 ps
CPU time	6.31 seconds
Started	May 23 04:28:03 PM PDT 24
Finished	May 23 04:28:11 PM PDT 24
Peak memory	563512 kb
Host	smart-125f3bab-5c37-4a06-83a0-950721070d77
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576179838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1576179838
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3184285190
Short name	T2227
Test name
Test status
Simulation time	6849757042 ps
CPU time	75.34 seconds
Started	May 23 04:28:02 PM PDT 24
Finished	May 23 04:29:20 PM PDT 24
Peak memory	563776 kb
Host	smart-9314dbe6-cbd6-4643-927e-61597a53434f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184285190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3184285190
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.102466539
Short name	T1316
Test name
Test status
Simulation time	5422980911 ps
CPU time	99.11 seconds
Started	May 23 04:28:02 PM PDT 24
Finished	May 23 04:29:42 PM PDT 24
Peak memory	563764 kb
Host	smart-97df26f3-c75c-414e-a05a-bafa5325c2bf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102466539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.102466539
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3161128913
Short name	T2734
Test name
Test status
Simulation time	51577074 ps
CPU time	7.43 seconds
Started	May 23 04:28:02 PM PDT 24
Finished	May 23 04:28:12 PM PDT 24
Peak memory	563556 kb
Host	smart-7f9dbade-02c5-4314-aafd-81e862460617
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161128913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.3161128913
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all.3021035235
Short name	T589
Test name
Test status
Simulation time	2270569399 ps
CPU time	213.15 seconds
Started	May 23 04:28:15 PM PDT 24
Finished	May 23 04:31:50 PM PDT 24
Peak memory	572592 kb
Host	smart-5a4b6dbf-60e7-4384-9f48-a913936f41cb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021035235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3021035235
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3432776457
Short name	T1273
Test name
Test status
Simulation time	2445921537 ps
CPU time	203.8 seconds
Started	May 23 04:28:16 PM PDT 24
Finished	May 23 04:31:41 PM PDT 24
Peak memory	572452 kb
Host	smart-093bcc3a-0440-43da-b338-88c92e789920
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432776457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3432776457
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.786111720
Short name	T2410
Test name
Test status
Simulation time	2275428225 ps
CPU time	249.08 seconds
Started	May 23 04:28:19 PM PDT 24
Finished	May 23 04:32:29 PM PDT 24
Peak memory	572632 kb
Host	smart-692776d5-8249-43bd-8178-431085294228
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786111720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_ with_rand_reset.786111720
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.986852855
Short name	T1518
Test name
Test status
Simulation time	1176912514 ps
CPU time	211.3 seconds
Started	May 23 04:28:15 PM PDT 24
Finished	May 23 04:31:47 PM PDT 24
Peak memory	573000 kb
Host	smart-2747cd57-c586-406f-b2d6-9302a471068b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986852855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_reset_error.986852855
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.3879868621
Short name	T2428
Test name
Test status
Simulation time	53499266 ps
CPU time	9.68 seconds
Started	May 23 04:28:16 PM PDT 24
Finished	May 23 04:28:27 PM PDT 24
Peak memory	563680 kb
Host	smart-7f3a53f6-ac19-48e7-aa7c-56211eb71045
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879868621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3879868621
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/25.chip_tl_errors.1187088077
Short name	T654
Test name
Test status
Simulation time	3621807052 ps
CPU time	336.92 seconds
Started	May 23 04:28:17 PM PDT 24
Finished	May 23 04:33:56 PM PDT 24
Peak memory	602192 kb
Host	smart-47ddda0a-b647-46f2-bab2-c670e86870b9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187088077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1187088077
Directory	/workspace/25.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_access_same_device.3519097656
Short name	T2271
Test name
Test status
Simulation time	1209513220 ps
CPU time	56.93 seconds
Started	May 23 04:28:29 PM PDT 24
Finished	May 23 04:29:28 PM PDT 24
Peak memory	563640 kb
Host	smart-b3f1bad1-b06c-4f3d-9209-935c4034c76a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519097656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .3519097656
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.347297942
Short name	T1739
Test name
Test status
Simulation time	127572081337 ps
CPU time	2182.28 seconds
Started	May 23 04:28:31 PM PDT 24
Finished	May 23 05:04:55 PM PDT 24
Peak memory	572048 kb
Host	smart-0ba3c57d-2011-4d55-8b42-1fc64c4d87c2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347297942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.347297942
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2214991337
Short name	T2476
Test name
Test status
Simulation time	16235191 ps
CPU time	5.07 seconds
Started	May 23 04:28:30 PM PDT 24
Finished	May 23 04:28:37 PM PDT 24
Peak memory	563540 kb
Host	smart-0869d32e-9139-4435-9178-d56a7102ff97
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214991337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2214991337
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_error_random.990636212
Short name	T1811
Test name
Test status
Simulation time	2740571237 ps
CPU time	111.27 seconds
Started	May 23 04:28:32 PM PDT 24
Finished	May 23 04:30:24 PM PDT 24
Peak memory	571896 kb
Host	smart-4ac60e01-a4c4-4b65-ab7c-cf9881bca709
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990636212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.990636212
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_random.3754159646
Short name	T1863
Test name
Test status
Simulation time	2326755655 ps
CPU time	108.03 seconds
Started	May 23 04:28:30 PM PDT 24
Finished	May 23 04:30:20 PM PDT 24
Peak memory	571876 kb
Host	smart-3e15a392-3282-400c-845b-806699a2b6a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754159646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3754159646
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_random_large_delays.226054774
Short name	T2787
Test name
Test status
Simulation time	103212566620 ps
CPU time	1168.82 seconds
Started	May 23 04:28:29 PM PDT 24
Finished	May 23 04:48:00 PM PDT 24
Peak memory	572072 kb
Host	smart-90da936b-6f3f-4520-a70d-8f00a0a16184
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226054774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.226054774
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.2448122996
Short name	T1989
Test name
Test status
Simulation time	65631306436 ps
CPU time	1195.67 seconds
Started	May 23 04:28:29 PM PDT 24
Finished	May 23 04:48:26 PM PDT 24
Peak memory	572028 kb
Host	smart-21e8f67b-ad87-406e-9400-e14bf0bf5ce2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448122996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2448122996
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.3156858405
Short name	T2272
Test name
Test status
Simulation time	71757208 ps
CPU time	8.91 seconds
Started	May 23 04:28:29 PM PDT 24
Finished	May 23 04:28:40 PM PDT 24
Peak memory	563492 kb
Host	smart-5916d230-b9a4-48cd-b423-5f387292028a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156858405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.3156858405
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_same_source.2665702788
Short name	T1512
Test name
Test status
Simulation time	242018525 ps
CPU time	11.36 seconds
Started	May 23 04:28:30 PM PDT 24
Finished	May 23 04:28:43 PM PDT 24
Peak memory	563572 kb
Host	smart-90b9713b-4d52-4db3-997f-3e79975644e3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665702788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2665702788
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke.3991483483
Short name	T1550
Test name
Test status
Simulation time	207542298 ps
CPU time	10.2 seconds
Started	May 23 04:28:15 PM PDT 24
Finished	May 23 04:28:27 PM PDT 24
Peak memory	563476 kb
Host	smart-97d56a87-7c0b-42e3-abac-f0c6e5be2f8f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991483483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3991483483
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.601371112
Short name	T2270
Test name
Test status
Simulation time	7050811525 ps
CPU time	74.31 seconds
Started	May 23 04:28:30 PM PDT 24
Finished	May 23 04:29:46 PM PDT 24
Peak memory	563776 kb
Host	smart-e75ed349-bd2c-465d-9343-c96d241f5efd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601371112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.601371112
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1758961947
Short name	T1929
Test name
Test status
Simulation time	5487599148 ps
CPU time	101.88 seconds
Started	May 23 04:28:29 PM PDT 24
Finished	May 23 04:30:12 PM PDT 24
Peak memory	563796 kb
Host	smart-d1b15fb3-cb47-4e2a-b98f-34a24f07b050
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758961947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1758961947
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2509991837
Short name	T1748
Test name
Test status
Simulation time	40052687 ps
CPU time	6.18 seconds
Started	May 23 04:28:17 PM PDT 24
Finished	May 23 04:28:25 PM PDT 24
Peak memory	563556 kb
Host	smart-8b409942-e14e-414a-a666-cafa47394f2e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509991837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.2509991837
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all.2029206724
Short name	T2583
Test name
Test status
Simulation time	12237351130 ps
CPU time	603.93 seconds
Started	May 23 04:28:28 PM PDT 24
Finished	May 23 04:38:33 PM PDT 24
Peak memory	572236 kb
Host	smart-8363048d-8db9-417b-bc64-440c727541f8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029206724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2029206724
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.120310546
Short name	T666
Test name
Test status
Simulation time	1923735037 ps
CPU time	69.33 seconds
Started	May 23 04:28:30 PM PDT 24
Finished	May 23 04:29:40 PM PDT 24
Peak memory	571836 kb
Host	smart-ded4da06-954d-46ab-b737-8930eb0353bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120310546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.120310546
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.651579764
Short name	T2275
Test name
Test status
Simulation time	8985686075 ps
CPU time	1014.48 seconds
Started	May 23 04:28:29 PM PDT 24
Finished	May 23 04:45:25 PM PDT 24
Peak memory	573964 kb
Host	smart-b7ca60ee-37c9-45b4-a963-39e205fbf15d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651579764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_ with_rand_reset.651579764
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3947191078
Short name	T596
Test name
Test status
Simulation time	16572845016 ps
CPU time	773.15 seconds
Started	May 23 04:28:50 PM PDT 24
Finished	May 23 04:41:44 PM PDT 24
Peak memory	573112 kb
Host	smart-6ecb4e35-a2c5-4a4e-bfa6-e437787be489
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947191078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.3947191078
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3290285424
Short name	T1481
Test name
Test status
Simulation time	1084360905 ps
CPU time	53.14 seconds
Started	May 23 04:28:28 PM PDT 24
Finished	May 23 04:29:22 PM PDT 24
Peak memory	571840 kb
Host	smart-9f4e8144-bcc1-47e6-8367-4577b837ec63
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290285424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3290285424
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_access_same_device.667436466
Short name	T2048
Test name
Test status
Simulation time	2342339756 ps
CPU time	112.78 seconds
Started	May 23 04:28:48 PM PDT 24
Finished	May 23 04:30:42 PM PDT 24
Peak memory	571900 kb
Host	smart-82c35f39-ef21-493a-956b-60b73a545aa0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667436466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device. 667436466
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.4236827734
Short name	T2710
Test name
Test status
Simulation time	24016089454 ps
CPU time	415.64 seconds
Started	May 23 04:28:48 PM PDT 24
Finished	May 23 04:35:45 PM PDT 24
Peak memory	572004 kb
Host	smart-9c91c5c5-5f6a-4faa-8474-73563e2f1d03
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236827734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.4236827734
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2697775725
Short name	T1246
Test name
Test status
Simulation time	260605194 ps
CPU time	32.41 seconds
Started	May 23 04:28:46 PM PDT 24
Finished	May 23 04:29:20 PM PDT 24
Peak memory	571844 kb
Host	smart-0b490972-8419-4d09-9a17-322b50a11ec7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697775725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.2697775725
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_error_random.895979505
Short name	T2515
Test name
Test status
Simulation time	1671227423 ps
CPU time	62.58 seconds
Started	May 23 04:28:47 PM PDT 24
Finished	May 23 04:29:51 PM PDT 24
Peak memory	571848 kb
Host	smart-2bfa9edd-466d-4cec-8dfc-d854438feb22
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895979505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.895979505
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_random.1872305037
Short name	T2327
Test name
Test status
Simulation time	42967685 ps
CPU time	7.35 seconds
Started	May 23 04:28:49 PM PDT 24
Finished	May 23 04:28:57 PM PDT 24
Peak memory	563576 kb
Host	smart-03911f22-e148-47e3-8ed9-48cbc38f522b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872305037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1872305037
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_random_large_delays.4219541108
Short name	T2452
Test name
Test status
Simulation time	42873584445 ps
CPU time	469.4 seconds
Started	May 23 04:28:48 PM PDT 24
Finished	May 23 04:36:38 PM PDT 24
Peak memory	572020 kb
Host	smart-3976e698-efd5-4d30-aeb5-a8a8eb53edcc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219541108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4219541108
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1373382671
Short name	T2246
Test name
Test status
Simulation time	10762092582 ps
CPU time	189.58 seconds
Started	May 23 04:28:47 PM PDT 24
Finished	May 23 04:31:58 PM PDT 24
Peak memory	571980 kb
Host	smart-4d39c716-9ace-48c6-b9d8-136e9357097f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373382671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1373382671
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.2973720020
Short name	T2290
Test name
Test status
Simulation time	592510944 ps
CPU time	58.46 seconds
Started	May 23 04:28:49 PM PDT 24
Finished	May 23 04:29:49 PM PDT 24
Peak memory	571772 kb
Host	smart-bcdc5358-bc5e-4d25-83b6-b654546e9e58
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973720020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.2973720020
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_same_source.3726936750
Short name	T530
Test name
Test status
Simulation time	2610416962 ps
CPU time	93.11 seconds
Started	May 23 04:28:51 PM PDT 24
Finished	May 23 04:30:24 PM PDT 24
Peak memory	571916 kb
Host	smart-9dee6c7d-01ea-4f43-bee1-a76867ff21d5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726936750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3726936750
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke.1333791440
Short name	T2524
Test name
Test status
Simulation time	43182459 ps
CPU time	6.89 seconds
Started	May 23 04:28:48 PM PDT 24
Finished	May 23 04:28:56 PM PDT 24
Peak memory	563536 kb
Host	smart-5824ecb6-2a63-4d79-92ca-28c2c84fc207
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333791440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1333791440
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3330280905
Short name	T1949
Test name
Test status
Simulation time	7065525210 ps
CPU time	75.1 seconds
Started	May 23 04:28:49 PM PDT 24
Finished	May 23 04:30:06 PM PDT 24
Peak memory	563764 kb
Host	smart-75e48d0f-025a-4ed2-bb46-08ddf5b69052
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330280905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3330280905
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.3163018400
Short name	T1796
Test name
Test status
Simulation time	4409490601 ps
CPU time	77.84 seconds
Started	May 23 04:28:46 PM PDT 24
Finished	May 23 04:30:05 PM PDT 24
Peak memory	563780 kb
Host	smart-1da4400a-4d2b-4375-904b-63c7a3bff44b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163018400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3163018400
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3807637397
Short name	T1326
Test name
Test status
Simulation time	42157982 ps
CPU time	6.19 seconds
Started	May 23 04:28:49 PM PDT 24
Finished	May 23 04:28:56 PM PDT 24
Peak memory	563492 kb
Host	smart-bede6ef0-d110-4523-b0eb-b96e298f854e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807637397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.3807637397
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all.379671323
Short name	T1720
Test name
Test status
Simulation time	17803866101 ps
CPU time	640.3 seconds
Started	May 23 04:28:50 PM PDT 24
Finished	May 23 04:39:31 PM PDT 24
Peak memory	573016 kb
Host	smart-8c0d5d46-4df2-4783-b31d-345ba8748356
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379671323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.379671323
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.445275642
Short name	T2692
Test name
Test status
Simulation time	3946421996 ps
CPU time	153.93 seconds
Started	May 23 04:28:47 PM PDT 24
Finished	May 23 04:31:22 PM PDT 24
Peak memory	572036 kb
Host	smart-12236c50-6922-4818-ae89-456f1e34228a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445275642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.445275642
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1663865591
Short name	T1535
Test name
Test status
Simulation time	473859835 ps
CPU time	170.77 seconds
Started	May 23 04:28:50 PM PDT 24
Finished	May 23 04:31:42 PM PDT 24
Peak memory	572904 kb
Host	smart-e340c43c-6db9-4c96-a91c-b09b32c3c2d8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663865591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.1663865591
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3904062197
Short name	T1789
Test name
Test status
Simulation time	2682126880 ps
CPU time	201.7 seconds
Started	May 23 04:28:48 PM PDT 24
Finished	May 23 04:32:11 PM PDT 24
Peak memory	574108 kb
Host	smart-7556a4f8-bdd5-4d8a-9ea1-6febd8e391c5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904062197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.3904062197
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.1530910603
Short name	T1715
Test name
Test status
Simulation time	949757486 ps
CPU time	48.2 seconds
Started	May 23 04:28:46 PM PDT 24
Finished	May 23 04:29:35 PM PDT 24
Peak memory	571884 kb
Host	smart-965344d1-34e4-4859-96d7-340e6a5f35a0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530910603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1530910603
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/27.chip_tl_errors.4248255680
Short name	T653
Test name
Test status
Simulation time	3762653448 ps
CPU time	178.56 seconds
Started	May 23 04:28:47 PM PDT 24
Finished	May 23 04:31:46 PM PDT 24
Peak memory	594044 kb
Host	smart-ed86a384-59cc-4471-893d-065994a29c05
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248255680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.4248255680
Directory	/workspace/27.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_access_same_device.1147123962
Short name	T1528
Test name
Test status
Simulation time	227531002 ps
CPU time	31.26 seconds
Started	May 23 04:29:02 PM PDT 24
Finished	May 23 04:29:35 PM PDT 24
Peak memory	563632 kb
Host	smart-fff2222e-183f-4218-b1ae-edbca1ce9bd7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147123962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .1147123962
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3265307664
Short name	T1908
Test name
Test status
Simulation time	101786564681 ps
CPU time	1784.64 seconds
Started	May 23 04:29:02 PM PDT 24
Finished	May 23 04:58:49 PM PDT 24
Peak memory	572072 kb
Host	smart-35fb5c6a-3ab5-4ab3-97ed-9843657cdfd1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265307664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.3265307664
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1150769584
Short name	T2597
Test name
Test status
Simulation time	502385951 ps
CPU time	24.25 seconds
Started	May 23 04:29:04 PM PDT 24
Finished	May 23 04:29:30 PM PDT 24
Peak memory	571736 kb
Host	smart-de3e1e1d-c1e8-4b7d-be09-9d68f2a087b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150769584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.1150769584
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_error_random.2057321754
Short name	T2174
Test name
Test status
Simulation time	463697874 ps
CPU time	42.59 seconds
Started	May 23 04:29:01 PM PDT 24
Finished	May 23 04:29:46 PM PDT 24
Peak memory	571804 kb
Host	smart-d4a2cf66-bd0b-436b-90c0-486b0a3c6781
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057321754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2057321754
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_random.3264348279
Short name	T2306
Test name
Test status
Simulation time	1648526465 ps
CPU time	73.9 seconds
Started	May 23 04:29:04 PM PDT 24
Finished	May 23 04:30:20 PM PDT 24
Peak memory	571820 kb
Host	smart-1b89c486-d9a7-4088-ac41-4fde0e5a9c5a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264348279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3264348279
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2207263152
Short name	T2089
Test name
Test status
Simulation time	45468204557 ps
CPU time	523.69 seconds
Started	May 23 04:29:00 PM PDT 24
Finished	May 23 04:37:46 PM PDT 24
Peak memory	572048 kb
Host	smart-731c7a67-2ff6-4a50-abfc-fa1863c8b2f0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207263152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2207263152
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.2649013483
Short name	T2243
Test name
Test status
Simulation time	44477252547 ps
CPU time	836.4 seconds
Started	May 23 04:29:03 PM PDT 24
Finished	May 23 04:43:01 PM PDT 24
Peak memory	572048 kb
Host	smart-85ae412a-bd97-4213-a393-a7ee8083e00f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649013483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2649013483
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.1815917822
Short name	T1634
Test name
Test status
Simulation time	70738141 ps
CPU time	9 seconds
Started	May 23 04:29:05 PM PDT 24
Finished	May 23 04:29:16 PM PDT 24
Peak memory	563620 kb
Host	smart-33d3082d-a1b4-4121-8977-240fef09e596
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815917822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.1815917822
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_same_source.955446460
Short name	T2640
Test name
Test status
Simulation time	731298941 ps
CPU time	25.86 seconds
Started	May 23 04:29:03 PM PDT 24
Finished	May 23 04:29:31 PM PDT 24
Peak memory	571748 kb
Host	smart-167c3905-f56d-4b0a-add5-4c8568a1a8c4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955446460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.955446460
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke.2515442162
Short name	T1378
Test name
Test status
Simulation time	241735648 ps
CPU time	10.51 seconds
Started	May 23 04:28:48 PM PDT 24
Finished	May 23 04:28:59 PM PDT 24
Peak memory	563532 kb
Host	smart-2500518c-ca89-4545-b667-decdb4f9dc6b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515442162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2515442162
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.1333000101
Short name	T1324
Test name
Test status
Simulation time	8733080032 ps
CPU time	92.71 seconds
Started	May 23 04:28:50 PM PDT 24
Finished	May 23 04:30:24 PM PDT 24
Peak memory	563780 kb
Host	smart-e02abe76-30b6-4b0a-af67-a85ba574502b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333000101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1333000101
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.3020016820
Short name	T1545
Test name
Test status
Simulation time	5329993370 ps
CPU time	92.82 seconds
Started	May 23 04:29:05 PM PDT 24
Finished	May 23 04:30:40 PM PDT 24
Peak memory	563804 kb
Host	smart-5dd98f42-fd2d-4a6d-93b1-7b38440403bf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020016820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3020016820
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1711912354
Short name	T2357
Test name
Test status
Simulation time	45171499 ps
CPU time	6.59 seconds
Started	May 23 04:28:47 PM PDT 24
Finished	May 23 04:28:55 PM PDT 24
Peak memory	563528 kb
Host	smart-34154f01-4741-4704-9133-a9860245d8fa
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711912354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.1711912354
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all.889496836
Short name	T2348
Test name
Test status
Simulation time	2373274030 ps
CPU time	237.39 seconds
Started	May 23 04:29:01 PM PDT 24
Finished	May 23 04:33:01 PM PDT 24
Peak memory	572596 kb
Host	smart-fe4f6512-bb4d-4f04-834d-39bd421bebd2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889496836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.889496836
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3002721262
Short name	T1692
Test name
Test status
Simulation time	4136753108 ps
CPU time	166.32 seconds
Started	May 23 04:29:02 PM PDT 24
Finished	May 23 04:31:51 PM PDT 24
Peak memory	571968 kb
Host	smart-121ef031-d633-4c38-8eb9-efc303db790b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002721262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3002721262
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.777932337
Short name	T2409
Test name
Test status
Simulation time	7716239178 ps
CPU time	464.07 seconds
Started	May 23 04:29:05 PM PDT 24
Finished	May 23 04:36:51 PM PDT 24
Peak memory	573052 kb
Host	smart-e73497a2-fb3f-41bf-8530-ec46c283c5df
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777932337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_ with_rand_reset.777932337
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1982511790
Short name	T1973
Test name
Test status
Simulation time	115034535 ps
CPU time	44.61 seconds
Started	May 23 04:29:03 PM PDT 24
Finished	May 23 04:29:50 PM PDT 24
Peak memory	572940 kb
Host	smart-5cddf5e6-935d-4f7f-8870-002ffba14cfa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982511790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.1982511790
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.4211948716
Short name	T2238
Test name
Test status
Simulation time	79364950 ps
CPU time	7.16 seconds
Started	May 23 04:29:01 PM PDT 24
Finished	May 23 04:29:11 PM PDT 24
Peak memory	563604 kb
Host	smart-244e8b83-cd26-4c63-95f8-912172dd0360
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211948716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.4211948716
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_access_same_device.3289902337
Short name	T1770
Test name
Test status
Simulation time	768316000 ps
CPU time	59.23 seconds
Started	May 23 04:29:15 PM PDT 24
Finished	May 23 04:30:15 PM PDT 24
Peak memory	571800 kb
Host	smart-6b0b8f1c-d054-4439-9ebe-528d692604d0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289902337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .3289902337
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.164672230
Short name	T2254
Test name
Test status
Simulation time	4577431260 ps
CPU time	87.43 seconds
Started	May 23 04:29:14 PM PDT 24
Finished	May 23 04:30:42 PM PDT 24
Peak memory	563824 kb
Host	smart-4e2cd81b-18e3-4150-a507-882a195df712
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164672230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_d evice_slow_rsp.164672230
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.3334031930
Short name	T1702
Test name
Test status
Simulation time	1185082227 ps
CPU time	48.95 seconds
Started	May 23 04:29:18 PM PDT 24
Finished	May 23 04:30:08 PM PDT 24
Peak memory	571748 kb
Host	smart-6b173dc8-995a-4667-a89b-96eae227aef9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334031930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.3334031930
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_error_random.3044467025
Short name	T2622
Test name
Test status
Simulation time	38715116 ps
CPU time	6.67 seconds
Started	May 23 04:29:15 PM PDT 24
Finished	May 23 04:29:23 PM PDT 24
Peak memory	563540 kb
Host	smart-65ad7f27-8d26-4225-8372-aa43fa32cce1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044467025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3044467025
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_random.2136000031
Short name	T1480
Test name
Test status
Simulation time	2536594889 ps
CPU time	97.85 seconds
Started	May 23 04:29:00 PM PDT 24
Finished	May 23 04:30:41 PM PDT 24
Peak memory	571944 kb
Host	smart-20c36145-807d-415a-9d10-810783c6a53f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136000031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.2136000031
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_random_large_delays.948845944
Short name	T2678
Test name
Test status
Simulation time	36021847682 ps
CPU time	377.83 seconds
Started	May 23 04:29:14 PM PDT 24
Finished	May 23 04:35:33 PM PDT 24
Peak memory	572032 kb
Host	smart-f83a48aa-6187-434c-b019-7f2c41330541
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948845944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.948845944
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.497527816
Short name	T592
Test name
Test status
Simulation time	38132506120 ps
CPU time	676.63 seconds
Started	May 23 04:29:15 PM PDT 24
Finished	May 23 04:40:33 PM PDT 24
Peak memory	572028 kb
Host	smart-b5ab29c8-4699-454d-9e4c-81f1f39a0af9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497527816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.497527816
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.3817653674
Short name	T1985
Test name
Test status
Simulation time	494832049 ps
CPU time	47.36 seconds
Started	May 23 04:29:18 PM PDT 24
Finished	May 23 04:30:06 PM PDT 24
Peak memory	571792 kb
Host	smart-eb1f3e9f-ecd0-4854-94f8-608180f5ace7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817653674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.3817653674
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_same_source.75637545
Short name	T1938
Test name
Test status
Simulation time	379520703 ps
CPU time	29.98 seconds
Started	May 23 04:29:18 PM PDT 24
Finished	May 23 04:29:50 PM PDT 24
Peak memory	571792 kb
Host	smart-70389bea-61bf-497d-91de-ff8e127af3db
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75637545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.75637545
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke.3800006729
Short name	T1743
Test name
Test status
Simulation time	196828292 ps
CPU time	8.93 seconds
Started	May 23 04:29:03 PM PDT 24
Finished	May 23 04:29:14 PM PDT 24
Peak memory	563516 kb
Host	smart-a32c8c5c-7761-4895-8805-30e801403b5a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800006729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3800006729
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.607571316
Short name	T1298
Test name
Test status
Simulation time	5935365675 ps
CPU time	63.81 seconds
Started	May 23 04:29:01 PM PDT 24
Finished	May 23 04:30:07 PM PDT 24
Peak memory	563684 kb
Host	smart-a18ae49c-de78-4dad-bffe-564172a701a1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607571316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.607571316
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.227334048
Short name	T1563
Test name
Test status
Simulation time	4397508620 ps
CPU time	81.64 seconds
Started	May 23 04:29:01 PM PDT 24
Finished	May 23 04:30:25 PM PDT 24
Peak memory	563772 kb
Host	smart-c0e1b571-2c9a-4556-bbf2-08b5eb01f3e0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227334048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.227334048
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.974766324
Short name	T1727
Test name
Test status
Simulation time	51142722 ps
CPU time	7.46 seconds
Started	May 23 04:29:01 PM PDT 24
Finished	May 23 04:29:11 PM PDT 24
Peak memory	563504 kb
Host	smart-a75dd5e2-8abf-4237-b1cb-3095ad8590b9
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974766324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays .974766324
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all.919845179
Short name	T520
Test name
Test status
Simulation time	3538684313 ps
CPU time	158.76 seconds
Started	May 23 04:29:16 PM PDT 24
Finished	May 23 04:31:56 PM PDT 24
Peak memory	571920 kb
Host	smart-6b342356-e374-4077-b666-04a4502d30a6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919845179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.919845179
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.4043692143
Short name	T2500
Test name
Test status
Simulation time	1920130022 ps
CPU time	172.35 seconds
Started	May 23 04:29:15 PM PDT 24
Finished	May 23 04:32:09 PM PDT 24
Peak memory	571860 kb
Host	smart-352f51db-bff5-4a3b-a555-fc9017c08d35
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043692143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.4043692143
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.4042237122
Short name	T1396
Test name
Test status
Simulation time	652718440 ps
CPU time	342.86 seconds
Started	May 23 04:29:17 PM PDT 24
Finished	May 23 04:35:01 PM PDT 24
Peak memory	573928 kb
Host	smart-4ec99ddc-f190-4944-810e-f57d463fa4b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042237122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.4042237122
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2234062872
Short name	T2284
Test name
Test status
Simulation time	20231615 ps
CPU time	9.94 seconds
Started	May 23 04:29:18 PM PDT 24
Finished	May 23 04:29:29 PM PDT 24
Peak memory	563680 kb
Host	smart-4fb5b3c2-f86e-4d1e-8704-eb579b5873ac
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234062872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.2234062872
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1640393072
Short name	T1952
Test name
Test status
Simulation time	899066906 ps
CPU time	41.89 seconds
Started	May 23 04:29:18 PM PDT 24
Finished	May 23 04:30:01 PM PDT 24
Peak memory	571784 kb
Host	smart-6e74872c-1780-41f7-9377-f1a7170e3935
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640393072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1640393072
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_access_same_device.1555227034
Short name	T2727
Test name
Test status
Simulation time	939681764 ps
CPU time	73.33 seconds
Started	May 23 04:29:31 PM PDT 24
Finished	May 23 04:30:45 PM PDT 24
Peak memory	571880 kb
Host	smart-248c7fa6-3dae-47ad-af8c-47e32b122427
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555227034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .1555227034
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3691082093
Short name	T2253
Test name
Test status
Simulation time	67761089290 ps
CPU time	1194.84 seconds
Started	May 23 04:29:32 PM PDT 24
Finished	May 23 04:49:28 PM PDT 24
Peak memory	572012 kb
Host	smart-78e66bb6-8049-4d1a-b4e1-0e7d13c77ba6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691082093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.3691082093
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2730479231
Short name	T1847
Test name
Test status
Simulation time	161172096 ps
CPU time	21.84 seconds
Started	May 23 04:29:34 PM PDT 24
Finished	May 23 04:29:57 PM PDT 24
Peak memory	571844 kb
Host	smart-70bf2689-2d8d-4a33-8490-0a6e50bfb140
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730479231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.2730479231
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_error_random.2714137507
Short name	T1799
Test name
Test status
Simulation time	491179903 ps
CPU time	47.96 seconds
Started	May 23 04:29:31 PM PDT 24
Finished	May 23 04:30:20 PM PDT 24
Peak memory	571804 kb
Host	smart-1f3c70f3-cca6-4eb3-a950-6073d0f9d1c8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714137507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2714137507
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_random.3856863562
Short name	T2026
Test name
Test status
Simulation time	569595127 ps
CPU time	51.59 seconds
Started	May 23 04:29:30 PM PDT 24
Finished	May 23 04:30:23 PM PDT 24
Peak memory	571812 kb
Host	smart-6fec18df-0d8a-4685-b473-38034da3be2c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856863562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.3856863562
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_random_large_delays.491189593
Short name	T1691
Test name
Test status
Simulation time	65239758615 ps
CPU time	707.08 seconds
Started	May 23 04:29:31 PM PDT 24
Finished	May 23 04:41:19 PM PDT 24
Peak memory	572024 kb
Host	smart-49045511-8a80-4cbe-855c-1c72d8de2500
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491189593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.491189593
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.478489871
Short name	T1460
Test name
Test status
Simulation time	6437745038 ps
CPU time	125.87 seconds
Started	May 23 04:29:30 PM PDT 24
Finished	May 23 04:31:38 PM PDT 24
Peak memory	563856 kb
Host	smart-369cf703-5a0e-46db-91cf-5bfc7a441e77
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478489871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.478489871
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.3564560165
Short name	T1431
Test name
Test status
Simulation time	314682688 ps
CPU time	32.34 seconds
Started	May 23 04:29:33 PM PDT 24
Finished	May 23 04:30:06 PM PDT 24
Peak memory	571804 kb
Host	smart-bfe8214b-838d-4be7-90fb-e36bbaafa89e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564560165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.3564560165
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_same_source.4081820668
Short name	T2496
Test name
Test status
Simulation time	2729782227 ps
CPU time	94.09 seconds
Started	May 23 04:29:33 PM PDT 24
Finished	May 23 04:31:08 PM PDT 24
Peak memory	571984 kb
Host	smart-458992a6-e351-4c8f-b6ba-d4710257d821
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081820668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4081820668
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke.2426499763
Short name	T2197
Test name
Test status
Simulation time	42444942 ps
CPU time	6.55 seconds
Started	May 23 04:29:17 PM PDT 24
Finished	May 23 04:29:24 PM PDT 24
Peak memory	563540 kb
Host	smart-6516271a-dce7-4644-9710-a99a80d2e97f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426499763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2426499763
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.568239204
Short name	T2059
Test name
Test status
Simulation time	8128941023 ps
CPU time	92.6 seconds
Started	May 23 04:29:33 PM PDT 24
Finished	May 23 04:31:07 PM PDT 24
Peak memory	563740 kb
Host	smart-ad387bad-0695-47a1-8116-e345dcca81b6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568239204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.568239204
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3055518207
Short name	T1267
Test name
Test status
Simulation time	5823063617 ps
CPU time	104.71 seconds
Started	May 23 04:29:32 PM PDT 24
Finished	May 23 04:31:18 PM PDT 24
Peak memory	563796 kb
Host	smart-686d1a3e-ed9e-45e9-a655-ba4e6ae803b3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055518207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3055518207
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1853226438
Short name	T2155
Test name
Test status
Simulation time	50054615 ps
CPU time	7.12 seconds
Started	May 23 04:29:18 PM PDT 24
Finished	May 23 04:29:27 PM PDT 24
Peak memory	563544 kb
Host	smart-44ba9418-3fd9-4b88-b4ac-8067e41773a8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853226438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.1853226438
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all.3769059205
Short name	T1800
Test name
Test status
Simulation time	5190781178 ps
CPU time	218.12 seconds
Started	May 23 04:29:31 PM PDT 24
Finished	May 23 04:33:11 PM PDT 24
Peak memory	571904 kb
Host	smart-1caf76fc-185f-4ef7-a973-ad499ead6e57
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769059205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3769059205
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.97111851
Short name	T1477
Test name
Test status
Simulation time	346267576 ps
CPU time	26.44 seconds
Started	May 23 04:29:31 PM PDT 24
Finished	May 23 04:29:58 PM PDT 24
Peak memory	571840 kb
Host	smart-88511cc6-df45-4f88-b237-a19a5f6cac30
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97111851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.97111851
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1249349607
Short name	T1845
Test name
Test status
Simulation time	20854066259 ps
CPU time	1155.6 seconds
Started	May 23 04:29:34 PM PDT 24
Finished	May 23 04:48:51 PM PDT 24
Peak memory	573076 kb
Host	smart-c477cbd8-4c15-417b-bfd3-ffdc4ef2301f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249349607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.1249349607
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3680750569
Short name	T833
Test name
Test status
Simulation time	76929362 ps
CPU time	31.08 seconds
Started	May 23 04:29:31 PM PDT 24
Finished	May 23 04:30:03 PM PDT 24
Peak memory	572924 kb
Host	smart-0d081f72-b7d9-4642-9973-83d6d91a6df9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680750569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.3680750569
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.2999851636
Short name	T2194
Test name
Test status
Simulation time	243066615 ps
CPU time	35.38 seconds
Started	May 23 04:29:33 PM PDT 24
Finished	May 23 04:30:10 PM PDT 24
Peak memory	571844 kb
Host	smart-9e7a7529-1886-4bcf-b107-d1d580ab441f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999851636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2999851636
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_aliasing.4048890238
Short name	T2090
Test name
Test status
Simulation time	30793491581 ps
CPU time	5718.78 seconds
Started	May 23 04:18:53 PM PDT 24
Finished	May 23 05:54:14 PM PDT 24
Peak memory	586496 kb
Host	smart-de181e13-98bc-4f1d-93c6-3d5e89cc8754
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048890238 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.4048890238
Directory	/workspace/3.chip_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.1889554236
Short name	T487
Test name
Test status
Simulation time	87431551245 ps
CPU time	8738.19 seconds
Started	May 23 04:18:36 PM PDT 24
Finished	May 23 06:44:16 PM PDT 24
Peak memory	586124 kb
Host	smart-d844bdc8-b200-4122-8346-40fb5adbc30d
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889554236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.1889554236
Directory	/workspace/3.chip_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_csr_rw.3126994793
Short name	T1776
Test name
Test status
Simulation time	5585337902 ps
CPU time	534.31 seconds
Started	May 23 04:19:35 PM PDT 24
Finished	May 23 04:28:31 PM PDT 24
Peak memory	592076 kb
Host	smart-722a7549-846a-4801-9dfa-c243a1c75136
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126994793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.3126994793
Directory	/workspace/3.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1563155201
Short name	T2035
Test name
Test status
Simulation time	27135312057 ps
CPU time	3389.58 seconds
Started	May 23 04:18:55 PM PDT 24
Finished	May 23 05:15:25 PM PDT 24
Peak memory	586600 kb
Host	smart-e11a6c3d-c2b6-47e5-b250-2619e29ecf40
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563155201 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1563155201
Directory	/workspace/3.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.chip_tl_errors.3693671466
Short name	T516
Test name
Test status
Simulation time	3315044100 ps
CPU time	312.4 seconds
Started	May 23 04:18:52 PM PDT 24
Finished	May 23 04:24:05 PM PDT 24
Peak memory	594576 kb
Host	smart-d6fccc27-d7a8-4608-8340-786e6a2ea84d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693671466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.3693671466
Directory	/workspace/3.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_access_same_device.3970662384
Short name	T1793
Test name
Test status
Simulation time	15522664 ps
CPU time	7.79 seconds
Started	May 23 04:19:18 PM PDT 24
Finished	May 23 04:19:27 PM PDT 24
Peak memory	563544 kb
Host	smart-d3df3fa9-7f8a-44d5-87fa-90390b484215
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970662384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 3970662384
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.41156400
Short name	T2444
Test name
Test status
Simulation time	127033199979 ps
CPU time	2126.14 seconds
Started	May 23 04:19:21 PM PDT 24
Finished	May 23 04:54:49 PM PDT 24
Peak memory	572048 kb
Host	smart-7119c1a4-7bfc-4d0f-88cf-d794b85815b7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41156400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_dev ice_slow_rsp.41156400
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3239055847
Short name	T1880
Test name
Test status
Simulation time	312177249 ps
CPU time	41.06 seconds
Started	May 23 04:19:17 PM PDT 24
Finished	May 23 04:19:59 PM PDT 24
Peak memory	571816 kb
Host	smart-e07414f6-2e31-48d6-8324-6d0e65ae55a1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239055847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .3239055847
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_error_random.2045652046
Short name	T502
Test name
Test status
Simulation time	2035010254 ps
CPU time	79.25 seconds
Started	May 23 04:20:12 PM PDT 24
Finished	May 23 04:21:32 PM PDT 24
Peak memory	571812 kb
Host	smart-a8ad56e7-8628-4a64-8878-587fe5b655cd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045652046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2045652046
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_random.1717202314
Short name	T1464
Test name
Test status
Simulation time	583473117 ps
CPU time	58.15 seconds
Started	May 23 04:19:26 PM PDT 24
Finished	May 23 04:20:25 PM PDT 24
Peak memory	571820 kb
Host	smart-238279ea-b2a1-4658-813d-d428aeb5ae22
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717202314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1717202314
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_random_large_delays.1889022150
Short name	T1386
Test name
Test status
Simulation time	56511379034 ps
CPU time	701.19 seconds
Started	May 23 04:19:15 PM PDT 24
Finished	May 23 04:30:57 PM PDT 24
Peak memory	572028 kb
Host	smart-d7228b75-4559-4543-a4f1-e8f09d78b413
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889022150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1889022150
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.2561655299
Short name	T2745
Test name
Test status
Simulation time	35213894481 ps
CPU time	651.93 seconds
Started	May 23 04:19:15 PM PDT 24
Finished	May 23 04:30:08 PM PDT 24
Peak memory	572012 kb
Host	smart-0fdfe829-8341-496f-811c-20af179616de
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561655299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2561655299
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.3250667455
Short name	T2615
Test name
Test status
Simulation time	220589223 ps
CPU time	22.96 seconds
Started	May 23 04:19:06 PM PDT 24
Finished	May 23 04:19:29 PM PDT 24
Peak memory	571776 kb
Host	smart-dfacf83c-9eea-4687-86f4-9dc53be182c5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250667455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.3250667455
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_same_source.1382544792
Short name	T406
Test name
Test status
Simulation time	241973820 ps
CPU time	24.24 seconds
Started	May 23 04:19:20 PM PDT 24
Finished	May 23 04:19:45 PM PDT 24
Peak memory	571744 kb
Host	smart-8ac11c64-9a10-46f7-ad30-69edfa87407a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382544792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1382544792
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke.4194819877
Short name	T54
Test name
Test status
Simulation time	258433857 ps
CPU time	13.14 seconds
Started	May 23 04:18:54 PM PDT 24
Finished	May 23 04:19:08 PM PDT 24
Peak memory	563596 kb
Host	smart-085bdea6-0dbb-40f6-aa7a-dfb858e2f2fc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194819877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.4194819877
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.3991035687
Short name	T2233
Test name
Test status
Simulation time	7695025182 ps
CPU time	98.19 seconds
Started	May 23 04:20:27 PM PDT 24
Finished	May 23 04:22:08 PM PDT 24
Peak memory	563812 kb
Host	smart-524ffa65-16b1-458d-b532-c953c358f2ee
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991035687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3991035687
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.4014229395
Short name	T2041
Test name
Test status
Simulation time	6953563796 ps
CPU time	135.54 seconds
Started	May 23 04:19:12 PM PDT 24
Finished	May 23 04:21:28 PM PDT 24
Peak memory	563720 kb
Host	smart-bf7d0adb-3b21-4404-a963-2b4d698973d9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014229395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.4014229395
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.526464288
Short name	T1616
Test name
Test status
Simulation time	41881852 ps
CPU time	6.7 seconds
Started	May 23 04:19:05 PM PDT 24
Finished	May 23 04:19:13 PM PDT 24
Peak memory	563552 kb
Host	smart-556f28fb-193b-4e1b-9827-a1e38cb145d1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526464288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays. 526464288
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all.1179398313
Short name	T1810
Test name
Test status
Simulation time	217546179 ps
CPU time	22.6 seconds
Started	May 23 04:20:43 PM PDT 24
Finished	May 23 04:21:06 PM PDT 24
Peak memory	571884 kb
Host	smart-b7a08414-81dc-451e-8f47-272e58025838
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179398313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1179398313
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2590300999
Short name	T1725
Test name
Test status
Simulation time	13117615537 ps
CPU time	586.6 seconds
Started	May 23 04:19:26 PM PDT 24
Finished	May 23 04:29:13 PM PDT 24
Peak memory	573096 kb
Host	smart-59c9d7bc-f17a-4d1c-9ca9-3cabc492348f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590300999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2590300999
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3103933764
Short name	T1980
Test name
Test status
Simulation time	136917832 ps
CPU time	110.91 seconds
Started	May 23 04:19:13 PM PDT 24
Finished	May 23 04:21:05 PM PDT 24
Peak memory	572712 kb
Host	smart-59026f77-7a89-43b4-8d13-2768645f4ac8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103933764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.3103933764
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.957002343
Short name	T828
Test name
Test status
Simulation time	937740744 ps
CPU time	173.25 seconds
Started	May 23 04:19:31 PM PDT 24
Finished	May 23 04:22:25 PM PDT 24
Peak memory	573024 kb
Host	smart-02b3e01e-20e7-43cf-a991-b18d6c041b95
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957002343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_reset_error.957002343
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.1295723367
Short name	T1934
Test name
Test status
Simulation time	311235953 ps
CPU time	50.23 seconds
Started	May 23 04:19:48 PM PDT 24
Finished	May 23 04:20:39 PM PDT 24
Peak memory	571836 kb
Host	smart-610c4c44-41c5-4fc9-bfab-68539b60735e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295723367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1295723367
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_access_same_device.1137961200
Short name	T2123
Test name
Test status
Simulation time	1320899588 ps
CPU time	78.82 seconds
Started	May 23 04:29:33 PM PDT 24
Finished	May 23 04:30:53 PM PDT 24
Peak memory	571852 kb
Host	smart-8aeff0f9-cab6-4227-8f63-35433a6346b2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137961200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .1137961200
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2789841006
Short name	T2552
Test name
Test status
Simulation time	76983670430 ps
CPU time	1363.45 seconds
Started	May 23 04:29:34 PM PDT 24
Finished	May 23 04:52:19 PM PDT 24
Peak memory	571976 kb
Host	smart-9b5da4c0-b06d-47cb-92d5-529bdd39bd29
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789841006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.2789841006
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2435111902
Short name	T2127
Test name
Test status
Simulation time	149036904 ps
CPU time	18.74 seconds
Started	May 23 04:29:47 PM PDT 24
Finished	May 23 04:30:07 PM PDT 24
Peak memory	571808 kb
Host	smart-14868745-91c1-4cab-b875-85a9b1887965
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435111902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.2435111902
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_error_random.1054117771
Short name	T2149
Test name
Test status
Simulation time	326139864 ps
CPU time	29.48 seconds
Started	May 23 04:29:31 PM PDT 24
Finished	May 23 04:30:02 PM PDT 24
Peak memory	571788 kb
Host	smart-8386b35a-94a0-401e-ab45-aaec149c0b87
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054117771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1054117771
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_random.521307250
Short name	T2187
Test name
Test status
Simulation time	1291623895 ps
CPU time	55.34 seconds
Started	May 23 04:29:33 PM PDT 24
Finished	May 23 04:30:30 PM PDT 24
Peak memory	571824 kb
Host	smart-8edaa50d-d050-4558-8717-6894b1ca5e76
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521307250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.521307250
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_random_large_delays.463506135
Short name	T1714
Test name
Test status
Simulation time	35552768332 ps
CPU time	366.52 seconds
Started	May 23 04:29:36 PM PDT 24
Finished	May 23 04:35:43 PM PDT 24
Peak memory	572056 kb
Host	smart-7751d879-80fd-415b-b44a-6fdc504b2eeb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463506135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.463506135
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.2453844210
Short name	T458
Test name
Test status
Simulation time	66994203036 ps
CPU time	1281.99 seconds
Started	May 23 04:29:29 PM PDT 24
Finished	May 23 04:50:52 PM PDT 24
Peak memory	572076 kb
Host	smart-c931f787-0e69-4800-8f25-a9d4580d60d9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453844210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2453844210
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3702139475
Short name	T1359
Test name
Test status
Simulation time	97793860 ps
CPU time	12.85 seconds
Started	May 23 04:29:32 PM PDT 24
Finished	May 23 04:29:46 PM PDT 24
Peak memory	571792 kb
Host	smart-0e133786-5541-44fd-be9c-0c78b1201bd7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702139475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.3702139475
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_same_source.812254047
Short name	T1437
Test name
Test status
Simulation time	1393036748 ps
CPU time	47.05 seconds
Started	May 23 04:29:30 PM PDT 24
Finished	May 23 04:30:18 PM PDT 24
Peak memory	571820 kb
Host	smart-62e0a9a5-04b8-40a4-a442-3c978130b11c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812254047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.812254047
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke.3389622799
Short name	T1924
Test name
Test status
Simulation time	47152892 ps
CPU time	6.77 seconds
Started	May 23 04:29:33 PM PDT 24
Finished	May 23 04:29:41 PM PDT 24
Peak memory	563484 kb
Host	smart-16bc5253-76c4-4862-8487-219ac68437cf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389622799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3389622799
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1383366559
Short name	T2051
Test name
Test status
Simulation time	9510369200 ps
CPU time	108.5 seconds
Started	May 23 04:29:32 PM PDT 24
Finished	May 23 04:31:21 PM PDT 24
Peak memory	563736 kb
Host	smart-39d6c9b9-6f9e-4c9d-b8ea-507effd68301
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383366559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1383366559
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1580855580
Short name	T2025
Test name
Test status
Simulation time	5522490894 ps
CPU time	97.54 seconds
Started	May 23 04:29:31 PM PDT 24
Finished	May 23 04:31:10 PM PDT 24
Peak memory	563752 kb
Host	smart-5b80ddbb-229c-497f-9f95-bc07d9f5984e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580855580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1580855580
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1200004356
Short name	T2220
Test name
Test status
Simulation time	37864623 ps
CPU time	6.37 seconds
Started	May 23 04:29:30 PM PDT 24
Finished	May 23 04:29:37 PM PDT 24
Peak memory	563512 kb
Host	smart-00988e69-c204-4e42-9baf-af5941e69fe0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200004356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.1200004356
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all.2009905666
Short name	T2535
Test name
Test status
Simulation time	8252271090 ps
CPU time	283.67 seconds
Started	May 23 04:29:45 PM PDT 24
Finished	May 23 04:34:30 PM PDT 24
Peak memory	572204 kb
Host	smart-86152341-3503-4199-b91c-66b1d0b7fe43
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009905666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2009905666
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.840417840
Short name	T504
Test name
Test status
Simulation time	8616082141 ps
CPU time	306.45 seconds
Started	May 23 04:29:46 PM PDT 24
Finished	May 23 04:34:53 PM PDT 24
Peak memory	571976 kb
Host	smart-04a74da1-b24a-4d94-ba9b-5210b88dbc10
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840417840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.840417840
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2727800499
Short name	T1434
Test name
Test status
Simulation time	323802931 ps
CPU time	150.07 seconds
Started	May 23 04:29:51 PM PDT 24
Finished	May 23 04:32:22 PM PDT 24
Peak memory	572928 kb
Host	smart-bfee503b-8493-4e5b-8494-a9b95a78f016
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727800499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.2727800499
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2234206281
Short name	T2206
Test name
Test status
Simulation time	51129237 ps
CPU time	47.79 seconds
Started	May 23 04:29:45 PM PDT 24
Finished	May 23 04:30:34 PM PDT 24
Peak memory	563704 kb
Host	smart-f63c631e-cd55-43ef-bda6-2527018ad8e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234206281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.2234206281
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.309963608
Short name	T1594
Test name
Test status
Simulation time	699494747 ps
CPU time	33.35 seconds
Started	May 23 04:29:45 PM PDT 24
Finished	May 23 04:30:19 PM PDT 24
Peak memory	571836 kb
Host	smart-71d1509f-70cb-464c-86c6-f2bf25dc63d6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309963608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.309963608
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_access_same_device.3434049629
Short name	T1388
Test name
Test status
Simulation time	3412892941 ps
CPU time	141.29 seconds
Started	May 23 04:29:44 PM PDT 24
Finished	May 23 04:32:06 PM PDT 24
Peak memory	571980 kb
Host	smart-13d3fc9a-0761-45b6-b5cd-4a26a5912251
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434049629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .3434049629
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2153610516
Short name	T2790
Test name
Test status
Simulation time	30091640380 ps
CPU time	507.62 seconds
Started	May 23 04:29:48 PM PDT 24
Finished	May 23 04:38:16 PM PDT 24
Peak memory	571984 kb
Host	smart-1a2a62e4-2655-42e1-a8a4-56210ecb4a1c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153610516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.2153610516
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2597651897
Short name	T1336
Test name
Test status
Simulation time	979895996 ps
CPU time	52.54 seconds
Started	May 23 04:29:51 PM PDT 24
Finished	May 23 04:30:45 PM PDT 24
Peak memory	571800 kb
Host	smart-69ec7924-2d93-4ece-8342-276929bdb6b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597651897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.2597651897
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_error_random.2858542201
Short name	T2698
Test name
Test status
Simulation time	605544876 ps
CPU time	56.19 seconds
Started	May 23 04:29:45 PM PDT 24
Finished	May 23 04:30:42 PM PDT 24
Peak memory	571804 kb
Host	smart-bacb9cf9-dac3-4488-93e0-7438bbecbb6f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858542201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2858542201
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_random.2575105891
Short name	T566
Test name
Test status
Simulation time	189629413 ps
CPU time	19.31 seconds
Started	May 23 04:29:45 PM PDT 24
Finished	May 23 04:30:05 PM PDT 24
Peak memory	571776 kb
Host	smart-0635301e-067f-4192-9d1a-5d7f667e3412
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575105891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.2575105891
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2038256675
Short name	T1809
Test name
Test status
Simulation time	6581301670 ps
CPU time	77.3 seconds
Started	May 23 04:29:45 PM PDT 24
Finished	May 23 04:31:03 PM PDT 24
Peak memory	563780 kb
Host	smart-1e9c503a-c4bd-4a37-8fde-e3f513d646cc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038256675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2038256675
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.3102682666
Short name	T456
Test name
Test status
Simulation time	38199449256 ps
CPU time	753.05 seconds
Started	May 23 04:29:48 PM PDT 24
Finished	May 23 04:42:22 PM PDT 24
Peak memory	572036 kb
Host	smart-19de1b59-641e-47dd-afce-1db4f00e93a4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102682666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3102682666
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.86661306
Short name	T483
Test name
Test status
Simulation time	434554861 ps
CPU time	47.42 seconds
Started	May 23 04:29:45 PM PDT 24
Finished	May 23 04:30:33 PM PDT 24
Peak memory	571792 kb
Host	smart-0c17de40-af34-4577-b927-b064fd41497e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86661306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delay s.86661306
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_same_source.1469196769
Short name	T1651
Test name
Test status
Simulation time	417980473 ps
CPU time	35.24 seconds
Started	May 23 04:29:48 PM PDT 24
Finished	May 23 04:30:24 PM PDT 24
Peak memory	571848 kb
Host	smart-b971c9fd-7617-42df-a948-8f7d48c5ab0f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469196769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1469196769
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke.141382279
Short name	T2278
Test name
Test status
Simulation time	261814373 ps
CPU time	10.98 seconds
Started	May 23 04:29:51 PM PDT 24
Finished	May 23 04:30:03 PM PDT 24
Peak memory	563612 kb
Host	smart-4fa9c86c-b2c2-441c-8b52-3a4e8acc0c7c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141382279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.141382279
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.437030486
Short name	T2283
Test name
Test status
Simulation time	7061597066 ps
CPU time	72.92 seconds
Started	May 23 04:29:44 PM PDT 24
Finished	May 23 04:30:58 PM PDT 24
Peak memory	563772 kb
Host	smart-ae747657-d6dc-4d0f-81e0-cb9eea9d4c50
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437030486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.437030486
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1449353704
Short name	T2387
Test name
Test status
Simulation time	5380407817 ps
CPU time	96.83 seconds
Started	May 23 04:29:44 PM PDT 24
Finished	May 23 04:31:22 PM PDT 24
Peak memory	563732 kb
Host	smart-acc926b2-86ef-4641-be6f-fbd299780771
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449353704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1449353704
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.303105904
Short name	T1352
Test name
Test status
Simulation time	39185756 ps
CPU time	6.54 seconds
Started	May 23 04:29:47 PM PDT 24
Finished	May 23 04:29:54 PM PDT 24
Peak memory	563492 kb
Host	smart-08e10fcf-8510-4b42-8f01-064c8dc66dbe
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303105904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays .303105904
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all.2425409263
Short name	T2574
Test name
Test status
Simulation time	1435125345 ps
CPU time	99.31 seconds
Started	May 23 04:29:47 PM PDT 24
Finished	May 23 04:31:27 PM PDT 24
Peak memory	572316 kb
Host	smart-4b5328d2-c3bc-44ea-8308-8fe88d71f843
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425409263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2425409263
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.84893052
Short name	T2288
Test name
Test status
Simulation time	5122019574 ps
CPU time	210.75 seconds
Started	May 23 04:29:47 PM PDT 24
Finished	May 23 04:33:18 PM PDT 24
Peak memory	572004 kb
Host	smart-ad797d8f-76a0-4609-b3ef-08ca75aa1fa6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84893052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.84893052
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2457128967
Short name	T2656
Test name
Test status
Simulation time	132161225 ps
CPU time	63.35 seconds
Started	May 23 04:29:48 PM PDT 24
Finished	May 23 04:30:52 PM PDT 24
Peak memory	572080 kb
Host	smart-9f1b7d31-4a6b-49e0-adba-9cd29758cb0b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457128967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.2457128967
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3235508888
Short name	T1315
Test name
Test status
Simulation time	22311584 ps
CPU time	31.75 seconds
Started	May 23 04:29:47 PM PDT 24
Finished	May 23 04:30:20 PM PDT 24
Peak memory	563728 kb
Host	smart-19f573de-8514-461c-9a65-c0df414142ec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235508888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.3235508888
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.3308648520
Short name	T1869
Test name
Test status
Simulation time	382856226 ps
CPU time	18.79 seconds
Started	May 23 04:29:45 PM PDT 24
Finished	May 23 04:30:05 PM PDT 24
Peak memory	571784 kb
Host	smart-7b7941c1-7b51-4938-be6f-705dbe69ee3f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308648520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3308648520
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_access_same_device.2400473437
Short name	T2400
Test name
Test status
Simulation time	413342873 ps
CPU time	20.08 seconds
Started	May 23 04:29:58 PM PDT 24
Finished	May 23 04:30:19 PM PDT 24
Peak memory	563612 kb
Host	smart-5ae05b2f-7add-48e6-84d0-1618d603196f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400473437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .2400473437
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.615027148
Short name	T1862
Test name
Test status
Simulation time	14626812985 ps
CPU time	261.66 seconds
Started	May 23 04:29:58 PM PDT 24
Finished	May 23 04:34:21 PM PDT 24
Peak memory	572072 kb
Host	smart-06be890d-3f6b-4697-b06c-8a5c64d5503b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615027148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_d evice_slow_rsp.615027148
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.160200577
Short name	T1868
Test name
Test status
Simulation time	18931215 ps
CPU time	5.62 seconds
Started	May 23 04:30:01 PM PDT 24
Finished	May 23 04:30:08 PM PDT 24
Peak memory	563572 kb
Host	smart-d9e45688-36cf-4610-9878-4465f80aca8c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160200577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr .160200577
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_error_random.582869239
Short name	T2312
Test name
Test status
Simulation time	904876558 ps
CPU time	35.68 seconds
Started	May 23 04:29:59 PM PDT 24
Finished	May 23 04:30:35 PM PDT 24
Peak memory	571720 kb
Host	smart-f4b9685b-09a9-48f6-9f57-87a819db7d79
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582869239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.582869239
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_random.2922318792
Short name	T1508
Test name
Test status
Simulation time	1433530258 ps
CPU time	60.61 seconds
Started	May 23 04:30:00 PM PDT 24
Finished	May 23 04:31:02 PM PDT 24
Peak memory	571832 kb
Host	smart-0269aaf1-5e29-43dc-b428-b74331c2cb1d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922318792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.2922318792
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_random_large_delays.493251759
Short name	T1925
Test name
Test status
Simulation time	9428992428 ps
CPU time	108.08 seconds
Started	May 23 04:29:59 PM PDT 24
Finished	May 23 04:31:48 PM PDT 24
Peak memory	563856 kb
Host	smart-5004846c-cba0-4e90-b458-bb8c9f5eda34
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493251759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.493251759
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.400966905
Short name	T400
Test name
Test status
Simulation time	39349220510 ps
CPU time	772.93 seconds
Started	May 23 04:29:58 PM PDT 24
Finished	May 23 04:42:52 PM PDT 24
Peak memory	572044 kb
Host	smart-f41999d7-f02b-456e-9fb6-851550abfa2e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400966905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.400966905
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.2143036005
Short name	T1427
Test name
Test status
Simulation time	38687293 ps
CPU time	6.86 seconds
Started	May 23 04:30:03 PM PDT 24
Finished	May 23 04:30:11 PM PDT 24
Peak memory	563496 kb
Host	smart-437dedf1-c04f-45f0-a887-c598a71463e8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143036005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.2143036005
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_same_source.3110903309
Short name	T429
Test name
Test status
Simulation time	1600974250 ps
CPU time	55.24 seconds
Started	May 23 04:30:03 PM PDT 24
Finished	May 23 04:30:59 PM PDT 24
Peak memory	571824 kb
Host	smart-2c0b0e32-273d-452b-ba75-92a31bc359ce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110903309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3110903309
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke.1971046099
Short name	T2066
Test name
Test status
Simulation time	48494084 ps
CPU time	6.64 seconds
Started	May 23 04:29:48 PM PDT 24
Finished	May 23 04:29:55 PM PDT 24
Peak memory	563480 kb
Host	smart-cc6234f4-5ec3-43a6-91da-d6699b2479cb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971046099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1971046099
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.3220243735
Short name	T1265
Test name
Test status
Simulation time	5881057730 ps
CPU time	63.19 seconds
Started	May 23 04:30:01 PM PDT 24
Finished	May 23 04:31:06 PM PDT 24
Peak memory	563760 kb
Host	smart-aff3f697-56e5-4363-8b7b-bc2618419bd8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220243735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3220243735
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3856359972
Short name	T1604
Test name
Test status
Simulation time	3884393428 ps
CPU time	66.7 seconds
Started	May 23 04:29:58 PM PDT 24
Finished	May 23 04:31:05 PM PDT 24
Peak memory	563676 kb
Host	smart-4ea63e84-8b64-45a1-9400-efc7455e651d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856359972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3856359972
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.2910156464
Short name	T2757
Test name
Test status
Simulation time	49438736 ps
CPU time	6.59 seconds
Started	May 23 04:29:47 PM PDT 24
Finished	May 23 04:29:55 PM PDT 24
Peak memory	563548 kb
Host	smart-a7e1a4a6-a2cc-43bd-8182-4badce60e7f9
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910156464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.2910156464
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all.256962502
Short name	T1523
Test name
Test status
Simulation time	3030269049 ps
CPU time	131.73 seconds
Started	May 23 04:29:57 PM PDT 24
Finished	May 23 04:32:10 PM PDT 24
Peak memory	572028 kb
Host	smart-f8bb7e80-ee52-413f-b7ac-2f62aed46e0e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256962502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.256962502
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1230388000
Short name	T2079
Test name
Test status
Simulation time	2542012118 ps
CPU time	280.34 seconds
Started	May 23 04:30:02 PM PDT 24
Finished	May 23 04:34:43 PM PDT 24
Peak memory	572808 kb
Host	smart-70ba6eef-dbd1-4e2f-8973-254562a404b4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230388000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.1230388000
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1423084890
Short name	T1339
Test name
Test status
Simulation time	68909025 ps
CPU time	10.91 seconds
Started	May 23 04:29:59 PM PDT 24
Finished	May 23 04:30:11 PM PDT 24
Peak memory	571812 kb
Host	smart-5ad0fa7a-442b-4c12-8a5a-23a1a6666a32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423084890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1423084890
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_access_same_device.2546299085
Short name	T2768
Test name
Test status
Simulation time	1318413319 ps
CPU time	61.25 seconds
Started	May 23 04:30:13 PM PDT 24
Finished	May 23 04:31:15 PM PDT 24
Peak memory	571860 kb
Host	smart-df13d974-4dcd-41a5-ba09-bb55f376dc6f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546299085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .2546299085
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2146797571
Short name	T797
Test name
Test status
Simulation time	5391067966 ps
CPU time	99.63 seconds
Started	May 23 04:30:15 PM PDT 24
Finished	May 23 04:31:55 PM PDT 24
Peak memory	572040 kb
Host	smart-30b412a5-ecd5-4540-8c29-1186426c9a3f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146797571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.2146797571
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.670325007
Short name	T1677
Test name
Test status
Simulation time	76261053 ps
CPU time	7.18 seconds
Started	May 23 04:30:12 PM PDT 24
Finished	May 23 04:30:21 PM PDT 24
Peak memory	563568 kb
Host	smart-5f7b0e90-b56a-4956-8ece-85dc257811e1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670325007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr .670325007
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_error_random.236077552
Short name	T1342
Test name
Test status
Simulation time	784778554 ps
CPU time	28.32 seconds
Started	May 23 04:30:12 PM PDT 24
Finished	May 23 04:30:42 PM PDT 24
Peak memory	571792 kb
Host	smart-0421815b-a4bb-4c4c-9364-e5124fb6fab3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236077552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.236077552
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_random.3043820432
Short name	T461
Test name
Test status
Simulation time	223862382 ps
CPU time	23.37 seconds
Started	May 23 04:29:59 PM PDT 24
Finished	May 23 04:30:23 PM PDT 24
Peak memory	571748 kb
Host	smart-8c6758fe-9ff3-4f11-8bc0-7220a9700290
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043820432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.3043820432
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_random_large_delays.1415302944
Short name	T2157
Test name
Test status
Simulation time	83131711001 ps
CPU time	970.17 seconds
Started	May 23 04:30:12 PM PDT 24
Finished	May 23 04:46:24 PM PDT 24
Peak memory	572056 kb
Host	smart-30135ccb-a723-4b71-878e-d0c1531ec683
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415302944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1415302944
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.2145015349
Short name	T1733
Test name
Test status
Simulation time	46525062956 ps
CPU time	813.07 seconds
Started	May 23 04:30:12 PM PDT 24
Finished	May 23 04:43:46 PM PDT 24
Peak memory	572036 kb
Host	smart-2ab3ef84-01f7-4df5-9b02-0b77a82bba34
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145015349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2145015349
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3448476738
Short name	T1507
Test name
Test status
Simulation time	223129722 ps
CPU time	24.62 seconds
Started	May 23 04:30:00 PM PDT 24
Finished	May 23 04:30:26 PM PDT 24
Peak memory	571792 kb
Host	smart-ab79b8ac-2bc2-4a69-9f0a-4864242330a3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448476738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.3448476738
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_same_source.1318457185
Short name	T2302
Test name
Test status
Simulation time	663525545 ps
CPU time	22.32 seconds
Started	May 23 04:30:14 PM PDT 24
Finished	May 23 04:30:37 PM PDT 24
Peak memory	571716 kb
Host	smart-8233c968-a801-42fc-89d0-a91e1a88b0fb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318457185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1318457185
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke.1136961388
Short name	T507
Test name
Test status
Simulation time	125389635 ps
CPU time	7.73 seconds
Started	May 23 04:30:00 PM PDT 24
Finished	May 23 04:30:10 PM PDT 24
Peak memory	563508 kb
Host	smart-b992fbe9-4695-4bf6-abdd-0142f4f1f817
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136961388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1136961388
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3256578241
Short name	T1955
Test name
Test status
Simulation time	7765310016 ps
CPU time	86.56 seconds
Started	May 23 04:29:58 PM PDT 24
Finished	May 23 04:31:25 PM PDT 24
Peak memory	563732 kb
Host	smart-6ccf86d0-d221-4158-a571-b7cabeb0e09a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256578241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3256578241
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1508220198
Short name	T499
Test name
Test status
Simulation time	3238297460 ps
CPU time	59.55 seconds
Started	May 23 04:30:01 PM PDT 24
Finished	May 23 04:31:02 PM PDT 24
Peak memory	563760 kb
Host	smart-44ed8bee-2db5-4a2c-b771-73384b920422
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508220198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1508220198
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.622481065
Short name	T1243
Test name
Test status
Simulation time	58495524 ps
CPU time	7.4 seconds
Started	May 23 04:30:03 PM PDT 24
Finished	May 23 04:30:11 PM PDT 24
Peak memory	563564 kb
Host	smart-103d052e-0846-40de-9647-078c41668e8b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622481065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays .622481065
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all.3635327487
Short name	T2256
Test name
Test status
Simulation time	3516590393 ps
CPU time	147.8 seconds
Started	May 23 04:30:13 PM PDT 24
Finished	May 23 04:32:43 PM PDT 24
Peak memory	571968 kb
Host	smart-3a5415b5-7ebd-4218-9777-f9baaf27937a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635327487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3635327487
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.437816479
Short name	T1753
Test name
Test status
Simulation time	8515421095 ps
CPU time	340.83 seconds
Started	May 23 04:30:15 PM PDT 24
Finished	May 23 04:35:57 PM PDT 24
Peak memory	572684 kb
Host	smart-a44ff783-6144-40cd-9e03-e41431d91f9e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437816479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.437816479
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.472262047
Short name	T582
Test name
Test status
Simulation time	1221757545 ps
CPU time	319.33 seconds
Started	May 23 04:30:16 PM PDT 24
Finished	May 23 04:35:36 PM PDT 24
Peak memory	572952 kb
Host	smart-84b8223a-441a-4784-9f0f-7b0a4d189b64
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472262047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_ with_rand_reset.472262047
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.509157141
Short name	T2342
Test name
Test status
Simulation time	2413841110 ps
CPU time	264.6 seconds
Started	May 23 04:30:13 PM PDT 24
Finished	May 23 04:34:39 PM PDT 24
Peak memory	574140 kb
Host	smart-a875b76e-e1b0-4f2f-8592-0288766ffdc5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509157141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_reset_error.509157141
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.1084976896
Short name	T491
Test name
Test status
Simulation time	117561903 ps
CPU time	17.65 seconds
Started	May 23 04:30:14 PM PDT 24
Finished	May 23 04:30:33 PM PDT 24
Peak memory	571876 kb
Host	smart-c1bc0d77-b091-47df-a383-3a18cd11e953
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084976896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1084976896
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_access_same_device.1205325409
Short name	T2150
Test name
Test status
Simulation time	1413763579 ps
CPU time	66.64 seconds
Started	May 23 04:30:12 PM PDT 24
Finished	May 23 04:31:19 PM PDT 24
Peak memory	571876 kb
Host	smart-80acead5-06ab-410b-b9e8-0cb6a4a74c8d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205325409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1205325409
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3015772602
Short name	T2075
Test name
Test status
Simulation time	41060593122 ps
CPU time	708.71 seconds
Started	May 23 04:30:15 PM PDT 24
Finished	May 23 04:42:05 PM PDT 24
Peak memory	572020 kb
Host	smart-81920b16-81f9-4210-8cea-0a8b87e2cca5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015772602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.3015772602
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2007038170
Short name	T1494
Test name
Test status
Simulation time	1161826642 ps
CPU time	49.42 seconds
Started	May 23 04:30:35 PM PDT 24
Finished	May 23 04:31:25 PM PDT 24
Peak memory	571820 kb
Host	smart-639e92d8-2fcf-41fa-bf54-2755e30a63c8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007038170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.2007038170
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_error_random.1482306688
Short name	T2240
Test name
Test status
Simulation time	1069488528 ps
CPU time	40.93 seconds
Started	May 23 04:30:31 PM PDT 24
Finished	May 23 04:31:14 PM PDT 24
Peak memory	571848 kb
Host	smart-86a0756f-bdfe-4b31-a2bd-c6f2dba40357
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482306688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1482306688
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_random.1474574833
Short name	T2700
Test name
Test status
Simulation time	1396557377 ps
CPU time	52.49 seconds
Started	May 23 04:30:12 PM PDT 24
Finished	May 23 04:31:06 PM PDT 24
Peak memory	571780 kb
Host	smart-64d89ba1-5a33-474d-aee8-c707e133574f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474574833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.1474574833
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2044420279
Short name	T2580
Test name
Test status
Simulation time	87412814875 ps
CPU time	997.23 seconds
Started	May 23 04:30:12 PM PDT 24
Finished	May 23 04:46:51 PM PDT 24
Peak memory	572028 kb
Host	smart-9f0e6fb6-2906-4cb0-9abc-5087dea81477
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044420279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2044420279
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.1304589404
Short name	T436
Test name
Test status
Simulation time	65304634751 ps
CPU time	1109.72 seconds
Started	May 23 04:30:14 PM PDT 24
Finished	May 23 04:48:45 PM PDT 24
Peak memory	571996 kb
Host	smart-47d93404-23b2-43b5-9797-c9714083194a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304589404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1304589404
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.4118308289
Short name	T1420
Test name
Test status
Simulation time	252516548 ps
CPU time	25.21 seconds
Started	May 23 04:30:13 PM PDT 24
Finished	May 23 04:30:39 PM PDT 24
Peak memory	571824 kb
Host	smart-e9a62cba-2aa6-46dd-a1d2-5bc0fc33f12c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118308289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.4118308289
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_same_source.4196854399
Short name	T2766
Test name
Test status
Simulation time	329167532 ps
CPU time	28.04 seconds
Started	May 23 04:30:19 PM PDT 24
Finished	May 23 04:30:48 PM PDT 24
Peak memory	571712 kb
Host	smart-5b1c75e3-c491-413e-a8d4-d082145616a8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196854399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4196854399
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke.2590071100
Short name	T2073
Test name
Test status
Simulation time	134847486 ps
CPU time	7.59 seconds
Started	May 23 04:30:19 PM PDT 24
Finished	May 23 04:30:28 PM PDT 24
Peak memory	563472 kb
Host	smart-644b2c20-c5d1-4b0f-8541-f4f9e121efb4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590071100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2590071100
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3666377237
Short name	T2770
Test name
Test status
Simulation time	9224628909 ps
CPU time	97.77 seconds
Started	May 23 04:30:13 PM PDT 24
Finished	May 23 04:31:52 PM PDT 24
Peak memory	563760 kb
Host	smart-b0d6deb4-6817-4103-b17d-d168e356a785
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666377237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3666377237
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3596684284
Short name	T1283
Test name
Test status
Simulation time	5352854632 ps
CPU time	97.4 seconds
Started	May 23 04:30:16 PM PDT 24
Finished	May 23 04:31:55 PM PDT 24
Peak memory	563788 kb
Host	smart-c16324c7-a8e1-44fb-93af-59c080ad8dff
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596684284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3596684284
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3141046618
Short name	T1333
Test name
Test status
Simulation time	44678387 ps
CPU time	6.85 seconds
Started	May 23 04:30:15 PM PDT 24
Finished	May 23 04:30:23 PM PDT 24
Peak memory	563520 kb
Host	smart-44bd0120-da17-4482-b2a0-6d4a4d70e318
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141046618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.3141046618
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all.3423492464
Short name	T1621
Test name
Test status
Simulation time	1383866212 ps
CPU time	138.54 seconds
Started	May 23 04:30:26 PM PDT 24
Finished	May 23 04:32:45 PM PDT 24
Peak memory	571896 kb
Host	smart-46ace629-a327-478a-aa4c-3918853ac3d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423492464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3423492464
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.3869597815
Short name	T2472
Test name
Test status
Simulation time	1772972657 ps
CPU time	151.24 seconds
Started	May 23 04:30:26 PM PDT 24
Finished	May 23 04:32:58 PM PDT 24
Peak memory	571980 kb
Host	smart-63d88b9f-57cb-4502-8de4-93752cb5342a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869597815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3869597815
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3289637811
Short name	T2634
Test name
Test status
Simulation time	711941942 ps
CPU time	296.55 seconds
Started	May 23 04:30:27 PM PDT 24
Finished	May 23 04:35:25 PM PDT 24
Peak memory	572876 kb
Host	smart-1a9cba75-bbbd-4227-be7d-9e7a1d596ee7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289637811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.3289637811
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1486027877
Short name	T812
Test name
Test status
Simulation time	4052577407 ps
CPU time	327.4 seconds
Started	May 23 04:30:27 PM PDT 24
Finished	May 23 04:35:56 PM PDT 24
Peak memory	573168 kb
Host	smart-c40821b5-835c-43b0-8d05-fd80764643ed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486027877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.1486027877
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.3228420757
Short name	T1570
Test name
Test status
Simulation time	36510685 ps
CPU time	8 seconds
Started	May 23 04:30:28 PM PDT 24
Finished	May 23 04:30:37 PM PDT 24
Peak memory	563648 kb
Host	smart-c76acae2-2276-44a4-8034-cd12919e1a22
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228420757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3228420757
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_access_same_device.1036615155
Short name	T794
Test name
Test status
Simulation time	155151892 ps
CPU time	20.52 seconds
Started	May 23 04:30:27 PM PDT 24
Finished	May 23 04:30:49 PM PDT 24
Peak memory	571876 kb
Host	smart-3a61a8b0-5261-4107-b73f-bf7386d275e1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036615155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .1036615155
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.506483937
Short name	T805
Test name
Test status
Simulation time	137777934490 ps
CPU time	2299.85 seconds
Started	May 23 04:30:28 PM PDT 24
Finished	May 23 05:08:50 PM PDT 24
Peak memory	572016 kb
Host	smart-87886133-166c-4be3-8817-e11a6600fed3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506483937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_d evice_slow_rsp.506483937
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2317816501
Short name	T1907
Test name
Test status
Simulation time	1315137139 ps
CPU time	58.17 seconds
Started	May 23 04:30:42 PM PDT 24
Finished	May 23 04:31:41 PM PDT 24
Peak memory	571756 kb
Host	smart-8b8fbe1a-44f3-43c9-9652-3193b03a7d9d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317816501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.2317816501
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_error_random.3918863418
Short name	T2795
Test name
Test status
Simulation time	192460522 ps
CPU time	10.49 seconds
Started	May 23 04:30:28 PM PDT 24
Finished	May 23 04:30:40 PM PDT 24
Peak memory	563552 kb
Host	smart-52a8d5e8-ed0f-4119-a9f6-3c687faa5fce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918863418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3918863418
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_random.2859186863
Short name	T553
Test name
Test status
Simulation time	477059386 ps
CPU time	22.84 seconds
Started	May 23 04:30:28 PM PDT 24
Finished	May 23 04:30:52 PM PDT 24
Peak memory	571800 kb
Host	smart-fe48a5c4-f5da-42ed-bda0-dedd3bacf8ed
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859186863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.2859186863
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2448784946
Short name	T2407
Test name
Test status
Simulation time	73557376175 ps
CPU time	895.92 seconds
Started	May 23 04:30:28 PM PDT 24
Finished	May 23 04:45:25 PM PDT 24
Peak memory	572052 kb
Host	smart-f07a9385-ac3b-4cf1-b0df-45dfe72cc5b0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448784946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2448784946
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.1790232775
Short name	T2094
Test name
Test status
Simulation time	6951618799 ps
CPU time	136.67 seconds
Started	May 23 04:30:31 PM PDT 24
Finished	May 23 04:32:49 PM PDT 24
Peak memory	563824 kb
Host	smart-b6d2730b-0487-4169-959a-7b7a6e6dc0ad
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790232775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1790232775
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.714169380
Short name	T1728
Test name
Test status
Simulation time	587413326 ps
CPU time	58.66 seconds
Started	May 23 04:30:35 PM PDT 24
Finished	May 23 04:31:34 PM PDT 24
Peak memory	571788 kb
Host	smart-3ef2c84b-924f-487c-b5b1-f2275ffc344d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714169380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_dela ys.714169380
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_same_source.3554448289
Short name	T1784
Test name
Test status
Simulation time	2032535594 ps
CPU time	71.24 seconds
Started	May 23 04:30:31 PM PDT 24
Finished	May 23 04:31:44 PM PDT 24
Peak memory	571812 kb
Host	smart-7b42ca75-09b4-4298-b6d0-68bf9188d4fa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554448289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3554448289
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke.3883916544
Short name	T2522
Test name
Test status
Simulation time	218294839 ps
CPU time	10.11 seconds
Started	May 23 04:30:33 PM PDT 24
Finished	May 23 04:30:44 PM PDT 24
Peak memory	563500 kb
Host	smart-5381f67d-a0e0-4c0c-ab80-d84bf86ebf36
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883916544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3883916544
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.2715983900
Short name	T1347
Test name
Test status
Simulation time	7533065112 ps
CPU time	82.6 seconds
Started	May 23 04:30:28 PM PDT 24
Finished	May 23 04:31:53 PM PDT 24
Peak memory	563776 kb
Host	smart-53c73814-a3a4-4326-bb68-7a4198acd7c1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715983900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2715983900
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.652493361
Short name	T2106
Test name
Test status
Simulation time	4496209689 ps
CPU time	89 seconds
Started	May 23 04:30:28 PM PDT 24
Finished	May 23 04:31:58 PM PDT 24
Peak memory	563804 kb
Host	smart-deb9ac09-812e-4c48-981a-5299262e9084
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652493361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.652493361
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2125325784
Short name	T1266
Test name
Test status
Simulation time	45936202 ps
CPU time	6.55 seconds
Started	May 23 04:30:34 PM PDT 24
Finished	May 23 04:30:41 PM PDT 24
Peak memory	563528 kb
Host	smart-cab33246-855d-4e15-b122-cb095585828f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125325784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.2125325784
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all.642615552
Short name	T1533
Test name
Test status
Simulation time	2093479489 ps
CPU time	76.03 seconds
Started	May 23 04:30:38 PM PDT 24
Finished	May 23 04:31:55 PM PDT 24
Peak memory	571880 kb
Host	smart-49537b97-b794-4715-a67f-96496fc21e50
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642615552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.642615552
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1225000114
Short name	T2024
Test name
Test status
Simulation time	9925951236 ps
CPU time	405.3 seconds
Started	May 23 04:30:40 PM PDT 24
Finished	May 23 04:37:26 PM PDT 24
Peak memory	572916 kb
Host	smart-f248d1c5-82b8-4291-a571-92828c18a0a1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225000114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1225000114
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.2272612403
Short name	T1942
Test name
Test status
Simulation time	13127486134 ps
CPU time	829.26 seconds
Started	May 23 04:30:44 PM PDT 24
Finished	May 23 04:44:34 PM PDT 24
Peak memory	573068 kb
Host	smart-62a73b44-5009-42d1-bc47-1b2368342cca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272612403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.2272612403
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.2470007958
Short name	T789
Test name
Test status
Simulation time	2138767433 ps
CPU time	345.15 seconds
Started	May 23 04:30:40 PM PDT 24
Finished	May 23 04:36:27 PM PDT 24
Peak memory	572944 kb
Host	smart-6262326b-a336-4207-84c4-75366401db79
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470007958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.2470007958
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1363421241
Short name	T2550
Test name
Test status
Simulation time	144540651 ps
CPU time	18.93 seconds
Started	May 23 04:30:39 PM PDT 24
Finished	May 23 04:31:00 PM PDT 24
Peak memory	571884 kb
Host	smart-0499d142-722d-47e9-903b-a98df4ec8148
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363421241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1363421241
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_access_same_device.1283267370
Short name	T1625
Test name
Test status
Simulation time	539049137 ps
CPU time	46.09 seconds
Started	May 23 04:30:41 PM PDT 24
Finished	May 23 04:31:28 PM PDT 24
Peak memory	571828 kb
Host	smart-ff0ce1ab-2964-4c8c-b930-69f623166606
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283267370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .1283267370
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3151604496
Short name	T2264
Test name
Test status
Simulation time	55108874321 ps
CPU time	964.65 seconds
Started	May 23 04:30:42 PM PDT 24
Finished	May 23 04:46:48 PM PDT 24
Peak memory	571980 kb
Host	smart-655758f9-9dc3-4dda-b277-b077b5cdd8dd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151604496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.3151604496
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3796636492
Short name	T1631
Test name
Test status
Simulation time	1243129735 ps
CPU time	55.76 seconds
Started	May 23 04:30:42 PM PDT 24
Finished	May 23 04:31:39 PM PDT 24
Peak memory	571768 kb
Host	smart-ca222497-2313-4b7d-8139-44e94d3bbe48
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796636492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3796636492
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_error_random.4024394569
Short name	T1466
Test name
Test status
Simulation time	49941411 ps
CPU time	7.93 seconds
Started	May 23 04:30:43 PM PDT 24
Finished	May 23 04:30:52 PM PDT 24
Peak memory	563628 kb
Host	smart-b904c5e7-e0c8-4911-890c-42ba5a8bb079
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024394569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4024394569
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_random.2985688234
Short name	T1798
Test name
Test status
Simulation time	421167277 ps
CPU time	41.04 seconds
Started	May 23 04:30:40 PM PDT 24
Finished	May 23 04:31:22 PM PDT 24
Peak memory	571764 kb
Host	smart-d476335a-ae41-4f31-8c1d-c9909738c1eb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985688234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.2985688234
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_random_large_delays.948150388
Short name	T1840
Test name
Test status
Simulation time	38754892584 ps
CPU time	446.69 seconds
Started	May 23 04:30:40 PM PDT 24
Finished	May 23 04:38:08 PM PDT 24
Peak memory	572020 kb
Host	smart-2c8d2005-6659-48fe-a748-ec64b4ea8966
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948150388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.948150388
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.1310987207
Short name	T555
Test name
Test status
Simulation time	34373041066 ps
CPU time	611.58 seconds
Started	May 23 04:30:42 PM PDT 24
Finished	May 23 04:40:55 PM PDT 24
Peak memory	571996 kb
Host	smart-07c05373-de7e-4ba5-aaa3-dce86ef5c7d4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310987207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1310987207
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2062356144
Short name	T534
Test name
Test status
Simulation time	503986009 ps
CPU time	49.45 seconds
Started	May 23 04:30:44 PM PDT 24
Finished	May 23 04:31:34 PM PDT 24
Peak memory	571836 kb
Host	smart-9ed8a0c4-0201-4a89-8906-af4ca22b6e77
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062356144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.2062356144
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_same_source.2377604727
Short name	T2207
Test name
Test status
Simulation time	550916805 ps
CPU time	19.31 seconds
Started	May 23 04:30:41 PM PDT 24
Finished	May 23 04:31:02 PM PDT 24
Peak memory	571816 kb
Host	smart-c3d0b06f-cc80-4da2-9641-7cf8285b8520
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377604727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2377604727
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke.270566805
Short name	T2368
Test name
Test status
Simulation time	231101819 ps
CPU time	10.21 seconds
Started	May 23 04:30:41 PM PDT 24
Finished	May 23 04:30:53 PM PDT 24
Peak memory	563548 kb
Host	smart-31a4064f-b663-434c-aeaa-0d140b2a6ef2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270566805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.270566805
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.3323172323
Short name	T1370
Test name
Test status
Simulation time	7488501837 ps
CPU time	86.52 seconds
Started	May 23 04:30:43 PM PDT 24
Finished	May 23 04:32:11 PM PDT 24
Peak memory	563784 kb
Host	smart-3e24c51c-7a6b-4bf8-9ac6-f5814e446572
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323172323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3323172323
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.528734645
Short name	T2282
Test name
Test status
Simulation time	5505506618 ps
CPU time	92 seconds
Started	May 23 04:30:43 PM PDT 24
Finished	May 23 04:32:16 PM PDT 24
Peak memory	563744 kb
Host	smart-296d51d7-62a9-4935-bf4b-89346e4e7fae
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528734645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.528734645
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2305087414
Short name	T1629
Test name
Test status
Simulation time	48721215 ps
CPU time	7.19 seconds
Started	May 23 04:30:39 PM PDT 24
Finished	May 23 04:30:48 PM PDT 24
Peak memory	563560 kb
Host	smart-94b45baf-eb8b-4185-bbbd-7eaa858dd16c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305087414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.2305087414
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all.3985722236
Short name	T2180
Test name
Test status
Simulation time	3139341209 ps
CPU time	138.13 seconds
Started	May 23 04:30:40 PM PDT 24
Finished	May 23 04:32:59 PM PDT 24
Peak memory	571964 kb
Host	smart-4d689d64-5875-42ad-8183-fb04fea7116a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985722236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3985722236
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.2513096225
Short name	T1595
Test name
Test status
Simulation time	6488452508 ps
CPU time	253.64 seconds
Started	May 23 04:30:41 PM PDT 24
Finished	May 23 04:34:56 PM PDT 24
Peak memory	572028 kb
Host	smart-ab1bdc85-bfaa-42f1-a8d2-38cc25230f1e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513096225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2513096225
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.4056925838
Short name	T2706
Test name
Test status
Simulation time	713876813 ps
CPU time	230.03 seconds
Started	May 23 04:30:59 PM PDT 24
Finished	May 23 04:34:51 PM PDT 24
Peak memory	574040 kb
Host	smart-06f53fef-5ebb-4d69-9463-c149c12771f2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056925838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.4056925838
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.1110271430
Short name	T1660
Test name
Test status
Simulation time	1181679541 ps
CPU time	55.14 seconds
Started	May 23 04:30:41 PM PDT 24
Finished	May 23 04:31:37 PM PDT 24
Peak memory	571816 kb
Host	smart-e7dcb7e9-f41f-473e-8acf-4e1eee50fa96
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110271430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1110271430
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_access_same_device.4158518088
Short name	T1436
Test name
Test status
Simulation time	3126459330 ps
CPU time	142.82 seconds
Started	May 23 04:30:58 PM PDT 24
Finished	May 23 04:33:22 PM PDT 24
Peak memory	571992 kb
Host	smart-37f4bc8a-c78b-4f28-9aab-36a3ac2d9ffc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158518088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .4158518088
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2904165314
Short name	T1948
Test name
Test status
Simulation time	125655656282 ps
CPU time	2101.89 seconds
Started	May 23 04:30:59 PM PDT 24
Finished	May 23 05:06:02 PM PDT 24
Peak memory	572044 kb
Host	smart-5f71c189-7ff3-4d28-8beb-1c69ecb0ccbc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904165314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.2904165314
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3487497661
Short name	T1442
Test name
Test status
Simulation time	71640013 ps
CPU time	6.52 seconds
Started	May 23 04:30:57 PM PDT 24
Finished	May 23 04:31:05 PM PDT 24
Peak memory	563512 kb
Host	smart-94e8d17e-8cd8-4b3d-9ec4-60eb0d67296c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487497661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.3487497661
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_error_random.3313855820
Short name	T1914
Test name
Test status
Simulation time	422949464 ps
CPU time	38.02 seconds
Started	May 23 04:30:58 PM PDT 24
Finished	May 23 04:31:37 PM PDT 24
Peak memory	571804 kb
Host	smart-2525db0f-3a9c-4a86-b967-9f3ebb7d90b5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313855820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3313855820
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_random.604034707
Short name	T1639
Test name
Test status
Simulation time	671173870 ps
CPU time	29.19 seconds
Started	May 23 04:30:59 PM PDT 24
Finished	May 23 04:31:30 PM PDT 24
Peak memory	571788 kb
Host	smart-ced7bdd4-f2bd-4b5f-bbf0-9ab46934581c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604034707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.604034707
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_random_large_delays.2336472720
Short name	T1409
Test name
Test status
Simulation time	81209925044 ps
CPU time	861.15 seconds
Started	May 23 04:30:57 PM PDT 24
Finished	May 23 04:45:19 PM PDT 24
Peak memory	572052 kb
Host	smart-2f61ac77-ebdd-44a4-bd48-f34d76af3aae
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336472720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2336472720
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.1524057074
Short name	T2381
Test name
Test status
Simulation time	15107368236 ps
CPU time	247.2 seconds
Started	May 23 04:30:59 PM PDT 24
Finished	May 23 04:35:07 PM PDT 24
Peak memory	572020 kb
Host	smart-f8285b9e-5467-479a-91a5-9cff5e07880b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524057074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1524057074
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.2884761029
Short name	T1835
Test name
Test status
Simulation time	221695398 ps
CPU time	27.62 seconds
Started	May 23 04:30:57 PM PDT 24
Finished	May 23 04:31:26 PM PDT 24
Peak memory	571744 kb
Host	smart-da8f321e-9f63-4e8d-8a4a-f43480d39c77
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884761029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.2884761029
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_same_source.578357543
Short name	T2686
Test name
Test status
Simulation time	1200638582 ps
CPU time	39.18 seconds
Started	May 23 04:30:57 PM PDT 24
Finished	May 23 04:31:38 PM PDT 24
Peak memory	571780 kb
Host	smart-8d44b1a6-9fad-4de2-95cd-d41a5c14f259
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578357543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.578357543
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke.3170865583
Short name	T2398
Test name
Test status
Simulation time	236656616 ps
CPU time	10.66 seconds
Started	May 23 04:30:59 PM PDT 24
Finished	May 23 04:31:11 PM PDT 24
Peak memory	563492 kb
Host	smart-398afba8-01b0-40d6-b57a-e23092594571
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170865583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3170865583
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1959899230
Short name	T1302
Test name
Test status
Simulation time	5730746613 ps
CPU time	61.19 seconds
Started	May 23 04:30:57 PM PDT 24
Finished	May 23 04:31:59 PM PDT 24
Peak memory	563792 kb
Host	smart-f36a6ace-5781-499d-9dde-2ee68c0f99e4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959899230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1959899230
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.764030722
Short name	T1841
Test name
Test status
Simulation time	5804646872 ps
CPU time	99.24 seconds
Started	May 23 04:30:59 PM PDT 24
Finished	May 23 04:32:39 PM PDT 24
Peak memory	563688 kb
Host	smart-6cb0a822-6edf-4fbd-8772-8ee400912165
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764030722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.764030722
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2389637969
Short name	T1622
Test name
Test status
Simulation time	43535872 ps
CPU time	6.52 seconds
Started	May 23 04:30:58 PM PDT 24
Finished	May 23 04:31:06 PM PDT 24
Peak memory	563556 kb
Host	smart-ded60cb5-6ffa-4ad0-8f93-5aa58de0775d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389637969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2389637969
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all.3948840162
Short name	T1814
Test name
Test status
Simulation time	1948152186 ps
CPU time	91.55 seconds
Started	May 23 04:30:56 PM PDT 24
Finished	May 23 04:32:29 PM PDT 24
Peak memory	571896 kb
Host	smart-f8978767-0aab-48ee-9b33-35922158dd55
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948840162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3948840162
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.2410475213
Short name	T2749
Test name
Test status
Simulation time	926110597 ps
CPU time	41.95 seconds
Started	May 23 04:30:58 PM PDT 24
Finished	May 23 04:31:41 PM PDT 24
Peak memory	571828 kb
Host	smart-ac5ec556-bca6-42e7-9882-13f1b1679257
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410475213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2410475213
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.1465242108
Short name	T1787
Test name
Test status
Simulation time	206745750 ps
CPU time	87.33 seconds
Started	May 23 04:30:57 PM PDT 24
Finished	May 23 04:32:26 PM PDT 24
Peak memory	572376 kb
Host	smart-59931c44-1f91-4387-866a-5a1b44a56b21
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465242108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.1465242108
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1612695380
Short name	T1618
Test name
Test status
Simulation time	398819454 ps
CPU time	131.47 seconds
Started	May 23 04:31:00 PM PDT 24
Finished	May 23 04:33:13 PM PDT 24
Peak memory	572936 kb
Host	smart-6114840c-3d12-4453-9230-f164b01f943d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612695380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.1612695380
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.3450761528
Short name	T2131
Test name
Test status
Simulation time	1133711150 ps
CPU time	48.89 seconds
Started	May 23 04:31:01 PM PDT 24
Finished	May 23 04:31:51 PM PDT 24
Peak memory	571860 kb
Host	smart-765d6a65-a8d2-4155-871f-f39a42fed0d7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450761528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3450761528
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_access_same_device.308051227
Short name	T2195
Test name
Test status
Simulation time	1943611406 ps
CPU time	86.68 seconds
Started	May 23 04:31:19 PM PDT 24
Finished	May 23 04:32:47 PM PDT 24
Peak memory	571848 kb
Host	smart-8bfbc1d7-54dd-4e17-b5bc-3eb4984bf7f4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308051227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device. 308051227
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2822726363
Short name	T1687
Test name
Test status
Simulation time	129368266231 ps
CPU time	2083.8 seconds
Started	May 23 04:31:13 PM PDT 24
Finished	May 23 05:05:59 PM PDT 24
Peak memory	572076 kb
Host	smart-2cf205d7-ed8a-4c5f-830f-7e605071f8b6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822726363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.2822726363
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1582024901
Short name	T2629
Test name
Test status
Simulation time	269594227 ps
CPU time	30.62 seconds
Started	May 23 04:31:13 PM PDT 24
Finished	May 23 04:31:45 PM PDT 24
Peak memory	571844 kb
Host	smart-9cbcc86f-3298-460b-b4f7-85aa8792a94f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582024901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.1582024901
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_error_random.4064043869
Short name	T2443
Test name
Test status
Simulation time	331467179 ps
CPU time	14.79 seconds
Started	May 23 04:31:16 PM PDT 24
Finished	May 23 04:31:33 PM PDT 24
Peak memory	571792 kb
Host	smart-1176d8cb-d471-4e2c-acba-1c62249e7c06
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064043869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.4064043869
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_random.522440104
Short name	T2589
Test name
Test status
Simulation time	637344628 ps
CPU time	25.96 seconds
Started	May 23 04:31:13 PM PDT 24
Finished	May 23 04:31:41 PM PDT 24
Peak memory	571764 kb
Host	smart-862dc31a-1f44-47c6-aa47-6cf0c34ee061
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522440104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.522440104
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_random_large_delays.4090800903
Short name	T1695
Test name
Test status
Simulation time	16628324252 ps
CPU time	173.5 seconds
Started	May 23 04:31:15 PM PDT 24
Finished	May 23 04:34:10 PM PDT 24
Peak memory	572012 kb
Host	smart-da73f971-a875-4a47-ac69-2ccc81f0fc1f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090800903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.4090800903
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.1455179192
Short name	T1376
Test name
Test status
Simulation time	58366418675 ps
CPU time	1077.1 seconds
Started	May 23 04:31:17 PM PDT 24
Finished	May 23 04:49:16 PM PDT 24
Peak memory	572016 kb
Host	smart-df1ecb0a-68dd-4f18-b188-edeb72be75e6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455179192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1455179192
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.1352745953
Short name	T2762
Test name
Test status
Simulation time	423304879 ps
CPU time	40.32 seconds
Started	May 23 04:31:12 PM PDT 24
Finished	May 23 04:31:53 PM PDT 24
Peak memory	571836 kb
Host	smart-aa90ec8a-87e7-4b9a-96dd-f1100adc15eb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352745953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.1352745953
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_same_source.3853851532
Short name	T2379
Test name
Test status
Simulation time	847416377 ps
CPU time	30.14 seconds
Started	May 23 04:31:15 PM PDT 24
Finished	May 23 04:31:47 PM PDT 24
Peak memory	571772 kb
Host	smart-0fe6b6e8-a849-43cc-8365-b0068c2c8f99
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853851532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3853851532
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke.4135353486
Short name	T1718
Test name
Test status
Simulation time	195806717 ps
CPU time	9.56 seconds
Started	May 23 04:31:15 PM PDT 24
Finished	May 23 04:31:26 PM PDT 24
Peak memory	563548 kb
Host	smart-0ac275c8-eff2-4f6c-aeec-4cda05e776a1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135353486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.4135353486
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.4249998072
Short name	T1998
Test name
Test status
Simulation time	8459035081 ps
CPU time	98.01 seconds
Started	May 23 04:31:16 PM PDT 24
Finished	May 23 04:32:56 PM PDT 24
Peak memory	563680 kb
Host	smart-57c254a2-5e53-4866-9a13-893d22a464e2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249998072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.4249998072
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3941472462
Short name	T1478
Test name
Test status
Simulation time	5675818655 ps
CPU time	99.11 seconds
Started	May 23 04:31:16 PM PDT 24
Finished	May 23 04:32:57 PM PDT 24
Peak memory	563772 kb
Host	smart-7161815c-f9d8-42ce-82ab-8f4b30495b0e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941472462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3941472462
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.681426685
Short name	T1346
Test name
Test status
Simulation time	46452777 ps
CPU time	6.77 seconds
Started	May 23 04:31:14 PM PDT 24
Finished	May 23 04:31:22 PM PDT 24
Peak memory	563464 kb
Host	smart-2d3463b7-82f9-4ba6-b506-f5e00a8dc6f1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681426685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays .681426685
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all.3610741849
Short name	T2778
Test name
Test status
Simulation time	14053145934 ps
CPU time	574.2 seconds
Started	May 23 04:31:17 PM PDT 24
Finished	May 23 04:40:53 PM PDT 24
Peak memory	573028 kb
Host	smart-213b6762-4555-461d-aaf7-4da7dbb59cfd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610741849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3610741849
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.2092900392
Short name	T2076
Test name
Test status
Simulation time	2141674564 ps
CPU time	145.79 seconds
Started	May 23 04:31:17 PM PDT 24
Finished	May 23 04:33:45 PM PDT 24
Peak memory	571936 kb
Host	smart-70e4ece0-fe35-4631-b085-d383ca62df7a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092900392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2092900392
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2381867421
Short name	T822
Test name
Test status
Simulation time	4522539999 ps
CPU time	424.19 seconds
Started	May 23 04:31:17 PM PDT 24
Finished	May 23 04:38:23 PM PDT 24
Peak memory	574132 kb
Host	smart-c315fc5f-00d9-4eee-a6ac-c6b5e104fc88
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381867421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2381867421
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1018869376
Short name	T2769
Test name
Test status
Simulation time	1095283874 ps
CPU time	45.16 seconds
Started	May 23 04:31:14 PM PDT 24
Finished	May 23 04:32:01 PM PDT 24
Peak memory	571848 kb
Host	smart-d4f76fc7-d8bd-402f-ba52-37903ae70638
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018869376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1018869376
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_access_same_device.51235804
Short name	T2606
Test name
Test status
Simulation time	355714717 ps
CPU time	28.11 seconds
Started	May 23 04:31:14 PM PDT 24
Finished	May 23 04:31:44 PM PDT 24
Peak memory	571844 kb
Host	smart-5bd0fb45-8dcb-4a1d-a485-60d5e0b4f5e4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51235804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.51235804
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2030974161
Short name	T431
Test name
Test status
Simulation time	77025357864 ps
CPU time	1300.43 seconds
Started	May 23 04:31:13 PM PDT 24
Finished	May 23 04:52:55 PM PDT 24
Peak memory	572076 kb
Host	smart-7d05b60e-93c3-47b6-9fad-399b36a5903d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030974161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.2030974161
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1247547690
Short name	T2620
Test name
Test status
Simulation time	1062627678 ps
CPU time	47.81 seconds
Started	May 23 04:31:16 PM PDT 24
Finished	May 23 04:32:05 PM PDT 24
Peak memory	571864 kb
Host	smart-e180b912-65e0-4c8a-8db0-0ee65050a56b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247547690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.1247547690
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_error_random.3017845818
Short name	T2162
Test name
Test status
Simulation time	345447957 ps
CPU time	30.73 seconds
Started	May 23 04:31:16 PM PDT 24
Finished	May 23 04:31:49 PM PDT 24
Peak memory	571768 kb
Host	smart-b8542a15-63eb-4099-9c6d-17ad3a8e7c3a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017845818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3017845818
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_random.1418199942
Short name	T2143
Test name
Test status
Simulation time	549936119 ps
CPU time	24.4 seconds
Started	May 23 04:31:13 PM PDT 24
Finished	May 23 04:31:39 PM PDT 24
Peak memory	571804 kb
Host	smart-b9fa1d83-3ad5-4e31-97ed-995759a7f95a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418199942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1418199942
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_random_large_delays.1284551899
Short name	T550
Test name
Test status
Simulation time	23910530878 ps
CPU time	257.53 seconds
Started	May 23 04:31:18 PM PDT 24
Finished	May 23 04:35:37 PM PDT 24
Peak memory	572004 kb
Host	smart-a97e8306-a893-4744-8f39-176cf03f15d1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284551899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1284551899
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.1377548315
Short name	T2468
Test name
Test status
Simulation time	48467535195 ps
CPU time	815.7 seconds
Started	May 23 04:31:16 PM PDT 24
Finished	May 23 04:44:54 PM PDT 24
Peak memory	571992 kb
Host	smart-f7fda8d2-6f11-445e-a932-90fcbfa6fc05
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377548315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1377548315
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.651299686
Short name	T2763
Test name
Test status
Simulation time	66484393 ps
CPU time	9.31 seconds
Started	May 23 04:31:14 PM PDT 24
Finished	May 23 04:31:25 PM PDT 24
Peak memory	563568 kb
Host	smart-25247525-4d76-4fdc-bff4-e1db91e30340
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651299686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela ys.651299686
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_same_source.3242289554
Short name	T2033
Test name
Test status
Simulation time	1765243177 ps
CPU time	58.9 seconds
Started	May 23 04:31:17 PM PDT 24
Finished	May 23 04:32:18 PM PDT 24
Peak memory	571772 kb
Host	smart-b89d1516-6dda-4b85-b244-4eea4aa5126e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242289554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3242289554
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke.3963549129
Short name	T2411
Test name
Test status
Simulation time	249555029 ps
CPU time	10.94 seconds
Started	May 23 04:31:15 PM PDT 24
Finished	May 23 04:31:28 PM PDT 24
Peak memory	563556 kb
Host	smart-9ff87e58-6f51-42d3-adb3-80e543773ca5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963549129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3963549129
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.361078797
Short name	T478
Test name
Test status
Simulation time	10254935929 ps
CPU time	105.87 seconds
Started	May 23 04:31:16 PM PDT 24
Finished	May 23 04:33:03 PM PDT 24
Peak memory	563780 kb
Host	smart-41c65f84-ad2a-4b46-bcc0-10eebde364b8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361078797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.361078797
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1255942587
Short name	T2015
Test name
Test status
Simulation time	3865927756 ps
CPU time	70.85 seconds
Started	May 23 04:31:15 PM PDT 24
Finished	May 23 04:32:28 PM PDT 24
Peak memory	563680 kb
Host	smart-93951337-a512-4ea8-bc45-d2b640ba4fed
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255942587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1255942587
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.1955949834
Short name	T1646
Test name
Test status
Simulation time	51377026 ps
CPU time	7.18 seconds
Started	May 23 04:31:15 PM PDT 24
Finished	May 23 04:31:24 PM PDT 24
Peak memory	563572 kb
Host	smart-86189f5a-bf6c-4f7b-a7b1-d44c1dae7619
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955949834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.1955949834
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all.2812782210
Short name	T2691
Test name
Test status
Simulation time	1829797055 ps
CPU time	181.28 seconds
Started	May 23 04:31:15 PM PDT 24
Finished	May 23 04:34:18 PM PDT 24
Peak memory	572484 kb
Host	smart-1b9a2da4-cddf-4af2-93b4-1e7d508decfc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812782210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2812782210
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2844910932
Short name	T1344
Test name
Test status
Simulation time	565350308 ps
CPU time	56.16 seconds
Started	May 23 04:31:19 PM PDT 24
Finished	May 23 04:32:16 PM PDT 24
Peak memory	571900 kb
Host	smart-136449bf-24c3-4f7f-98c3-d33b8b971ea4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844910932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2844910932
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2965045479
Short name	T1697
Test name
Test status
Simulation time	83716893 ps
CPU time	41.13 seconds
Started	May 23 04:31:13 PM PDT 24
Finished	May 23 04:31:56 PM PDT 24
Peak memory	572224 kb
Host	smart-827b8a53-2849-4b4e-98af-6e12a5457c01
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965045479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.2965045479
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1158844760
Short name	T817
Test name
Test status
Simulation time	163472637 ps
CPU time	32.61 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:32:04 PM PDT 24
Peak memory	571880 kb
Host	smart-7351585b-b5a8-4748-b69d-41f14db926da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158844760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.1158844760
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1137084620
Short name	T2158
Test name
Test status
Simulation time	42484613 ps
CPU time	7.56 seconds
Started	May 23 04:31:16 PM PDT 24
Finished	May 23 04:31:26 PM PDT 24
Peak memory	563644 kb
Host	smart-7fb9b16a-c522-4c9f-965f-3648d399af5d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137084620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1137084620
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2031919921
Short name	T1745
Test name
Test status
Simulation time	63527682332 ps
CPU time	9330.58 seconds
Started	May 23 04:19:41 PM PDT 24
Finished	May 23 06:55:13 PM PDT 24
Peak memory	638304 kb
Host	smart-0d2cc404-a6ad-433b-9c2a-b6f163165af4
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031919921 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.2031919921
Directory	/workspace/4.chip_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.3758561386
Short name	T2750
Test name
Test status
Simulation time	6098736736 ps
CPU time	646.06 seconds
Started	May 23 04:19:26 PM PDT 24
Finished	May 23 04:30:12 PM PDT 24
Peak memory	585780 kb
Host	smart-b09b0cd7-46cd-44bf-b555-f8fdaae5e11d
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758561386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.3758561386
Directory	/workspace/4.chip_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_csr_rw.2497097101
Short name	T409
Test name
Test status
Simulation time	4805045966 ps
CPU time	454.66 seconds
Started	May 23 04:20:32 PM PDT 24
Finished	May 23 04:28:08 PM PDT 24
Peak memory	592272 kb
Host	smart-5a53acaa-c300-4017-aca8-b7f294da6146
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497097101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.2497097101
Directory	/workspace/4.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.1746855901
Short name	T373
Test name
Test status
Simulation time	27652134540 ps
CPU time	3499.01 seconds
Started	May 23 04:19:38 PM PDT 24
Finished	May 23 05:17:58 PM PDT 24
Peak memory	586708 kb
Host	smart-f6e17327-a56e-4aa1-9b3d-2fcd5be3cbd2
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746855901 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.1746855901
Directory	/workspace/4.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.chip_tl_errors.795425903
Short name	T2551
Test name
Test status
Simulation time	3360895349 ps
CPU time	242.38 seconds
Started	May 23 04:20:21 PM PDT 24
Finished	May 23 04:24:25 PM PDT 24
Peak memory	602132 kb
Host	smart-cf35d94d-4280-4804-8e5a-3f6f77eb77af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795425903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.795425903
Directory	/workspace/4.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_access_same_device.3457430494
Short name	T2755
Test name
Test status
Simulation time	1171261529 ps
CPU time	111.41 seconds
Started	May 23 04:21:22 PM PDT 24
Finished	May 23 04:23:14 PM PDT 24
Peak memory	571912 kb
Host	smart-fa7a678c-a9d0-4ffe-968b-c63a2f4baa2c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457430494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 3457430494
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.1804000544
Short name	T1950
Test name
Test status
Simulation time	48805956660 ps
CPU time	898.07 seconds
Started	May 23 04:20:19 PM PDT 24
Finished	May 23 04:35:18 PM PDT 24
Peak memory	572036 kb
Host	smart-fadd015b-525e-42f6-b63a-dd5bb4a6bd93
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804000544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.1804000544
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3519469509
Short name	T1669
Test name
Test status
Simulation time	239685400 ps
CPU time	32.22 seconds
Started	May 23 04:21:28 PM PDT 24
Finished	May 23 04:22:01 PM PDT 24
Peak memory	571756 kb
Host	smart-3e335c00-f03e-4161-aacf-ff83273aa7c2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519469509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .3519469509
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_error_random.2738839281
Short name	T1537
Test name
Test status
Simulation time	451815216 ps
CPU time	38.33 seconds
Started	May 23 04:20:18 PM PDT 24
Finished	May 23 04:20:57 PM PDT 24
Peak memory	571736 kb
Host	smart-85ab3ea4-5fad-4a4b-a0b0-a6e4b0fdaa95
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738839281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2738839281
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_random.1698556752
Short name	T2399
Test name
Test status
Simulation time	428365279 ps
CPU time	44.12 seconds
Started	May 23 04:19:54 PM PDT 24
Finished	May 23 04:20:40 PM PDT 24
Peak memory	571700 kb
Host	smart-a96ed176-a717-49aa-92ce-cb87814d1b87
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698556752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.1698556752
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1572564950
Short name	T1278
Test name
Test status
Simulation time	13724028452 ps
CPU time	154.69 seconds
Started	May 23 04:20:06 PM PDT 24
Finished	May 23 04:22:42 PM PDT 24
Peak memory	563840 kb
Host	smart-9a0b58e3-765e-4ad3-bfc0-ab19ec79b607
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572564950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1572564950
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.3727118224
Short name	T1808
Test name
Test status
Simulation time	61657803940 ps
CPU time	1178.61 seconds
Started	May 23 04:20:31 PM PDT 24
Finished	May 23 04:40:12 PM PDT 24
Peak memory	572000 kb
Host	smart-8d4c13a6-2d58-425b-8a79-7bbe451b712c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727118224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3727118224
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.295260125
Short name	T2611
Test name
Test status
Simulation time	59398589 ps
CPU time	9.6 seconds
Started	May 23 04:20:10 PM PDT 24
Finished	May 23 04:20:20 PM PDT 24
Peak memory	563608 kb
Host	smart-79919396-b412-4e15-bf04-29339a011898
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295260125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delay s.295260125
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_same_source.2475474925
Short name	T1902
Test name
Test status
Simulation time	1096657614 ps
CPU time	35.6 seconds
Started	May 23 04:20:26 PM PDT 24
Finished	May 23 04:21:02 PM PDT 24
Peak memory	571776 kb
Host	smart-6f46fcdc-6fdd-47c5-8839-40fec0cbd82a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475474925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2475474925
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke.4257332259
Short name	T1961
Test name
Test status
Simulation time	182374244 ps
CPU time	10.5 seconds
Started	May 23 04:19:44 PM PDT 24
Finished	May 23 04:19:56 PM PDT 24
Peak memory	563596 kb
Host	smart-2e3ed9b9-705c-4cce-8b5c-f79e58a4e68f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257332259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4257332259
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2308040665
Short name	T2530
Test name
Test status
Simulation time	5588025218 ps
CPU time	62.73 seconds
Started	May 23 04:19:54 PM PDT 24
Finished	May 23 04:20:57 PM PDT 24
Peak memory	563788 kb
Host	smart-30a0d872-6d62-4a74-aada-d56d8e0060e0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308040665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2308040665
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1427017409
Short name	T2676
Test name
Test status
Simulation time	5905315085 ps
CPU time	111.94 seconds
Started	May 23 04:20:05 PM PDT 24
Finished	May 23 04:21:58 PM PDT 24
Peak memory	563776 kb
Host	smart-793a1f73-d49f-4054-95ef-c6718c55f8f5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427017409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1427017409
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.759053592
Short name	T1815
Test name
Test status
Simulation time	54216787 ps
CPU time	6.78 seconds
Started	May 23 04:19:54 PM PDT 24
Finished	May 23 04:20:01 PM PDT 24
Peak memory	563564 kb
Host	smart-018c4a5c-bafc-4047-8494-46b8a2c13658
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759053592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays. 759053592
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.163959997
Short name	T2372
Test name
Test status
Simulation time	1547262859 ps
CPU time	138.59 seconds
Started	May 23 04:20:32 PM PDT 24
Finished	May 23 04:22:52 PM PDT 24
Peak memory	571948 kb
Host	smart-e1aba51d-c2a8-487a-9b95-01192e244430
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163959997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.163959997
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1460536422
Short name	T2154
Test name
Test status
Simulation time	9706460593 ps
CPU time	1137.17 seconds
Started	May 23 04:20:32 PM PDT 24
Finished	May 23 04:39:31 PM PDT 24
Peak memory	573016 kb
Host	smart-79714e7f-7904-4289-9f88-b26b041bc0bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460536422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.1460536422
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2028284355
Short name	T1876
Test name
Test status
Simulation time	360864429 ps
CPU time	120.63 seconds
Started	May 23 04:20:33 PM PDT 24
Finished	May 23 04:22:34 PM PDT 24
Peak memory	573980 kb
Host	smart-fbf9c2ce-24d4-4475-b275-0e0b5c75f175
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028284355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.2028284355
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.1310080307
Short name	T1765
Test name
Test status
Simulation time	780168718 ps
CPU time	34.94 seconds
Started	May 23 04:20:20 PM PDT 24
Finished	May 23 04:20:56 PM PDT 24
Peak memory	571868 kb
Host	smart-483d5d75-7fdb-4250-b499-5516d212a885
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310080307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1310080307
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_access_same_device.485094150
Short name	T809
Test name
Test status
Simulation time	816523469 ps
CPU time	35.87 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:32:07 PM PDT 24
Peak memory	571744 kb
Host	smart-e0cf52ee-0186-44e1-955c-a9ac0714d1ad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485094150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device. 485094150
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1403211788
Short name	T1428
Test name
Test status
Simulation time	1264323246 ps
CPU time	54.95 seconds
Started	May 23 04:31:34 PM PDT 24
Finished	May 23 04:32:30 PM PDT 24
Peak memory	571800 kb
Host	smart-6538fe69-4e3a-43fa-a7c5-43f8cca2d51d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403211788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.1403211788
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_error_random.2549724321
Short name	T1371
Test name
Test status
Simulation time	2296465815 ps
CPU time	91.32 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:33:03 PM PDT 24
Peak memory	571940 kb
Host	smart-a04dacdb-e58e-4490-9022-980d27138fe6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549724321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2549724321
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_random.455903550
Short name	T2504
Test name
Test status
Simulation time	929408343 ps
CPU time	35.95 seconds
Started	May 23 04:31:34 PM PDT 24
Finished	May 23 04:32:11 PM PDT 24
Peak memory	571760 kb
Host	smart-5a0a8e3c-9c5d-457b-be93-4e50dba64ad1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455903550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.455903550
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.4067709156
Short name	T2265
Test name
Test status
Simulation time	14010189862 ps
CPU time	264.38 seconds
Started	May 23 04:31:32 PM PDT 24
Finished	May 23 04:35:57 PM PDT 24
Peak memory	572020 kb
Host	smart-270e6faf-538c-4b92-9e6d-ab4fd82fb1a0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067709156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.4067709156
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1667757838
Short name	T1947
Test name
Test status
Simulation time	62866335 ps
CPU time	9.47 seconds
Started	May 23 04:31:32 PM PDT 24
Finished	May 23 04:31:42 PM PDT 24
Peak memory	563612 kb
Host	smart-cc07aa05-bcad-4d66-89fd-d24318998391
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667757838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1667757838
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_same_source.3445044738
Short name	T2571
Test name
Test status
Simulation time	50833436 ps
CPU time	7.85 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:31:39 PM PDT 24
Peak memory	563604 kb
Host	smart-8eec475a-f656-4021-9008-4f35b6714dc6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445044738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3445044738
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke.739183469
Short name	T1247
Test name
Test status
Simulation time	168765738 ps
CPU time	8.79 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:31:40 PM PDT 24
Peak memory	563572 kb
Host	smart-814de47e-10cb-4342-beb2-2b608c460115
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739183469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.739183469
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1279732447
Short name	T1377
Test name
Test status
Simulation time	7308451260 ps
CPU time	78.4 seconds
Started	May 23 04:31:36 PM PDT 24
Finished	May 23 04:32:55 PM PDT 24
Peak memory	563792 kb
Host	smart-18d21e10-a484-4073-b884-fa5152711600
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279732447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1279732447
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2347688704
Short name	T2135
Test name
Test status
Simulation time	4980827533 ps
CPU time	93.55 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:33:05 PM PDT 24
Peak memory	563748 kb
Host	smart-1badcd58-0c3b-4d07-8256-569ce158e126
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347688704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2347688704
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.4280012103
Short name	T1576
Test name
Test status
Simulation time	48087306 ps
CPU time	6.7 seconds
Started	May 23 04:31:32 PM PDT 24
Finished	May 23 04:31:40 PM PDT 24
Peak memory	563520 kb
Host	smart-db2048e6-1869-4c7d-86e5-7b25cc3aaa3e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280012103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.4280012103
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all.137139545
Short name	T427
Test name
Test status
Simulation time	1700683326 ps
CPU time	66.62 seconds
Started	May 23 04:31:29 PM PDT 24
Finished	May 23 04:32:37 PM PDT 24
Peak memory	571888 kb
Host	smart-33141306-5a7d-4227-9524-e913233f9ec1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137139545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.137139545
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.3656104766
Short name	T2531
Test name
Test status
Simulation time	3775739191 ps
CPU time	131.49 seconds
Started	May 23 04:31:34 PM PDT 24
Finished	May 23 04:33:47 PM PDT 24
Peak memory	572008 kb
Host	smart-51d237b6-04fb-49ab-a485-865161ae640c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656104766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3656104766
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3806678642
Short name	T2153
Test name
Test status
Simulation time	335341930 ps
CPU time	158.3 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:34:09 PM PDT 24
Peak memory	572880 kb
Host	smart-b0439cb0-a1e3-46d6-bea9-e304e3b1a074
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806678642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.3806678642
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2506381639
Short name	T827
Test name
Test status
Simulation time	4589872889 ps
CPU time	475.41 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:39:26 PM PDT 24
Peak memory	574164 kb
Host	smart-fcf8070f-4fb2-40ff-b0ff-54e9e85bfa80
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506381639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.2506381639
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.2755887589
Short name	T522
Test name
Test status
Simulation time	333651115 ps
CPU time	42.9 seconds
Started	May 23 04:31:35 PM PDT 24
Finished	May 23 04:32:19 PM PDT 24
Peak memory	571872 kb
Host	smart-ce1a92fa-2f54-4e8e-ba27-cce297dca894
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755887589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2755887589
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_access_same_device.2303865418
Short name	T1641
Test name
Test status
Simulation time	253785600 ps
CPU time	23.43 seconds
Started	May 23 04:31:33 PM PDT 24
Finished	May 23 04:31:58 PM PDT 24
Peak memory	563596 kb
Host	smart-45d868d6-4d3e-4921-b216-b41f04db7709
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303865418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .2303865418
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.3629500746
Short name	T2779
Test name
Test status
Simulation time	83648682747 ps
CPU time	1559.09 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:57:30 PM PDT 24
Peak memory	572072 kb
Host	smart-a1310720-ca1d-46df-822c-6f5280827a4e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629500746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.3629500746
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.4072701782
Short name	T1254
Test name
Test status
Simulation time	1218776618 ps
CPU time	49.33 seconds
Started	May 23 04:31:35 PM PDT 24
Finished	May 23 04:32:26 PM PDT 24
Peak memory	571808 kb
Host	smart-41d62df9-15a9-4fed-a597-adeabd93c5fa
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072701782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.4072701782
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_error_random.6813340
Short name	T1708
Test name
Test status
Simulation time	1543359327 ps
CPU time	55.9 seconds
Started	May 23 04:31:34 PM PDT 24
Finished	May 23 04:32:30 PM PDT 24
Peak memory	571800 kb
Host	smart-a2b878c4-0443-403a-b781-262138d1dc60
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6813340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.6813340
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_random.951551726
Short name	T2129
Test name
Test status
Simulation time	586452988 ps
CPU time	54.88 seconds
Started	May 23 04:31:32 PM PDT 24
Finished	May 23 04:32:27 PM PDT 24
Peak memory	571840 kb
Host	smart-e48500de-42b1-4aa8-89fa-f25de7356360
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951551726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.951551726
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2768482353
Short name	T1499
Test name
Test status
Simulation time	75013282282 ps
CPU time	848.35 seconds
Started	May 23 04:31:32 PM PDT 24
Finished	May 23 04:45:42 PM PDT 24
Peak memory	572052 kb
Host	smart-5ae23808-bd47-487b-81cb-1e755121e494
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768482353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2768482353
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.2201760913
Short name	T2679
Test name
Test status
Simulation time	37952338888 ps
CPU time	669.19 seconds
Started	May 23 04:31:32 PM PDT 24
Finished	May 23 04:42:42 PM PDT 24
Peak memory	572028 kb
Host	smart-f194e261-7474-4165-877f-130dd8d960d6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201760913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2201760913
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2281276224
Short name	T586
Test name
Test status
Simulation time	560273718 ps
CPU time	57.61 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:32:29 PM PDT 24
Peak memory	571824 kb
Host	smart-b0d15a25-c410-47b2-b800-1684182a945c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281276224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2281276224
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_same_source.1227035190
Short name	T1502
Test name
Test status
Simulation time	1120855964 ps
CPU time	39.2 seconds
Started	May 23 04:31:32 PM PDT 24
Finished	May 23 04:32:12 PM PDT 24
Peak memory	571796 kb
Host	smart-9a2bea35-b128-40a4-8e02-346f41c5f314
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227035190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1227035190
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke.2867884065
Short name	T1729
Test name
Test status
Simulation time	198037865 ps
CPU time	9.73 seconds
Started	May 23 04:31:30 PM PDT 24
Finished	May 23 04:31:41 PM PDT 24
Peak memory	563500 kb
Host	smart-61880d29-f440-4f63-b6fd-a5317ed51072
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867884065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2867884065
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.788008122
Short name	T1322
Test name
Test status
Simulation time	5956725693 ps
CPU time	68.13 seconds
Started	May 23 04:31:33 PM PDT 24
Finished	May 23 04:32:42 PM PDT 24
Peak memory	563760 kb
Host	smart-ba7cb9a2-2830-463d-85b0-ba2e7e9585d0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788008122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.788008122
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1702373047
Short name	T2385
Test name
Test status
Simulation time	5390259917 ps
CPU time	95.71 seconds
Started	May 23 04:31:36 PM PDT 24
Finished	May 23 04:33:13 PM PDT 24
Peak memory	563808 kb
Host	smart-d4c8fa60-734d-4c9f-a777-b5471ddbf54e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702373047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1702373047
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.1645758994
Short name	T1444
Test name
Test status
Simulation time	54504432 ps
CPU time	7.22 seconds
Started	May 23 04:31:31 PM PDT 24
Finished	May 23 04:31:39 PM PDT 24
Peak memory	563532 kb
Host	smart-61d9fdc9-b0a3-4f5b-becc-3ab8e7383637
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645758994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.1645758994
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all.3626667504
Short name	T2019
Test name
Test status
Simulation time	2767058546 ps
CPU time	212.31 seconds
Started	May 23 04:31:33 PM PDT 24
Finished	May 23 04:35:06 PM PDT 24
Peak memory	572928 kb
Host	smart-62acaf93-e7af-4930-af7c-787c1e54205e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626667504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3626667504
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1520477668
Short name	T1933
Test name
Test status
Simulation time	6048870292 ps
CPU time	244.62 seconds
Started	May 23 04:31:53 PM PDT 24
Finished	May 23 04:35:59 PM PDT 24
Peak memory	572024 kb
Host	smart-a338ec66-ffa1-46aa-9fc7-82170b20f3d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520477668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1520477668
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1347576117
Short name	T2616
Test name
Test status
Simulation time	461192464 ps
CPU time	146.04 seconds
Started	May 23 04:31:50 PM PDT 24
Finished	May 23 04:34:17 PM PDT 24
Peak memory	573772 kb
Host	smart-3c9b290c-4fb9-4784-8c83-c694ba28fff6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347576117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.1347576117
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.466806737
Short name	T1804
Test name
Test status
Simulation time	6177137365 ps
CPU time	665.16 seconds
Started	May 23 04:31:48 PM PDT 24
Finished	May 23 04:42:54 PM PDT 24
Peak memory	574072 kb
Host	smart-fc75a31a-e35a-4274-a484-fae972337122
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466806737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_reset_error.466806737
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.70620845
Short name	T2081
Test name
Test status
Simulation time	251420666 ps
CPU time	33.98 seconds
Started	May 23 04:31:35 PM PDT 24
Finished	May 23 04:32:10 PM PDT 24
Peak memory	571868 kb
Host	smart-726f93bd-c4aa-4a21-aeaa-4cb1e0a7b078
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70620845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.70620845
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_access_same_device.639515282
Short name	T1982
Test name
Test status
Simulation time	1345972736 ps
CPU time	72.58 seconds
Started	May 23 04:31:50 PM PDT 24
Finished	May 23 04:33:04 PM PDT 24
Peak memory	571872 kb
Host	smart-edb13b44-c54d-447d-b927-afe0263cf448
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639515282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device. 639515282
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.214843385
Short name	T2731
Test name
Test status
Simulation time	140173360002 ps
CPU time	2359.62 seconds
Started	May 23 04:31:53 PM PDT 24
Finished	May 23 05:11:14 PM PDT 24
Peak memory	572024 kb
Host	smart-c483704e-c07e-484b-a613-31c2f439e371
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214843385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.214843385
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.946330556
Short name	T2255
Test name
Test status
Simulation time	1051100957 ps
CPU time	43.86 seconds
Started	May 23 04:31:51 PM PDT 24
Finished	May 23 04:32:37 PM PDT 24
Peak memory	571764 kb
Host	smart-1c90f7d8-80eb-4abe-8f3e-a28cae915170
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946330556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr .946330556
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_error_random.3822062251
Short name	T1313
Test name
Test status
Simulation time	640758487 ps
CPU time	53.56 seconds
Started	May 23 04:31:52 PM PDT 24
Finished	May 23 04:32:47 PM PDT 24
Peak memory	571840 kb
Host	smart-5a677d0a-04f0-45cf-9125-b4541a0ddc6c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822062251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3822062251
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_random.1603182981
Short name	T501
Test name
Test status
Simulation time	2169976354 ps
CPU time	83.09 seconds
Started	May 23 04:31:52 PM PDT 24
Finished	May 23 04:33:16 PM PDT 24
Peak memory	571936 kb
Host	smart-c1c86f4c-ed7a-434c-8b34-7f62f3f63a30
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603182981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.1603182981
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_random_large_delays.2122838926
Short name	T1432
Test name
Test status
Simulation time	42655487108 ps
CPU time	498.4 seconds
Started	May 23 04:31:51 PM PDT 24
Finished	May 23 04:40:11 PM PDT 24
Peak memory	572048 kb
Host	smart-ff32238a-2564-4b7b-83d8-40d2ed707b4b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122838926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2122838926
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.4256336397
Short name	T2607
Test name
Test status
Simulation time	23985504233 ps
CPU time	404.77 seconds
Started	May 23 04:31:54 PM PDT 24
Finished	May 23 04:38:39 PM PDT 24
Peak memory	572032 kb
Host	smart-762e5dc2-16d6-47b4-9741-e4701adc9ab2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256336397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.4256336397
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.4116230283
Short name	T384
Test name
Test status
Simulation time	109275740 ps
CPU time	13.38 seconds
Started	May 23 04:31:57 PM PDT 24
Finished	May 23 04:32:12 PM PDT 24
Peak memory	571740 kb
Host	smart-6be06d33-f21c-4798-ad77-555d7cfe72fc
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116230283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.4116230283
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_same_source.423776843
Short name	T1412
Test name
Test status
Simulation time	1989355233 ps
CPU time	61.2 seconds
Started	May 23 04:31:53 PM PDT 24
Finished	May 23 04:32:55 PM PDT 24
Peak memory	571808 kb
Host	smart-8ea0f167-5dfd-4519-8452-1eaa19403486
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423776843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.423776843
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke.743875810
Short name	T1369
Test name
Test status
Simulation time	254387320 ps
CPU time	11.64 seconds
Started	May 23 04:31:53 PM PDT 24
Finished	May 23 04:32:06 PM PDT 24
Peak memory	563556 kb
Host	smart-4b2c5bdf-4c2d-45e0-a27c-df0241ba62b9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743875810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.743875810
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.4247125202
Short name	T1852
Test name
Test status
Simulation time	7432212922 ps
CPU time	85.54 seconds
Started	May 23 04:31:45 PM PDT 24
Finished	May 23 04:33:11 PM PDT 24
Peak memory	563728 kb
Host	smart-66495c3b-669c-4363-9ddd-7d73bfba7860
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247125202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.4247125202
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.4217191858
Short name	T2151
Test name
Test status
Simulation time	5896119690 ps
CPU time	101.51 seconds
Started	May 23 04:31:58 PM PDT 24
Finished	May 23 04:33:41 PM PDT 24
Peak memory	563708 kb
Host	smart-4f3f09f3-1d97-4667-9f61-6dda279bd8bd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217191858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.4217191858
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.972327903
Short name	T2714
Test name
Test status
Simulation time	41266268 ps
CPU time	6.76 seconds
Started	May 23 04:31:49 PM PDT 24
Finished	May 23 04:31:57 PM PDT 24
Peak memory	563564 kb
Host	smart-05142673-e2bc-496d-964d-2fe531b000c0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972327903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays .972327903
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all.1431408480
Short name	T1769
Test name
Test status
Simulation time	2331247530 ps
CPU time	204.84 seconds
Started	May 23 04:31:56 PM PDT 24
Finished	May 23 04:35:23 PM PDT 24
Peak memory	573080 kb
Host	smart-1e7b8c87-a54c-48b8-8cde-dee38baff3cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431408480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1431408480
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3718535724
Short name	T2654
Test name
Test status
Simulation time	7155409351 ps
CPU time	273.54 seconds
Started	May 23 04:31:52 PM PDT 24
Finished	May 23 04:36:27 PM PDT 24
Peak memory	572052 kb
Host	smart-0b488bb1-a6c6-40b8-937a-32a6e56db1d1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718535724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3718535724
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.455023222
Short name	T2005
Test name
Test status
Simulation time	2696776348 ps
CPU time	269.92 seconds
Started	May 23 04:31:52 PM PDT 24
Finished	May 23 04:36:23 PM PDT 24
Peak memory	573080 kb
Host	smart-d3d1a401-0851-448f-a3cb-0f2cc970c043
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455023222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_ with_rand_reset.455023222
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1718691401
Short name	T623
Test name
Test status
Simulation time	3316602165 ps
CPU time	195.95 seconds
Started	May 23 04:31:50 PM PDT 24
Finished	May 23 04:35:07 PM PDT 24
Peak memory	572692 kb
Host	smart-e2a3f8b4-509e-4034-8bdb-646d291435fb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718691401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.1718691401
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.214013638
Short name	T1349
Test name
Test status
Simulation time	937993079 ps
CPU time	46.61 seconds
Started	May 23 04:31:50 PM PDT 24
Finished	May 23 04:32:39 PM PDT 24
Peak memory	571784 kb
Host	smart-48d58a86-8f30-4c80-bf3c-c817f64741af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214013638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.214013638
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_access_same_device.2353236086
Short name	T1865
Test name
Test status
Simulation time	1038516549 ps
CPU time	87.93 seconds
Started	May 23 04:31:54 PM PDT 24
Finished	May 23 04:33:23 PM PDT 24
Peak memory	571848 kb
Host	smart-da14acbf-5322-4736-b436-e172860f9057
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353236086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .2353236086
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2968796591
Short name	T1995
Test name
Test status
Simulation time	90430534075 ps
CPU time	1603.33 seconds
Started	May 23 04:31:48 PM PDT 24
Finished	May 23 04:58:33 PM PDT 24
Peak memory	572044 kb
Host	smart-de9b9011-cf0e-4f82-b1a6-0b7fa4c35912
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968796591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.2968796591
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3134570477
Short name	T1368
Test name
Test status
Simulation time	656142969 ps
CPU time	31.66 seconds
Started	May 23 04:31:52 PM PDT 24
Finished	May 23 04:32:25 PM PDT 24
Peak memory	571792 kb
Host	smart-aa5b33e0-76cc-4fcb-9166-e10db85bd549
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134570477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.3134570477
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_error_random.330734220
Short name	T1671
Test name
Test status
Simulation time	411013036 ps
CPU time	39.81 seconds
Started	May 23 04:31:56 PM PDT 24
Finished	May 23 04:32:36 PM PDT 24
Peak memory	571852 kb
Host	smart-92b83441-085b-4597-b471-f9384ff8fcba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330734220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.330734220
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_random.452515544
Short name	T606
Test name
Test status
Simulation time	677214951 ps
CPU time	26.07 seconds
Started	May 23 04:31:58 PM PDT 24
Finished	May 23 04:32:25 PM PDT 24
Peak memory	571748 kb
Host	smart-3b8b2902-fcee-44a6-8046-a5593c034c04
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452515544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.452515544
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_random_large_delays.232635965
Short name	T2217
Test name
Test status
Simulation time	44188677583 ps
CPU time	540.91 seconds
Started	May 23 04:31:48 PM PDT 24
Finished	May 23 04:40:50 PM PDT 24
Peak memory	572012 kb
Host	smart-5779b949-763c-43e2-a543-9439bb0efeae
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232635965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.232635965
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1384296534
Short name	T2295
Test name
Test status
Simulation time	2906551170 ps
CPU time	51.69 seconds
Started	May 23 04:31:49 PM PDT 24
Finished	May 23 04:32:42 PM PDT 24
Peak memory	563752 kb
Host	smart-f2793d06-dfe8-4e95-a78e-8e8ef3e8ad7a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384296534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1384296534
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.2223167487
Short name	T1312
Test name
Test status
Simulation time	286529708 ps
CPU time	24.89 seconds
Started	May 23 04:31:50 PM PDT 24
Finished	May 23 04:32:17 PM PDT 24
Peak memory	571732 kb
Host	smart-8b6ed6c2-82d8-476d-920f-6086288f9d95
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223167487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.2223167487
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_same_source.3588065180
Short name	T1610
Test name
Test status
Simulation time	511220481 ps
CPU time	19.75 seconds
Started	May 23 04:31:52 PM PDT 24
Finished	May 23 04:32:13 PM PDT 24
Peak memory	571684 kb
Host	smart-abb05dea-1217-4e75-9687-7fd01385ccb3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588065180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3588065180
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke.3793640450
Short name	T2178
Test name
Test status
Simulation time	217194237 ps
CPU time	10.36 seconds
Started	May 23 04:31:49 PM PDT 24
Finished	May 23 04:32:01 PM PDT 24
Peak memory	563520 kb
Host	smart-2de0789d-b1bc-4e7b-9fec-b56cbdf881f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793640450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3793640450
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.1265792402
Short name	T1249
Test name
Test status
Simulation time	6980696477 ps
CPU time	78.32 seconds
Started	May 23 04:31:49 PM PDT 24
Finished	May 23 04:33:09 PM PDT 24
Peak memory	563792 kb
Host	smart-760d38dd-3b8e-42b5-94a5-6e49bcc4605c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265792402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1265792402
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3164585418
Short name	T2393
Test name
Test status
Simulation time	5609928142 ps
CPU time	104.56 seconds
Started	May 23 04:31:53 PM PDT 24
Finished	May 23 04:33:38 PM PDT 24
Peak memory	563796 kb
Host	smart-89085181-38fc-4af0-8b30-70f0e301406b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164585418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3164585418
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.596700643
Short name	T1351
Test name
Test status
Simulation time	40341600 ps
CPU time	5.84 seconds
Started	May 23 04:31:50 PM PDT 24
Finished	May 23 04:31:57 PM PDT 24
Peak memory	563552 kb
Host	smart-b0ac5068-6a05-44dd-acef-9de85e462932
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596700643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays .596700643
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all.3708743199
Short name	T2386
Test name
Test status
Simulation time	4274602939 ps
CPU time	377.84 seconds
Started	May 23 04:31:54 PM PDT 24
Finished	May 23 04:38:13 PM PDT 24
Peak memory	573088 kb
Host	smart-faeba79b-030c-4fa2-89a8-75bca45f5f97
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708743199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3708743199
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.125889043
Short name	T2003
Test name
Test status
Simulation time	177437848 ps
CPU time	15.94 seconds
Started	May 23 04:31:49 PM PDT 24
Finished	May 23 04:32:06 PM PDT 24
Peak memory	571860 kb
Host	smart-8434c81d-f5b1-4828-9aa8-2e1df411bfff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125889043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.125889043
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1043912802
Short name	T2671
Test name
Test status
Simulation time	1858145517 ps
CPU time	427.82 seconds
Started	May 23 04:31:53 PM PDT 24
Finished	May 23 04:39:02 PM PDT 24
Peak memory	572912 kb
Host	smart-3bfde8db-060f-4639-aeb8-a2c494d55b24
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043912802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.1043912802
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3849577636
Short name	T1503
Test name
Test status
Simulation time	256845228 ps
CPU time	88.39 seconds
Started	May 23 04:31:50 PM PDT 24
Finished	May 23 04:33:20 PM PDT 24
Peak memory	573860 kb
Host	smart-70860ad9-fffc-4222-9934-d7c7b0072dfb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849577636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.3849577636
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2737573075
Short name	T225
Test name
Test status
Simulation time	338842694 ps
CPU time	41.79 seconds
Started	May 23 04:31:54 PM PDT 24
Finished	May 23 04:32:37 PM PDT 24
Peak memory	571892 kb
Host	smart-c28d80a4-21a0-4d65-89ef-b3f524ba2e9a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737573075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2737573075
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_access_same_device.1814396765
Short name	T782
Test name
Test status
Simulation time	2507150114 ps
CPU time	110.18 seconds
Started	May 23 04:32:13 PM PDT 24
Finished	May 23 04:34:04 PM PDT 24
Peak memory	571932 kb
Host	smart-cebc58c6-e1f5-4871-be50-adc4f469aab7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814396765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .1814396765
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2053019001
Short name	T1665
Test name
Test status
Simulation time	72294868999 ps
CPU time	1205.55 seconds
Started	May 23 04:32:13 PM PDT 24
Finished	May 23 04:52:20 PM PDT 24
Peak memory	572064 kb
Host	smart-db6f83b5-8431-45bd-8688-ea0a9a882929
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053019001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.2053019001
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.977734291
Short name	T1711
Test name
Test status
Simulation time	1106375613 ps
CPU time	47.32 seconds
Started	May 23 04:32:11 PM PDT 24
Finished	May 23 04:32:59 PM PDT 24
Peak memory	571840 kb
Host	smart-7315ed2e-c17b-4fdf-8301-c7b564e18ca6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977734291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr .977734291
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_error_random.1247165942
Short name	T1447
Test name
Test status
Simulation time	235424457 ps
CPU time	22.61 seconds
Started	May 23 04:32:10 PM PDT 24
Finished	May 23 04:32:34 PM PDT 24
Peak memory	571784 kb
Host	smart-e0260c30-5fdc-4b7b-8449-199890b2a5bc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247165942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1247165942
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_random.1732880247
Short name	T2566
Test name
Test status
Simulation time	1224392059 ps
CPU time	50.1 seconds
Started	May 23 04:32:14 PM PDT 24
Finished	May 23 04:33:05 PM PDT 24
Peak memory	571800 kb
Host	smart-bad2a800-44ca-4871-8e30-c089062af673
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732880247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.1732880247
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_random_large_delays.3715300207
Short name	T2746
Test name
Test status
Simulation time	86274350960 ps
CPU time	902.09 seconds
Started	May 23 04:32:08 PM PDT 24
Finished	May 23 04:47:12 PM PDT 24
Peak memory	572024 kb
Host	smart-b3003f07-c5f8-4b78-9e13-2aa668e4bd9f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715300207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3715300207
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.281723680
Short name	T1976
Test name
Test status
Simulation time	42058535222 ps
CPU time	756.34 seconds
Started	May 23 04:32:10 PM PDT 24
Finished	May 23 04:44:48 PM PDT 24
Peak memory	572044 kb
Host	smart-8d8a7343-bdbe-4306-b16e-cc429e0edb20
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281723680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.281723680
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.1612456218
Short name	T2218
Test name
Test status
Simulation time	379114310 ps
CPU time	39.77 seconds
Started	May 23 04:32:09 PM PDT 24
Finished	May 23 04:32:51 PM PDT 24
Peak memory	571820 kb
Host	smart-fa58331e-9008-4593-a7b1-615b17ab31ad
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612456218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.1612456218
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_same_source.4089916296
Short name	T2000
Test name
Test status
Simulation time	615032444 ps
CPU time	23.39 seconds
Started	May 23 04:32:09 PM PDT 24
Finished	May 23 04:32:34 PM PDT 24
Peak memory	571840 kb
Host	smart-abcfd689-fab2-4846-b561-8c4e6307db78
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089916296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.4089916296
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke.1885207948
Short name	T1536
Test name
Test status
Simulation time	187790467 ps
CPU time	8.77 seconds
Started	May 23 04:32:10 PM PDT 24
Finished	May 23 04:32:20 PM PDT 24
Peak memory	563476 kb
Host	smart-03ff556b-a825-47ae-a5cb-0d349a7fd4fe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885207948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1885207948
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.2336316479
Short name	T2222
Test name
Test status
Simulation time	6609906714 ps
CPU time	73.81 seconds
Started	May 23 04:32:12 PM PDT 24
Finished	May 23 04:33:28 PM PDT 24
Peak memory	563740 kb
Host	smart-794d0e7b-f219-4bbb-b386-b77b4a832c24
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336316479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2336316479
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.175482464
Short name	T2721
Test name
Test status
Simulation time	3760821373 ps
CPU time	65.59 seconds
Started	May 23 04:32:13 PM PDT 24
Finished	May 23 04:33:20 PM PDT 24
Peak memory	563768 kb
Host	smart-fc127719-8713-4b45-82ed-2246fe58b6a9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175482464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.175482464
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.2804882688
Short name	T2752
Test name
Test status
Simulation time	53322132 ps
CPU time	7.52 seconds
Started	May 23 04:32:09 PM PDT 24
Finished	May 23 04:32:17 PM PDT 24
Peak memory	563572 kb
Host	smart-07c570a5-93c7-4934-8e5d-2988a3050c2d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804882688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.2804882688
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all.4035304859
Short name	T1561
Test name
Test status
Simulation time	2830186126 ps
CPU time	95.79 seconds
Started	May 23 04:32:15 PM PDT 24
Finished	May 23 04:33:52 PM PDT 24
Peak memory	571968 kb
Host	smart-e6fcafe2-73b5-486d-a189-c3c917e296b7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035304859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4035304859
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.109028987
Short name	T1772
Test name
Test status
Simulation time	3739388451 ps
CPU time	299.86 seconds
Started	May 23 04:32:15 PM PDT 24
Finished	May 23 04:37:16 PM PDT 24
Peak memory	572024 kb
Host	smart-2d70e262-183d-417f-964c-b99729329b90
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109028987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.109028987
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.4226644851
Short name	T2052
Test name
Test status
Simulation time	8123609704 ps
CPU time	540.55 seconds
Started	May 23 04:32:12 PM PDT 24
Finished	May 23 04:41:14 PM PDT 24
Peak memory	574008 kb
Host	smart-d1f449f1-3a49-4e72-a9b1-0637c3bf1257
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226644851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.4226644851
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.187086101
Short name	T2085
Test name
Test status
Simulation time	9960275429 ps
CPU time	452.4 seconds
Started	May 23 04:32:16 PM PDT 24
Finished	May 23 04:39:49 PM PDT 24
Peak memory	573100 kb
Host	smart-90afd62b-1949-49c4-a88e-81559a664dbc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187086101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_reset_error.187086101
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.1587417194
Short name	T2690
Test name
Test status
Simulation time	275451395 ps
CPU time	13.87 seconds
Started	May 23 04:32:14 PM PDT 24
Finished	May 23 04:32:28 PM PDT 24
Peak memory	571776 kb
Host	smart-13179f29-da83-4d6c-9a85-9016ba8fd5c0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587417194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1587417194
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_access_same_device.750771828
Short name	T1750
Test name
Test status
Simulation time	3122856309 ps
CPU time	138.34 seconds
Started	May 23 04:32:08 PM PDT 24
Finished	May 23 04:34:28 PM PDT 24
Peak memory	571948 kb
Host	smart-3d37f75b-7876-4712-9ae7-86656b45a4bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750771828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device. 750771828
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3898546317
Short name	T2001
Test name
Test status
Simulation time	138731489163 ps
CPU time	2279.19 seconds
Started	May 23 04:32:10 PM PDT 24
Finished	May 23 05:10:11 PM PDT 24
Peak memory	572088 kb
Host	smart-d52c664d-96a4-4037-858e-88a122bbda3a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898546317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.3898546317
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.1886433639
Short name	T55
Test name
Test status
Simulation time	520675026 ps
CPU time	23.13 seconds
Started	May 23 04:32:12 PM PDT 24
Finished	May 23 04:32:36 PM PDT 24
Peak memory	571832 kb
Host	smart-f8692da9-b4e3-4ae8-a63b-32c8df5e4a49
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886433639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.1886433639
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_error_random.1214597299
Short name	T1778
Test name
Test status
Simulation time	251010817 ps
CPU time	22.97 seconds
Started	May 23 04:32:10 PM PDT 24
Finished	May 23 04:32:34 PM PDT 24
Peak memory	571744 kb
Host	smart-f9e2d4c0-69a6-4ef3-b013-ad1ed3bb5e1d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214597299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1214597299
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_random.2209305015
Short name	T2378
Test name
Test status
Simulation time	314411488 ps
CPU time	30.41 seconds
Started	May 23 04:32:11 PM PDT 24
Finished	May 23 04:32:43 PM PDT 24
Peak memory	571824 kb
Host	smart-8df08daa-031b-458c-80d6-67c6d7cf8fb8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209305015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.2209305015
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3104483063
Short name	T2675
Test name
Test status
Simulation time	36716040289 ps
CPU time	632.58 seconds
Started	May 23 04:32:09 PM PDT 24
Finished	May 23 04:42:43 PM PDT 24
Peak memory	572028 kb
Host	smart-c6e583df-a743-4af9-a0d2-8ba3bd66e2e7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104483063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3104483063
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.4204480965
Short name	T2424
Test name
Test status
Simulation time	430172236 ps
CPU time	41.1 seconds
Started	May 23 04:32:12 PM PDT 24
Finished	May 23 04:32:54 PM PDT 24
Peak memory	571840 kb
Host	smart-3f5eee31-895c-4c89-b09f-85463305874a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204480965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.4204480965
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_same_source.3556187873
Short name	T2114
Test name
Test status
Simulation time	468394937 ps
CPU time	34.97 seconds
Started	May 23 04:32:12 PM PDT 24
Finished	May 23 04:32:48 PM PDT 24
Peak memory	571792 kb
Host	smart-2aeb7d9b-785f-468c-9c39-f874dbb94f0e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556187873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3556187873
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke.3685389208
Short name	T1299
Test name
Test status
Simulation time	157300564 ps
CPU time	8.33 seconds
Started	May 23 04:32:12 PM PDT 24
Finished	May 23 04:32:22 PM PDT 24
Peak memory	563556 kb
Host	smart-204cbcd4-768e-4cf5-8736-23c94240f383
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685389208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3685389208
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.182985866
Short name	T1607
Test name
Test status
Simulation time	5554060827 ps
CPU time	58.42 seconds
Started	May 23 04:32:10 PM PDT 24
Finished	May 23 04:33:10 PM PDT 24
Peak memory	563740 kb
Host	smart-01fdb9f9-1d50-4d4b-8f8d-ed20095f47c6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182985866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.182985866
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1555428962
Short name	T2785
Test name
Test status
Simulation time	4799686360 ps
CPU time	85.61 seconds
Started	May 23 04:32:11 PM PDT 24
Finished	May 23 04:33:38 PM PDT 24
Peak memory	563784 kb
Host	smart-45a8657a-6747-489b-aa87-c9f3e58abef9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555428962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1555428962
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.1673212053
Short name	T2507
Test name
Test status
Simulation time	37704978 ps
CPU time	6.11 seconds
Started	May 23 04:32:09 PM PDT 24
Finished	May 23 04:32:16 PM PDT 24
Peak memory	563516 kb
Host	smart-3ceebb7a-0fea-49bb-8a05-2e18b937e455
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673212053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.1673212053
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all.4213314529
Short name	T1738
Test name
Test status
Simulation time	2167502921 ps
CPU time	229.37 seconds
Started	May 23 04:32:09 PM PDT 24
Finished	May 23 04:35:59 PM PDT 24
Peak memory	572896 kb
Host	smart-25f532a6-191a-4cf5-b37b-c1c06c82221f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213314529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4213314529
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.3084446968
Short name	T1881
Test name
Test status
Simulation time	6953862551 ps
CPU time	257.9 seconds
Started	May 23 04:32:11 PM PDT 24
Finished	May 23 04:36:30 PM PDT 24
Peak memory	572004 kb
Host	smart-9c5b1fd6-0454-4d20-a91b-824f8850c73e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084446968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3084446968
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3094016971
Short name	T1297
Test name
Test status
Simulation time	267955445 ps
CPU time	112.86 seconds
Started	May 23 04:32:12 PM PDT 24
Finished	May 23 04:34:06 PM PDT 24
Peak memory	572512 kb
Host	smart-d9a1cf1c-dda5-48d6-83a3-94ca2ac1cc8c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094016971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.3094016971
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.965126925
Short name	T839
Test name
Test status
Simulation time	2016758314 ps
CPU time	393.57 seconds
Started	May 23 04:32:26 PM PDT 24
Finished	May 23 04:39:00 PM PDT 24
Peak memory	572940 kb
Host	smart-056b811d-8353-4cb4-ba69-b97ea9d4b8b2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965126925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_reset_error.965126925
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.666814762
Short name	T2347
Test name
Test status
Simulation time	557800219 ps
CPU time	24.25 seconds
Started	May 23 04:32:12 PM PDT 24
Finished	May 23 04:32:38 PM PDT 24
Peak memory	571832 kb
Host	smart-a59d630a-5650-4929-836f-a444f82762e5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666814762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.666814762
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_access_same_device.1812631900
Short name	T1472
Test name
Test status
Simulation time	496904348 ps
CPU time	21.67 seconds
Started	May 23 04:32:23 PM PDT 24
Finished	May 23 04:32:45 PM PDT 24
Peak memory	563584 kb
Host	smart-86600b31-af92-4dd7-95dd-f71837423313
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812631900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .1812631900
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2403219359
Short name	T2767
Test name
Test status
Simulation time	145405004913 ps
CPU time	2429.85 seconds
Started	May 23 04:32:40 PM PDT 24
Finished	May 23 05:13:11 PM PDT 24
Peak memory	572008 kb
Host	smart-532ff4d6-9ef5-4e47-ac61-2fa13a9a5725
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403219359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.2403219359
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.4194267414
Short name	T1560
Test name
Test status
Simulation time	1181136979 ps
CPU time	49.15 seconds
Started	May 23 04:32:24 PM PDT 24
Finished	May 23 04:33:15 PM PDT 24
Peak memory	571820 kb
Host	smart-0b70ce53-2f2a-4c05-8b14-df29730615f5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194267414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.4194267414
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_error_random.2420313587
Short name	T1890
Test name
Test status
Simulation time	965240220 ps
CPU time	33.94 seconds
Started	May 23 04:32:23 PM PDT 24
Finished	May 23 04:32:58 PM PDT 24
Peak memory	571828 kb
Host	smart-3a7ca1a1-208a-4ccb-90c6-d2b4d7fde503
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420313587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2420313587
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_random.2832018308
Short name	T2545
Test name
Test status
Simulation time	32009082 ps
CPU time	6.27 seconds
Started	May 23 04:32:27 PM PDT 24
Finished	May 23 04:32:35 PM PDT 24
Peak memory	563496 kb
Host	smart-335a5a0e-9583-4eed-a24f-f1ebceb16f4e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832018308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2832018308
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_random_large_delays.3563503210
Short name	T471
Test name
Test status
Simulation time	71707449022 ps
CPU time	771.4 seconds
Started	May 23 04:32:22 PM PDT 24
Finished	May 23 04:45:14 PM PDT 24
Peak memory	572032 kb
Host	smart-5ced0731-1c2c-4d84-bfb9-31a90fcf29fe
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563503210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3563503210
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2753309622
Short name	T438
Test name
Test status
Simulation time	51466450231 ps
CPU time	880.84 seconds
Started	May 23 04:32:23 PM PDT 24
Finished	May 23 04:47:04 PM PDT 24
Peak memory	572024 kb
Host	smart-cdb75ed0-6afa-48db-b02e-9ca6ad302517
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753309622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2753309622
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.3345898667
Short name	T2185
Test name
Test status
Simulation time	274829597 ps
CPU time	28.23 seconds
Started	May 23 04:32:23 PM PDT 24
Finished	May 23 04:32:52 PM PDT 24
Peak memory	571864 kb
Host	smart-f180e88b-9dc7-445d-b929-1983e8157064
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345898667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.3345898667
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_same_source.2366024775
Short name	T1826
Test name
Test status
Simulation time	581970748 ps
CPU time	21.11 seconds
Started	May 23 04:32:27 PM PDT 24
Finished	May 23 04:32:49 PM PDT 24
Peak memory	571796 kb
Host	smart-8da83bab-534b-4091-b707-97f9de43740f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366024775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2366024775
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke.1472179508
Short name	T1849
Test name
Test status
Simulation time	125356432 ps
CPU time	7.23 seconds
Started	May 23 04:32:41 PM PDT 24
Finished	May 23 04:32:49 PM PDT 24
Peak memory	563500 kb
Host	smart-19a4e401-e1ba-493e-9c11-fbf8382e9201
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472179508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1472179508
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.2863973691
Short name	T2314
Test name
Test status
Simulation time	7582992989 ps
CPU time	83.28 seconds
Started	May 23 04:32:24 PM PDT 24
Finished	May 23 04:33:49 PM PDT 24
Peak memory	563728 kb
Host	smart-9dfb5cde-5e1a-44a2-a9de-145b05f5ba71
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863973691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2863973691
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.3227219036
Short name	T2339
Test name
Test status
Simulation time	4655538655 ps
CPU time	85.86 seconds
Started	May 23 04:32:23 PM PDT 24
Finished	May 23 04:33:50 PM PDT 24
Peak memory	563748 kb
Host	smart-397adee5-5781-4462-86e8-552da89e6a39
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227219036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3227219036
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1201705222
Short name	T1637
Test name
Test status
Simulation time	48695682 ps
CPU time	7.11 seconds
Started	May 23 04:32:24 PM PDT 24
Finished	May 23 04:32:33 PM PDT 24
Peak memory	563508 kb
Host	smart-04d1affe-6215-4992-982c-6a159ed080ad
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201705222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.1201705222
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all.182530396
Short name	T549
Test name
Test status
Simulation time	737852943 ps
CPU time	75.61 seconds
Started	May 23 04:32:25 PM PDT 24
Finished	May 23 04:33:42 PM PDT 24
Peak memory	571836 kb
Host	smart-db7327e0-aad4-4cc9-b8f6-ae1945eb2162
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182530396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.182530396
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2021780217
Short name	T1723
Test name
Test status
Simulation time	785591839 ps
CPU time	78.95 seconds
Started	May 23 04:32:28 PM PDT 24
Finished	May 23 04:33:48 PM PDT 24
Peak memory	571856 kb
Host	smart-3c40da3a-29a4-4294-a35d-6fbc13eb2326
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021780217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2021780217
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1526199234
Short name	T816
Test name
Test status
Simulation time	8244156588 ps
CPU time	493.29 seconds
Started	May 23 04:32:23 PM PDT 24
Finished	May 23 04:40:37 PM PDT 24
Peak memory	573548 kb
Host	smart-2d36aee2-0b27-40f3-b496-7406345a16ba
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526199234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1526199234
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3421769409
Short name	T1970
Test name
Test status
Simulation time	3237143994 ps
CPU time	398.3 seconds
Started	May 23 04:32:40 PM PDT 24
Finished	May 23 04:39:19 PM PDT 24
Peak memory	573108 kb
Host	smart-bcb88453-8d93-4227-8ff6-07b46a5c445d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421769409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.3421769409
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.1481000114
Short name	T1706
Test name
Test status
Simulation time	515179874 ps
CPU time	25.23 seconds
Started	May 23 04:32:23 PM PDT 24
Finished	May 23 04:32:50 PM PDT 24
Peak memory	571824 kb
Host	smart-bd80ebd8-c84f-41ff-a88f-96ed8bd228fe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481000114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1481000114
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_access_same_device.2836837428
Short name	T1591
Test name
Test status
Simulation time	220281257 ps
CPU time	26.48 seconds
Started	May 23 04:32:24 PM PDT 24
Finished	May 23 04:32:51 PM PDT 24
Peak memory	571872 kb
Host	smart-d26779c4-dc74-4d13-b25a-01f9bf5db59f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836837428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .2836837428
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3789681225
Short name	T1755
Test name
Test status
Simulation time	108986952655 ps
CPU time	1864.46 seconds
Started	May 23 04:32:35 PM PDT 24
Finished	May 23 05:03:42 PM PDT 24
Peak memory	572020 kb
Host	smart-6530fce1-2d80-4343-ae66-1a3cb955bf21
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789681225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.3789681225
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.301134573
Short name	T1855
Test name
Test status
Simulation time	324977796 ps
CPU time	42.44 seconds
Started	May 23 04:32:36 PM PDT 24
Finished	May 23 04:33:20 PM PDT 24
Peak memory	571828 kb
Host	smart-0051ae7d-e690-461e-a823-ba87f33e5978
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301134573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr .301134573
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_error_random.1662123667
Short name	T1340
Test name
Test status
Simulation time	936125002 ps
CPU time	32.17 seconds
Started	May 23 04:32:38 PM PDT 24
Finished	May 23 04:33:12 PM PDT 24
Peak memory	571372 kb
Host	smart-250472f1-05a3-4f8e-bff8-6e5d84cd2e8c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662123667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1662123667
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_random.3621431938
Short name	T1650
Test name
Test status
Simulation time	67978178 ps
CPU time	9.77 seconds
Started	May 23 04:32:40 PM PDT 24
Finished	May 23 04:32:51 PM PDT 24
Peak memory	571788 kb
Host	smart-af8d58c7-b07c-4db8-839c-3e3a6eeb8243
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621431938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.3621431938
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_random_large_delays.171312130
Short name	T1864
Test name
Test status
Simulation time	102706568699 ps
CPU time	1107.26 seconds
Started	May 23 04:32:24 PM PDT 24
Finished	May 23 04:50:53 PM PDT 24
Peak memory	572008 kb
Host	smart-e1ac932d-7cd8-4801-8bb3-96bfdd577fa6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171312130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.171312130
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.2481626198
Short name	T1596
Test name
Test status
Simulation time	68183558630 ps
CPU time	1227.67 seconds
Started	May 23 04:32:23 PM PDT 24
Finished	May 23 04:52:51 PM PDT 24
Peak memory	572036 kb
Host	smart-6d172246-e38f-4755-a4bd-107e65578561
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481626198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2481626198
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.2977853637
Short name	T415
Test name
Test status
Simulation time	562071277 ps
CPU time	56.83 seconds
Started	May 23 04:32:24 PM PDT 24
Finished	May 23 04:33:22 PM PDT 24
Peak memory	571852 kb
Host	smart-2b108984-1d46-41ba-b8fe-096f19d34cac
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977853637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.2977853637
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_same_source.2431962681
Short name	T2139
Test name
Test status
Simulation time	1261196235 ps
CPU time	38.49 seconds
Started	May 23 04:32:35 PM PDT 24
Finished	May 23 04:33:16 PM PDT 24
Peak memory	571788 kb
Host	smart-2441677c-58d5-4113-b3c5-9b2e25559ca1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431962681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2431962681
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke.3445414482
Short name	T2491
Test name
Test status
Simulation time	43441230 ps
CPU time	6.42 seconds
Started	May 23 04:32:40 PM PDT 24
Finished	May 23 04:32:48 PM PDT 24
Peak memory	563516 kb
Host	smart-a959f57a-72cf-4f04-a031-64fc7ae17a87
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445414482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3445414482
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.3133298676
Short name	T1440
Test name
Test status
Simulation time	5928283143 ps
CPU time	63.44 seconds
Started	May 23 04:32:24 PM PDT 24
Finished	May 23 04:33:29 PM PDT 24
Peak memory	563764 kb
Host	smart-6899c9ca-9864-42fe-8cac-12490155eb49
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133298676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3133298676
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3350096382
Short name	T1567
Test name
Test status
Simulation time	7212954570 ps
CPU time	133.71 seconds
Started	May 23 04:32:26 PM PDT 24
Finished	May 23 04:34:41 PM PDT 24
Peak memory	563820 kb
Host	smart-21408351-7c03-4bde-9fbc-45573c3253d0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350096382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3350096382
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.660397580
Short name	T2510
Test name
Test status
Simulation time	48212937 ps
CPU time	7.05 seconds
Started	May 23 04:32:23 PM PDT 24
Finished	May 23 04:32:32 PM PDT 24
Peak memory	563564 kb
Host	smart-6569c66c-80f0-4337-8175-87701adb0cb1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660397580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays .660397580
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all.3920193433
Short name	T1574
Test name
Test status
Simulation time	10419521716 ps
CPU time	422.25 seconds
Started	May 23 04:32:48 PM PDT 24
Finished	May 23 04:39:51 PM PDT 24
Peak memory	572352 kb
Host	smart-afac1ae4-95a4-400c-a26c-67f35b25a6dc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920193433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3920193433
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.2553920462
Short name	T1311
Test name
Test status
Simulation time	1170550412 ps
CPU time	109.69 seconds
Started	May 23 04:32:34 PM PDT 24
Finished	May 23 04:34:26 PM PDT 24
Peak memory	571920 kb
Host	smart-975aea1a-ec35-4cb8-bf98-ad05509f5959
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553920462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2553920462
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2385454847
Short name	T2720
Test name
Test status
Simulation time	4086669250 ps
CPU time	345.8 seconds
Started	May 23 04:32:34 PM PDT 24
Finished	May 23 04:38:22 PM PDT 24
Peak memory	573036 kb
Host	smart-4f284fec-87ff-4910-a411-a610d68009f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385454847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.2385454847
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3300922800
Short name	T226
Test name
Test status
Simulation time	158641599 ps
CPU time	23.79 seconds
Started	May 23 04:32:35 PM PDT 24
Finished	May 23 04:33:00 PM PDT 24
Peak memory	572936 kb
Host	smart-3a4ac184-455c-44e2-b594-54da1bc39009
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300922800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.3300922800
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.1714729323
Short name	T2477
Test name
Test status
Simulation time	134147590 ps
CPU time	19.78 seconds
Started	May 23 04:32:37 PM PDT 24
Finished	May 23 04:32:59 PM PDT 24
Peak memory	571796 kb
Host	smart-9fcaac69-c594-4308-a44f-d1a7cef38615
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714729323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1714729323
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_access_same_device.865371862
Short name	T803
Test name
Test status
Simulation time	306860269 ps
CPU time	27.12 seconds
Started	May 23 04:32:34 PM PDT 24
Finished	May 23 04:33:03 PM PDT 24
Peak memory	571796 kb
Host	smart-f78716b9-21a1-4dff-8e33-e4ae249a30c4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865371862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device. 865371862
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2908245412
Short name	T779
Test name
Test status
Simulation time	72702946601 ps
CPU time	1323.35 seconds
Started	May 23 04:32:36 PM PDT 24
Finished	May 23 04:54:41 PM PDT 24
Peak memory	572068 kb
Host	smart-38d375d3-89c6-4d2b-9bea-273097107e51
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908245412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.2908245412
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1209402891
Short name	T1517
Test name
Test status
Simulation time	906635922 ps
CPU time	38.73 seconds
Started	May 23 04:32:42 PM PDT 24
Finished	May 23 04:33:22 PM PDT 24
Peak memory	571800 kb
Host	smart-a95f5ccc-f817-41d3-a6f5-71c11520e5a8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209402891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.1209402891
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_error_random.1631729163
Short name	T2543
Test name
Test status
Simulation time	364882358 ps
CPU time	16.69 seconds
Started	May 23 04:32:34 PM PDT 24
Finished	May 23 04:32:53 PM PDT 24
Peak memory	571756 kb
Host	smart-9c6a8488-2353-4745-8538-a3f6980eb8e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631729163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1631729163
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_random.2211898646
Short name	T1969
Test name
Test status
Simulation time	1463369303 ps
CPU time	48.08 seconds
Started	May 23 04:32:34 PM PDT 24
Finished	May 23 04:33:24 PM PDT 24
Peak memory	571816 kb
Host	smart-583ec951-935b-4342-a718-4d0b955afac2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211898646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2211898646
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2211973798
Short name	T2034
Test name
Test status
Simulation time	17491462739 ps
CPU time	186.22 seconds
Started	May 23 04:32:34 PM PDT 24
Finished	May 23 04:35:43 PM PDT 24
Peak memory	571984 kb
Host	smart-affde337-e49d-4393-9ee5-bac885e2016d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211973798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2211973798
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.3633024825
Short name	T2321
Test name
Test status
Simulation time	6011470516 ps
CPU time	104.21 seconds
Started	May 23 04:32:37 PM PDT 24
Finished	May 23 04:34:23 PM PDT 24
Peak memory	563784 kb
Host	smart-4e278e28-4065-483f-a945-d714b6d16edf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633024825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3633024825
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.2755719204
Short name	T1754
Test name
Test status
Simulation time	360987282 ps
CPU time	34.21 seconds
Started	May 23 04:32:48 PM PDT 24
Finished	May 23 04:33:23 PM PDT 24
Peak memory	571732 kb
Host	smart-0a852dc5-bf52-40b4-9296-59c9c5ea9f3c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755719204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.2755719204
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_same_source.1367448952
Short name	T1288
Test name
Test status
Simulation time	1332251262 ps
CPU time	42.72 seconds
Started	May 23 04:32:42 PM PDT 24
Finished	May 23 04:33:26 PM PDT 24
Peak memory	571752 kb
Host	smart-6610e9fb-cec6-4625-a9fd-7bbef119b624
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367448952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1367448952
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke.3028563849
Short name	T544
Test name
Test status
Simulation time	50942628 ps
CPU time	6.22 seconds
Started	May 23 04:32:34 PM PDT 24
Finished	May 23 04:32:42 PM PDT 24
Peak memory	563544 kb
Host	smart-47a07d9a-5b2a-49eb-87b9-671e849e77c4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028563849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3028563849
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.2060204646
Short name	T1515
Test name
Test status
Simulation time	6520832259 ps
CPU time	71.03 seconds
Started	May 23 04:32:38 PM PDT 24
Finished	May 23 04:33:50 PM PDT 24
Peak memory	563740 kb
Host	smart-63d169fb-0699-4a33-838d-5c8db622bfe0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060204646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2060204646
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3124417525
Short name	T1355
Test name
Test status
Simulation time	3147760650 ps
CPU time	56.32 seconds
Started	May 23 04:32:47 PM PDT 24
Finished	May 23 04:33:44 PM PDT 24
Peak memory	563728 kb
Host	smart-f2372ccc-b720-49d9-88ba-fcf7566b1736
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124417525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3124417525
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.897416169
Short name	T1248
Test name
Test status
Simulation time	39827860 ps
CPU time	6.35 seconds
Started	May 23 04:32:42 PM PDT 24
Finished	May 23 04:32:49 PM PDT 24
Peak memory	563552 kb
Host	smart-695035b9-be65-49e4-8c6a-66b994048924
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897416169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .897416169
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all.3939547899
Short name	T2199
Test name
Test status
Simulation time	4916966113 ps
CPU time	208.9 seconds
Started	May 23 04:32:42 PM PDT 24
Finished	May 23 04:36:12 PM PDT 24
Peak memory	572364 kb
Host	smart-2615b53c-f71d-4629-97cd-4de13863b4e6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939547899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3939547899
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.3756540437
Short name	T2057
Test name
Test status
Simulation time	9820380785 ps
CPU time	319.18 seconds
Started	May 23 04:32:38 PM PDT 24
Finished	May 23 04:37:59 PM PDT 24
Peak memory	572104 kb
Host	smart-a4306218-899f-4aaf-b9d8-121edde15830
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756540437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3756540437
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3171737312
Short name	T1882
Test name
Test status
Simulation time	3045030760 ps
CPU time	449.84 seconds
Started	May 23 04:32:35 PM PDT 24
Finished	May 23 04:40:07 PM PDT 24
Peak memory	572716 kb
Host	smart-b3e94be0-c943-4dea-9d77-c9727d24b781
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171737312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.3171737312
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2429980456
Short name	T830
Test name
Test status
Simulation time	351685977 ps
CPU time	120.58 seconds
Started	May 23 04:32:35 PM PDT 24
Finished	May 23 04:34:37 PM PDT 24
Peak memory	573948 kb
Host	smart-d5c33c0c-2151-4b9e-bea8-5227d586480a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429980456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.2429980456
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2930167297
Short name	T2101
Test name
Test status
Simulation time	1310862549 ps
CPU time	70.74 seconds
Started	May 23 04:32:35 PM PDT 24
Finished	May 23 04:33:48 PM PDT 24
Peak memory	571852 kb
Host	smart-65760dc0-ad5e-4b23-a612-a358fcea2117
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930167297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2930167297
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_access_same_device.2006727033
Short name	T1408
Test name
Test status
Simulation time	1626481612 ps
CPU time	78.7 seconds
Started	May 23 04:32:50 PM PDT 24
Finished	May 23 04:34:10 PM PDT 24
Peak memory	571800 kb
Host	smart-ce2471b9-8731-4198-ab32-d93146d3c82c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006727033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .2006727033
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1346104721
Short name	T2680
Test name
Test status
Simulation time	87753975812 ps
CPU time	1491.03 seconds
Started	May 23 04:32:53 PM PDT 24
Finished	May 23 04:57:45 PM PDT 24
Peak memory	572016 kb
Host	smart-66ca7617-d97b-48b2-aba2-e1d938f2e2b9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346104721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.1346104721
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1481869100
Short name	T2458
Test name
Test status
Simulation time	102498830 ps
CPU time	14.31 seconds
Started	May 23 04:32:51 PM PDT 24
Finished	May 23 04:33:06 PM PDT 24
Peak memory	571824 kb
Host	smart-e322ed9a-179f-4e91-9232-baccacca8a9e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481869100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1481869100
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_error_random.1966059870
Short name	T1731
Test name
Test status
Simulation time	368685079 ps
CPU time	35.19 seconds
Started	May 23 04:32:53 PM PDT 24
Finished	May 23 04:33:29 PM PDT 24
Peak memory	571804 kb
Host	smart-7a2e74bb-4370-4082-98a5-a5abc2417a0a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966059870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1966059870
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_random.3930221916
Short name	T463
Test name
Test status
Simulation time	1607901780 ps
CPU time	60.29 seconds
Started	May 23 04:32:49 PM PDT 24
Finished	May 23 04:33:51 PM PDT 24
Peak memory	571816 kb
Host	smart-4f35c82f-b196-4d7d-8142-bb3b6e38e768
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930221916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3930221916
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_random_large_delays.728558371
Short name	T1975
Test name
Test status
Simulation time	19155993529 ps
CPU time	219.53 seconds
Started	May 23 04:32:49 PM PDT 24
Finished	May 23 04:36:29 PM PDT 24
Peak memory	572016 kb
Host	smart-4fb47a6d-2457-4db8-93b9-0ed9a7a27be9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728558371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.728558371
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.873218059
Short name	T2055
Test name
Test status
Simulation time	26328798409 ps
CPU time	471.75 seconds
Started	May 23 04:32:52 PM PDT 24
Finished	May 23 04:40:45 PM PDT 24
Peak memory	571964 kb
Host	smart-179f5456-30c3-446d-9841-557ee79e5bf9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873218059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.873218059
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1871055
Short name	T2647
Test name
Test status
Simulation time	638666307 ps
CPU time	55.47 seconds
Started	May 23 04:32:49 PM PDT 24
Finished	May 23 04:33:46 PM PDT 24
Peak memory	571760 kb
Host	smart-90729bd8-82c6-41b8-8766-40928d815a32
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1871055
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_same_source.1112717789
Short name	T573
Test name
Test status
Simulation time	170311741 ps
CPU time	16.14 seconds
Started	May 23 04:32:49 PM PDT 24
Finished	May 23 04:33:07 PM PDT 24
Peak memory	571796 kb
Host	smart-c2cd9d4f-a641-45cf-a2d5-4f44454819cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112717789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1112717789
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke.440675770
Short name	T2450
Test name
Test status
Simulation time	229789493 ps
CPU time	11.01 seconds
Started	May 23 04:32:37 PM PDT 24
Finished	May 23 04:32:50 PM PDT 24
Peak memory	563552 kb
Host	smart-8f1761c8-cd2d-4632-8241-2e3dfe40119b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440675770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.440675770
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.3678659366
Short name	T1541
Test name
Test status
Simulation time	9800900864 ps
CPU time	107.62 seconds
Started	May 23 04:32:50 PM PDT 24
Finished	May 23 04:34:39 PM PDT 24
Peak memory	563756 kb
Host	smart-f3c57e01-7d54-4fbd-8329-8057368fb5a4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678659366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3678659366
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.962722240
Short name	T1931
Test name
Test status
Simulation time	4603931687 ps
CPU time	82.31 seconds
Started	May 23 04:32:50 PM PDT 24
Finished	May 23 04:34:14 PM PDT 24
Peak memory	563740 kb
Host	smart-2102ada1-6e89-4ef9-a8bc-50702f7cccad
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962722240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.962722240
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3572656534
Short name	T2559
Test name
Test status
Simulation time	42256841 ps
CPU time	6.3 seconds
Started	May 23 04:32:35 PM PDT 24
Finished	May 23 04:32:43 PM PDT 24
Peak memory	563548 kb
Host	smart-af35f63a-6551-4d60-af99-beb56280bb1d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572656534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.3572656534
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all.4267599198
Short name	T2122
Test name
Test status
Simulation time	2923379113 ps
CPU time	133.35 seconds
Started	May 23 04:32:50 PM PDT 24
Finished	May 23 04:35:05 PM PDT 24
Peak memory	572012 kb
Host	smart-0924c1c6-2704-47b0-8d56-0b34ee05629e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267599198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.4267599198
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1739888842
Short name	T425
Test name
Test status
Simulation time	194932024 ps
CPU time	121.68 seconds
Started	May 23 04:32:48 PM PDT 24
Finished	May 23 04:34:50 PM PDT 24
Peak memory	572388 kb
Host	smart-7250f887-76d3-4071-860a-7dc0ec1bb476
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739888842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.1739888842
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.243011137
Short name	T2546
Test name
Test status
Simulation time	4755673048 ps
CPU time	212.62 seconds
Started	May 23 04:32:49 PM PDT 24
Finished	May 23 04:36:24 PM PDT 24
Peak memory	573084 kb
Host	smart-8292392c-4648-4f8e-ad55-cd04394deb34
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243011137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_reset_error.243011137
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.2397420692
Short name	T1611
Test name
Test status
Simulation time	1104063992 ps
CPU time	48.86 seconds
Started	May 23 04:32:50 PM PDT 24
Finished	May 23 04:33:41 PM PDT 24
Peak memory	571852 kb
Host	smart-919dae19-6403-4265-b451-760e557a35f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397420692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2397420692
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/5.chip_csr_rw.1040832084
Short name	T2121
Test name
Test status
Simulation time	6082810981 ps
CPU time	647.18 seconds
Started	May 23 04:21:11 PM PDT 24
Finished	May 23 04:31:59 PM PDT 24
Peak memory	592616 kb
Host	smart-abd7ffc4-ada2-43ab-9abb-c9e2d4404dac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040832084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.1040832084
Directory	/workspace/5.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.176948214
Short name	T168
Test name
Test status
Simulation time	16803350160 ps
CPU time	2427.16 seconds
Started	May 23 04:20:32 PM PDT 24
Finished	May 23 05:01:01 PM PDT 24
Peak memory	586452 kb
Host	smart-a7d35b90-3577-42cf-9555-cbb199c0522f
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176948214 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.chip_same_csr_outstanding.176948214
Directory	/workspace/5.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.chip_tl_errors.2362995554
Short name	T2423
Test name
Test status
Simulation time	4203453210 ps
CPU time	270.1 seconds
Started	May 23 04:20:57 PM PDT 24
Finished	May 23 04:25:28 PM PDT 24
Peak memory	594108 kb
Host	smart-2fbad35c-f091-4d7e-86a5-b91d20747ca0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362995554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.2362995554
Directory	/workspace/5.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_access_same_device.2202254748
Short name	T792
Test name
Test status
Simulation time	536788753 ps
CPU time	41.97 seconds
Started	May 23 04:20:45 PM PDT 24
Finished	May 23 04:21:28 PM PDT 24
Peak memory	571816 kb
Host	smart-e8a80a33-2cf7-4010-be65-04c01cd2f5ee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202254748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 2202254748
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1290792973
Short name	T2177
Test name
Test status
Simulation time	38259486161 ps
CPU time	680.02 seconds
Started	May 23 04:20:50 PM PDT 24
Finished	May 23 04:32:11 PM PDT 24
Peak memory	571984 kb
Host	smart-805dff10-5d48-49b8-8b6d-6a3ccb785c9d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290792973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.1290792973
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1753741838
Short name	T1525
Test name
Test status
Simulation time	227902957 ps
CPU time	14.17 seconds
Started	May 23 04:21:16 PM PDT 24
Finished	May 23 04:21:31 PM PDT 24
Peak memory	571820 kb
Host	smart-eb989334-20c9-4fd7-b79f-017485a2e47b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753741838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1753741838
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_error_random.897268732
Short name	T2709
Test name
Test status
Simulation time	1483189748 ps
CPU time	56.68 seconds
Started	May 23 04:20:53 PM PDT 24
Finished	May 23 04:21:51 PM PDT 24
Peak memory	571736 kb
Host	smart-c92eaa32-2ac4-415e-93c2-901dbcf6eb2e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897268732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.897268732
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_random.2673820537
Short name	T2728
Test name
Test status
Simulation time	396530843 ps
CPU time	18.66 seconds
Started	May 23 04:20:48 PM PDT 24
Finished	May 23 04:21:07 PM PDT 24
Peak memory	571776 kb
Host	smart-bebe5c56-b02a-4c9c-904c-2c37922bc72c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673820537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2673820537
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3814485054
Short name	T441
Test name
Test status
Simulation time	84851858063 ps
CPU time	929.57 seconds
Started	May 23 04:20:44 PM PDT 24
Finished	May 23 04:36:15 PM PDT 24
Peak memory	571956 kb
Host	smart-69e3d44b-2041-4fe4-b779-7ee3ef985db0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814485054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3814485054
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.2632537175
Short name	T1272
Test name
Test status
Simulation time	4771016035 ps
CPU time	89.05 seconds
Started	May 23 04:20:41 PM PDT 24
Finished	May 23 04:22:11 PM PDT 24
Peak memory	563804 kb
Host	smart-9f48b407-e5a6-40ad-8d45-1dd5c024e8ea
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632537175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2632537175
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.12460912
Short name	T1932
Test name
Test status
Simulation time	311240162 ps
CPU time	33.61 seconds
Started	May 23 04:21:52 PM PDT 24
Finished	May 23 04:22:28 PM PDT 24
Peak memory	571716 kb
Host	smart-834b4060-2afa-4395-b81e-7c5f26950676
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12460912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays .12460912
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_same_source.1731113341
Short name	T547
Test name
Test status
Simulation time	295216029 ps
CPU time	25.4 seconds
Started	May 23 04:20:54 PM PDT 24
Finished	May 23 04:21:20 PM PDT 24
Peak memory	571848 kb
Host	smart-59305905-724e-4adf-ae0a-4919ad9222a7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731113341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1731113341
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke.3777086935
Short name	T1279
Test name
Test status
Simulation time	239842421 ps
CPU time	12.02 seconds
Started	May 23 04:20:35 PM PDT 24
Finished	May 23 04:20:49 PM PDT 24
Peak memory	563604 kb
Host	smart-8c5d9195-ac69-4d35-82f4-9e4d43acc020
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777086935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3777086935
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.3463854942
Short name	T2074
Test name
Test status
Simulation time	7905357198 ps
CPU time	82.24 seconds
Started	May 23 04:20:47 PM PDT 24
Finished	May 23 04:22:09 PM PDT 24
Peak memory	563752 kb
Host	smart-55fcc45f-75e6-46c0-9236-8be6d62e02c8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463854942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3463854942
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1936888142
Short name	T2331
Test name
Test status
Simulation time	2938805540 ps
CPU time	52.24 seconds
Started	May 23 04:20:53 PM PDT 24
Finished	May 23 04:21:46 PM PDT 24
Peak memory	563760 kb
Host	smart-39e15ddd-0f9b-4c45-ba22-f03163b7052b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936888142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1936888142
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3332746205
Short name	T1510
Test name
Test status
Simulation time	41253284 ps
CPU time	7.32 seconds
Started	May 23 04:20:37 PM PDT 24
Finished	May 23 04:20:45 PM PDT 24
Peak memory	563492 kb
Host	smart-64c55209-b184-4a7f-9ffc-2dc03a3f66f4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332746205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .3332746205
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all.418823295
Short name	T2536
Test name
Test status
Simulation time	13094353560 ps
CPU time	555.4 seconds
Started	May 23 04:20:55 PM PDT 24
Finished	May 23 04:30:11 PM PDT 24
Peak memory	573004 kb
Host	smart-cb6aba3d-d6b1-47e7-9ecf-28bb5592f475
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418823295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.418823295
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.3463995135
Short name	T1923
Test name
Test status
Simulation time	2638533962 ps
CPU time	248.14 seconds
Started	May 23 04:20:59 PM PDT 24
Finished	May 23 04:25:08 PM PDT 24
Peak memory	572128 kb
Host	smart-fd3147d7-dafe-4b7a-9df4-5efe1e1e70f3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463995135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3463995135
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2392214209
Short name	T524
Test name
Test status
Simulation time	1055412891 ps
CPU time	305.65 seconds
Started	May 23 04:20:56 PM PDT 24
Finished	May 23 04:26:02 PM PDT 24
Peak memory	572828 kb
Host	smart-a16d106c-9542-45fc-8a22-5517c3560a4c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392214209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.2392214209
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.3049681567
Short name	T2142
Test name
Test status
Simulation time	1460835509 ps
CPU time	63.52 seconds
Started	May 23 04:20:45 PM PDT 24
Finished	May 23 04:21:49 PM PDT 24
Peak memory	571808 kb
Host	smart-ff94ddcc-f89e-43fa-8a75-c0d50981f371
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049681567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3049681567
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_access_same_device.1447546850
Short name	T2087
Test name
Test status
Simulation time	4040263234 ps
CPU time	180.6 seconds
Started	May 23 04:32:54 PM PDT 24
Finished	May 23 04:35:55 PM PDT 24
Peak memory	572000 kb
Host	smart-f4f6dd01-13a9-4663-818e-cbca0847b9a3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447546850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1447546850
Directory	/workspace/50.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.648110441
Short name	T2427
Test name
Test status
Simulation time	43462339842 ps
CPU time	767.19 seconds
Started	May 23 04:32:48 PM PDT 24
Finished	May 23 04:45:36 PM PDT 24
Peak memory	572036 kb
Host	smart-744f5658-6faf-4d58-af1a-a270198b0757
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648110441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_d evice_slow_rsp.648110441
Directory	/workspace/50.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.2627532139
Short name	T2492
Test name
Test status
Simulation time	197020384 ps
CPU time	23.56 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:33:33 PM PDT 24
Peak memory	571788 kb
Host	smart-cb6e3061-8dee-4ddc-a47b-c0f163270392
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627532139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.2627532139
Directory	/workspace/50.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_error_random.4024724401
Short name	T2213
Test name
Test status
Simulation time	102547568 ps
CPU time	10.57 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:33:20 PM PDT 24
Peak memory	571772 kb
Host	smart-43438876-c5f9-4e35-934d-770dfc6b1353
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024724401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.4024724401
Directory	/workspace/50.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_random.2410865801
Short name	T1392
Test name
Test status
Simulation time	803707262 ps
CPU time	31.69 seconds
Started	May 23 04:32:50 PM PDT 24
Finished	May 23 04:33:23 PM PDT 24
Peak memory	571808 kb
Host	smart-5ac38cef-b91e-4917-9e32-0452229a646a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410865801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.2410865801
Directory	/workspace/50.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_random_large_delays.790987641
Short name	T2186
Test name
Test status
Simulation time	70137784025 ps
CPU time	795.88 seconds
Started	May 23 04:32:50 PM PDT 24
Finished	May 23 04:46:08 PM PDT 24
Peak memory	572032 kb
Host	smart-4006947e-62c6-4541-8429-4a7394a519c6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790987641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.790987641
Directory	/workspace/50.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.3445589065
Short name	T1379
Test name
Test status
Simulation time	70976457386 ps
CPU time	1259.13 seconds
Started	May 23 04:32:51 PM PDT 24
Finished	May 23 04:53:51 PM PDT 24
Peak memory	572052 kb
Host	smart-3c32bc1a-6ca6-467b-a427-681b677698c0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445589065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.3445589065
Directory	/workspace/50.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.3674472003
Short name	T1598
Test name
Test status
Simulation time	404718841 ps
CPU time	33.84 seconds
Started	May 23 04:32:51 PM PDT 24
Finished	May 23 04:33:26 PM PDT 24
Peak memory	571788 kb
Host	smart-f9141c8d-9dde-489f-aaac-2d725ff16810
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674472003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.3674472003
Directory	/workspace/50.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_same_source.740272048
Short name	T1638
Test name
Test status
Simulation time	872975995 ps
CPU time	29.02 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:33:37 PM PDT 24
Peak memory	571792 kb
Host	smart-a9f339d5-62db-4842-915d-1de698640d6d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740272048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.740272048
Directory	/workspace/50.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke.1290279450
Short name	T1895
Test name
Test status
Simulation time	45136808 ps
CPU time	6.5 seconds
Started	May 23 04:32:49 PM PDT 24
Finished	May 23 04:32:57 PM PDT 24
Peak memory	563504 kb
Host	smart-e089144d-21c0-4369-baf4-ac8536443264
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290279450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.1290279450
Directory	/workspace/50.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2311087158
Short name	T2506
Test name
Test status
Simulation time	8411442621 ps
CPU time	89.78 seconds
Started	May 23 04:32:50 PM PDT 24
Finished	May 23 04:34:21 PM PDT 24
Peak memory	563760 kb
Host	smart-9d258788-89de-4fd9-93e9-fecf23b88e3a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311087158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2311087158
Directory	/workspace/50.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3362957145
Short name	T1752
Test name
Test status
Simulation time	5715035116 ps
CPU time	106.42 seconds
Started	May 23 04:32:53 PM PDT 24
Finished	May 23 04:34:40 PM PDT 24
Peak memory	563748 kb
Host	smart-9fadffe0-a6df-4cec-8e9e-82cc616a5997
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362957145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.3362957145
Directory	/workspace/50.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.44613961
Short name	T2602
Test name
Test status
Simulation time	50874778 ps
CPU time	7.14 seconds
Started	May 23 04:32:49 PM PDT 24
Finished	May 23 04:32:57 PM PDT 24
Peak memory	563552 kb
Host	smart-6dfd3bd2-c29e-44a5-baf3-5b85ed585c57
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44613961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays.44613961
Directory	/workspace/50.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all.1764354468
Short name	T1389
Test name
Test status
Simulation time	648310981 ps
CPU time	51.2 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:34:00 PM PDT 24
Peak memory	571872 kb
Host	smart-d74d8b36-7e72-4717-8dde-0ad30cdebb1e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764354468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.1764354468
Directory	/workspace/50.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.3663677474
Short name	T1452
Test name
Test status
Simulation time	833944624 ps
CPU time	74.45 seconds
Started	May 23 04:33:09 PM PDT 24
Finished	May 23 04:34:25 PM PDT 24
Peak memory	571896 kb
Host	smart-a1ffe6ac-0ac2-4ba6-86e4-4f999ded6d8f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663677474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.3663677474
Directory	/workspace/50.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2614434307
Short name	T1771
Test name
Test status
Simulation time	184278282 ps
CPU time	82.15 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:34:32 PM PDT 24
Peak memory	573496 kb
Host	smart-ee7edad5-a19d-4a35-bc5e-e994779fa4c1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614434307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.2614434307
Directory	/workspace/50.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.164788150
Short name	T2743
Test name
Test status
Simulation time	8366136952 ps
CPU time	415.82 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:40:05 PM PDT 24
Peak memory	573112 kb
Host	smart-6ccb0e5e-2750-4a58-81f9-a0cb7b32f7d6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164788150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_reset_error.164788150
Directory	/workspace/50.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1280898740
Short name	T2261
Test name
Test status
Simulation time	1026338499 ps
CPU time	47.81 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:33:56 PM PDT 24
Peak memory	571876 kb
Host	smart-8e2d149b-7a2e-4b58-9f84-b819d55eba16
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280898740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1280898740
Directory	/workspace/50.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_access_same_device.3861001929
Short name	T1897
Test name
Test status
Simulation time	741781534 ps
CPU time	58.27 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:34:08 PM PDT 24
Peak memory	571788 kb
Host	smart-dfbe6ded-dae9-4458-92d7-b9417c642ed8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861001929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .3861001929
Directory	/workspace/51.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3543962331
Short name	T804
Test name
Test status
Simulation time	98849727617 ps
CPU time	1639.38 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 05:00:28 PM PDT 24
Peak memory	572020 kb
Host	smart-6be884e4-7fa6-4f96-a6ae-a007bdb780d1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543962331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.3543962331
Directory	/workspace/51.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2002998701
Short name	T1330
Test name
Test status
Simulation time	60383402 ps
CPU time	9.87 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:33:18 PM PDT 24
Peak memory	571868 kb
Host	smart-9fa569e7-de0c-4a77-bf29-0f0b5675b98a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002998701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.2002998701
Directory	/workspace/51.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_error_random.4160689129
Short name	T2723
Test name
Test status
Simulation time	1481719472 ps
CPU time	60.16 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:34:09 PM PDT 24
Peak memory	571788 kb
Host	smart-b726ccb7-f207-469b-87b2-37cacb7e408f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160689129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.4160689129
Directory	/workspace/51.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_random.3366773799
Short name	T1414
Test name
Test status
Simulation time	940131361 ps
CPU time	36.78 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:33:46 PM PDT 24
Peak memory	571796 kb
Host	smart-0af21dbd-f4db-4f47-aaa7-e7a0b0f9cf01
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366773799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3366773799
Directory	/workspace/51.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3530478819
Short name	T423
Test name
Test status
Simulation time	36027261555 ps
CPU time	408.61 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:39:58 PM PDT 24
Peak memory	572036 kb
Host	smart-7e2edad4-fb59-4b43-a9d7-82898d3bb246
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530478819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3530478819
Directory	/workspace/51.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.163061251
Short name	T451
Test name
Test status
Simulation time	54585714464 ps
CPU time	955.74 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:49:05 PM PDT 24
Peak memory	572044 kb
Host	smart-a2e6cba5-b010-4ae3-a0c0-a12050431e52
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163061251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.163061251
Directory	/workspace/51.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.2693424605
Short name	T1858
Test name
Test status
Simulation time	197239509 ps
CPU time	17.27 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:33:25 PM PDT 24
Peak memory	571828 kb
Host	smart-d4bc0a11-1131-4791-a55c-fa85739554ce
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693424605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.2693424605
Directory	/workspace/51.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_same_source.955487348
Short name	T1461
Test name
Test status
Simulation time	775362374 ps
CPU time	23.84 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:33:33 PM PDT 24
Peak memory	571744 kb
Host	smart-18c2d0e3-f2c0-4178-9aec-d61c2f1a3265
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955487348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.955487348
Directory	/workspace/51.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke.2375946267
Short name	T2382
Test name
Test status
Simulation time	223122452 ps
CPU time	10.63 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:33:21 PM PDT 24
Peak memory	563552 kb
Host	smart-e190048b-9890-4852-b8ae-51fa6d575975
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375946267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2375946267
Directory	/workspace/51.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.3520233505
Short name	T1486
Test name
Test status
Simulation time	9323923871 ps
CPU time	96.85 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:34:46 PM PDT 24
Peak memory	563812 kb
Host	smart-696c33c9-7a23-4ea2-a442-96efeb448b3c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520233505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.3520233505
Directory	/workspace/51.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2537395033
Short name	T1323
Test name
Test status
Simulation time	4451841889 ps
CPU time	77.68 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:34:26 PM PDT 24
Peak memory	563788 kb
Host	smart-1bc862aa-fd82-43e3-9346-2d35385ec2b9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537395033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.2537395033
Directory	/workspace/51.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3341676904
Short name	T2658
Test name
Test status
Simulation time	36310513 ps
CPU time	6.33 seconds
Started	May 23 04:33:11 PM PDT 24
Finished	May 23 04:33:19 PM PDT 24
Peak memory	563588 kb
Host	smart-aa229ae9-8c3d-4c84-bb1a-561b3176ba7a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341676904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.3341676904
Directory	/workspace/51.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all.709252914
Short name	T1867
Test name
Test status
Simulation time	2053901559 ps
CPU time	177.48 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:36:07 PM PDT 24
Peak memory	571876 kb
Host	smart-efafffc0-d65b-4ce3-bb61-f2f58e3d6f25
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709252914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.709252914
Directory	/workspace/51.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.607695702
Short name	T1968
Test name
Test status
Simulation time	14500705578 ps
CPU time	612.53 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:43:22 PM PDT 24
Peak memory	573124 kb
Host	smart-473a5c2d-1e65-4688-807d-8f01796116d3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607695702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.607695702
Directory	/workspace/51.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.881782580
Short name	T1601
Test name
Test status
Simulation time	3550576719 ps
CPU time	186.16 seconds
Started	May 23 04:33:10 PM PDT 24
Finished	May 23 04:36:17 PM PDT 24
Peak memory	573000 kb
Host	smart-72d33fde-3c78-4ea5-9c59-557ec1deed84
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881782580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_ with_rand_reset.881782580
Directory	/workspace/51.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2010236284
Short name	T826
Test name
Test status
Simulation time	168123252 ps
CPU time	37.19 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:33:46 PM PDT 24
Peak memory	571928 kb
Host	smart-f8cb019a-6e62-4466-b608-d56e181e5c74
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010236284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.2010236284
Directory	/workspace/51.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2299486441
Short name	T1391
Test name
Test status
Simulation time	642857070 ps
CPU time	31.34 seconds
Started	May 23 04:33:10 PM PDT 24
Finished	May 23 04:33:43 PM PDT 24
Peak memory	571864 kb
Host	smart-d4e838f3-25ea-4c87-9287-4e0871196796
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299486441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2299486441
Directory	/workspace/51.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_access_same_device.342262361
Short name	T453
Test name
Test status
Simulation time	2551397712 ps
CPU time	109.85 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:35:12 PM PDT 24
Peak memory	571988 kb
Host	smart-a10bf2d8-2edc-42ad-8b64-fcc272752217
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342262361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device. 342262361
Directory	/workspace/52.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.1414970557
Short name	T1670
Test name
Test status
Simulation time	24784089613 ps
CPU time	458.75 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:41:02 PM PDT 24
Peak memory	572060 kb
Host	smart-32609d05-2621-4f23-989d-db40cb67661b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414970557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.1414970557
Directory	/workspace/52.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2381712902
Short name	T1335
Test name
Test status
Simulation time	344786570 ps
CPU time	39.15 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:34:02 PM PDT 24
Peak memory	571736 kb
Host	smart-ad176aef-3ab1-4df1-adba-db39fc5e7279
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381712902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.2381712902
Directory	/workspace/52.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_error_random.3108536143
Short name	T2134
Test name
Test status
Simulation time	1396612290 ps
CPU time	50.36 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:34:13 PM PDT 24
Peak memory	571800 kb
Host	smart-7e5dfb22-198a-4909-93d2-109b14504317
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108536143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.3108536143
Directory	/workspace/52.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_random.2150965606
Short name	T2268
Test name
Test status
Simulation time	1860859825 ps
CPU time	82.53 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:34:32 PM PDT 24
Peak memory	571848 kb
Host	smart-60a08fa5-5ca5-4648-bfc8-decbff7ee307
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150965606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.2150965606
Directory	/workspace/52.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_random_large_delays.3277616369
Short name	T2451
Test name
Test status
Simulation time	104233814883 ps
CPU time	1084.78 seconds
Started	May 23 04:33:20 PM PDT 24
Finished	May 23 04:51:27 PM PDT 24
Peak memory	572032 kb
Host	smart-04c1bb10-5a73-4c00-9840-dc99f0c8acf8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277616369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.3277616369
Directory	/workspace/52.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.2913288277
Short name	T2696
Test name
Test status
Simulation time	43602895560 ps
CPU time	809.12 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:46:52 PM PDT 24
Peak memory	571964 kb
Host	smart-c85df398-2457-46fc-8c57-6145a4919bb6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913288277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.2913288277
Directory	/workspace/52.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.337833630
Short name	T1602
Test name
Test status
Simulation time	97968309 ps
CPU time	11.12 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:33:20 PM PDT 24
Peak memory	571780 kb
Host	smart-3351629a-90f0-4c2e-b400-23eaf713593b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337833630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_dela ys.337833630
Directory	/workspace/52.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_same_source.4112043940
Short name	T1647
Test name
Test status
Simulation time	233136707 ps
CPU time	9.65 seconds
Started	May 23 04:33:20 PM PDT 24
Finished	May 23 04:33:30 PM PDT 24
Peak memory	563552 kb
Host	smart-f001fcb8-de7a-4eae-8253-bf0458997b1f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112043940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.4112043940
Directory	/workspace/52.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke.4027630731
Short name	T2280
Test name
Test status
Simulation time	209190084 ps
CPU time	9.51 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:33:19 PM PDT 24
Peak memory	563508 kb
Host	smart-0c476f2c-d56d-4a2b-a7ec-c2d3432fb906
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027630731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.4027630731
Directory	/workspace/52.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.1432450947
Short name	T2277
Test name
Test status
Simulation time	8576670969 ps
CPU time	89.48 seconds
Started	May 23 04:33:08 PM PDT 24
Finished	May 23 04:34:39 PM PDT 24
Peak memory	563740 kb
Host	smart-bc34f117-9095-4ff5-bfcc-f21d80d973c9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432450947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.1432450947
Directory	/workspace/52.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1727042878
Short name	T599
Test name
Test status
Simulation time	4610999294 ps
CPU time	80.72 seconds
Started	May 23 04:33:10 PM PDT 24
Finished	May 23 04:34:31 PM PDT 24
Peak memory	563740 kb
Host	smart-2d99d246-ec69-4ed7-9ac4-2fc8dc9fa056
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727042878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1727042878
Directory	/workspace/52.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3868836099
Short name	T2470
Test name
Test status
Simulation time	55973160 ps
CPU time	7.33 seconds
Started	May 23 04:33:07 PM PDT 24
Finished	May 23 04:33:15 PM PDT 24
Peak memory	563524 kb
Host	smart-e1c09087-7601-4226-a89e-882887b8666c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868836099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.3868836099
Directory	/workspace/52.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all.2475392333
Short name	T2070
Test name
Test status
Simulation time	9086019797 ps
CPU time	374.63 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:39:38 PM PDT 24
Peak memory	573036 kb
Host	smart-d0d8cc2e-ebb5-4154-8461-dd082bb1c0b3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475392333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2475392333
Directory	/workspace/52.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.1567281701
Short name	T1572
Test name
Test status
Simulation time	5709886047 ps
CPU time	219.89 seconds
Started	May 23 04:33:20 PM PDT 24
Finished	May 23 04:37:01 PM PDT 24
Peak memory	572004 kb
Host	smart-a9703b7b-6d25-4d8f-8032-084ccd1830c0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567281701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.1567281701
Directory	/workspace/52.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.294063353
Short name	T1721
Test name
Test status
Simulation time	111272679 ps
CPU time	37.72 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:34:01 PM PDT 24
Peak memory	571960 kb
Host	smart-8034fa08-1693-4427-87a2-be64961f88f8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294063353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_ with_rand_reset.294063353
Directory	/workspace/52.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2560818548
Short name	T2383
Test name
Test status
Simulation time	1084091742 ps
CPU time	249.59 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:37:32 PM PDT 24
Peak memory	572932 kb
Host	smart-cdabe241-b265-4b93-86c5-ffaffc93257f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560818548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.2560818548
Directory	/workspace/52.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2553042542
Short name	T385
Test name
Test status
Simulation time	386333490 ps
CPU time	19.65 seconds
Started	May 23 04:33:20 PM PDT 24
Finished	May 23 04:33:41 PM PDT 24
Peak memory	571844 kb
Host	smart-a0f93861-e969-4bb5-b3d3-1fde8fd476f9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553042542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2553042542
Directory	/workspace/52.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_access_same_device.484122096
Short name	T572
Test name
Test status
Simulation time	769328419 ps
CPU time	60.37 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:34:22 PM PDT 24
Peak memory	571816 kb
Host	smart-1039bf1e-13f4-465e-a5be-96d93f7670c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484122096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device. 484122096
Directory	/workspace/53.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.4136957549
Short name	T1758
Test name
Test status
Simulation time	19703545537 ps
CPU time	373.01 seconds
Started	May 23 04:33:23 PM PDT 24
Finished	May 23 04:39:37 PM PDT 24
Peak memory	572024 kb
Host	smart-7717179d-9503-4862-a78c-1582730a8ba2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136957549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.4136957549
Directory	/workspace/53.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2685481052
Short name	T2351
Test name
Test status
Simulation time	669411520 ps
CPU time	28.76 seconds
Started	May 23 04:33:22 PM PDT 24
Finished	May 23 04:33:52 PM PDT 24
Peak memory	571836 kb
Host	smart-a0502c33-47c6-422d-bbea-702c7b3824cf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685481052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.2685481052
Directory	/workspace/53.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_error_random.3644396470
Short name	T2061
Test name
Test status
Simulation time	2391447283 ps
CPU time	78.8 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:34:41 PM PDT 24
Peak memory	571944 kb
Host	smart-07c907e7-6be6-454f-b721-468d4c288cc7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644396470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.3644396470
Directory	/workspace/53.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_random.966938180
Short name	T617
Test name
Test status
Simulation time	591067761 ps
CPU time	25.67 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:33:48 PM PDT 24
Peak memory	571768 kb
Host	smart-98210ec0-5705-45b0-a109-a1b5d698581f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966938180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.966938180
Directory	/workspace/53.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3499718618
Short name	T604
Test name
Test status
Simulation time	60012129451 ps
CPU time	655.1 seconds
Started	May 23 04:33:24 PM PDT 24
Finished	May 23 04:44:21 PM PDT 24
Peak memory	572004 kb
Host	smart-c0c27b33-38af-489b-bbf0-7acd0bae189a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499718618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3499718618
Directory	/workspace/53.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.1731434098
Short name	T1589
Test name
Test status
Simulation time	15220289676 ps
CPU time	281.97 seconds
Started	May 23 04:33:23 PM PDT 24
Finished	May 23 04:38:07 PM PDT 24
Peak memory	571956 kb
Host	smart-6f47dbf6-b5ec-4579-b5f9-2c200d85b6b8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731434098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.1731434098
Directory	/workspace/53.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.2946702325
Short name	T2161
Test name
Test status
Simulation time	581268126 ps
CPU time	57.49 seconds
Started	May 23 04:33:26 PM PDT 24
Finished	May 23 04:34:24 PM PDT 24
Peak memory	571816 kb
Host	smart-43bc3c56-029c-4035-84a9-a1522a65e882
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946702325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.2946702325
Directory	/workspace/53.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_same_source.343985660
Short name	T532
Test name
Test status
Simulation time	1750846163 ps
CPU time	52.88 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:34:15 PM PDT 24
Peak memory	571812 kb
Host	smart-4858b4e1-ff25-4719-b578-7b1f0aaa7398
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343985660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.343985660
Directory	/workspace/53.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke.2264321677
Short name	T1454
Test name
Test status
Simulation time	39144079 ps
CPU time	6.83 seconds
Started	May 23 04:33:20 PM PDT 24
Finished	May 23 04:33:27 PM PDT 24
Peak memory	563524 kb
Host	smart-da083c89-cc99-49c4-9e10-648246c2ba9b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264321677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2264321677
Directory	/workspace/53.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.986100034
Short name	T2359
Test name
Test status
Simulation time	8366218785 ps
CPU time	95.14 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:34:57 PM PDT 24
Peak memory	563804 kb
Host	smart-a06495a5-9a54-4960-91c8-91d19ca81b25
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986100034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.986100034
Directory	/workspace/53.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1823461930
Short name	T528
Test name
Test status
Simulation time	4956039909 ps
CPU time	86.2 seconds
Started	May 23 04:33:22 PM PDT 24
Finished	May 23 04:34:50 PM PDT 24
Peak memory	563780 kb
Host	smart-d059a2d1-abbf-4a86-af4c-d1e719ba5763
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823461930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1823461930
Directory	/workspace/53.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2442997417
Short name	T2518
Test name
Test status
Simulation time	39744500 ps
CPU time	6.18 seconds
Started	May 23 04:33:22 PM PDT 24
Finished	May 23 04:33:30 PM PDT 24
Peak memory	563476 kb
Host	smart-dd577240-8131-4476-8e4f-7479cd65fb62
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442997417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.2442997417
Directory	/workspace/53.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all.3657717853
Short name	T468
Test name
Test status
Simulation time	1342533797 ps
CPU time	127.94 seconds
Started	May 23 04:33:27 PM PDT 24
Finished	May 23 04:35:35 PM PDT 24
Peak memory	571932 kb
Host	smart-9f772491-4d0c-41da-aaf0-61c265d1c599
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657717853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.3657717853
Directory	/workspace/53.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1690870405
Short name	T1805
Test name
Test status
Simulation time	10222919049 ps
CPU time	334.69 seconds
Started	May 23 04:33:26 PM PDT 24
Finished	May 23 04:39:02 PM PDT 24
Peak memory	572036 kb
Host	smart-5daf1c60-11cd-4f39-b718-fbab6c1e7173
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690870405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1690870405
Directory	/workspace/53.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3313644828
Short name	T1496
Test name
Test status
Simulation time	2694577766 ps
CPU time	275.58 seconds
Started	May 23 04:33:24 PM PDT 24
Finished	May 23 04:38:01 PM PDT 24
Peak memory	573008 kb
Host	smart-952148df-af4f-4cd1-8aa6-85a1ff51e1d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313644828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.3313644828
Directory	/workspace/53.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.3910037942
Short name	T813
Test name
Test status
Simulation time	189509135 ps
CPU time	68.24 seconds
Started	May 23 04:33:23 PM PDT 24
Finished	May 23 04:34:33 PM PDT 24
Peak memory	572916 kb
Host	smart-6339dec8-94a9-4d86-9ea2-e1e8da1f305f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910037942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.3910037942
Directory	/workspace/53.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2290643460
Short name	T2088
Test name
Test status
Simulation time	33842633 ps
CPU time	7.77 seconds
Started	May 23 04:33:21 PM PDT 24
Finished	May 23 04:33:30 PM PDT 24
Peak memory	563676 kb
Host	smart-135705a4-de6e-4858-af59-feaf293c0334
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290643460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2290643460
Directory	/workspace/53.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_access_same_device.557536910
Short name	T2210
Test name
Test status
Simulation time	3178641788 ps
CPU time	157.37 seconds
Started	May 23 04:33:24 PM PDT 24
Finished	May 23 04:36:03 PM PDT 24
Peak memory	571952 kb
Host	smart-1b54f6a9-358a-4e65-a1f4-f8e452e13f5d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557536910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device. 557536910
Directory	/workspace/54.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2300024036
Short name	T806
Test name
Test status
Simulation time	9570199916 ps
CPU time	171.13 seconds
Started	May 23 04:33:37 PM PDT 24
Finished	May 23 04:36:30 PM PDT 24
Peak memory	563796 kb
Host	smart-1ad3aeaf-a691-47f8-8cbd-8fae37bd402a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300024036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.2300024036
Directory	/workspace/54.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.936676217
Short name	T2487
Test name
Test status
Simulation time	1273542380 ps
CPU time	52.62 seconds
Started	May 23 04:33:34 PM PDT 24
Finished	May 23 04:34:27 PM PDT 24
Peak memory	571836 kb
Host	smart-cc6616e0-54f6-4ad9-814f-ea0205a6d464
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936676217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr .936676217
Directory	/workspace/54.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_error_random.3710709918
Short name	T1546
Test name
Test status
Simulation time	145119554 ps
CPU time	13.93 seconds
Started	May 23 04:33:36 PM PDT 24
Finished	May 23 04:33:51 PM PDT 24
Peak memory	571700 kb
Host	smart-9fb6e581-de44-4c0e-b522-1547cba4f694
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710709918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.3710709918
Directory	/workspace/54.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_random.1754742014
Short name	T1364
Test name
Test status
Simulation time	304257415 ps
CPU time	26.15 seconds
Started	May 23 04:33:20 PM PDT 24
Finished	May 23 04:33:47 PM PDT 24
Peak memory	571848 kb
Host	smart-58160b18-9f4f-4a74-a8a9-2bf3cb43f31b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754742014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.1754742014
Directory	/workspace/54.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2890681390
Short name	T424
Test name
Test status
Simulation time	62145904441 ps
CPU time	653.92 seconds
Started	May 23 04:33:27 PM PDT 24
Finished	May 23 04:44:22 PM PDT 24
Peak memory	572004 kb
Host	smart-66a22810-9150-4686-a0f5-1e7d441d1e93
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890681390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2890681390
Directory	/workspace/54.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.3881865781
Short name	T419
Test name
Test status
Simulation time	31068076614 ps
CPU time	515.55 seconds
Started	May 23 04:33:20 PM PDT 24
Finished	May 23 04:41:56 PM PDT 24
Peak memory	572012 kb
Host	smart-ef9983c2-8a97-4c0c-a45d-0436449a2f3a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881865781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.3881865781
Directory	/workspace/54.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.983408249
Short name	T2593
Test name
Test status
Simulation time	321283041 ps
CPU time	32.76 seconds
Started	May 23 04:33:23 PM PDT 24
Finished	May 23 04:33:57 PM PDT 24
Peak memory	571800 kb
Host	smart-3174a28e-a24d-4308-9cff-e2fc4edae4e4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983408249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_dela ys.983408249
Directory	/workspace/54.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_same_source.2318202299
Short name	T1790
Test name
Test status
Simulation time	448901329 ps
CPU time	16.47 seconds
Started	May 23 04:33:34 PM PDT 24
Finished	May 23 04:33:52 PM PDT 24
Peak memory	571800 kb
Host	smart-17ce1ce1-beef-4e4b-9eee-fc969113491c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318202299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.2318202299
Directory	/workspace/54.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke.2914619063
Short name	T1577
Test name
Test status
Simulation time	46170522 ps
CPU time	6.37 seconds
Started	May 23 04:33:25 PM PDT 24
Finished	May 23 04:33:33 PM PDT 24
Peak memory	563472 kb
Host	smart-a10405a9-9ec6-4475-81d7-8aa5d4a13276
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914619063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.2914619063
Directory	/workspace/54.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.1103013937
Short name	T1817
Test name
Test status
Simulation time	6538772997 ps
CPU time	71.62 seconds
Started	May 23 04:33:23 PM PDT 24
Finished	May 23 04:34:36 PM PDT 24
Peak memory	563796 kb
Host	smart-939f590c-963d-4772-805d-223d7341d342
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103013937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.1103013937
Directory	/workspace/54.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.4169568309
Short name	T1328
Test name
Test status
Simulation time	3369079899 ps
CPU time	60.52 seconds
Started	May 23 04:33:23 PM PDT 24
Finished	May 23 04:34:25 PM PDT 24
Peak memory	563732 kb
Host	smart-dedba6e4-c5d5-4ef8-a310-7e0a4a122de6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169568309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.4169568309
Directory	/workspace/54.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1562650604
Short name	T1374
Test name
Test status
Simulation time	46472012 ps
CPU time	6.57 seconds
Started	May 23 04:33:23 PM PDT 24
Finished	May 23 04:33:31 PM PDT 24
Peak memory	563544 kb
Host	smart-a43b7351-dda8-41c6-8769-2d0a45a1fd7d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562650604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1562650604
Directory	/workspace/54.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all.2415946528
Short name	T1922
Test name
Test status
Simulation time	2558643076 ps
CPU time	116.67 seconds
Started	May 23 04:33:34 PM PDT 24
Finished	May 23 04:35:32 PM PDT 24
Peak memory	571944 kb
Host	smart-ad4aa1bd-297d-4e10-baae-c7d95a878aa7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415946528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.2415946528
Directory	/workspace/54.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.1216433895
Short name	T790
Test name
Test status
Simulation time	8670909612 ps
CPU time	358.3 seconds
Started	May 23 04:33:36 PM PDT 24
Finished	May 23 04:39:36 PM PDT 24
Peak memory	572064 kb
Host	smart-6cc4a454-e9ea-4c9b-bbd2-c8fcf474937a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216433895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.1216433895
Directory	/workspace/54.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.1880081523
Short name	T2130
Test name
Test status
Simulation time	11366570483 ps
CPU time	566.17 seconds
Started	May 23 04:33:35 PM PDT 24
Finished	May 23 04:43:02 PM PDT 24
Peak memory	573020 kb
Host	smart-651d7982-f715-4d9e-aa1c-e72bdc3dc1b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880081523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.1880081523
Directory	/workspace/54.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.407020006
Short name	T503
Test name
Test status
Simulation time	287043934 ps
CPU time	50.65 seconds
Started	May 23 04:33:38 PM PDT 24
Finished	May 23 04:34:30 PM PDT 24
Peak memory	571920 kb
Host	smart-24b7aadb-d86c-4a7d-8275-a0f8b682da38
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407020006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_reset_error.407020006
Directory	/workspace/54.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.2289221668
Short name	T1892
Test name
Test status
Simulation time	311591237 ps
CPU time	44.98 seconds
Started	May 23 04:33:35 PM PDT 24
Finished	May 23 04:34:21 PM PDT 24
Peak memory	571840 kb
Host	smart-40585a47-66b7-45ea-9b5a-eb223088e520
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289221668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.2289221668
Directory	/workspace/54.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_access_same_device.3577792392
Short name	T1564
Test name
Test status
Simulation time	779812224 ps
CPU time	43.54 seconds
Started	May 23 04:33:35 PM PDT 24
Finished	May 23 04:34:20 PM PDT 24
Peak memory	571840 kb
Host	smart-ea365d0c-e20a-45a8-8fd4-f86ef7de1603
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577792392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .3577792392
Directory	/workspace/55.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3376369787
Short name	T2159
Test name
Test status
Simulation time	13562186267 ps
CPU time	247.18 seconds
Started	May 23 04:33:38 PM PDT 24
Finished	May 23 04:37:47 PM PDT 24
Peak memory	572056 kb
Host	smart-e36033eb-9a1e-4e59-9da1-3a1278687d63
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376369787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.3376369787
Directory	/workspace/55.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3760181633
Short name	T1958
Test name
Test status
Simulation time	1002887406 ps
CPU time	40.91 seconds
Started	May 23 04:33:33 PM PDT 24
Finished	May 23 04:34:15 PM PDT 24
Peak memory	571820 kb
Host	smart-80f11204-d554-4381-9930-c426f01c51d7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760181633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.3760181633
Directory	/workspace/55.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_error_random.3791936664
Short name	T1357
Test name
Test status
Simulation time	308289368 ps
CPU time	12.99 seconds
Started	May 23 04:33:35 PM PDT 24
Finished	May 23 04:33:49 PM PDT 24
Peak memory	563572 kb
Host	smart-36aab5e8-9e01-4cba-92a8-2b5ea74fc143
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791936664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.3791936664
Directory	/workspace/55.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_random.4113810012
Short name	T593
Test name
Test status
Simulation time	564932214 ps
CPU time	56.27 seconds
Started	May 23 04:33:34 PM PDT 24
Finished	May 23 04:34:32 PM PDT 24
Peak memory	571764 kb
Host	smart-594be5fa-5ef6-4afd-9518-d6bc3817ee89
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113810012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.4113810012
Directory	/workspace/55.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_random_large_delays.1124853814
Short name	T1909
Test name
Test status
Simulation time	57250412606 ps
CPU time	611.38 seconds
Started	May 23 04:33:36 PM PDT 24
Finished	May 23 04:43:49 PM PDT 24
Peak memory	572028 kb
Host	smart-5b4fec9b-0bd4-4086-a104-83d3d79db82f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124853814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.1124853814
Directory	/workspace/55.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.606466915
Short name	T2704
Test name
Test status
Simulation time	10538671331 ps
CPU time	199.16 seconds
Started	May 23 04:33:35 PM PDT 24
Finished	May 23 04:36:56 PM PDT 24
Peak memory	572000 kb
Host	smart-ab172689-49d2-4bf2-b2ea-64d32f3c432a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606466915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.606466915
Directory	/workspace/55.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1798487732
Short name	T2002
Test name
Test status
Simulation time	550899166 ps
CPU time	48.94 seconds
Started	May 23 04:33:37 PM PDT 24
Finished	May 23 04:34:27 PM PDT 24
Peak memory	571720 kb
Host	smart-3cdbdbdc-ca0a-4181-b523-8dc343888200
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798487732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.1798487732
Directory	/workspace/55.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_same_source.3507085551
Short name	T2569
Test name
Test status
Simulation time	1450858943 ps
CPU time	47.19 seconds
Started	May 23 04:33:36 PM PDT 24
Finished	May 23 04:34:24 PM PDT 24
Peak memory	571784 kb
Host	smart-33a77cb7-d9dd-40b3-93de-28e6385ebb2c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507085551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.3507085551
Directory	/workspace/55.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke.4017396840
Short name	T585
Test name
Test status
Simulation time	38024917 ps
CPU time	5.22 seconds
Started	May 23 04:33:36 PM PDT 24
Finished	May 23 04:33:42 PM PDT 24
Peak memory	563508 kb
Host	smart-83028a16-58c8-46c0-bc9c-bd5488847ebf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017396840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.4017396840
Directory	/workspace/55.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.1504404307
Short name	T1468
Test name
Test status
Simulation time	8712626645 ps
CPU time	93.63 seconds
Started	May 23 04:33:37 PM PDT 24
Finished	May 23 04:35:12 PM PDT 24
Peak memory	563748 kb
Host	smart-515f9301-3849-426e-a358-38179a6fb4a4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504404307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.1504404307
Directory	/workspace/55.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.4049250132
Short name	T1382
Test name
Test status
Simulation time	5267102151 ps
CPU time	99.66 seconds
Started	May 23 04:33:36 PM PDT 24
Finished	May 23 04:35:16 PM PDT 24
Peak memory	563792 kb
Host	smart-b02b1067-464e-4b4a-9104-5896d9cc2440
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049250132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.4049250132
Directory	/workspace/55.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.4238473312
Short name	T2097
Test name
Test status
Simulation time	57083044 ps
CPU time	7.17 seconds
Started	May 23 04:33:37 PM PDT 24
Finished	May 23 04:33:46 PM PDT 24
Peak memory	563556 kb
Host	smart-cf7fe561-2466-4fc8-9084-09751c501b6d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238473312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.4238473312
Directory	/workspace/55.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all.3914943022
Short name	T2479
Test name
Test status
Simulation time	20251647782 ps
CPU time	739.37 seconds
Started	May 23 04:33:50 PM PDT 24
Finished	May 23 04:46:12 PM PDT 24
Peak memory	573036 kb
Host	smart-ad7ccf57-ca65-4187-bcd9-d008f8a70362
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914943022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3914943022
Directory	/workspace/55.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3253023684
Short name	T1883
Test name
Test status
Simulation time	3687246159 ps
CPU time	136.32 seconds
Started	May 23 04:33:49 PM PDT 24
Finished	May 23 04:36:08 PM PDT 24
Peak memory	572036 kb
Host	smart-edbb486d-d0b1-4b2f-93ee-1d2f0ec63bb5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253023684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.3253023684
Directory	/workspace/55.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3613917852
Short name	T512
Test name
Test status
Simulation time	2968564206 ps
CPU time	104.28 seconds
Started	May 23 04:33:48 PM PDT 24
Finished	May 23 04:35:33 PM PDT 24
Peak memory	572016 kb
Host	smart-e18f941b-c1fa-4445-ab00-4a352a23d412
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613917852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.3613917852
Directory	/workspace/55.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3860777498
Short name	T1766
Test name
Test status
Simulation time	118414477 ps
CPU time	15.23 seconds
Started	May 23 04:33:35 PM PDT 24
Finished	May 23 04:33:52 PM PDT 24
Peak memory	571872 kb
Host	smart-49f1f3f1-a91b-488a-95f2-c1f263074a11
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860777498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3860777498
Directory	/workspace/55.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_access_same_device.3954577974
Short name	T774
Test name
Test status
Simulation time	2140152749 ps
CPU time	86.54 seconds
Started	May 23 04:33:47 PM PDT 24
Finished	May 23 04:35:15 PM PDT 24
Peak memory	571824 kb
Host	smart-9b876ba6-64c9-4615-97b1-640859849ce4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954577974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .3954577974
Directory	/workspace/56.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3572318654
Short name	T781
Test name
Test status
Simulation time	84462315831 ps
CPU time	1488 seconds
Started	May 23 04:33:49 PM PDT 24
Finished	May 23 04:58:39 PM PDT 24
Peak memory	572052 kb
Host	smart-80b239ef-744a-4905-87ec-4030c7f18543
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572318654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.3572318654
Directory	/workspace/56.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3696046730
Short name	T2467
Test name
Test status
Simulation time	112393015 ps
CPU time	15.1 seconds
Started	May 23 04:33:53 PM PDT 24
Finished	May 23 04:34:09 PM PDT 24
Peak memory	571800 kb
Host	smart-b9421cc2-eb22-49c1-9c54-fa02536b5f33
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696046730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.3696046730
Directory	/workspace/56.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_error_random.4070603
Short name	T1303
Test name
Test status
Simulation time	2388833609 ps
CPU time	78.9 seconds
Started	May 23 04:33:49 PM PDT 24
Finished	May 23 04:35:10 PM PDT 24
Peak memory	571968 kb
Host	smart-2b30c93e-59a5-476a-8f3f-cbfe91e7ac32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.4070603
Directory	/workspace/56.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_random.446158174
Short name	T2112
Test name
Test status
Simulation time	1312591516 ps
CPU time	49.13 seconds
Started	May 23 04:33:51 PM PDT 24
Finished	May 23 04:34:42 PM PDT 24
Peak memory	571832 kb
Host	smart-feef8e6f-985b-48c8-8a68-d5d297c92c6f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446158174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.446158174
Directory	/workspace/56.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_random_large_delays.654112507
Short name	T2637
Test name
Test status
Simulation time	60690991753 ps
CPU time	616.06 seconds
Started	May 23 04:33:49 PM PDT 24
Finished	May 23 04:44:07 PM PDT 24
Peak memory	572024 kb
Host	smart-a60f0846-0903-47c8-91a9-1d9298f2096d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654112507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.654112507
Directory	/workspace/56.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.1640820271
Short name	T1993
Test name
Test status
Simulation time	35939119590 ps
CPU time	637.38 seconds
Started	May 23 04:33:50 PM PDT 24
Finished	May 23 04:44:29 PM PDT 24
Peak memory	571984 kb
Host	smart-23098997-0f82-430c-8723-18c05950b542
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640820271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.1640820271
Directory	/workspace/56.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.1673241473
Short name	T2221
Test name
Test status
Simulation time	186101748 ps
CPU time	18.54 seconds
Started	May 23 04:33:47 PM PDT 24
Finished	May 23 04:34:07 PM PDT 24
Peak memory	571764 kb
Host	smart-b6d74465-b6ec-4f81-b35d-ae4ea972088a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673241473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.1673241473
Directory	/workspace/56.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_same_source.2699567812
Short name	T2216
Test name
Test status
Simulation time	310842336 ps
CPU time	28.08 seconds
Started	May 23 04:33:52 PM PDT 24
Finished	May 23 04:34:21 PM PDT 24
Peak memory	571740 kb
Host	smart-dac2d66f-b90b-4558-8f2d-c9c69e40ab72
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699567812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.2699567812
Directory	/workspace/56.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke.3701085346
Short name	T1484
Test name
Test status
Simulation time	223243542 ps
CPU time	10.05 seconds
Started	May 23 04:33:48 PM PDT 24
Finished	May 23 04:33:59 PM PDT 24
Peak memory	563504 kb
Host	smart-db426d58-299c-4339-bf29-b0aa26458be0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701085346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.3701085346
Directory	/workspace/56.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.2617415050
Short name	T2429
Test name
Test status
Simulation time	7771886227 ps
CPU time	84.64 seconds
Started	May 23 04:33:52 PM PDT 24
Finished	May 23 04:35:17 PM PDT 24
Peak memory	563780 kb
Host	smart-b7a1130a-41c9-40c0-b053-be34f93cb573
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617415050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.2617415050
Directory	/workspace/56.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2654685930
Short name	T2354
Test name
Test status
Simulation time	4779135441 ps
CPU time	89.22 seconds
Started	May 23 04:33:49 PM PDT 24
Finished	May 23 04:35:20 PM PDT 24
Peak memory	563780 kb
Host	smart-12813b8a-698e-45a1-afac-20737b625a19
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654685930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2654685930
Directory	/workspace/56.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.1770529569
Short name	T1878
Test name
Test status
Simulation time	35665832 ps
CPU time	6.43 seconds
Started	May 23 04:33:48 PM PDT 24
Finished	May 23 04:33:56 PM PDT 24
Peak memory	563560 kb
Host	smart-4a8a4504-fc05-412b-ac01-b5b34c34f651
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770529569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.1770529569
Directory	/workspace/56.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all.3630445437
Short name	T452
Test name
Test status
Simulation time	15170301436 ps
CPU time	619.12 seconds
Started	May 23 04:33:47 PM PDT 24
Finished	May 23 04:44:08 PM PDT 24
Peak memory	571928 kb
Host	smart-7b541e88-f925-4b52-abff-d0dd0a550564
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630445437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3630445437
Directory	/workspace/56.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.4221811257
Short name	T2587
Test name
Test status
Simulation time	17428930650 ps
CPU time	727.26 seconds
Started	May 23 04:33:52 PM PDT 24
Finished	May 23 04:46:00 PM PDT 24
Peak memory	571972 kb
Host	smart-d9132b08-ce33-496f-8102-822ed0d33d8d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221811257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.4221811257
Directory	/workspace/56.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3569504337
Short name	T2236
Test name
Test status
Simulation time	71250761 ps
CPU time	33.82 seconds
Started	May 23 04:33:49 PM PDT 24
Finished	May 23 04:34:25 PM PDT 24
Peak memory	572948 kb
Host	smart-9f959b35-5cec-4dfd-8940-f70a99c4ce89
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569504337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.3569504337
Directory	/workspace/56.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.583018382
Short name	T2099
Test name
Test status
Simulation time	1510888982 ps
CPU time	152.1 seconds
Started	May 23 04:33:49 PM PDT 24
Finished	May 23 04:36:22 PM PDT 24
Peak memory	572888 kb
Host	smart-34a122c7-4e4f-4f6d-8e3b-3cf7734e1577
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583018382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_reset_error.583018382
Directory	/workspace/56.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3496389265
Short name	T1986
Test name
Test status
Simulation time	941344582 ps
CPU time	40.39 seconds
Started	May 23 04:33:50 PM PDT 24
Finished	May 23 04:34:32 PM PDT 24
Peak memory	571888 kb
Host	smart-c76d90c7-71e9-463c-8a62-1175677f997b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496389265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3496389265
Directory	/workspace/56.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_access_same_device.3100534490
Short name	T1802
Test name
Test status
Simulation time	1021641080 ps
CPU time	45.11 seconds
Started	May 23 04:34:08 PM PDT 24
Finished	May 23 04:34:54 PM PDT 24
Peak memory	571872 kb
Host	smart-9797c64c-42dd-431c-a163-c6bb3da027e4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100534490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .3100534490
Directory	/workspace/57.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.808510109
Short name	T470
Test name
Test status
Simulation time	94569523634 ps
CPU time	1615.89 seconds
Started	May 23 04:34:04 PM PDT 24
Finished	May 23 05:01:02 PM PDT 24
Peak memory	572032 kb
Host	smart-a1efe0ac-97a5-4b2a-b640-e9471d56250d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808510109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_d evice_slow_rsp.808510109
Directory	/workspace/57.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3194120159
Short name	T1255
Test name
Test status
Simulation time	352776822 ps
CPU time	18.6 seconds
Started	May 23 04:34:04 PM PDT 24
Finished	May 23 04:34:24 PM PDT 24
Peak memory	571760 kb
Host	smart-411cea90-f5f6-442e-a9e8-f64b10b5904c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194120159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.3194120159
Directory	/workspace/57.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_error_random.1881984752
Short name	T2167
Test name
Test status
Simulation time	559046563 ps
CPU time	49.66 seconds
Started	May 23 04:34:04 PM PDT 24
Finished	May 23 04:34:56 PM PDT 24
Peak memory	571840 kb
Host	smart-22106844-d200-4141-aca3-1c8ec9ca9847
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881984752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.1881984752
Directory	/workspace/57.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_random.3186473624
Short name	T472
Test name
Test status
Simulation time	601815607 ps
CPU time	52.07 seconds
Started	May 23 04:34:03 PM PDT 24
Finished	May 23 04:34:57 PM PDT 24
Peak memory	571812 kb
Host	smart-9d89b9c0-0c33-4173-9c16-6e83c62efbd0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186473624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.3186473624
Directory	/workspace/57.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_random_large_delays.297385178
Short name	T580
Test name
Test status
Simulation time	102018036368 ps
CPU time	1099.51 seconds
Started	May 23 04:34:04 PM PDT 24
Finished	May 23 04:52:25 PM PDT 24
Peak memory	572016 kb
Host	smart-7d1be296-c027-4798-bac8-93bfaac809d8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297385178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.297385178
Directory	/workspace/57.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.2777166149
Short name	T1813
Test name
Test status
Simulation time	36270807221 ps
CPU time	670 seconds
Started	May 23 04:34:09 PM PDT 24
Finished	May 23 04:45:20 PM PDT 24
Peak memory	572052 kb
Host	smart-81b3e4ed-7314-45b8-b466-a30c0a69cc03
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777166149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.2777166149
Directory	/workspace/57.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.3531713719
Short name	T2486
Test name
Test status
Simulation time	187791466 ps
CPU time	20.08 seconds
Started	May 23 04:34:06 PM PDT 24
Finished	May 23 04:34:28 PM PDT 24
Peak memory	571800 kb
Host	smart-c8904bd9-3768-4646-abe3-d83cf72719f7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531713719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.3531713719
Directory	/workspace/57.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_same_source.652570233
Short name	T2488
Test name
Test status
Simulation time	286059061 ps
CPU time	11.14 seconds
Started	May 23 04:34:05 PM PDT 24
Finished	May 23 04:34:18 PM PDT 24
Peak memory	563588 kb
Host	smart-171188ce-2cf8-4cd3-ada4-503960c35821
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652570233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.652570233
Directory	/workspace/57.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke.485897422
Short name	T1293
Test name
Test status
Simulation time	42993592 ps
CPU time	6.81 seconds
Started	May 23 04:33:48 PM PDT 24
Finished	May 23 04:33:57 PM PDT 24
Peak memory	563572 kb
Host	smart-6abfa9d7-6450-408f-9673-052b77f368d7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485897422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.485897422
Directory	/workspace/57.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.3625729126
Short name	T2390
Test name
Test status
Simulation time	6605472323 ps
CPU time	74.87 seconds
Started	May 23 04:33:49 PM PDT 24
Finished	May 23 04:35:05 PM PDT 24
Peak memory	563756 kb
Host	smart-d7445865-fb2a-4176-bf5d-0d07b12a1dfb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625729126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.3625729126
Directory	/workspace/57.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2754424585
Short name	T2171
Test name
Test status
Simulation time	5082409135 ps
CPU time	88.37 seconds
Started	May 23 04:33:52 PM PDT 24
Finished	May 23 04:35:22 PM PDT 24
Peak memory	563752 kb
Host	smart-c152d6f2-ca28-434b-b4d3-ea19dac0e645
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754424585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2754424585
Directory	/workspace/57.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3207334001
Short name	T2125
Test name
Test status
Simulation time	47300235 ps
CPU time	7.31 seconds
Started	May 23 04:33:52 PM PDT 24
Finished	May 23 04:34:00 PM PDT 24
Peak memory	563568 kb
Host	smart-1bb6603b-bc6a-4382-9f16-ea4185c0bbd5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207334001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.3207334001
Directory	/workspace/57.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all.1659335469
Short name	T2689
Test name
Test status
Simulation time	2685607705 ps
CPU time	257.45 seconds
Started	May 23 04:34:05 PM PDT 24
Finished	May 23 04:38:24 PM PDT 24
Peak memory	571968 kb
Host	smart-fcd1e1be-7d85-43c3-a1b3-cf96e2cbe98b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659335469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.1659335469
Directory	/workspace/57.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3234264943
Short name	T2712
Test name
Test status
Simulation time	6247584408 ps
CPU time	222.62 seconds
Started	May 23 04:34:05 PM PDT 24
Finished	May 23 04:37:50 PM PDT 24
Peak memory	572056 kb
Host	smart-3dd2ddd2-dc90-4b00-84f0-93f681db3640
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234264943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.3234264943
Directory	/workspace/57.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.805499781
Short name	T2200
Test name
Test status
Simulation time	6834096 ps
CPU time	4.16 seconds
Started	May 23 04:34:03 PM PDT 24
Finished	May 23 04:34:09 PM PDT 24
Peak memory	563444 kb
Host	smart-b99d078a-f5d3-4c10-9f2c-d70f4c815df5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805499781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_ with_rand_reset.805499781
Directory	/workspace/57.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1604215791
Short name	T2613
Test name
Test status
Simulation time	23888961910 ps
CPU time	1006.27 seconds
Started	May 23 04:34:05 PM PDT 24
Finished	May 23 04:50:53 PM PDT 24
Peak memory	575192 kb
Host	smart-a94db7f5-6269-432e-828a-b1210833b08f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604215791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.1604215791
Directory	/workspace/57.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.423530486
Short name	T2418
Test name
Test status
Simulation time	182641302 ps
CPU time	11.54 seconds
Started	May 23 04:34:05 PM PDT 24
Finished	May 23 04:34:18 PM PDT 24
Peak memory	563640 kb
Host	smart-98fbfb6e-b468-4194-b338-ea12bc551cae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423530486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.423530486
Directory	/workspace/57.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_access_same_device.1181581088
Short name	T460
Test name
Test status
Simulation time	3580401272 ps
CPU time	158.03 seconds
Started	May 23 04:34:05 PM PDT 24
Finished	May 23 04:36:45 PM PDT 24
Peak memory	571932 kb
Host	smart-d8265ed9-e1b2-4c62-8fdb-554e079998ab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181581088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .1181581088
Directory	/workspace/58.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3412106233
Short name	T783
Test name
Test status
Simulation time	8337057647 ps
CPU time	150.47 seconds
Started	May 23 04:34:06 PM PDT 24
Finished	May 23 04:36:38 PM PDT 24
Peak memory	572048 kb
Host	smart-5170c2c9-9df4-4f26-88c6-ce095bcdfa53
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412106233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.3412106233
Directory	/workspace/58.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2619095665
Short name	T1362
Test name
Test status
Simulation time	246022426 ps
CPU time	12.14 seconds
Started	May 23 04:34:15 PM PDT 24
Finished	May 23 04:34:28 PM PDT 24
Peak memory	563656 kb
Host	smart-17a4c540-2155-4dfa-af81-11908e048d97
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619095665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.2619095665
Directory	/workspace/58.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_error_random.2361751220
Short name	T2563
Test name
Test status
Simulation time	632198697 ps
CPU time	24.64 seconds
Started	May 23 04:34:10 PM PDT 24
Finished	May 23 04:34:36 PM PDT 24
Peak memory	571824 kb
Host	smart-52a786a9-ec3e-469f-9ced-ed431f9ae1af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361751220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.2361751220
Directory	/workspace/58.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_random.747134975
Short name	T2394
Test name
Test status
Simulation time	178143427 ps
CPU time	18.59 seconds
Started	May 23 04:34:15 PM PDT 24
Finished	May 23 04:34:34 PM PDT 24
Peak memory	571800 kb
Host	smart-e3c22078-7f50-48ac-a18f-eb3de23f45fc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747134975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.747134975
Directory	/workspace/58.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_random_large_delays.712856318
Short name	T535
Test name
Test status
Simulation time	95249993835 ps
CPU time	1025.84 seconds
Started	May 23 04:34:10 PM PDT 24
Finished	May 23 04:51:17 PM PDT 24
Peak memory	572068 kb
Host	smart-6d6923ad-5476-4724-a484-e6d8a8a09a13
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712856318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.712856318
Directory	/workspace/58.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.2875178759
Short name	T1568
Test name
Test status
Simulation time	8380921801 ps
CPU time	158.6 seconds
Started	May 23 04:34:14 PM PDT 24
Finished	May 23 04:36:54 PM PDT 24
Peak memory	572048 kb
Host	smart-325455d8-10dd-486e-8cec-09fe651e3b46
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875178759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.2875178759
Directory	/workspace/58.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3582390330
Short name	T2215
Test name
Test status
Simulation time	99300240 ps
CPU time	12.47 seconds
Started	May 23 04:34:07 PM PDT 24
Finished	May 23 04:34:20 PM PDT 24
Peak memory	571792 kb
Host	smart-5061baed-be35-4c66-8eea-c5b3a24eee74
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582390330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.3582390330
Directory	/workspace/58.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_same_source.3374292906
Short name	T448
Test name
Test status
Simulation time	695674564 ps
CPU time	26.55 seconds
Started	May 23 04:34:04 PM PDT 24
Finished	May 23 04:34:33 PM PDT 24
Peak memory	571832 kb
Host	smart-e7e807a5-068a-436d-a868-06f897c22b13
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374292906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.3374292906
Directory	/workspace/58.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke.3077427075
Short name	T1308
Test name
Test status
Simulation time	133121311 ps
CPU time	8.17 seconds
Started	May 23 04:34:15 PM PDT 24
Finished	May 23 04:34:24 PM PDT 24
Peak memory	563544 kb
Host	smart-0cf86d85-590b-4605-b39a-5bd0bf41b688
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077427075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.3077427075
Directory	/workspace/58.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2763682611
Short name	T2110
Test name
Test status
Simulation time	10326335460 ps
CPU time	116.14 seconds
Started	May 23 04:34:05 PM PDT 24
Finished	May 23 04:36:03 PM PDT 24
Peak memory	563768 kb
Host	smart-387c5720-39d9-4360-acd9-50f1b221a41c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763682611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.2763682611
Directory	/workspace/58.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2510106439
Short name	T1425
Test name
Test status
Simulation time	4604615065 ps
CPU time	82.88 seconds
Started	May 23 04:34:04 PM PDT 24
Finished	May 23 04:35:29 PM PDT 24
Peak memory	563744 kb
Host	smart-a76787f1-b014-487d-85e0-32f8c65814dd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510106439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2510106439
Directory	/workspace/58.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2787876434
Short name	T1954
Test name
Test status
Simulation time	37068332 ps
CPU time	5.88 seconds
Started	May 23 04:34:09 PM PDT 24
Finished	May 23 04:34:15 PM PDT 24
Peak memory	563568 kb
Host	smart-47dda839-0263-4b3f-a3f5-0da5357e231d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787876434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.2787876434
Directory	/workspace/58.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all.3847147726
Short name	T1397
Test name
Test status
Simulation time	3327630672 ps
CPU time	133.18 seconds
Started	May 23 04:34:03 PM PDT 24
Finished	May 23 04:36:18 PM PDT 24
Peak memory	571960 kb
Host	smart-f2280237-bf1b-4ed0-a397-7f4c7b373b4b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847147726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.3847147726
Directory	/workspace/58.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.3948055953
Short name	T2023
Test name
Test status
Simulation time	7165140364 ps
CPU time	257.31 seconds
Started	May 23 04:34:04 PM PDT 24
Finished	May 23 04:38:23 PM PDT 24
Peak memory	572100 kb
Host	smart-7dfa72bd-a1f9-4373-8531-520c1b7f66f6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948055953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.3948055953
Directory	/workspace/58.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3030059583
Short name	T1664
Test name
Test status
Simulation time	1614646285 ps
CPU time	320.72 seconds
Started	May 23 04:34:04 PM PDT 24
Finished	May 23 04:39:27 PM PDT 24
Peak memory	572968 kb
Host	smart-bf02a087-746f-429c-a4ce-f5a94c5bd871
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030059583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3030059583
Directory	/workspace/58.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3408583543
Short name	T835
Test name
Test status
Simulation time	379185561 ps
CPU time	72.36 seconds
Started	May 23 04:34:03 PM PDT 24
Finished	May 23 04:35:17 PM PDT 24
Peak memory	572340 kb
Host	smart-eab24645-17bd-43cd-9a6a-e5f6d2d2c435
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408583543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.3408583543
Directory	/workspace/58.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2446766486
Short name	T2601
Test name
Test status
Simulation time	283159336 ps
CPU time	35.58 seconds
Started	May 23 04:34:15 PM PDT 24
Finished	May 23 04:34:52 PM PDT 24
Peak memory	571888 kb
Host	smart-45340216-72e3-4e07-9256-ef7d43baf051
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446766486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2446766486
Directory	/workspace/58.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_access_same_device.3118624585
Short name	T2541
Test name
Test status
Simulation time	2372364373 ps
CPU time	105.59 seconds
Started	May 23 04:34:26 PM PDT 24
Finished	May 23 04:36:12 PM PDT 24
Peak memory	571952 kb
Host	smart-fa3e5846-46f4-454a-b4b1-40d100f49dd2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118624585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .3118624585
Directory	/workspace/59.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.284914212
Short name	T1704
Test name
Test status
Simulation time	72440103585 ps
CPU time	1272.36 seconds
Started	May 23 04:34:20 PM PDT 24
Finished	May 23 04:55:34 PM PDT 24
Peak memory	572060 kb
Host	smart-cf348bc3-8174-4b88-9fa0-44a25114b332
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284914212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_d evice_slow_rsp.284914212
Directory	/workspace/59.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3710336999
Short name	T2652
Test name
Test status
Simulation time	748444879 ps
CPU time	32.24 seconds
Started	May 23 04:34:18 PM PDT 24
Finished	May 23 04:34:52 PM PDT 24
Peak memory	571768 kb
Host	smart-1665ed56-6c0f-4bbf-bc9b-3525aa964028
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710336999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.3710336999
Directory	/workspace/59.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_error_random.3949443829
Short name	T2554
Test name
Test status
Simulation time	977918593 ps
CPU time	37.27 seconds
Started	May 23 04:34:20 PM PDT 24
Finished	May 23 04:34:59 PM PDT 24
Peak memory	571796 kb
Host	smart-0fd8b274-0964-4ddc-a393-974f866e25d9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949443829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.3949443829
Directory	/workspace/59.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_random.3345392825
Short name	T567
Test name
Test status
Simulation time	1722752444 ps
CPU time	70.8 seconds
Started	May 23 04:34:18 PM PDT 24
Finished	May 23 04:35:30 PM PDT 24
Peak memory	571848 kb
Host	smart-caf37a11-856a-4caf-94c6-b4956ba67d3e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345392825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.3345392825
Directory	/workspace/59.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_random_large_delays.846080158
Short name	T1672
Test name
Test status
Simulation time	6784313085 ps
CPU time	77.75 seconds
Started	May 23 04:34:18 PM PDT 24
Finished	May 23 04:35:37 PM PDT 24
Peak memory	563764 kb
Host	smart-69f54305-e65d-49e2-928a-055da69472aa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846080158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.846080158
Directory	/workspace/59.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1545787856
Short name	T1474
Test name
Test status
Simulation time	20275554650 ps
CPU time	357.6 seconds
Started	May 23 04:34:16 PM PDT 24
Finished	May 23 04:40:15 PM PDT 24
Peak memory	571984 kb
Host	smart-e0c71062-d2c7-4464-8818-1aab9a2b3fd5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545787856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1545787856
Directory	/workspace/59.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.439086310
Short name	T1443
Test name
Test status
Simulation time	504714735 ps
CPU time	53.88 seconds
Started	May 23 04:34:17 PM PDT 24
Finished	May 23 04:35:12 PM PDT 24
Peak memory	571788 kb
Host	smart-385c901a-e33d-4d2b-8916-125ebb54eb5c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439086310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela ys.439086310
Directory	/workspace/59.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_same_source.3005294988
Short name	T1901
Test name
Test status
Simulation time	320925194 ps
CPU time	13.59 seconds
Started	May 23 04:34:20 PM PDT 24
Finished	May 23 04:34:35 PM PDT 24
Peak memory	563552 kb
Host	smart-a17a0f7d-421b-4c62-b8b7-96298da3dad3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005294988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3005294988
Directory	/workspace/59.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke.829051699
Short name	T2789
Test name
Test status
Simulation time	45670103 ps
CPU time	6.13 seconds
Started	May 23 04:34:03 PM PDT 24
Finished	May 23 04:34:10 PM PDT 24
Peak memory	563548 kb
Host	smart-9ddd1780-35a4-4697-aef1-61be35185ce4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829051699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.829051699
Directory	/workspace/59.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.3449407520
Short name	T2021
Test name
Test status
Simulation time	8967752414 ps
CPU time	97.15 seconds
Started	May 23 04:34:05 PM PDT 24
Finished	May 23 04:35:44 PM PDT 24
Peak memory	563748 kb
Host	smart-d351da61-06b3-45ea-b1c4-2db6773ee85d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449407520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.3449407520
Directory	/workspace/59.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1984776370
Short name	T1381
Test name
Test status
Simulation time	6027271595 ps
CPU time	110.23 seconds
Started	May 23 04:34:02 PM PDT 24
Finished	May 23 04:35:54 PM PDT 24
Peak memory	563792 kb
Host	smart-96eb1550-17e2-4c3b-849b-1358fb227ecb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984776370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.1984776370
Directory	/workspace/59.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2994810185
Short name	T1760
Test name
Test status
Simulation time	48344500 ps
CPU time	6.36 seconds
Started	May 23 04:34:11 PM PDT 24
Finished	May 23 04:34:18 PM PDT 24
Peak memory	563552 kb
Host	smart-f4557b86-cadc-43d4-8072-c67f3009fccc
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994810185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.2994810185
Directory	/workspace/59.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all.1730586103
Short name	T2791
Test name
Test status
Simulation time	1315373044 ps
CPU time	54.84 seconds
Started	May 23 04:34:17 PM PDT 24
Finished	May 23 04:35:13 PM PDT 24
Peak memory	571864 kb
Host	smart-23f34c46-a405-4727-9b4c-a940d54b1a47
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730586103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1730586103
Directory	/workspace/59.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.2595918687
Short name	T1566
Test name
Test status
Simulation time	409928678 ps
CPU time	36.5 seconds
Started	May 23 04:34:16 PM PDT 24
Finished	May 23 04:34:54 PM PDT 24
Peak memory	571916 kb
Host	smart-6d0cf252-b5c3-47a0-a028-c69449ccbbe3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595918687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.2595918687
Directory	/workspace/59.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2175592994
Short name	T1612
Test name
Test status
Simulation time	94852583 ps
CPU time	28.4 seconds
Started	May 23 04:34:19 PM PDT 24
Finished	May 23 04:34:48 PM PDT 24
Peak memory	571984 kb
Host	smart-89b9c8d2-9445-49f8-a6cc-1c2adbf42c0d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175592994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.2175592994
Directory	/workspace/59.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1008980581
Short name	T1936
Test name
Test status
Simulation time	4785689819 ps
CPU time	483.55 seconds
Started	May 23 04:34:19 PM PDT 24
Finished	May 23 04:42:25 PM PDT 24
Peak memory	573112 kb
Host	smart-969eb6bc-5857-4c8a-b51c-35b02f48a5c4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008980581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.1008980581
Directory	/workspace/59.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.624809673
Short name	T2526
Test name
Test status
Simulation time	1037848123 ps
CPU time	47 seconds
Started	May 23 04:34:16 PM PDT 24
Finished	May 23 04:35:05 PM PDT 24
Peak memory	571848 kb
Host	smart-f7fb3054-4d9f-486c-9706-72a3911e4601
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624809673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.624809673
Directory	/workspace/59.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/6.chip_csr_rw.3977617486
Short name	T2325
Test name
Test status
Simulation time	4630895392 ps
CPU time	511.68 seconds
Started	May 23 04:21:40 PM PDT 24
Finished	May 23 04:30:13 PM PDT 24
Peak memory	590448 kb
Host	smart-a2b7acd0-dfda-4a40-9968-069ea1ed704a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977617486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.3977617486
Directory	/workspace/6.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.216737372
Short name	T2547
Test name
Test status
Simulation time	13776496200 ps
CPU time	1638.01 seconds
Started	May 23 04:21:28 PM PDT 24
Finished	May 23 04:48:47 PM PDT 24
Peak memory	585828 kb
Host	smart-0826df81-b65e-4a63-9184-6340f80632d8
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216737372 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.chip_same_csr_outstanding.216737372
Directory	/workspace/6.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.chip_tl_errors.3279172114
Short name	T2299
Test name
Test status
Simulation time	3652230600 ps
CPU time	190.93 seconds
Started	May 23 04:21:10 PM PDT 24
Finished	May 23 04:24:22 PM PDT 24
Peak memory	602268 kb
Host	smart-4e59dac0-7d34-4c70-a1c2-9faeea77c2b5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279172114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.3279172114
Directory	/workspace/6.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_access_same_device.3191863991
Short name	T2049
Test name
Test status
Simulation time	503253461 ps
CPU time	27.67 seconds
Started	May 23 04:21:29 PM PDT 24
Finished	May 23 04:21:57 PM PDT 24
Peak memory	563604 kb
Host	smart-7f6abe1f-7317-4f00-a930-cfe586c770d3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191863991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 3191863991
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.4057671185
Short name	T1780
Test name
Test status
Simulation time	98793007658 ps
CPU time	1699.77 seconds
Started	May 23 04:21:26 PM PDT 24
Finished	May 23 04:49:47 PM PDT 24
Peak memory	572072 kb
Host	smart-c5f032de-99e4-48fa-966a-3edbbcf4e838
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057671185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.4057671185
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2825459880
Short name	T1417
Test name
Test status
Simulation time	67415670 ps
CPU time	9.65 seconds
Started	May 23 04:21:24 PM PDT 24
Finished	May 23 04:21:34 PM PDT 24
Peak memory	571824 kb
Host	smart-a1e094fe-4d08-4650-8f82-0faca338318e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825459880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .2825459880
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_error_random.609894475
Short name	T2667
Test name
Test status
Simulation time	620952876 ps
CPU time	57.16 seconds
Started	May 23 04:21:54 PM PDT 24
Finished	May 23 04:22:52 PM PDT 24
Peak memory	571776 kb
Host	smart-7ff3fd97-eb0e-44f6-9165-b4282e57fd70
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609894475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.609894475
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_random.1067543855
Short name	T1871
Test name
Test status
Simulation time	96115075 ps
CPU time	13.6 seconds
Started	May 23 04:21:11 PM PDT 24
Finished	May 23 04:21:25 PM PDT 24
Peak memory	571752 kb
Host	smart-f74b2b4d-e06c-42c7-8912-cf5db0ebb195
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067543855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.1067543855
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_random_large_delays.1188918666
Short name	T611
Test name
Test status
Simulation time	46575191877 ps
CPU time	529.47 seconds
Started	May 23 04:21:11 PM PDT 24
Finished	May 23 04:30:01 PM PDT 24
Peak memory	572040 kb
Host	smart-80b45269-ab6f-4905-aa93-a169e689d92d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188918666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1188918666
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.1886678000
Short name	T2432
Test name
Test status
Simulation time	41705662638 ps
CPU time	749.36 seconds
Started	May 23 04:21:25 PM PDT 24
Finished	May 23 04:33:55 PM PDT 24
Peak memory	572028 kb
Host	smart-710a6b18-3dae-439b-8eab-7531d496d457
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886678000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1886678000
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.1653262828
Short name	T475
Test name
Test status
Simulation time	539789814 ps
CPU time	55.73 seconds
Started	May 23 04:21:10 PM PDT 24
Finished	May 23 04:22:07 PM PDT 24
Peak memory	571832 kb
Host	smart-d2e1f6ab-40e3-4f5f-b32a-56a8fc361896
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653262828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.1653262828
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_same_source.3318413292
Short name	T2457
Test name
Test status
Simulation time	149844418 ps
CPU time	14.62 seconds
Started	May 23 04:21:28 PM PDT 24
Finished	May 23 04:21:44 PM PDT 24
Peak memory	571808 kb
Host	smart-696edc46-f8b4-4155-9396-d1342e9babf9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318413292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3318413292
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke.3565188686
Short name	T1848
Test name
Test status
Simulation time	43602598 ps
CPU time	7.07 seconds
Started	May 23 04:21:22 PM PDT 24
Finished	May 23 04:21:30 PM PDT 24
Peak memory	563540 kb
Host	smart-301a0da1-9b88-488b-b8b2-f94c5dd2946f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565188686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3565188686
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.4294130001
Short name	T1911
Test name
Test status
Simulation time	7421243976 ps
CPU time	88.15 seconds
Started	May 23 04:21:17 PM PDT 24
Finished	May 23 04:22:46 PM PDT 24
Peak memory	563704 kb
Host	smart-02334723-b72d-4d53-9433-665eb8ef245c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294130001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4294130001
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1731903093
Short name	T1317
Test name
Test status
Simulation time	5531064012 ps
CPU time	121.06 seconds
Started	May 23 04:21:49 PM PDT 24
Finished	May 23 04:23:51 PM PDT 24
Peak memory	563720 kb
Host	smart-b7295b71-0eb9-4c71-b2ce-a8037937bce9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731903093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1731903093
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2003057983
Short name	T1539
Test name
Test status
Simulation time	47370461 ps
CPU time	6.77 seconds
Started	May 23 04:21:14 PM PDT 24
Finished	May 23 04:21:22 PM PDT 24
Peak memory	563508 kb
Host	smart-f08010e4-9c7e-43a8-bf47-27ec589f2d11
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003057983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .2003057983
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all.3082702254
Short name	T2417
Test name
Test status
Simulation time	7070306306 ps
CPU time	306.37 seconds
Started	May 23 04:21:29 PM PDT 24
Finished	May 23 04:26:36 PM PDT 24
Peak memory	572556 kb
Host	smart-305ab886-5d24-4df1-b4c8-9e0a53930063
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082702254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3082702254
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.4150510838
Short name	T2412
Test name
Test status
Simulation time	7869126603 ps
CPU time	287.48 seconds
Started	May 23 04:21:26 PM PDT 24
Finished	May 23 04:26:14 PM PDT 24
Peak memory	572852 kb
Host	smart-a2f79528-99fb-4ccf-8408-e0387139a713
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150510838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.4150510838
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2559380446
Short name	T1820
Test name
Test status
Simulation time	873597642 ps
CPU time	339.1 seconds
Started	May 23 04:21:25 PM PDT 24
Finished	May 23 04:27:05 PM PDT 24
Peak memory	573864 kb
Host	smart-3ae7cb12-9833-4df2-acf3-62b6b7c3ad2e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559380446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.2559380446
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1876786929
Short name	T824
Test name
Test status
Simulation time	10136398396 ps
CPU time	577.94 seconds
Started	May 23 04:21:32 PM PDT 24
Finished	May 23 04:31:11 PM PDT 24
Peak memory	573132 kb
Host	smart-1207b600-5f7e-4117-a129-0bc0d3bef77b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876786929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.1876786929
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.2811213177
Short name	T2684
Test name
Test status
Simulation time	329586540 ps
CPU time	42.79 seconds
Started	May 23 04:21:32 PM PDT 24
Finished	May 23 04:22:16 PM PDT 24
Peak memory	571828 kb
Host	smart-3be4247a-5d1f-4945-b94b-a3cd0d5a084d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811213177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2811213177
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_access_same_device.778433243
Short name	T1614
Test name
Test status
Simulation time	291131283 ps
CPU time	24.15 seconds
Started	May 23 04:34:26 PM PDT 24
Finished	May 23 04:34:51 PM PDT 24
Peak memory	571836 kb
Host	smart-bf78dcf4-9a81-4177-b154-3eda6ffe9e02
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778433243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device. 778433243
Directory	/workspace/60.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.154071049
Short name	T2370
Test name
Test status
Simulation time	63006991095 ps
CPU time	1112.54 seconds
Started	May 23 04:34:18 PM PDT 24
Finished	May 23 04:52:52 PM PDT 24
Peak memory	572056 kb
Host	smart-c210de55-b1ad-4fa7-9ac6-8ecf3432157c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154071049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_d evice_slow_rsp.154071049
Directory	/workspace/60.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1099685777
Short name	T2252
Test name
Test status
Simulation time	109632007 ps
CPU time	14.48 seconds
Started	May 23 04:34:20 PM PDT 24
Finished	May 23 04:34:36 PM PDT 24
Peak memory	571816 kb
Host	smart-51d5dd3a-f42e-4253-b298-dfece222c7a0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099685777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.1099685777
Directory	/workspace/60.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_error_random.1781470946
Short name	T1705
Test name
Test status
Simulation time	867120272 ps
CPU time	33.07 seconds
Started	May 23 04:34:20 PM PDT 24
Finished	May 23 04:34:55 PM PDT 24
Peak memory	571776 kb
Host	smart-a81f15df-6577-470c-936d-a2a0c2bfe9fd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781470946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1781470946
Directory	/workspace/60.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_random.1653954610
Short name	T1544
Test name
Test status
Simulation time	1809051727 ps
CPU time	68.02 seconds
Started	May 23 04:34:17 PM PDT 24
Finished	May 23 04:35:27 PM PDT 24
Peak memory	571844 kb
Host	smart-e7b63390-0b84-4989-aa11-dd14f78c1700
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653954610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.1653954610
Directory	/workspace/60.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2415897816
Short name	T581
Test name
Test status
Simulation time	18096795250 ps
CPU time	216.63 seconds
Started	May 23 04:34:26 PM PDT 24
Finished	May 23 04:38:04 PM PDT 24
Peak memory	572008 kb
Host	smart-853d151b-3651-4de4-a0f7-ff4e215af5d5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415897816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2415897816
Directory	/workspace/60.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.267745404
Short name	T2594
Test name
Test status
Simulation time	32128194610 ps
CPU time	608.18 seconds
Started	May 23 04:34:14 PM PDT 24
Finished	May 23 04:44:24 PM PDT 24
Peak memory	572040 kb
Host	smart-131c18fb-e56a-478e-8177-e0089bf2dad5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267745404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.267745404
Directory	/workspace/60.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3924399515
Short name	T1803
Test name
Test status
Simulation time	506160713 ps
CPU time	45.41 seconds
Started	May 23 04:34:18 PM PDT 24
Finished	May 23 04:35:04 PM PDT 24
Peak memory	571788 kb
Host	smart-41509696-59cd-4a5f-9f20-ae9748ce4ed9
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924399515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.3924399515
Directory	/workspace/60.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_same_source.3370736882
Short name	T2771
Test name
Test status
Simulation time	489315147 ps
CPU time	34.39 seconds
Started	May 23 04:34:18 PM PDT 24
Finished	May 23 04:34:54 PM PDT 24
Peak memory	571800 kb
Host	smart-a123221d-d52c-4501-9cdb-6ed42af7f899
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370736882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.3370736882
Directory	/workspace/60.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke.3807073019
Short name	T1874
Test name
Test status
Simulation time	244887680 ps
CPU time	10.97 seconds
Started	May 23 04:34:26 PM PDT 24
Finished	May 23 04:34:39 PM PDT 24
Peak memory	563556 kb
Host	smart-a6ce5736-dc48-4aff-b66a-f6c3437789c2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807073019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.3807073019
Directory	/workspace/60.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.964969145
Short name	T1251
Test name
Test status
Simulation time	7360646309 ps
CPU time	76.67 seconds
Started	May 23 04:34:18 PM PDT 24
Finished	May 23 04:35:36 PM PDT 24
Peak memory	563712 kb
Host	smart-d9dc1721-8171-4c52-a89f-ab719bf66b5d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964969145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.964969145
Directory	/workspace/60.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3756912357
Short name	T661
Test name
Test status
Simulation time	4929266597 ps
CPU time	85.59 seconds
Started	May 23 04:34:16 PM PDT 24
Finished	May 23 04:35:43 PM PDT 24
Peak memory	563784 kb
Host	smart-4665e7fb-db1a-459b-87fd-aef06acf29a1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756912357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.3756912357
Directory	/workspace/60.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3694990224
Short name	T2694
Test name
Test status
Simulation time	41065767 ps
CPU time	6.33 seconds
Started	May 23 04:34:20 PM PDT 24
Finished	May 23 04:34:28 PM PDT 24
Peak memory	563444 kb
Host	smart-6b56c4b1-389c-48f7-b70e-43fb18acad54
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694990224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.3694990224
Directory	/workspace/60.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all.3558653575
Short name	T1489
Test name
Test status
Simulation time	268706808 ps
CPU time	28 seconds
Started	May 23 04:34:20 PM PDT 24
Finished	May 23 04:34:49 PM PDT 24
Peak memory	571848 kb
Host	smart-20eb0193-13d1-4e55-9cc5-3350a35a5220
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558653575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.3558653575
Directory	/workspace/60.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.375783187
Short name	T481
Test name
Test status
Simulation time	174694998 ps
CPU time	104.87 seconds
Started	May 23 04:34:17 PM PDT 24
Finished	May 23 04:36:03 PM PDT 24
Peak memory	572388 kb
Host	smart-bb736bd8-5f03-4a66-b9f8-1c4b1bbdd29e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375783187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_ with_rand_reset.375783187
Directory	/workspace/60.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1997156030
Short name	T2608
Test name
Test status
Simulation time	16966992526 ps
CPU time	1319.46 seconds
Started	May 23 04:34:16 PM PDT 24
Finished	May 23 04:56:17 PM PDT 24
Peak memory	581236 kb
Host	smart-fcfbe57a-5a91-4ed7-8121-bcc7e117117a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997156030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.1997156030
Directory	/workspace/60.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2679154848
Short name	T2237
Test name
Test status
Simulation time	912502345 ps
CPU time	43.41 seconds
Started	May 23 04:34:16 PM PDT 24
Finished	May 23 04:35:01 PM PDT 24
Peak memory	571848 kb
Host	smart-7969abe5-b038-4300-9c15-6f15eee21475
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679154848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2679154848
Directory	/workspace/60.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_access_same_device.2028628745
Short name	T2374
Test name
Test status
Simulation time	843968784 ps
CPU time	85.89 seconds
Started	May 23 04:34:31 PM PDT 24
Finished	May 23 04:35:58 PM PDT 24
Peak memory	571848 kb
Host	smart-09605d97-415c-49e8-8f4c-c7f77154e4da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028628745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .2028628745
Directory	/workspace/61.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2878234534
Short name	T1261
Test name
Test status
Simulation time	1287728512 ps
CPU time	59.5 seconds
Started	May 23 04:34:29 PM PDT 24
Finished	May 23 04:35:29 PM PDT 24
Peak memory	571836 kb
Host	smart-b533de0f-19bc-43f4-8297-fa7e2a864856
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878234534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.2878234534
Directory	/workspace/61.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_error_random.344875078
Short name	T2514
Test name
Test status
Simulation time	2418168597 ps
CPU time	87.52 seconds
Started	May 23 04:34:30 PM PDT 24
Finished	May 23 04:35:59 PM PDT 24
Peak memory	571908 kb
Host	smart-940cf9c3-fa26-43ed-830b-e6a18aecf5e4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344875078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.344875078
Directory	/workspace/61.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_random.3130263604
Short name	T2344
Test name
Test status
Simulation time	1267915922 ps
CPU time	43.7 seconds
Started	May 23 04:34:31 PM PDT 24
Finished	May 23 04:35:16 PM PDT 24
Peak memory	571848 kb
Host	smart-620c7c00-330b-4aa0-b83f-13a6b569ae5a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130263604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.3130263604
Directory	/workspace/61.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_random_large_delays.388277176
Short name	T2759
Test name
Test status
Simulation time	58982690404 ps
CPU time	655.71 seconds
Started	May 23 04:34:30 PM PDT 24
Finished	May 23 04:45:27 PM PDT 24
Peak memory	572060 kb
Host	smart-9d2ccbbc-145e-43a1-aba1-4fe38ff34122
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388277176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.388277176
Directory	/workspace/61.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.4188137904
Short name	T1951
Test name
Test status
Simulation time	55135519276 ps
CPU time	977.29 seconds
Started	May 23 04:34:32 PM PDT 24
Finished	May 23 04:50:51 PM PDT 24
Peak memory	572052 kb
Host	smart-a022e79c-305b-4b61-84dc-b20e225fe4d7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188137904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.4188137904
Directory	/workspace/61.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.4015181822
Short name	T1724
Test name
Test status
Simulation time	600789734 ps
CPU time	57.01 seconds
Started	May 23 04:34:29 PM PDT 24
Finished	May 23 04:35:28 PM PDT 24
Peak memory	571804 kb
Host	smart-e7c896f9-bdfc-4838-a662-b608c6b120b8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015181822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.4015181822
Directory	/workspace/61.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_same_source.520349095
Short name	T2431
Test name
Test status
Simulation time	288907660 ps
CPU time	10.7 seconds
Started	May 23 04:34:33 PM PDT 24
Finished	May 23 04:34:45 PM PDT 24
Peak memory	563548 kb
Host	smart-9b3b9af7-a474-4398-bf4f-c593af0a5d2c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520349095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.520349095
Directory	/workspace/61.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke.982191753
Short name	T1467
Test name
Test status
Simulation time	226949678 ps
CPU time	9.91 seconds
Started	May 23 04:34:32 PM PDT 24
Finished	May 23 04:34:44 PM PDT 24
Peak memory	563528 kb
Host	smart-b5a313a2-65ab-48d2-be7a-6527c7a3d7da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982191753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.982191753
Directory	/workspace/61.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.971980492
Short name	T1365
Test name
Test status
Simulation time	6805182378 ps
CPU time	72.07 seconds
Started	May 23 04:34:33 PM PDT 24
Finished	May 23 04:35:46 PM PDT 24
Peak memory	563764 kb
Host	smart-6bd9e605-e184-4f17-a33f-5f3e2efc5df0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971980492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.971980492
Directory	/workspace/61.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2177289168
Short name	T2532
Test name
Test status
Simulation time	4720576062 ps
CPU time	84.27 seconds
Started	May 23 04:34:30 PM PDT 24
Finished	May 23 04:35:55 PM PDT 24
Peak memory	563776 kb
Host	smart-9202f1e0-98ca-461d-9298-2759615a28e4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177289168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.2177289168
Directory	/workspace/61.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.32364641
Short name	T2083
Test name
Test status
Simulation time	47735846 ps
CPU time	6.84 seconds
Started	May 23 04:34:30 PM PDT 24
Finished	May 23 04:34:38 PM PDT 24
Peak memory	563500 kb
Host	smart-7d402b30-99fa-49a7-8f0b-56c1fd0ba2c6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32364641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays.32364641
Directory	/workspace/61.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all.2139313729
Short name	T2603
Test name
Test status
Simulation time	22925345265 ps
CPU time	949.6 seconds
Started	May 23 04:34:31 PM PDT 24
Finished	May 23 04:50:22 PM PDT 24
Peak memory	573076 kb
Host	smart-3f77b85f-1ec9-4a08-bc50-dab836d9a236
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139313729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.2139313729
Directory	/workspace/61.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2000847253
Short name	T1658
Test name
Test status
Simulation time	18790801646 ps
CPU time	685.25 seconds
Started	May 23 04:34:32 PM PDT 24
Finished	May 23 04:45:58 PM PDT 24
Peak memory	572044 kb
Host	smart-46620a27-813d-401b-8e48-55724bd24157
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000847253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.2000847253
Directory	/workspace/61.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1544663994
Short name	T2509
Test name
Test status
Simulation time	1196297253 ps
CPU time	137.24 seconds
Started	May 23 04:34:33 PM PDT 24
Finished	May 23 04:36:52 PM PDT 24
Peak memory	572836 kb
Host	smart-0101f0d0-00d7-4672-a8dc-e83a8f8ff717
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544663994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1544663994
Directory	/workspace/61.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.92068097
Short name	T2020
Test name
Test status
Simulation time	245612081 ps
CPU time	85.13 seconds
Started	May 23 04:34:32 PM PDT 24
Finished	May 23 04:35:58 PM PDT 24
Peak memory	572000 kb
Host	smart-36450a67-fa43-40d4-b180-fbb729416219
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92068097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_ with_reset_error.92068097
Directory	/workspace/61.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.3565631815
Short name	T1497
Test name
Test status
Simulation time	146823528 ps
CPU time	20.86 seconds
Started	May 23 04:34:29 PM PDT 24
Finished	May 23 04:34:51 PM PDT 24
Peak memory	571804 kb
Host	smart-bdb324f5-b971-46c6-8306-3c5c26aa3232
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565631815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.3565631815
Directory	/workspace/61.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_access_same_device.3175309386
Short name	T514
Test name
Test status
Simulation time	1581848643 ps
CPU time	60.14 seconds
Started	May 23 04:34:51 PM PDT 24
Finished	May 23 04:35:53 PM PDT 24
Peak memory	571824 kb
Host	smart-b30bc311-08ba-4832-b913-031f71977004
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175309386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .3175309386
Directory	/workspace/62.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.256738493
Short name	T2345
Test name
Test status
Simulation time	18010064142 ps
CPU time	299.1 seconds
Started	May 23 04:34:46 PM PDT 24
Finished	May 23 04:39:47 PM PDT 24
Peak memory	572032 kb
Host	smart-aa6a0874-eb91-4487-adce-708feac2d1ba
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256738493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d evice_slow_rsp.256738493
Directory	/workspace/62.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3002540224
Short name	T2741
Test name
Test status
Simulation time	534447757 ps
CPU time	26.24 seconds
Started	May 23 04:34:48 PM PDT 24
Finished	May 23 04:35:17 PM PDT 24
Peak memory	571812 kb
Host	smart-c2500501-c87e-4aec-8c54-71160497f15d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002540224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.3002540224
Directory	/workspace/62.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_error_random.2933500834
Short name	T2326
Test name
Test status
Simulation time	472320051 ps
CPU time	37.01 seconds
Started	May 23 04:34:49 PM PDT 24
Finished	May 23 04:35:29 PM PDT 24
Peak memory	571872 kb
Host	smart-5c9f7a80-75c0-470e-8cb5-27236c990366
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933500834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.2933500834
Directory	/workspace/62.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_random.3757121682
Short name	T1603
Test name
Test status
Simulation time	2002693369 ps
CPU time	80.54 seconds
Started	May 23 04:34:29 PM PDT 24
Finished	May 23 04:35:51 PM PDT 24
Peak memory	571840 kb
Host	smart-eb8f45f2-bcb7-4e95-97c2-a4a374cfb4fd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757121682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3757121682
Directory	/workspace/62.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_random_large_delays.3829712964
Short name	T1565
Test name
Test status
Simulation time	43316442220 ps
CPU time	466.82 seconds
Started	May 23 04:34:32 PM PDT 24
Finished	May 23 04:42:20 PM PDT 24
Peak memory	572032 kb
Host	smart-8d9d7290-afdf-4586-bee4-f51acb1e3dd8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829712964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.3829712964
Directory	/workspace/62.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.2242235642
Short name	T2042
Test name
Test status
Simulation time	25370157290 ps
CPU time	489.88 seconds
Started	May 23 04:34:33 PM PDT 24
Finished	May 23 04:42:44 PM PDT 24
Peak memory	572044 kb
Host	smart-07d38cda-a7cd-486e-a447-ceb3dc525ab4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242235642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.2242235642
Directory	/workspace/62.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.1548017051
Short name	T556
Test name
Test status
Simulation time	251637118 ps
CPU time	25.31 seconds
Started	May 23 04:34:34 PM PDT 24
Finished	May 23 04:35:01 PM PDT 24
Peak memory	571812 kb
Host	smart-3849b0a2-60df-4209-8c29-6027925b9647
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548017051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.1548017051
Directory	/workspace/62.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_same_source.4109863438
Short name	T1558
Test name
Test status
Simulation time	1689116182 ps
CPU time	51.69 seconds
Started	May 23 04:34:50 PM PDT 24
Finished	May 23 04:35:44 PM PDT 24
Peak memory	571792 kb
Host	smart-80111f7c-1f32-471c-a43e-d645d374eb7b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109863438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.4109863438
Directory	/workspace/62.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke.2878070659
Short name	T2419
Test name
Test status
Simulation time	206038186 ps
CPU time	9.95 seconds
Started	May 23 04:34:33 PM PDT 24
Finished	May 23 04:34:44 PM PDT 24
Peak memory	563548 kb
Host	smart-a841a253-0796-4d9d-b428-ec7113c08e28
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878070659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2878070659
Directory	/workspace/62.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.2520836047
Short name	T1732
Test name
Test status
Simulation time	8704966644 ps
CPU time	99.05 seconds
Started	May 23 04:34:31 PM PDT 24
Finished	May 23 04:36:12 PM PDT 24
Peak memory	563760 kb
Host	smart-0ed75980-ca76-4cab-b6d7-cf0146f56ae6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520836047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.2520836047
Directory	/workspace/62.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3709715233
Short name	T2269
Test name
Test status
Simulation time	4530852139 ps
CPU time	88.76 seconds
Started	May 23 04:34:29 PM PDT 24
Finished	May 23 04:35:59 PM PDT 24
Peak memory	563760 kb
Host	smart-9057149c-1894-4109-833f-245cf6f85ef1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709715233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3709715233
Directory	/workspace/62.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3845576295
Short name	T2561
Test name
Test status
Simulation time	44491036 ps
CPU time	6.55 seconds
Started	May 23 04:34:31 PM PDT 24
Finished	May 23 04:34:40 PM PDT 24
Peak memory	563568 kb
Host	smart-7c3441b3-0c30-411b-a599-7891633b5ae1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845576295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.3845576295
Directory	/workspace/62.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all.71774214
Short name	T2402
Test name
Test status
Simulation time	1912584694 ps
CPU time	140.81 seconds
Started	May 23 04:34:49 PM PDT 24
Finished	May 23 04:37:12 PM PDT 24
Peak memory	571844 kb
Host	smart-0dcdc895-e084-40a4-b882-b929cf6753bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71774214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.71774214
Directory	/workspace/62.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3342144817
Short name	T2244
Test name
Test status
Simulation time	7307294097 ps
CPU time	235.78 seconds
Started	May 23 04:34:47 PM PDT 24
Finished	May 23 04:38:45 PM PDT 24
Peak memory	571976 kb
Host	smart-98ea9190-0250-4a96-b1d3-4d4147d0674d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342144817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.3342144817
Directory	/workspace/62.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.794340565
Short name	T2140
Test name
Test status
Simulation time	4999712866 ps
CPU time	292.76 seconds
Started	May 23 04:34:50 PM PDT 24
Finished	May 23 04:39:44 PM PDT 24
Peak memory	573024 kb
Host	smart-eb2e5c6e-6a2a-4516-9d98-cc91d11d1f27
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794340565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_ with_rand_reset.794340565
Directory	/workspace/62.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1853115882
Short name	T2718
Test name
Test status
Simulation time	97619893 ps
CPU time	23.56 seconds
Started	May 23 04:34:53 PM PDT 24
Finished	May 23 04:35:18 PM PDT 24
Peak memory	563668 kb
Host	smart-e7872859-9b00-4e49-9bb8-2d2197900c7a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853115882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.1853115882
Directory	/workspace/62.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.2255291171
Short name	T2164
Test name
Test status
Simulation time	152037151 ps
CPU time	23.23 seconds
Started	May 23 04:34:48 PM PDT 24
Finished	May 23 04:35:13 PM PDT 24
Peak memory	571888 kb
Host	smart-c1c5d6ed-dae5-4e26-bb81-4207a3d5dc31
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255291171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.2255291171
Directory	/workspace/62.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_access_same_device.2686391153
Short name	T2639
Test name
Test status
Simulation time	195880851 ps
CPU time	16.07 seconds
Started	May 23 04:34:52 PM PDT 24
Finished	May 23 04:35:09 PM PDT 24
Peak memory	563532 kb
Host	smart-cf799c5f-2c61-4a1d-902c-2ff961f5ac8a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686391153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .2686391153
Directory	/workspace/63.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.3482169524
Short name	T1416
Test name
Test status
Simulation time	265014844 ps
CPU time	35.26 seconds
Started	May 23 04:35:05 PM PDT 24
Finished	May 23 04:35:42 PM PDT 24
Peak memory	571856 kb
Host	smart-e1ca28e3-46e9-4cb8-89ac-fb2aa88fdfbf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482169524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.3482169524
Directory	/workspace/63.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_error_random.3168085995
Short name	T1284
Test name
Test status
Simulation time	978746697 ps
CPU time	38.01 seconds
Started	May 23 04:34:47 PM PDT 24
Finished	May 23 04:35:26 PM PDT 24
Peak memory	571724 kb
Host	smart-e180040d-ef1a-44cf-9160-d099dff1d012
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168085995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.3168085995
Directory	/workspace/63.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_random.1807888117
Short name	T2211
Test name
Test status
Simulation time	1900847270 ps
CPU time	74.91 seconds
Started	May 23 04:34:49 PM PDT 24
Finished	May 23 04:36:06 PM PDT 24
Peak memory	571808 kb
Host	smart-ace2e046-4cf9-484e-ae61-82d9ae1eea45
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807888117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1807888117
Directory	/workspace/63.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3075867802
Short name	T1458
Test name
Test status
Simulation time	36936512301 ps
CPU time	405.65 seconds
Started	May 23 04:34:48 PM PDT 24
Finished	May 23 04:41:36 PM PDT 24
Peak memory	572020 kb
Host	smart-7511153e-b02e-4d5f-b735-290daeda1fc9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075867802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3075867802
Directory	/workspace/63.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3612015238
Short name	T2421
Test name
Test status
Simulation time	32781938324 ps
CPU time	633.77 seconds
Started	May 23 04:34:48 PM PDT 24
Finished	May 23 04:45:24 PM PDT 24
Peak memory	572044 kb
Host	smart-a1d21a1e-5882-4864-8d72-07dbf42643fc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612015238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3612015238
Directory	/workspace/63.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.797885405
Short name	T597
Test name
Test status
Simulation time	367901011 ps
CPU time	31.95 seconds
Started	May 23 04:34:52 PM PDT 24
Finished	May 23 04:35:25 PM PDT 24
Peak memory	571776 kb
Host	smart-12b2bdf4-f95d-47f3-b8fb-4b059030d52e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797885405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela ys.797885405
Directory	/workspace/63.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_same_source.1191218851
Short name	T2683
Test name
Test status
Simulation time	2268819216 ps
CPU time	76.54 seconds
Started	May 23 04:34:49 PM PDT 24
Finished	May 23 04:36:08 PM PDT 24
Peak memory	571964 kb
Host	smart-32602cad-3d74-4573-ac13-f9eb08cb9a70
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191218851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.1191218851
Directory	/workspace/63.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke.2291501109
Short name	T2296
Test name
Test status
Simulation time	184712515 ps
CPU time	8.17 seconds
Started	May 23 04:34:49 PM PDT 24
Finished	May 23 04:34:59 PM PDT 24
Peak memory	563528 kb
Host	smart-cf9b89a9-d1c2-49fc-8a2e-03533e056150
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291501109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2291501109
Directory	/workspace/63.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.2918581205
Short name	T2303
Test name
Test status
Simulation time	8323000819 ps
CPU time	93.03 seconds
Started	May 23 04:34:47 PM PDT 24
Finished	May 23 04:36:22 PM PDT 24
Peak memory	563776 kb
Host	smart-a401d6f3-9475-4691-8418-7ac59bed070d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918581205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.2918581205
Directory	/workspace/63.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1366887992
Short name	T1699
Test name
Test status
Simulation time	5710038856 ps
CPU time	96.36 seconds
Started	May 23 04:34:48 PM PDT 24
Finished	May 23 04:36:26 PM PDT 24
Peak memory	563788 kb
Host	smart-c2ac42fb-a7ad-4054-841e-fef23e29436c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366887992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1366887992
Directory	/workspace/63.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.4094366061
Short name	T2069
Test name
Test status
Simulation time	36914183 ps
CPU time	6.53 seconds
Started	May 23 04:34:52 PM PDT 24
Finished	May 23 04:35:01 PM PDT 24
Peak memory	563504 kb
Host	smart-ef8f9f29-b248-4707-b5aa-b2170290aea4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094366061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.4094366061
Directory	/workspace/63.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all.575745164
Short name	T537
Test name
Test status
Simulation time	3242210986 ps
CPU time	294.37 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 04:40:02 PM PDT 24
Peak memory	572008 kb
Host	smart-2e9b50a0-a317-4be6-ab04-780a0deb3f19
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575745164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.575745164
Directory	/workspace/63.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3708698122
Short name	T2058
Test name
Test status
Simulation time	15504219893 ps
CPU time	596.3 seconds
Started	May 23 04:35:10 PM PDT 24
Finished	May 23 04:45:08 PM PDT 24
Peak memory	573108 kb
Host	smart-058e848d-fd07-41bd-9c0d-b91a2592a404
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708698122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3708698122
Directory	/workspace/63.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.4216754812
Short name	T2029
Test name
Test status
Simulation time	72529028 ps
CPU time	49.9 seconds
Started	May 23 04:35:10 PM PDT 24
Finished	May 23 04:36:01 PM PDT 24
Peak memory	563784 kb
Host	smart-bd0cb73b-ddb4-4c04-89cc-d778d6499a3e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216754812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.4216754812
Directory	/workspace/63.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.4109516873
Short name	T2294
Test name
Test status
Simulation time	406953541 ps
CPU time	112.5 seconds
Started	May 23 04:35:09 PM PDT 24
Finished	May 23 04:37:03 PM PDT 24
Peak memory	573404 kb
Host	smart-c45980fa-b328-4602-b8e2-0f2955dec613
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109516873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.4109516873
Directory	/workspace/63.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.1342505252
Short name	T1292
Test name
Test status
Simulation time	385193078 ps
CPU time	22.65 seconds
Started	May 23 04:34:50 PM PDT 24
Finished	May 23 04:35:15 PM PDT 24
Peak memory	571816 kb
Host	smart-3c41b79b-fed8-49f6-93e2-ad8e098978e7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342505252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.1342505252
Directory	/workspace/63.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_access_same_device.2494451893
Short name	T1271
Test name
Test status
Simulation time	259399896 ps
CPU time	11.85 seconds
Started	May 23 04:35:08 PM PDT 24
Finished	May 23 04:35:21 PM PDT 24
Peak memory	563544 kb
Host	smart-82782a19-4eb7-4cc2-bc85-0ab4c777a7a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494451893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .2494451893
Directory	/workspace/64.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3774791253
Short name	T2657
Test name
Test status
Simulation time	91755799623 ps
CPU time	1566.97 seconds
Started	May 23 04:35:05 PM PDT 24
Finished	May 23 05:01:14 PM PDT 24
Peak memory	572040 kb
Host	smart-b13dce46-0006-4ea2-acf8-1baa5b2243fd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774791253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.3774791253
Directory	/workspace/64.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2813249157
Short name	T2307
Test name
Test status
Simulation time	308501093 ps
CPU time	36.32 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 04:35:44 PM PDT 24
Peak memory	571820 kb
Host	smart-ff7e3fde-2844-4dc3-aec1-a9205ade7ed6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813249157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.2813249157
Directory	/workspace/64.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_error_random.2955994555
Short name	T2636
Test name
Test status
Simulation time	315518868 ps
CPU time	28.54 seconds
Started	May 23 04:35:09 PM PDT 24
Finished	May 23 04:35:39 PM PDT 24
Peak memory	571776 kb
Host	smart-fe23422f-815b-46bc-9a03-41992e9ec9d1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955994555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.2955994555
Directory	/workspace/64.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_random.852420141
Short name	T1358
Test name
Test status
Simulation time	1519566120 ps
CPU time	55.55 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 04:36:04 PM PDT 24
Peak memory	571796 kb
Host	smart-db6007b8-cbb4-4fb7-8713-fb441f4fafa9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852420141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.852420141
Directory	/workspace/64.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1452300716
Short name	T2697
Test name
Test status
Simulation time	8277873723 ps
CPU time	93.73 seconds
Started	May 23 04:35:08 PM PDT 24
Finished	May 23 04:36:44 PM PDT 24
Peak memory	563812 kb
Host	smart-b9f72edf-2d37-43e3-ad03-2aaa82f0b78e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452300716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.1452300716
Directory	/workspace/64.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.968287708
Short name	T2120
Test name
Test status
Simulation time	23221461783 ps
CPU time	404.28 seconds
Started	May 23 04:35:16 PM PDT 24
Finished	May 23 04:42:02 PM PDT 24
Peak memory	572056 kb
Host	smart-08b2d24f-ff3a-42a5-8f1b-9fb8b4351e2c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968287708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.968287708
Directory	/workspace/64.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.1538146650
Short name	T608
Test name
Test status
Simulation time	119139134 ps
CPU time	14.6 seconds
Started	May 23 04:35:08 PM PDT 24
Finished	May 23 04:35:25 PM PDT 24
Peak memory	571788 kb
Host	smart-8029211a-5cc1-4a22-9b85-2f818976cc5f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538146650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.1538146650
Directory	/workspace/64.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_same_source.2750332417
Short name	T2631
Test name
Test status
Simulation time	440454732 ps
CPU time	37.13 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 04:35:45 PM PDT 24
Peak memory	571764 kb
Host	smart-89721b71-d235-4391-a6c0-c5ea72b3c382
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750332417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2750332417
Directory	/workspace/64.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke.3112613583
Short name	T2115
Test name
Test status
Simulation time	39420695 ps
CPU time	6.08 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 04:35:14 PM PDT 24
Peak memory	563516 kb
Host	smart-c2a44064-253a-4584-9f63-e9d986f2ffa2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112613583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.3112613583
Directory	/workspace/64.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.1139236972
Short name	T2262
Test name
Test status
Simulation time	8835638473 ps
CPU time	92.45 seconds
Started	May 23 04:35:08 PM PDT 24
Finished	May 23 04:36:42 PM PDT 24
Peak memory	563756 kb
Host	smart-53df79d0-2614-43d3-9695-c8a9c9dc4683
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139236972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.1139236972
Directory	/workspace/64.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2554451017
Short name	T1276
Test name
Test status
Simulation time	5225960266 ps
CPU time	93.64 seconds
Started	May 23 04:35:07 PM PDT 24
Finished	May 23 04:36:43 PM PDT 24
Peak memory	563748 kb
Host	smart-2ffb04dc-cb32-49da-bae6-ffa4cf421d73
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554451017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.2554451017
Directory	/workspace/64.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.283139130
Short name	T2708
Test name
Test status
Simulation time	49189105 ps
CPU time	6.98 seconds
Started	May 23 04:35:07 PM PDT 24
Finished	May 23 04:35:16 PM PDT 24
Peak memory	563492 kb
Host	smart-f57395a3-bb21-4e7a-9a39-28a5a597c3ca
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283139130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays .283139130
Directory	/workspace/64.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all.483494027
Short name	T2276
Test name
Test status
Simulation time	5742178667 ps
CPU time	237.4 seconds
Started	May 23 04:35:10 PM PDT 24
Finished	May 23 04:39:09 PM PDT 24
Peak memory	572172 kb
Host	smart-048119b0-3789-48af-af1c-1371afcf3548
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483494027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.483494027
Directory	/workspace/64.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.566254377
Short name	T2558
Test name
Test status
Simulation time	2233594792 ps
CPU time	98.75 seconds
Started	May 23 04:35:12 PM PDT 24
Finished	May 23 04:36:52 PM PDT 24
Peak memory	571972 kb
Host	smart-05541b24-3e69-4e32-99c0-2c3af043f293
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566254377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.566254377
Directory	/workspace/64.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.3061981367
Short name	T527
Test name
Test status
Simulation time	697758702 ps
CPU time	327.94 seconds
Started	May 23 04:35:05 PM PDT 24
Finished	May 23 04:40:35 PM PDT 24
Peak memory	572924 kb
Host	smart-35da7cb8-2701-4f5b-b381-c6af4bdc8d5d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061981367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.3061981367
Directory	/workspace/64.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3787498687
Short name	T2169
Test name
Test status
Simulation time	15886775743 ps
CPU time	601.45 seconds
Started	May 23 04:35:10 PM PDT 24
Finished	May 23 04:45:13 PM PDT 24
Peak memory	573104 kb
Host	smart-6c45d032-5f80-45a3-8de9-8f76188bb633
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787498687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.3787498687
Directory	/workspace/64.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.3777922156
Short name	T1345
Test name
Test status
Simulation time	1401702413 ps
CPU time	59.71 seconds
Started	May 23 04:35:11 PM PDT 24
Finished	May 23 04:36:12 PM PDT 24
Peak memory	571864 kb
Host	smart-c537f4ee-af3a-43b2-bf3e-f4c2c24bc9e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777922156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3777922156
Directory	/workspace/64.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_access_same_device.3091064796
Short name	T2241
Test name
Test status
Simulation time	1336066304 ps
CPU time	53.06 seconds
Started	May 23 04:35:10 PM PDT 24
Finished	May 23 04:36:05 PM PDT 24
Peak memory	571852 kb
Host	smart-38b55a64-727c-4c38-a4e0-5b59b6386c30
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091064796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .3091064796
Directory	/workspace/65.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3154713997
Short name	T1900
Test name
Test status
Simulation time	127567578619 ps
CPU time	2257.66 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 05:12:46 PM PDT 24
Peak memory	572044 kb
Host	smart-d2f38bd1-9c10-409f-bd58-6d89d0c4c72d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154713997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.3154713997
Directory	/workspace/65.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1079850015
Short name	T1795
Test name
Test status
Simulation time	277878253 ps
CPU time	15.11 seconds
Started	May 23 04:35:22 PM PDT 24
Finished	May 23 04:35:39 PM PDT 24
Peak memory	571844 kb
Host	smart-f631aece-42b0-4c2e-bcbb-19a25925f63a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079850015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.1079850015
Directory	/workspace/65.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_error_random.2336683045
Short name	T2285
Test name
Test status
Simulation time	2597929071 ps
CPU time	96.59 seconds
Started	May 23 04:35:21 PM PDT 24
Finished	May 23 04:36:59 PM PDT 24
Peak memory	571828 kb
Host	smart-0a0d3b0a-2d51-4522-90ab-d7dea009d154
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336683045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.2336683045
Directory	/workspace/65.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_random.2060570902
Short name	T2119
Test name
Test status
Simulation time	2094832503 ps
CPU time	81.22 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 04:36:29 PM PDT 24
Peak memory	571804 kb
Host	smart-80c48d3f-b851-4d15-8b53-5863f63e4bfd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060570902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2060570902
Directory	/workspace/65.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_random_large_delays.1339506214
Short name	T2191
Test name
Test status
Simulation time	94170606624 ps
CPU time	1052.92 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 04:52:41 PM PDT 24
Peak memory	572012 kb
Host	smart-6bb6f356-8754-4b20-9987-738cd1ab0044
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339506214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.1339506214
Directory	/workspace/65.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.546197599
Short name	T2297
Test name
Test status
Simulation time	46168056153 ps
CPU time	795.82 seconds
Started	May 23 04:35:08 PM PDT 24
Finished	May 23 04:48:25 PM PDT 24
Peak memory	572068 kb
Host	smart-600845d0-0d30-4944-ae95-39d0328d8e1f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546197599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.546197599
Directory	/workspace/65.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.2649056021
Short name	T2653
Test name
Test status
Simulation time	156011927 ps
CPU time	16.83 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 04:35:24 PM PDT 24
Peak memory	571748 kb
Host	smart-acba4839-dc55-4680-beac-eafe652bbe9e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649056021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.2649056021
Directory	/workspace/65.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_same_source.1262296307
Short name	T2189
Test name
Test status
Simulation time	424886311 ps
CPU time	35.26 seconds
Started	May 23 04:35:08 PM PDT 24
Finished	May 23 04:35:45 PM PDT 24
Peak memory	571764 kb
Host	smart-f1b53cff-96c2-4f0d-870d-bf1381f6b797
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262296307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.1262296307
Directory	/workspace/65.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke.355739322
Short name	T2624
Test name
Test status
Simulation time	50481366 ps
CPU time	6.81 seconds
Started	May 23 04:35:10 PM PDT 24
Finished	May 23 04:35:19 PM PDT 24
Peak memory	563568 kb
Host	smart-8985c3d6-6b2d-4331-a80c-c45b8c52075b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355739322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.355739322
Directory	/workspace/65.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2614781016
Short name	T2313
Test name
Test status
Simulation time	9146027481 ps
CPU time	105.49 seconds
Started	May 23 04:35:05 PM PDT 24
Finished	May 23 04:36:52 PM PDT 24
Peak memory	563752 kb
Host	smart-46e93029-9c67-4f90-9790-89abf4ae340f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614781016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2614781016
Directory	/workspace/65.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2313124856
Short name	T1296
Test name
Test status
Simulation time	4388263639 ps
CPU time	76.48 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 04:36:24 PM PDT 24
Peak memory	563808 kb
Host	smart-df42cede-d440-4ac4-9064-17d41e8c708d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313124856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.2313124856
Directory	/workspace/65.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2558331595
Short name	T2756
Test name
Test status
Simulation time	42930233 ps
CPU time	6.54 seconds
Started	May 23 04:35:06 PM PDT 24
Finished	May 23 04:35:14 PM PDT 24
Peak memory	563536 kb
Host	smart-12cfd9b0-0ea6-47d8-a896-98bb703c1dfe
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558331595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.2558331595
Directory	/workspace/65.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all.606935714
Short name	T447
Test name
Test status
Simulation time	6667462330 ps
CPU time	263.8 seconds
Started	May 23 04:35:21 PM PDT 24
Finished	May 23 04:39:46 PM PDT 24
Peak memory	572768 kb
Host	smart-111870ff-c8ad-463c-ac30-b499fd6f444f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606935714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.606935714
Directory	/workspace/65.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1486345448
Short name	T2772
Test name
Test status
Simulation time	10920912221 ps
CPU time	431.65 seconds
Started	May 23 04:35:26 PM PDT 24
Finished	May 23 04:42:39 PM PDT 24
Peak memory	572292 kb
Host	smart-dfc31bca-2a51-48e3-bcb9-1c34235d9461
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486345448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.1486345448
Directory	/workspace/65.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.248850962
Short name	T832
Test name
Test status
Simulation time	291190373 ps
CPU time	172.45 seconds
Started	May 23 04:35:20 PM PDT 24
Finished	May 23 04:38:14 PM PDT 24
Peak memory	572532 kb
Host	smart-0fca7d46-bafa-4833-8d39-a1f720bb0155
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248850962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_ with_rand_reset.248850962
Directory	/workspace/65.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.4101889150
Short name	T841
Test name
Test status
Simulation time	4437294316 ps
CPU time	540.72 seconds
Started	May 23 04:35:22 PM PDT 24
Finished	May 23 04:44:25 PM PDT 24
Peak memory	573140 kb
Host	smart-d973db1f-11ae-4975-9624-402d6b1fa604
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101889150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.4101889150
Directory	/workspace/65.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1163194768
Short name	T521
Test name
Test status
Simulation time	1141893667 ps
CPU time	57.32 seconds
Started	May 23 04:35:20 PM PDT 24
Finished	May 23 04:36:19 PM PDT 24
Peak memory	571844 kb
Host	smart-c1869492-e705-4ae4-a0b0-ebd45211ee3a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163194768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1163194768
Directory	/workspace/65.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_access_same_device.4143235214
Short name	T784
Test name
Test status
Simulation time	1331907538 ps
CPU time	63.2 seconds
Started	May 23 04:35:20 PM PDT 24
Finished	May 23 04:36:24 PM PDT 24
Peak memory	571836 kb
Host	smart-63fc3cda-6ffe-4eaa-a213-3e68df518e99
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143235214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .4143235214
Directory	/workspace/66.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3489572695
Short name	T1372
Test name
Test status
Simulation time	9432614773 ps
CPU time	170.44 seconds
Started	May 23 04:35:26 PM PDT 24
Finished	May 23 04:38:18 PM PDT 24
Peak memory	563832 kb
Host	smart-190acfa4-1a9e-4cc8-aec2-055552cef7e1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489572695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.3489572695
Directory	/workspace/66.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1102464965
Short name	T2556
Test name
Test status
Simulation time	778930053 ps
CPU time	35.19 seconds
Started	May 23 04:35:23 PM PDT 24
Finished	May 23 04:36:00 PM PDT 24
Peak memory	571808 kb
Host	smart-9cadb804-663b-41b3-a8a4-25b0cbfee908
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102464965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.1102464965
Directory	/workspace/66.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_error_random.675417555
Short name	T1879
Test name
Test status
Simulation time	592030196 ps
CPU time	52.49 seconds
Started	May 23 04:35:19 PM PDT 24
Finished	May 23 04:36:13 PM PDT 24
Peak memory	571808 kb
Host	smart-19043d80-4223-41f1-97f8-6aa17977b4ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675417555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.675417555
Directory	/workspace/66.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_random.2214109876
Short name	T2783
Test name
Test status
Simulation time	381313613 ps
CPU time	16.36 seconds
Started	May 23 04:35:23 PM PDT 24
Finished	May 23 04:35:41 PM PDT 24
Peak memory	571788 kb
Host	smart-56c9c164-0797-4e1c-b01e-50403cb03c09
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214109876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2214109876
Directory	/workspace/66.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2118957133
Short name	T1713
Test name
Test status
Simulation time	20922418144 ps
CPU time	229.09 seconds
Started	May 23 04:35:20 PM PDT 24
Finished	May 23 04:39:11 PM PDT 24
Peak memory	572056 kb
Host	smart-5be69cfb-2875-4f3b-b333-f71663a6e138
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118957133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2118957133
Directory	/workspace/66.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1786141777
Short name	T1742
Test name
Test status
Simulation time	22518724662 ps
CPU time	385.59 seconds
Started	May 23 04:35:23 PM PDT 24
Finished	May 23 04:41:51 PM PDT 24
Peak memory	572032 kb
Host	smart-70aa7832-3be3-4957-82c4-d9aaeb00c9f6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786141777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.1786141777
Directory	/workspace/66.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.487720629
Short name	T1675
Test name
Test status
Simulation time	445298788 ps
CPU time	39.8 seconds
Started	May 23 04:35:22 PM PDT 24
Finished	May 23 04:36:04 PM PDT 24
Peak memory	571736 kb
Host	smart-0183120e-587e-4c8c-b0c5-83f24ac58c22
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487720629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_dela ys.487720629
Directory	/workspace/66.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_same_source.3871888139
Short name	T1860
Test name
Test status
Simulation time	601067437 ps
CPU time	21.87 seconds
Started	May 23 04:35:20 PM PDT 24
Finished	May 23 04:35:43 PM PDT 24
Peak memory	571808 kb
Host	smart-d21cf2f2-814d-4f95-8177-ae42de8171cf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871888139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.3871888139
Directory	/workspace/66.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke.3830017084
Short name	T1375
Test name
Test status
Simulation time	43049490 ps
CPU time	6.8 seconds
Started	May 23 04:35:21 PM PDT 24
Finished	May 23 04:35:30 PM PDT 24
Peak memory	563500 kb
Host	smart-9394343f-5d68-4eed-8585-a77dd2527721
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830017084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.3830017084
Directory	/workspace/66.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.1093410307
Short name	T561
Test name
Test status
Simulation time	9969236287 ps
CPU time	106.27 seconds
Started	May 23 04:35:25 PM PDT 24
Finished	May 23 04:37:14 PM PDT 24
Peak memory	563796 kb
Host	smart-f43bb203-16c6-4de1-b2fa-45077b367bd0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093410307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.1093410307
Directory	/workspace/66.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.4139924749
Short name	T2582
Test name
Test status
Simulation time	4502712980 ps
CPU time	83.19 seconds
Started	May 23 04:35:25 PM PDT 24
Finished	May 23 04:36:50 PM PDT 24
Peak memory	563792 kb
Host	smart-2d11ca62-1f24-4a37-98fe-f2174f9205b1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139924749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.4139924749
Directory	/workspace/66.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.4028173563
Short name	T2403
Test name
Test status
Simulation time	38799785 ps
CPU time	5.99 seconds
Started	May 23 04:35:25 PM PDT 24
Finished	May 23 04:35:33 PM PDT 24
Peak memory	563576 kb
Host	smart-fd49e893-2977-484b-ae9c-c23e735fd745
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028173563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.4028173563
Directory	/workspace/66.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all.1649372023
Short name	T2047
Test name
Test status
Simulation time	565888636 ps
CPU time	51.41 seconds
Started	May 23 04:35:23 PM PDT 24
Finished	May 23 04:36:16 PM PDT 24
Peak memory	571888 kb
Host	smart-2dcbef64-9cea-477e-98df-17979b9e261d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649372023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1649372023
Directory	/workspace/66.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3548647248
Short name	T493
Test name
Test status
Simulation time	1541686303 ps
CPU time	133.85 seconds
Started	May 23 04:35:23 PM PDT 24
Finished	May 23 04:37:39 PM PDT 24
Peak memory	572192 kb
Host	smart-b3728ca1-3555-4837-befc-e62c4673eac7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548647248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.3548647248
Directory	/workspace/66.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1228443235
Short name	T1423
Test name
Test status
Simulation time	422888451 ps
CPU time	129.37 seconds
Started	May 23 04:35:25 PM PDT 24
Finished	May 23 04:37:36 PM PDT 24
Peak memory	572232 kb
Host	smart-6e65a9ac-29a2-444d-8efe-b646a4d060c4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228443235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.1228443235
Directory	/workspace/66.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1276309574
Short name	T1575
Test name
Test status
Simulation time	2625277240 ps
CPU time	329.69 seconds
Started	May 23 04:35:20 PM PDT 24
Finished	May 23 04:40:51 PM PDT 24
Peak memory	573068 kb
Host	smart-403388a1-1860-4c88-9a27-46323de390bc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276309574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.1276309574
Directory	/workspace/66.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.2036788877
Short name	T1361
Test name
Test status
Simulation time	249853056 ps
CPU time	14.12 seconds
Started	May 23 04:35:22 PM PDT 24
Finished	May 23 04:35:38 PM PDT 24
Peak memory	571756 kb
Host	smart-a72b58b8-17d9-4bc3-b3d3-4996e6321476
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036788877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.2036788877
Directory	/workspace/66.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_access_same_device.3049138368
Short name	T1945
Test name
Test status
Simulation time	175910912 ps
CPU time	14.23 seconds
Started	May 23 04:35:35 PM PDT 24
Finished	May 23 04:35:50 PM PDT 24
Peak memory	563552 kb
Host	smart-a68fc492-6764-44de-aa07-b265c108edfc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049138368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .3049138368
Directory	/workspace/67.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.4006832131
Short name	T1260
Test name
Test status
Simulation time	540079687 ps
CPU time	25.75 seconds
Started	May 23 04:35:35 PM PDT 24
Finished	May 23 04:36:02 PM PDT 24
Peak memory	571776 kb
Host	smart-ae62cd06-5251-4c9c-9992-3bdd996343d9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006832131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.4006832131
Directory	/workspace/67.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_error_random.2570108458
Short name	T1270
Test name
Test status
Simulation time	792861408 ps
CPU time	29.49 seconds
Started	May 23 04:35:35 PM PDT 24
Finished	May 23 04:36:06 PM PDT 24
Peak memory	571828 kb
Host	smart-b8d339f5-c1d8-43ad-9ffc-47c7d6ac956d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570108458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2570108458
Directory	/workspace/67.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_random.2452774917
Short name	T1259
Test name
Test status
Simulation time	505107699 ps
CPU time	22.82 seconds
Started	May 23 04:35:26 PM PDT 24
Finished	May 23 04:35:51 PM PDT 24
Peak memory	571832 kb
Host	smart-fe6360bb-7d83-46c2-b7d3-3469dfdc051b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452774917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.2452774917
Directory	/workspace/67.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_random_large_delays.2231849736
Short name	T2540
Test name
Test status
Simulation time	44775557985 ps
CPU time	505.03 seconds
Started	May 23 04:35:21 PM PDT 24
Finished	May 23 04:43:48 PM PDT 24
Peak memory	572088 kb
Host	smart-33110fd6-7b69-45e7-b2c3-ec6ec9f2e423
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231849736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.2231849736
Directory	/workspace/67.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.1540718090
Short name	T1884
Test name
Test status
Simulation time	59051403139 ps
CPU time	1024.6 seconds
Started	May 23 04:35:37 PM PDT 24
Finished	May 23 04:52:43 PM PDT 24
Peak memory	572020 kb
Host	smart-4e9169c3-a075-445a-8a14-259305fcba15
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540718090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.1540718090
Directory	/workspace/67.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3422568177
Short name	T439
Test name
Test status
Simulation time	290787602 ps
CPU time	26.37 seconds
Started	May 23 04:35:20 PM PDT 24
Finished	May 23 04:35:47 PM PDT 24
Peak memory	571748 kb
Host	smart-961b30eb-cdaf-4ddd-a6c1-5c65c4282271
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422568177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.3422568177
Directory	/workspace/67.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_same_source.660889824
Short name	T1903
Test name
Test status
Simulation time	555371246 ps
CPU time	45.81 seconds
Started	May 23 04:35:32 PM PDT 24
Finished	May 23 04:36:19 PM PDT 24
Peak memory	571804 kb
Host	smart-7c033350-f186-4771-ac89-dcff978dd84b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660889824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.660889824
Directory	/workspace/67.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke.3465600330
Short name	T2329
Test name
Test status
Simulation time	180375661 ps
CPU time	8.87 seconds
Started	May 23 04:35:20 PM PDT 24
Finished	May 23 04:35:31 PM PDT 24
Peak memory	563556 kb
Host	smart-27cfb38a-cadb-4dc6-be74-4a288de8fb52
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465600330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.3465600330
Directory	/workspace/67.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.3632475797
Short name	T1617
Test name
Test status
Simulation time	7389474677 ps
CPU time	79.19 seconds
Started	May 23 04:35:18 PM PDT 24
Finished	May 23 04:36:39 PM PDT 24
Peak memory	563784 kb
Host	smart-451ff485-b72b-4352-b785-08f3b7173b56
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632475797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.3632475797
Directory	/workspace/67.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2255705429
Short name	T1300
Test name
Test status
Simulation time	6447856425 ps
CPU time	120.99 seconds
Started	May 23 04:35:23 PM PDT 24
Finished	May 23 04:37:26 PM PDT 24
Peak memory	563768 kb
Host	smart-32182e8d-2e48-4591-8491-c5d6b7498c05
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255705429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2255705429
Directory	/workspace/67.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.4081706158
Short name	T1511
Test name
Test status
Simulation time	53264702 ps
CPU time	6.86 seconds
Started	May 23 04:35:22 PM PDT 24
Finished	May 23 04:35:31 PM PDT 24
Peak memory	563460 kb
Host	smart-03467244-e497-4548-a70a-6752c76f1f74
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081706158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.4081706158
Directory	/workspace/67.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all.3691784779
Short name	T2133
Test name
Test status
Simulation time	6135164653 ps
CPU time	272.76 seconds
Started	May 23 04:35:36 PM PDT 24
Finished	May 23 04:40:10 PM PDT 24
Peak memory	571952 kb
Host	smart-76e9be81-5e25-4a8b-bdf4-b6976437598f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691784779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.3691784779
Directory	/workspace/67.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.1463392400
Short name	T2335
Test name
Test status
Simulation time	8327962841 ps
CPU time	333.74 seconds
Started	May 23 04:35:33 PM PDT 24
Finished	May 23 04:41:08 PM PDT 24
Peak memory	571992 kb
Host	smart-ca875576-c082-428f-af42-b69c16e45e69
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463392400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.1463392400
Directory	/workspace/67.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1672577282
Short name	T1977
Test name
Test status
Simulation time	9775637192 ps
CPU time	594.79 seconds
Started	May 23 04:35:34 PM PDT 24
Finished	May 23 04:45:30 PM PDT 24
Peak memory	573048 kb
Host	smart-03be89e5-7d9e-4cd9-b34d-d597048efd93
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672577282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.1672577282
Directory	/workspace/67.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1299305389
Short name	T819
Test name
Test status
Simulation time	5589192945 ps
CPU time	428.28 seconds
Started	May 23 04:35:36 PM PDT 24
Finished	May 23 04:42:46 PM PDT 24
Peak memory	573100 kb
Host	smart-a893900d-f8ac-4aa9-9346-94540ff44457
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299305389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.1299305389
Directory	/workspace/67.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3365683568
Short name	T1717
Test name
Test status
Simulation time	157963486 ps
CPU time	22.04 seconds
Started	May 23 04:35:36 PM PDT 24
Finished	May 23 04:35:59 PM PDT 24
Peak memory	571880 kb
Host	smart-1d43401b-e072-4273-8590-fe84e0917406
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365683568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3365683568
Directory	/workspace/67.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_access_same_device.284378013
Short name	T1649
Test name
Test status
Simulation time	1166581760 ps
CPU time	59.27 seconds
Started	May 23 04:35:33 PM PDT 24
Finished	May 23 04:36:33 PM PDT 24
Peak memory	571808 kb
Host	smart-f8bd3db2-3266-4936-850e-57d14c1482bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284378013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device. 284378013
Directory	/workspace/68.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.4141754607
Short name	T401
Test name
Test status
Simulation time	32586634766 ps
CPU time	595.87 seconds
Started	May 23 04:35:33 PM PDT 24
Finished	May 23 04:45:30 PM PDT 24
Peak memory	572068 kb
Host	smart-a5e949b7-a422-4060-a24f-3b497c8dd906
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141754607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.4141754607
Directory	/workspace/68.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.1384709467
Short name	T2609
Test name
Test status
Simulation time	318122389 ps
CPU time	36.72 seconds
Started	May 23 04:35:33 PM PDT 24
Finished	May 23 04:36:11 PM PDT 24
Peak memory	571772 kb
Host	smart-ca0dda30-86d0-4851-b18b-13d3eac41483
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384709467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.1384709467
Directory	/workspace/68.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_error_random.1413001821
Short name	T1325
Test name
Test status
Simulation time	1361249866 ps
CPU time	52.35 seconds
Started	May 23 04:35:35 PM PDT 24
Finished	May 23 04:36:28 PM PDT 24
Peak memory	571808 kb
Host	smart-013b0fdb-7426-44e0-9dfe-9651671f8093
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413001821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.1413001821
Directory	/workspace/68.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_random.3330947156
Short name	T1513
Test name
Test status
Simulation time	605137057 ps
CPU time	54.9 seconds
Started	May 23 04:35:36 PM PDT 24
Finished	May 23 04:36:32 PM PDT 24
Peak memory	571840 kb
Host	smart-28e66148-97b1-4070-9729-86f5c4f75305
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330947156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.3330947156
Directory	/workspace/68.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_random_large_delays.900468751
Short name	T1740
Test name
Test status
Simulation time	21102661414 ps
CPU time	249.65 seconds
Started	May 23 04:35:32 PM PDT 24
Finished	May 23 04:39:43 PM PDT 24
Peak memory	572060 kb
Host	smart-39c79d43-f812-4f13-a03c-853a995cdbc8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900468751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.900468751
Directory	/workspace/68.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.4184012859
Short name	T2028
Test name
Test status
Simulation time	10877915211 ps
CPU time	193.94 seconds
Started	May 23 04:35:35 PM PDT 24
Finished	May 23 04:38:50 PM PDT 24
Peak memory	572008 kb
Host	smart-c35000fb-f0a2-4ad2-8eda-c9d0df56357a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184012859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.4184012859
Directory	/workspace/68.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3529700280
Short name	T2260
Test name
Test status
Simulation time	235164546 ps
CPU time	24.99 seconds
Started	May 23 04:35:36 PM PDT 24
Finished	May 23 04:36:02 PM PDT 24
Peak memory	571800 kb
Host	smart-d6fcf0e4-f731-407c-8b78-b369bc5c5cc3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529700280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.3529700280
Directory	/workspace/68.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_same_source.1225008816
Short name	T2598
Test name
Test status
Simulation time	235702225 ps
CPU time	21.29 seconds
Started	May 23 04:35:32 PM PDT 24
Finished	May 23 04:35:54 PM PDT 24
Peak memory	571800 kb
Host	smart-c4ba1ec5-7f52-4c92-b9c7-9680c780c97b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225008816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1225008816
Directory	/workspace/68.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke.2221346121
Short name	T1495
Test name
Test status
Simulation time	231098395 ps
CPU time	9.89 seconds
Started	May 23 04:35:35 PM PDT 24
Finished	May 23 04:35:46 PM PDT 24
Peak memory	563536 kb
Host	smart-a1d5f946-2729-468b-a99b-6d89eeabf6af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221346121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2221346121
Directory	/workspace/68.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.1533772279
Short name	T598
Test name
Test status
Simulation time	7336825651 ps
CPU time	82.96 seconds
Started	May 23 04:35:34 PM PDT 24
Finished	May 23 04:36:58 PM PDT 24
Peak memory	563704 kb
Host	smart-142bfd69-ae20-4e04-b9f6-5df81510df1c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533772279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.1533772279
Directory	/workspace/68.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1769474903
Short name	T2744
Test name
Test status
Simulation time	4895323043 ps
CPU time	87.41 seconds
Started	May 23 04:35:35 PM PDT 24
Finished	May 23 04:37:04 PM PDT 24
Peak memory	563700 kb
Host	smart-71997fbd-b855-40ba-8d42-eda632c95e77
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769474903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.1769474903
Directory	/workspace/68.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2769169982
Short name	T1441
Test name
Test status
Simulation time	41932754 ps
CPU time	6.42 seconds
Started	May 23 04:35:36 PM PDT 24
Finished	May 23 04:35:44 PM PDT 24
Peak memory	563572 kb
Host	smart-d76f5da9-d0bd-4406-a261-1f19f9eae912
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769169982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.2769169982
Directory	/workspace/68.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all.3215849319
Short name	T1657
Test name
Test status
Simulation time	132214405 ps
CPU time	14.83 seconds
Started	May 23 04:35:35 PM PDT 24
Finished	May 23 04:35:51 PM PDT 24
Peak memory	571864 kb
Host	smart-0b967284-ee3f-498b-882d-d629359d5953
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215849319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.3215849319
Directory	/workspace/68.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.707823624
Short name	T1404
Test name
Test status
Simulation time	370000917 ps
CPU time	155 seconds
Started	May 23 04:35:33 PM PDT 24
Finished	May 23 04:38:09 PM PDT 24
Peak memory	572824 kb
Host	smart-a7db4cbd-32f7-41c8-9bec-5ae91924302e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707823624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_ with_rand_reset.707823624
Directory	/workspace/68.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3786041565
Short name	T834
Test name
Test status
Simulation time	352690310 ps
CPU time	123.53 seconds
Started	May 23 04:35:30 PM PDT 24
Finished	May 23 04:37:34 PM PDT 24
Peak memory	573948 kb
Host	smart-758b552b-2686-4593-9771-4c58cbe865af
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786041565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3786041565
Directory	/workspace/68.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.2702670890
Short name	T1587
Test name
Test status
Simulation time	24620874 ps
CPU time	5.72 seconds
Started	May 23 04:35:32 PM PDT 24
Finished	May 23 04:35:39 PM PDT 24
Peak memory	563576 kb
Host	smart-cae82803-498a-4a08-ac58-45f716da11b2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702670890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.2702670890
Directory	/workspace/68.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_access_same_device.391633237
Short name	T2560
Test name
Test status
Simulation time	1088792003 ps
CPU time	54.07 seconds
Started	May 23 04:35:50 PM PDT 24
Finished	May 23 04:36:45 PM PDT 24
Peak memory	571860 kb
Host	smart-88f7f7f8-9a0a-4201-9762-cfeb755bb6ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391633237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device. 391633237
Directory	/workspace/69.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3111729070
Short name	T811
Test name
Test status
Simulation time	58996612185 ps
CPU time	1032.1 seconds
Started	May 23 04:35:47 PM PDT 24
Finished	May 23 04:53:00 PM PDT 24
Peak memory	572028 kb
Host	smart-bfb53d99-3991-444c-bd80-c451bf782d35
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111729070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.3111729070
Directory	/workspace/69.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3235496169
Short name	T1250
Test name
Test status
Simulation time	1054435360 ps
CPU time	47.86 seconds
Started	May 23 04:35:48 PM PDT 24
Finished	May 23 04:36:37 PM PDT 24
Peak memory	571868 kb
Host	smart-d3010375-91a3-43df-b13b-b806f8755b66
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235496169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.3235496169
Directory	/workspace/69.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_error_random.2216102929
Short name	T2489
Test name
Test status
Simulation time	418548366 ps
CPU time	21.67 seconds
Started	May 23 04:35:46 PM PDT 24
Finished	May 23 04:36:09 PM PDT 24
Peak memory	571764 kb
Host	smart-475908fc-3b59-4565-b8f3-d2d531543857
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216102929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.2216102929
Directory	/workspace/69.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_random.2202901294
Short name	T1736
Test name
Test status
Simulation time	1324150413 ps
CPU time	57.11 seconds
Started	May 23 04:35:48 PM PDT 24
Finished	May 23 04:36:46 PM PDT 24
Peak memory	571824 kb
Host	smart-329fef7e-dd25-4b94-9370-0eb623a21298
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202901294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2202901294
Directory	/workspace/69.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2781618788
Short name	T1751
Test name
Test status
Simulation time	83360709139 ps
CPU time	844.63 seconds
Started	May 23 04:35:50 PM PDT 24
Finished	May 23 04:49:55 PM PDT 24
Peak memory	572064 kb
Host	smart-1cb59fab-44e2-4b86-81de-9aa0af620114
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781618788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2781618788
Directory	/workspace/69.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.585001814
Short name	T2193
Test name
Test status
Simulation time	13251042965 ps
CPU time	248.22 seconds
Started	May 23 04:35:47 PM PDT 24
Finished	May 23 04:39:56 PM PDT 24
Peak memory	572060 kb
Host	smart-31fcca38-5191-461c-b721-43c7fd3f95a6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585001814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.585001814
Directory	/workspace/69.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.664301651
Short name	T2739
Test name
Test status
Simulation time	148589894 ps
CPU time	16.78 seconds
Started	May 23 04:35:48 PM PDT 24
Finished	May 23 04:36:06 PM PDT 24
Peak memory	571748 kb
Host	smart-7f815de0-d2e2-4f2a-b24e-b84b8fe76cab
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664301651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_dela ys.664301651
Directory	/workspace/69.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_same_source.3568747483
Short name	T1356
Test name
Test status
Simulation time	955955839 ps
CPU time	32.01 seconds
Started	May 23 04:35:45 PM PDT 24
Finished	May 23 04:36:18 PM PDT 24
Peak memory	571788 kb
Host	smart-dd051f9d-a4f6-494f-a6b6-f695f9985131
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568747483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.3568747483
Directory	/workspace/69.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke.906617323
Short name	T538
Test name
Test status
Simulation time	49631723 ps
CPU time	7.29 seconds
Started	May 23 04:35:35 PM PDT 24
Finished	May 23 04:35:44 PM PDT 24
Peak memory	563584 kb
Host	smart-2f55b663-8c0c-4707-b8f9-7a54b26c9556
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906617323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.906617323
Directory	/workspace/69.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.597150269
Short name	T2358
Test name
Test status
Simulation time	8663494975 ps
CPU time	95.79 seconds
Started	May 23 04:35:35 PM PDT 24
Finished	May 23 04:37:12 PM PDT 24
Peak memory	563724 kb
Host	smart-69d2d681-461c-46b2-9848-5f50303e590c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597150269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.597150269
Directory	/workspace/69.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.206244467
Short name	T2539
Test name
Test status
Simulation time	4225917486 ps
CPU time	71.22 seconds
Started	May 23 04:35:47 PM PDT 24
Finished	May 23 04:37:00 PM PDT 24
Peak memory	563728 kb
Host	smart-59699eb7-03f2-4e19-93c6-8da9596adf39
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206244467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.206244467
Directory	/workspace/69.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.676695810
Short name	T2630
Test name
Test status
Simulation time	50083148 ps
CPU time	6.41 seconds
Started	May 23 04:35:36 PM PDT 24
Finished	May 23 04:35:44 PM PDT 24
Peak memory	563564 kb
Host	smart-2b3f0d95-0ea0-465a-80c0-2ff4aa3cb358
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676695810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays .676695810
Directory	/workspace/69.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all.1142564832
Short name	T1393
Test name
Test status
Simulation time	12172294156 ps
CPU time	531.42 seconds
Started	May 23 04:35:50 PM PDT 24
Finished	May 23 04:44:43 PM PDT 24
Peak memory	573080 kb
Host	smart-25485fee-646e-4b02-bbf6-7f753a6ac571
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142564832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.1142564832
Directory	/workspace/69.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.214175458
Short name	T1642
Test name
Test status
Simulation time	2310284037 ps
CPU time	96.3 seconds
Started	May 23 04:35:48 PM PDT 24
Finished	May 23 04:37:25 PM PDT 24
Peak memory	572056 kb
Host	smart-8b1c3576-d33c-494e-8a4d-bddfbfbf8156
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214175458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.214175458
Directory	/workspace/69.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1729068800
Short name	T2466
Test name
Test status
Simulation time	8080097081 ps
CPU time	478 seconds
Started	May 23 04:35:50 PM PDT 24
Finished	May 23 04:43:49 PM PDT 24
Peak memory	574068 kb
Host	smart-debe64a9-c094-4869-9271-1c4e6628f8f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729068800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.1729068800
Directory	/workspace/69.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3619678979
Short name	T2612
Test name
Test status
Simulation time	3827475311 ps
CPU time	260.05 seconds
Started	May 23 04:35:49 PM PDT 24
Finished	May 23 04:40:10 PM PDT 24
Peak memory	574164 kb
Host	smart-6925f58f-2706-493d-8161-78d804f16772
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619678979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.3619678979
Directory	/workspace/69.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2630652143
Short name	T1701
Test name
Test status
Simulation time	783325585 ps
CPU time	36.14 seconds
Started	May 23 04:35:49 PM PDT 24
Finished	May 23 04:36:26 PM PDT 24
Peak memory	571880 kb
Host	smart-20cdbf95-2f6d-466a-bc00-00a5e1992ba6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630652143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2630652143
Directory	/workspace/69.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/7.chip_csr_rw.731410586
Short name	T382
Test name
Test status
Simulation time	4593950834 ps
CPU time	341.44 seconds
Started	May 23 04:22:26 PM PDT 24
Finished	May 23 04:28:08 PM PDT 24
Peak memory	590944 kb
Host	smart-3a92ab49-d3aa-477a-aa22-f8bb5f53f4d0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731410586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.731410586
Directory	/workspace/7.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.783824190
Short name	T486
Test name
Test status
Simulation time	13954925754 ps
CPU time	2052.66 seconds
Started	May 23 04:21:44 PM PDT 24
Finished	May 23 04:55:58 PM PDT 24
Peak memory	585924 kb
Host	smart-dc7411fa-c1aa-465e-a6f1-8ef1c5de585b
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783824190 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.chip_same_csr_outstanding.783824190
Directory	/workspace/7.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.chip_tl_errors.2896131015
Short name	T2786
Test name
Test status
Simulation time	3463759825 ps
CPU time	213.8 seconds
Started	May 23 04:21:45 PM PDT 24
Finished	May 23 04:25:20 PM PDT 24
Peak memory	602268 kb
Host	smart-7a8391af-28b6-43d3-8387-7575186275f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896131015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.2896131015
Directory	/workspace/7.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_access_same_device.2765756728
Short name	T1309
Test name
Test status
Simulation time	97514777 ps
CPU time	9.54 seconds
Started	May 23 04:21:57 PM PDT 24
Finished	May 23 04:22:07 PM PDT 24
Peak memory	563556 kb
Host	smart-da12c837-55a6-4bc5-b84d-7f421409053f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765756728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 2765756728
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2588219068
Short name	T1506
Test name
Test status
Simulation time	44901115184 ps
CPU time	810.24 seconds
Started	May 23 04:21:59 PM PDT 24
Finished	May 23 04:35:30 PM PDT 24
Peak memory	572028 kb
Host	smart-176c59f0-12ff-436f-ad31-3242b536cc66
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588219068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.2588219068
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.995081554
Short name	T2333
Test name
Test status
Simulation time	533736454 ps
CPU time	27.77 seconds
Started	May 23 04:22:04 PM PDT 24
Finished	May 23 04:22:33 PM PDT 24
Peak memory	571816 kb
Host	smart-337199a0-62e0-4da5-a113-6126a5b3bef4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995081554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr. 995081554
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_error_random.2743535889
Short name	T1380
Test name
Test status
Simulation time	351198339 ps
CPU time	36.23 seconds
Started	May 23 04:22:07 PM PDT 24
Finished	May 23 04:22:44 PM PDT 24
Peak memory	571720 kb
Host	smart-c275e989-2300-4a0d-a838-889960e87924
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743535889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2743535889
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_random.3259939907
Short name	T1991
Test name
Test status
Simulation time	162821329 ps
CPU time	18.82 seconds
Started	May 23 04:21:57 PM PDT 24
Finished	May 23 04:22:16 PM PDT 24
Peak memory	571796 kb
Host	smart-64338ae0-a2e3-49fc-8637-bf7ef45c455c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259939907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3259939907
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_random_large_delays.553581565
Short name	T2098
Test name
Test status
Simulation time	8345751662 ps
CPU time	96.22 seconds
Started	May 23 04:21:58 PM PDT 24
Finished	May 23 04:23:35 PM PDT 24
Peak memory	563852 kb
Host	smart-4ce15eec-6e26-4e97-8b7d-533b21a9ebec
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553581565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.553581565
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.211065831
Short name	T1475
Test name
Test status
Simulation time	38173813974 ps
CPU time	640.08 seconds
Started	May 23 04:22:00 PM PDT 24
Finished	May 23 04:32:40 PM PDT 24
Peak memory	572048 kb
Host	smart-ab896f9f-c7aa-4912-8212-2c799dd9a130
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211065831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.211065831
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.2575707884
Short name	T2446
Test name
Test status
Simulation time	460142311 ps
CPU time	42.85 seconds
Started	May 23 04:21:59 PM PDT 24
Finished	May 23 04:22:42 PM PDT 24
Peak memory	571800 kb
Host	smart-d97b8e7b-bf1d-4d35-8948-9ee28c97d2fe
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575707884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.2575707884
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_same_source.3795584470
Short name	T2688
Test name
Test status
Simulation time	1286201198 ps
CPU time	43.37 seconds
Started	May 23 04:21:53 PM PDT 24
Finished	May 23 04:22:38 PM PDT 24
Peak memory	571836 kb
Host	smart-f5f6f02c-79af-4667-ba32-6a38fc703d0c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795584470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3795584470
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke.1104989598
Short name	T1678
Test name
Test status
Simulation time	43014889 ps
CPU time	7 seconds
Started	May 23 04:21:46 PM PDT 24
Finished	May 23 04:21:54 PM PDT 24
Peak memory	563556 kb
Host	smart-24f4859f-760f-47a8-84a9-abb4c4420870
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104989598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1104989598
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.702464655
Short name	T1282
Test name
Test status
Simulation time	8936166312 ps
CPU time	103.18 seconds
Started	May 23 04:21:38 PM PDT 24
Finished	May 23 04:23:22 PM PDT 24
Peak memory	563816 kb
Host	smart-849cf843-cba6-43f4-b713-f3c122695270
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702464655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.702464655
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.4259259228
Short name	T2445
Test name
Test status
Simulation time	6691270248 ps
CPU time	122.06 seconds
Started	May 23 04:21:47 PM PDT 24
Finished	May 23 04:23:50 PM PDT 24
Peak memory	563772 kb
Host	smart-c7e4b340-698f-4f56-a2bc-db9cc17312b9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259259228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4259259228
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.45172186
Short name	T1314
Test name
Test status
Simulation time	39652500 ps
CPU time	6.5 seconds
Started	May 23 04:21:41 PM PDT 24
Finished	May 23 04:21:48 PM PDT 24
Peak memory	563516 kb
Host	smart-b079debb-02cf-4675-93dd-fece29b4d5f0
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45172186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.45172186
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all.1162900266
Short name	T1645
Test name
Test status
Simulation time	6965033862 ps
CPU time	317.96 seconds
Started	May 23 04:22:08 PM PDT 24
Finished	May 23 04:27:26 PM PDT 24
Peak memory	572772 kb
Host	smart-debf3e59-5d9d-4ebb-b071-97c9c884bf1a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162900266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1162900266
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2782192088
Short name	T1522
Test name
Test status
Simulation time	4930295037 ps
CPU time	204.86 seconds
Started	May 23 04:22:08 PM PDT 24
Finished	May 23 04:25:34 PM PDT 24
Peak memory	572040 kb
Host	smart-1d61b2b9-434c-4ecd-8823-6c7b1a9fec31
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782192088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2782192088
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.95372369
Short name	T2592
Test name
Test status
Simulation time	2430242562 ps
CPU time	450.99 seconds
Started	May 23 04:22:08 PM PDT 24
Finished	May 23 04:29:40 PM PDT 24
Peak memory	573044 kb
Host	smart-3847fbf0-29fc-489e-bcb3-fbfca74babe7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95372369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_wi th_rand_reset.95372369
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.938998173
Short name	T2644
Test name
Test status
Simulation time	67406832 ps
CPU time	13.13 seconds
Started	May 23 04:22:08 PM PDT 24
Finished	May 23 04:22:22 PM PDT 24
Peak memory	563672 kb
Host	smart-236f9265-0931-4320-91e9-ce733cb614b6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938998173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_reset_error.938998173
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.3441086596
Short name	T602
Test name
Test status
Simulation time	186966690 ps
CPU time	25.78 seconds
Started	May 23 04:22:07 PM PDT 24
Finished	May 23 04:22:34 PM PDT 24
Peak memory	571796 kb
Host	smart-c20e9f90-95b0-4157-a8c0-80276268e3ce
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441086596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3441086596
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_access_same_device.3444293383
Short name	T2614
Test name
Test status
Simulation time	2717064214 ps
CPU time	118.46 seconds
Started	May 23 04:35:49 PM PDT 24
Finished	May 23 04:37:49 PM PDT 24
Peak memory	571920 kb
Host	smart-d55991b7-9b87-42a8-bc82-b852437acd1c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444293383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .3444293383
Directory	/workspace/70.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2681740623
Short name	T808
Test name
Test status
Simulation time	114369308411 ps
CPU time	2026.58 seconds
Started	May 23 04:35:48 PM PDT 24
Finished	May 23 05:09:36 PM PDT 24
Peak memory	572076 kb
Host	smart-d394fc50-5183-4cef-8e5e-a04487fd4d6e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681740623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2681740623
Directory	/workspace/70.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.623017823
Short name	T2503
Test name
Test status
Simulation time	290847068 ps
CPU time	15.98 seconds
Started	May 23 04:35:48 PM PDT 24
Finished	May 23 04:36:05 PM PDT 24
Peak memory	571784 kb
Host	smart-4a1484dc-4c18-4c20-ba18-76887bcc440f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623017823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr .623017823
Directory	/workspace/70.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_error_random.2528364555
Short name	T1482
Test name
Test status
Simulation time	1793134632 ps
CPU time	57.23 seconds
Started	May 23 04:35:50 PM PDT 24
Finished	May 23 04:36:48 PM PDT 24
Peak memory	571836 kb
Host	smart-bc7467db-ca69-4d58-a74f-986a22a43f5f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528364555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2528364555
Directory	/workspace/70.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_random.2695115298
Short name	T2336
Test name
Test status
Simulation time	886499007 ps
CPU time	32.83 seconds
Started	May 23 04:35:50 PM PDT 24
Finished	May 23 04:36:24 PM PDT 24
Peak memory	571764 kb
Host	smart-3e492937-bb7f-414b-ba32-7bcedd4a7175
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695115298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2695115298
Directory	/workspace/70.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1000963466
Short name	T1818
Test name
Test status
Simulation time	100509232881 ps
CPU time	1156.34 seconds
Started	May 23 04:35:47 PM PDT 24
Finished	May 23 04:55:04 PM PDT 24
Peak memory	572052 kb
Host	smart-7f7a051e-624d-4291-8927-128fb1cddef5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000963466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1000963466
Directory	/workspace/70.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2952138042
Short name	T403
Test name
Test status
Simulation time	16303794246 ps
CPU time	303.61 seconds
Started	May 23 04:35:46 PM PDT 24
Finished	May 23 04:40:51 PM PDT 24
Peak memory	572056 kb
Host	smart-44391d1e-e012-4ff2-82b9-792947bdbbba
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952138042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2952138042
Directory	/workspace/70.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.1903753032
Short name	T574
Test name
Test status
Simulation time	606829086 ps
CPU time	53.25 seconds
Started	May 23 04:35:48 PM PDT 24
Finished	May 23 04:36:42 PM PDT 24
Peak memory	571736 kb
Host	smart-e64d4ef8-5d03-48a7-8872-10fa9abdbfa9
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903753032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.1903753032
Directory	/workspace/70.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_same_source.785761880
Short name	T1757
Test name
Test status
Simulation time	444358282 ps
CPU time	34.76 seconds
Started	May 23 04:35:51 PM PDT 24
Finished	May 23 04:36:26 PM PDT 24
Peak memory	571780 kb
Host	smart-782023b3-097a-4e67-8973-849d817839bd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785761880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.785761880
Directory	/workspace/70.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke.2326845307
Short name	T2224
Test name
Test status
Simulation time	151071588 ps
CPU time	8.26 seconds
Started	May 23 04:35:47 PM PDT 24
Finished	May 23 04:35:56 PM PDT 24
Peak memory	563556 kb
Host	smart-bfd4edf6-ce61-4d61-b19e-820053f20f06
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326845307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.2326845307
Directory	/workspace/70.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.229063313
Short name	T2126
Test name
Test status
Simulation time	6681716520 ps
CPU time	73.01 seconds
Started	May 23 04:35:49 PM PDT 24
Finished	May 23 04:37:03 PM PDT 24
Peak memory	563768 kb
Host	smart-3c718b8b-ce8e-44d2-8530-36483b1a0b13
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229063313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.229063313
Directory	/workspace/70.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2862863166
Short name	T2568
Test name
Test status
Simulation time	3169345799 ps
CPU time	52.75 seconds
Started	May 23 04:35:46 PM PDT 24
Finished	May 23 04:36:40 PM PDT 24
Peak memory	563760 kb
Host	smart-f7b43633-0fee-4b29-8e3c-d981f08a7eb8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862863166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.2862863166
Directory	/workspace/70.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.2971473145
Short name	T2436
Test name
Test status
Simulation time	50562185 ps
CPU time	6.13 seconds
Started	May 23 04:35:46 PM PDT 24
Finished	May 23 04:35:53 PM PDT 24
Peak memory	563548 kb
Host	smart-32bb6ce0-04a6-433c-bd8e-c1573ba60ffb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971473145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.2971473145
Directory	/workspace/70.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all.2835087901
Short name	T1716
Test name
Test status
Simulation time	2407232628 ps
CPU time	93.91 seconds
Started	May 23 04:35:47 PM PDT 24
Finished	May 23 04:37:21 PM PDT 24
Peak memory	572008 kb
Host	smart-56015bb1-6549-4b1a-bd49-a11599163a2e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835087901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2835087901
Directory	/workspace/70.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.3125731421
Short name	T1997
Test name
Test status
Simulation time	1978475073 ps
CPU time	81.46 seconds
Started	May 23 04:36:01 PM PDT 24
Finished	May 23 04:37:24 PM PDT 24
Peak memory	571912 kb
Host	smart-e3c55f5a-5d05-4646-b1cb-e387b3d77b55
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125731421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.3125731421
Directory	/workspace/70.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2918079892
Short name	T2352
Test name
Test status
Simulation time	11558869561 ps
CPU time	530.66 seconds
Started	May 23 04:36:00 PM PDT 24
Finished	May 23 04:44:53 PM PDT 24
Peak memory	572672 kb
Host	smart-2deb8fea-cfa9-4f58-a0b4-0cada40f43e3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918079892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.2918079892
Directory	/workspace/70.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.527598543
Short name	T838
Test name
Test status
Simulation time	8637428254 ps
CPU time	558.47 seconds
Started	May 23 04:36:01 PM PDT 24
Finished	May 23 04:45:22 PM PDT 24
Peak memory	574180 kb
Host	smart-3a864304-67df-4590-965f-aae8925ebcdd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527598543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_reset_error.527598543
Directory	/workspace/70.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2152929271
Short name	T2742
Test name
Test status
Simulation time	205423238 ps
CPU time	11.92 seconds
Started	May 23 04:35:50 PM PDT 24
Finished	May 23 04:36:03 PM PDT 24
Peak memory	563616 kb
Host	smart-c40e6988-b1ce-47c8-9726-09552854a759
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152929271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2152929271
Directory	/workspace/70.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_access_same_device.1860869510
Short name	T2173
Test name
Test status
Simulation time	794384529 ps
CPU time	70.55 seconds
Started	May 23 04:36:00 PM PDT 24
Finished	May 23 04:37:13 PM PDT 24
Peak memory	571860 kb
Host	smart-93615974-ff73-4c0c-befb-f32f6d9f3b96
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860869510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .1860869510
Directory	/workspace/71.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1080096207
Short name	T2118
Test name
Test status
Simulation time	75276065486 ps
CPU time	1360.26 seconds
Started	May 23 04:36:00 PM PDT 24
Finished	May 23 04:58:43 PM PDT 24
Peak memory	572012 kb
Host	smart-0712a4da-6079-492c-bb0d-6831301d10f6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080096207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.1080096207
Directory	/workspace/71.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.630695362
Short name	T2729
Test name
Test status
Simulation time	85166834 ps
CPU time	11.06 seconds
Started	May 23 04:36:03 PM PDT 24
Finished	May 23 04:36:15 PM PDT 24
Peak memory	571776 kb
Host	smart-8b302234-7057-473b-a970-c5c16600aaf4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630695362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr .630695362
Directory	/workspace/71.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_error_random.1565597981
Short name	T1277
Test name
Test status
Simulation time	186088327 ps
CPU time	18.24 seconds
Started	May 23 04:36:01 PM PDT 24
Finished	May 23 04:36:21 PM PDT 24
Peak memory	571760 kb
Host	smart-bc50be8f-c736-4341-b0f5-79b66472fac9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565597981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.1565597981
Directory	/workspace/71.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_random.1799550579
Short name	T2305
Test name
Test status
Simulation time	1034593981 ps
CPU time	37.39 seconds
Started	May 23 04:36:03 PM PDT 24
Finished	May 23 04:36:41 PM PDT 24
Peak memory	571828 kb
Host	smart-50c7d6ea-a26a-4cb1-a840-ef832d402c60
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799550579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1799550579
Directory	/workspace/71.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_random_large_delays.610141735
Short name	T2168
Test name
Test status
Simulation time	32436833070 ps
CPU time	367.46 seconds
Started	May 23 04:36:02 PM PDT 24
Finished	May 23 04:42:11 PM PDT 24
Peak memory	572004 kb
Host	smart-44202716-d58e-4ba8-b6c4-6a7d2fe25fcf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610141735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.610141735
Directory	/workspace/71.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2131888556
Short name	T2036
Test name
Test status
Simulation time	24231416614 ps
CPU time	418.85 seconds
Started	May 23 04:36:01 PM PDT 24
Finished	May 23 04:43:02 PM PDT 24
Peak memory	572004 kb
Host	smart-cc6db1b0-7fca-4943-bab6-621719ce01e4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131888556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2131888556
Directory	/workspace/71.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1696289407
Short name	T557
Test name
Test status
Simulation time	416590533 ps
CPU time	31.16 seconds
Started	May 23 04:35:59 PM PDT 24
Finished	May 23 04:36:31 PM PDT 24
Peak memory	571776 kb
Host	smart-7675eda0-337a-44f2-9cfb-61a730d13fed
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696289407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.1696289407
Directory	/workspace/71.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_same_source.4081824603
Short name	T2471
Test name
Test status
Simulation time	1982185804 ps
CPU time	66.28 seconds
Started	May 23 04:36:02 PM PDT 24
Finished	May 23 04:37:10 PM PDT 24
Peak memory	571864 kb
Host	smart-b13fd606-a19b-4ae5-96b0-935eafc7076e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081824603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.4081824603
Directory	/workspace/71.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke.325160821
Short name	T2626
Test name
Test status
Simulation time	206332453 ps
CPU time	9.51 seconds
Started	May 23 04:36:00 PM PDT 24
Finished	May 23 04:36:11 PM PDT 24
Peak memory	563596 kb
Host	smart-bbfdc0a9-4322-4c3f-9628-3cb1cf293e7e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325160821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.325160821
Directory	/workspace/71.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.80984485
Short name	T1256
Test name
Test status
Simulation time	10462326471 ps
CPU time	109.12 seconds
Started	May 23 04:36:02 PM PDT 24
Finished	May 23 04:37:52 PM PDT 24
Peak memory	563776 kb
Host	smart-27539db7-f7fd-4a48-b6a4-3dd097d76b96
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80984485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.80984485
Directory	/workspace/71.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.4146473330
Short name	T2475
Test name
Test status
Simulation time	4287576332 ps
CPU time	76.69 seconds
Started	May 23 04:36:01 PM PDT 24
Finished	May 23 04:37:20 PM PDT 24
Peak memory	563732 kb
Host	smart-09f33ba7-174a-4c76-ac80-d72a570b7415
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146473330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.4146473330
Directory	/workspace/71.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.670251069
Short name	T2095
Test name
Test status
Simulation time	48056101 ps
CPU time	6.87 seconds
Started	May 23 04:36:04 PM PDT 24
Finished	May 23 04:36:12 PM PDT 24
Peak memory	563568 kb
Host	smart-049228a4-3e6f-4fcb-ab81-a22edf989919
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670251069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays .670251069
Directory	/workspace/71.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all.1200581108
Short name	T2586
Test name
Test status
Simulation time	2512593728 ps
CPU time	108.31 seconds
Started	May 23 04:36:02 PM PDT 24
Finished	May 23 04:37:52 PM PDT 24
Peak memory	571972 kb
Host	smart-81054036-7c59-4d29-b32e-35b7c17f7fec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200581108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.1200581108
Directory	/workspace/71.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.1807487519
Short name	T1514
Test name
Test status
Simulation time	7333974630 ps
CPU time	282.33 seconds
Started	May 23 04:36:00 PM PDT 24
Finished	May 23 04:40:45 PM PDT 24
Peak memory	571968 kb
Host	smart-7208b65f-e5e9-46bf-9f72-4328527a1cef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807487519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.1807487519
Directory	/workspace/71.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3888514944
Short name	T1656
Test name
Test status
Simulation time	305169453 ps
CPU time	113.61 seconds
Started	May 23 04:36:03 PM PDT 24
Finished	May 23 04:37:58 PM PDT 24
Peak memory	572344 kb
Host	smart-7cb1b6fc-3c2c-4ba9-9cb3-9a8303de613d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888514944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.3888514944
Directory	/workspace/71.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3048983044
Short name	T2501
Test name
Test status
Simulation time	884200889 ps
CPU time	233.72 seconds
Started	May 23 04:36:01 PM PDT 24
Finished	May 23 04:39:57 PM PDT 24
Peak memory	572948 kb
Host	smart-61d01c07-0edf-4374-b8af-b27b5496b4cd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048983044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.3048983044
Directory	/workspace/71.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.4224727081
Short name	T2677
Test name
Test status
Simulation time	1009803695 ps
CPU time	43.2 seconds
Started	May 23 04:36:01 PM PDT 24
Finished	May 23 04:36:46 PM PDT 24
Peak memory	571844 kb
Host	smart-772ea62c-13e2-41c2-8d7e-8ea7aaf1d354
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224727081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.4224727081
Directory	/workspace/71.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_access_same_device.2340040613
Short name	T1941
Test name
Test status
Simulation time	260230561 ps
CPU time	26.62 seconds
Started	May 23 04:36:18 PM PDT 24
Finished	May 23 04:36:45 PM PDT 24
Peak memory	571788 kb
Host	smart-6dad2a21-af57-47f1-b9ff-b056594d13e2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340040613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .2340040613
Directory	/workspace/72.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.4032639070
Short name	T445
Test name
Test status
Simulation time	72726390582 ps
CPU time	1233.39 seconds
Started	May 23 04:36:15 PM PDT 24
Finished	May 23 04:56:50 PM PDT 24
Peak memory	572080 kb
Host	smart-4036c5fa-1a23-4e03-981d-60ab4dbd28ab
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032639070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.4032639070
Directory	/workspace/72.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1290767871
Short name	T1258
Test name
Test status
Simulation time	782002080 ps
CPU time	39.23 seconds
Started	May 23 04:36:19 PM PDT 24
Finished	May 23 04:36:59 PM PDT 24
Peak memory	571852 kb
Host	smart-c2d39a46-19e3-4ec0-bffc-e5313ad1162c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290767871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.1290767871
Directory	/workspace/72.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_error_random.3348180558
Short name	T1543
Test name
Test status
Simulation time	2050201336 ps
CPU time	71.57 seconds
Started	May 23 04:36:15 PM PDT 24
Finished	May 23 04:37:27 PM PDT 24
Peak memory	571764 kb
Host	smart-9bf6a16b-8db4-45fa-a15f-30556cd046f3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348180558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.3348180558
Directory	/workspace/72.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_random.283821172
Short name	T1588
Test name
Test status
Simulation time	531419980 ps
CPU time	45.54 seconds
Started	May 23 04:36:00 PM PDT 24
Finished	May 23 04:36:47 PM PDT 24
Peak memory	571840 kb
Host	smart-56d8c8c8-4bf1-4dd1-81ae-61c74b26fd1a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283821172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.283821172
Directory	/workspace/72.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_random_large_delays.2838923979
Short name	T2146
Test name
Test status
Simulation time	108233409298 ps
CPU time	1218.32 seconds
Started	May 23 04:36:13 PM PDT 24
Finished	May 23 04:56:32 PM PDT 24
Peak memory	572016 kb
Host	smart-e3d15581-2454-4719-9b99-88767cefe60d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838923979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.2838923979
Directory	/workspace/72.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.2477396136
Short name	T2392
Test name
Test status
Simulation time	32795755140 ps
CPU time	601.49 seconds
Started	May 23 04:36:15 PM PDT 24
Finished	May 23 04:46:17 PM PDT 24
Peak memory	572016 kb
Host	smart-1e6a917d-f86d-4008-a0d7-c2c50373464f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477396136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.2477396136
Directory	/workspace/72.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3895683364
Short name	T2664
Test name
Test status
Simulation time	486012513 ps
CPU time	49.54 seconds
Started	May 23 04:36:16 PM PDT 24
Finished	May 23 04:37:07 PM PDT 24
Peak memory	571804 kb
Host	smart-3ead56e7-4a04-4bbb-8653-7549c22b5216
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895683364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.3895683364
Directory	/workspace/72.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_same_source.2134602439
Short name	T2595
Test name
Test status
Simulation time	2034744806 ps
CPU time	62 seconds
Started	May 23 04:36:15 PM PDT 24
Finished	May 23 04:37:19 PM PDT 24
Peak memory	571764 kb
Host	smart-9b8303e4-3054-4092-868f-c1a8c8718f5f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134602439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.2134602439
Directory	/workspace/72.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke.868179204
Short name	T1953
Test name
Test status
Simulation time	174827171 ps
CPU time	8.71 seconds
Started	May 23 04:36:01 PM PDT 24
Finished	May 23 04:36:11 PM PDT 24
Peak memory	563564 kb
Host	smart-ba8b1e96-265e-46fa-a257-0470404cf520
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868179204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.868179204
Directory	/workspace/72.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.999777522
Short name	T1644
Test name
Test status
Simulation time	7975166826 ps
CPU time	78.64 seconds
Started	May 23 04:36:01 PM PDT 24
Finished	May 23 04:37:21 PM PDT 24
Peak memory	563756 kb
Host	smart-68a7ff7a-3f41-4ade-8e97-2fb9fe27f5e9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999777522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.999777522
Directory	/workspace/72.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2938700422
Short name	T2395
Test name
Test status
Simulation time	5435247827 ps
CPU time	93.55 seconds
Started	May 23 04:36:00 PM PDT 24
Finished	May 23 04:37:35 PM PDT 24
Peak memory	563716 kb
Host	smart-d11a1c7d-aa5c-4ba5-9d1a-82d71100302b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938700422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.2938700422
Directory	/workspace/72.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.386497236
Short name	T1363
Test name
Test status
Simulation time	47504411 ps
CPU time	6.94 seconds
Started	May 23 04:36:03 PM PDT 24
Finished	May 23 04:36:11 PM PDT 24
Peak memory	563552 kb
Host	smart-12c47e34-98b7-4fd3-8df0-26899865362b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386497236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays .386497236
Directory	/workspace/72.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all.1964488082
Short name	T435
Test name
Test status
Simulation time	5931421323 ps
CPU time	234.59 seconds
Started	May 23 04:36:16 PM PDT 24
Finished	May 23 04:40:12 PM PDT 24
Peak memory	571928 kb
Host	smart-e3fb5ab5-8c4b-4c59-95d2-63a85f29e301
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964488082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.1964488082
Directory	/workspace/72.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3322115987
Short name	T1779
Test name
Test status
Simulation time	2428198837 ps
CPU time	96.4 seconds
Started	May 23 04:36:15 PM PDT 24
Finished	May 23 04:37:52 PM PDT 24
Peak memory	571996 kb
Host	smart-8feaf78c-83cb-4b63-8708-0c72c286d863
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322115987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3322115987
Directory	/workspace/72.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.101523390
Short name	T1984
Test name
Test status
Simulation time	1231690001 ps
CPU time	313.73 seconds
Started	May 23 04:36:19 PM PDT 24
Finished	May 23 04:41:34 PM PDT 24
Peak memory	572860 kb
Host	smart-b361bec4-fbf8-4d08-9721-09a0603f07f9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101523390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_ with_rand_reset.101523390
Directory	/workspace/72.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3159812936
Short name	T2663
Test name
Test status
Simulation time	1748606896 ps
CPU time	238.36 seconds
Started	May 23 04:36:16 PM PDT 24
Finished	May 23 04:40:16 PM PDT 24
Peak memory	574028 kb
Host	smart-ff2426b9-ed65-4ef3-ba15-25d78d7ba68b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159812936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.3159812936
Directory	/workspace/72.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.212938316
Short name	T615
Test name
Test status
Simulation time	1210228899 ps
CPU time	48.21 seconds
Started	May 23 04:36:17 PM PDT 24
Finished	May 23 04:37:06 PM PDT 24
Peak memory	571884 kb
Host	smart-a37e38ae-1fd9-404f-8dcd-e136c491d364
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212938316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.212938316
Directory	/workspace/72.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_access_same_device.3322642247
Short name	T1777
Test name
Test status
Simulation time	2762614603 ps
CPU time	121.05 seconds
Started	May 23 04:36:31 PM PDT 24
Finished	May 23 04:38:34 PM PDT 24
Peak memory	571880 kb
Host	smart-25b8acec-842b-4bc8-81f9-9150324df982
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322642247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .3322642247
Directory	/workspace/73.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.1600937693
Short name	T810
Test name
Test status
Simulation time	115204316034 ps
CPU time	1880.64 seconds
Started	May 23 04:36:34 PM PDT 24
Finished	May 23 05:07:57 PM PDT 24
Peak memory	572060 kb
Host	smart-6d7fea69-004a-4d75-9e33-8d65ba197958
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600937693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.1600937693
Directory	/workspace/73.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2076292713
Short name	T1264
Test name
Test status
Simulation time	23591982 ps
CPU time	5.24 seconds
Started	May 23 04:36:34 PM PDT 24
Finished	May 23 04:36:40 PM PDT 24
Peak memory	563556 kb
Host	smart-4f81ef05-d684-438f-a724-b04376e90b1e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076292713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.2076292713
Directory	/workspace/73.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_error_random.3114435805
Short name	T1694
Test name
Test status
Simulation time	1969537590 ps
CPU time	74.09 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 04:37:48 PM PDT 24
Peak memory	571796 kb
Host	smart-589263a4-8c15-42e4-b2bf-ead28f50a8cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114435805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.3114435805
Directory	/workspace/73.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_random.1167548284
Short name	T577
Test name
Test status
Simulation time	869351172 ps
CPU time	35.73 seconds
Started	May 23 04:36:15 PM PDT 24
Finished	May 23 04:36:52 PM PDT 24
Peak memory	571804 kb
Host	smart-65c84c16-7e0e-4d7c-9e41-179ade664c6d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167548284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1167548284
Directory	/workspace/73.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1059215106
Short name	T2650
Test name
Test status
Simulation time	21872917982 ps
CPU time	270.88 seconds
Started	May 23 04:36:17 PM PDT 24
Finished	May 23 04:40:49 PM PDT 24
Peak memory	571964 kb
Host	smart-49ed72a4-8ceb-4ed0-b06f-133039a321eb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059215106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1059215106
Directory	/workspace/73.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.1413709448
Short name	T2369
Test name
Test status
Simulation time	7389831461 ps
CPU time	128.72 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 04:38:42 PM PDT 24
Peak memory	563792 kb
Host	smart-701037ab-213b-4739-a59e-10d191d5f1c3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413709448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.1413709448
Directory	/workspace/73.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.3033501061
Short name	T1463
Test name
Test status
Simulation time	154693034 ps
CPU time	16.05 seconds
Started	May 23 04:36:18 PM PDT 24
Finished	May 23 04:36:35 PM PDT 24
Peak memory	571784 kb
Host	smart-57cfe168-25e1-4fdc-bde1-114b70382b27
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033501061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.3033501061
Directory	/workspace/73.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_same_source.2252761749
Short name	T1498
Test name
Test status
Simulation time	1234553103 ps
CPU time	36.21 seconds
Started	May 23 04:36:36 PM PDT 24
Finished	May 23 04:37:13 PM PDT 24
Peak memory	571764 kb
Host	smart-54e34321-c799-48fa-a614-395e8cc3d07e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252761749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2252761749
Directory	/workspace/73.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke.2182878412
Short name	T533
Test name
Test status
Simulation time	141023929 ps
CPU time	7.9 seconds
Started	May 23 04:36:17 PM PDT 24
Finished	May 23 04:36:26 PM PDT 24
Peak memory	563524 kb
Host	smart-29626a9c-e2cf-4dee-92e6-13cd8b361f1b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182878412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.2182878412
Directory	/workspace/73.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.2277372838
Short name	T1262
Test name
Test status
Simulation time	9703965357 ps
CPU time	104.48 seconds
Started	May 23 04:36:18 PM PDT 24
Finished	May 23 04:38:03 PM PDT 24
Peak memory	563796 kb
Host	smart-186efc56-4374-4ca9-9d94-5cbe4dfa9996
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277372838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.2277372838
Directory	/workspace/73.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2728090846
Short name	T2604
Test name
Test status
Simulation time	4402311635 ps
CPU time	78.38 seconds
Started	May 23 04:36:17 PM PDT 24
Finished	May 23 04:37:37 PM PDT 24
Peak memory	563688 kb
Host	smart-47e16130-b9e7-48fc-b72c-8fbe6ed6fb81
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728090846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.2728090846
Directory	/workspace/73.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.4238701771
Short name	T1348
Test name
Test status
Simulation time	44062809 ps
CPU time	6.81 seconds
Started	May 23 04:36:17 PM PDT 24
Finished	May 23 04:36:25 PM PDT 24
Peak memory	563564 kb
Host	smart-dd86ed9b-5586-40b7-b98d-dca41238592b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238701771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.4238701771
Directory	/workspace/73.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all.1804756435
Short name	T2464
Test name
Test status
Simulation time	1236837562 ps
CPU time	89.24 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 04:38:02 PM PDT 24
Peak memory	571860 kb
Host	smart-a31851d6-a661-40c6-8b6f-d8b3dc856204
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804756435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.1804756435
Directory	/workspace/73.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2738176507
Short name	T2570
Test name
Test status
Simulation time	1904254731 ps
CPU time	167.07 seconds
Started	May 23 04:36:33 PM PDT 24
Finished	May 23 04:39:21 PM PDT 24
Peak memory	571972 kb
Host	smart-3385a09b-c80e-4edf-b0dd-a972843c39b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738176507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2738176507
Directory	/workspace/73.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.1788884937
Short name	T2460
Test name
Test status
Simulation time	706124711 ps
CPU time	284.35 seconds
Started	May 23 04:36:33 PM PDT 24
Finished	May 23 04:41:19 PM PDT 24
Peak memory	572964 kb
Host	smart-f5582215-6e7d-41aa-90ce-1aebbe90fe1d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788884937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.1788884937
Directory	/workspace/73.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1855776406
Short name	T2291
Test name
Test status
Simulation time	5392106729 ps
CPU time	581.28 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 04:46:15 PM PDT 24
Peak memory	573108 kb
Host	smart-d21ecfdb-5923-411a-91b8-11aadbf0f7d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855776406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.1855776406
Directory	/workspace/73.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.2643181427
Short name	T1759
Test name
Test status
Simulation time	1078846853 ps
CPU time	60.11 seconds
Started	May 23 04:36:34 PM PDT 24
Finished	May 23 04:37:35 PM PDT 24
Peak memory	571812 kb
Host	smart-ed00337f-0af6-46fe-9451-4d5a378cb5fb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643181427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.2643181427
Directory	/workspace/73.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_access_same_device.2517517383
Short name	T2068
Test name
Test status
Simulation time	1007051728 ps
CPU time	87.77 seconds
Started	May 23 04:36:33 PM PDT 24
Finished	May 23 04:38:02 PM PDT 24
Peak memory	571872 kb
Host	smart-f3098e6d-61ad-4df3-a47a-23be09e8ea12
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517517383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .2517517383
Directory	/workspace/74.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1881342138
Short name	T2011
Test name
Test status
Simulation time	80302152427 ps
CPU time	1476.85 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 05:01:10 PM PDT 24
Peak memory	572060 kb
Host	smart-14cada1a-bf78-488a-a0d9-9b338b40dd62
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881342138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.1881342138
Directory	/workspace/74.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3177086260
Short name	T2478
Test name
Test status
Simulation time	260604664 ps
CPU time	13.5 seconds
Started	May 23 04:36:35 PM PDT 24
Finished	May 23 04:36:50 PM PDT 24
Peak memory	571740 kb
Host	smart-48b1afdc-e59a-41c6-b721-b2fcb44e4e35
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177086260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.3177086260
Directory	/workspace/74.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_error_random.148963315
Short name	T2320
Test name
Test status
Simulation time	115976022 ps
CPU time	12.18 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 04:36:46 PM PDT 24
Peak memory	571748 kb
Host	smart-29cef539-b891-4746-9e21-b47d902010f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148963315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.148963315
Directory	/workspace/74.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_random.369918809
Short name	T1471
Test name
Test status
Simulation time	591397228 ps
CPU time	26.7 seconds
Started	May 23 04:36:35 PM PDT 24
Finished	May 23 04:37:03 PM PDT 24
Peak memory	571788 kb
Host	smart-e21fd88a-e992-4577-a3ef-cc4a09905c60
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369918809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.369918809
Directory	/workspace/74.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1923071413
Short name	T2361
Test name
Test status
Simulation time	39925572323 ps
CPU time	471.83 seconds
Started	May 23 04:36:34 PM PDT 24
Finished	May 23 04:44:27 PM PDT 24
Peak memory	571932 kb
Host	smart-9aee7e13-f24b-46c8-b445-f6482f3f1d60
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923071413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1923071413
Directory	/workspace/74.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.4236493816
Short name	T2201
Test name
Test status
Simulation time	28473090707 ps
CPU time	477.44 seconds
Started	May 23 04:36:34 PM PDT 24
Finished	May 23 04:44:33 PM PDT 24
Peak memory	572024 kb
Host	smart-d22d95ce-593f-4d11-88dd-4814f3e7c742
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236493816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.4236493816
Directory	/workspace/74.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.2102440009
Short name	T482
Test name
Test status
Simulation time	141301111 ps
CPU time	16.64 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 04:36:49 PM PDT 24
Peak memory	571800 kb
Host	smart-8d0ebff2-4934-4936-9e0d-dc8bd55ecde2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102440009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.2102440009
Directory	/workspace/74.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_same_source.4234020782
Short name	T1956
Test name
Test status
Simulation time	458224534 ps
CPU time	37.14 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 04:37:11 PM PDT 24
Peak memory	571828 kb
Host	smart-0687b3ba-e9be-4709-bcd8-79061becddcb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234020782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.4234020782
Directory	/workspace/74.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke.3154992845
Short name	T404
Test name
Test status
Simulation time	154620809 ps
CPU time	8.41 seconds
Started	May 23 04:36:30 PM PDT 24
Finished	May 23 04:36:40 PM PDT 24
Peak memory	563504 kb
Host	smart-dcad27e6-0764-41a8-8b3f-5e8a3bef1597
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154992845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.3154992845
Directory	/workspace/74.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.4149099175
Short name	T1483
Test name
Test status
Simulation time	6292717208 ps
CPU time	67.5 seconds
Started	May 23 04:36:35 PM PDT 24
Finished	May 23 04:37:44 PM PDT 24
Peak memory	563760 kb
Host	smart-44fff1d4-ff26-4dc5-92cb-cfd15e8f13a2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149099175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.4149099175
Directory	/workspace/74.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3730705548
Short name	T1928
Test name
Test status
Simulation time	3950495761 ps
CPU time	76.9 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 04:37:50 PM PDT 24
Peak memory	563680 kb
Host	smart-93fc80c4-9ca7-4c2e-93e2-e45641e24fa5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730705548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.3730705548
Directory	/workspace/74.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3756321182
Short name	T1685
Test name
Test status
Simulation time	47943193 ps
CPU time	6.88 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 04:36:41 PM PDT 24
Peak memory	563508 kb
Host	smart-2276a826-33f7-4157-bfac-8b13b1d0aaa8
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756321182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.3756321182
Directory	/workspace/74.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all.946711006
Short name	T2380
Test name
Test status
Simulation time	9159460795 ps
CPU time	425.23 seconds
Started	May 23 04:36:35 PM PDT 24
Finished	May 23 04:43:42 PM PDT 24
Peak memory	573020 kb
Host	smart-87fca23b-9df2-47fc-802d-9d82573dfba7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946711006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.946711006
Directory	/workspace/74.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.592205465
Short name	T1797
Test name
Test status
Simulation time	4086442403 ps
CPU time	150.43 seconds
Started	May 23 04:36:35 PM PDT 24
Finished	May 23 04:39:07 PM PDT 24
Peak memory	571988 kb
Host	smart-3ba65db8-e298-4f95-b183-36d5f1bbea93
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592205465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.592205465
Directory	/workspace/74.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1305311853
Short name	T837
Test name
Test status
Simulation time	3390580951 ps
CPU time	399.64 seconds
Started	May 23 04:36:33 PM PDT 24
Finished	May 23 04:43:14 PM PDT 24
Peak memory	572392 kb
Host	smart-a747a359-cea1-4433-b725-b8dcfea2963e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305311853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.1305311853
Directory	/workspace/74.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3606911662
Short name	T791
Test name
Test status
Simulation time	6093450814 ps
CPU time	695.42 seconds
Started	May 23 04:36:32 PM PDT 24
Finished	May 23 04:48:09 PM PDT 24
Peak memory	573160 kb
Host	smart-b9039a71-d31e-4687-a103-e75e2de6b5d2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606911662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.3606911662
Directory	/workspace/74.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1378943275
Short name	T2573
Test name
Test status
Simulation time	1226394823 ps
CPU time	56.01 seconds
Started	May 23 04:36:35 PM PDT 24
Finished	May 23 04:37:33 PM PDT 24
Peak memory	571868 kb
Host	smart-0e206541-1d0c-445e-a3e3-2d92c7b174dd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378943275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1378943275
Directory	/workspace/74.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_access_same_device.1947453878
Short name	T799
Test name
Test status
Simulation time	2181605654 ps
CPU time	97.73 seconds
Started	May 23 04:36:50 PM PDT 24
Finished	May 23 04:38:29 PM PDT 24
Peak memory	571980 kb
Host	smart-abe2fa6a-ab01-40d4-966a-b9b34a3492cf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947453878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .1947453878
Directory	/workspace/75.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.186570785
Short name	T1957
Test name
Test status
Simulation time	41368333975 ps
CPU time	729.84 seconds
Started	May 23 04:36:49 PM PDT 24
Finished	May 23 04:49:01 PM PDT 24
Peak memory	572064 kb
Host	smart-fb81be1d-d368-435e-8b12-68cf01a56e5c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186570785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_d evice_slow_rsp.186570785
Directory	/workspace/75.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2111589297
Short name	T1628
Test name
Test status
Simulation time	214910203 ps
CPU time	11.76 seconds
Started	May 23 04:36:51 PM PDT 24
Finished	May 23 04:37:05 PM PDT 24
Peak memory	563648 kb
Host	smart-865aea03-7c62-4e1e-b2ae-c705c3bab02a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111589297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.2111589297
Directory	/workspace/75.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_error_random.3121674372
Short name	T1573
Test name
Test status
Simulation time	149047476 ps
CPU time	15.53 seconds
Started	May 23 04:36:52 PM PDT 24
Finished	May 23 04:37:09 PM PDT 24
Peak memory	571692 kb
Host	smart-2261f8aa-c584-454b-a9d2-8ea65490656d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121674372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.3121674372
Directory	/workspace/75.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_random.1769221876
Short name	T2337
Test name
Test status
Simulation time	236278946 ps
CPU time	12.56 seconds
Started	May 23 04:36:49 PM PDT 24
Finished	May 23 04:37:03 PM PDT 24
Peak memory	563612 kb
Host	smart-0b66e886-d292-416b-8f5a-b4fb5e867ab7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769221876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.1769221876
Directory	/workspace/75.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1693190482
Short name	T1623
Test name
Test status
Simulation time	33188750063 ps
CPU time	365.15 seconds
Started	May 23 04:36:49 PM PDT 24
Finished	May 23 04:42:56 PM PDT 24
Peak memory	572004 kb
Host	smart-18ce7585-0d79-4f77-9971-39f718ec4fce
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693190482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.1693190482
Directory	/workspace/75.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.4153490785
Short name	T410
Test name
Test status
Simulation time	25041800766 ps
CPU time	439.57 seconds
Started	May 23 04:36:51 PM PDT 24
Finished	May 23 04:44:12 PM PDT 24
Peak memory	572032 kb
Host	smart-820da84f-83dc-4b27-a4cf-a563b347901f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153490785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.4153490785
Directory	/workspace/75.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.2918384484
Short name	T1402
Test name
Test status
Simulation time	112589113 ps
CPU time	13.25 seconds
Started	May 23 04:36:52 PM PDT 24
Finished	May 23 04:37:07 PM PDT 24
Peak memory	571736 kb
Host	smart-3522fd94-aa6c-42c1-84d3-29d3072a15d7
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918384484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.2918384484
Directory	/workspace/75.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_same_source.3298706680
Short name	T562
Test name
Test status
Simulation time	2422938828 ps
CPU time	84.3 seconds
Started	May 23 04:36:50 PM PDT 24
Finished	May 23 04:38:16 PM PDT 24
Peak memory	571956 kb
Host	smart-b54322b8-791c-40ef-a9c4-3238fbf9512b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298706680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3298706680
Directory	/workspace/75.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke.1472801838
Short name	T1712
Test name
Test status
Simulation time	167309927 ps
CPU time	8.16 seconds
Started	May 23 04:36:34 PM PDT 24
Finished	May 23 04:36:44 PM PDT 24
Peak memory	563532 kb
Host	smart-bb93c07e-d794-4f8f-ae46-961c60385d61
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472801838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1472801838
Directory	/workspace/75.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.275417131
Short name	T2208
Test name
Test status
Simulation time	10499174374 ps
CPU time	108.6 seconds
Started	May 23 04:36:51 PM PDT 24
Finished	May 23 04:38:42 PM PDT 24
Peak memory	563732 kb
Host	smart-64634d7d-a5c6-46e2-99c2-9895f37e1af7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275417131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.275417131
Directory	/workspace/75.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2553747960
Short name	T2137
Test name
Test status
Simulation time	6407126225 ps
CPU time	115.94 seconds
Started	May 23 04:36:52 PM PDT 24
Finished	May 23 04:38:50 PM PDT 24
Peak memory	563784 kb
Host	smart-dea0b3cc-f946-4f47-a752-0cf27c303032
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553747960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.2553747960
Directory	/workspace/75.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2267345032
Short name	T2022
Test name
Test status
Simulation time	42115785 ps
CPU time	5.96 seconds
Started	May 23 04:36:49 PM PDT 24
Finished	May 23 04:36:57 PM PDT 24
Peak memory	563472 kb
Host	smart-c2cd1758-561a-40fb-8547-d69f85735567
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267345032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2267345032
Directory	/workspace/75.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.815938243
Short name	T1353
Test name
Test status
Simulation time	6010529 ps
CPU time	3.95 seconds
Started	May 23 04:36:51 PM PDT 24
Finished	May 23 04:36:57 PM PDT 24
Peak memory	555272 kb
Host	smart-d7a376e2-0a12-43d1-bc7f-5083f96fddf0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815938243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.815938243
Directory	/workspace/75.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.832243630
Short name	T1395
Test name
Test status
Simulation time	98594581 ps
CPU time	33.06 seconds
Started	May 23 04:36:54 PM PDT 24
Finished	May 23 04:37:28 PM PDT 24
Peak memory	572956 kb
Host	smart-8992fb1e-f32a-44f4-9c4b-6d28311aba09
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832243630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_reset_error.832243630
Directory	/workspace/75.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.3106885298
Short name	T590
Test name
Test status
Simulation time	399931727 ps
CPU time	21.23 seconds
Started	May 23 04:36:52 PM PDT 24
Finished	May 23 04:37:15 PM PDT 24
Peak memory	571804 kb
Host	smart-212ce81d-21c7-416a-ac4b-844d15898cb8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106885298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.3106885298
Directory	/workspace/75.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_access_same_device.2667557443
Short name	T2203
Test name
Test status
Simulation time	2559178740 ps
CPU time	108.07 seconds
Started	May 23 04:36:56 PM PDT 24
Finished	May 23 04:38:45 PM PDT 24
Peak memory	571968 kb
Host	smart-c944c429-d636-4612-8dec-097bfa01296e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667557443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .2667557443
Directory	/workspace/76.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2031688860
Short name	T1422
Test name
Test status
Simulation time	90683628735 ps
CPU time	1595.66 seconds
Started	May 23 04:36:53 PM PDT 24
Finished	May 23 05:03:30 PM PDT 24
Peak memory	572076 kb
Host	smart-c5fd7bf7-4f74-4252-babf-1a1332b14b41
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031688860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.2031688860
Directory	/workspace/76.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1249962275
Short name	T2027
Test name
Test status
Simulation time	57434375 ps
CPU time	9.9 seconds
Started	May 23 04:36:51 PM PDT 24
Finished	May 23 04:37:03 PM PDT 24
Peak memory	563580 kb
Host	smart-d4ce66b0-eaf0-46ac-b00c-6e73c8beae47
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249962275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.1249962275
Directory	/workspace/76.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_error_random.3126320351
Short name	T2760
Test name
Test status
Simulation time	502711321 ps
CPU time	45.01 seconds
Started	May 23 04:36:50 PM PDT 24
Finished	May 23 04:37:37 PM PDT 24
Peak memory	571732 kb
Host	smart-d891d568-0549-4e5b-b21e-a43ea1d58508
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126320351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3126320351
Directory	/workspace/76.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_random.3038462575
Short name	T459
Test name
Test status
Simulation time	2124254735 ps
CPU time	92.1 seconds
Started	May 23 04:36:52 PM PDT 24
Finished	May 23 04:38:26 PM PDT 24
Peak memory	571852 kb
Host	smart-5f943d23-78a4-409d-bde0-ccb6662b7935
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038462575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.3038462575
Directory	/workspace/76.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_random_large_delays.1922371598
Short name	T2214
Test name
Test status
Simulation time	44858875873 ps
CPU time	507.72 seconds
Started	May 23 04:36:54 PM PDT 24
Finished	May 23 04:45:23 PM PDT 24
Peak memory	572060 kb
Host	smart-690d6602-510a-4308-a399-fe6d00375810
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922371598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.1922371598
Directory	/workspace/76.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.4204313378
Short name	T2232
Test name
Test status
Simulation time	54974925730 ps
CPU time	1001.28 seconds
Started	May 23 04:36:54 PM PDT 24
Finished	May 23 04:53:37 PM PDT 24
Peak memory	572072 kb
Host	smart-ff03d687-4adc-403d-9550-2af5bbb7d67c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204313378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.4204313378
Directory	/workspace/76.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.47355166
Short name	T2267
Test name
Test status
Simulation time	372660723 ps
CPU time	32.93 seconds
Started	May 23 04:36:50 PM PDT 24
Finished	May 23 04:37:25 PM PDT 24
Peak memory	571852 kb
Host	smart-678eca24-50de-4783-b339-657fa04f2837
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47355166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_delay s.47355166
Directory	/workspace/76.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_same_source.594434620
Short name	T1597
Test name
Test status
Simulation time	1715875156 ps
CPU time	51.11 seconds
Started	May 23 04:36:51 PM PDT 24
Finished	May 23 04:37:45 PM PDT 24
Peak memory	571816 kb
Host	smart-cb032cea-e31e-4dbf-bd47-4dadfb7153da
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594434620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.594434620
Directory	/workspace/76.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke.3420821219
Short name	T2188
Test name
Test status
Simulation time	205126162 ps
CPU time	9.42 seconds
Started	May 23 04:36:51 PM PDT 24
Finished	May 23 04:37:02 PM PDT 24
Peak memory	563520 kb
Host	smart-efbfe5da-386c-4b90-a96f-5c3ee11bb7ef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420821219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.3420821219
Directory	/workspace/76.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.599781661
Short name	T1910
Test name
Test status
Simulation time	7224734900 ps
CPU time	78.03 seconds
Started	May 23 04:36:55 PM PDT 24
Finished	May 23 04:38:14 PM PDT 24
Peak memory	563752 kb
Host	smart-b0e3f54c-0d59-4521-b873-1341b34af4b7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599781661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.599781661
Directory	/workspace/76.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1313801243
Short name	T2549
Test name
Test status
Simulation time	4565166615 ps
CPU time	86.89 seconds
Started	May 23 04:36:50 PM PDT 24
Finished	May 23 04:38:19 PM PDT 24
Peak memory	563712 kb
Host	smart-da198d68-9eff-48d7-a0ec-29adb6ac4a84
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313801243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.1313801243
Directory	/workspace/76.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.25409422
Short name	T1894
Test name
Test status
Simulation time	52544307 ps
CPU time	6.79 seconds
Started	May 23 04:36:53 PM PDT 24
Finished	May 23 04:37:02 PM PDT 24
Peak memory	563524 kb
Host	smart-15ee785e-cedb-450f-a89e-0c69f23c9b3b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25409422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays.25409422
Directory	/workspace/76.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all.4209886278
Short name	T466
Test name
Test status
Simulation time	279030493 ps
CPU time	33.92 seconds
Started	May 23 04:36:51 PM PDT 24
Finished	May 23 04:37:27 PM PDT 24
Peak memory	571852 kb
Host	smart-e51f6216-5cbf-4740-873e-3dc6ad012f85
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209886278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.4209886278
Directory	/workspace/76.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.3210630296
Short name	T1749
Test name
Test status
Simulation time	3120916360 ps
CPU time	115.22 seconds
Started	May 23 04:36:57 PM PDT 24
Finished	May 23 04:38:53 PM PDT 24
Peak memory	571976 kb
Host	smart-f5224415-ca6b-4cbe-accc-53decd5fc024
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210630296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3210630296
Directory	/workspace/76.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1650748491
Short name	T1636
Test name
Test status
Simulation time	1159182136 ps
CPU time	49.49 seconds
Started	May 23 04:36:57 PM PDT 24
Finished	May 23 04:37:47 PM PDT 24
Peak memory	571804 kb
Host	smart-99fbf4ec-9d01-4dee-89d1-ab54a6674364
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650748491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1650748491
Directory	/workspace/76.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_access_same_device.1762101626
Short name	T2229
Test name
Test status
Simulation time	1430164831 ps
CPU time	63.05 seconds
Started	May 23 04:37:14 PM PDT 24
Finished	May 23 04:38:18 PM PDT 24
Peak memory	571820 kb
Host	smart-84ce388e-bd94-45d8-ade2-89218533f177
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762101626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .1762101626
Directory	/workspace/77.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1663967607
Short name	T2505
Test name
Test status
Simulation time	22191793021 ps
CPU time	404.14 seconds
Started	May 23 04:37:11 PM PDT 24
Finished	May 23 04:43:57 PM PDT 24
Peak memory	572044 kb
Host	smart-c0f6976d-26fa-4034-a9c0-c828399a4a51
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663967607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.1663967607
Directory	/workspace/77.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2174848509
Short name	T2054
Test name
Test status
Simulation time	77690181 ps
CPU time	11.95 seconds
Started	May 23 04:37:13 PM PDT 24
Finished	May 23 04:37:26 PM PDT 24
Peak memory	571848 kb
Host	smart-f241216b-6b56-45e0-8be9-11e4ff408a8b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174848509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.2174848509
Directory	/workspace/77.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_error_random.810671654
Short name	T2517
Test name
Test status
Simulation time	132534183 ps
CPU time	14.64 seconds
Started	May 23 04:37:11 PM PDT 24
Finished	May 23 04:37:28 PM PDT 24
Peak memory	571836 kb
Host	smart-0945dd27-8bb2-410b-a133-72ad5085b5bc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810671654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.810671654
Directory	/workspace/77.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_random.1629533880
Short name	T2043
Test name
Test status
Simulation time	143966088 ps
CPU time	15.11 seconds
Started	May 23 04:37:10 PM PDT 24
Finished	May 23 04:37:27 PM PDT 24
Peak memory	571784 kb
Host	smart-01ac2349-3197-48c4-aa01-0aeff17d884d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629533880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.1629533880
Directory	/workspace/77.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_random_large_delays.650313058
Short name	T1801
Test name
Test status
Simulation time	10532662404 ps
CPU time	116.26 seconds
Started	May 23 04:37:11 PM PDT 24
Finished	May 23 04:39:09 PM PDT 24
Peak memory	563876 kb
Host	smart-19d0d3c3-aecf-45b7-9238-98565ba1e830
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650313058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.650313058
Directory	/workspace/77.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.4220008186
Short name	T1556
Test name
Test status
Simulation time	54162728698 ps
CPU time	905.39 seconds
Started	May 23 04:37:15 PM PDT 24
Finished	May 23 04:52:21 PM PDT 24
Peak memory	572056 kb
Host	smart-5c1ee015-e7a1-4e94-82d0-a101d271dbb4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220008186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.4220008186
Directory	/workspace/77.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3441655399
Short name	T1825
Test name
Test status
Simulation time	238866866 ps
CPU time	24.06 seconds
Started	May 23 04:37:17 PM PDT 24
Finished	May 23 04:37:42 PM PDT 24
Peak memory	571816 kb
Host	smart-a70fb7f4-2749-4a0f-810f-b9598f78afdb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441655399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3441655399
Directory	/workspace/77.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_same_source.145577980
Short name	T2781
Test name
Test status
Simulation time	818804668 ps
CPU time	28.79 seconds
Started	May 23 04:37:10 PM PDT 24
Finished	May 23 04:37:39 PM PDT 24
Peak memory	571900 kb
Host	smart-f573ba63-724d-4419-8b5b-6e14aa37b984
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145577980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.145577980
Directory	/workspace/77.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke.3062990265
Short name	T2077
Test name
Test status
Simulation time	268791553 ps
CPU time	11.16 seconds
Started	May 23 04:37:13 PM PDT 24
Finished	May 23 04:37:26 PM PDT 24
Peak memory	563504 kb
Host	smart-cc1f0a1e-81ef-44a6-a9eb-6d1527b00767
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062990265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3062990265
Directory	/workspace/77.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.877608023
Short name	T2349
Test name
Test status
Simulation time	8582917053 ps
CPU time	100.35 seconds
Started	May 23 04:37:11 PM PDT 24
Finished	May 23 04:38:53 PM PDT 24
Peak memory	563748 kb
Host	smart-5c2f815d-3510-41e9-b73a-a7c0aa5bfbef
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877608023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.877608023
Directory	/workspace/77.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.781720873
Short name	T1635
Test name
Test status
Simulation time	5742217679 ps
CPU time	106.36 seconds
Started	May 23 04:37:21 PM PDT 24
Finished	May 23 04:39:08 PM PDT 24
Peak memory	563724 kb
Host	smart-8f39bdcc-1b6a-42da-ae88-c9e34cc228b1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781720873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.781720873
Directory	/workspace/77.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1247647915
Short name	T2542
Test name
Test status
Simulation time	46227019 ps
CPU time	6.88 seconds
Started	May 23 04:37:17 PM PDT 24
Finished	May 23 04:37:25 PM PDT 24
Peak memory	563556 kb
Host	smart-b9df3d16-20eb-4999-8a59-22ade21a17e4
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247647915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.1247647915
Directory	/workspace/77.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all.2648923907
Short name	T386
Test name
Test status
Simulation time	8819736405 ps
CPU time	392.35 seconds
Started	May 23 04:37:12 PM PDT 24
Finished	May 23 04:43:46 PM PDT 24
Peak memory	573064 kb
Host	smart-7d49aea7-bab0-4a34-9a44-c2f9c4c2382f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648923907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.2648923907
Directory	/workspace/77.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3182436783
Short name	T1963
Test name
Test status
Simulation time	10236298182 ps
CPU time	369 seconds
Started	May 23 04:37:17 PM PDT 24
Finished	May 23 04:43:27 PM PDT 24
Peak memory	572032 kb
Host	smart-2a1af4e8-c866-4981-a9a3-d0e1cc76f07c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182436783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3182436783
Directory	/workspace/77.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1948993020
Short name	T1680
Test name
Test status
Simulation time	413349872 ps
CPU time	149.33 seconds
Started	May 23 04:37:12 PM PDT 24
Finished	May 23 04:39:43 PM PDT 24
Peak memory	572792 kb
Host	smart-ff5a5a1f-a60b-46b8-ae07-99af6eb619c5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948993020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.1948993020
Directory	/workspace/77.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3324273409
Short name	T829
Test name
Test status
Simulation time	21578057138 ps
CPU time	830.67 seconds
Started	May 23 04:37:19 PM PDT 24
Finished	May 23 04:51:11 PM PDT 24
Peak memory	574140 kb
Host	smart-baa6fb5a-5746-48f7-9847-bd7adc1b9560
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324273409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.3324273409
Directory	/workspace/77.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1569768326
Short name	T1334
Test name
Test status
Simulation time	70360752 ps
CPU time	11.21 seconds
Started	May 23 04:37:12 PM PDT 24
Finished	May 23 04:37:24 PM PDT 24
Peak memory	571876 kb
Host	smart-0e3889f2-49e0-4120-85f4-a8441c2af591
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569768326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1569768326
Directory	/workspace/77.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_access_same_device.1671485895
Short name	T788
Test name
Test status
Simulation time	2866951457 ps
CPU time	124 seconds
Started	May 23 04:37:11 PM PDT 24
Finished	May 23 04:39:17 PM PDT 24
Peak memory	571900 kb
Host	smart-8e44fe9e-9dac-4b99-9e13-4712e68f2e02
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671485895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .1671485895
Directory	/workspace/78.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.59365382
Short name	T1896
Test name
Test status
Simulation time	70847049514 ps
CPU time	1228.17 seconds
Started	May 23 04:37:11 PM PDT 24
Finished	May 23 04:57:41 PM PDT 24
Peak memory	571976 kb
Host	smart-055a098f-4084-4e85-b1bb-ab64f41424e8
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59365382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_de vice_slow_rsp.59365382
Directory	/workspace/78.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2728194406
Short name	T1620
Test name
Test status
Simulation time	299095459 ps
CPU time	31.47 seconds
Started	May 23 04:37:11 PM PDT 24
Finished	May 23 04:37:44 PM PDT 24
Peak memory	571796 kb
Host	smart-93d8b614-86df-48ac-9050-5b7eab630cb6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728194406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.2728194406
Directory	/workspace/78.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_error_random.4047747123
Short name	T2442
Test name
Test status
Simulation time	2336504627 ps
CPU time	97.09 seconds
Started	May 23 04:37:17 PM PDT 24
Finished	May 23 04:38:55 PM PDT 24
Peak memory	571924 kb
Host	smart-62794d47-e2f7-4796-b0d9-ccfb5a1b9d5e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047747123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.4047747123
Directory	/workspace/78.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_random.2368393403
Short name	T1979
Test name
Test status
Simulation time	441644829 ps
CPU time	42.84 seconds
Started	May 23 04:37:13 PM PDT 24
Finished	May 23 04:37:57 PM PDT 24
Peak memory	571800 kb
Host	smart-8e1df4fc-f750-4ff3-bce5-38623486b5a7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368393403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2368393403
Directory	/workspace/78.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_random_large_delays.681011864
Short name	T2695
Test name
Test status
Simulation time	72781632441 ps
CPU time	768.34 seconds
Started	May 23 04:37:12 PM PDT 24
Finished	May 23 04:50:02 PM PDT 24
Peak memory	572064 kb
Host	smart-cf1a954e-23b5-46fd-9292-bd5db915833e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681011864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.681011864
Directory	/workspace/78.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.4073094515
Short name	T1548
Test name
Test status
Simulation time	33083927905 ps
CPU time	622.95 seconds
Started	May 23 04:37:15 PM PDT 24
Finished	May 23 04:47:39 PM PDT 24
Peak memory	572048 kb
Host	smart-f0cb8ac6-683f-4c2b-b17f-8eddc79bc5a4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073094515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.4073094515
Directory	/workspace/78.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.481060672
Short name	T1491
Test name
Test status
Simulation time	89244551 ps
CPU time	12.21 seconds
Started	May 23 04:37:14 PM PDT 24
Finished	May 23 04:37:28 PM PDT 24
Peak memory	571740 kb
Host	smart-1e490143-ad7f-4e41-abbc-8ee550e7b490
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481060672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_dela ys.481060672
Directory	/workspace/78.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_same_source.3256356396
Short name	T569
Test name
Test status
Simulation time	1447929981 ps
CPU time	49.45 seconds
Started	May 23 04:37:15 PM PDT 24
Finished	May 23 04:38:05 PM PDT 24
Peak memory	571740 kb
Host	smart-77414eff-318e-4371-930a-1efb7497a357
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256356396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3256356396
Directory	/workspace/78.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke.1580853476
Short name	T1552
Test name
Test status
Simulation time	157658762 ps
CPU time	8.55 seconds
Started	May 23 04:37:12 PM PDT 24
Finished	May 23 04:37:22 PM PDT 24
Peak memory	563528 kb
Host	smart-4a0c225d-7fc7-4d89-aa52-88a6edfcce6b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580853476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.1580853476
Directory	/workspace/78.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.4157416336
Short name	T603
Test name
Test status
Simulation time	8335769645 ps
CPU time	85.65 seconds
Started	May 23 04:37:13 PM PDT 24
Finished	May 23 04:38:40 PM PDT 24
Peak memory	563732 kb
Host	smart-38fb6cd1-6bb2-4901-90fa-c86ee09fc3e3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157416336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.4157416336
Directory	/workspace/78.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.647710114
Short name	T2596
Test name
Test status
Simulation time	4222643166 ps
CPU time	79.24 seconds
Started	May 23 04:37:11 PM PDT 24
Finished	May 23 04:38:31 PM PDT 24
Peak memory	563708 kb
Host	smart-7a6244e6-903a-4841-a716-97a7b6ea8f4c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647710114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.647710114
Directory	/workspace/78.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2805919048
Short name	T1291
Test name
Test status
Simulation time	53821245 ps
CPU time	6.55 seconds
Started	May 23 04:37:17 PM PDT 24
Finished	May 23 04:37:24 PM PDT 24
Peak memory	563556 kb
Host	smart-60d37de2-9f7c-49f3-8865-3eb88954075f
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805919048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.2805919048
Directory	/workspace/78.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all.4013474618
Short name	T2623
Test name
Test status
Simulation time	6711927266 ps
CPU time	244.76 seconds
Started	May 23 04:37:12 PM PDT 24
Finished	May 23 04:41:19 PM PDT 24
Peak memory	572000 kb
Host	smart-54dfb618-0e66-4fd4-856b-47447a5257f4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013474618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.4013474618
Directory	/workspace/78.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.3694839907
Short name	T1842
Test name
Test status
Simulation time	14223403002 ps
CPU time	525.72 seconds
Started	May 23 04:37:11 PM PDT 24
Finished	May 23 04:45:58 PM PDT 24
Peak memory	572892 kb
Host	smart-cdeca70a-c58e-47fd-a18f-a8116393ab85
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694839907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.3694839907
Directory	/workspace/78.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1810694032
Short name	T2346
Test name
Test status
Simulation time	978204242 ps
CPU time	354.38 seconds
Started	May 23 04:37:16 PM PDT 24
Finished	May 23 04:43:12 PM PDT 24
Peak memory	572908 kb
Host	smart-0a724e36-5c01-408f-bf05-ac6522bbcb4e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810694032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.1810694032
Directory	/workspace/78.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3207100360
Short name	T2641
Test name
Test status
Simulation time	796188059 ps
CPU time	201.28 seconds
Started	May 23 04:37:09 PM PDT 24
Finished	May 23 04:40:31 PM PDT 24
Peak memory	574020 kb
Host	smart-2d2ed226-967d-4243-91bc-84f210926a75
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207100360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.3207100360
Directory	/workspace/78.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.691483114
Short name	T2793
Test name
Test status
Simulation time	665223988 ps
CPU time	31.25 seconds
Started	May 23 04:37:11 PM PDT 24
Finished	May 23 04:37:44 PM PDT 24
Peak memory	571836 kb
Host	smart-b3c2c6f3-bf8b-4321-92b4-67cfa7b456bc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691483114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.691483114
Directory	/workspace/78.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_access_same_device.118190182
Short name	T2600
Test name
Test status
Simulation time	706778322 ps
CPU time	59.37 seconds
Started	May 23 04:37:30 PM PDT 24
Finished	May 23 04:38:31 PM PDT 24
Peak memory	571824 kb
Host	smart-46c957ea-9513-4a91-92ed-1e2299b9c4b2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118190182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device. 118190182
Directory	/workspace/79.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2174447744
Short name	T2152
Test name
Test status
Simulation time	28783548378 ps
CPU time	503.49 seconds
Started	May 23 04:37:40 PM PDT 24
Finished	May 23 04:46:05 PM PDT 24
Peak memory	572004 kb
Host	smart-d56b7c07-b745-4bfa-8e32-a23bd0757111
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174447744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.2174447744
Directory	/workspace/79.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1469299333
Short name	T2717
Test name
Test status
Simulation time	503244873 ps
CPU time	24.37 seconds
Started	May 23 04:37:34 PM PDT 24
Finished	May 23 04:37:59 PM PDT 24
Peak memory	571752 kb
Host	smart-fcf591f0-ab3d-4094-84e8-e8caa9a9be2a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469299333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.1469299333
Directory	/workspace/79.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_error_random.2353717780
Short name	T636
Test name
Test status
Simulation time	263890299 ps
CPU time	24.14 seconds
Started	May 23 04:37:30 PM PDT 24
Finished	May 23 04:37:55 PM PDT 24
Peak memory	571800 kb
Host	smart-c3fdea05-5d29-4aa5-8a03-47018c0bdd16
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353717780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.2353717780
Directory	/workspace/79.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_random.1258535570
Short name	T2711
Test name
Test status
Simulation time	889733127 ps
CPU time	34.64 seconds
Started	May 23 04:37:28 PM PDT 24
Finished	May 23 04:38:04 PM PDT 24
Peak memory	571764 kb
Host	smart-1a7de019-92ad-4c5f-b25c-f689f19ae2f9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258535570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.1258535570
Directory	/workspace/79.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3797600738
Short name	T2388
Test name
Test status
Simulation time	10205029093 ps
CPU time	110.68 seconds
Started	May 23 04:37:35 PM PDT 24
Finished	May 23 04:39:26 PM PDT 24
Peak memory	563836 kb
Host	smart-0d17012a-1df0-4872-8b2b-33991d292430
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797600738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3797600738
Directory	/workspace/79.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.2941718173
Short name	T1843
Test name
Test status
Simulation time	13158603571 ps
CPU time	246.5 seconds
Started	May 23 04:37:34 PM PDT 24
Finished	May 23 04:41:41 PM PDT 24
Peak memory	571984 kb
Host	smart-8c1ca72a-e688-4a34-a6b7-e6ae2c594985
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941718173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.2941718173
Directory	/workspace/79.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.1199363457
Short name	T576
Test name
Test status
Simulation time	154368628 ps
CPU time	18.32 seconds
Started	May 23 04:37:35 PM PDT 24
Finished	May 23 04:37:54 PM PDT 24
Peak memory	571812 kb
Host	smart-202c5325-95dc-41e1-8042-f1ec0cc46d7a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199363457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.1199363457
Directory	/workspace/79.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_same_source.1196770984
Short name	T1838
Test name
Test status
Simulation time	416674023 ps
CPU time	16.11 seconds
Started	May 23 04:37:35 PM PDT 24
Finished	May 23 04:37:52 PM PDT 24
Peak memory	571756 kb
Host	smart-65e68ac0-3f82-4479-abc3-95649ee8d3ae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196770984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.1196770984
Directory	/workspace/79.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke.402496944
Short name	T1580
Test name
Test status
Simulation time	213926278 ps
CPU time	9.76 seconds
Started	May 23 04:37:30 PM PDT 24
Finished	May 23 04:37:41 PM PDT 24
Peak memory	563520 kb
Host	smart-6bcff435-fee1-4a79-85bc-296f21ce3072
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402496944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.402496944
Directory	/workspace/79.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.1447107405
Short name	T2223
Test name
Test status
Simulation time	7052756620 ps
CPU time	81.65 seconds
Started	May 23 04:37:18 PM PDT 24
Finished	May 23 04:38:40 PM PDT 24
Peak memory	563772 kb
Host	smart-566bc602-5b5c-4dd8-97db-f1487fbc30b1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447107405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.1447107405
Directory	/workspace/79.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.4036712301
Short name	T2747
Test name
Test status
Simulation time	6861787585 ps
CPU time	119.51 seconds
Started	May 23 04:37:37 PM PDT 24
Finished	May 23 04:39:37 PM PDT 24
Peak memory	563820 kb
Host	smart-8aa54797-7f93-482b-92d4-95a67886094e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036712301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.4036712301
Directory	/workspace/79.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1981104181
Short name	T1615
Test name
Test status
Simulation time	51678670 ps
CPU time	7.12 seconds
Started	May 23 04:37:37 PM PDT 24
Finished	May 23 04:37:45 PM PDT 24
Peak memory	563564 kb
Host	smart-5b812e03-b5e9-40dd-8f71-bdf1fccf4091
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981104181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.1981104181
Directory	/workspace/79.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all.2089174231
Short name	T2078
Test name
Test status
Simulation time	1475300801 ps
CPU time	135.31 seconds
Started	May 23 04:37:32 PM PDT 24
Finished	May 23 04:39:48 PM PDT 24
Peak memory	571848 kb
Host	smart-29cdccdb-3a69-473c-9720-1fdb735aa347
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089174231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2089174231
Directory	/workspace/79.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.4123757833
Short name	T1274
Test name
Test status
Simulation time	53803508 ps
CPU time	27.18 seconds
Started	May 23 04:37:30 PM PDT 24
Finished	May 23 04:37:59 PM PDT 24
Peak memory	571908 kb
Host	smart-5f934bb8-720e-4c10-a0ee-014b0a6fc85f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123757833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.4123757833
Directory	/workspace/79.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.1889104599
Short name	T1762
Test name
Test status
Simulation time	891089474 ps
CPU time	38.61 seconds
Started	May 23 04:37:37 PM PDT 24
Finished	May 23 04:38:16 PM PDT 24
Peak memory	571844 kb
Host	smart-215fde45-2457-468d-b072-1c8b3cc35dee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889104599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.1889104599
Directory	/workspace/79.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/8.chip_csr_rw.1864571848
Short name	T2521
Test name
Test status
Simulation time	5984803044 ps
CPU time	679.91 seconds
Started	May 23 04:22:50 PM PDT 24
Finished	May 23 04:34:11 PM PDT 24
Peak memory	591956 kb
Host	smart-3e3db676-b106-43b4-88ad-6c9e7082153e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864571848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1864571848
Directory	/workspace/8.chip_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.28769639
Short name	T2726
Test name
Test status
Simulation time	15395680646 ps
CPU time	1994.44 seconds
Started	May 23 04:22:18 PM PDT 24
Finished	May 23 04:55:34 PM PDT 24
Peak memory	586704 kb
Host	smart-952810a9-ccd9-470d-8ef7-c2bb519904c8
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28769639 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.chip_same_csr_outstanding.28769639
Directory	/workspace/8.chip_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.chip_tl_errors.4231648606
Short name	T515
Test name
Test status
Simulation time	3692517620 ps
CPU time	360.23 seconds
Started	May 23 04:22:19 PM PDT 24
Finished	May 23 04:28:20 PM PDT 24
Peak memory	594244 kb
Host	smart-0cfa4055-3006-46b5-9953-6eeb6ea47924
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231648606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.4231648606
Directory	/workspace/8.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_access_same_device.2475236486
Short name	T1734
Test name
Test status
Simulation time	1084011216 ps
CPU time	98.67 seconds
Started	May 23 04:22:33 PM PDT 24
Finished	May 23 04:24:13 PM PDT 24
Peak memory	571980 kb
Host	smart-08b37a57-b89a-45a7-98d2-2db96041ae12
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475236486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 2475236486
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.812698419
Short name	T432
Test name
Test status
Simulation time	127395257813 ps
CPU time	2295.55 seconds
Started	May 23 04:22:34 PM PDT 24
Finished	May 23 05:00:52 PM PDT 24
Peak memory	571980 kb
Host	smart-6b9763b0-d03d-4f57-ab16-27dd7b5d42c4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812698419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de vice_slow_rsp.812698419
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3348880827
Short name	T1280
Test name
Test status
Simulation time	479392539 ps
CPU time	21.17 seconds
Started	May 23 04:22:34 PM PDT 24
Finished	May 23 04:22:57 PM PDT 24
Peak memory	571868 kb
Host	smart-4442fc7e-700e-40ab-bce8-5b8d415e5bc3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348880827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .3348880827
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_error_random.1844103553
Short name	T548
Test name
Test status
Simulation time	565176734 ps
CPU time	55.12 seconds
Started	May 23 04:22:33 PM PDT 24
Finished	May 23 04:23:30 PM PDT 24
Peak memory	571804 kb
Host	smart-8bae5914-fc05-4cb7-a7da-4f817e8a1386
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844103553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1844103553
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_random.2374093866
Short name	T1329
Test name
Test status
Simulation time	66944068 ps
CPU time	11.63 seconds
Started	May 23 04:22:27 PM PDT 24
Finished	May 23 04:22:40 PM PDT 24
Peak memory	563632 kb
Host	smart-3230810c-4503-440d-90ac-7d8365a47ffe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374093866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.2374093866
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1166485871
Short name	T1886
Test name
Test status
Simulation time	31039843115 ps
CPU time	335.52 seconds
Started	May 23 04:22:18 PM PDT 24
Finished	May 23 04:27:55 PM PDT 24
Peak memory	571980 kb
Host	smart-c22373c1-7127-4e23-acfe-8fa5120d6f5e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166485871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1166485871
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.3630498480
Short name	T2013
Test name
Test status
Simulation time	9078958610 ps
CPU time	174.51 seconds
Started	May 23 04:22:17 PM PDT 24
Finished	May 23 04:25:12 PM PDT 24
Peak memory	572056 kb
Host	smart-b3947569-1c49-4095-ac4e-d100aae175dd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630498480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3630498480
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.595459531
Short name	T449
Test name
Test status
Simulation time	383738334 ps
CPU time	42.47 seconds
Started	May 23 04:22:34 PM PDT 24
Finished	May 23 04:23:19 PM PDT 24
Peak memory	571848 kb
Host	smart-8e7cd117-d8da-4413-af9b-3e94837ee9f6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595459531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delay s.595459531
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_same_source.912347185
Short name	T1827
Test name
Test status
Simulation time	521438692 ps
CPU time	42.89 seconds
Started	May 23 04:22:39 PM PDT 24
Finished	May 23 04:23:23 PM PDT 24
Peak memory	571792 kb
Host	smart-5fae9ce1-f7b4-4484-b2b4-561fa9fb6f3d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912347185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.912347185
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke.3974845368
Short name	T1579
Test name
Test status
Simulation time	156034200 ps
CPU time	8.09 seconds
Started	May 23 04:22:15 PM PDT 24
Finished	May 23 04:22:24 PM PDT 24
Peak memory	563548 kb
Host	smart-f4b77b02-5c5e-408b-acce-9b519d1d836e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974845368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3974845368
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.3749926311
Short name	T2091
Test name
Test status
Simulation time	10461931868 ps
CPU time	118.69 seconds
Started	May 23 04:22:18 PM PDT 24
Finished	May 23 04:24:18 PM PDT 24
Peak memory	563732 kb
Host	smart-15422150-12bd-4504-9b2f-0b5fa6ccf2b6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749926311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3749926311
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3820690793
Short name	T2362
Test name
Test status
Simulation time	5762733279 ps
CPU time	103.51 seconds
Started	May 23 04:22:26 PM PDT 24
Finished	May 23 04:24:10 PM PDT 24
Peak memory	563752 kb
Host	smart-8b8c76c7-e306-4579-be68-4a2268353e5b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820690793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3820690793
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.2441404943
Short name	T2266
Test name
Test status
Simulation time	50951222 ps
CPU time	7.43 seconds
Started	May 23 04:22:18 PM PDT 24
Finished	May 23 04:22:26 PM PDT 24
Peak memory	563572 kb
Host	smart-f7efb255-6c76-476a-8f65-6008714b8332
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441404943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .2441404943
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all.623876817
Short name	T1853
Test name
Test status
Simulation time	1911860098 ps
CPU time	199.79 seconds
Started	May 23 04:22:34 PM PDT 24
Finished	May 23 04:25:56 PM PDT 24
Peak memory	572584 kb
Host	smart-1ea37c20-a764-43cf-b18b-1eb37faa86b8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623876817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.623876817
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3521853539
Short name	T1653
Test name
Test status
Simulation time	3404196787 ps
CPU time	298.77 seconds
Started	May 23 04:22:47 PM PDT 24
Finished	May 23 04:27:47 PM PDT 24
Peak memory	573104 kb
Host	smart-a4c93617-a2ba-4154-ae2c-6e1e629df9cf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521853539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3521853539
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.196550767
Short name	T2482
Test name
Test status
Simulation time	7466613349 ps
CPU time	521.61 seconds
Started	May 23 04:22:47 PM PDT 24
Finished	May 23 04:31:29 PM PDT 24
Peak memory	573048 kb
Host	smart-fac8cc82-ae2e-4b25-a8d2-4d320b1762fe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196550767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_w ith_rand_reset.196550767
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.716567503
Short name	T1899
Test name
Test status
Simulation time	4261676331 ps
CPU time	420.47 seconds
Started	May 23 04:22:57 PM PDT 24
Finished	May 23 04:29:59 PM PDT 24
Peak memory	573128 kb
Host	smart-1c104b9b-c11f-4eda-bda1-21d36efcfc96
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716567503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_reset_error.716567503
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.3615102212
Short name	T1875
Test name
Test status
Simulation time	18330985 ps
CPU time	5.65 seconds
Started	May 23 04:22:33 PM PDT 24
Finished	May 23 04:22:41 PM PDT 24
Peak memory	563588 kb
Host	smart-9f7f133e-b561-466e-ac77-266a5a57477c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615102212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3615102212
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_access_same_device.2732988049
Short name	T1943
Test name
Test status
Simulation time	93785858 ps
CPU time	8.55 seconds
Started	May 23 04:37:29 PM PDT 24
Finished	May 23 04:37:39 PM PDT 24
Peak memory	563568 kb
Host	smart-be94f2db-6f07-4b72-909f-7910af2edf35
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732988049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .2732988049
Directory	/workspace/80.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2600900725
Short name	T1965
Test name
Test status
Simulation time	52700213312 ps
CPU time	978.87 seconds
Started	May 23 04:37:29 PM PDT 24
Finished	May 23 04:53:49 PM PDT 24
Peak memory	572072 kb
Host	smart-b7d62f39-6ea6-4892-8588-c539487474f7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600900725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.2600900725
Directory	/workspace/80.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.3447543640
Short name	T1321
Test name
Test status
Simulation time	520632665 ps
CPU time	21.91 seconds
Started	May 23 04:37:35 PM PDT 24
Finished	May 23 04:37:57 PM PDT 24
Peak memory	571752 kb
Host	smart-edca59a0-4ee0-40d7-909b-7324736adee3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447543640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.3447543640
Directory	/workspace/80.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_error_random.932692314
Short name	T1581
Test name
Test status
Simulation time	1571248467 ps
CPU time	62.58 seconds
Started	May 23 04:37:36 PM PDT 24
Finished	May 23 04:38:39 PM PDT 24
Peak memory	571792 kb
Host	smart-ce5ef55b-6da9-4ed9-b62d-5ce75ce6d092
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932692314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.932692314
Directory	/workspace/80.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_random.2078910081
Short name	T2165
Test name
Test status
Simulation time	532739557 ps
CPU time	19.27 seconds
Started	May 23 04:37:28 PM PDT 24
Finished	May 23 04:37:48 PM PDT 24
Peak memory	571856 kb
Host	smart-99496388-59fb-480b-a990-b311337792f7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078910081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.2078910081
Directory	/workspace/80.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1004956205
Short name	T1873
Test name
Test status
Simulation time	98707037493 ps
CPU time	1136.82 seconds
Started	May 23 04:37:29 PM PDT 24
Finished	May 23 04:56:27 PM PDT 24
Peak memory	572032 kb
Host	smart-899c8664-37d7-4eef-a2c9-ddcbe1acab97
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004956205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.1004956205
Directory	/workspace/80.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3273062548
Short name	T610
Test name
Test status
Simulation time	28473404612 ps
CPU time	491.28 seconds
Started	May 23 04:37:35 PM PDT 24
Finished	May 23 04:45:47 PM PDT 24
Peak memory	572008 kb
Host	smart-5e451990-7312-448d-981c-cde30c459312
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273062548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3273062548
Directory	/workspace/80.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.3015584223
Short name	T437
Test name
Test status
Simulation time	521434315 ps
CPU time	52.81 seconds
Started	May 23 04:37:38 PM PDT 24
Finished	May 23 04:38:32 PM PDT 24
Peak memory	571816 kb
Host	smart-0654d9ae-e9ce-4b85-937c-d627bb1a2a0a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015584223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.3015584223
Directory	/workspace/80.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_same_source.1854229939
Short name	T2649
Test name
Test status
Simulation time	1611845003 ps
CPU time	49.76 seconds
Started	May 23 04:37:40 PM PDT 24
Finished	May 23 04:38:32 PM PDT 24
Peak memory	571716 kb
Host	smart-1843f8b6-3aa2-46c4-b1a5-ed5b4e4f8e6c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854229939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.1854229939
Directory	/workspace/80.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke.3641423809
Short name	T600
Test name
Test status
Simulation time	59923060 ps
CPU time	6.97 seconds
Started	May 23 04:37:28 PM PDT 24
Finished	May 23 04:37:36 PM PDT 24
Peak memory	563472 kb
Host	smart-1d8b0eef-5866-459f-ab0d-1b7464176eca
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641423809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.3641423809
Directory	/workspace/80.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1004283470
Short name	T2754
Test name
Test status
Simulation time	10567904837 ps
CPU time	115.5 seconds
Started	May 23 04:37:29 PM PDT 24
Finished	May 23 04:39:26 PM PDT 24
Peak memory	563804 kb
Host	smart-a202d553-bad6-450a-8769-6a7480e2caa3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004283470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1004283470
Directory	/workspace/80.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1716806690
Short name	T1244
Test name
Test status
Simulation time	4583957008 ps
CPU time	81.16 seconds
Started	May 23 04:37:27 PM PDT 24
Finished	May 23 04:38:49 PM PDT 24
Peak memory	563788 kb
Host	smart-f7a73739-74cd-4b5b-a7d8-154cbed5d573
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716806690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.1716806690
Directory	/workspace/80.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.4274538809
Short name	T2632
Test name
Test status
Simulation time	50791243 ps
CPU time	6.41 seconds
Started	May 23 04:37:35 PM PDT 24
Finished	May 23 04:37:43 PM PDT 24
Peak memory	563524 kb
Host	smart-7af33894-ecad-4071-946f-417a92db88a5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274538809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.4274538809
Directory	/workspace/80.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all.1982660577
Short name	T554
Test name
Test status
Simulation time	669809055 ps
CPU time	24.32 seconds
Started	May 23 04:37:31 PM PDT 24
Finished	May 23 04:37:56 PM PDT 24
Peak memory	571856 kb
Host	smart-2db98bed-b4ef-4cf6-83b9-9d2b97827967
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982660577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.1982660577
Directory	/workspace/80.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.726749170
Short name	T2136
Test name
Test status
Simulation time	3846260855 ps
CPU time	139.51 seconds
Started	May 23 04:37:32 PM PDT 24
Finished	May 23 04:39:53 PM PDT 24
Peak memory	572072 kb
Host	smart-e7ad039f-9497-4b76-a4fd-f332b90a20bc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726749170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.726749170
Directory	/workspace/80.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2549229683
Short name	T2377
Test name
Test status
Simulation time	354577985 ps
CPU time	175.83 seconds
Started	May 23 04:37:37 PM PDT 24
Finished	May 23 04:40:34 PM PDT 24
Peak memory	573620 kb
Host	smart-85337d27-afdd-4ad4-89a7-d62d5925ce9a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549229683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2549229683
Directory	/workspace/80.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2514010005
Short name	T2525
Test name
Test status
Simulation time	3263241693 ps
CPU time	399.87 seconds
Started	May 23 04:37:29 PM PDT 24
Finished	May 23 04:44:10 PM PDT 24
Peak memory	574172 kb
Host	smart-2d41c57b-6df1-42dd-aed4-d93b1665dd0e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514010005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.2514010005
Directory	/workspace/80.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.1324902957
Short name	T1861
Test name
Test status
Simulation time	60758698 ps
CPU time	10.69 seconds
Started	May 23 04:37:36 PM PDT 24
Finished	May 23 04:37:47 PM PDT 24
Peak memory	563624 kb
Host	smart-a546798e-96d2-4331-8321-bbcc310c655b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324902957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.1324902957
Directory	/workspace/80.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_access_same_device.3395600946
Short name	T1290
Test name
Test status
Simulation time	862115600 ps
CPU time	67.21 seconds
Started	May 23 04:37:37 PM PDT 24
Finished	May 23 04:38:45 PM PDT 24
Peak memory	571864 kb
Host	smart-b4d7bfc7-b1b7-4829-b190-73253debeacd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395600946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .3395600946
Directory	/workspace/81.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3736578529
Short name	T2100
Test name
Test status
Simulation time	94536475561 ps
CPU time	1626.07 seconds
Started	May 23 04:37:33 PM PDT 24
Finished	May 23 05:04:40 PM PDT 24
Peak memory	572088 kb
Host	smart-e5fcb653-4391-4734-b072-98642c36de0b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736578529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3736578529
Directory	/workspace/81.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.745298650
Short name	T1252
Test name
Test status
Simulation time	801062358 ps
CPU time	37.4 seconds
Started	May 23 04:37:49 PM PDT 24
Finished	May 23 04:38:28 PM PDT 24
Peak memory	571776 kb
Host	smart-59c52955-3700-4855-871d-23250129cd6b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745298650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr .745298650
Directory	/workspace/81.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_error_random.2128528625
Short name	T2008
Test name
Test status
Simulation time	495746952 ps
CPU time	22.09 seconds
Started	May 23 04:37:30 PM PDT 24
Finished	May 23 04:37:53 PM PDT 24
Peak memory	571752 kb
Host	smart-229d5192-816d-4d7f-a993-ad04e5d90c78
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128528625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.2128528625
Directory	/workspace/81.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_random.1726047641
Short name	T2330
Test name
Test status
Simulation time	1672903920 ps
CPU time	62.85 seconds
Started	May 23 04:37:28 PM PDT 24
Finished	May 23 04:38:31 PM PDT 24
Peak memory	571744 kb
Host	smart-cadf74ef-1269-45c2-8275-f16d7528f43a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726047641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.1726047641
Directory	/workspace/81.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_random_large_delays.1089584672
Short name	T1281
Test name
Test status
Simulation time	42745558478 ps
CPU time	482.08 seconds
Started	May 23 04:37:34 PM PDT 24
Finished	May 23 04:45:37 PM PDT 24
Peak memory	571972 kb
Host	smart-d589a079-40d3-4257-b3ca-451259f080b6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089584672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.1089584672
Directory	/workspace/81.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.2722249901
Short name	T2699
Test name
Test status
Simulation time	59461458491 ps
CPU time	995.96 seconds
Started	May 23 04:37:31 PM PDT 24
Finished	May 23 04:54:09 PM PDT 24
Peak memory	572048 kb
Host	smart-56ff2bf9-371b-4966-a790-35face85f4a3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722249901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.2722249901
Directory	/workspace/81.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.1192040523
Short name	T2353
Test name
Test status
Simulation time	230955761 ps
CPU time	23.38 seconds
Started	May 23 04:37:29 PM PDT 24
Finished	May 23 04:37:54 PM PDT 24
Peak memory	571708 kb
Host	smart-95c6e7f4-1236-43fd-9589-de163b0ce88b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192040523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.1192040523
Directory	/workspace/81.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_same_source.20446110
Short name	T1821
Test name
Test status
Simulation time	327899978 ps
CPU time	25.82 seconds
Started	May 23 04:37:37 PM PDT 24
Finished	May 23 04:38:04 PM PDT 24
Peak memory	571764 kb
Host	smart-03b7c9f2-0876-40f0-945e-9bc2d14bbce9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20446110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.20446110
Directory	/workspace/81.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke.1349203884
Short name	T2638
Test name
Test status
Simulation time	132087695 ps
CPU time	7.59 seconds
Started	May 23 04:37:38 PM PDT 24
Finished	May 23 04:37:46 PM PDT 24
Peak memory	563504 kb
Host	smart-5fe845ba-214c-4772-bdff-c34948ce8286
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349203884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.1349203884
Directory	/workspace/81.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1834921508
Short name	T560
Test name
Test status
Simulation time	9224238177 ps
CPU time	104.23 seconds
Started	May 23 04:37:32 PM PDT 24
Finished	May 23 04:39:17 PM PDT 24
Peak memory	563688 kb
Host	smart-2bac71da-9d41-4341-9706-dfa184d0b45b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834921508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1834921508
Directory	/workspace/81.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.523759637
Short name	T1407
Test name
Test status
Simulation time	5122412414 ps
CPU time	87.61 seconds
Started	May 23 04:37:33 PM PDT 24
Finished	May 23 04:39:01 PM PDT 24
Peak memory	563784 kb
Host	smart-2bb6a6d2-aa8f-4e4a-aa17-59ad07f86427
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523759637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.523759637
Directory	/workspace/81.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.401595516
Short name	T1919
Test name
Test status
Simulation time	48403269 ps
CPU time	6.92 seconds
Started	May 23 04:37:31 PM PDT 24
Finished	May 23 04:37:39 PM PDT 24
Peak memory	563496 kb
Host	smart-e6cefa90-e048-4734-b844-edd0ca10e529
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401595516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays .401595516
Directory	/workspace/81.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all.3122339599
Short name	T407
Test name
Test status
Simulation time	4382689791 ps
CPU time	353.48 seconds
Started	May 23 04:37:56 PM PDT 24
Finished	May 23 04:43:50 PM PDT 24
Peak memory	573004 kb
Host	smart-beeeec55-3835-469f-9f21-1fe6432e80ab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122339599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.3122339599
Directory	/workspace/81.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1826728917
Short name	T1426
Test name
Test status
Simulation time	5672993012 ps
CPU time	226.15 seconds
Started	May 23 04:37:46 PM PDT 24
Finished	May 23 04:41:34 PM PDT 24
Peak memory	572000 kb
Host	smart-c9b7e6af-d1e2-4464-b26f-6c5ee59ee004
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826728917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1826728917
Directory	/workspace/81.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3989792461
Short name	T1435
Test name
Test status
Simulation time	483438734 ps
CPU time	164.18 seconds
Started	May 23 04:37:45 PM PDT 24
Finished	May 23 04:40:31 PM PDT 24
Peak memory	572840 kb
Host	smart-5e120659-3fb2-4d40-853f-13e7b39955b6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989792461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.3989792461
Directory	/workspace/81.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3094886319
Short name	T825
Test name
Test status
Simulation time	9671929883 ps
CPU time	492.37 seconds
Started	May 23 04:37:46 PM PDT 24
Finished	May 23 04:46:01 PM PDT 24
Peak memory	573052 kb
Host	smart-845d5a69-0214-41fe-8f1c-eff442be9a6d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094886319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.3094886319
Directory	/workspace/81.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.1405828400
Short name	T2533
Test name
Test status
Simulation time	145975110 ps
CPU time	8.62 seconds
Started	May 23 04:37:41 PM PDT 24
Finished	May 23 04:37:51 PM PDT 24
Peak memory	563552 kb
Host	smart-94bb7c63-4127-4ce3-963a-c023afa2adc7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405828400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.1405828400
Directory	/workspace/81.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_access_same_device.1788695035
Short name	T1719
Test name
Test status
Simulation time	722582767 ps
CPU time	54 seconds
Started	May 23 04:37:45 PM PDT 24
Finished	May 23 04:38:41 PM PDT 24
Peak memory	571872 kb
Host	smart-56a3cabd-b148-4071-b03a-954a8c167cd4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788695035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .1788695035
Directory	/workspace/82.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1358218217
Short name	T2528
Test name
Test status
Simulation time	124774246692 ps
CPU time	2143.54 seconds
Started	May 23 04:37:46 PM PDT 24
Finished	May 23 05:13:33 PM PDT 24
Peak memory	572044 kb
Host	smart-43f2fdba-c326-4bd7-b436-a927bffcd8f4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358218217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.1358218217
Directory	/workspace/82.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2906953556
Short name	T2719
Test name
Test status
Simulation time	39850380 ps
CPU time	6.66 seconds
Started	May 23 04:37:56 PM PDT 24
Finished	May 23 04:38:03 PM PDT 24
Peak memory	563508 kb
Host	smart-30f69987-4829-4ee0-a4aa-b2d1080bcaf3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906953556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.2906953556
Directory	/workspace/82.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_error_random.2085830580
Short name	T2796
Test name
Test status
Simulation time	480736143 ps
CPU time	19.42 seconds
Started	May 23 04:37:49 PM PDT 24
Finished	May 23 04:38:10 PM PDT 24
Peak memory	571792 kb
Host	smart-253f72cc-db3b-4d1f-8dbb-be10e7be3220
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085830580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.2085830580
Directory	/workspace/82.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_random.548112662
Short name	T1836
Test name
Test status
Simulation time	2365426263 ps
CPU time	92.47 seconds
Started	May 23 04:37:47 PM PDT 24
Finished	May 23 04:39:22 PM PDT 24
Peak memory	571952 kb
Host	smart-fc3a4b08-dd31-47a1-aad7-a876f72fecb9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548112662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.548112662
Directory	/workspace/82.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2195329910
Short name	T465
Test name
Test status
Simulation time	71280293497 ps
CPU time	791.66 seconds
Started	May 23 04:37:53 PM PDT 24
Finished	May 23 04:51:06 PM PDT 24
Peak memory	572068 kb
Host	smart-6f5bd37e-59e4-4d28-bea7-b3e6184c464a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195329910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.2195329910
Directory	/workspace/82.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2389920186
Short name	T1410
Test name
Test status
Simulation time	41285538493 ps
CPU time	702.68 seconds
Started	May 23 04:37:48 PM PDT 24
Finished	May 23 04:49:33 PM PDT 24
Peak memory	572000 kb
Host	smart-d60c212c-2e10-4a98-bc04-1a7c8f5f9ef9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389920186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2389920186
Directory	/workspace/82.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1794647415
Short name	T552
Test name
Test status
Simulation time	299819358 ps
CPU time	31.11 seconds
Started	May 23 04:37:46 PM PDT 24
Finished	May 23 04:38:20 PM PDT 24
Peak memory	571732 kb
Host	smart-ee1379b8-b3cf-4a06-b24f-7247cd5d9d19
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794647415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.1794647415
Directory	/workspace/82.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_same_source.1302060511
Short name	T2438
Test name
Test status
Simulation time	1308722084 ps
CPU time	43.16 seconds
Started	May 23 04:37:46 PM PDT 24
Finished	May 23 04:38:31 PM PDT 24
Peak memory	571820 kb
Host	smart-b92418af-3ee9-43b1-bfd9-c9671192f462
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302060511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1302060511
Directory	/workspace/82.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke.3156968930
Short name	T1918
Test name
Test status
Simulation time	52854290 ps
CPU time	7.32 seconds
Started	May 23 04:37:48 PM PDT 24
Finished	May 23 04:37:57 PM PDT 24
Peak memory	563504 kb
Host	smart-7b3e1078-733b-421a-9187-bd17d9f915fb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156968930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3156968930
Directory	/workspace/82.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.3539332208
Short name	T2124
Test name
Test status
Simulation time	9709070873 ps
CPU time	108.19 seconds
Started	May 23 04:37:48 PM PDT 24
Finished	May 23 04:39:38 PM PDT 24
Peak memory	563812 kb
Host	smart-23fde85a-f83e-4c18-89d2-6a389ad2b081
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539332208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.3539332208
Directory	/workspace/82.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1988968639
Short name	T2520
Test name
Test status
Simulation time	4115543356 ps
CPU time	72.23 seconds
Started	May 23 04:37:46 PM PDT 24
Finished	May 23 04:39:01 PM PDT 24
Peak memory	563724 kb
Host	smart-5d634c76-8387-4e77-9041-4d3730973b24
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988968639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.1988968639
Directory	/workspace/82.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.1232805346
Short name	T1398
Test name
Test status
Simulation time	55002712 ps
CPU time	7.95 seconds
Started	May 23 04:37:47 PM PDT 24
Finished	May 23 04:37:57 PM PDT 24
Peak memory	563524 kb
Host	smart-c4f3c48d-8f18-472f-8956-0e100a966733
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232805346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.1232805346
Directory	/workspace/82.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all.1602504457
Short name	T474
Test name
Test status
Simulation time	11598869118 ps
CPU time	423.04 seconds
Started	May 23 04:37:48 PM PDT 24
Finished	May 23 04:44:53 PM PDT 24
Peak memory	573016 kb
Host	smart-b3dbf36c-90f6-4390-952f-3e26e8233dfe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602504457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.1602504457
Directory	/workspace/82.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.2603444857
Short name	T2242
Test name
Test status
Simulation time	5080968482 ps
CPU time	186.45 seconds
Started	May 23 04:37:46 PM PDT 24
Finished	May 23 04:40:54 PM PDT 24
Peak memory	571976 kb
Host	smart-78ae3841-c762-47e1-8676-6916cf15f798
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603444857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.2603444857
Directory	/workspace/82.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.542053389
Short name	T2319
Test name
Test status
Simulation time	119889068 ps
CPU time	47.03 seconds
Started	May 23 04:37:45 PM PDT 24
Finished	May 23 04:38:34 PM PDT 24
Peak memory	572924 kb
Host	smart-12eb0d80-9581-4dd4-abd6-a09cb31b5dc3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542053389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_ with_rand_reset.542053389
Directory	/workspace/82.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.854416493
Short name	T2367
Test name
Test status
Simulation time	483501394 ps
CPU time	102.73 seconds
Started	May 23 04:37:48 PM PDT 24
Finished	May 23 04:39:33 PM PDT 24
Peak memory	571960 kb
Host	smart-681d978d-cf25-415a-8690-fbb8b17105b1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854416493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_reset_error.854416493
Directory	/workspace/82.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.612717152
Short name	T2449
Test name
Test status
Simulation time	320336050 ps
CPU time	43.49 seconds
Started	May 23 04:37:47 PM PDT 24
Finished	May 23 04:38:33 PM PDT 24
Peak memory	571872 kb
Host	smart-d079a6c9-a595-4f50-9280-cadd0f63c1a4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612717152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.612717152
Directory	/workspace/82.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_access_same_device.1262863769
Short name	T2693
Test name
Test status
Simulation time	644039358 ps
CPU time	51.77 seconds
Started	May 23 04:38:00 PM PDT 24
Finished	May 23 04:38:53 PM PDT 24
Peak memory	571828 kb
Host	smart-df0a3f03-83d2-42ad-879a-b8da9c26d14c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262863769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .1262863769
Directory	/workspace/83.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3853929679
Short name	T1856
Test name
Test status
Simulation time	166460593098 ps
CPU time	2835.44 seconds
Started	May 23 04:37:56 PM PDT 24
Finished	May 23 05:25:12 PM PDT 24
Peak memory	572068 kb
Host	smart-ed0ce1af-0725-4439-b22f-bcbd55915c28
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853929679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.3853929679
Directory	/workspace/83.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.1656862879
Short name	T2116
Test name
Test status
Simulation time	157686409 ps
CPU time	19.64 seconds
Started	May 23 04:37:58 PM PDT 24
Finished	May 23 04:38:19 PM PDT 24
Peak memory	571812 kb
Host	smart-b0270238-cd12-45c2-950f-034267775f19
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656862879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.1656862879
Directory	/workspace/83.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_error_random.1361363538
Short name	T2713
Test name
Test status
Simulation time	300647768 ps
CPU time	29.49 seconds
Started	May 23 04:38:00 PM PDT 24
Finished	May 23 04:38:31 PM PDT 24
Peak memory	571788 kb
Host	smart-182b802b-ca08-40c4-a1e5-a8ec484c2340
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361363538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.1361363538
Directory	/workspace/83.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_random.3393110148
Short name	T2619
Test name
Test status
Simulation time	1288865272 ps
CPU time	50.61 seconds
Started	May 23 04:37:55 PM PDT 24
Finished	May 23 04:38:47 PM PDT 24
Peak memory	571696 kb
Host	smart-02d5a82a-9969-403d-a583-2dffa1144b45
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393110148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.3393110148
Directory	/workspace/83.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_random_large_delays.4049255179
Short name	T1774
Test name
Test status
Simulation time	12472592419 ps
CPU time	133.15 seconds
Started	May 23 04:37:46 PM PDT 24
Finished	May 23 04:40:02 PM PDT 24
Peak memory	563832 kb
Host	smart-06727f90-c3a2-4610-bb46-93b62f90ed34
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049255179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.4049255179
Directory	/workspace/83.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.3775712620
Short name	T2627
Test name
Test status
Simulation time	47061256554 ps
CPU time	785.53 seconds
Started	May 23 04:37:56 PM PDT 24
Finished	May 23 04:51:03 PM PDT 24
Peak memory	571940 kb
Host	smart-5b5b139b-eb42-4089-9136-4ad9f8f8e91d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775712620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.3775712620
Directory	/workspace/83.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.840688171
Short name	T1521
Test name
Test status
Simulation time	169412490 ps
CPU time	18.02 seconds
Started	May 23 04:37:46 PM PDT 24
Finished	May 23 04:38:06 PM PDT 24
Peak memory	571804 kb
Host	smart-6d32c3c5-03bc-4b9f-9270-e8c5e60d97c3
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840688171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_dela ys.840688171
Directory	/workspace/83.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_same_source.366927212
Short name	T2184
Test name
Test status
Simulation time	2829189583 ps
CPU time	80.2 seconds
Started	May 23 04:37:58 PM PDT 24
Finished	May 23 04:39:19 PM PDT 24
Peak memory	571944 kb
Host	smart-8e697285-e602-4202-80a0-805ab793b85d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366927212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.366927212
Directory	/workspace/83.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke.662749552
Short name	T2102
Test name
Test status
Simulation time	38077523 ps
CPU time	6.05 seconds
Started	May 23 04:37:49 PM PDT 24
Finished	May 23 04:37:56 PM PDT 24
Peak memory	563556 kb
Host	smart-51848bfa-0aa3-4929-ab3b-b53ca072b78a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662749552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.662749552
Directory	/workspace/83.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.2600121974
Short name	T1401
Test name
Test status
Simulation time	9286538582 ps
CPU time	104.09 seconds
Started	May 23 04:37:49 PM PDT 24
Finished	May 23 04:39:35 PM PDT 24
Peak memory	563784 kb
Host	smart-59fbcbed-bf3e-4605-8e3d-2c33278f6b8f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600121974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.2600121974
Directory	/workspace/83.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3998646010
Short name	T1698
Test name
Test status
Simulation time	5309611158 ps
CPU time	93.64 seconds
Started	May 23 04:37:47 PM PDT 24
Finished	May 23 04:39:23 PM PDT 24
Peak memory	563752 kb
Host	smart-2a17b46b-9333-49e6-9ff2-21d882cc5b19
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998646010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3998646010
Directory	/workspace/83.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2052541415
Short name	T2516
Test name
Test status
Simulation time	48846180 ps
CPU time	6.34 seconds
Started	May 23 04:37:47 PM PDT 24
Finished	May 23 04:37:56 PM PDT 24
Peak memory	563556 kb
Host	smart-94df56a2-f62e-4029-8ec5-77ce06988ef1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052541415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.2052541415
Directory	/workspace/83.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all.576351438
Short name	T621
Test name
Test status
Simulation time	3734344128 ps
CPU time	140.68 seconds
Started	May 23 04:37:56 PM PDT 24
Finished	May 23 04:40:18 PM PDT 24
Peak memory	571960 kb
Host	smart-1d6b7a80-c6a9-462c-8a53-cfc6acaf7557
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576351438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.576351438
Directory	/workspace/83.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2618330570
Short name	T1354
Test name
Test status
Simulation time	2195787525 ps
CPU time	185.14 seconds
Started	May 23 04:38:03 PM PDT 24
Finished	May 23 04:41:09 PM PDT 24
Peak memory	572060 kb
Host	smart-6d5dfffc-71e5-4891-ae7a-4af76dbc1607
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618330570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2618330570
Directory	/workspace/83.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2126440362
Short name	T1569
Test name
Test status
Simulation time	2514360125 ps
CPU time	338.41 seconds
Started	May 23 04:37:56 PM PDT 24
Finished	May 23 04:43:36 PM PDT 24
Peak memory	574072 kb
Host	smart-0d616e35-0157-460b-bca8-f75bfa1e47c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126440362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.2126440362
Directory	/workspace/83.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.2462769956
Short name	T2576
Test name
Test status
Simulation time	547915834 ps
CPU time	28.87 seconds
Started	May 23 04:38:00 PM PDT 24
Finished	May 23 04:38:31 PM PDT 24
Peak memory	571872 kb
Host	smart-cfb5b5f5-9b13-4d5e-8f28-13da54924b19
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462769956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.2462769956
Directory	/workspace/83.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_access_same_device.322790731
Short name	T773
Test name
Test status
Simulation time	185443424 ps
CPU time	20.32 seconds
Started	May 23 04:37:56 PM PDT 24
Finished	May 23 04:38:17 PM PDT 24
Peak memory	571692 kb
Host	smart-c873bc1c-332d-4808-837f-4a10d45c358d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322790731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device. 322790731
Directory	/workspace/84.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2561586118
Short name	T1608
Test name
Test status
Simulation time	79693771538 ps
CPU time	1381.56 seconds
Started	May 23 04:38:00 PM PDT 24
Finished	May 23 05:01:04 PM PDT 24
Peak memory	572044 kb
Host	smart-ff3c2e89-ab9c-4b8a-9158-2f788b6ae4d0
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561586118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.2561586118
Directory	/workspace/84.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1247235085
Short name	T2080
Test name
Test status
Simulation time	713424809 ps
CPU time	31.13 seconds
Started	May 23 04:37:58 PM PDT 24
Finished	May 23 04:38:31 PM PDT 24
Peak memory	571800 kb
Host	smart-df746660-cd53-44b7-b1d7-9ed4ecfc4fcb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247235085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.1247235085
Directory	/workspace/84.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_error_random.457833720
Short name	T1263
Test name
Test status
Simulation time	403408042 ps
CPU time	38.82 seconds
Started	May 23 04:38:10 PM PDT 24
Finished	May 23 04:38:50 PM PDT 24
Peak memory	571812 kb
Host	smart-4ef39637-6dab-4064-8139-b8b42ba2a57a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457833720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.457833720
Directory	/workspace/84.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_random.781434902
Short name	T2440
Test name
Test status
Simulation time	1464886170 ps
CPU time	54.57 seconds
Started	May 23 04:37:57 PM PDT 24
Finished	May 23 04:38:52 PM PDT 24
Peak memory	571804 kb
Host	smart-4cac7252-798d-496b-9dae-5200930762bc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781434902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.781434902
Directory	/workspace/84.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_random_large_delays.3874223048
Short name	T1586
Test name
Test status
Simulation time	12645588680 ps
CPU time	145.4 seconds
Started	May 23 04:38:01 PM PDT 24
Finished	May 23 04:40:27 PM PDT 24
Peak memory	563824 kb
Host	smart-da6d0af0-8d33-4099-9b7f-74d21c16e7da
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874223048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.3874223048
Directory	/workspace/84.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3297009331
Short name	T2300
Test name
Test status
Simulation time	54930493742 ps
CPU time	1035.74 seconds
Started	May 23 04:38:03 PM PDT 24
Finished	May 23 04:55:20 PM PDT 24
Peak memory	571996 kb
Host	smart-0d9a1e84-3ddc-41a6-9b22-a94bf07d539f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297009331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3297009331
Directory	/workspace/84.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.752314280
Short name	T1413
Test name
Test status
Simulation time	257967236 ps
CPU time	24.38 seconds
Started	May 23 04:38:10 PM PDT 24
Finished	May 23 04:38:35 PM PDT 24
Peak memory	571812 kb
Host	smart-c98615bf-d697-422c-9313-89609c44d67e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752314280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela ys.752314280
Directory	/workspace/84.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_same_source.926051685
Short name	T1939
Test name
Test status
Simulation time	1811080073 ps
CPU time	58.57 seconds
Started	May 23 04:38:09 PM PDT 24
Finished	May 23 04:39:09 PM PDT 24
Peak memory	571828 kb
Host	smart-36ecb5b5-65de-42b5-9720-5fb581a86be5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926051685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.926051685
Directory	/workspace/84.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke.1083104567
Short name	T2108
Test name
Test status
Simulation time	240189696 ps
CPU time	11.03 seconds
Started	May 23 04:37:59 PM PDT 24
Finished	May 23 04:38:11 PM PDT 24
Peak memory	563500 kb
Host	smart-f71a874a-aa6f-4c46-91d9-560d43ace714
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083104567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.1083104567
Directory	/workspace/84.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2156315377
Short name	T510
Test name
Test status
Simulation time	7429326462 ps
CPU time	83.2 seconds
Started	May 23 04:37:58 PM PDT 24
Finished	May 23 04:39:22 PM PDT 24
Peak memory	563756 kb
Host	smart-33f75c4b-df14-4dee-89f1-f965e4d422b1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156315377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2156315377
Directory	/workspace/84.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.2748148747
Short name	T2009
Test name
Test status
Simulation time	4136384955 ps
CPU time	77.91 seconds
Started	May 23 04:37:58 PM PDT 24
Finished	May 23 04:39:17 PM PDT 24
Peak memory	563764 kb
Host	smart-2a8c4bdc-fc40-436d-aac7-264b3e276fbb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748148747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.2748148747
Directory	/workspace/84.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.2532241835
Short name	T1269
Test name
Test status
Simulation time	53901570 ps
CPU time	7.48 seconds
Started	May 23 04:37:53 PM PDT 24
Finished	May 23 04:38:01 PM PDT 24
Peak memory	563544 kb
Host	smart-d638424c-042a-49df-aa1f-3e0419db135d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532241835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.2532241835
Directory	/workspace/84.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all.4138902119
Short name	T1830
Test name
Test status
Simulation time	2218833532 ps
CPU time	94.61 seconds
Started	May 23 04:38:04 PM PDT 24
Finished	May 23 04:39:40 PM PDT 24
Peak memory	571956 kb
Host	smart-44224d5c-1c53-4799-8ec6-a447e88ccb61
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138902119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.4138902119
Directory	/workspace/84.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.3096885369
Short name	T2363
Test name
Test status
Simulation time	732157610 ps
CPU time	30.09 seconds
Started	May 23 04:37:57 PM PDT 24
Finished	May 23 04:38:28 PM PDT 24
Peak memory	571908 kb
Host	smart-f27b6f50-fd73-4783-895d-8324e41bd0f2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096885369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3096885369
Directory	/workspace/84.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.1758845216
Short name	T2086
Test name
Test status
Simulation time	3552212449 ps
CPU time	315.71 seconds
Started	May 23 04:37:58 PM PDT 24
Finished	May 23 04:43:15 PM PDT 24
Peak memory	572948 kb
Host	smart-7311a59e-085c-4b85-aebc-e29da9214b03
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758845216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.1758845216
Directory	/workspace/84.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.18262854
Short name	T2435
Test name
Test status
Simulation time	7489581 ps
CPU time	11.57 seconds
Started	May 23 04:38:09 PM PDT 24
Finished	May 23 04:38:22 PM PDT 24
Peak memory	563712 kb
Host	smart-e1ed7765-9220-487f-bae8-a0a04d6da327
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18262854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_ with_reset_error.18262854
Directory	/workspace/84.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.723395536
Short name	T1935
Test name
Test status
Simulation time	881645822 ps
CPU time	36.29 seconds
Started	May 23 04:37:58 PM PDT 24
Finished	May 23 04:38:36 PM PDT 24
Peak memory	571892 kb
Host	smart-e14edf36-efd4-4f5d-84b9-9405d092ba6e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723395536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.723395536
Directory	/workspace/84.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_access_same_device.1948376912
Short name	T644
Test name
Test status
Simulation time	1543268323 ps
CPU time	71.18 seconds
Started	May 23 04:38:10 PM PDT 24
Finished	May 23 04:39:22 PM PDT 24
Peak memory	571852 kb
Host	smart-81de1ff4-6153-45ce-8cc2-331e9136d4e8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948376912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .1948376912
Directory	/workspace/85.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3448464393
Short name	T1988
Test name
Test status
Simulation time	68812976416 ps
CPU time	1140.94 seconds
Started	May 23 04:38:16 PM PDT 24
Finished	May 23 04:57:18 PM PDT 24
Peak memory	572056 kb
Host	smart-0c33f56b-c447-4f53-90eb-66168c9627a7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448464393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.3448464393
Directory	/workspace/85.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.639005234
Short name	T1406
Test name
Test status
Simulation time	615443766 ps
CPU time	28.66 seconds
Started	May 23 04:38:12 PM PDT 24
Finished	May 23 04:38:42 PM PDT 24
Peak memory	571844 kb
Host	smart-44d2461a-8bab-4dfb-8385-6cde697fc5c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639005234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr .639005234
Directory	/workspace/85.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_error_random.4172934543
Short name	T506
Test name
Test status
Simulation time	2333502351 ps
CPU time	89.52 seconds
Started	May 23 04:38:16 PM PDT 24
Finished	May 23 04:39:47 PM PDT 24
Peak memory	571948 kb
Host	smart-7010306f-a7f5-44ad-bcd0-102c50c1bb4b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172934543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.4172934543
Directory	/workspace/85.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_random.3029632606
Short name	T1411
Test name
Test status
Simulation time	139508333 ps
CPU time	17.42 seconds
Started	May 23 04:38:11 PM PDT 24
Finished	May 23 04:38:30 PM PDT 24
Peak memory	571772 kb
Host	smart-8b0a0be9-0a5e-4a55-95c1-34de593b692b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029632606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.3029632606
Directory	/workspace/85.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_random_large_delays.3721645015
Short name	T1962
Test name
Test status
Simulation time	43173381953 ps
CPU time	460.11 seconds
Started	May 23 04:38:15 PM PDT 24
Finished	May 23 04:45:56 PM PDT 24
Peak memory	572052 kb
Host	smart-914e4945-ce7c-434e-aeb2-08d656c87929
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721645015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.3721645015
Directory	/workspace/85.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.2274692868
Short name	T1794
Test name
Test status
Simulation time	34186688499 ps
CPU time	553.77 seconds
Started	May 23 04:38:14 PM PDT 24
Finished	May 23 04:47:29 PM PDT 24
Peak memory	571972 kb
Host	smart-bfd91e14-9af9-4c1a-9359-3b07c6c2b25d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274692868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.2274692868
Directory	/workspace/85.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3795792946
Short name	T2141
Test name
Test status
Simulation time	219323750 ps
CPU time	23.97 seconds
Started	May 23 04:38:13 PM PDT 24
Finished	May 23 04:38:38 PM PDT 24
Peak memory	571788 kb
Host	smart-5f2b6a7d-0a88-4003-8735-89dcdc3a15da
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795792946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.3795792946
Directory	/workspace/85.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_same_source.640537216
Short name	T2437
Test name
Test status
Simulation time	126435152 ps
CPU time	12.13 seconds
Started	May 23 04:38:23 PM PDT 24
Finished	May 23 04:38:36 PM PDT 24
Peak memory	571864 kb
Host	smart-c076b0b6-6034-481a-a24e-7d70ec69e973
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640537216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.640537216
Directory	/workspace/85.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke.2329471576
Short name	T1967
Test name
Test status
Simulation time	42298768 ps
CPU time	6.52 seconds
Started	May 23 04:38:10 PM PDT 24
Finished	May 23 04:38:17 PM PDT 24
Peak memory	563548 kb
Host	smart-eb0fdd0b-ae0d-41f5-b332-c36eab876166
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329471576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.2329471576
Directory	/workspace/85.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2531952519
Short name	T2391
Test name
Test status
Simulation time	9732710855 ps
CPU time	110.62 seconds
Started	May 23 04:38:11 PM PDT 24
Finished	May 23 04:40:03 PM PDT 24
Peak memory	563756 kb
Host	smart-3b394e20-03de-45e9-bbd2-eb61739ceaf4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531952519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2531952519
Directory	/workspace/85.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.3020568043
Short name	T2228
Test name
Test status
Simulation time	6331768663 ps
CPU time	110.36 seconds
Started	May 23 04:38:14 PM PDT 24
Finished	May 23 04:40:06 PM PDT 24
Peak memory	563720 kb
Host	smart-38e1c53e-3c0e-45b4-b256-03628d01519c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020568043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.3020568043
Directory	/workspace/85.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2079262320
Short name	T2308
Test name
Test status
Simulation time	43159728 ps
CPU time	6.46 seconds
Started	May 23 04:37:56 PM PDT 24
Finished	May 23 04:38:03 PM PDT 24
Peak memory	563528 kb
Host	smart-768c4842-9bba-4654-b49e-fbfae66176cd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079262320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.2079262320
Directory	/workspace/85.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all.335705721
Short name	T2212
Test name
Test status
Simulation time	10304024292 ps
CPU time	409.75 seconds
Started	May 23 04:38:11 PM PDT 24
Finished	May 23 04:45:01 PM PDT 24
Peak memory	573040 kb
Host	smart-f6130876-2687-4b8e-85af-8c0638ecdb11
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335705721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.335705721
Directory	/workspace/85.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.1885340146
Short name	T1331
Test name
Test status
Simulation time	1750783848 ps
CPU time	145.99 seconds
Started	May 23 04:38:11 PM PDT 24
Finished	May 23 04:40:38 PM PDT 24
Peak memory	571884 kb
Host	smart-2003f647-1f5e-43ec-ad5e-87d681cb2d97
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885340146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.1885340146
Directory	/workspace/85.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3800789878
Short name	T2456
Test name
Test status
Simulation time	11384419209 ps
CPU time	607.29 seconds
Started	May 23 04:38:11 PM PDT 24
Finished	May 23 04:48:20 PM PDT 24
Peak memory	573052 kb
Host	smart-9e367b98-d257-4c45-9941-c56d0f98eb32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800789878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.3800789878
Directory	/workspace/85.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3465539695
Short name	T1859
Test name
Test status
Simulation time	2262393779 ps
CPU time	249.48 seconds
Started	May 23 04:38:15 PM PDT 24
Finished	May 23 04:42:26 PM PDT 24
Peak memory	573108 kb
Host	smart-14afeaa4-da5f-4ff2-a5d6-7aa6a72f9911
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465539695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.3465539695
Directory	/workspace/85.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3909796504
Short name	T2748
Test name
Test status
Simulation time	214383078 ps
CPU time	26.51 seconds
Started	May 23 04:38:16 PM PDT 24
Finished	May 23 04:38:44 PM PDT 24
Peak memory	571856 kb
Host	smart-9d39ba6c-0063-4482-a140-b7ecb9fc97b7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909796504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3909796504
Directory	/workspace/85.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_access_same_device.2208378426
Short name	T1633
Test name
Test status
Simulation time	1919176327 ps
CPU time	87.83 seconds
Started	May 23 04:38:11 PM PDT 24
Finished	May 23 04:39:40 PM PDT 24
Peak memory	571796 kb
Host	smart-f056a1b7-e2de-44ac-8277-7df49150674b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208378426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .2208378426
Directory	/workspace/86.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3335463466
Short name	T2761
Test name
Test status
Simulation time	87870079620 ps
CPU time	1547.57 seconds
Started	May 23 04:38:24 PM PDT 24
Finished	May 23 05:04:13 PM PDT 24
Peak memory	572032 kb
Host	smart-9c556203-ada3-4bae-a00d-1cfe90e617c6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335463466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.3335463466
Directory	/workspace/86.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1265081065
Short name	T2454
Test name
Test status
Simulation time	774730386 ps
CPU time	34.2 seconds
Started	May 23 04:38:22 PM PDT 24
Finished	May 23 04:38:57 PM PDT 24
Peak memory	571792 kb
Host	smart-beb46e69-a36d-44d8-8540-dd13bd99bba4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265081065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.1265081065
Directory	/workspace/86.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_error_random.2556228370
Short name	T2030
Test name
Test status
Simulation time	1124756100 ps
CPU time	37.02 seconds
Started	May 23 04:38:34 PM PDT 24
Finished	May 23 04:39:13 PM PDT 24
Peak memory	571792 kb
Host	smart-8eb9b922-6e46-431f-8fc9-fa8bad8df4fb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556228370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2556228370
Directory	/workspace/86.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_random.429368363
Short name	T1833
Test name
Test status
Simulation time	149084041 ps
CPU time	14.18 seconds
Started	May 23 04:38:23 PM PDT 24
Finished	May 23 04:38:38 PM PDT 24
Peak memory	571796 kb
Host	smart-4124fd48-649e-46c9-8db7-c72f461f18ac
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429368363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.429368363
Directory	/workspace/86.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_random_large_delays.4058833516
Short name	T1487
Test name
Test status
Simulation time	54282589435 ps
CPU time	615.83 seconds
Started	May 23 04:38:23 PM PDT 24
Finished	May 23 04:48:40 PM PDT 24
Peak memory	572068 kb
Host	smart-b5281f0d-29c0-4707-8ff6-823044e4a1c4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058833516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.4058833516
Directory	/workspace/86.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.3536395692
Short name	T616
Test name
Test status
Simulation time	45737186655 ps
CPU time	825.91 seconds
Started	May 23 04:38:12 PM PDT 24
Finished	May 23 04:51:59 PM PDT 24
Peak memory	572044 kb
Host	smart-d20732a7-3050-4230-9637-1d60a4bd6b10
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536395692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.3536395692
Directory	/workspace/86.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.1162924174
Short name	T2315
Test name
Test status
Simulation time	560452949 ps
CPU time	52.39 seconds
Started	May 23 04:38:14 PM PDT 24
Finished	May 23 04:39:07 PM PDT 24
Peak memory	571788 kb
Host	smart-a39b3220-9439-4bd3-ba0d-6233d81c8ed5
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162924174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.1162924174
Directory	/workspace/86.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_same_source.235374999
Short name	T2495
Test name
Test status
Simulation time	1810541031 ps
CPU time	59.71 seconds
Started	May 23 04:38:35 PM PDT 24
Finished	May 23 04:39:36 PM PDT 24
Peak memory	571836 kb
Host	smart-dca8a545-b4a4-47af-ac13-93a1a329635c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235374999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.235374999
Directory	/workspace/86.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke.3623723362
Short name	T583
Test name
Test status
Simulation time	236543513 ps
CPU time	11.01 seconds
Started	May 23 04:38:14 PM PDT 24
Finished	May 23 04:38:26 PM PDT 24
Peak memory	563544 kb
Host	smart-145dd141-d7e0-41b8-a075-ad065e329873
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623723362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.3623723362
Directory	/workspace/86.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.2385492292
Short name	T1667
Test name
Test status
Simulation time	6972056406 ps
CPU time	76.69 seconds
Started	May 23 04:38:11 PM PDT 24
Finished	May 23 04:39:29 PM PDT 24
Peak memory	563744 kb
Host	smart-991d25a7-8245-42e7-986f-fa5357e72810
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385492292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.2385492292
Directory	/workspace/86.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1399878488
Short name	T508
Test name
Test status
Simulation time	6077408588 ps
CPU time	111.75 seconds
Started	May 23 04:38:11 PM PDT 24
Finished	May 23 04:40:03 PM PDT 24
Peak memory	563804 kb
Host	smart-ebb6cf44-55f9-4e8a-b25a-81bd36f06aa4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399878488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1399878488
Directory	/workspace/86.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2033235482
Short name	T2163
Test name
Test status
Simulation time	51936450 ps
CPU time	6.82 seconds
Started	May 23 04:38:17 PM PDT 24
Finished	May 23 04:38:25 PM PDT 24
Peak memory	563568 kb
Host	smart-9f2a13d2-5734-4fd4-9edf-10a19bf8ff5e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033235482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.2033235482
Directory	/workspace/86.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all.1964536660
Short name	T2484
Test name
Test status
Simulation time	4238875296 ps
CPU time	341.08 seconds
Started	May 23 04:38:23 PM PDT 24
Finished	May 23 04:44:05 PM PDT 24
Peak memory	573084 kb
Host	smart-3cf1a9b7-ab54-4d23-8385-6a0fd92f7bbf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964536660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.1964536660
Directory	/workspace/86.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3586592878
Short name	T1851
Test name
Test status
Simulation time	3510855617 ps
CPU time	116.87 seconds
Started	May 23 04:38:34 PM PDT 24
Finished	May 23 04:40:33 PM PDT 24
Peak memory	572036 kb
Host	smart-1096cafa-69ab-415a-98ac-d5ffb1fac569
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586592878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.3586592878
Directory	/workspace/86.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2582828719
Short name	T1655
Test name
Test status
Simulation time	7893314 ps
CPU time	8.1 seconds
Started	May 23 04:38:34 PM PDT 24
Finished	May 23 04:38:44 PM PDT 24
Peak memory	563624 kb
Host	smart-3caaef2b-e91a-48a7-97ef-feaba7503840
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582828719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.2582828719
Directory	/workspace/86.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1302794490
Short name	T1538
Test name
Test status
Simulation time	9708218839 ps
CPU time	472.8 seconds
Started	May 23 04:38:35 PM PDT 24
Finished	May 23 04:46:29 PM PDT 24
Peak memory	574140 kb
Host	smart-a56adebf-7b7f-402d-80b0-b514257546c9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302794490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.1302794490
Directory	/workspace/86.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.2851091474
Short name	T2599
Test name
Test status
Simulation time	168350956 ps
CPU time	20.71 seconds
Started	May 23 04:38:22 PM PDT 24
Finished	May 23 04:38:44 PM PDT 24
Peak memory	571892 kb
Host	smart-7d3f2b0e-749d-4f94-9d1b-3d8550bdbed8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851091474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.2851091474
Directory	/workspace/86.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_access_same_device.2704571914
Short name	T1438
Test name
Test status
Simulation time	1968397275 ps
CPU time	91.39 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:40:10 PM PDT 24
Peak memory	571876 kb
Host	smart-9be7a7e8-0016-4142-a990-d7dafab6fc0a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704571914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .2704571914
Directory	/workspace/87.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2117933065
Short name	T1527
Test name
Test status
Simulation time	41153080093 ps
CPU time	706.33 seconds
Started	May 23 04:38:38 PM PDT 24
Finished	May 23 04:50:27 PM PDT 24
Peak memory	572072 kb
Host	smart-4d7d91bf-be06-463f-a2ae-f7d6706710bb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117933065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.2117933065
Directory	/workspace/87.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1722543627
Short name	T2635
Test name
Test status
Simulation time	282704714 ps
CPU time	33.03 seconds
Started	May 23 04:38:37 PM PDT 24
Finished	May 23 04:39:12 PM PDT 24
Peak memory	571788 kb
Host	smart-acd524f2-ae6a-4383-9d7c-23fb6f5565fe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722543627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.1722543627
Directory	/workspace/87.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_error_random.2589833907
Short name	T2617
Test name
Test status
Simulation time	2166085482 ps
CPU time	77.28 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:39:56 PM PDT 24
Peak memory	571908 kb
Host	smart-1bbdef7b-e3c5-47ee-b2e3-dfea48ddd513
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589833907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.2589833907
Directory	/workspace/87.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_random.2464916061
Short name	T2564
Test name
Test status
Simulation time	365394333 ps
CPU time	36.9 seconds
Started	May 23 04:38:22 PM PDT 24
Finished	May 23 04:39:00 PM PDT 24
Peak memory	571824 kb
Host	smart-583c2b06-55a4-464f-867e-f1dc5d13edbb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464916061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.2464916061
Directory	/workspace/87.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2240084199
Short name	T2248
Test name
Test status
Simulation time	77000075501 ps
CPU time	834.95 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:52:33 PM PDT 24
Peak memory	572060 kb
Host	smart-f6d61c13-a4ce-4a75-965e-7d4466edf7dc
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240084199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.2240084199
Directory	/workspace/87.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.1640748117
Short name	T2666
Test name
Test status
Simulation time	8986646725 ps
CPU time	167.83 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:41:26 PM PDT 24
Peak memory	572004 kb
Host	smart-657a3d51-d0e9-4eb8-b953-b0e5e57aa7e9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640748117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.1640748117
Directory	/workspace/87.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.2335570922
Short name	T578
Test name
Test status
Simulation time	408630115 ps
CPU time	46.02 seconds
Started	May 23 04:38:23 PM PDT 24
Finished	May 23 04:39:11 PM PDT 24
Peak memory	571788 kb
Host	smart-13a524b7-afec-4274-98cf-a5e9743e9f5c
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335570922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.2335570922
Directory	/workspace/87.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_same_source.193284784
Short name	T1551
Test name
Test status
Simulation time	2217852904 ps
CPU time	72.66 seconds
Started	May 23 04:38:39 PM PDT 24
Finished	May 23 04:39:53 PM PDT 24
Peak memory	571892 kb
Host	smart-81cbc5a6-df9b-4adc-a022-eae9c1ae640f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193284784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.193284784
Directory	/workspace/87.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke.2087381317
Short name	T513
Test name
Test status
Simulation time	150942228 ps
CPU time	7.38 seconds
Started	May 23 04:38:22 PM PDT 24
Finished	May 23 04:38:30 PM PDT 24
Peak memory	563536 kb
Host	smart-81f5b4f4-9869-49d8-8fe3-1d6b5ac23298
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087381317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2087381317
Directory	/workspace/87.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.3599046061
Short name	T1673
Test name
Test status
Simulation time	7451447470 ps
CPU time	82.26 seconds
Started	May 23 04:38:22 PM PDT 24
Finished	May 23 04:39:45 PM PDT 24
Peak memory	563800 kb
Host	smart-6e8e74d2-762a-44e4-bed5-884b16913296
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599046061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.3599046061
Directory	/workspace/87.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1905749084
Short name	T1289
Test name
Test status
Simulation time	5351402065 ps
CPU time	94.35 seconds
Started	May 23 04:38:23 PM PDT 24
Finished	May 23 04:39:59 PM PDT 24
Peak memory	563760 kb
Host	smart-aa9ba5d9-bde4-4995-970b-c3d916257b7a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905749084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.1905749084
Directory	/workspace/87.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.1391583099
Short name	T2572
Test name
Test status
Simulation time	37548841 ps
CPU time	6.37 seconds
Started	May 23 04:38:23 PM PDT 24
Finished	May 23 04:38:31 PM PDT 24
Peak memory	563460 kb
Host	smart-12c101df-c3af-4e0f-bfb0-2d67d11f0c02
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391583099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.1391583099
Directory	/workspace/87.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all.1782614649
Short name	T1583
Test name
Test status
Simulation time	6294819 ps
CPU time	3.85 seconds
Started	May 23 04:38:37 PM PDT 24
Finished	May 23 04:38:43 PM PDT 24
Peak memory	555236 kb
Host	smart-6815044e-3443-4333-b818-b8c7488143b6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782614649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.1782614649
Directory	/workspace/87.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.4205045939
Short name	T1679
Test name
Test status
Simulation time	8047973917 ps
CPU time	305.73 seconds
Started	May 23 04:38:37 PM PDT 24
Finished	May 23 04:43:45 PM PDT 24
Peak memory	572180 kb
Host	smart-debb3c42-f893-448f-b5ec-1051a842d5f9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205045939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.4205045939
Directory	/workspace/87.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1268315432
Short name	T1600
Test name
Test status
Simulation time	7077206 ps
CPU time	23.46 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:39:02 PM PDT 24
Peak memory	563648 kb
Host	smart-5bab83ae-db30-49a6-9f77-d209e2d13649
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268315432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.1268315432
Directory	/workspace/87.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1391757824
Short name	T651
Test name
Test status
Simulation time	4731135449 ps
CPU time	491.9 seconds
Started	May 23 04:38:38 PM PDT 24
Finished	May 23 04:46:53 PM PDT 24
Peak memory	573100 kb
Host	smart-3bc5c759-454f-4e45-850c-9ff241389cda
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391757824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.1391757824
Directory	/workspace/87.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.3158093008
Short name	T2591
Test name
Test status
Simulation time	386000859 ps
CPU time	19.53 seconds
Started	May 23 04:38:39 PM PDT 24
Finished	May 23 04:39:01 PM PDT 24
Peak memory	571812 kb
Host	smart-6e6ee147-2284-4e7a-ba57-9afb91653cdb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158093008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.3158093008
Directory	/workspace/87.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_access_same_device.3084828530
Short name	T2416
Test name
Test status
Simulation time	413299079 ps
CPU time	25.3 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:39:04 PM PDT 24
Peak memory	571832 kb
Host	smart-4eb1d7fb-a645-4283-9c92-1b169673cf4c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084828530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .3084828530
Directory	/workspace/88.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2234378282
Short name	T1999
Test name
Test status
Simulation time	151257216922 ps
CPU time	2540.08 seconds
Started	May 23 04:38:37 PM PDT 24
Finished	May 23 05:21:00 PM PDT 24
Peak memory	572000 kb
Host	smart-e5a413d0-08b2-4da9-acf4-2b13d42d4aaf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234378282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.2234378282
Directory	/workspace/88.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.127868508
Short name	T1449
Test name
Test status
Simulation time	18454109 ps
CPU time	5.6 seconds
Started	May 23 04:38:41 PM PDT 24
Finished	May 23 04:38:48 PM PDT 24
Peak memory	563492 kb
Host	smart-3cfaadd3-6a9e-4f46-ba1f-29cfcc63e01d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127868508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr .127868508
Directory	/workspace/88.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_error_random.3117597186
Short name	T1994
Test name
Test status
Simulation time	55808728 ps
CPU time	7.91 seconds
Started	May 23 04:38:38 PM PDT 24
Finished	May 23 04:38:49 PM PDT 24
Peak memory	563528 kb
Host	smart-5b9945dc-f73d-41a5-904d-57e0da9bc3e9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117597186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.3117597186
Directory	/workspace/88.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_random.3846653142
Short name	T1756
Test name
Test status
Simulation time	212813119 ps
CPU time	23.75 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:39:02 PM PDT 24
Peak memory	571820 kb
Host	smart-e7a8cea6-2acd-4813-a900-0a435938df83
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846653142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.3846653142
Directory	/workspace/88.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_random_large_delays.3997536929
Short name	T1373
Test name
Test status
Simulation time	81494611662 ps
CPU time	845.25 seconds
Started	May 23 04:38:37 PM PDT 24
Finished	May 23 04:52:45 PM PDT 24
Peak memory	572080 kb
Host	smart-5babe299-e46d-4642-9c6c-954fd882df11
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997536929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.3997536929
Directory	/workspace/88.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.354975397
Short name	T1529
Test name
Test status
Simulation time	67599889317 ps
CPU time	1216.45 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:58:55 PM PDT 24
Peak memory	571988 kb
Host	smart-ea1216c3-13b2-41c4-a16f-d6928b02e408
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354975397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.354975397
Directory	/workspace/88.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1909988489
Short name	T1783
Test name
Test status
Simulation time	44021487 ps
CPU time	6.81 seconds
Started	May 23 04:38:37 PM PDT 24
Finished	May 23 04:38:47 PM PDT 24
Peak memory	563552 kb
Host	smart-0de7ef64-4556-4f63-b1cc-0d013474cd93
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909988489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.1909988489
Directory	/workspace/88.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_same_source.260244664
Short name	T2317
Test name
Test status
Simulation time	447667427 ps
CPU time	31.08 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:39:09 PM PDT 24
Peak memory	571808 kb
Host	smart-3ed88ece-ee94-4bd8-a065-a5684de193b5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260244664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.260244664
Directory	/workspace/88.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke.1415931006
Short name	T1429
Test name
Test status
Simulation time	225672150 ps
CPU time	10.77 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:38:48 PM PDT 24
Peak memory	563536 kb
Host	smart-7b45bf5e-9554-47f6-ab69-b01d16f5fe6b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415931006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.1415931006
Directory	/workspace/88.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.3197844993
Short name	T2548
Test name
Test status
Simulation time	8147438694 ps
CPU time	91.13 seconds
Started	May 23 04:38:39 PM PDT 24
Finished	May 23 04:40:12 PM PDT 24
Peak memory	563780 kb
Host	smart-8f38f0dd-a6b7-4d04-8238-9f26baa7f789
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197844993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.3197844993
Directory	/workspace/88.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3881203730
Short name	T1403
Test name
Test status
Simulation time	5138436598 ps
CPU time	89.78 seconds
Started	May 23 04:38:39 PM PDT 24
Finished	May 23 04:40:11 PM PDT 24
Peak memory	563772 kb
Host	smart-1f6a7b0c-c673-48b9-8fff-242ff942acaa
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881203730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3881203730
Directory	/workspace/88.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.4191659603
Short name	T2147
Test name
Test status
Simulation time	41735587 ps
CPU time	6 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:38:44 PM PDT 24
Peak memory	563524 kb
Host	smart-44b2bb2a-9fb2-49b5-bc6c-dfc1ef06e06e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191659603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.4191659603
Directory	/workspace/88.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all.1261884753
Short name	T479
Test name
Test status
Simulation time	2651158845 ps
CPU time	238.35 seconds
Started	May 23 04:38:39 PM PDT 24
Finished	May 23 04:42:39 PM PDT 24
Peak memory	572564 kb
Host	smart-99d567cf-76e2-4574-a393-a4947961f048
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261884753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.1261884753
Directory	/workspace/88.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.3199863675
Short name	T1666
Test name
Test status
Simulation time	2181982478 ps
CPU time	85.53 seconds
Started	May 23 04:38:50 PM PDT 24
Finished	May 23 04:40:17 PM PDT 24
Peak memory	571964 kb
Host	smart-9cfd2e9f-a5ba-4a70-b58e-957062b900bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199863675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.3199863675
Directory	/workspace/88.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1355076024
Short name	T1747
Test name
Test status
Simulation time	397308817 ps
CPU time	220.65 seconds
Started	May 23 04:38:36 PM PDT 24
Finished	May 23 04:42:19 PM PDT 24
Peak memory	573724 kb
Host	smart-6b6e86c0-5478-46db-98a2-870d99a1d37c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355076024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.1355076024
Directory	/workspace/88.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1849772106
Short name	T2774
Test name
Test status
Simulation time	586484586 ps
CPU time	174.39 seconds
Started	May 23 04:38:50 PM PDT 24
Finished	May 23 04:41:46 PM PDT 24
Peak memory	574036 kb
Host	smart-5ad2f07c-e963-4e0d-ada6-6d42c018f522
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849772106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.1849772106
Directory	/workspace/88.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.4046332238
Short name	T1505
Test name
Test status
Simulation time	849375887 ps
CPU time	41.5 seconds
Started	May 23 04:38:37 PM PDT 24
Finished	May 23 04:39:21 PM PDT 24
Peak memory	571844 kb
Host	smart-37e8d1e5-5021-4649-991e-93d191eb36de
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046332238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.4046332238
Directory	/workspace/88.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_access_same_device.3275234648
Short name	T1593
Test name
Test status
Simulation time	1849356969 ps
CPU time	89.06 seconds
Started	May 23 04:38:52 PM PDT 24
Finished	May 23 04:40:22 PM PDT 24
Peak memory	571872 kb
Host	smart-93907219-5d4c-439b-ab82-fd8ce37fc441
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275234648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .3275234648
Directory	/workspace/89.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.891849005
Short name	T2511
Test name
Test status
Simulation time	104724464508 ps
CPU time	1694.77 seconds
Started	May 23 04:38:52 PM PDT 24
Finished	May 23 05:07:08 PM PDT 24
Peak memory	572068 kb
Host	smart-a219e9a7-7651-4355-985c-b0388e867a4b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891849005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d evice_slow_rsp.891849005
Directory	/workspace/89.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2624252898
Short name	T1819
Test name
Test status
Simulation time	413097713 ps
CPU time	20.83 seconds
Started	May 23 04:38:51 PM PDT 24
Finished	May 23 04:39:13 PM PDT 24
Peak memory	571772 kb
Host	smart-f2267ce0-ceb1-4a5d-b0eb-ab3abefa1edb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624252898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.2624252898
Directory	/workspace/89.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_error_random.1674024702
Short name	T1735
Test name
Test status
Simulation time	2663888357 ps
CPU time	106.62 seconds
Started	May 23 04:38:52 PM PDT 24
Finished	May 23 04:40:40 PM PDT 24
Peak memory	571964 kb
Host	smart-77c9689b-ff0c-4ab8-b2ad-79268a09262b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674024702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1674024702
Directory	/workspace/89.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_random.894738226
Short name	T2067
Test name
Test status
Simulation time	1358369864 ps
CPU time	48.23 seconds
Started	May 23 04:38:49 PM PDT 24
Finished	May 23 04:39:38 PM PDT 24
Peak memory	571840 kb
Host	smart-127ca9dd-0a5e-49c5-b516-6096afe055f8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894738226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.894738226
Directory	/workspace/89.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_random_large_delays.2124215536
Short name	T1430
Test name
Test status
Simulation time	74142483366 ps
CPU time	798 seconds
Started	May 23 04:38:49 PM PDT 24
Finished	May 23 04:52:09 PM PDT 24
Peak memory	572044 kb
Host	smart-00825224-4406-460c-8558-97e92f72f310
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124215536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.2124215536
Directory	/workspace/89.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.2693569557
Short name	T2247
Test name
Test status
Simulation time	7571409499 ps
CPU time	129.41 seconds
Started	May 23 04:38:53 PM PDT 24
Finished	May 23 04:41:03 PM PDT 24
Peak memory	563896 kb
Host	smart-09577dda-bb97-4e21-861c-fb3befb67ade
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693569557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.2693569557
Directory	/workspace/89.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.45088306
Short name	T579
Test name
Test status
Simulation time	392848576 ps
CPU time	38.4 seconds
Started	May 23 04:38:52 PM PDT 24
Finished	May 23 04:39:32 PM PDT 24
Peak memory	571808 kb
Host	smart-f168b148-7bec-4d8f-96b0-5c4497c0243e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45088306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_delay s.45088306
Directory	/workspace/89.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_same_source.1786392925
Short name	T1399
Test name
Test status
Simulation time	467316432 ps
CPU time	39.09 seconds
Started	May 23 04:38:51 PM PDT 24
Finished	May 23 04:39:31 PM PDT 24
Peak memory	571804 kb
Host	smart-e347a6ac-eea5-4829-b9ce-558743c4245b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786392925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.1786392925
Directory	/workspace/89.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke.522930096
Short name	T2263
Test name
Test status
Simulation time	192229630 ps
CPU time	8.31 seconds
Started	May 23 04:38:51 PM PDT 24
Finished	May 23 04:39:00 PM PDT 24
Peak memory	563564 kb
Host	smart-b76085cb-acad-425e-b1c2-4a975197b708
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522930096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.522930096
Directory	/workspace/89.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.2065278436
Short name	T1557
Test name
Test status
Simulation time	8574624788 ps
CPU time	87.56 seconds
Started	May 23 04:38:49 PM PDT 24
Finished	May 23 04:40:18 PM PDT 24
Peak memory	563720 kb
Host	smart-5f62dbbf-f3d9-4a9e-861c-3c241e5d4e9c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065278436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.2065278436
Directory	/workspace/89.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3815695586
Short name	T2557
Test name
Test status
Simulation time	5651417617 ps
CPU time	100.95 seconds
Started	May 23 04:38:49 PM PDT 24
Finished	May 23 04:40:32 PM PDT 24
Peak memory	563768 kb
Host	smart-cd403727-956c-4ea9-94b6-3944494776c9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815695586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3815695586
Directory	/workspace/89.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1688600401
Short name	T536
Test name
Test status
Simulation time	52178081 ps
CPU time	6.73 seconds
Started	May 23 04:38:52 PM PDT 24
Finished	May 23 04:39:00 PM PDT 24
Peak memory	563528 kb
Host	smart-b322b507-abc2-4772-aa7a-f3a8afe6546a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688600401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.1688600401
Directory	/workspace/89.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all.340086089
Short name	T402
Test name
Test status
Simulation time	1944444865 ps
CPU time	153.42 seconds
Started	May 23 04:38:51 PM PDT 24
Finished	May 23 04:41:26 PM PDT 24
Peak memory	571924 kb
Host	smart-91c1ee24-01fd-4fe1-a4a4-6df173f41f94
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340086089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.340086089
Directory	/workspace/89.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.1452439704
Short name	T1676
Test name
Test status
Simulation time	8560815185 ps
CPU time	318.12 seconds
Started	May 23 04:38:49 PM PDT 24
Finished	May 23 04:44:09 PM PDT 24
Peak memory	571996 kb
Host	smart-48529641-1cff-478b-80f7-f18715f18e18
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452439704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.1452439704
Directory	/workspace/89.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.3359694722
Short name	T815
Test name
Test status
Simulation time	487739151 ps
CPU time	214.59 seconds
Started	May 23 04:38:51 PM PDT 24
Finished	May 23 04:42:27 PM PDT 24
Peak memory	572780 kb
Host	smart-6c272cb9-bd32-4bfd-bba4-7bdddc1874ae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359694722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.3359694722
Directory	/workspace/89.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1190871674
Short name	T1470
Test name
Test status
Simulation time	850519029 ps
CPU time	38.46 seconds
Started	May 23 04:38:52 PM PDT 24
Finished	May 23 04:39:32 PM PDT 24
Peak memory	571900 kb
Host	smart-88cc9245-3209-47d3-b342-2c63e239a958
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190871674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1190871674
Directory	/workspace/89.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/9.chip_tl_errors.875622316
Short name	T563
Test name
Test status
Simulation time	3435659740 ps
CPU time	325.76 seconds
Started	May 23 04:22:56 PM PDT 24
Finished	May 23 04:28:23 PM PDT 24
Peak memory	586196 kb
Host	smart-407dfc20-821b-4409-b6da-94b050d430af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875622316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.875622316
Directory	/workspace/9.chip_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_access_same_device.1326890733
Short name	T2562
Test name
Test status
Simulation time	2197649752 ps
CPU time	105.18 seconds
Started	May 23 04:23:04 PM PDT 24
Finished	May 23 04:24:50 PM PDT 24
Peak memory	571928 kb
Host	smart-802af66c-47e1-41cd-96f8-16771a58e381
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326890733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 1326890733
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2403916570
Short name	T480
Test name
Test status
Simulation time	73904004160 ps
CPU time	1403.39 seconds
Started	May 23 04:22:59 PM PDT 24
Finished	May 23 04:46:23 PM PDT 24
Peak memory	572056 kb
Host	smart-f72ebf48-9f06-41d2-a9b9-ce05e49ccb10
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403916570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2403916570
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3689902402
Short name	T1268
Test name
Test status
Simulation time	1126699057 ps
CPU time	49.77 seconds
Started	May 23 04:23:03 PM PDT 24
Finished	May 23 04:23:53 PM PDT 24
Peak memory	571796 kb
Host	smart-58ed9345-1c6f-41e1-8c1c-8cacaf1c48ea
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689902402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .3689902402
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_error_random.763070046
Short name	T1285
Test name
Test status
Simulation time	2257534237 ps
CPU time	88.64 seconds
Started	May 23 04:22:58 PM PDT 24
Finished	May 23 04:24:28 PM PDT 24
Peak memory	571836 kb
Host	smart-1e998c78-8f78-43a5-a013-16c8c07eb6ef
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763070046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.763070046
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_random.3975112322
Short name	T587
Test name
Test status
Simulation time	1215033815 ps
CPU time	50.34 seconds
Started	May 23 04:23:05 PM PDT 24
Finished	May 23 04:23:57 PM PDT 24
Peak memory	571808 kb
Host	smart-f237074b-fcc8-426f-b407-0d3371e72a9b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975112322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.3975112322
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2766597236
Short name	T2703
Test name
Test status
Simulation time	39440086416 ps
CPU time	480.09 seconds
Started	May 23 04:23:05 PM PDT 24
Finished	May 23 04:31:07 PM PDT 24
Peak memory	572048 kb
Host	smart-76a4a849-445b-4ea5-bbc5-4988cf9332ae
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766597236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2766597236
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.3645405883
Short name	T2537
Test name
Test status
Simulation time	38530852030 ps
CPU time	683.09 seconds
Started	May 23 04:22:59 PM PDT 24
Finished	May 23 04:34:23 PM PDT 24
Peak memory	572000 kb
Host	smart-e5805701-c627-48be-8567-ecc22f990945
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645405883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3645405883
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.178173698
Short name	T1959
Test name
Test status
Simulation time	376176075 ps
CPU time	36.56 seconds
Started	May 23 04:23:07 PM PDT 24
Finished	May 23 04:23:45 PM PDT 24
Peak memory	571812 kb
Host	smart-90c1de50-fd34-4007-a458-c09781e03be1
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178173698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delay s.178173698
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_same_source.2131231464
Short name	T2318
Test name
Test status
Simulation time	139296847 ps
CPU time	13.35 seconds
Started	May 23 04:23:04 PM PDT 24
Finished	May 23 04:23:18 PM PDT 24
Peak memory	571764 kb
Host	smart-e912da51-3224-4dce-b157-23d0476f915f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131231464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2131231464
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke.3872140013
Short name	T1640
Test name
Test status
Simulation time	201232018 ps
CPU time	9.63 seconds
Started	May 23 04:22:48 PM PDT 24
Finished	May 23 04:22:58 PM PDT 24
Peak memory	563548 kb
Host	smart-9e7832ec-c9ee-4bd3-ab2a-fee7f2652bc5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872140013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3872140013
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.3360344657
Short name	T2111
Test name
Test status
Simulation time	6416066231 ps
CPU time	73.68 seconds
Started	May 23 04:22:46 PM PDT 24
Finished	May 23 04:24:01 PM PDT 24
Peak memory	563792 kb
Host	smart-11a9c3a4-b602-4061-806b-3a0e3a46e691
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360344657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3360344657
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1055510265
Short name	T2257
Test name
Test status
Simulation time	4762933577 ps
CPU time	85.07 seconds
Started	May 23 04:23:06 PM PDT 24
Finished	May 23 04:24:32 PM PDT 24
Peak memory	563756 kb
Host	smart-17b55015-6925-480a-96b5-edb0fe83cadf
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055510265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1055510265
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.248536250
Short name	T2138
Test name
Test status
Simulation time	41625490 ps
CPU time	6.48 seconds
Started	May 23 04:22:50 PM PDT 24
Finished	May 23 04:22:58 PM PDT 24
Peak memory	563532 kb
Host	smart-ef099990-d2aa-4c94-9b1d-95ca806a93bb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248536250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays. 248536250
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all.3924282809
Short name	T455
Test name
Test status
Simulation time	15241575419 ps
CPU time	632.52 seconds
Started	May 23 04:22:58 PM PDT 24
Finished	May 23 04:33:31 PM PDT 24
Peak memory	573076 kb
Host	smart-429081ad-693b-4aa9-a2e7-fb5807d7be20
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924282809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3924282809
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.839916603
Short name	T1722
Test name
Test status
Simulation time	2561729529 ps
CPU time	109.91 seconds
Started	May 23 04:23:19 PM PDT 24
Finished	May 23 04:25:09 PM PDT 24
Peak memory	572012 kb
Host	smart-9cd163cc-5e0c-420a-97c7-3e5ecfe7c81c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839916603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.839916603
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2334503512
Short name	T2645
Test name
Test status
Simulation time	15154300502 ps
CPU time	786.82 seconds
Started	May 23 04:23:11 PM PDT 24
Finished	May 23 04:36:19 PM PDT 24
Peak memory	573064 kb
Host	smart-2504400e-b79d-4fc1-8f50-18bf0e0efeb9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334503512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.2334503512
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.291133971
Short name	T2037
Test name
Test status
Simulation time	9722673992 ps
CPU time	563.42 seconds
Started	May 23 04:23:10 PM PDT 24
Finished	May 23 04:32:34 PM PDT 24
Peak memory	573080 kb
Host	smart-a3e0adab-b8b0-426b-89bd-18ec41c7f8f2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291133971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.291133971
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.2765451882
Short name	T2274
Test name
Test status
Simulation time	196865649 ps
CPU time	24.29 seconds
Started	May 23 04:23:06 PM PDT 24
Finished	May 23 04:23:31 PM PDT 24
Peak memory	571792 kb
Host	smart-e4dc8d83-65f0-4de2-aed8-d546160793bf
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765451882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2765451882
Directory	/workspace/9.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_access_same_device.810662311
Short name	T1831
Test name
Test status
Simulation time	143878999 ps
CPU time	9.06 seconds
Started	May 23 04:39:05 PM PDT 24
Finished	May 23 04:39:16 PM PDT 24
Peak memory	563620 kb
Host	smart-6ddd99a0-22ba-49b9-b5f7-acfaf39de708
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810662311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device. 810662311
Directory	/workspace/90.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3680803563
Short name	T1682
Test name
Test status
Simulation time	141340960082 ps
CPU time	2628.95 seconds
Started	May 23 04:39:04 PM PDT 24
Finished	May 23 05:22:55 PM PDT 24
Peak memory	572040 kb
Host	smart-78c2d082-1806-4664-9f0a-8d9438bcfb49
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680803563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.3680803563
Directory	/workspace/90.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.838657457
Short name	T1930
Test name
Test status
Simulation time	1064113082 ps
CPU time	45.13 seconds
Started	May 23 04:39:05 PM PDT 24
Finished	May 23 04:39:52 PM PDT 24
Peak memory	571832 kb
Host	smart-de47ccc0-5213-4713-a0d4-a6039aaeb698
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838657457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr .838657457
Directory	/workspace/90.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_error_random.2922983077
Short name	T2031
Test name
Test status
Simulation time	1570307320 ps
CPU time	53.18 seconds
Started	May 23 04:39:05 PM PDT 24
Finished	May 23 04:40:00 PM PDT 24
Peak memory	571744 kb
Host	smart-33ba53e6-b3c8-486f-85a1-8b7711074727
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922983077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.2922983077
Directory	/workspace/90.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_random.1513992432
Short name	T450
Test name
Test status
Simulation time	1449153993 ps
CPU time	53.38 seconds
Started	May 23 04:39:07 PM PDT 24
Finished	May 23 04:40:02 PM PDT 24
Peak memory	571788 kb
Host	smart-2d6990c4-aa37-4226-a7ce-7b7f9f39ff45
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513992432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.1513992432
Directory	/workspace/90.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3655874804
Short name	T2555
Test name
Test status
Simulation time	92759629124 ps
CPU time	997.17 seconds
Started	May 23 04:39:07 PM PDT 24
Finished	May 23 04:55:46 PM PDT 24
Peak memory	572060 kb
Host	smart-15c88617-ebf8-44c0-bd27-bb04bea1995e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655874804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3655874804
Directory	/workspace/90.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.4155284154
Short name	T571
Test name
Test status
Simulation time	9561822586 ps
CPU time	166.67 seconds
Started	May 23 04:39:03 PM PDT 24
Finished	May 23 04:41:51 PM PDT 24
Peak memory	571988 kb
Host	smart-806c1a12-86b3-43d7-bf42-c2b2f026fcd4
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155284154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.4155284154
Directory	/workspace/90.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1636840991
Short name	T2672
Test name
Test status
Simulation time	482655747 ps
CPU time	40.28 seconds
Started	May 23 04:39:08 PM PDT 24
Finished	May 23 04:39:49 PM PDT 24
Peak memory	571828 kb
Host	smart-bfeae431-03ba-4715-9c7c-8eab7aa1b3dd
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636840991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.1636840991
Directory	/workspace/90.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_same_source.20555388
Short name	T1418
Test name
Test status
Simulation time	432012939 ps
CPU time	40.08 seconds
Started	May 23 04:39:04 PM PDT 24
Finished	May 23 04:39:46 PM PDT 24
Peak memory	571772 kb
Host	smart-4f42a6bc-e62a-4ff2-baa1-7b6af45f5901
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20555388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.20555388
Directory	/workspace/90.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke.642545756
Short name	T1767
Test name
Test status
Simulation time	168579400 ps
CPU time	8.69 seconds
Started	May 23 04:38:53 PM PDT 24
Finished	May 23 04:39:02 PM PDT 24
Peak memory	563548 kb
Host	smart-d6838568-f3a9-4dca-bb95-23e34a6679c7
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642545756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.642545756
Directory	/workspace/90.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2499295452
Short name	T1990
Test name
Test status
Simulation time	8811972003 ps
CPU time	99.82 seconds
Started	May 23 04:38:53 PM PDT 24
Finished	May 23 04:40:34 PM PDT 24
Peak memory	563772 kb
Host	smart-ef38ae15-2420-49ad-ab33-06d686219fea
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499295452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.2499295452
Directory	/workspace/90.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1784789946
Short name	T2538
Test name
Test status
Simulation time	6136131036 ps
CPU time	110.24 seconds
Started	May 23 04:39:02 PM PDT 24
Finished	May 23 04:40:53 PM PDT 24
Peak memory	563784 kb
Host	smart-baa6cc47-21d6-4692-9f59-e8ef26319c0f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784789946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.1784789946
Directory	/workspace/90.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2947463614
Short name	T622
Test name
Test status
Simulation time	49673079 ps
CPU time	6.74 seconds
Started	May 23 04:38:51 PM PDT 24
Finished	May 23 04:38:58 PM PDT 24
Peak memory	563524 kb
Host	smart-06d967f8-5c9e-4c03-8d8a-9f371d26fd1b
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947463614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.2947463614
Directory	/workspace/90.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all.3588052803
Short name	T575
Test name
Test status
Simulation time	1764619033 ps
CPU time	207.26 seconds
Started	May 23 04:39:03 PM PDT 24
Finished	May 23 04:42:31 PM PDT 24
Peak memory	572792 kb
Host	smart-29be81ae-74d3-423c-9c8d-e8b30c5445e5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588052803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.3588052803
Directory	/workspace/90.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.3469053359
Short name	T2405
Test name
Test status
Simulation time	2037703371 ps
CPU time	163.16 seconds
Started	May 23 04:39:05 PM PDT 24
Finished	May 23 04:41:50 PM PDT 24
Peak memory	571932 kb
Host	smart-39f1084c-c336-4953-b4ed-61c20f7a3df2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469053359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.3469053359
Directory	/workspace/90.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.1329970570
Short name	T517
Test name
Test status
Simulation time	4807350984 ps
CPU time	334.16 seconds
Started	May 23 04:39:06 PM PDT 24
Finished	May 23 04:44:42 PM PDT 24
Peak memory	572576 kb
Host	smart-f2848b5f-416d-407d-844d-44506fa33469
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329970570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.1329970570
Directory	/workspace/90.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.106286573
Short name	T2775
Test name
Test status
Simulation time	905753118 ps
CPU time	95.83 seconds
Started	May 23 04:39:02 PM PDT 24
Finished	May 23 04:40:39 PM PDT 24
Peak memory	572728 kb
Host	smart-a2bf677b-e136-4e9e-9cb3-1234fcc54dc5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106286573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_reset_error.106286573
Directory	/workspace/90.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3799307757
Short name	T2722
Test name
Test status
Simulation time	330742340 ps
CPU time	39.35 seconds
Started	May 23 04:39:05 PM PDT 24
Finished	May 23 04:39:46 PM PDT 24
Peak memory	571800 kb
Host	smart-b91c656b-691a-4f99-b461-9b48be68376c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799307757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3799307757
Directory	/workspace/90.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_access_same_device.1576038154
Short name	T2463
Test name
Test status
Simulation time	627821882 ps
CPU time	28.49 seconds
Started	May 23 04:39:08 PM PDT 24
Finished	May 23 04:39:38 PM PDT 24
Peak memory	563564 kb
Host	smart-dcefbf13-69f4-47b0-ada2-2dd60f85dfe2
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576038154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .1576038154
Directory	/workspace/91.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1797032430
Short name	T1424
Test name
Test status
Simulation time	88942747318 ps
CPU time	1507.91 seconds
Started	May 23 04:39:04 PM PDT 24
Finished	May 23 05:04:14 PM PDT 24
Peak memory	572024 kb
Host	smart-f1a6559e-8839-4518-a3ab-6e440a0e03ca
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797032430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.1797032430
Directory	/workspace/91.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1990739445
Short name	T1542
Test name
Test status
Simulation time	149097507 ps
CPU time	8.8 seconds
Started	May 23 04:39:06 PM PDT 24
Finished	May 23 04:39:16 PM PDT 24
Peak memory	563568 kb
Host	smart-f6762b34-4d33-469f-b2e5-232a1daca780
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990739445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.1990739445
Directory	/workspace/91.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_error_random.546424291
Short name	T1781
Test name
Test status
Simulation time	1276584646 ps
CPU time	42.54 seconds
Started	May 23 04:39:07 PM PDT 24
Finished	May 23 04:39:50 PM PDT 24
Peak memory	571840 kb
Host	smart-aa01d84f-5974-49ef-829e-ae5fc52e47bd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546424291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.546424291
Directory	/workspace/91.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_random.2653984845
Short name	T1877
Test name
Test status
Simulation time	148542815 ps
CPU time	16.08 seconds
Started	May 23 04:39:03 PM PDT 24
Finished	May 23 04:39:20 PM PDT 24
Peak memory	571792 kb
Host	smart-b7e078bb-c921-400c-bf84-4833e3fdc6b5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653984845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2653984845
Directory	/workspace/91.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_random_large_delays.592690483
Short name	T476
Test name
Test status
Simulation time	39185022682 ps
CPU time	429.45 seconds
Started	May 23 04:39:05 PM PDT 24
Finished	May 23 04:46:16 PM PDT 24
Peak memory	571964 kb
Host	smart-a334c3c7-ec27-4082-aade-0d74d7da3520
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592690483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.592690483
Directory	/workspace/91.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.2762935658
Short name	T2490
Test name
Test status
Simulation time	33790590217 ps
CPU time	569.85 seconds
Started	May 23 04:39:04 PM PDT 24
Finished	May 23 04:48:36 PM PDT 24
Peak memory	572028 kb
Host	smart-01fad838-6fda-420a-87fb-9e1fda77e08b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762935658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.2762935658
Directory	/workspace/91.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.2658883217
Short name	T1832
Test name
Test status
Simulation time	43572135 ps
CPU time	6.29 seconds
Started	May 23 04:39:02 PM PDT 24
Finished	May 23 04:39:09 PM PDT 24
Peak memory	563576 kb
Host	smart-0374f495-07d1-4c96-b76d-256672a6da69
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658883217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.2658883217
Directory	/workspace/91.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_same_source.3424853890
Short name	T1916
Test name
Test status
Simulation time	1525387657 ps
CPU time	44.51 seconds
Started	May 23 04:39:04 PM PDT 24
Finished	May 23 04:39:50 PM PDT 24
Peak memory	571656 kb
Host	smart-2355e46f-6428-4813-9bc4-fa0038ed734e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424853890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3424853890
Directory	/workspace/91.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke.1154800790
Short name	T2670
Test name
Test status
Simulation time	41480440 ps
CPU time	6.6 seconds
Started	May 23 04:39:05 PM PDT 24
Finished	May 23 04:39:13 PM PDT 24
Peak memory	563532 kb
Host	smart-e8879bfa-341f-4967-9f88-b6590c7ae530
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154800790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.1154800790
Directory	/workspace/91.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.735452031
Short name	T2434
Test name
Test status
Simulation time	8094702168 ps
CPU time	89.82 seconds
Started	May 23 04:39:05 PM PDT 24
Finished	May 23 04:40:37 PM PDT 24
Peak memory	563752 kb
Host	smart-11519b14-ea1c-42dd-bb70-eaff4aa1c8f6
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735452031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.735452031
Directory	/workspace/91.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2634880760
Short name	T1609
Test name
Test status
Simulation time	4794284465 ps
CPU time	83.34 seconds
Started	May 23 04:39:03 PM PDT 24
Finished	May 23 04:40:28 PM PDT 24
Peak memory	563720 kb
Host	smart-1d58e106-8e18-4bea-9e50-b54a4142973b
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634880760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.2634880760
Directory	/workspace/91.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1161310052
Short name	T1913
Test name
Test status
Simulation time	51822147 ps
CPU time	7.37 seconds
Started	May 23 04:39:03 PM PDT 24
Finished	May 23 04:39:11 PM PDT 24
Peak memory	563508 kb
Host	smart-152fc6c9-a5c5-4e2d-8048-f8ae60ed2458
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161310052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.1161310052
Directory	/workspace/91.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all.2036465724
Short name	T2485
Test name
Test status
Simulation time	12048146360 ps
CPU time	417 seconds
Started	May 23 04:39:07 PM PDT 24
Finished	May 23 04:46:05 PM PDT 24
Peak memory	573012 kb
Host	smart-e51d3599-0e26-4e5a-bcd4-ef272782bc77
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036465724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.2036465724
Directory	/workspace/91.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.2644963822
Short name	T2202
Test name
Test status
Simulation time	3361492562 ps
CPU time	123.25 seconds
Started	May 23 04:39:22 PM PDT 24
Finished	May 23 04:41:28 PM PDT 24
Peak memory	571964 kb
Host	smart-619b8808-00f9-400c-9bba-89a823637073
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644963822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.2644963822
Directory	/workspace/91.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.892916962
Short name	T2588
Test name
Test status
Simulation time	460769114 ps
CPU time	187.72 seconds
Started	May 23 04:39:21 PM PDT 24
Finished	May 23 04:42:32 PM PDT 24
Peak memory	572728 kb
Host	smart-50257db2-da87-4f71-b603-1ea4ae5c4608
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892916962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_ with_rand_reset.892916962
Directory	/workspace/91.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3023364130
Short name	T831
Test name
Test status
Simulation time	624168977 ps
CPU time	197.64 seconds
Started	May 23 04:39:27 PM PDT 24
Finished	May 23 04:42:47 PM PDT 24
Peak memory	572932 kb
Host	smart-987156cd-0541-4e0d-a530-de8c86cba577
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023364130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.3023364130
Directory	/workspace/91.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.675957330
Short name	T1493
Test name
Test status
Simulation time	955610272 ps
CPU time	41.68 seconds
Started	May 23 04:39:06 PM PDT 24
Finished	May 23 04:39:49 PM PDT 24
Peak memory	571800 kb
Host	smart-ebd56299-2227-4a57-855c-53abe5cb1cd8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675957330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.675957330
Directory	/workspace/91.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_access_same_device.788170160
Short name	T2239
Test name
Test status
Simulation time	3161476858 ps
CPU time	174.42 seconds
Started	May 23 04:39:25 PM PDT 24
Finished	May 23 04:42:22 PM PDT 24
Peak memory	572004 kb
Host	smart-9e0b0f74-7df7-4612-8777-8316896ca638
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788170160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device. 788170160
Directory	/workspace/92.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.1425027605
Short name	T793
Test name
Test status
Simulation time	88323979061 ps
CPU time	1541.9 seconds
Started	May 23 04:39:25 PM PDT 24
Finished	May 23 05:05:10 PM PDT 24
Peak memory	572076 kb
Host	smart-1c292fe2-0421-4a57-9085-dfce08c7f3cd
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425027605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.1425027605
Directory	/workspace/92.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_error_random.643300270
Short name	T2376
Test name
Test status
Simulation time	1371793611 ps
CPU time	49.68 seconds
Started	May 23 04:39:20 PM PDT 24
Finished	May 23 04:40:14 PM PDT 24
Peak memory	571832 kb
Host	smart-4d790d63-b840-4097-99af-cc9bcb6a1fec
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643300270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.643300270
Directory	/workspace/92.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_random.2774159185
Short name	T2397
Test name
Test status
Simulation time	375698621 ps
CPU time	35.96 seconds
Started	May 23 04:39:23 PM PDT 24
Finished	May 23 04:40:02 PM PDT 24
Peak memory	571800 kb
Host	smart-73dbfbc5-5b09-4239-aa8b-81e524442a9a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774159185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.2774159185
Directory	/workspace/92.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_random_large_delays.967486661
Short name	T1419
Test name
Test status
Simulation time	22480548594 ps
CPU time	258.64 seconds
Started	May 23 04:39:23 PM PDT 24
Finished	May 23 04:43:44 PM PDT 24
Peak memory	571964 kb
Host	smart-bcf61ffb-2420-44bd-a408-82ce3cab455f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967486661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.967486661
Directory	/workspace/92.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.2041537695
Short name	T2462
Test name
Test status
Simulation time	32410890841 ps
CPU time	567.84 seconds
Started	May 23 04:39:22 PM PDT 24
Finished	May 23 04:48:53 PM PDT 24
Peak memory	572020 kb
Host	smart-b60049f3-09e0-4cb3-b649-28f215e313c1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041537695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.2041537695
Directory	/workspace/92.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.2579536804
Short name	T2448
Test name
Test status
Simulation time	242865165 ps
CPU time	23.74 seconds
Started	May 23 04:39:22 PM PDT 24
Finished	May 23 04:39:49 PM PDT 24
Peak memory	571676 kb
Host	smart-d6fd2274-8b6c-4d78-8d11-43b09f6d3b36
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579536804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.2579536804
Directory	/workspace/92.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_same_source.778573353
Short name	T2040
Test name
Test status
Simulation time	259887473 ps
CPU time	23.57 seconds
Started	May 23 04:39:22 PM PDT 24
Finished	May 23 04:39:48 PM PDT 24
Peak memory	571696 kb
Host	smart-16365d72-dc09-4b99-b482-b01072ed6b72
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778573353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.778573353
Directory	/workspace/92.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke.2591903719
Short name	T1927
Test name
Test status
Simulation time	49918305 ps
CPU time	7.03 seconds
Started	May 23 04:39:22 PM PDT 24
Finished	May 23 04:39:32 PM PDT 24
Peak memory	563552 kb
Host	smart-c49896c9-287d-48f9-b394-738dd9f659ab
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591903719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.2591903719
Directory	/workspace/92.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.2411726115
Short name	T2737
Test name
Test status
Simulation time	8789276155 ps
CPU time	94.94 seconds
Started	May 23 04:39:22 PM PDT 24
Finished	May 23 04:41:00 PM PDT 24
Peak memory	563724 kb
Host	smart-cd9f65da-ed9c-407e-99a5-b608db7b2fc9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411726115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.2411726115
Directory	/workspace/92.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1990409408
Short name	T1822
Test name
Test status
Simulation time	4695535892 ps
CPU time	82.09 seconds
Started	May 23 04:39:22 PM PDT 24
Finished	May 23 04:40:47 PM PDT 24
Peak memory	563812 kb
Host	smart-070a34ef-7538-486e-96f6-36a28a25f95c
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990409408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1990409408
Directory	/workspace/92.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3561055932
Short name	T2401
Test name
Test status
Simulation time	47841108 ps
CPU time	6.58 seconds
Started	May 23 04:39:22 PM PDT 24
Finished	May 23 04:39:32 PM PDT 24
Peak memory	563488 kb
Host	smart-12cc781e-faf9-46a3-96de-267e5c48e29a
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561055932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.3561055932
Directory	/workspace/92.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all.2230182004
Short name	T2413
Test name
Test status
Simulation time	7348948785 ps
CPU time	258.09 seconds
Started	May 23 04:39:24 PM PDT 24
Finished	May 23 04:43:45 PM PDT 24
Peak memory	571956 kb
Host	smart-dca8d73e-2f81-4e7c-b2a7-4451dfdd989a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230182004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2230182004
Directory	/workspace/92.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.542533142
Short name	T2281
Test name
Test status
Simulation time	11483402432 ps
CPU time	489.62 seconds
Started	May 23 04:39:24 PM PDT 24
Finished	May 23 04:47:36 PM PDT 24
Peak memory	572768 kb
Host	smart-cb50b3fd-e7d7-42d3-9a0f-da25a3b1b339
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542533142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.542533142
Directory	/workspace/92.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3698016508
Short name	T1553
Test name
Test status
Simulation time	995786926 ps
CPU time	232.56 seconds
Started	May 23 04:39:26 PM PDT 24
Finished	May 23 04:43:21 PM PDT 24
Peak memory	573004 kb
Host	smart-7e5d697e-6341-44d6-b02d-5e26df98abd9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698016508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.3698016508
Directory	/workspace/92.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.3912708509
Short name	T2373
Test name
Test status
Simulation time	262539601 ps
CPU time	28.98 seconds
Started	May 23 04:39:25 PM PDT 24
Finished	May 23 04:39:56 PM PDT 24
Peak memory	571864 kb
Host	smart-fa0de2f5-b84e-4b0a-8658-ee383885ad28
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912708509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.3912708509
Directory	/workspace/92.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_access_same_device.3340239020
Short name	T772
Test name
Test status
Simulation time	2791805686 ps
CPU time	130.98 seconds
Started	May 23 04:39:39 PM PDT 24
Finished	May 23 04:41:53 PM PDT 24
Peak memory	571928 kb
Host	smart-6e34ffda-70a3-4702-bacd-38b658195cc8
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340239020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3340239020
Directory	/workspace/93.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.4288784513
Short name	T2425
Test name
Test status
Simulation time	123642711757 ps
CPU time	2169.08 seconds
Started	May 23 04:39:38 PM PDT 24
Finished	May 23 05:15:50 PM PDT 24
Peak memory	572048 kb
Host	smart-c9121352-b25a-4c90-bed9-a2ffec95e7e3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288784513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.4288784513
Directory	/workspace/93.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.767936989
Short name	T1684
Test name
Test status
Simulation time	417212813 ps
CPU time	20.22 seconds
Started	May 23 04:39:39 PM PDT 24
Finished	May 23 04:40:02 PM PDT 24
Peak memory	571692 kb
Host	smart-851a534b-9530-47a8-b9b6-b62909bce14b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767936989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr .767936989
Directory	/workspace/93.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_error_random.2427550981
Short name	T1746
Test name
Test status
Simulation time	88679350 ps
CPU time	11.69 seconds
Started	May 23 04:39:39 PM PDT 24
Finished	May 23 04:39:54 PM PDT 24
Peak memory	571828 kb
Host	smart-a950d2d9-bd69-458c-94ee-03b5f5e0cd58
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427550981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.2427550981
Directory	/workspace/93.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_random.4160733373
Short name	T1473
Test name
Test status
Simulation time	518691365 ps
CPU time	44.6 seconds
Started	May 23 04:39:40 PM PDT 24
Finished	May 23 04:40:27 PM PDT 24
Peak memory	571864 kb
Host	smart-fa19dfc5-e47c-451e-a17c-d776bd2e758c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160733373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.4160733373
Directory	/workspace/93.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1374354276
Short name	T1844
Test name
Test status
Simulation time	26191131841 ps
CPU time	314.91 seconds
Started	May 23 04:39:40 PM PDT 24
Finished	May 23 04:44:57 PM PDT 24
Peak memory	572048 kb
Host	smart-b04a700a-bdeb-4265-bd30-29a3e00e042a
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374354276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1374354276
Directory	/workspace/93.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.1315729451
Short name	T541
Test name
Test status
Simulation time	31079270715 ps
CPU time	556.07 seconds
Started	May 23 04:39:39 PM PDT 24
Finished	May 23 04:48:57 PM PDT 24
Peak memory	572008 kb
Host	smart-66f97250-bc38-4049-8b17-e494118684f7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315729451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.1315729451
Directory	/workspace/93.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.3083185065
Short name	T594
Test name
Test status
Simulation time	240667358 ps
CPU time	20.12 seconds
Started	May 23 04:39:38 PM PDT 24
Finished	May 23 04:40:00 PM PDT 24
Peak memory	571808 kb
Host	smart-e54d087a-ef5a-4a12-aad0-5cb17e502b97
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083185065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.3083185065
Directory	/workspace/93.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_same_source.4039525905
Short name	T2250
Test name
Test status
Simulation time	2060308626 ps
CPU time	67.64 seconds
Started	May 23 04:39:39 PM PDT 24
Finished	May 23 04:40:49 PM PDT 24
Peak memory	571808 kb
Host	smart-51a50e00-639d-46f8-aa8d-f835b583df65
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039525905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.4039525905
Directory	/workspace/93.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke.3011135052
Short name	T2447
Test name
Test status
Simulation time	124833957 ps
CPU time	7.28 seconds
Started	May 23 04:39:39 PM PDT 24
Finished	May 23 04:39:49 PM PDT 24
Peak memory	563464 kb
Host	smart-5cc3d30f-30ec-4814-9a00-3341108dab1b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011135052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3011135052
Directory	/workspace/93.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.2530767836
Short name	T1917
Test name
Test status
Simulation time	5109533269 ps
CPU time	55.79 seconds
Started	May 23 04:39:42 PM PDT 24
Finished	May 23 04:40:40 PM PDT 24
Peak memory	563776 kb
Host	smart-34fda6f3-1a74-4bb6-97a6-1da4dbfda880
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530767836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2530767836
Directory	/workspace/93.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.2105687002
Short name	T1320
Test name
Test status
Simulation time	4214747390 ps
CPU time	80.19 seconds
Started	May 23 04:39:42 PM PDT 24
Finished	May 23 04:41:04 PM PDT 24
Peak memory	563736 kb
Host	smart-42bfdf2c-94ae-451c-aaa3-63819def7b9d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105687002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.2105687002
Directory	/workspace/93.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.572198951
Short name	T2293
Test name
Test status
Simulation time	48906134 ps
CPU time	6.42 seconds
Started	May 23 04:39:38 PM PDT 24
Finished	May 23 04:39:47 PM PDT 24
Peak memory	563528 kb
Host	smart-63b3296c-b741-46b9-b4e1-3059eed74bee
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572198951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays .572198951
Directory	/workspace/93.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all.514142200
Short name	T1688
Test name
Test status
Simulation time	4027388168 ps
CPU time	170.34 seconds
Started	May 23 04:39:39 PM PDT 24
Finished	May 23 04:42:32 PM PDT 24
Peak memory	572016 kb
Host	smart-4325b53e-6148-48dc-a145-341c0833b2eb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514142200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.514142200
Directory	/workspace/93.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.2420905288
Short name	T1630
Test name
Test status
Simulation time	10794727569 ps
CPU time	436.97 seconds
Started	May 23 04:39:40 PM PDT 24
Finished	May 23 04:46:59 PM PDT 24
Peak memory	572836 kb
Host	smart-ec53faf5-4454-49c5-8d55-10453bb6174b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420905288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.2420905288
Directory	/workspace/93.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3757655879
Short name	T2735
Test name
Test status
Simulation time	2004278671 ps
CPU time	358.97 seconds
Started	May 23 04:39:44 PM PDT 24
Finished	May 23 04:45:44 PM PDT 24
Peak memory	572896 kb
Host	smart-241f3a5c-d7ec-4dce-a2f1-abe73ff2d148
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757655879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3757655879
Directory	/workspace/93.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.3036144497
Short name	T2430
Test name
Test status
Simulation time	907707590 ps
CPU time	223.08 seconds
Started	May 23 04:39:38 PM PDT 24
Finished	May 23 04:43:22 PM PDT 24
Peak memory	575036 kb
Host	smart-eb79a02e-6b6f-46cc-8e83-6a44b3ee4680
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036144497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.3036144497
Directory	/workspace/93.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.1646501003
Short name	T484
Test name
Test status
Simulation time	261032872 ps
CPU time	29.39 seconds
Started	May 23 04:39:41 PM PDT 24
Finished	May 23 04:40:12 PM PDT 24
Peak memory	571868 kb
Host	smart-65404778-f3f3-4884-82d8-fd8a01230966
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646501003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.1646501003
Directory	/workspace/93.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_access_same_device.1036152888
Short name	T1307
Test name
Test status
Simulation time	590650584 ps
CPU time	47.38 seconds
Started	May 23 04:39:57 PM PDT 24
Finished	May 23 04:40:46 PM PDT 24
Peak memory	571852 kb
Host	smart-71d09cda-d0bf-4ada-854f-f49ff78665fc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036152888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .1036152888
Directory	/workspace/94.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3308522483
Short name	T2286
Test name
Test status
Simulation time	26340815265 ps
CPU time	448.09 seconds
Started	May 23 04:39:53 PM PDT 24
Finished	May 23 04:47:24 PM PDT 24
Peak memory	572064 kb
Host	smart-6777682a-e74e-44ba-920b-1f9c7072d571
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308522483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.3308522483
Directory	/workspace/94.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.181894528
Short name	T2259
Test name
Test status
Simulation time	729297773 ps
CPU time	32.5 seconds
Started	May 23 04:39:57 PM PDT 24
Finished	May 23 04:40:31 PM PDT 24
Peak memory	571840 kb
Host	smart-ecb1672e-2ecf-447d-86c0-2d73c6669f43
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181894528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr .181894528
Directory	/workspace/94.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_error_random.2297506103
Short name	T2553
Test name
Test status
Simulation time	1248390356 ps
CPU time	43.23 seconds
Started	May 23 04:39:57 PM PDT 24
Finished	May 23 04:40:42 PM PDT 24
Peak memory	571780 kb
Host	smart-4a8755e4-220d-4da1-9125-bc5a4d02da0f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297506103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.2297506103
Directory	/workspace/94.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_random.3027268525
Short name	T1974
Test name
Test status
Simulation time	1120080834 ps
CPU time	43.03 seconds
Started	May 23 04:39:41 PM PDT 24
Finished	May 23 04:40:26 PM PDT 24
Peak memory	571808 kb
Host	smart-35cd074a-18b2-433b-a507-0c63c8d8cefd
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027268525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.3027268525
Directory	/workspace/94.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_random_large_delays.3282756632
Short name	T2044
Test name
Test status
Simulation time	39901468980 ps
CPU time	422.64 seconds
Started	May 23 04:39:44 PM PDT 24
Finished	May 23 04:46:48 PM PDT 24
Peak memory	572008 kb
Host	smart-e0b676e1-026f-4968-a7f1-5fb840e55e27
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282756632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.3282756632
Directory	/workspace/94.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3614775640
Short name	T2655
Test name
Test status
Simulation time	41333447341 ps
CPU time	708.67 seconds
Started	May 23 04:39:44 PM PDT 24
Finished	May 23 04:51:33 PM PDT 24
Peak memory	572000 kb
Host	smart-cab16e29-5934-41a9-b830-97223e591641
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614775640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3614775640
Directory	/workspace/94.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.2799876627
Short name	T1689
Test name
Test status
Simulation time	575309603 ps
CPU time	55.22 seconds
Started	May 23 04:39:41 PM PDT 24
Finished	May 23 04:40:38 PM PDT 24
Peak memory	571788 kb
Host	smart-010114f3-9cab-45b7-aa40-ff8de62182e9
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799876627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.2799876627
Directory	/workspace/94.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_same_source.3037830050
Short name	T1812
Test name
Test status
Simulation time	651295642 ps
CPU time	21.37 seconds
Started	May 23 04:39:55 PM PDT 24
Finished	May 23 04:40:19 PM PDT 24
Peak memory	571740 kb
Host	smart-dd29d0e2-84cf-4556-a766-126ceaf22b8a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037830050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3037830050
Directory	/workspace/94.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke.2397420502
Short name	T1400
Test name
Test status
Simulation time	149100168 ps
CPU time	7.7 seconds
Started	May 23 04:39:41 PM PDT 24
Finished	May 23 04:39:50 PM PDT 24
Peak memory	563556 kb
Host	smart-014ae2d6-c5f2-4333-92f8-e2e4abce338a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397420502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.2397420502
Directory	/workspace/94.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2975808829
Short name	T1366
Test name
Test status
Simulation time	8657067705 ps
CPU time	99.05 seconds
Started	May 23 04:39:41 PM PDT 24
Finished	May 23 04:41:22 PM PDT 24
Peak memory	563792 kb
Host	smart-12b5f89a-d804-4444-bec3-bc2c87989c13
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975808829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.2975808829
Directory	/workspace/94.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.2030316095
Short name	T2673
Test name
Test status
Simulation time	3809307384 ps
CPU time	66.5 seconds
Started	May 23 04:39:42 PM PDT 24
Finished	May 23 04:40:50 PM PDT 24
Peak memory	563748 kb
Host	smart-5ac43be5-fdd5-4054-b0e1-378bf6c96f9d
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030316095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.2030316095
Directory	/workspace/94.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1739372401
Short name	T1768
Test name
Test status
Simulation time	47264660 ps
CPU time	6.59 seconds
Started	May 23 04:39:40 PM PDT 24
Finished	May 23 04:39:49 PM PDT 24
Peak memory	563508 kb
Host	smart-907ca071-68de-4246-8c00-ffe36256d2fb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739372401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.1739372401
Directory	/workspace/94.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all.326485593
Short name	T1385
Test name
Test status
Simulation time	131302469 ps
CPU time	7.54 seconds
Started	May 23 04:39:55 PM PDT 24
Finished	May 23 04:40:05 PM PDT 24
Peak memory	563568 kb
Host	smart-e98d6a34-7223-47f4-b3a4-6c87777e67fe
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326485593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.326485593
Directory	/workspace/94.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2834787933
Short name	T2093
Test name
Test status
Simulation time	9620506024 ps
CPU time	324.03 seconds
Started	May 23 04:39:54 PM PDT 24
Finished	May 23 04:45:21 PM PDT 24
Peak memory	572012 kb
Host	smart-f50d5f05-566c-4151-82c9-831af8dca2ff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834787933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2834787933
Directory	/workspace/94.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3510965978
Short name	T2439
Test name
Test status
Simulation time	179829464 ps
CPU time	120.84 seconds
Started	May 23 04:39:52 PM PDT 24
Finished	May 23 04:41:55 PM PDT 24
Peak memory	572212 kb
Host	smart-d8c1e502-bfcb-4a13-bd69-cffa2d6b6eb4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510965978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.3510965978
Directory	/workspace/94.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1014295323
Short name	T1791
Test name
Test status
Simulation time	5149677677 ps
CPU time	540.04 seconds
Started	May 23 04:39:53 PM PDT 24
Finished	May 23 04:48:55 PM PDT 24
Peak memory	573100 kb
Host	smart-98ae60f0-4a34-4b8f-8a56-28963b98caa6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014295323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.1014295323
Directory	/workspace/94.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.286398568
Short name	T2682
Test name
Test status
Simulation time	216093789 ps
CPU time	25.72 seconds
Started	May 23 04:39:53 PM PDT 24
Finished	May 23 04:40:21 PM PDT 24
Peak memory	571868 kb
Host	smart-c788e18e-718c-436c-ab49-5d68652311bb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286398568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.286398568
Directory	/workspace/94.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_access_same_device.4264417808
Short name	T2465
Test name
Test status
Simulation time	536198278 ps
CPU time	51.7 seconds
Started	May 23 04:39:52 PM PDT 24
Finished	May 23 04:40:46 PM PDT 24
Peak memory	571780 kb
Host	smart-e02d79d3-fe80-475b-bc89-c9e0a945b947
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264417808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .4264417808
Directory	/workspace/95.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.3137052637
Short name	T2414
Test name
Test status
Simulation time	131496336046 ps
CPU time	2259.79 seconds
Started	May 23 04:39:56 PM PDT 24
Finished	May 23 05:17:38 PM PDT 24
Peak memory	572004 kb
Host	smart-ebb98cc8-43d2-4b05-857c-3d3163369620
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137052637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.3137052637
Directory	/workspace/95.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2109521932
Short name	T2053
Test name
Test status
Simulation time	97690388 ps
CPU time	13.68 seconds
Started	May 23 04:39:55 PM PDT 24
Finished	May 23 04:40:11 PM PDT 24
Peak memory	571820 kb
Host	smart-ae644866-0ba3-444d-896e-507cc63d4d0c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109521932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2109521932
Directory	/workspace/95.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_error_random.3249452934
Short name	T1253
Test name
Test status
Simulation time	614792733 ps
CPU time	24.97 seconds
Started	May 23 04:39:54 PM PDT 24
Finished	May 23 04:40:22 PM PDT 24
Peak memory	571716 kb
Host	smart-470f0604-5c5e-4578-9bba-8c15e92b8a09
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249452934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3249452934
Directory	/workspace/95.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_random.2823073778
Short name	T1455
Test name
Test status
Simulation time	475150453 ps
CPU time	19.16 seconds
Started	May 23 04:39:55 PM PDT 24
Finished	May 23 04:40:17 PM PDT 24
Peak memory	571752 kb
Host	smart-42531e63-420e-480c-beb5-462e68ce10ad
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823073778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2823073778
Directory	/workspace/95.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_random_large_delays.3033127618
Short name	T1792
Test name
Test status
Simulation time	84478425467 ps
CPU time	909.49 seconds
Started	May 23 04:39:54 PM PDT 24
Finished	May 23 04:55:06 PM PDT 24
Peak memory	571988 kb
Host	smart-f05e2d34-9b54-4683-997b-f7e27fcf5683
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033127618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.3033127618
Directory	/workspace/95.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.3795484034
Short name	T2198
Test name
Test status
Simulation time	8099487968 ps
CPU time	140.51 seconds
Started	May 23 04:39:53 PM PDT 24
Finished	May 23 04:42:16 PM PDT 24
Peak memory	571956 kb
Host	smart-2d3a75da-e32a-4e3a-9bb7-ddc8103b6151
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795484034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.3795484034
Directory	/workspace/95.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.1911885313
Short name	T1816
Test name
Test status
Simulation time	139698283 ps
CPU time	17.09 seconds
Started	May 23 04:39:55 PM PDT 24
Finished	May 23 04:40:14 PM PDT 24
Peak memory	571772 kb
Host	smart-89ba0317-6262-4b3e-932a-d9473881d6e6
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911885313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.1911885313
Directory	/workspace/95.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_same_source.292157743
Short name	T2687
Test name
Test status
Simulation time	1048594141 ps
CPU time	33.58 seconds
Started	May 23 04:39:49 PM PDT 24
Finished	May 23 04:40:24 PM PDT 24
Peak memory	571792 kb
Host	smart-f65310f4-e745-43c3-8098-57da3f62c121
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292157743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.292157743
Directory	/workspace/95.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke.1971885705
Short name	T543
Test name
Test status
Simulation time	51959387 ps
CPU time	7.1 seconds
Started	May 23 04:39:53 PM PDT 24
Finished	May 23 04:40:03 PM PDT 24
Peak memory	563496 kb
Host	smart-5584a5cf-f8e0-4a50-810c-8ff56e99a02d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971885705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1971885705
Directory	/workspace/95.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.3559350004
Short name	T56
Test name
Test status
Simulation time	6633056714 ps
CPU time	75.72 seconds
Started	May 23 04:39:52 PM PDT 24
Finished	May 23 04:41:10 PM PDT 24
Peak memory	563720 kb
Host	smart-4cd8e91c-dc0a-4e49-936b-9097206379ee
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559350004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.3559350004
Directory	/workspace/95.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.1814352413
Short name	T1693
Test name
Test status
Simulation time	6225167015 ps
CPU time	116.86 seconds
Started	May 23 04:39:52 PM PDT 24
Finished	May 23 04:41:52 PM PDT 24
Peak memory	563688 kb
Host	smart-affe7b74-62cc-4f08-a854-5784dae856b1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814352413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.1814352413
Directory	/workspace/95.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1577062234
Short name	T1245
Test name
Test status
Simulation time	58044957 ps
CPU time	7.75 seconds
Started	May 23 04:39:53 PM PDT 24
Finished	May 23 04:40:03 PM PDT 24
Peak memory	563472 kb
Host	smart-8e7da8f2-2638-490b-b871-7986ed3dfb40
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577062234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.1577062234
Directory	/workspace/95.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2836636911
Short name	T2642
Test name
Test status
Simulation time	15712566199 ps
CPU time	520.2 seconds
Started	May 23 04:39:52 PM PDT 24
Finished	May 23 04:48:34 PM PDT 24
Peak memory	572864 kb
Host	smart-d899f3d0-44b7-4b1a-85b9-797423325543
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836636911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2836636911
Directory	/workspace/95.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.2883987593
Short name	T2605
Test name
Test status
Simulation time	5131957715 ps
CPU time	273.31 seconds
Started	May 23 04:39:55 PM PDT 24
Finished	May 23 04:44:30 PM PDT 24
Peak memory	573020 kb
Host	smart-18cf17a0-e0ec-44a0-b865-aa3b49f785ee
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883987593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.2883987593
Directory	/workspace/95.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2583148758
Short name	T796
Test name
Test status
Simulation time	3361646695 ps
CPU time	240.57 seconds
Started	May 23 04:39:56 PM PDT 24
Finished	May 23 04:43:59 PM PDT 24
Peak memory	573136 kb
Host	smart-8fe612ca-9226-4146-b5e1-99e19ad1589f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583148758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.2583148758
Directory	/workspace/95.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.1456774291
Short name	T469
Test name
Test status
Simulation time	262060957 ps
CPU time	30.53 seconds
Started	May 23 04:39:57 PM PDT 24
Finished	May 23 04:40:29 PM PDT 24
Peak memory	571864 kb
Host	smart-8189c669-c58f-49f1-9415-e23194d90301
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456774291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.1456774291
Directory	/workspace/95.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_access_same_device.1212450182
Short name	T785
Test name
Test status
Simulation time	643094447 ps
CPU time	33.66 seconds
Started	May 23 04:40:08 PM PDT 24
Finished	May 23 04:40:42 PM PDT 24
Peak memory	571788 kb
Host	smart-6e0f007b-faf3-4586-96f9-5c3accd90b32
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212450182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .1212450182
Directory	/workspace/96.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1555608139
Short name	T1696
Test name
Test status
Simulation time	69520488805 ps
CPU time	1220.59 seconds
Started	May 23 04:40:06 PM PDT 24
Finished	May 23 05:00:27 PM PDT 24
Peak memory	572040 kb
Host	smart-94c23cee-5f14-482f-a5ee-9f656eac6f0e
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555608139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.1555608139
Directory	/workspace/96.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1281825096
Short name	T2301
Test name
Test status
Simulation time	56642947 ps
CPU time	9.75 seconds
Started	May 23 04:40:07 PM PDT 24
Finished	May 23 04:40:18 PM PDT 24
Peak memory	563632 kb
Host	smart-73672459-eb37-4620-85ef-e1257d3a1201
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281825096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.1281825096
Directory	/workspace/96.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_error_random.822173029
Short name	T1981
Test name
Test status
Simulation time	1832857107 ps
CPU time	58.2 seconds
Started	May 23 04:40:09 PM PDT 24
Finished	May 23 04:41:08 PM PDT 24
Peak memory	571800 kb
Host	smart-3495f271-ca99-4f7a-9f70-6097083b3a9e
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822173029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.822173029
Directory	/workspace/96.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_random.4122957750
Short name	T2433
Test name
Test status
Simulation time	512518515 ps
CPU time	47.63 seconds
Started	May 23 04:39:54 PM PDT 24
Finished	May 23 04:40:44 PM PDT 24
Peak memory	571868 kb
Host	smart-8e88f5ca-7023-46d1-931f-99886c702201
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122957750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.4122957750
Directory	/workspace/96.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_random_large_delays.1732932356
Short name	T1415
Test name
Test status
Simulation time	33495896650 ps
CPU time	361.94 seconds
Started	May 23 04:39:53 PM PDT 24
Finished	May 23 04:45:57 PM PDT 24
Peak memory	572004 kb
Host	smart-dc39ca93-a4db-46ce-99d6-7f51a41ed5fb
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732932356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.1732932356
Directory	/workspace/96.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1674239991
Short name	T1384
Test name
Test status
Simulation time	24206553926 ps
CPU time	424.44 seconds
Started	May 23 04:39:57 PM PDT 24
Finished	May 23 04:47:03 PM PDT 24
Peak memory	571976 kb
Host	smart-835d1dc5-e349-4a16-835a-3a9861d96a09
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674239991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1674239991
Directory	/workspace/96.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.593992535
Short name	T2618
Test name
Test status
Simulation time	92724439 ps
CPU time	12.33 seconds
Started	May 23 04:39:51 PM PDT 24
Finished	May 23 04:40:05 PM PDT 24
Peak memory	571800 kb
Host	smart-96df52ce-9703-40b5-bda9-949edd0891cb
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593992535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_dela ys.593992535
Directory	/workspace/96.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_same_source.2272907497
Short name	T2251
Test name
Test status
Simulation time	996395769 ps
CPU time	29.24 seconds
Started	May 23 04:40:10 PM PDT 24
Finished	May 23 04:40:40 PM PDT 24
Peak memory	571832 kb
Host	smart-1a53c1be-7369-4df3-8023-1a794aa4f62f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272907497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.2272907497
Directory	/workspace/96.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke.2362163590
Short name	T2764
Test name
Test status
Simulation time	54359543 ps
CPU time	6.87 seconds
Started	May 23 04:39:58 PM PDT 24
Finished	May 23 04:40:06 PM PDT 24
Peak memory	563512 kb
Host	smart-3b9e2275-8aaa-4264-b51f-0cdac60bab0c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362163590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.2362163590
Directory	/workspace/96.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2196698411
Short name	T1519
Test name
Test status
Simulation time	8471007281 ps
CPU time	88.42 seconds
Started	May 23 04:39:52 PM PDT 24
Finished	May 23 04:41:23 PM PDT 24
Peak memory	563756 kb
Host	smart-ef969a99-ab9d-4181-97bc-3f353e0c3be5
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196698411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2196698411
Directory	/workspace/96.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.909213718
Short name	T2082
Test name
Test status
Simulation time	6194720440 ps
CPU time	103.97 seconds
Started	May 23 04:39:51 PM PDT 24
Finished	May 23 04:41:37 PM PDT 24
Peak memory	563776 kb
Host	smart-0c074c90-e6b0-4f95-84a0-1f0b8b3a9d56
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909213718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.909213718
Directory	/workspace/96.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.1871457407
Short name	T1898
Test name
Test status
Simulation time	40179086 ps
CPU time	6.11 seconds
Started	May 23 04:39:54 PM PDT 24
Finished	May 23 04:40:03 PM PDT 24
Peak memory	563512 kb
Host	smart-82e25230-f9df-45dd-a754-1f9844fccea2
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871457407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.1871457407
Directory	/workspace/96.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all.802214684
Short name	T417
Test name
Test status
Simulation time	1110896487 ps
CPU time	99.93 seconds
Started	May 23 04:40:11 PM PDT 24
Finished	May 23 04:41:52 PM PDT 24
Peak memory	572296 kb
Host	smart-6ef6e570-8337-45d1-949b-d99967fa0bf4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802214684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.802214684
Directory	/workspace/96.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3820892964
Short name	T2355
Test name
Test status
Simulation time	604714830 ps
CPU time	46.42 seconds
Started	May 23 04:40:08 PM PDT 24
Finished	May 23 04:40:55 PM PDT 24
Peak memory	571880 kb
Host	smart-61b4065d-1768-4c61-9a47-0835caaecf89
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820892964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.3820892964
Directory	/workspace/96.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2051943425
Short name	T2494
Test name
Test status
Simulation time	1613175848 ps
CPU time	421.7 seconds
Started	May 23 04:40:12 PM PDT 24
Finished	May 23 04:47:15 PM PDT 24
Peak memory	573948 kb
Host	smart-14bc87db-eb1f-4974-a027-630fd1ddad45
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051943425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.2051943425
Directory	/workspace/96.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.801104916
Short name	T1562
Test name
Test status
Simulation time	6082600291 ps
CPU time	230.95 seconds
Started	May 23 04:40:07 PM PDT 24
Finished	May 23 04:43:59 PM PDT 24
Peak memory	573004 kb
Host	smart-ffd5b21b-aec5-442b-8bb4-84703770f813
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801104916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_reset_error.801104916
Directory	/workspace/96.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2928182986
Short name	T2765
Test name
Test status
Simulation time	632572635 ps
CPU time	27.14 seconds
Started	May 23 04:40:09 PM PDT 24
Finished	May 23 04:40:37 PM PDT 24
Peak memory	571876 kb
Host	smart-63236a54-1c24-4d03-8828-c4dd4a76383f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928182986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2928182986
Directory	/workspace/96.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_access_same_device.2844792085
Short name	T2060
Test name
Test status
Simulation time	2417550794 ps
CPU time	124.98 seconds
Started	May 23 04:40:10 PM PDT 24
Finished	May 23 04:42:16 PM PDT 24
Peak memory	571972 kb
Host	smart-d8e82999-be23-4413-b19b-913c3ad7d42b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844792085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .2844792085
Directory	/workspace/97.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2250794284
Short name	T1578
Test name
Test status
Simulation time	798300917 ps
CPU time	33.79 seconds
Started	May 23 04:40:26 PM PDT 24
Finished	May 23 04:41:01 PM PDT 24
Peak memory	571812 kb
Host	smart-9ea2cb65-5c33-4e86-850c-80082f9448ff
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250794284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.2250794284
Directory	/workspace/97.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_error_random.1707877561
Short name	T1295
Test name
Test status
Simulation time	470875090 ps
CPU time	20.24 seconds
Started	May 23 04:40:26 PM PDT 24
Finished	May 23 04:40:47 PM PDT 24
Peak memory	571768 kb
Host	smart-091565d8-ffc9-4411-8861-ce63697be4db
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707877561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1707877561
Directory	/workspace/97.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_random.3729256977
Short name	T511
Test name
Test status
Simulation time	594225758 ps
CPU time	24.16 seconds
Started	May 23 04:40:11 PM PDT 24
Finished	May 23 04:40:36 PM PDT 24
Peak memory	571828 kb
Host	smart-b8b511e8-4eb9-4a7a-abd9-6edd7b7c536b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729256977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3729256977
Directory	/workspace/97.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_random_large_delays.4152090220
Short name	T2148
Test name
Test status
Simulation time	64271045261 ps
CPU time	618.87 seconds
Started	May 23 04:40:11 PM PDT 24
Finished	May 23 04:50:31 PM PDT 24
Peak memory	572036 kb
Host	smart-1f3bf517-b097-4703-b487-acb78d2ef227
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152090220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.4152090220
Directory	/workspace/97.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.4079398542
Short name	T444
Test name
Test status
Simulation time	60960604309 ps
CPU time	1056.81 seconds
Started	May 23 04:40:09 PM PDT 24
Finished	May 23 04:57:48 PM PDT 24
Peak memory	571980 kb
Host	smart-06649512-8781-4a1a-b5bf-4be16febe8c1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079398542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.4079398542
Directory	/workspace/97.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.516641257
Short name	T540
Test name
Test status
Simulation time	95854838 ps
CPU time	11.9 seconds
Started	May 23 04:40:09 PM PDT 24
Finished	May 23 04:40:22 PM PDT 24
Peak memory	571788 kb
Host	smart-abe858d5-8ae7-4f5f-aeaa-6cdf832b1783
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516641257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_dela ys.516641257
Directory	/workspace/97.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_same_source.2274683012
Short name	T1488
Test name
Test status
Simulation time	874745237 ps
CPU time	27.08 seconds
Started	May 23 04:40:09 PM PDT 24
Finished	May 23 04:40:37 PM PDT 24
Peak memory	571836 kb
Host	smart-b26a1269-7579-4146-9847-b8bea51714f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274683012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.2274683012
Directory	/workspace/97.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke.1031475807
Short name	T2105
Test name
Test status
Simulation time	53356190 ps
CPU time	7.39 seconds
Started	May 23 04:40:12 PM PDT 24
Finished	May 23 04:40:20 PM PDT 24
Peak memory	563532 kb
Host	smart-3e22f654-847d-42b7-b51d-d5698d992d6b
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031475807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.1031475807
Directory	/workspace/97.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.4042645208
Short name	T2341
Test name
Test status
Simulation time	7872370104 ps
CPU time	86.77 seconds
Started	May 23 04:40:07 PM PDT 24
Finished	May 23 04:41:35 PM PDT 24
Peak memory	563804 kb
Host	smart-a101ff11-d3e6-4641-8a00-041957f88436
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042645208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.4042645208
Directory	/workspace/97.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.938900278
Short name	T2322
Test name
Test status
Simulation time	4980480440 ps
CPU time	94.35 seconds
Started	May 23 04:40:07 PM PDT 24
Finished	May 23 04:41:42 PM PDT 24
Peak memory	563688 kb
Host	smart-8cd500df-7b9b-4fa8-86cd-ed2e458e02da
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938900278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.938900278
Directory	/workspace/97.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.3494100698
Short name	T1453
Test name
Test status
Simulation time	39470812 ps
CPU time	6.28 seconds
Started	May 23 04:40:09 PM PDT 24
Finished	May 23 04:40:16 PM PDT 24
Peak memory	563552 kb
Host	smart-b489fbb9-7a50-434f-afe2-7394cc9e0184
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494100698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.3494100698
Directory	/workspace/97.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all.2219791423
Short name	T1626
Test name
Test status
Simulation time	771911024 ps
CPU time	64.41 seconds
Started	May 23 04:40:22 PM PDT 24
Finished	May 23 04:41:28 PM PDT 24
Peak memory	571864 kb
Host	smart-b248b280-cb55-4845-b20c-b48a1bf9fddb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219791423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2219791423
Directory	/workspace/97.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2740019583
Short name	T776
Test name
Test status
Simulation time	11941135732 ps
CPU time	369.87 seconds
Started	May 23 04:40:25 PM PDT 24
Finished	May 23 04:46:36 PM PDT 24
Peak memory	573100 kb
Host	smart-0d3aea52-2e69-4652-81a7-017e0490d864
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740019583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2740019583
Directory	/workspace/97.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.3865490319
Short name	T2328
Test name
Test status
Simulation time	513186650 ps
CPU time	198.77 seconds
Started	May 23 04:40:26 PM PDT 24
Finished	May 23 04:43:46 PM PDT 24
Peak memory	572908 kb
Host	smart-4583cab7-34d2-4df2-a914-32067e3e29f0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865490319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.3865490319
Directory	/workspace/97.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1368361709
Short name	T1763
Test name
Test status
Simulation time	3759856118 ps
CPU time	442.92 seconds
Started	May 23 04:40:22 PM PDT 24
Finished	May 23 04:47:46 PM PDT 24
Peak memory	573144 kb
Host	smart-69956bc7-ce8a-4733-9bb5-2d41d6c6160f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368361709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.1368361709
Directory	/workspace/97.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1974061000
Short name	T1661
Test name
Test status
Simulation time	332677511 ps
CPU time	41.86 seconds
Started	May 23 04:40:23 PM PDT 24
Finished	May 23 04:41:06 PM PDT 24
Peak memory	571856 kb
Host	smart-c7f337dc-bee0-4a54-8d42-6d70bf876c0c
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974061000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.1974061000
Directory	/workspace/97.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_access_same_device.2373375998
Short name	T2364
Test name
Test status
Simulation time	2810105474 ps
CPU time	118.56 seconds
Started	May 23 04:40:25 PM PDT 24
Finished	May 23 04:42:25 PM PDT 24
Peak memory	571960 kb
Host	smart-10d4935a-3f79-4d1d-a109-c5f3b1686a33
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373375998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .2373375998
Directory	/workspace/98.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3781973413
Short name	T1275
Test name
Test status
Simulation time	104874707 ps
CPU time	13.32 seconds
Started	May 23 04:40:21 PM PDT 24
Finished	May 23 04:40:35 PM PDT 24
Peak memory	571844 kb
Host	smart-4d99f3ce-d076-42cb-8278-201643a6fca6
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781973413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.3781973413
Directory	/workspace/98.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_error_random.839973468
Short name	T2062
Test name
Test status
Simulation time	2181951398 ps
CPU time	77.8 seconds
Started	May 23 04:40:23 PM PDT 24
Finished	May 23 04:41:42 PM PDT 24
Peak memory	571928 kb
Host	smart-b14a918f-1ea7-466e-81be-1412c1d506cb
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839973468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.839973468
Directory	/workspace/98.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_random.871840972
Short name	T2183
Test name
Test status
Simulation time	1889347301 ps
CPU time	77.22 seconds
Started	May 23 04:40:25 PM PDT 24
Finished	May 23 04:41:44 PM PDT 24
Peak memory	571824 kb
Host	smart-11005674-baa4-4a92-a4e1-024e4fd9de1d
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871840972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.871840972
Directory	/workspace/98.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3417032465
Short name	T570
Test name
Test status
Simulation time	50407136411 ps
CPU time	529.57 seconds
Started	May 23 04:40:21 PM PDT 24
Finished	May 23 04:49:12 PM PDT 24
Peak memory	572016 kb
Host	smart-cc9b4061-39af-427b-9b1b-cc4a1ebf49d1
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417032465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.3417032465
Directory	/workspace/98.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.438539523
Short name	T558
Test name
Test status
Simulation time	41036303805 ps
CPU time	693.47 seconds
Started	May 23 04:40:22 PM PDT 24
Finished	May 23 04:51:56 PM PDT 24
Peak memory	572008 kb
Host	smart-d21430df-60b4-485d-b111-64d0bb2ae325
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438539523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.438539523
Directory	/workspace/98.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1533404805
Short name	T2780
Test name
Test status
Simulation time	100242947 ps
CPU time	11.2 seconds
Started	May 23 04:40:24 PM PDT 24
Finished	May 23 04:40:36 PM PDT 24
Peak memory	571716 kb
Host	smart-bab7d313-8788-44ab-af4a-911243f0809d
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533404805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.1533404805
Directory	/workspace/98.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_same_source.591639976
Short name	T2196
Test name
Test status
Simulation time	1816643800 ps
CPU time	62.46 seconds
Started	May 23 04:40:23 PM PDT 24
Finished	May 23 04:41:26 PM PDT 24
Peak memory	571756 kb
Host	smart-d1b70b55-3053-4724-b712-5f642417b5f1
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591639976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.591639976
Directory	/workspace/98.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke.2906215809
Short name	T1829
Test name
Test status
Simulation time	42342183 ps
CPU time	6.03 seconds
Started	May 23 04:40:22 PM PDT 24
Finished	May 23 04:40:29 PM PDT 24
Peak memory	563544 kb
Host	smart-a9a455ea-9cba-43f2-92ae-726dfa7bfb55
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906215809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.2906215809
Directory	/workspace/98.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3865264606
Short name	T1286
Test name
Test status
Simulation time	7156059938 ps
CPU time	79.21 seconds
Started	May 23 04:40:21 PM PDT 24
Finished	May 23 04:41:42 PM PDT 24
Peak memory	563828 kb
Host	smart-188ebaae-d41c-4c8c-8de1-615067edab1f
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865264606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3865264606
Directory	/workspace/98.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1281407520
Short name	T1304
Test name
Test status
Simulation time	5145957382 ps
CPU time	91.1 seconds
Started	May 23 04:40:21 PM PDT 24
Finished	May 23 04:41:53 PM PDT 24
Peak memory	563792 kb
Host	smart-02607c88-f709-4a8d-a2a2-1773ea0631f3
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281407520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1281407520
Directory	/workspace/98.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.966717231
Short name	T1526
Test name
Test status
Simulation time	41345473 ps
CPU time	6.36 seconds
Started	May 23 04:40:25 PM PDT 24
Finished	May 23 04:40:33 PM PDT 24
Peak memory	563560 kb
Host	smart-35de4a13-f3c3-4325-9c4a-7f7056646278
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966717231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays .966717231
Directory	/workspace/98.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all.1182511090
Short name	T2579
Test name
Test status
Simulation time	1809236504 ps
CPU time	77.5 seconds
Started	May 23 04:40:25 PM PDT 24
Finished	May 23 04:41:44 PM PDT 24
Peak memory	571872 kb
Host	smart-ff50485c-c3bb-4684-996f-6f902db3057a
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182511090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.1182511090
Directory	/workspace/98.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.1576035188
Short name	T414
Test name
Test status
Simulation time	1212945170 ps
CPU time	108.66 seconds
Started	May 23 04:40:26 PM PDT 24
Finished	May 23 04:42:15 PM PDT 24
Peak memory	571904 kb
Host	smart-7397cb2c-6f6f-4fe5-b457-08ca9d87b0c3
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576035188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.1576035188
Directory	/workspace/98.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.395945880
Short name	T2493
Test name
Test status
Simulation time	750860719 ps
CPU time	334.89 seconds
Started	May 23 04:40:24 PM PDT 24
Finished	May 23 04:46:00 PM PDT 24
Peak memory	572796 kb
Host	smart-9c06bdd4-c5c8-4a0e-806b-045436d18a3f
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395945880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_ with_rand_reset.395945880
Directory	/workspace/98.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.330371562
Short name	T1707
Test name
Test status
Simulation time	316271423 ps
CPU time	73.02 seconds
Started	May 23 04:40:22 PM PDT 24
Finished	May 23 04:41:36 PM PDT 24
Peak memory	572000 kb
Host	smart-b2fb3eeb-54ad-4718-abf0-9c9c71638859
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330371562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_reset_error.330371562
Directory	/workspace/98.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.543801722
Short name	T2404
Test name
Test status
Simulation time	318778650 ps
CPU time	42.35 seconds
Started	May 23 04:40:23 PM PDT 24
Finished	May 23 04:41:06 PM PDT 24
Peak memory	571896 kb
Host	smart-bfd178d3-ee97-4328-98fa-45650a44aead
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543801722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.543801722
Directory	/workspace/98.xbar_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_access_same_device.2790556649
Short name	T2753
Test name
Test status
Simulation time	2638323034 ps
CPU time	108.7 seconds
Started	May 23 04:40:42 PM PDT 24
Finished	May 23 04:42:31 PM PDT 24
Peak memory	572008 kb
Host	smart-48f16f5d-3cf1-4ae6-af3c-37a9f99bddae
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790556649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .2790556649
Directory	/workspace/99.xbar_access_same_device/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.680047783
Short name	T433
Test name
Test status
Simulation time	133810933276 ps
CPU time	2257.55 seconds
Started	May 23 04:40:36 PM PDT 24
Finished	May 23 05:18:15 PM PDT 24
Peak memory	572024 kb
Host	smart-0a8972eb-fe67-4662-aeaf-768d4efe62da
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680047783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_d evice_slow_rsp.680047783
Directory	/workspace/99.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2340946567
Short name	T2072
Test name
Test status
Simulation time	782142450 ps
CPU time	34.1 seconds
Started	May 23 04:40:33 PM PDT 24
Finished	May 23 04:41:08 PM PDT 24
Peak memory	571880 kb
Host	smart-b0c49f93-22ac-4b84-af0d-21fd601549cc
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340946567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.2340946567
Directory	/workspace/99.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_error_random.2653591373
Short name	T2473
Test name
Test status
Simulation time	442104893 ps
CPU time	41.42 seconds
Started	May 23 04:40:35 PM PDT 24
Finished	May 23 04:41:18 PM PDT 24
Peak memory	571828 kb
Host	smart-b578c3c2-c2e9-4530-a390-0faf6a06f783
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653591373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.2653591373
Directory	/workspace/99.xbar_error_random/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_random.478421000
Short name	T1504
Test name
Test status
Simulation time	325456906 ps
CPU time	31.53 seconds
Started	May 23 04:40:23 PM PDT 24
Finished	May 23 04:40:56 PM PDT 24
Peak memory	571872 kb
Host	smart-af62a6df-0577-4194-81ef-86b3b8d99ab9
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478421000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.478421000
Directory	/workspace/99.xbar_random/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3221804644
Short name	T2144
Test name
Test status
Simulation time	5210160220 ps
CPU time	58.51 seconds
Started	May 23 04:40:23 PM PDT 24
Finished	May 23 04:41:22 PM PDT 24
Peak memory	563804 kb
Host	smart-c2e9b164-7b99-4a34-863f-ab412549e0f9
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221804644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3221804644
Directory	/workspace/99.xbar_random_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.1202774237
Short name	T1659
Test name
Test status
Simulation time	30233038246 ps
CPU time	496.34 seconds
Started	May 23 04:40:26 PM PDT 24
Finished	May 23 04:48:43 PM PDT 24
Peak memory	572060 kb
Host	smart-9eadca79-8f25-4ace-b5c8-e07591c66ba2
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202774237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.1202774237
Directory	/workspace/99.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.2718395367
Short name	T2113
Test name
Test status
Simulation time	183667121 ps
CPU time	18.25 seconds
Started	May 23 04:40:22 PM PDT 24
Finished	May 23 04:40:41 PM PDT 24
Peak memory	571744 kb
Host	smart-d08b82c8-03c4-481a-9004-809f2259aecc
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718395367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.2718395367
Directory	/workspace/99.xbar_random_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_same_source.2887277081
Short name	T568
Test name
Test status
Simulation time	1966390370 ps
CPU time	60.48 seconds
Started	May 23 04:40:33 PM PDT 24
Finished	May 23 04:41:35 PM PDT 24
Peak memory	571824 kb
Host	smart-be10ef11-e4a9-4237-880b-fb8e474cfef5
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887277081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2887277081
Directory	/workspace/99.xbar_same_source/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke.2082321314
Short name	T1946
Test name
Test status
Simulation time	232874461 ps
CPU time	11.16 seconds
Started	May 23 04:40:23 PM PDT 24
Finished	May 23 04:40:35 PM PDT 24
Peak memory	563556 kb
Host	smart-cd23aca3-69fc-4172-861b-13ee9c713e08
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082321314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.2082321314
Directory	/workspace/99.xbar_smoke/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.4158594464
Short name	T2648
Test name
Test status
Simulation time	6647607139 ps
CPU time	72.35 seconds
Started	May 23 04:40:22 PM PDT 24
Finished	May 23 04:41:36 PM PDT 24
Peak memory	563684 kb
Host	smart-556d897b-215b-4703-befb-241a4989f5a7
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158594464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.4158594464
Directory	/workspace/99.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2726835227
Short name	T2512
Test name
Test status
Simulation time	2533669789 ps
CPU time	45.18 seconds
Started	May 23 04:40:23 PM PDT 24
Finished	May 23 04:41:09 PM PDT 24
Peak memory	563732 kb
Host	smart-0e1c3457-6b3a-4700-b87a-b34617f1d1df
User	root
Command	/workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726835227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2726835227
Directory	/workspace/99.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.578413952
Short name	T1547
Test name
Test status
Simulation time	57621454 ps
CPU time	6.72 seconds
Started	May 23 04:40:21 PM PDT 24
Finished	May 23 04:40:29 PM PDT 24
Peak memory	563596 kb
Host	smart-fff1bda0-d981-4119-9195-35f05f81346e
User	root
Command	/workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578413952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays .578413952
Directory	/workspace/99.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all.3846234942
Short name	T2287
Test name
Test status
Simulation time	12415458410 ps
CPU time	504.08 seconds
Started	May 23 04:40:32 PM PDT 24
Finished	May 23 04:48:57 PM PDT 24
Peak memory	573048 kb
Host	smart-3410f276-67f1-46f5-8fd3-6a4105f24aa0
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846234942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.3846234942
Directory	/workspace/99.xbar_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.2084816058
Short name	T2646
Test name
Test status
Simulation time	620510259 ps
CPU time	64.48 seconds
Started	May 23 04:40:36 PM PDT 24
Finished	May 23 04:41:41 PM PDT 24
Peak memory	571916 kb
Host	smart-9d07aa0b-bf1b-4627-8f95-85a50cb71109
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084816058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.2084816058
Directory	/workspace/99.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3712679970
Short name	T619
Test name
Test status
Simulation time	3567529947 ps
CPU time	288.92 seconds
Started	May 23 04:40:35 PM PDT 24
Finished	May 23 04:45:25 PM PDT 24
Peak memory	574108 kb
Host	smart-528ed78b-4bd4-475b-bd72-6bad23df1188
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712679970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.3712679970
Directory	/workspace/99.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3227224682
Short name	T818
Test name
Test status
Simulation time	14744310435 ps
CPU time	769.94 seconds
Started	May 23 04:40:33 PM PDT 24
Finished	May 23 04:53:24 PM PDT 24
Peak memory	574152 kb
Host	smart-958602cf-6d1d-4b02-99b5-d074882ff120
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227224682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.3227224682
Directory	/workspace/99.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.3570125629
Short name	T609
Test name
Test status
Simulation time	287907553 ps
CPU time	12.3 seconds
Started	May 23 04:40:35 PM PDT 24
Finished	May 23 04:40:49 PM PDT 24
Peak memory	571816 kb
Host	smart-8c37215a-c526-4fae-bdc6-673ab49907b4
User	root
Command	/workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570125629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.3570125629
Directory	/workspace/99.xbar_unmapped_addr/latest

Test location	/workspace/coverage/default/0.chip_jtag_csr_rw.2378952968
Short name	T169
Test name
Test status
Simulation time	4182865364 ps
CPU time	222.53 seconds
Started	May 23 03:48:17 PM PDT 24
Finished	May 23 03:52:02 PM PDT 24
Peak memory	603876 kb
Host	smart-cf72bc78-1590-4df1-b950-d1e6a6b527c5
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378952968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.2378952968
Directory	/workspace/0.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2954189339
Short name	T48
Test name
Test status
Simulation time	3931779480 ps
CPU time	296.74 seconds
Started	May 23 04:04:21 PM PDT 24
Finished	May 23 04:09:19 PM PDT 24
Peak memory	611216 kb
Host	smart-fb2e34eb-13f6-4468-bb80-e40f68287758
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 954189339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.2954189339
Directory	/workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/0.chip_sival_flash_info_access.4161139894
Short name	T312
Test name
Test status
Simulation time	3314156012 ps
CPU time	359.87 seconds
Started	May 23 03:59:17 PM PDT 24
Finished	May 23 04:05:19 PM PDT 24
Peak memory	601516 kb
Host	smart-fc298d8e-e776-4a63-9c06-bcafb99ff42d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4161139894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.4161139894
Directory	/workspace/0.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc.165385007
Short name	T932
Test name
Test status
Simulation time	2798572482 ps
CPU time	269.08 seconds
Started	May 23 03:58:56 PM PDT 24
Finished	May 23 04:03:27 PM PDT 24
Peak memory	601380 kb
Host	smart-0af05de5-2c79-4333-8ea7-e93ff0bd7572
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165385007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.165385007
Directory	/workspace/0.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.211340581
Short name	T257
Test name
Test status
Simulation time	2031496365 ps
CPU time	251.62 seconds
Started	May 23 04:02:13 PM PDT 24
Finished	May 23 04:06:28 PM PDT 24
Peak memory	601452 kb
Host	smart-3c919d15-c23d-4485-bf8a-64206d633ba0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113 40581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.211340581
Directory	/workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1562409936
Short name	T864
Test name
Test status
Simulation time	2770593270 ps
CPU time	237.2 seconds
Started	May 23 04:04:10 PM PDT 24
Finished	May 23 04:08:09 PM PDT 24
Peak memory	601516 kb
Host	smart-24ecd0d6-3d11-48f2-9e80-b8894ca285ad
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562409936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.1562409936
Directory	/workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_entropy.4049777822
Short name	T900
Test name
Test status
Simulation time	2999682600 ps
CPU time	248.3 seconds
Started	May 23 04:00:30 PM PDT 24
Finished	May 23 04:04:39 PM PDT 24
Peak memory	601512 kb
Host	smart-2bd26846-5362-441e-8f09-ff59b20aa904
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049777822 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.4049777822
Directory	/workspace/0.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_idle.1587541514
Short name	T952
Test name
Test status
Simulation time	2492660000 ps
CPU time	199.45 seconds
Started	May 23 04:04:54 PM PDT 24
Finished	May 23 04:08:16 PM PDT 24
Peak memory	601536 kb
Host	smart-64ead50f-a48a-42ee-878f-eed486f7ebec
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587541514 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1587541514
Directory	/workspace/0.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_masking_off.970259786
Short name	T1152
Test name
Test status
Simulation time	2633532247 ps
CPU time	287.86 seconds
Started	May 23 03:59:05 PM PDT 24
Finished	May 23 04:03:54 PM PDT 24
Peak memory	601716 kb
Host	smart-c9ce778a-47c7-4d11-b917-20474878d4a4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970259786 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.970259786
Directory	/workspace/0.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_smoketest.1253839568
Short name	T923
Test name
Test status
Simulation time	2959045918 ps
CPU time	294.63 seconds
Started	May 23 04:02:41 PM PDT 24
Finished	May 23 04:07:37 PM PDT 24
Peak memory	601488 kb
Host	smart-6420e789-7a54-4bab-a226-0eff72e3572f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253839568 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.1253839568
Directory	/workspace/0.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.4107037679
Short name	T71
Test name
Test status
Simulation time	2777638632 ps
CPU time	287.32 seconds
Started	May 23 04:00:28 PM PDT 24
Finished	May 23 04:05:17 PM PDT 24
Peak memory	602296 kb
Host	smart-6a32f2f6-c4e7-4d9c-b145-ff24c80101b3
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4107037679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.4107037679
Directory	/workspace/0.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.587148187
Short name	T1091
Test name
Test status
Simulation time	4414464288 ps
CPU time	403.75 seconds
Started	May 23 03:58:05 PM PDT 24
Finished	May 23 04:04:49 PM PDT 24
Peak memory	609036 kb
Host	smart-bc0cb26a-31e0-447e-93bf-2124503c1bc7
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=587148187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.587148187
Directory	/workspace/0.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.135472643
Short name	T341
Test name
Test status
Simulation time	7070866172 ps
CPU time	1399.22 seconds
Started	May 23 04:07:28 PM PDT 24
Finished	May 23 04:30:48 PM PDT 24
Peak memory	601896 kb
Host	smart-8819ea55-025e-4ed8-ab8c-b460ce24f020
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135472643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.135472643
Directory	/workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.570894298
Short name	T916
Test name
Test status
Simulation time	4426639612 ps
CPU time	481.86 seconds
Started	May 23 04:03:15 PM PDT 24
Finished	May 23 04:11:18 PM PDT 24
Peak memory	601884 kb
Host	smart-42a05fad-5e3b-4da4-98bf-29f6b9546be7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=570894298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.570894298
Directory	/workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1198815107
Short name	T1225
Test name
Test status
Simulation time	255247116380 ps
CPU time	11174.1 seconds
Started	May 23 04:07:18 PM PDT 24
Finished	May 23 07:13:34 PM PDT 24
Peak memory	602312 kb
Host	smart-af6decc8-8b12-40d8-8c0c-7f287d339774
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1198815107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1198815107
Directory	/workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_test.1189015975
Short name	T96
Test name
Test status
Simulation time	3019705520 ps
CPU time	300.37 seconds
Started	May 23 03:58:05 PM PDT 24
Finished	May 23 04:03:07 PM PDT 24
Peak memory	601700 kb
Host	smart-471db557-2a60-4360-8720-cde0ec6893c4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189015975 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.1189015975
Directory	/workspace/0.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1276621290
Short name	T918
Test name
Test status
Simulation time	4155537560 ps
CPU time	470.26 seconds
Started	May 23 04:02:03 PM PDT 24
Finished	May 23 04:09:56 PM PDT 24
Peak memory	601648 kb
Host	smart-a2a5550b-a892-4ef5-b485-649119ecd502
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276621290 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1276621290
Directory	/workspace/0.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.551135842
Short name	T890
Test name
Test status
Simulation time	6557455640 ps
CPU time	345.44 seconds
Started	May 23 03:58:20 PM PDT 24
Finished	May 23 04:04:08 PM PDT 24
Peak memory	602152 kb
Host	smart-e542dd47-f3b5-4f5a-b642-1fc4457d15e5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=551135842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.551135842
Directory	/workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.498478329
Short name	T870
Test name
Test status
Simulation time	2811556620 ps
CPU time	399.39 seconds
Started	May 23 04:02:46 PM PDT 24
Finished	May 23 04:09:27 PM PDT 24
Peak memory	601648 kb
Host	smart-56098bfe-ebe1-4f19-9a4e-e49d6fd79bc1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498478329 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_aon_timer_smoketest.498478329
Directory	/workspace/0.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2456632187
Short name	T1041
Test name
Test status
Simulation time	9239191060 ps
CPU time	793.49 seconds
Started	May 23 04:06:03 PM PDT 24
Finished	May 23 04:19:18 PM PDT 24
Peak memory	602140 kb
Host	smart-916f2ad1-9f26-4f8d-a157-75cf8260921f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2456632187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2456632187
Directory	/workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1228871583
Short name	T315
Test name
Test status
Simulation time	5847697900 ps
CPU time	706.66 seconds
Started	May 23 03:57:59 PM PDT 24
Finished	May 23 04:09:49 PM PDT 24
Peak memory	602280 kb
Host	smart-089f53c6-1260-4bca-a8e3-9532080d2070
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1228871583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.1228871583
Directory	/workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3595499650
Short name	T856
Test name
Test status
Simulation time	7443600088 ps
CPU time	957.31 seconds
Started	May 23 04:04:13 PM PDT 24
Finished	May 23 04:20:12 PM PDT 24
Peak memory	608484 kb
Host	smart-e6f39b3c-af07-4d07-a906-c395be8c065b
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595499650 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.3595499650
Directory	/workspace/0.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2513981794
Short name	T1012
Test name
Test status
Simulation time	3661537888 ps
CPU time	647.49 seconds
Started	May 23 03:58:19 PM PDT 24
Finished	May 23 04:09:08 PM PDT 24
Peak memory	604888 kb
Host	smart-3cc8dab1-e499-4095-98fe-7d54ffc7bc22
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513981794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2513981794
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.448382768
Short name	T906
Test name
Test status
Simulation time	4119598908 ps
CPU time	577.23 seconds
Started	May 23 04:02:34 PM PDT 24
Finished	May 23 04:12:14 PM PDT 24
Peak memory	604880 kb
Host	smart-a1b8c77a-849b-4191-9249-415a89e1c253
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448382768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.448382768
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2372539069
Short name	T1169
Test name
Test status
Simulation time	4313086688 ps
CPU time	775.36 seconds
Started	May 23 04:02:13 PM PDT 24
Finished	May 23 04:15:11 PM PDT 24
Peak memory	604936 kb
Host	smart-06f17bc5-086f-44a0-ab29-402c63b0703d
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372539069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2372539069
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1687979131
Short name	T968
Test name
Test status
Simulation time	5086347496 ps
CPU time	642.88 seconds
Started	May 23 03:58:19 PM PDT 24
Finished	May 23 04:09:04 PM PDT 24
Peak memory	604928 kb
Host	smart-95a26f5b-02bb-4cb9-a3ac-4b3963845837
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687979131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1687979131
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4143174928
Short name	T896
Test name
Test status
Simulation time	4640211984 ps
CPU time	640.5 seconds
Started	May 23 04:04:49 PM PDT 24
Finished	May 23 04:15:31 PM PDT 24
Peak memory	604872 kb
Host	smart-46b23e16-ac93-43ba-bd1c-7fb3700358c4
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143174928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4143174928
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3701458181
Short name	T1042
Test name
Test status
Simulation time	3170396967 ps
CPU time	150.37 seconds
Started	May 23 03:58:12 PM PDT 24
Finished	May 23 04:00:43 PM PDT 24
Peak memory	601552 kb
Host	smart-d9b0d899-0b93-4c91-949e-dcce32a672b0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701458181 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.3701458181
Directory	/workspace/0.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1236746618
Short name	T340
Test name
Test status
Simulation time	3744413432 ps
CPU time	463.41 seconds
Started	May 23 03:59:11 PM PDT 24
Finished	May 23 04:06:56 PM PDT 24
Peak memory	601532 kb
Host	smart-5f0e0ea9-4bff-4e4d-bfd2-c0cea745f8a5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236746618 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.1236746618
Directory	/workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1403851439
Short name	T143
Test name
Test status
Simulation time	2910026649 ps
CPU time	199.97 seconds
Started	May 23 04:00:27 PM PDT 24
Finished	May 23 04:03:49 PM PDT 24
Peak memory	601304 kb
Host	smart-5db03674-aacf-4b44-b471-e427ce78ef01
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403851439 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1403851439
Directory	/workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2432002095
Short name	T1145
Test name
Test status
Simulation time	5620400040 ps
CPU time	495.28 seconds
Started	May 23 04:03:38 PM PDT 24
Finished	May 23 04:11:55 PM PDT 24
Peak memory	601880 kb
Host	smart-2241117c-2a4b-4857-bd7b-33b0dda758f3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432002095 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.2432002095
Directory	/workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1645860622
Short name	T862
Test name
Test status
Simulation time	5603912908 ps
CPU time	432.66 seconds
Started	May 23 04:00:42 PM PDT 24
Finished	May 23 04:07:56 PM PDT 24
Peak memory	601772 kb
Host	smart-d3a5ef46-9bda-4882-bbbe-463ed93fa61b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645860622 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.1645860622
Directory	/workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3581975180
Short name	T1178
Test name
Test status
Simulation time	4412512612 ps
CPU time	374.94 seconds
Started	May 23 04:02:05 PM PDT 24
Finished	May 23 04:08:22 PM PDT 24
Peak memory	601888 kb
Host	smart-2a5f4e6c-d5d4-420e-86be-153a80c05be4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581975180 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.3581975180
Directory	/workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3512767807
Short name	T1205
Test name
Test status
Simulation time	4452157248 ps
CPU time	394.2 seconds
Started	May 23 04:00:51 PM PDT 24
Finished	May 23 04:07:29 PM PDT 24
Peak memory	602148 kb
Host	smart-9ebdcb0c-84bb-453c-bab8-f2ab8c857f32
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512767807 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.3512767807
Directory	/workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2293658308
Short name	T1186
Test name
Test status
Simulation time	11572148010 ps
CPU time	1236.68 seconds
Started	May 23 04:00:40 PM PDT 24
Finished	May 23 04:21:19 PM PDT 24
Peak memory	603304 kb
Host	smart-d520f326-8e1b-47a4-879e-f78b98ce1abc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293658308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2293658308
Directory	/workspace/0.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3545724893
Short name	T1010
Test name
Test status
Simulation time	3172506167 ps
CPU time	377.55 seconds
Started	May 23 03:59:47 PM PDT 24
Finished	May 23 04:06:06 PM PDT 24
Peak memory	601608 kb
Host	smart-f5c09f8a-a006-49f3-b502-cb20155dffd2
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545724893 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.3545724893
Directory	/workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1300802558
Short name	T1195
Test name
Test status
Simulation time	4317771294 ps
CPU time	690.73 seconds
Started	May 23 04:04:20 PM PDT 24
Finished	May 23 04:15:52 PM PDT 24
Peak memory	601904 kb
Host	smart-ae6b092c-8aa1-459a-9b1a-78fc4b8b6cce
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300802558 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1300802558
Directory	/workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4133798021
Short name	T969
Test name
Test status
Simulation time	2478941160 ps
CPU time	268.02 seconds
Started	May 23 04:02:29 PM PDT 24
Finished	May 23 04:06:59 PM PDT 24
Peak memory	601444 kb
Host	smart-1146b538-7444-4e70-a96f-4d9b28caf719
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133798021 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.4133798021
Directory	/workspace/0.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.822756373
Short name	T286
Test name
Test status
Simulation time	12210629176 ps
CPU time	2976.09 seconds
Started	May 23 04:01:56 PM PDT 24
Finished	May 23 04:51:34 PM PDT 24
Peak memory	601856 kb
Host	smart-6e87e81e-f117-4a7d-967b-aaffa7428f06
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822756373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.822756373
Directory	/workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1835241400
Short name	T94
Test name
Test status
Simulation time	5204633160 ps
CPU time	438.55 seconds
Started	May 23 04:04:58 PM PDT 24
Finished	May 23 04:12:18 PM PDT 24
Peak memory	602192 kb
Host	smart-0c08a947-0a2c-4b2a-8258-22b0ffe7a8e9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18352 41400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1835241400
Directory	/workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_kat_test.1452030145
Short name	T964
Test name
Test status
Simulation time	2919131000 ps
CPU time	203.07 seconds
Started	May 23 03:57:53 PM PDT 24
Finished	May 23 04:01:18 PM PDT 24
Peak memory	601556 kb
Host	smart-3122b1ec-2e13-4a54-a9f1-031e43e022bb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452030145 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.1452030145
Directory	/workspace/0.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2014454578
Short name	T61
Test name
Test status
Simulation time	7579874925 ps
CPU time	715.66 seconds
Started	May 23 03:58:11 PM PDT 24
Finished	May 23 04:10:08 PM PDT 24
Peak memory	602220 kb
Host	smart-b1a78dd1-0ecd-4377-8637-68f502bfe606
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014454578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.2014454578
Directory	/workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_smoketest.377935141
Short name	T346
Test name
Test status
Simulation time	3290057880 ps
CPU time	329.99 seconds
Started	May 23 04:01:13 PM PDT 24
Finished	May 23 04:06:45 PM PDT 24
Peak memory	601488 kb
Host	smart-e2099188-0588-4605-a7d5-203271c06d93
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377935141 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_csrng_smoketest.377935141
Directory	/workspace/0.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1698410492
Short name	T182
Test name
Test status
Simulation time	6962826364 ps
CPU time	1452.18 seconds
Started	May 23 04:00:50 PM PDT 24
Finished	May 23 04:25:06 PM PDT 24
Peak memory	602700 kb
Host	smart-a1b5e97f-3d44-4af3-9f7c-c9c5fe8a7705
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698410492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.1698410492
Directory	/workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_kat.486297185
Short name	T1029
Test name
Test status
Simulation time	3628664472 ps
CPU time	709.28 seconds
Started	May 23 03:59:13 PM PDT 24
Finished	May 23 04:11:04 PM PDT 24
Peak memory	608020 kb
Host	smart-3851f050-e4a6-4282-b1ab-ba8a0b7a2747
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486297185 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_edn_kat.486297185
Directory	/workspace/0.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.670738701
Short name	T1123
Test name
Test status
Simulation time	2693903888 ps
CPU time	314.58 seconds
Started	May 23 04:00:44 PM PDT 24
Finished	May 23 04:06:01 PM PDT 24
Peak memory	601652 kb
Host	smart-8384e351-998b-4434-b478-95aa55a4b3fc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67 0738701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.670738701
Directory	/workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2348227413
Short name	T850
Test name
Test status
Simulation time	2862450120 ps
CPU time	184.28 seconds
Started	May 23 03:59:31 PM PDT 24
Finished	May 23 04:02:37 PM PDT 24
Peak memory	601476 kb
Host	smart-34c5beb6-0459-4ee7-be07-381adb741e01
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348227413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.2348227413
Directory	/workspace/0.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1993731134
Short name	T1175
Test name
Test status
Simulation time	2782976104 ps
CPU time	398.21 seconds
Started	May 23 04:00:32 PM PDT 24
Finished	May 23 04:07:13 PM PDT 24
Peak memory	601508 kb
Host	smart-da8cc1f6-e34c-449b-b573-ec7cfe253f81
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1993731134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.1993731134
Directory	/workspace/0.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_example_concurrency.4234552421
Short name	T959
Test name
Test status
Simulation time	2687742920 ps
CPU time	259.93 seconds
Started	May 23 03:59:31 PM PDT 24
Finished	May 23 04:03:53 PM PDT 24
Peak memory	601520 kb
Host	smart-f12a64c1-8975-4dc5-907b-7aa436f0e69a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234552421 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.4234552421
Directory	/workspace/0.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_example_flash.891040083
Short name	T1147
Test name
Test status
Simulation time	2451209150 ps
CPU time	239.68 seconds
Started	May 23 03:58:56 PM PDT 24
Finished	May 23 04:02:57 PM PDT 24
Peak memory	601596 kb
Host	smart-c5c9b22e-80ce-4e10-8987-4ccdd98928d4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891040083 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.891040083
Directory	/workspace/0.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/0.chip_sw_example_manufacturer.164448810
Short name	T1179
Test name
Test status
Simulation time	2661909570 ps
CPU time	234.99 seconds
Started	May 23 03:57:49 PM PDT 24
Finished	May 23 04:01:45 PM PDT 24
Peak memory	601232 kb
Host	smart-16363abf-c4da-4af2-90d5-7d911aa53af9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164448810 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_example_manufacturer.164448810
Directory	/workspace/0.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/0.chip_sw_example_rom.825167493
Short name	T337
Test name
Test status
Simulation time	2577688140 ps
CPU time	137.63 seconds
Started	May 23 03:56:19 PM PDT 24
Finished	May 23 03:58:39 PM PDT 24
Peak memory	601380 kb
Host	smart-dd25e072-1c5d-4eb4-a64a-2ea68a77cdbc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825167493 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_example_rom.825167493
Directory	/workspace/0.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1722532746
Short name	T1119
Test name
Test status
Simulation time	5779949608 ps
CPU time	601.85 seconds
Started	May 23 04:04:22 PM PDT 24
Finished	May 23 04:14:25 PM PDT 24
Peak memory	603884 kb
Host	smart-8c9e8ad6-e3a5-4b14-a505-7c8059a47fb7
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1722532746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1722532746
Directory	/workspace/0.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2839674198
Short name	T1136
Test name
Test status
Simulation time	6101748080 ps
CPU time	1074.15 seconds
Started	May 23 03:59:46 PM PDT 24
Finished	May 23 04:17:42 PM PDT 24
Peak memory	601800 kb
Host	smart-55a506e5-8e03-4df4-b971-94d53b075e2c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839674198 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.2839674198
Directory	/workspace/0.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.229246014
Short name	T344
Test name
Test status
Simulation time	6245381815 ps
CPU time	1189.83 seconds
Started	May 23 04:00:18 PM PDT 24
Finished	May 23 04:20:10 PM PDT 24
Peak memory	601628 kb
Host	smart-ffe7bce6-8fdb-4777-b588-853e8040ef8d
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229246014 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.229246014
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2680988558
Short name	T1071
Test name
Test status
Simulation time	7541106363 ps
CPU time	1227.84 seconds
Started	May 23 04:04:21 PM PDT 24
Finished	May 23 04:24:50 PM PDT 24
Peak memory	601884 kb
Host	smart-d828a160-a311-4805-8d38-5146e9de5fa3
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680988558 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2680988558
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.801352687
Short name	T1082
Test name
Test status
Simulation time	5785572305 ps
CPU time	995.65 seconds
Started	May 23 04:02:28 PM PDT 24
Finished	May 23 04:19:06 PM PDT 24
Peak memory	601796 kb
Host	smart-3906c8b1-1fab-4e20-9fb7-65dbc2896b8e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801352687 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.801352687
Directory	/workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2608105085
Short name	T273
Test name
Test status
Simulation time	3275670300 ps
CPU time	372.57 seconds
Started	May 23 04:04:18 PM PDT 24
Finished	May 23 04:10:32 PM PDT 24
Peak memory	601400 kb
Host	smart-ea23dca6-992b-4b88-a36c-8f1939522f64
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608105085 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.2608105085
Directory	/workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2846523324
Short name	T1207
Test name
Test status
Simulation time	5807208340 ps
CPU time	1163.34 seconds
Started	May 23 04:03:20 PM PDT 24
Finished	May 23 04:22:44 PM PDT 24
Peak memory	601816 kb
Host	smart-4978b0f1-6fc6-4748-841e-7cac2e186e0f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846523324 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.2846523324
Directory	/workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1894720570
Short name	T247
Test name
Test status
Simulation time	4878760012 ps
CPU time	820.72 seconds
Started	May 23 04:00:53 PM PDT 24
Finished	May 23 04:14:37 PM PDT 24
Peak memory	601948 kb
Host	smart-34c52c86-f767-4bc1-b726-2912880e82f8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894720570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.1894720570
Directory	/workspace/0.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3942151220
Short name	T1069
Test name
Test status
Simulation time	4105402781 ps
CPU time	735.27 seconds
Started	May 23 03:58:51 PM PDT 24
Finished	May 23 04:11:08 PM PDT 24
Peak memory	601412 kb
Host	smart-b8dde1e0-972c-443e-8b70-90a286f34ade
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3942151220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.3942151220
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2334845035
Short name	T393
Test name
Test status
Simulation time	2312510024 ps
CPU time	261.09 seconds
Started	May 23 04:06:52 PM PDT 24
Finished	May 23 04:11:14 PM PDT 24
Peak memory	601564 kb
Host	smart-f0ac6002-18d1-46cb-a025-973f0790906d
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334845 035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.2334845035
Directory	/workspace/0.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.4164117228
Short name	T885
Test name
Test status
Simulation time	2461900874 ps
CPU time	228.05 seconds
Started	May 23 04:07:12 PM PDT 24
Finished	May 23 04:11:02 PM PDT 24
Peak memory	602956 kb
Host	smart-db70aa13-345f-4052-8459-681fe7e940f8
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4164117228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.4164117228
Directory	/workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_gpio_smoketest.166915889
Short name	T193
Test name
Test status
Simulation time	2748387739 ps
CPU time	271.3 seconds
Started	May 23 04:01:10 PM PDT 24
Finished	May 23 04:05:43 PM PDT 24
Peak memory	601624 kb
Host	smart-45e0e6b3-f086-4586-b1e4-0ead362f666a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166915889 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_gpio_smoketest.166915889
Directory	/workspace/0.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.480853261
Short name	T1093
Test name
Test status
Simulation time	2906271384 ps
CPU time	258.15 seconds
Started	May 23 04:00:01 PM PDT 24
Finished	May 23 04:04:21 PM PDT 24
Peak memory	601304 kb
Host	smart-32a6d4f8-502a-40d4-8aa3-58b3eb5fb809
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480853261 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_hmac_enc_idle.480853261
Directory	/workspace/0.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3364920302
Short name	T1107
Test name
Test status
Simulation time	2210687467 ps
CPU time	240.21 seconds
Started	May 23 04:04:28 PM PDT 24
Finished	May 23 04:08:30 PM PDT 24
Peak memory	601396 kb
Host	smart-f96b0b6b-6954-43fd-acc7-29caa33586f4
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364920302 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3364920302
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2756945468
Short name	T319
Test name
Test status
Simulation time	2344349983 ps
CPU time	224.35 seconds
Started	May 23 04:01:23 PM PDT 24
Finished	May 23 04:05:10 PM PDT 24
Peak memory	601720 kb
Host	smart-b7ef4f62-f250-4778-b9b8-ca3ff4b4da20
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756945468 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.2756945468
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_smoketest.4037525851
Short name	T1053
Test name
Test status
Simulation time	3097608246 ps
CPU time	339.58 seconds
Started	May 23 04:02:05 PM PDT 24
Finished	May 23 04:07:46 PM PDT 24
Peak memory	601480 kb
Host	smart-ad01a059-0fe2-47a8-8c5f-037dc24caaf5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037525851 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.4037525851
Directory	/workspace/0.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.365896873
Short name	T322
Test name
Test status
Simulation time	4337129128 ps
CPU time	636.59 seconds
Started	May 23 04:04:57 PM PDT 24
Finished	May 23 04:15:36 PM PDT 24
Peak memory	602732 kb
Host	smart-fd2000b6-06ab-4f0e-9287-8a68154aca35
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365896873 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.365896873
Directory	/workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.787948197
Short name	T345
Test name
Test status
Simulation time	63174668502 ps
CPU time	11579.7 seconds
Started	May 23 04:00:12 PM PDT 24
Finished	May 23 07:13:15 PM PDT 24
Peak memory	620356 kb
Host	smart-47eb9b7d-5c66-49cc-94ed-bfe462ad4083
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=787948197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.787948197
Directory	/workspace/0.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.574859296
Short name	T1109
Test name
Test status
Simulation time	7715768846 ps
CPU time	1556.84 seconds
Started	May 23 03:59:01 PM PDT 24
Finished	May 23 04:24:59 PM PDT 24
Peak memory	609404 kb
Host	smart-eec23229-dd9f-4e43-b334-554c2f643aaf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=574859296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.574859296
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2970396935
Short name	T1106
Test name
Test status
Simulation time	9502833850 ps
CPU time	2197.2 seconds
Started	May 23 03:58:51 PM PDT 24
Finished	May 23 04:35:29 PM PDT 24
Peak memory	609112 kb
Host	smart-96af1150-32e1-4686-aff0-820330be1b55
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2970396935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.2970396935
Directory	/workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.956880757
Short name	T212
Test name
Test status
Simulation time	8396296018 ps
CPU time	1859.58 seconds
Started	May 23 04:05:28 PM PDT 24
Finished	May 23 04:36:29 PM PDT 24
Peak memory	602600 kb
Host	smart-97749961-f902-4949-9ce9-a9562a3f63ea
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956880 757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.956880757
Directory	/workspace/0.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1852491872
Short name	T209
Test name
Test status
Simulation time	5851086448 ps
CPU time	1130.99 seconds
Started	May 23 03:59:28 PM PDT 24
Finished	May 23 04:18:21 PM PDT 24
Peak memory	602768 kb
Host	smart-e91080de-7380-4434-bea0-c16c7a336ebd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18524 91872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.1852491872
Directory	/workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2730072494
Short name	T214
Test name
Test status
Simulation time	17607146184 ps
CPU time	4034.25 seconds
Started	May 23 04:04:57 PM PDT 24
Finished	May 23 05:12:13 PM PDT 24
Peak memory	603696 kb
Host	smart-32cc2137-4914-4897-a0c9-1a8ff7ed60df
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27300 72494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2730072494
Directory	/workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_app_rom.3309042807
Short name	T377
Test name
Test status
Simulation time	3145055438 ps
CPU time	218.28 seconds
Started	May 23 04:01:34 PM PDT 24
Finished	May 23 04:05:15 PM PDT 24
Peak memory	601476 kb
Host	smart-8c8d708f-6f4c-4596-a006-dc9cd3993190
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309042807 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.3309042807
Directory	/workspace/0.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_idle.2968444946
Short name	T892
Test name
Test status
Simulation time	2769277752 ps
CPU time	283.2 seconds
Started	May 23 04:06:55 PM PDT 24
Finished	May 23 04:11:39 PM PDT 24
Peak memory	601456 kb
Host	smart-af367f74-7a4e-44e9-9275-6974d6f8f785
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968444946 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2968444946
Directory	/workspace/0.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1857811683
Short name	T919
Test name
Test status
Simulation time	2766805904 ps
CPU time	252.69 seconds
Started	May 23 04:01:18 PM PDT 24
Finished	May 23 04:05:32 PM PDT 24
Peak memory	601372 kb
Host	smart-2e99ce11-17e8-4bfd-b8b4-737c3ac6e477
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857811683 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.1857811683
Directory	/workspace/0.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.404215087
Short name	T1065
Test name
Test status
Simulation time	2529169036 ps
CPU time	424.27 seconds
Started	May 23 03:59:49 PM PDT 24
Finished	May 23 04:06:55 PM PDT 24
Peak memory	601472 kb
Host	smart-d89c9cde-61b3-4b91-8e98-85ad28b6f12b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404215087 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_kmac_mode_kmac.404215087
Directory	/workspace/0.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3440145988
Short name	T955
Test name
Test status
Simulation time	3279742079 ps
CPU time	349.49 seconds
Started	May 23 04:01:45 PM PDT 24
Finished	May 23 04:07:36 PM PDT 24
Peak memory	601552 kb
Host	smart-0072c75f-343b-4776-9148-30f31dff1c2a
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440145988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.3440145988
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2940302535
Short name	T886
Test name
Test status
Simulation time	3126985981 ps
CPU time	279.13 seconds
Started	May 23 04:01:57 PM PDT 24
Finished	May 23 04:06:38 PM PDT 24
Peak memory	601540 kb
Host	smart-33a80acb-2f48-465c-9759-74eab6a9fb65
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403025 35 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2940302535
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_smoketest.2896933041
Short name	T1184
Test name
Test status
Simulation time	2792031880 ps
CPU time	250.76 seconds
Started	May 23 04:01:35 PM PDT 24
Finished	May 23 04:05:48 PM PDT 24
Peak memory	601480 kb
Host	smart-735efdd9-b4f0-4df9-a75c-4b3df1af23fa
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896933041 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.2896933041
Directory	/workspace/0.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1685929546
Short name	T860
Test name
Test status
Simulation time	3680571096 ps
CPU time	352.63 seconds
Started	May 23 04:04:00 PM PDT 24
Finished	May 23 04:09:54 PM PDT 24
Peak memory	601444 kb
Host	smart-3dede88c-1132-4b79-a707-fb7393de9a65
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685929546 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.1685929546
Directory	/workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.984843716
Short name	T124
Test name
Test status
Simulation time	17018446100 ps
CPU time	3527.42 seconds
Started	May 23 04:03:14 PM PDT 24
Finished	May 23 05:02:03 PM PDT 24
Peak memory	602120 kb
Host	smart-24cee19b-ff38-4cca-81e4-8b20fda934bf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=984843716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.984843716
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1591661178
Short name	T887
Test name
Test status
Simulation time	18456005934 ps
CPU time	4659.17 seconds
Started	May 23 04:02:57 PM PDT 24
Finished	May 23 05:20:38 PM PDT 24
Peak memory	602104 kb
Host	smart-e50fae6c-d9ad-49f6-aa23-d878b7515196
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1591661178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1591661178
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1184351149
Short name	T262
Test name
Test status
Simulation time	3799636878 ps
CPU time	507.67 seconds
Started	May 23 04:01:04 PM PDT 24
Finished	May 23 04:09:33 PM PDT 24
Peak memory	601352 kb
Host	smart-81e24159-a95d-4943-a660-974045f37acd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184351149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1184351149
Directory	/workspace/0.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_smoketest.2638108970
Short name	T877
Test name
Test status
Simulation time	11752998510 ps
CPU time	2683.2 seconds
Started	May 23 04:02:01 PM PDT 24
Finished	May 23 04:46:46 PM PDT 24
Peak memory	602036 kb
Host	smart-b3ab3842-5289-491b-8187-da98acee7901
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638108970 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.2638108970
Directory	/workspace/0.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3014646117
Short name	T1036
Test name
Test status
Simulation time	2934878009 ps
CPU time	339.44 seconds
Started	May 23 04:00:46 PM PDT 24
Finished	May 23 04:06:27 PM PDT 24
Peak memory	601496 kb
Host	smart-e7bad092-c840-41f6-baea-dc001fad4ffb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014646117 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3014646117
Directory	/workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3826597575
Short name	T1017
Test name
Test status
Simulation time	6972345200 ps
CPU time	1088.05 seconds
Started	May 23 03:58:10 PM PDT 24
Finished	May 23 04:16:19 PM PDT 24
Peak memory	602380 kb
Host	smart-c8a91d73-ea8e-4100-b812-0a4f0396e534
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3826597575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.3826597575
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1800004569
Short name	T179
Test name
Test status
Simulation time	8237261182 ps
CPU time	1076.73 seconds
Started	May 23 04:01:41 PM PDT 24
Finished	May 23 04:19:39 PM PDT 24
Peak memory	603492 kb
Host	smart-0403a05e-52ed-43ab-af46-f366b4a48be7
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1800004569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1800004569
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3951522253
Short name	T1083
Test name
Test status
Simulation time	7515585772 ps
CPU time	1176.35 seconds
Started	May 23 04:01:07 PM PDT 24
Finished	May 23 04:20:44 PM PDT 24
Peak memory	602092 kb
Host	smart-eb5e2a34-972f-46eb-a7e4-c56a4c0bbac0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3951522253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3951522253
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2382658422
Short name	T81
Test name
Test status
Simulation time	3646357080 ps
CPU time	738.04 seconds
Started	May 23 03:59:03 PM PDT 24
Finished	May 23 04:11:22 PM PDT 24
Peak memory	601620 kb
Host	smart-a982b4d8-821f-4829-9c6a-2494280029a8
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2382658422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2382658422
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3931358708
Short name	T1098
Test name
Test status
Simulation time	2572148638 ps
CPU time	305.18 seconds
Started	May 23 04:01:05 PM PDT 24
Finished	May 23 04:06:11 PM PDT 24
Peak memory	601648 kb
Host	smart-89920c6d-0739-4b54-9350-0bff5c974f22
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931358708 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.3931358708
Directory	/workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pattgen_ios.3980125009
Short name	T314
Test name
Test status
Simulation time	3145589880 ps
CPU time	255.33 seconds
Started	May 23 04:01:08 PM PDT 24
Finished	May 23 04:05:26 PM PDT 24
Peak memory	602160 kb
Host	smart-6f998490-cffd-41dd-8243-e32c27f70ab8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980125009 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3980125009
Directory	/workspace/0.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/0.chip_sw_power_idle_load.3163146427
Short name	T1131
Test name
Test status
Simulation time	4153153388 ps
CPU time	757.92 seconds
Started	May 23 04:03:11 PM PDT 24
Finished	May 23 04:15:51 PM PDT 24
Peak memory	601916 kb
Host	smart-1d112b3c-5407-4e4a-a7b9-3cb30ca9c25d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163146427 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.3163146427
Directory	/workspace/0.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.200436647
Short name	T1121
Test name
Test status
Simulation time	11241898157 ps
CPU time	2146.75 seconds
Started	May 23 04:00:20 PM PDT 24
Finished	May 23 04:36:08 PM PDT 24
Peak memory	603160 kb
Host	smart-e6211260-a320-4ae5-82e8-9e18df7d4070
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004 36647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.200436647
Directory	/workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1547096707
Short name	T1223
Test name
Test status
Simulation time	22818991558 ps
CPU time	2401.5 seconds
Started	May 23 04:00:32 PM PDT 24
Finished	May 23 04:40:35 PM PDT 24
Peak memory	602168 kb
Host	smart-b2100140-ab29-4fdf-8c15-c077743e2887
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154 7096707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.1547096707
Directory	/workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1412783538
Short name	T121
Test name
Test status
Simulation time	21989386252 ps
CPU time	2331.44 seconds
Started	May 23 04:00:45 PM PDT 24
Finished	May 23 04:39:39 PM PDT 24
Peak memory	603580 kb
Host	smart-2c777a65-987f-4c1b-9ef1-200501b0eaf2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1412783538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1412783538
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1029987372
Short name	T847
Test name
Test status
Simulation time	9278532500 ps
CPU time	834.14 seconds
Started	May 23 04:00:59 PM PDT 24
Finished	May 23 04:14:55 PM PDT 24
Peak memory	602200 kb
Host	smart-7bd73afb-b189-4228-a896-c0c3705baa44
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029987372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1029987372
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1735355259
Short name	T873
Test name
Test status
Simulation time	3817369204 ps
CPU time	470.17 seconds
Started	May 23 04:02:50 PM PDT 24
Finished	May 23 04:10:41 PM PDT 24
Peak memory	608864 kb
Host	smart-f95712fd-851d-4ebc-a7c4-db37a26e7fc3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1735355259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.1735355259
Directory	/workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4269936033
Short name	T922
Test name
Test status
Simulation time	10096463354 ps
CPU time	1570.53 seconds
Started	May 23 04:00:07 PM PDT 24
Finished	May 23 04:26:20 PM PDT 24
Peak memory	604152 kb
Host	smart-dcbca155-bcab-4334-ada4-4585f73b0eae
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269936033 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4269936033
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.350443515
Short name	T119
Test name
Test status
Simulation time	7209706240 ps
CPU time	484.1 seconds
Started	May 23 04:02:08 PM PDT 24
Finished	May 23 04:10:14 PM PDT 24
Peak memory	602216 kb
Host	smart-01ae0d9c-0153-409c-b6c7-05d44783c612
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350443515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.350443515
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1108190877
Short name	T957
Test name
Test status
Simulation time	6455576277 ps
CPU time	396.9 seconds
Started	May 23 04:00:52 PM PDT 24
Finished	May 23 04:07:31 PM PDT 24
Peak memory	602216 kb
Host	smart-573b6970-886f-4e52-aae8-5d82343c770f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108190877 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.1108190877
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2360120159
Short name	T245
Test name
Test status
Simulation time	25018350252 ps
CPU time	2751.74 seconds
Started	May 23 04:00:10 PM PDT 24
Finished	May 23 04:46:03 PM PDT 24
Peak memory	604176 kb
Host	smart-169a75c1-b8c1-4d3f-bb3d-94aed7748664
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2360120159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2360120159
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.22704047
Short name	T991
Test name
Test status
Simulation time	35705687846 ps
CPU time	3293.78 seconds
Started	May 23 04:00:46 PM PDT 24
Finished	May 23 04:55:41 PM PDT 24
Peak memory	603968 kb
Host	smart-a92d591f-f4e0-4a05-b8b5-c1c291744cb8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22704047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitch _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sle ep_power_glitch_reset.22704047
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3102069481
Short name	T650
Test name
Test status
Simulation time	2848259492 ps
CPU time	310.13 seconds
Started	May 23 03:59:51 PM PDT 24
Finished	May 23 04:05:03 PM PDT 24
Peak memory	601484 kb
Host	smart-c51b45da-efb2-4fa3-9b80-6f5c3940b30c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102069481 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.3102069481
Directory	/workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.848166782
Short name	T1138
Test name
Test status
Simulation time	4182875116 ps
CPU time	560.56 seconds
Started	May 23 03:59:04 PM PDT 24
Finished	May 23 04:08:26 PM PDT 24
Peak memory	609028 kb
Host	smart-1d1d7ee9-0f22-4c8b-8993-fc7fec495393
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=848166782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.848166782
Directory	/workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3103193064
Short name	T153
Test name
Test status
Simulation time	4978239576 ps
CPU time	497.72 seconds
Started	May 23 04:05:28 PM PDT 24
Finished	May 23 04:13:47 PM PDT 24
Peak memory	601592 kb
Host	smart-ea4084a7-1195-4692-ab2f-03d191aeec99
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31031930 64 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3103193064
Directory	/workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2247542509
Short name	T1156
Test name
Test status
Simulation time	5035929864 ps
CPU time	429.18 seconds
Started	May 23 04:04:33 PM PDT 24
Finished	May 23 04:11:44 PM PDT 24
Peak memory	603316 kb
Host	smart-279cc641-1c35-41ca-9312-cf422ff6b618
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2247542509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.2247542509
Directory	/workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.432947535
Short name	T975
Test name
Test status
Simulation time	4995582328 ps
CPU time	316.48 seconds
Started	May 23 04:09:40 PM PDT 24
Finished	May 23 04:14:57 PM PDT 24
Peak memory	602204 kb
Host	smart-9cfc59b0-061f-4de3-a44c-b4dade0e484e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432947535 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.432947535
Directory	/workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3170213992
Short name	T853
Test name
Test status
Simulation time	6528054100 ps
CPU time	1085.58 seconds
Started	May 23 03:59:02 PM PDT 24
Finished	May 23 04:17:09 PM PDT 24
Peak memory	602328 kb
Host	smart-1cfc5efb-0e13-459b-b059-fa787d51897f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170213992 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.3170213992
Directory	/workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1996643180
Short name	T366
Test name
Test status
Simulation time	6023261188 ps
CPU time	525.56 seconds
Started	May 23 03:57:55 PM PDT 24
Finished	May 23 04:06:43 PM PDT 24
Peak memory	602180 kb
Host	smart-9730f3f3-441c-43fd-8d73-65317a618166
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996643180 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1996643180
Directory	/workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.4214530463
Short name	T102
Test name
Test status
Simulation time	5031745624 ps
CPU time	529.33 seconds
Started	May 23 04:08:00 PM PDT 24
Finished	May 23 04:16:51 PM PDT 24
Peak memory	602160 kb
Host	smart-9299f050-26b3-4cc2-a03c-9b6f05367543
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214530463 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.4214530463
Directory	/workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2688971316
Short name	T990
Test name
Test status
Simulation time	4970372268 ps
CPU time	626.06 seconds
Started	May 23 03:59:22 PM PDT 24
Finished	May 23 04:09:50 PM PDT 24
Peak memory	602204 kb
Host	smart-38dfc323-ffe0-415d-b057-743975f27a7f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268 8971316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.2688971316
Directory	/workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1073382315
Short name	T289
Test name
Test status
Simulation time	9776848388 ps
CPU time	1803.43 seconds
Started	May 23 04:04:40 PM PDT 24
Finished	May 23 04:34:45 PM PDT 24
Peak memory	603636 kb
Host	smart-439f6b42-5574-4c25-819f-da85480d519c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1073382315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.1073382315
Directory	/workspace/0.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3245217716
Short name	T238
Test name
Test status
Simulation time	5226566200 ps
CPU time	750.58 seconds
Started	May 23 04:00:50 PM PDT 24
Finished	May 23 04:13:25 PM PDT 24
Peak memory	602248 kb
Host	smart-33dca448-3aeb-4556-aa16-8f309ef1d445
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245217716 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.3245217716
Directory	/workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.321640644
Short name	T1187
Test name
Test status
Simulation time	5368317760 ps
CPU time	725.36 seconds
Started	May 23 04:01:05 PM PDT 24
Finished	May 23 04:13:12 PM PDT 24
Peak memory	634560 kb
Host	smart-808009af-081b-41df-9e53-a03ea491ff7c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 321640644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.321640644
Directory	/workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2823067944
Short name	T874
Test name
Test status
Simulation time	2204866160 ps
CPU time	271.92 seconds
Started	May 23 04:07:43 PM PDT 24
Finished	May 23 04:12:16 PM PDT 24
Peak memory	601452 kb
Host	smart-8791507e-ba65-4e53-b1cf-4930d5e2b55a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823067944 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.2823067944
Directory	/workspace/0.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3945633156
Short name	T1167
Test name
Test status
Simulation time	3381288970 ps
CPU time	468.16 seconds
Started	May 23 04:02:35 PM PDT 24
Finished	May 23 04:10:25 PM PDT 24
Peak memory	601512 kb
Host	smart-5470994e-40fa-4d61-aa6b-fe78d50fe4b6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945633156 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.3945633156
Directory	/workspace/0.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2870693297
Short name	T1165
Test name
Test status
Simulation time	2979384530 ps
CPU time	247.67 seconds
Started	May 23 04:00:31 PM PDT 24
Finished	May 23 04:04:39 PM PDT 24
Peak memory	601384 kb
Host	smart-3749823b-04bc-484f-8b3b-f8ba9908d85a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870693297 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.2870693297
Directory	/workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3342796003
Short name	T134
Test name
Test status
Simulation time	2705915312 ps
CPU time	183.71 seconds
Started	May 23 04:05:54 PM PDT 24
Finished	May 23 04:08:59 PM PDT 24
Peak memory	601484 kb
Host	smart-e4a19963-bef8-4f56-a0ad-7ad223c2fe8b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342796003 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3342796003
Directory	/workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2933381791
Short name	T357
Test name
Test status
Simulation time	3092204328 ps
CPU time	229.16 seconds
Started	May 23 04:01:54 PM PDT 24
Finished	May 23 04:05:45 PM PDT 24
Peak memory	634084 kb
Host	smart-7534a43f-8aa6-44c9-ab39-220bf7b2a788
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933381791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.2933381791
Directory	/workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3238810845
Short name	T1058
Test name
Test status
Simulation time	5133096236 ps
CPU time	927.56 seconds
Started	May 23 04:07:18 PM PDT 24
Finished	May 23 04:22:47 PM PDT 24
Peak memory	601772 kb
Host	smart-dabdbee5-901b-44fb-a833-45d7e112038b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3238810845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3238810845
Directory	/workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1605036519
Short name	T876
Test name
Test status
Simulation time	2566981752 ps
CPU time	234.02 seconds
Started	May 23 04:09:42 PM PDT 24
Finished	May 23 04:13:37 PM PDT 24
Peak memory	601656 kb
Host	smart-d5e9ab8a-f81d-4b95-b05d-a40dfa2a49fe
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605036519 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.1605036519
Directory	/workspace/0.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_irq.864801832
Short name	T231
Test name
Test status
Simulation time	2598400512 ps
CPU time	251.95 seconds
Started	May 23 03:58:57 PM PDT 24
Finished	May 23 04:03:11 PM PDT 24
Peak memory	601416 kb
Host	smart-8419e545-4708-49e7-af6f-e0362ce92af7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864801832 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_irq.864801832
Directory	/workspace/0.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2051150899
Short name	T880
Test name
Test status
Simulation time	2215227024 ps
CPU time	216.39 seconds
Started	May 23 04:07:15 PM PDT 24
Finished	May 23 04:10:53 PM PDT 24
Peak memory	601660 kb
Host	smart-79279668-65ea-4304-8958-4054c8e75c4e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051150899 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.2051150899
Directory	/workspace/0.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1507324352
Short name	T164
Test name
Test status
Simulation time	3193859253 ps
CPU time	217.21 seconds
Started	May 23 04:05:43 PM PDT 24
Finished	May 23 04:09:22 PM PDT 24
Peak memory	602316 kb
Host	smart-b9a51c44-1ef4-40fd-a026-c317e046d3bc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507324 352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1507324352
Directory	/workspace/0.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3585629789
Short name	T50
Test name
Test status
Simulation time	3758099864 ps
CPU time	401.74 seconds
Started	May 23 04:00:24 PM PDT 24
Finished	May 23 04:07:08 PM PDT 24
Peak memory	601804 kb
Host	smart-64881a7e-a035-4ada-9059-d5002925686e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585629789 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.3585629789
Directory	/workspace/0.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3883342431
Short name	T191
Test name
Test status
Simulation time	2612411548 ps
CPU time	222.08 seconds
Started	May 23 03:58:36 PM PDT 24
Finished	May 23 04:02:20 PM PDT 24
Peak memory	601860 kb
Host	smart-db85a5dc-db54-4db7-ab34-362148f39a2d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883342431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.3883342431
Directory	/workspace/0.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.335157393
Short name	T1060
Test name
Test status
Simulation time	7932016192 ps
CPU time	1707.26 seconds
Started	May 23 04:00:26 PM PDT 24
Finished	May 23 04:28:55 PM PDT 24
Peak memory	602460 kb
Host	smart-0f86bf26-fcbe-4e03-91c6-775814f6a0ab
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335157393 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.335157393
Directory	/workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1674322464
Short name	T963
Test name
Test status
Simulation time	8649974120 ps
CPU time	796.26 seconds
Started	May 23 04:05:49 PM PDT 24
Finished	May 23 04:19:07 PM PDT 24
Peak memory	603268 kb
Host	smart-6df80a4c-016c-4407-b6cd-a53709771958
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674322464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1674322464
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4199950458
Short name	T1057
Test name
Test status
Simulation time	5939871720 ps
CPU time	819.58 seconds
Started	May 23 04:00:03 PM PDT 24
Finished	May 23 04:13:44 PM PDT 24
Peak memory	602340 kb
Host	smart-99275df1-8476-4e2a-853c-9fe15efcb5dd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199950458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.4199950458
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2293507153
Short name	T10
Test name
Test status
Simulation time	7287343882 ps
CPU time	795.15 seconds
Started	May 23 03:59:00 PM PDT 24
Finished	May 23 04:12:18 PM PDT 24
Peak memory	621076 kb
Host	smart-67aa3752-fb70-4154-87d1-ef24f32ad107
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293507153 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.2293507153
Directory	/workspace/0.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3138601684
Short name	T188
Test name
Test status
Simulation time	4875070000 ps
CPU time	460.07 seconds
Started	May 23 03:57:53 PM PDT 24
Finished	May 23 04:05:35 PM PDT 24
Peak memory	619528 kb
Host	smart-a5d96702-1391-4e03-9ef9-851c0ee905a2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138601684 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3138601684
Directory	/workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2921210009
Short name	T12
Test name
Test status
Simulation time	2711346756 ps
CPU time	287.92 seconds
Started	May 23 03:59:55 PM PDT 24
Finished	May 23 04:04:45 PM PDT 24
Peak memory	601972 kb
Host	smart-2dff6b10-ff2b-4b68-ba8c-2620a3ff14a5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921210009 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2921210009
Directory	/workspace/0.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1655770203
Short name	T133
Test name
Test status
Simulation time	5109756550 ps
CPU time	731.5 seconds
Started	May 23 03:58:39 PM PDT 24
Finished	May 23 04:10:53 PM PDT 24
Peak memory	602336 kb
Host	smart-00a00a47-18ce-4e74-b3f1-40129e230444
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655770203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.1655770203
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1451385645
Short name	T1038
Test name
Test status
Simulation time	4973536416 ps
CPU time	620.72 seconds
Started	May 23 04:05:58 PM PDT 24
Finished	May 23 04:16:21 PM PDT 24
Peak memory	602408 kb
Host	smart-0c25223a-75b0-49a7-8679-5237d78ccbc7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451385645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1451385645
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2470011257
Short name	T264
Test name
Test status
Simulation time	4909579792 ps
CPU time	566.97 seconds
Started	May 23 04:01:13 PM PDT 24
Finished	May 23 04:10:43 PM PDT 24
Peak memory	602424 kb
Host	smart-75ff434e-337f-4953-aaaf-a1aa3fbee650
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470011257 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2470011257
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2740275954
Short name	T971
Test name
Test status
Simulation time	2279936300 ps
CPU time	294.2 seconds
Started	May 23 04:08:44 PM PDT 24
Finished	May 23 04:13:40 PM PDT 24
Peak memory	601488 kb
Host	smart-4168c2b6-e936-4b17-8899-d55d8711067c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740275954 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.2740275954
Directory	/workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.636527198
Short name	T1125
Test name
Test status
Simulation time	4470474703 ps
CPU time	565.36 seconds
Started	May 23 03:59:27 PM PDT 24
Finished	May 23 04:08:55 PM PDT 24
Peak memory	606616 kb
Host	smart-8ba3127a-0c7a-4fdb-a8eb-dadf8e780dcf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636527198 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.636527198
Directory	/workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3095107654
Short name	T364
Test name
Test status
Simulation time	2495523804 ps
CPU time	294.54 seconds
Started	May 23 03:57:35 PM PDT 24
Finished	May 23 04:02:33 PM PDT 24
Peak memory	605996 kb
Host	smart-8b9bb89d-0317-4e79-ba30-510951dee841
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095107654 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.3095107654
Directory	/workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1901724043
Short name	T21
Test name
Test status
Simulation time	20461027802 ps
CPU time	1554.95 seconds
Started	May 23 03:57:49 PM PDT 24
Finished	May 23 04:23:46 PM PDT 24
Peak memory	606888 kb
Host	smart-6c59f15a-d7b3-4fb7-ab84-a748567048ba
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19017240 43 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.1901724043
Directory	/workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.86506141
Short name	T37
Test name
Test status
Simulation time	4209552596 ps
CPU time	356.37 seconds
Started	May 23 03:59:38 PM PDT 24
Finished	May 23 04:05:35 PM PDT 24
Peak memory	602516 kb
Host	smart-2797642c-947e-4e37-866b-38ec5750524a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86506141 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.86506141
Directory	/workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_smoketest.2619287010
Short name	T1006
Test name
Test status
Simulation time	3092207948 ps
CPU time	238.86 seconds
Started	May 23 04:08:07 PM PDT 24
Finished	May 23 04:12:08 PM PDT 24
Peak memory	601796 kb
Host	smart-9271b1a3-3efa-4a64-8394-42ba4ce5ec0d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619287010 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.2619287010
Directory	/workspace/0.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx.1350355871
Short name	T1024
Test name
Test status
Simulation time	4006739500 ps
CPU time	544.47 seconds
Started	May 23 03:59:44 PM PDT 24
Finished	May 23 04:08:51 PM PDT 24
Peak memory	608132 kb
Host	smart-284251f9-dc12-460f-90cf-30babe6a2c39
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350355871 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1350355871
Directory	/workspace/0.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1009643843
Short name	T927
Test name
Test status
Simulation time	4356732458 ps
CPU time	536.67 seconds
Started	May 23 03:58:02 PM PDT 24
Finished	May 23 04:07:02 PM PDT 24
Peak memory	610684 kb
Host	smart-22d781c0-9b30-4b47-bcb9-2e90cf99f3bf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009643843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.1009643843
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3165179927
Short name	T1235
Test name
Test status
Simulation time	4470886428 ps
CPU time	587.98 seconds
Started	May 23 04:00:51 PM PDT 24
Finished	May 23 04:10:42 PM PDT 24
Peak memory	610372 kb
Host	smart-1177a79b-d086-4913-a176-303fa529c49f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165179927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3165179927
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.960038343
Short name	T863
Test name
Test status
Simulation time	3609235020 ps
CPU time	633.08 seconds
Started	May 23 03:59:23 PM PDT 24
Finished	May 23 04:09:59 PM PDT 24
Peak memory	608096 kb
Host	smart-60099375-43fb-4aaf-9b04-59f0634f208e
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960038343 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.960038343
Directory	/workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2368108211
Short name	T961
Test name
Test status
Simulation time	4207605956 ps
CPU time	629.3 seconds
Started	May 23 03:58:38 PM PDT 24
Finished	May 23 04:09:10 PM PDT 24
Peak memory	611084 kb
Host	smart-3d8bb432-2d01-4145-850f-38f60d960db6
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368108211 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2368108211
Directory	/workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.4159822668
Short name	T1086
Test name
Test status
Simulation time	4846380440 ps
CPU time	785.32 seconds
Started	May 23 04:01:40 PM PDT 24
Finished	May 23 04:14:47 PM PDT 24
Peak memory	608184 kb
Host	smart-41252cca-a555-4662-9c19-905ea697dc10
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159822668 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.4159822668
Directory	/workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1184390219
Short name	T1003
Test name
Test status
Simulation time	2545567686 ps
CPU time	268.91 seconds
Started	May 23 04:00:28 PM PDT 24
Finished	May 23 04:04:58 PM PDT 24
Peak memory	601848 kb
Host	smart-2120a2a6-2742-45c9-812c-8f22a5595b28
User	root
Command	/workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184390219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.1184390219
Directory	/workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_dpi.3810629009
Short name	T24
Test name
Test status
Simulation time	11503662904 ps
CPU time	2829.07 seconds
Started	May 23 04:00:45 PM PDT 24
Finished	May 23 04:47:57 PM PDT 24
Peak memory	601956 kb
Host	smart-3c60052d-1bd0-49a2-b968-f39eeaa6daa7
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3810629009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.3810629009
Directory	/workspace/0.chip_sw_usbdev_dpi/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.394897214
Short name	T23
Test name
Test status
Simulation time	31538995680 ps
CPU time	6919.14 seconds
Started	May 23 03:59:46 PM PDT 24
Finished	May 23 05:55:08 PM PDT 24
Peak memory	601968 kb
Host	smart-548423c4-7059-43e3-8d5e-db7d21491b6c
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=394897214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.394897214
Directory	/workspace/0.chip_sw_usbdev_pincfg/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pullup.3396689363
Short name	T101
Test name
Test status
Simulation time	3429160180 ps
CPU time	264.8 seconds
Started	May 23 03:59:07 PM PDT 24
Finished	May 23 04:03:33 PM PDT 24
Peak memory	601520 kb
Host	smart-81bd3a58-3f23-4b80-9fb7-df52935f3006
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396689363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.3396689363
Directory	/workspace/0.chip_sw_usbdev_pullup/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3229492450
Short name	T1232
Test name
Test status
Simulation time	3492761400 ps
CPU time	551.5 seconds
Started	May 23 03:59:07 PM PDT 24
Finished	May 23 04:08:20 PM PDT 24
Peak memory	601544 kb
Host	smart-77bd95a8-1859-4a4c-8d45-729e6d8114b1
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322949245 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.3229492450
Directory	/workspace/0.chip_sw_usbdev_setuprx/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_stream.3298588233
Short name	T1130
Test name
Test status
Simulation time	18713534936 ps
CPU time	5208.26 seconds
Started	May 23 04:00:23 PM PDT 24
Finished	May 23 05:27:14 PM PDT 24
Peak memory	601704 kb
Host	smart-1f008176-668c-4c59-8a16-0791e3e131de
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3298588233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3298588233
Directory	/workspace/0.chip_sw_usbdev_stream/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_vbus.1932576586
Short name	T998
Test name
Test status
Simulation time	2538865834 ps
CPU time	242.18 seconds
Started	May 23 03:58:10 PM PDT 24
Finished	May 23 04:02:14 PM PDT 24
Peak memory	601508 kb
Host	smart-27bfcefc-b44f-47e2-83cb-48a91ac69d9a
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932576586 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1932576586
Directory	/workspace/0.chip_sw_usbdev_vbus/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_dev.2906057211
Short name	T100
Test name
Test status
Simulation time	11628861775 ps
CPU time	1329.91 seconds
Started	May 23 03:59:24 PM PDT 24
Finished	May 23 04:21:36 PM PDT 24
Peak memory	611656 kb
Host	smart-b427a5d9-6a25-47ec-b969-0005cb26ab30
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2906057211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.2906057211
Directory	/workspace/0.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_prod.50512746
Short name	T171
Test name
Test status
Simulation time	9017356378 ps
CPU time	1010.21 seconds
Started	May 23 04:00:59 PM PDT 24
Finished	May 23 04:17:51 PM PDT 24
Peak memory	613120 kb
Host	smart-6378dd54-9e27-4c1c-9c5a-504e39203362
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50512746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.50512746
Directory	/workspace/0.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_rma.123695079
Short name	T1172
Test name
Test status
Simulation time	2897725580 ps
CPU time	156.15 seconds
Started	May 23 04:05:08 PM PDT 24
Finished	May 23 04:07:45 PM PDT 24
Peak memory	611280 kb
Host	smart-cd949b5e-7401-4b4d-bd3d-9c92e61f5936
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123695079 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.123695079
Directory	/workspace/0.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_testunlock0.2043053122
Short name	T68
Test name
Test status
Simulation time	2799639447 ps
CPU time	148.78 seconds
Started	May 23 04:05:33 PM PDT 24
Finished	May 23 04:08:03 PM PDT 24
Peak memory	612116 kb
Host	smart-a8b9fd3a-93bc-48a1-b4a3-83577232ef65
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043053122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.2043053122
Directory	/workspace/0.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_dev.4215090444
Short name	T395
Test name
Test status
Simulation time	14458678222 ps
CPU time	3442.01 seconds
Started	May 23 04:14:05 PM PDT 24
Finished	May 23 05:11:28 PM PDT 24
Peak memory	603356 kb
Host	smart-c75a5f5f-e5fc-4c31-ab75-0ef120ea07ce
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215090444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.4215090444
Directory	/workspace/0.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_prod.2869215727
Short name	T888
Test name
Test status
Simulation time	14072228541 ps
CPU time	3786.23 seconds
Started	May 23 04:07:17 PM PDT 24
Finished	May 23 05:10:25 PM PDT 24
Peak memory	603332 kb
Host	smart-269c1993-bed5-4cfc-bc87-f6e047f550d5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869215727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.2869215727
Directory	/workspace/0.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3713266087
Short name	T1089
Test name
Test status
Simulation time	14500799285 ps
CPU time	3653.79 seconds
Started	May 23 04:07:29 PM PDT 24
Finished	May 23 05:08:24 PM PDT 24
Peak memory	603336 kb
Host	smart-4e93eb0d-a74b-445c-ac3b-848c208f86c2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713266087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.3713266087
Directory	/workspace/0.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_rma.3506904755
Short name	T1113
Test name
Test status
Simulation time	14374836301 ps
CPU time	3690.69 seconds
Started	May 23 04:07:14 PM PDT 24
Finished	May 23 05:08:46 PM PDT 24
Peak memory	602016 kb
Host	smart-629506c6-7d52-4ef0-852e-d206aa310ada
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506904755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.3506904755
Directory	/workspace/0.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1731029407
Short name	T861
Test name
Test status
Simulation time	10880653704 ps
CPU time	3616.25 seconds
Started	May 23 04:06:11 PM PDT 24
Finished	May 23 05:06:29 PM PDT 24
Peak memory	602340 kb
Host	smart-e2e27833-81f0-4000-b862-e0e0aeddeaf2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731029407 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1731029407
Directory	/workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1963728993
Short name	T1001
Test name
Test status
Simulation time	22181938184 ps
CPU time	6136.37 seconds
Started	May 23 04:05:23 PM PDT 24
Finished	May 23 05:47:41 PM PDT 24
Peak memory	602100 kb
Host	smart-177ec639-b2b8-4d28-ab35-18391420833f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1963728993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1963728993
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1211594710
Short name	T353
Test name
Test status
Simulation time	22506512700 ps
CPU time	5799.81 seconds
Started	May 23 04:14:33 PM PDT 24
Finished	May 23 05:51:14 PM PDT 24
Peak memory	602080 kb
Host	smart-ea631164-77e6-4db0-af5b-5f07cb4adb87
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1211594710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1211594710
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4019418929
Short name	T934
Test name
Test status
Simulation time	22377862832 ps
CPU time	5820.73 seconds
Started	May 23 04:05:06 PM PDT 24
Finished	May 23 05:42:08 PM PDT 24
Peak memory	602068 kb
Host	smart-6c1a894a-3a86-4ecd-a0ac-4809905df578
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4019418929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4019418929
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.666991711
Short name	T248
Test name
Test status
Simulation time	17827071400 ps
CPU time	5077.1 seconds
Started	May 23 04:05:14 PM PDT 24
Finished	May 23 05:29:53 PM PDT 24
Peak memory	601904 kb
Host	smart-5e9fe91e-a52c-43b6-bc58-6c6feb14b9fc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666991711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.666991711
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.4239317519
Short name	T1137
Test name
Test status
Simulation time	14606624684 ps
CPU time	3816.73 seconds
Started	May 23 04:05:07 PM PDT 24
Finished	May 23 05:08:46 PM PDT 24
Peak memory	602128 kb
Host	smart-8017f3b6-c0bc-4f23-bb1d-698b94599ba6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4239317519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.4239317519
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1046077642
Short name	T938
Test name
Test status
Simulation time	14522890368 ps
CPU time	3648.29 seconds
Started	May 23 04:04:20 PM PDT 24
Finished	May 23 05:05:09 PM PDT 24
Peak memory	603156 kb
Host	smart-d540e8a0-0300-4d62-b45e-294d8459c0a7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1046077642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1046077642
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2796363078
Short name	T868
Test name
Test status
Simulation time	14152211196 ps
CPU time	3611.57 seconds
Started	May 23 04:12:40 PM PDT 24
Finished	May 23 05:12:53 PM PDT 24
Peak memory	602060 kb
Host	smart-8e79cf70-83d3-48b5-a0dc-eefbbd5cc7de
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2796363078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2796363078
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1957607792
Short name	T1078
Test name
Test status
Simulation time	14460518810 ps
CPU time	4095.05 seconds
Started	May 23 04:06:07 PM PDT 24
Finished	May 23 05:14:24 PM PDT 24
Peak memory	603172 kb
Host	smart-53a92b43-ad6f-4e3a-8d2f-7ff0a16beca2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1957607792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1957607792
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4213235339
Short name	T1094
Test name
Test status
Simulation time	11139813540 ps
CPU time	2717.58 seconds
Started	May 23 04:06:17 PM PDT 24
Finished	May 23 04:51:35 PM PDT 24
Peak memory	601968 kb
Host	smart-4390d042-55c9-43cb-971f-1b1b01c6754f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213235339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4213235339
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3389581158
Short name	T1197
Test name
Test status
Simulation time	14535679722 ps
CPU time	3423.06 seconds
Started	May 23 04:14:01 PM PDT 24
Finished	May 23 05:11:06 PM PDT 24
Peak memory	602108 kb
Host	smart-f7a2c155-6897-4833-accd-af55d8d24f7b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389581158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3389581158
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1994436726
Short name	T858
Test name
Test status
Simulation time	14350004470 ps
CPU time	4073.42 seconds
Started	May 23 04:09:38 PM PDT 24
Finished	May 23 05:17:32 PM PDT 24
Peak memory	602092 kb
Host	smart-6ab46d30-fcdc-47b4-b85e-061700a00cbd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994436726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1994436726
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.472251912
Short name	T960
Test name
Test status
Simulation time	13529077928 ps
CPU time	3633.68 seconds
Started	May 23 04:14:05 PM PDT 24
Finished	May 23 05:14:40 PM PDT 24
Peak memory	602124 kb
Host	smart-3a148b90-c08e-4a01-82c2-82d0f85dcc04
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472251 912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.472251912
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3528231004
Short name	T246
Test name
Test status
Simulation time	14647451294 ps
CPU time	3811.71 seconds
Started	May 23 04:05:27 PM PDT 24
Finished	May 23 05:09:00 PM PDT 24
Peak memory	602148 kb
Host	smart-c30422f1-37b8-4779-a0f6-0598409785b1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528231004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3528231004
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3857755842
Short name	T1213
Test name
Test status
Simulation time	10908572498 ps
CPU time	2767.76 seconds
Started	May 23 04:05:39 PM PDT 24
Finished	May 23 04:51:47 PM PDT 24
Peak memory	602048 kb
Host	smart-846aed88-98fd-4f0f-8f0a-3b365b7e4f2b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3857755842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3857755842
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.4205425917
Short name	T205
Test name
Test status
Simulation time	14254843300 ps
CPU time	3704.17 seconds
Started	May 23 04:06:25 PM PDT 24
Finished	May 23 05:08:11 PM PDT 24
Peak memory	603180 kb
Host	smart-8c394fea-f4b8-4cd7-8f3a-a6003357b0f3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205425917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.4205425917
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2936228153
Short name	T849
Test name
Test status
Simulation time	15770257456 ps
CPU time	4787.34 seconds
Started	May 23 04:08:02 PM PDT 24
Finished	May 23 05:27:51 PM PDT 24
Peak memory	603172 kb
Host	smart-db24de9c-3576-4f9a-b7f0-df3d368aef11
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936228153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2936228153
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2793242109
Short name	T951
Test name
Test status
Simulation time	14374840880 ps
CPU time	4089.46 seconds
Started	May 23 04:06:49 PM PDT 24
Finished	May 23 05:15:00 PM PDT 24
Peak memory	603192 kb
Host	smart-3374fc9a-18e7-4d21-870c-cd92d39e1386
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793242109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.2793242109
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3084364020
Short name	T999
Test name
Test status
Simulation time	14388810071 ps
CPU time	4149.45 seconds
Started	May 23 04:07:24 PM PDT 24
Finished	May 23 05:16:35 PM PDT 24
Peak memory	601936 kb
Host	smart-244044ac-fdc9-444f-9403-6f8de7e2d7ea
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084364020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.3084364020
Directory	/workspace/0.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/0.rom_e2e_shutdown_output.1549411683
Short name	T1141
Test name
Test status
Simulation time	27494897432 ps
CPU time	3264.37 seconds
Started	May 23 04:05:13 PM PDT 24
Finished	May 23 04:59:39 PM PDT 24
Peak memory	603344 kb
Host	smart-3791f20a-223f-44a5-ba2f-05f53221091b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549411683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.1549411683
Directory	/workspace/0.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1400236582
Short name	T1209
Test name
Test status
Simulation time	21473692946 ps
CPU time	5785.12 seconds
Started	May 23 04:05:49 PM PDT 24
Finished	May 23 05:42:16 PM PDT 24
Peak memory	602216 kb
Host	smart-42a65aa8-1f01-4bba-ace1-9c5e21d76d70
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1400236582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.1400236582
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.437605257
Short name	T997
Test name
Test status
Simulation time	21558950440 ps
CPU time	5294.52 seconds
Started	May 23 04:04:50 PM PDT 24
Finished	May 23 05:33:06 PM PDT 24
Peak memory	603580 kb
Host	smart-438d23ea-9377-48fb-a7c0-263bdf127723
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=437605257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_prod.437605257
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3013893779
Short name	T6
Test name
Test status
Simulation time	22137346555 ps
CPU time	5402.29 seconds
Started	May 23 04:12:19 PM PDT 24
Finished	May 23 05:42:23 PM PDT 24
Peak memory	603256 kb
Host	smart-303846a3-e3f6-4d28-979b-88d804958f8c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3013893779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.3013893779
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.632188583
Short name	T1050
Test name
Test status
Simulation time	21708570409 ps
CPU time	5016.21 seconds
Started	May 23 04:05:36 PM PDT 24
Finished	May 23 05:29:13 PM PDT 24
Peak memory	601976 kb
Host	smart-411c0293-d7af-4409-9fbb-ad625ebcfde4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=632188583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_ bad_rma.632188583
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2061120822
Short name	T82
Test name
Test status
Simulation time	17718023160 ps
CPU time	4617.94 seconds
Started	May 23 04:04:54 PM PDT 24
Finished	May 23 05:21:53 PM PDT 24
Peak memory	603600 kb
Host	smart-171d740d-8efc-4d45-a50f-b155f2906b66
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2061120822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.2061120822
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3423429185
Short name	T252
Test name
Test status
Simulation time	13590519778 ps
CPU time	3671.19 seconds
Started	May 23 04:03:38 PM PDT 24
Finished	May 23 05:04:50 PM PDT 24
Peak memory	601948 kb
Host	smart-a41d6b34-e3fd-4fdf-bc93-435320125bac
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423429185 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3423429185
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.624033919
Short name	T250
Test name
Test status
Simulation time	13374601059 ps
CPU time	3580.01 seconds
Started	May 23 04:03:57 PM PDT 24
Finished	May 23 05:03:38 PM PDT 24
Peak memory	603536 kb
Host	smart-74aae31b-fdf3-4c27-a0ae-8175bab56129
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624033919 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.624033919
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.4032379136
Short name	T1166
Test name
Test status
Simulation time	13779113346 ps
CPU time	3906.46 seconds
Started	May 23 04:04:16 PM PDT 24
Finished	May 23 05:09:23 PM PDT 24
Peak memory	603300 kb
Host	smart-fdade343-a956-4e3f-af1d-5dbc1467a2aa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032379136 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.4032379136
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.975050002
Short name	T1007
Test name
Test status
Simulation time	13950948245 ps
CPU time	3531.01 seconds
Started	May 23 04:06:04 PM PDT 24
Finished	May 23 05:04:57 PM PDT 24
Peak memory	601936 kb
Host	smart-f849acd7-0abf-4b4e-bd31-6edb0aef5f8e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975050002 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.975050002
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.636875943
Short name	T989
Test name
Test status
Simulation time	10941363989 ps
CPU time	3027.02 seconds
Started	May 23 04:08:14 PM PDT 24
Finished	May 23 04:58:43 PM PDT 24
Peak memory	603436 kb
Host	smart-c029eeb9-e663-4ce4-954b-3e7eb36cedd5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636875943 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.636875943
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1306630642
Short name	T899
Test name
Test status
Simulation time	13526297621 ps
CPU time	3435.71 seconds
Started	May 23 04:08:05 PM PDT 24
Finished	May 23 05:05:22 PM PDT 24
Peak memory	602236 kb
Host	smart-2ac228cc-a0b4-49a5-b80e-369d525628f6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306630642 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1306630642
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1841969920
Short name	T1104
Test name
Test status
Simulation time	13515962433 ps
CPU time	3884.08 seconds
Started	May 23 04:04:25 PM PDT 24
Finished	May 23 05:09:11 PM PDT 24
Peak memory	601956 kb
Host	smart-593841b7-2827-4de8-86f0-46ffcb0ca0cd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841969920 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1841969920
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.735721278
Short name	T912
Test name
Test status
Simulation time	13743382333 ps
CPU time	3768.33 seconds
Started	May 23 04:06:41 PM PDT 24
Finished	May 23 05:09:30 PM PDT 24
Peak memory	601984 kb
Host	smart-1879ffe5-5e29-4ed7-9483-e4a06e2e1f50
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735721278 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.735721278
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.659430733
Short name	T40
Test name
Test status
Simulation time	11079573578 ps
CPU time	3334.89 seconds
Started	May 23 04:03:58 PM PDT 24
Finished	May 23 04:59:34 PM PDT 24
Peak memory	603556 kb
Host	smart-a60c23de-5ae8-46d2-bf92-93d98c9a4115
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659430733 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.659430733
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_smoke.691611166
Short name	T1188
Test name
Test status
Simulation time	14025785998 ps
CPU time	3312.14 seconds
Started	May 23 04:03:48 PM PDT 24
Finished	May 23 04:59:02 PM PDT 24
Peak memory	603164 kb
Host	smart-db3f1bef-aabd-48d6-93a4-bd6441879a30
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=691611166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.691611166
Directory	/workspace/0.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/0.rom_keymgr_functest.778818179
Short name	T901
Test name
Test status
Simulation time	5499303560 ps
CPU time	622.89 seconds
Started	May 23 04:01:40 PM PDT 24
Finished	May 23 04:12:05 PM PDT 24
Peak memory	602076 kb
Host	smart-852613ba-7625-4ba2-b981-7b49c9e1fa37
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778818179 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.778818179
Directory	/workspace/0.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/1.chip_jtag_csr_rw.2142632257
Short name	T57
Test name
Test status
Simulation time	3549944350 ps
CPU time	235.31 seconds
Started	May 23 03:49:15 PM PDT 24
Finished	May 23 03:53:12 PM PDT 24
Peak memory	596608 kb
Host	smart-aa8913c0-31d6-4d7b-b3bb-b3a547947f12
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142632257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.2142632257
Directory	/workspace/1.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/1.chip_jtag_mem_access.4022486305
Short name	T44
Test name
Test status
Simulation time	13564433064 ps
CPU time	1403.31 seconds
Started	May 23 03:49:15 PM PDT 24
Finished	May 23 04:12:40 PM PDT 24
Peak memory	599600 kb
Host	smart-570552b1-b25c-47da-a023-6f6f36a1a584
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022486305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.4 022486305
Directory	/workspace/1.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1596194717
Short name	T47
Test name
Test status
Simulation time	4956115200 ps
CPU time	476.31 seconds
Started	May 23 04:04:26 PM PDT 24
Finished	May 23 04:12:25 PM PDT 24
Peak memory	611196 kb
Host	smart-74989eca-ac6a-4d3f-9712-5a2f64345953
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 596194717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.1596194717
Directory	/workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/1.chip_sival_flash_info_access.3525012564
Short name	T1190
Test name
Test status
Simulation time	3841134696 ps
CPU time	366.55 seconds
Started	May 23 04:01:12 PM PDT 24
Finished	May 23 04:07:21 PM PDT 24
Peak memory	601676 kb
Host	smart-cd1fadc3-30f0-444f-8002-126bbcd792dd
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3525012564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3525012564
Directory	/workspace/1.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.703383459
Short name	T317
Test name
Test status
Simulation time	18138188760 ps
CPU time	664.31 seconds
Started	May 23 04:02:17 PM PDT 24
Finished	May 23 04:13:23 PM PDT 24
Peak memory	609132 kb
Host	smart-58dfb95d-7a42-415c-b5d9-7aff25678245
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=703383459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.703383459
Directory	/workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc.3291152783
Short name	T1046
Test name
Test status
Simulation time	2771032584 ps
CPU time	240.96 seconds
Started	May 23 04:06:52 PM PDT 24
Finished	May 23 04:10:54 PM PDT 24
Peak memory	601540 kb
Host	smart-103c30e7-8bd9-4798-8147-c9b3c88ac1a9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291152783 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.3291152783
Directory	/workspace/1.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2539269872
Short name	T1170
Test name
Test status
Simulation time	2242044530 ps
CPU time	202 seconds
Started	May 23 04:01:40 PM PDT 24
Finished	May 23 04:05:03 PM PDT 24
Peak memory	601520 kb
Host	smart-10ba4fe3-935a-40ec-9c0b-4f7ee704acfc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539 269872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2539269872
Directory	/workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3906820677
Short name	T658
Test name
Test status
Simulation time	2814610306 ps
CPU time	219.92 seconds
Started	May 23 04:03:09 PM PDT 24
Finished	May 23 04:06:51 PM PDT 24
Peak memory	601496 kb
Host	smart-f4f3cc4f-7119-4176-87c7-fb071eefcbb9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906820677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.3906820677
Directory	/workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_entropy.2071358020
Short name	T891
Test name
Test status
Simulation time	2871344050 ps
CPU time	288.99 seconds
Started	May 23 04:08:03 PM PDT 24
Finished	May 23 04:12:54 PM PDT 24
Peak memory	601508 kb
Host	smart-47445b62-ca49-406b-a0f3-de8c03370246
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071358020 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2071358020
Directory	/workspace/1.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_idle.3588887690
Short name	T867
Test name
Test status
Simulation time	3369515224 ps
CPU time	218.27 seconds
Started	May 23 04:03:42 PM PDT 24
Finished	May 23 04:07:21 PM PDT 24
Peak memory	601592 kb
Host	smart-4f618c37-e772-476b-8645-d8d6d836fefc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588887690 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3588887690
Directory	/workspace/1.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_masking_off.537539427
Short name	T628
Test name
Test status
Simulation time	2637006332 ps
CPU time	286.91 seconds
Started	May 23 04:00:57 PM PDT 24
Finished	May 23 04:05:45 PM PDT 24
Peak memory	601716 kb
Host	smart-5d1935ce-cde5-46db-81ff-a5266bb8855f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537539427 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.537539427
Directory	/workspace/1.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_smoketest.1752964207
Short name	T1151
Test name
Test status
Simulation time	3259172294 ps
CPU time	271.71 seconds
Started	May 23 04:06:47 PM PDT 24
Finished	May 23 04:11:20 PM PDT 24
Peak memory	601488 kb
Host	smart-a7f481c8-cd56-4937-950a-d4524c08a66d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752964207 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.1752964207
Directory	/workspace/1.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3914866454
Short name	T1230
Test name
Test status
Simulation time	3303487442 ps
CPU time	328.03 seconds
Started	May 23 04:03:45 PM PDT 24
Finished	May 23 04:09:14 PM PDT 24
Peak memory	602512 kb
Host	smart-542de7f7-a99f-4058-ae2d-8d2000683067
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3914866454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3914866454
Directory	/workspace/1.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3706821817
Short name	T1206
Test name
Test status
Simulation time	5227090968 ps
CPU time	523.11 seconds
Started	May 23 04:00:22 PM PDT 24
Finished	May 23 04:09:06 PM PDT 24
Peak memory	609048 kb
Host	smart-335d5e64-ecb2-45c9-ad80-c386797e2018
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3706821817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.3706821817
Directory	/workspace/1.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2560130757
Short name	T914
Test name
Test status
Simulation time	5546832364 ps
CPU time	1370.17 seconds
Started	May 23 04:03:56 PM PDT 24
Finished	May 23 04:26:48 PM PDT 24
Peak memory	602944 kb
Host	smart-c40921da-b399-4bbf-83c6-0b3528b107d1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2560130757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.2560130757
Directory	/workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1612773134
Short name	T78
Test name
Test status
Simulation time	7893916096 ps
CPU time	1739.97 seconds
Started	May 23 04:02:11 PM PDT 24
Finished	May 23 04:31:13 PM PDT 24
Peak memory	601916 kb
Host	smart-d6d6d54f-0291-4957-bbc2-f8d04e903c1d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612773134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.1612773134
Directory	/workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.551254269
Short name	T631
Test name
Test status
Simulation time	13075551400 ps
CPU time	1774.49 seconds
Started	May 23 04:00:30 PM PDT 24
Finished	May 23 04:30:05 PM PDT 24
Peak memory	603536 kb
Host	smart-11c84690-b310-4696-8e48-1abd5a6415ec
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551254269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.551254269
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.870191257
Short name	T325
Test name
Test status
Simulation time	4463645586 ps
CPU time	513.99 seconds
Started	May 23 04:01:22 PM PDT 24
Finished	May 23 04:09:59 PM PDT 24
Peak memory	601860 kb
Host	smart-74397449-4431-42cf-a547-7cdbcc7bcf1f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=870191257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.870191257
Directory	/workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3829487294
Short name	T993
Test name
Test status
Simulation time	254995239880 ps
CPU time	12124.7 seconds
Started	May 23 04:02:52 PM PDT 24
Finished	May 23 07:24:59 PM PDT 24
Peak memory	602036 kb
Host	smart-befd8d9b-b645-4f7b-98be-dede84bf4d45
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829487294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3829487294
Directory	/workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_test.3593596188
Short name	T95
Test name
Test status
Simulation time	2930896024 ps
CPU time	310.01 seconds
Started	May 23 04:02:59 PM PDT 24
Finished	May 23 04:08:11 PM PDT 24
Peak memory	601716 kb
Host	smart-146c6b6b-5717-44c2-9c18-db29ab3bbcfe
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593596188 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.3593596188
Directory	/workspace/1.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2804673394
Short name	T904
Test name
Test status
Simulation time	6173847000 ps
CPU time	384.05 seconds
Started	May 23 04:02:52 PM PDT 24
Finished	May 23 04:09:17 PM PDT 24
Peak memory	602124 kb
Host	smart-fc9db0e5-6a52-4e24-a73b-31fb35c16a9a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2804673394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2804673394
Directory	/workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2706758176
Short name	T1182
Test name
Test status
Simulation time	3137759818 ps
CPU time	340.15 seconds
Started	May 23 04:02:07 PM PDT 24
Finished	May 23 04:07:49 PM PDT 24
Peak memory	601468 kb
Host	smart-82171ca4-b5d2-4650-b050-5d6de8460d49
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706758176 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.2706758176
Directory	/workspace/1.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.873841599
Short name	T852
Test name
Test status
Simulation time	8953774074 ps
CPU time	812.67 seconds
Started	May 23 04:08:40 PM PDT 24
Finished	May 23 04:22:14 PM PDT 24
Peak memory	602200 kb
Host	smart-7b4a4f31-a774-4aa4-b335-d1617937cfdc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 873841599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.873841599
Directory	/workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1559051132
Short name	T1011
Test name
Test status
Simulation time	5627686040 ps
CPU time	593.55 seconds
Started	May 23 04:02:28 PM PDT 24
Finished	May 23 04:12:24 PM PDT 24
Peak memory	601992 kb
Host	smart-ba729106-d547-4f5d-83b7-fbdb8dcea983
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1559051132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1559051132
Directory	/workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.1316156363
Short name	T851
Test name
Test status
Simulation time	7246647964 ps
CPU time	1128.03 seconds
Started	May 23 04:01:39 PM PDT 24
Finished	May 23 04:20:29 PM PDT 24
Peak memory	608788 kb
Host	smart-21f25893-0e43-4e62-a863-b5383ac866f1
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316156363 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.1316156363
Directory	/workspace/1.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1698894847
Short name	T1192
Test name
Test status
Simulation time	4019548084 ps
CPU time	613.96 seconds
Started	May 23 04:07:43 PM PDT 24
Finished	May 23 04:17:59 PM PDT 24
Peak memory	604900 kb
Host	smart-1dbdb269-71c5-4481-94c0-fa9e7a4f53dc
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698894847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1698894847
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2290713910
Short name	T1157
Test name
Test status
Simulation time	3769647348 ps
CPU time	626.34 seconds
Started	May 23 04:08:13 PM PDT 24
Finished	May 23 04:18:41 PM PDT 24
Peak memory	604968 kb
Host	smart-a11c88a1-c4ab-4d92-8ce0-5b7f1608a45e
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290713910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2290713910
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3874999162
Short name	T1127
Test name
Test status
Simulation time	3451796406 ps
CPU time	631.85 seconds
Started	May 23 04:03:15 PM PDT 24
Finished	May 23 04:13:48 PM PDT 24
Peak memory	604776 kb
Host	smart-68b8ddc5-5af1-4944-86af-e1093c31b6fa
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874999162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3874999162
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.460015308
Short name	T147
Test name
Test status
Simulation time	4031144176 ps
CPU time	602.9 seconds
Started	May 23 04:01:44 PM PDT 24
Finished	May 23 04:11:48 PM PDT 24
Peak memory	604820 kb
Host	smart-fb1e8e06-52da-4fbc-809c-c00453c2c90f
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460015308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.460015308
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.713952513
Short name	T1028
Test name
Test status
Simulation time	4949233976 ps
CPU time	548.46 seconds
Started	May 23 04:08:20 PM PDT 24
Finished	May 23 04:17:30 PM PDT 24
Peak memory	604996 kb
Host	smart-c09c5b7d-2f67-4984-a68c-d5ae6093e56f
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713952513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.713952513
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3339787515
Short name	T1075
Test name
Test status
Simulation time	4283493932 ps
CPU time	740.54 seconds
Started	May 23 04:06:45 PM PDT 24
Finished	May 23 04:19:08 PM PDT 24
Peak memory	604864 kb
Host	smart-b48d3a5a-22df-403e-b1f3-f8a88fb2ecaa
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339787515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3339787515
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2395661044
Short name	T962
Test name
Test status
Simulation time	2521592151 ps
CPU time	225.22 seconds
Started	May 23 04:08:17 PM PDT 24
Finished	May 23 04:12:03 PM PDT 24
Peak memory	601356 kb
Host	smart-db511b8c-608b-408a-88e0-43733ef807e5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395661044 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.2395661044
Directory	/workspace/1.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3759055618
Short name	T846
Test name
Test status
Simulation time	3665445446 ps
CPU time	441.12 seconds
Started	May 23 04:00:37 PM PDT 24
Finished	May 23 04:08:00 PM PDT 24
Peak memory	601532 kb
Host	smart-ec13028b-5f32-46f7-8af9-bda49129647e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759055618 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.3759055618
Directory	/workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1244400462
Short name	T144
Test name
Test status
Simulation time	2459815652 ps
CPU time	170.24 seconds
Started	May 23 04:03:11 PM PDT 24
Finished	May 23 04:06:02 PM PDT 24
Peak memory	601540 kb
Host	smart-2e5d1dbc-89bb-4a84-8efc-815075e47db1
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244400462 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1244400462
Directory	/workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3949588225
Short name	T174
Test name
Test status
Simulation time	4154034200 ps
CPU time	354.86 seconds
Started	May 23 04:05:23 PM PDT 24
Finished	May 23 04:11:19 PM PDT 24
Peak memory	601896 kb
Host	smart-c45b936e-202f-4c1c-9dec-889187e9fc2e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949588225 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3949588225
Directory	/workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.962633037
Short name	T336
Test name
Test status
Simulation time	5125433352 ps
CPU time	644.93 seconds
Started	May 23 04:07:04 PM PDT 24
Finished	May 23 04:17:51 PM PDT 24
Peak memory	602180 kb
Host	smart-b3613047-c11c-4551-99dd-bf9a8540d73d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962633037 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.962633037
Directory	/workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.576278307
Short name	T394
Test name
Test status
Simulation time	5039699756 ps
CPU time	500.15 seconds
Started	May 23 04:01:51 PM PDT 24
Finished	May 23 04:10:12 PM PDT 24
Peak memory	602156 kb
Host	smart-94833408-6cf6-4784-80aa-281dc900698f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576278307 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.576278307
Directory	/workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3114262951
Short name	T1126
Test name
Test status
Simulation time	4363846856 ps
CPU time	591.83 seconds
Started	May 23 04:03:39 PM PDT 24
Finished	May 23 04:13:32 PM PDT 24
Peak memory	601872 kb
Host	smart-0f70ecab-6eaa-4fae-8746-7a2811a8830b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114262951 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.3114262951
Directory	/workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3475509014
Short name	T988
Test name
Test status
Simulation time	9401608736 ps
CPU time	1401.87 seconds
Started	May 23 04:07:50 PM PDT 24
Finished	May 23 04:31:13 PM PDT 24
Peak memory	603264 kb
Host	smart-ffedd93d-49f9-4b6b-ab1a-fdf0b404c36b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475509014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3475509014
Directory	/workspace/1.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1709152243
Short name	T1059
Test name
Test status
Simulation time	3560483994 ps
CPU time	409.49 seconds
Started	May 23 04:01:39 PM PDT 24
Finished	May 23 04:08:30 PM PDT 24
Peak memory	601540 kb
Host	smart-f96c69f2-4254-40eb-8f97-923acc9dddef
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709152243 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.1709152243
Directory	/workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3298680851
Short name	T1045
Test name
Test status
Simulation time	4586609908 ps
CPU time	664.7 seconds
Started	May 23 04:01:48 PM PDT 24
Finished	May 23 04:12:54 PM PDT 24
Peak memory	602032 kb
Host	smart-b38bd928-578b-4b38-b01d-0ceb19a187eb
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298680851 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.3298680851
Directory	/workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4284041131
Short name	T1153
Test name
Test status
Simulation time	3224201600 ps
CPU time	209.24 seconds
Started	May 23 04:07:05 PM PDT 24
Finished	May 23 04:10:36 PM PDT 24
Peak memory	601320 kb
Host	smart-5b39956a-1570-4b2d-8e5a-cb52b1fb1ef2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284041131 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.4284041131
Directory	/workspace/1.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4223056990
Short name	T992
Test name
Test status
Simulation time	19651243520 ps
CPU time	4823.44 seconds
Started	May 23 04:01:02 PM PDT 24
Finished	May 23 05:21:27 PM PDT 24
Peak memory	601928 kb
Host	smart-9cb9382a-53d9-41bb-9dce-c755b9dc5122
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223056990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.4223056990
Directory	/workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3129784484
Short name	T140
Test name
Test status
Simulation time	14070846269 ps
CPU time	2541.48 seconds
Started	May 23 04:03:31 PM PDT 24
Finished	May 23 04:45:54 PM PDT 24
Peak memory	601984 kb
Host	smart-36411a05-5167-4627-894d-1207c9b561ac
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129784484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _csrng_edn_concurrency_reduced_freq.3129784484
Directory	/workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1368227618
Short name	T944
Test name
Test status
Simulation time	3343125316 ps
CPU time	363.1 seconds
Started	May 23 04:00:22 PM PDT 24
Finished	May 23 04:06:27 PM PDT 24
Peak memory	602252 kb
Host	smart-f75271eb-e6c8-4ca4-b540-495310bc4c24
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13682 27618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1368227618
Directory	/workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_kat_test.278608294
Short name	T928
Test name
Test status
Simulation time	2728690832 ps
CPU time	203.23 seconds
Started	May 23 04:08:01 PM PDT 24
Finished	May 23 04:11:26 PM PDT 24
Peak memory	601368 kb
Host	smart-5a313885-14f3-4a66-84a9-0cd3da9fbf7d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278608294 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.278608294
Directory	/workspace/1.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_smoketest.3093014153
Short name	T1000
Test name
Test status
Simulation time	2728987290 ps
CPU time	168.98 seconds
Started	May 23 04:05:29 PM PDT 24
Finished	May 23 04:08:19 PM PDT 24
Peak memory	601324 kb
Host	smart-3de49beb-8bbb-46e9-9354-bd02d95d4549
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093014153 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.3093014153
Directory	/workspace/1.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1320642423
Short name	T115
Test name
Test status
Simulation time	5901807242 ps
CPU time	597.31 seconds
Started	May 23 04:02:58 PM PDT 24
Finished	May 23 04:12:57 PM PDT 24
Peak memory	603748 kb
Host	smart-be5373c8-0293-4862-bbe8-80a5f5ca26e9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1320642423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.1320642423
Directory	/workspace/1.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2959386975
Short name	T236
Test name
Test status
Simulation time	4744210044 ps
CPU time	1281.74 seconds
Started	May 23 04:03:30 PM PDT 24
Finished	May 23 04:24:53 PM PDT 24
Peak memory	602080 kb
Host	smart-723449d2-bd00-4308-8286-1b8d35776ad4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959386975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.2959386975
Directory	/workspace/1.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_boot_mode.471732212
Short name	T630
Test name
Test status
Simulation time	2696937320 ps
CPU time	453.19 seconds
Started	May 23 04:03:26 PM PDT 24
Finished	May 23 04:11:01 PM PDT 24
Peak memory	601560 kb
Host	smart-da5de533-6b23-4161-8cd4-2d074e75e42e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471732212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b oot_mode.471732212
Directory	/workspace/1.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3656740600
Short name	T181
Test name
Test status
Simulation time	7570383208 ps
CPU time	1306.01 seconds
Started	May 23 04:05:19 PM PDT 24
Finished	May 23 04:27:07 PM PDT 24
Peak memory	603728 kb
Host	smart-7d75db6c-00ab-41bc-9c80-4cbf5eb6f6e0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3656740600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.3656740600
Directory	/workspace/1.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3875723962
Short name	T1044
Test name
Test status
Simulation time	6510904167 ps
CPU time	1222.21 seconds
Started	May 23 04:03:34 PM PDT 24
Finished	May 23 04:23:58 PM PDT 24
Peak memory	602636 kb
Host	smart-1bc4a229-61cc-4466-9770-9a39a87ac14c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875723962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3875723962
Directory	/workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_kat.1622211971
Short name	T342
Test name
Test status
Simulation time	3638777624 ps
CPU time	706.52 seconds
Started	May 23 04:03:22 PM PDT 24
Finished	May 23 04:15:10 PM PDT 24
Peak memory	608048 kb
Host	smart-90d10906-5169-4f5a-a7a3-a657755a5205
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622211971 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.1622211971
Directory	/workspace/1.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_sw_mode.2675717274
Short name	T898
Test name
Test status
Simulation time	6828759366 ps
CPU time	1490.2 seconds
Started	May 23 03:59:58 PM PDT 24
Finished	May 23 04:24:49 PM PDT 24
Peak memory	601896 kb
Host	smart-e0abe5a2-806c-4183-9daf-40d42bb7fd7c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675717274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.2675717274
Directory	/workspace/1.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3540248918
Short name	T884
Test name
Test status
Simulation time	2770240280 ps
CPU time	260.1 seconds
Started	May 23 04:02:41 PM PDT 24
Finished	May 23 04:07:02 PM PDT 24
Peak memory	601384 kb
Host	smart-ba137b11-253a-4587-9940-602a56ec7225
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35 40248918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.3540248918
Directory	/workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3743551942
Short name	T302
Test name
Test status
Simulation time	7519744904 ps
CPU time	2273.08 seconds
Started	May 23 04:07:01 PM PDT 24
Finished	May 23 04:44:56 PM PDT 24
Peak memory	602108 kb
Host	smart-e3b2bb1e-5481-4f0c-9afd-13fd78617794
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3743551942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3743551942
Directory	/workspace/1.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2436652404
Short name	T399
Test name
Test status
Simulation time	2814346502 ps
CPU time	230.74 seconds
Started	May 23 04:00:07 PM PDT 24
Finished	May 23 04:03:58 PM PDT 24
Peak memory	601516 kb
Host	smart-45498137-4f42-40d7-883a-7b941ad4e9e6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436652404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2436652404
Directory	/workspace/1.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2824697594
Short name	T1018
Test name
Test status
Simulation time	4114323818 ps
CPU time	570.26 seconds
Started	May 23 04:08:17 PM PDT 24
Finished	May 23 04:17:49 PM PDT 24
Peak memory	601552 kb
Host	smart-e4629f12-c530-47fe-8cf8-508664565db4
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2824697594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2824697594
Directory	/workspace/1.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_example_concurrency.3017836690
Short name	T1074
Test name
Test status
Simulation time	2773744748 ps
CPU time	262.44 seconds
Started	May 23 04:05:34 PM PDT 24
Finished	May 23 04:09:58 PM PDT 24
Peak memory	601396 kb
Host	smart-ca0872b5-11a9-40b4-85a2-365fb832f020
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017836690 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.3017836690
Directory	/workspace/1.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/1.chip_sw_example_flash.3322291310
Short name	T1139
Test name
Test status
Simulation time	2754569792 ps
CPU time	256.4 seconds
Started	May 23 04:08:47 PM PDT 24
Finished	May 23 04:13:04 PM PDT 24
Peak memory	601396 kb
Host	smart-c525d020-f056-4bc5-8b3f-fce92eba9df3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322291310 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.3322291310
Directory	/workspace/1.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/1.chip_sw_example_manufacturer.2582230728
Short name	T843
Test name
Test status
Simulation time	2381699360 ps
CPU time	208.4 seconds
Started	May 23 04:08:46 PM PDT 24
Finished	May 23 04:12:16 PM PDT 24
Peak memory	601460 kb
Host	smart-bdd6dcff-502c-43bd-b7ec-432a153de2b9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582230728 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.2582230728
Directory	/workspace/1.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/1.chip_sw_example_rom.141428899
Short name	T1202
Test name
Test status
Simulation time	2223238680 ps
CPU time	108.79 seconds
Started	May 23 04:00:14 PM PDT 24
Finished	May 23 04:02:06 PM PDT 24
Peak memory	602504 kb
Host	smart-06d8d01e-20d4-438c-b43b-56d112bdd5dc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141428899 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_example_rom.141428899
Directory	/workspace/1.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_crash_alert.2402926460
Short name	T1208
Test name
Test status
Simulation time	4578144364 ps
CPU time	463.95 seconds
Started	May 23 04:03:01 PM PDT 24
Finished	May 23 04:10:46 PM PDT 24
Peak memory	603904 kb
Host	smart-a200ee7d-d136-4f1d-a7b2-f449cf0e7dcc
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2402926460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2402926460
Directory	/workspace/1.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.834058922
Short name	T865
Test name
Test status
Simulation time	6035461872 ps
CPU time	1044.2 seconds
Started	May 23 04:03:33 PM PDT 24
Finished	May 23 04:20:59 PM PDT 24
Peak memory	601864 kb
Host	smart-ccb322ae-c3a3-4bdb-b276-afff0eec6bde
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834058922 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_flash_ctrl_access.834058922
Directory	/workspace/1.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.4089844520
Short name	T859
Test name
Test status
Simulation time	5377026247 ps
CPU time	996.79 seconds
Started	May 23 04:01:31 PM PDT 24
Finished	May 23 04:18:10 PM PDT 24
Peak memory	601904 kb
Host	smart-246447ab-f839-445c-bf46-13373cf14e0a
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089844520 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.4089844520
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2353126239
Short name	T694
Test name
Test status
Simulation time	7176193042 ps
CPU time	1169.28 seconds
Started	May 23 04:03:30 PM PDT 24
Finished	May 23 04:23:01 PM PDT 24
Peak memory	601860 kb
Host	smart-eebf0d37-112a-4e08-9bf7-86d8921d0b94
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353126239 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2353126239
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3125179498
Short name	T878
Test name
Test status
Simulation time	4918393397 ps
CPU time	1165.72 seconds
Started	May 23 04:08:16 PM PDT 24
Finished	May 23 04:27:44 PM PDT 24
Peak memory	601792 kb
Host	smart-a2204bb0-4a3a-45d7-9cd2-9a420a9160e8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125179498 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3125179498
Directory	/workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2335657089
Short name	T985
Test name
Test status
Simulation time	3018018968 ps
CPU time	427.33 seconds
Started	May 23 04:03:42 PM PDT 24
Finished	May 23 04:10:50 PM PDT 24
Peak memory	601564 kb
Host	smart-259fbd4c-4489-4d46-99a7-087b1fc1572b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335657089 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.2335657089
Directory	/workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1684345315
Short name	T1054
Test name
Test status
Simulation time	5362328976 ps
CPU time	1104.14 seconds
Started	May 23 04:01:10 PM PDT 24
Finished	May 23 04:19:36 PM PDT 24
Peak memory	601656 kb
Host	smart-82394b29-ff43-4b76-9a13-f75a02d92da0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684345315 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.1684345315
Directory	/workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.722390175
Short name	T318
Test name
Test status
Simulation time	4117173380 ps
CPU time	665.08 seconds
Started	May 23 04:00:26 PM PDT 24
Finished	May 23 04:11:33 PM PDT 24
Peak memory	601388 kb
Host	smart-025e2824-b988-4c69-9df3-192046b2a115
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722390175 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.722390175
Directory	/workspace/1.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.279540216
Short name	T298
Test name
Test status
Simulation time	4821894250 ps
CPU time	755.5 seconds
Started	May 23 04:04:09 PM PDT 24
Finished	May 23 04:16:46 PM PDT 24
Peak memory	601728 kb
Host	smart-86e0c503-4b75-47ec-af97-209fcaf12cb7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=279540216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.279540216
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4105749299
Short name	T931
Test name
Test status
Simulation time	3222169000 ps
CPU time	258.73 seconds
Started	May 23 04:02:51 PM PDT 24
Finished	May 23 04:07:12 PM PDT 24
Peak memory	601408 kb
Host	smart-852459a9-c05a-4959-a54a-611797294a43
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105749 299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.4105749299
Directory	/workspace/1.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.810819117
Short name	T392
Test name
Test status
Simulation time	2540170328 ps
CPU time	271.57 seconds
Started	May 23 04:05:00 PM PDT 24
Finished	May 23 04:09:34 PM PDT 24
Peak memory	602952 kb
Host	smart-ab3a4e4a-27d5-4a27-9b9f-2703f91a247c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=810819117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.810819117
Directory	/workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_gpio_smoketest.4227399458
Short name	T983
Test name
Test status
Simulation time	2862617732 ps
CPU time	256.48 seconds
Started	May 23 04:05:34 PM PDT 24
Finished	May 23 04:09:51 PM PDT 24
Peak memory	601960 kb
Host	smart-abc75893-1cbd-4b9f-80de-3f1235d8e345
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227399458 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.4227399458
Directory	/workspace/1.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc.3122686403
Short name	T320
Test name
Test status
Simulation time	3399973640 ps
CPU time	321.88 seconds
Started	May 23 04:01:38 PM PDT 24
Finished	May 23 04:07:00 PM PDT 24
Peak memory	601328 kb
Host	smart-0f662f1c-c38b-4bad-b726-ffb4617909e1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122686403 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.3122686403
Directory	/workspace/1.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3006687897
Short name	T1146
Test name
Test status
Simulation time	2486404934 ps
CPU time	181.79 seconds
Started	May 23 04:03:35 PM PDT 24
Finished	May 23 04:06:38 PM PDT 24
Peak memory	601604 kb
Host	smart-a45fb0f6-6237-45ea-8f6e-8ef3469ad87b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006687897 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.3006687897
Directory	/workspace/1.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2211749604
Short name	T285
Test name
Test status
Simulation time	2747403940 ps
CPU time	295.41 seconds
Started	May 23 04:03:43 PM PDT 24
Finished	May 23 04:08:40 PM PDT 24
Peak memory	601360 kb
Host	smart-9cad8d39-53f0-415e-94f9-4187155b11c4
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211749604 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.2211749604
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1086754600
Short name	T321
Test name
Test status
Simulation time	2968966253 ps
CPU time	257.67 seconds
Started	May 23 04:05:10 PM PDT 24
Finished	May 23 04:09:29 PM PDT 24
Peak memory	601532 kb
Host	smart-ac60ccb7-d24c-42e5-8094-df4f050365d8
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086754600 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1086754600
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1965581087
Short name	T375
Test name
Test status
Simulation time	3163277160 ps
CPU time	300.21 seconds
Started	May 23 04:05:28 PM PDT 24
Finished	May 23 04:10:29 PM PDT 24
Peak memory	601496 kb
Host	smart-10bb7f5f-55ff-464a-85d4-1e24311f132e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965581087 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.1965581087
Directory	/workspace/1.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.973541849
Short name	T323
Test name
Test status
Simulation time	3236065256 ps
CPU time	554.33 seconds
Started	May 23 04:04:44 PM PDT 24
Finished	May 23 04:14:00 PM PDT 24
Peak memory	602460 kb
Host	smart-e44d45ae-7089-4218-9c01-233e78c58306
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973541849 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.973541849
Directory	/workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1472795058
Short name	T305
Test name
Test status
Simulation time	5657589296 ps
CPU time	883.65 seconds
Started	May 23 04:01:20 PM PDT 24
Finished	May 23 04:16:06 PM PDT 24
Peak memory	602104 kb
Host	smart-bbf18267-e7d6-484e-a115-a2b3859b316b
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472795058 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.1472795058
Directory	/workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2214449594
Short name	T197
Test name
Test status
Simulation time	5220453998 ps
CPU time	701.68 seconds
Started	May 23 04:03:15 PM PDT 24
Finished	May 23 04:14:59 PM PDT 24
Peak memory	602096 kb
Host	smart-b7c8cbe1-b402-4617-87b6-36ceb8d30cd2
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214449594 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.2214449594
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2761091352
Short name	T361
Test name
Test status
Simulation time	4178919480 ps
CPU time	673.48 seconds
Started	May 23 04:02:52 PM PDT 24
Finished	May 23 04:14:07 PM PDT 24
Peak memory	601884 kb
Host	smart-f5c68670-2d92-45dc-8cf8-4bcc94a27b10
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761091352 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.2761091352
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3631338525
Short name	T165
Test name
Test status
Simulation time	64702209010 ps
CPU time	11235.4 seconds
Started	May 23 04:03:50 PM PDT 24
Finished	May 23 07:11:08 PM PDT 24
Peak memory	619376 kb
Host	smart-798beed5-8c56-41ae-a57d-65def4d16db5
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3631338525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.3631338525
Directory	/workspace/1.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.580953922
Short name	T145
Test name
Test status
Simulation time	8870708885 ps
CPU time	1365.5 seconds
Started	May 23 04:03:11 PM PDT 24
Finished	May 23 04:25:58 PM PDT 24
Peak memory	609124 kb
Host	smart-488a5997-00c5-4d2d-ba1c-4292794931c0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=580953922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.580953922
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3796230114
Short name	T85
Test name
Test status
Simulation time	8491759784 ps
CPU time	1657.1 seconds
Started	May 23 04:02:29 PM PDT 24
Finished	May 23 04:30:08 PM PDT 24
Peak memory	609056 kb
Host	smart-d470897a-a446-4615-9cd1-afd5f8165571
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3796230114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.3796230114
Directory	/workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_app_rom.931563901
Short name	T376
Test name
Test status
Simulation time	2704584628 ps
CPU time	149.92 seconds
Started	May 23 04:03:12 PM PDT 24
Finished	May 23 04:05:43 PM PDT 24
Peak memory	601348 kb
Host	smart-e670a434-ff3e-492f-900b-f6de272bab8d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931563901 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_kmac_app_rom.931563901
Directory	/workspace/1.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_entropy.2302041731
Short name	T180
Test name
Test status
Simulation time	3166657896 ps
CPU time	322.68 seconds
Started	May 23 04:00:27 PM PDT 24
Finished	May 23 04:05:51 PM PDT 24
Peak memory	601596 kb
Host	smart-64954b04-1b40-414a-a8d6-4d1a6e39d966
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302041731 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2302041731
Directory	/workspace/1.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_idle.1770312822
Short name	T1090
Test name
Test status
Simulation time	3362708816 ps
CPU time	282.79 seconds
Started	May 23 04:02:53 PM PDT 24
Finished	May 23 04:07:37 PM PDT 24
Peak memory	601456 kb
Host	smart-1761f911-32cb-429d-885b-6ca47211a008
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770312822 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1770312822
Directory	/workspace/1.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3574992411
Short name	T1238
Test name
Test status
Simulation time	2398922030 ps
CPU time	180.75 seconds
Started	May 23 04:04:06 PM PDT 24
Finished	May 23 04:07:08 PM PDT 24
Peak memory	601624 kb
Host	smart-86587642-f792-4ed2-8606-3dec8135204d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574992411 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3574992411
Directory	/workspace/1.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1542703739
Short name	T882
Test name
Test status
Simulation time	3152521614 ps
CPU time	436 seconds
Started	May 23 04:02:01 PM PDT 24
Finished	May 23 04:09:19 PM PDT 24
Peak memory	601328 kb
Host	smart-377a7509-6a7a-4197-a334-940d809d2700
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542703739 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1542703739
Directory	/workspace/1.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4263312463
Short name	T903
Test name
Test status
Simulation time	2750836271 ps
CPU time	250.8 seconds
Started	May 23 04:02:55 PM PDT 24
Finished	May 23 04:07:06 PM PDT 24
Peak memory	601356 kb
Host	smart-c6d791ba-b4cd-4aae-a156-1d85bcc358de
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263312463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.4263312463
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2429655937
Short name	T175
Test name
Test status
Simulation time	3279460362 ps
CPU time	327.18 seconds
Started	May 23 04:04:38 PM PDT 24
Finished	May 23 04:10:07 PM PDT 24
Peak memory	601528 kb
Host	smart-51e1bb73-4fca-4ab7-b17a-401adad19cce
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24296559 37 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2429655937
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_smoketest.3237453171
Short name	T1101
Test name
Test status
Simulation time	2350453742 ps
CPU time	250.17 seconds
Started	May 23 04:08:20 PM PDT 24
Finished	May 23 04:12:31 PM PDT 24
Peak memory	601520 kb
Host	smart-0f62dfb2-0292-4761-b5f6-7050be262ca0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237453171 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.3237453171
Directory	/workspace/1.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.182506499
Short name	T1030
Test name
Test status
Simulation time	2901813708 ps
CPU time	273.64 seconds
Started	May 23 04:04:17 PM PDT 24
Finished	May 23 04:08:51 PM PDT 24
Peak memory	601580 kb
Host	smart-d732eff5-308a-43c4-a23a-2a3bfef27a0a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182506499 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.182506499
Directory	/workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3257490953
Short name	T1239
Test name
Test status
Simulation time	17563247406 ps
CPU time	3443.9 seconds
Started	May 23 04:02:59 PM PDT 24
Finished	May 23 05:00:24 PM PDT 24
Peak memory	601900 kb
Host	smart-83db878f-466e-482b-9a5a-f977f028f551
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3257490953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.3257490953
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.657144935
Short name	T126
Test name
Test status
Simulation time	19116607360 ps
CPU time	3971.98 seconds
Started	May 23 04:03:15 PM PDT 24
Finished	May 23 05:09:30 PM PDT 24
Peak memory	601960 kb
Host	smart-a5bbbd6c-bb67-4b68-b52b-d68dec1eeb39
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=657144935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.657144935
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3802873863
Short name	T125
Test name
Test status
Simulation time	24952988944 ps
CPU time	3860.58 seconds
Started	May 23 04:03:53 PM PDT 24
Finished	May 23 05:08:16 PM PDT 24
Peak memory	601904 kb
Host	smart-92514a80-5647-4acf-a20a-5b1a857975b7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802873863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3802873863
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.334422084
Short name	T953
Test name
Test status
Simulation time	3042525256 ps
CPU time	580.53 seconds
Started	May 23 04:03:38 PM PDT 24
Finished	May 23 04:13:20 PM PDT 24
Peak memory	601404 kb
Host	smart-39089c00-ccf7-43b5-8eb7-ee561a6b7091
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334422084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.334422084
Directory	/workspace/1.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_randomness.128209050
Short name	T256
Test name
Test status
Simulation time	5735854612 ps
CPU time	943.21 seconds
Started	May 23 04:04:52 PM PDT 24
Finished	May 23 04:20:37 PM PDT 24
Peak memory	601900 kb
Host	smart-f76daaab-11f7-4f11-9707-17c5509c93f1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=128209050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.128209050
Directory	/workspace/1.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_smoketest.2245971209
Short name	T696
Test name
Test status
Simulation time	7561273130 ps
CPU time	1670.38 seconds
Started	May 23 04:07:26 PM PDT 24
Finished	May 23 04:35:18 PM PDT 24
Peak memory	602008 kb
Host	smart-e9012d8c-ba8f-43da-9121-41e208c66243
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245971209 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.2245971209
Directory	/workspace/1.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3518733027
Short name	T946
Test name
Test status
Simulation time	2660247075 ps
CPU time	231.3 seconds
Started	May 23 04:03:55 PM PDT 24
Finished	May 23 04:07:48 PM PDT 24
Peak memory	601536 kb
Host	smart-a8637ead-8e89-424c-a823-ebf1baa48b9c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518733027 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.3518733027
Directory	/workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2267595840
Short name	T208
Test name
Test status
Simulation time	7527987816 ps
CPU time	1466.36 seconds
Started	May 23 04:04:00 PM PDT 24
Finished	May 23 04:28:29 PM PDT 24
Peak memory	602428 kb
Host	smart-12c5a07c-8f98-4205-ae64-631785163668
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2267595840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.2267595840
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3900951031
Short name	T1203
Test name
Test status
Simulation time	6733030040 ps
CPU time	1107.05 seconds
Started	May 23 04:04:30 PM PDT 24
Finished	May 23 04:22:59 PM PDT 24
Peak memory	602060 kb
Host	smart-e5079b9a-faf0-4e71-ad3d-f7ea036b6d9b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3900951031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3900951031
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4043603352
Short name	T930
Test name
Test status
Simulation time	9123415952 ps
CPU time	1199.29 seconds
Started	May 23 04:03:56 PM PDT 24
Finished	May 23 04:23:57 PM PDT 24
Peak memory	602416 kb
Host	smart-49e86616-5451-4d35-8328-2f8d2c053ad6
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4043603352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.4043603352
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3949457056
Short name	T915
Test name
Test status
Simulation time	4050026950 ps
CPU time	563.34 seconds
Started	May 23 04:03:55 PM PDT 24
Finished	May 23 04:13:19 PM PDT 24
Peak memory	601724 kb
Host	smart-c4203bc2-8648-496b-9353-a5f7d69e6a64
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3949457056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3949457056
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1256370717
Short name	T127
Test name
Test status
Simulation time	2390944880 ps
CPU time	234.92 seconds
Started	May 23 04:06:47 PM PDT 24
Finished	May 23 04:10:43 PM PDT 24
Peak memory	601384 kb
Host	smart-7e65b52c-1137-4ef1-ae89-5fef655d7c98
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256370717 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.1256370717
Directory	/workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pattgen_ios.885396064
Short name	T310
Test name
Test status
Simulation time	2883715746 ps
CPU time	257.43 seconds
Started	May 23 04:02:10 PM PDT 24
Finished	May 23 04:06:30 PM PDT 24
Peak memory	601784 kb
Host	smart-ab361fee-98aa-4c2e-8ed1-25f1bbc4dd52
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885396064 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.885396064
Directory	/workspace/1.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/1.chip_sw_plic_sw_irq.3943350627
Short name	T228
Test name
Test status
Simulation time	2436594056 ps
CPU time	350.39 seconds
Started	May 23 04:07:39 PM PDT 24
Finished	May 23 04:13:30 PM PDT 24
Peak memory	601432 kb
Host	smart-cfb50b46-f39e-470a-ac65-83d0af708842
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943350627 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.3943350627
Directory	/workspace/1.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_power_idle_load.3354309583
Short name	T1149
Test name
Test status
Simulation time	4451217038 ps
CPU time	695.89 seconds
Started	May 23 04:00:55 PM PDT 24
Finished	May 23 04:12:33 PM PDT 24
Peak memory	602132 kb
Host	smart-160b7a06-ebcc-4817-9ed4-865cc956a54b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354309583 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3354309583
Directory	/workspace/1.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/1.chip_sw_power_sleep_load.179062278
Short name	T230
Test name
Test status
Simulation time	3765521384 ps
CPU time	376.48 seconds
Started	May 23 04:02:33 PM PDT 24
Finished	May 23 04:08:51 PM PDT 24
Peak memory	601764 kb
Host	smart-09d7b172-c6a4-444a-9a54-1d477e595414
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179062278 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.179062278
Directory	/workspace/1.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3289270876
Short name	T235
Test name
Test status
Simulation time	11802592184 ps
CPU time	1671.28 seconds
Started	May 23 04:00:11 PM PDT 24
Finished	May 23 04:28:03 PM PDT 24
Peak memory	603112 kb
Host	smart-6d91af2e-87bf-4061-952e-6cbf251eed1a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289 270876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3289270876
Directory	/workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4122155600
Short name	T1204
Test name
Test status
Simulation time	23058041368 ps
CPU time	2499.19 seconds
Started	May 23 04:04:15 PM PDT 24
Finished	May 23 04:45:55 PM PDT 24
Peak memory	602160 kb
Host	smart-001dee00-c981-43b8-8146-e21a20f3f9a8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412 2155600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.4122155600
Directory	/workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3231807779
Short name	T1132
Test name
Test status
Simulation time	18182034389 ps
CPU time	1649.73 seconds
Started	May 23 04:01:56 PM PDT 24
Finished	May 23 04:29:26 PM PDT 24
Peak memory	603808 kb
Host	smart-a67a42d3-5cd7-4252-a632-78c5b563ae2a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3231807779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3231807779
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4258920901
Short name	T52
Test name
Test status
Simulation time	22050525368 ps
CPU time	1967.93 seconds
Started	May 23 04:07:42 PM PDT 24
Finished	May 23 04:40:32 PM PDT 24
Peak memory	603640 kb
Host	smart-24a84aa2-80d4-4676-af74-1f1b94fe1a8e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4258920901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4258920901
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2164191951
Short name	T879
Test name
Test status
Simulation time	7515881536 ps
CPU time	520.38 seconds
Started	May 23 04:01:11 PM PDT 24
Finished	May 23 04:09:54 PM PDT 24
Peak memory	602544 kb
Host	smart-619dfdb0-47d5-45dc-8230-64f26268f24f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164191951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.2164191951
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3920815295
Short name	T1013
Test name
Test status
Simulation time	7239817730 ps
CPU time	469.64 seconds
Started	May 23 04:02:00 PM PDT 24
Finished	May 23 04:09:52 PM PDT 24
Peak memory	609084 kb
Host	smart-435d4ab5-ebb0-410c-a3ee-b72b933f3831
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3920815295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3920815295
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1517337575
Short name	T973
Test name
Test status
Simulation time	7089745325 ps
CPU time	556.96 seconds
Started	May 23 04:02:37 PM PDT 24
Finished	May 23 04:11:55 PM PDT 24
Peak memory	602144 kb
Host	smart-739f7d7c-5db0-4aa5-baea-116859b038d0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517337575 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.1517337575
Directory	/workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2812503304
Short name	T917
Test name
Test status
Simulation time	3714912365 ps
CPU time	378.61 seconds
Started	May 23 04:05:04 PM PDT 24
Finished	May 23 04:11:23 PM PDT 24
Peak memory	608776 kb
Host	smart-74546ccf-cec6-435e-8988-6b223cda11e2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2812503304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.2812503304
Directory	/workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.509443396
Short name	T380
Test name
Test status
Simulation time	7580257960 ps
CPU time	388.45 seconds
Started	May 23 04:08:15 PM PDT 24
Finished	May 23 04:14:44 PM PDT 24
Peak memory	602220 kb
Host	smart-bc141aa1-95bf-47f8-bef5-ed0f78d7ffa8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509443396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.509443396
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.776544266
Short name	T920
Test name
Test status
Simulation time	6054823176 ps
CPU time	434.38 seconds
Started	May 23 04:02:56 PM PDT 24
Finished	May 23 04:10:12 PM PDT 24
Peak memory	602212 kb
Host	smart-34334a03-1ce3-47ac-b52b-8d7a8cf69f39
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776544266 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.776544266
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1245668943
Short name	T954
Test name
Test status
Simulation time	18618950594 ps
CPU time	1836.48 seconds
Started	May 23 04:01:31 PM PDT 24
Finished	May 23 04:32:09 PM PDT 24
Peak memory	602872 kb
Host	smart-364bd0ec-4bb2-41f2-b532-8208f72edb61
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1245668943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1245668943
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2180293615
Short name	T18
Test name
Test status
Simulation time	18279350400 ps
CPU time	1424.62 seconds
Started	May 23 04:08:40 PM PDT 24
Finished	May 23 04:32:25 PM PDT 24
Peak memory	603384 kb
Host	smart-2d53e65f-bef9-411a-9e7e-a0292067f75f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2180293615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2180293615
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4106250449
Short name	T326
Test name
Test status
Simulation time	33076982686 ps
CPU time	3034.49 seconds
Started	May 23 04:00:25 PM PDT 24
Finished	May 23 04:51:01 PM PDT 24
Peak memory	605004 kb
Host	smart-348ad923-56d2-4b00-98bf-968b2526cf33
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106250449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.4106250449
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3025979725
Short name	T332
Test name
Test status
Simulation time	5300523000 ps
CPU time	449.01 seconds
Started	May 23 04:04:21 PM PDT 24
Finished	May 23 04:11:51 PM PDT 24
Peak memory	602840 kb
Host	smart-4e5a23f6-c1c6-4d0d-80e0-4fad7a4175b3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3025979725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3025979725
Directory	/workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3219475458
Short name	T649
Test name
Test status
Simulation time	3531277396 ps
CPU time	289.88 seconds
Started	May 23 04:02:39 PM PDT 24
Finished	May 23 04:07:31 PM PDT 24
Peak memory	601540 kb
Host	smart-e7cd74ad-574c-4c8b-bd70-0ab04069b3fa
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219475458 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.3219475458
Directory	/workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2216172604
Short name	T979
Test name
Test status
Simulation time	4233592297 ps
CPU time	459.04 seconds
Started	May 23 04:04:19 PM PDT 24
Finished	May 23 04:11:59 PM PDT 24
Peak memory	608952 kb
Host	smart-c42f8f1c-480b-468d-b715-f49cdeac4290
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2216172604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.2216172604
Directory	/workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3846114897
Short name	T150
Test name
Test status
Simulation time	5376679290 ps
CPU time	453.98 seconds
Started	May 23 04:03:36 PM PDT 24
Finished	May 23 04:11:10 PM PDT 24
Peak memory	601512 kb
Host	smart-ce5b80c3-acb7-4aea-84ef-4f6c46715e0b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38461148 97 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3846114897
Directory	/workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.381957784
Short name	T152
Test name
Test status
Simulation time	5874003264 ps
CPU time	585.02 seconds
Started	May 23 04:04:35 PM PDT 24
Finished	May 23 04:14:21 PM PDT 24
Peak memory	603324 kb
Host	smart-98f0927d-8a26-4856-8fa8-87fcd782b3a8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=381957784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.381957784
Directory	/workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.641992992
Short name	T905
Test name
Test status
Simulation time	4337660460 ps
CPU time	396.55 seconds
Started	May 23 04:01:27 PM PDT 24
Finished	May 23 04:08:06 PM PDT 24
Peak memory	601836 kb
Host	smart-ed3da597-645d-4882-927f-a6fbcaa0a6c2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641992992 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.641992992
Directory	/workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.163213620
Short name	T234
Test name
Test status
Simulation time	8440853580 ps
CPU time	1099.85 seconds
Started	May 23 04:01:38 PM PDT 24
Finished	May 23 04:19:58 PM PDT 24
Peak memory	602344 kb
Host	smart-b832501b-a3f3-4078-8617-5ea3382821b1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163213620 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.163213620
Directory	/workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.27341925
Short name	T1019
Test name
Test status
Simulation time	4618686760 ps
CPU time	398.61 seconds
Started	May 23 04:01:34 PM PDT 24
Finished	May 23 04:08:14 PM PDT 24
Peak memory	602152 kb
Host	smart-2ff818a3-6247-441f-9d99-9fc869be99f4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27341925 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.27341925
Directory	/workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1153883203
Short name	T1218
Test name
Test status
Simulation time	4818069560 ps
CPU time	423.25 seconds
Started	May 23 04:08:45 PM PDT 24
Finished	May 23 04:15:49 PM PDT 24
Peak memory	601844 kb
Host	smart-7a5ef730-19dd-409e-ad45-bc7852733605
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153883203 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.1153883203
Directory	/workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1521191373
Short name	T1067
Test name
Test status
Simulation time	4902018800 ps
CPU time	475.97 seconds
Started	May 23 04:05:52 PM PDT 24
Finished	May 23 04:13:49 PM PDT 24
Peak memory	602188 kb
Host	smart-781fb8de-138e-437e-8086-852ef775796c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152 1191373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1521191373
Directory	/workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1957912068
Short name	T1033
Test name
Test status
Simulation time	9580238861 ps
CPU time	488.62 seconds
Started	May 23 04:04:23 PM PDT 24
Finished	May 23 04:12:33 PM PDT 24
Peak memory	602496 kb
Host	smart-6cb307a2-0c3c-47f3-8b61-9b8531b9a750
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957912068 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1957912068
Directory	/workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2450539284
Short name	T219
Test name
Test status
Simulation time	6453154696 ps
CPU time	945.5 seconds
Started	May 23 04:03:35 PM PDT 24
Finished	May 23 04:19:22 PM PDT 24
Peak memory	601960 kb
Host	smart-4b3d8534-79a9-4d4a-b82a-543f79fe496e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450539284 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.2450539284
Directory	/workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1726861581
Short name	T688
Test name
Test status
Simulation time	4420753736 ps
CPU time	509.05 seconds
Started	May 23 04:02:29 PM PDT 24
Finished	May 23 04:11:00 PM PDT 24
Peak memory	634580 kb
Host	smart-ed02e636-e6f7-4ee6-828f-9d7779e48207
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1726861581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1726861581
Directory	/workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1888297838
Short name	T857
Test name
Test status
Simulation time	2459320492 ps
CPU time	243.56 seconds
Started	May 23 04:06:15 PM PDT 24
Finished	May 23 04:10:20 PM PDT 24
Peak memory	601448 kb
Host	smart-ddd77c44-68f7-4f1d-a1c4-50d17e5599e6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888297838 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.1888297838
Directory	/workspace/1.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2935844965
Short name	T845
Test name
Test status
Simulation time	4881562260 ps
CPU time	510.05 seconds
Started	May 23 03:59:47 PM PDT 24
Finished	May 23 04:08:19 PM PDT 24
Peak memory	602064 kb
Host	smart-e1e24fb4-0531-4e85-a02b-a76632d2b88c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935844965 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.2935844965
Directory	/workspace/1.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2293182314
Short name	T370
Test name
Test status
Simulation time	2659523814 ps
CPU time	230.08 seconds
Started	May 23 04:04:13 PM PDT 24
Finished	May 23 04:08:04 PM PDT 24
Peak memory	601604 kb
Host	smart-0b6e7a81-aab3-4f60-9c74-8e53483b54ea
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293182314 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2293182314
Directory	/workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1681054602
Short name	T136
Test name
Test status
Simulation time	2793046352 ps
CPU time	284.39 seconds
Started	May 23 04:01:55 PM PDT 24
Finished	May 23 04:06:41 PM PDT 24
Peak memory	601692 kb
Host	smart-07acf925-8326-4cc0-94a7-fce48ce822c2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1681054602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1681054602
Directory	/workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.4294658692
Short name	T137
Test name
Test status
Simulation time	2346599494 ps
CPU time	180.57 seconds
Started	May 23 04:02:52 PM PDT 24
Finished	May 23 04:05:53 PM PDT 24
Peak memory	601452 kb
Host	smart-baa048ab-25c8-4dc4-94ee-095140afb5d7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294658692 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.4294658692
Directory	/workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4017010314
Short name	T489
Test name
Test status
Simulation time	4373845518 ps
CPU time	861.32 seconds
Started	May 23 04:02:44 PM PDT 24
Finished	May 23 04:17:07 PM PDT 24
Peak memory	601832 kb
Host	smart-7574102a-e38a-43fe-8fa2-b05321187f52
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40170 10314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.4017010314
Directory	/workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2523990346
Short name	T237
Test name
Test status
Simulation time	5382743144 ps
CPU time	1092.58 seconds
Started	May 23 04:04:05 PM PDT 24
Finished	May 23 04:22:19 PM PDT 24
Peak memory	601692 kb
Host	smart-0c0a4123-6e44-4520-822e-e90e606293f1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2523990346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.2523990346
Directory	/workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1101936988
Short name	T42
Test name
Test status
Simulation time	6018126774 ps
CPU time	657.74 seconds
Started	May 23 04:03:34 PM PDT 24
Finished	May 23 04:14:32 PM PDT 24
Peak memory	610180 kb
Host	smart-b1b4b3b6-be5b-4fa8-bf48-d978eb9b3029
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101936988 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1101936988
Directory	/workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4131810956
Short name	T64
Test name
Test status
Simulation time	4838212568 ps
CPU time	362.91 seconds
Started	May 23 04:04:29 PM PDT 24
Finished	May 23 04:10:33 PM PDT 24
Peak memory	611332 kb
Host	smart-fde47da5-1312-4f13-9a56-cdcb3dd18eb9
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413181 0956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4131810956
Directory	/workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.447863625
Short name	T1128
Test name
Test status
Simulation time	2505850336 ps
CPU time	177.29 seconds
Started	May 23 04:08:09 PM PDT 24
Finished	May 23 04:11:07 PM PDT 24
Peak memory	601596 kb
Host	smart-75cb0754-6110-4df3-a705-e13414216053
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447863625 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rv_plic_smoketest.447863625
Directory	/workspace/1.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_irq.2830634651
Short name	T3
Test name
Test status
Simulation time	3345397316 ps
CPU time	171.61 seconds
Started	May 23 04:00:16 PM PDT 24
Finished	May 23 04:03:09 PM PDT 24
Peak memory	601300 kb
Host	smart-8eb9bf91-8bc1-440d-b843-01ce45304e53
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830634651 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.2830634651
Directory	/workspace/1.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2703969538
Short name	T1176
Test name
Test status
Simulation time	2250638248 ps
CPU time	230.75 seconds
Started	May 23 04:08:10 PM PDT 24
Finished	May 23 04:12:02 PM PDT 24
Peak memory	601684 kb
Host	smart-ecb087ce-c51d-4e52-b7e9-ed976bc99aae
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703969538 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2703969538
Directory	/workspace/1.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3067498142
Short name	T159
Test name
Test status
Simulation time	5031368940 ps
CPU time	562.48 seconds
Started	May 23 04:03:04 PM PDT 24
Finished	May 23 04:12:28 PM PDT 24
Peak memory	602172 kb
Host	smart-2ad10a73-e6b5-4f5d-bed4-962a62eb3657
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30674981 42 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.3067498142
Directory	/workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1351141538
Short name	T1211
Test name
Test status
Simulation time	2898278326 ps
CPU time	255.68 seconds
Started	May 23 04:03:28 PM PDT 24
Finished	May 23 04:07:45 PM PDT 24
Peak memory	602016 kb
Host	smart-69a55172-7137-4a45-9ad4-8591b22d8969
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351141 538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1351141538
Directory	/workspace/1.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2958829653
Short name	T25
Test name
Test status
Simulation time	3341434462 ps
CPU time	351.75 seconds
Started	May 23 04:04:20 PM PDT 24
Finished	May 23 04:10:13 PM PDT 24
Peak memory	601824 kb
Host	smart-73962172-f8ae-4215-a585-45d13f7e98a2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958829653 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.2958829653
Directory	/workspace/1.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4176993772
Short name	T1168
Test name
Test status
Simulation time	8152533032 ps
CPU time	1237.79 seconds
Started	May 23 03:59:30 PM PDT 24
Finished	May 23 04:20:10 PM PDT 24
Peak memory	602412 kb
Host	smart-fde4d920-d722-41c5-a916-52edaf32db25
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176993772 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.4176993772
Directory	/workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3547153594
Short name	T1185
Test name
Test status
Simulation time	6548864296 ps
CPU time	521.76 seconds
Started	May 23 04:04:12 PM PDT 24
Finished	May 23 04:12:55 PM PDT 24
Peak memory	603388 kb
Host	smart-49814a19-bf1d-4bd5-ab4d-8046a8c2e8a5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547153594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.3547153594
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.180701008
Short name	T131
Test name
Test status
Simulation time	6444387112 ps
CPU time	786.2 seconds
Started	May 23 04:03:37 PM PDT 24
Finished	May 23 04:16:44 PM PDT 24
Peak memory	603272 kb
Host	smart-9b18b568-9229-45c5-ac38-65c085b17ca3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180701008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_ sram_ret_contents_scramble.180701008
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1190934379
Short name	T185
Test name
Test status
Simulation time	7452262351 ps
CPU time	974.89 seconds
Started	May 23 04:05:26 PM PDT 24
Finished	May 23 04:21:42 PM PDT 24
Peak memory	620852 kb
Host	smart-42fffd83-97db-432c-bb59-7fe093b1713b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190934379 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1190934379
Directory	/workspace/1.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_tpm.1494630293
Short name	T38
Test name
Test status
Simulation time	3328395864 ps
CPU time	360.99 seconds
Started	May 23 04:01:51 PM PDT 24
Finished	May 23 04:07:54 PM PDT 24
Peak memory	610332 kb
Host	smart-6cfdeaf1-a33a-46b2-99e6-95c9f002715a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494630293 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1494630293
Directory	/workspace/1.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2408003331
Short name	T34
Test name
Test status
Simulation time	2469495744 ps
CPU time	285.63 seconds
Started	May 23 04:07:14 PM PDT 24
Finished	May 23 04:12:01 PM PDT 24
Peak memory	601932 kb
Host	smart-cccc3ccb-a162-4a26-96db-761bce1a9b0e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408003331 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.2408003331
Directory	/workspace/1.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.882578700
Short name	T276
Test name
Test status
Simulation time	8826214146 ps
CPU time	724.34 seconds
Started	May 23 04:04:17 PM PDT 24
Finished	May 23 04:16:23 PM PDT 24
Peak memory	602412 kb
Host	smart-76942d3c-6965-4186-ac8f-217ba183398c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882578700 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.882578700
Directory	/workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2958937086
Short name	T1189
Test name
Test status
Simulation time	3638875270 ps
CPU time	436.08 seconds
Started	May 23 04:01:47 PM PDT 24
Finished	May 23 04:09:05 PM PDT 24
Peak memory	602984 kb
Host	smart-f8319f89-df59-4c5a-b483-b4f1056017d4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958937086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.2958937086
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4109380483
Short name	T1199
Test name
Test status
Simulation time	4027914138 ps
CPU time	429.92 seconds
Started	May 23 04:02:36 PM PDT 24
Finished	May 23 04:09:47 PM PDT 24
Peak memory	603652 kb
Host	smart-3115553f-1707-4f54-b20e-6f5fc19b8726
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109380483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4109380483
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1508878591
Short name	T1087
Test name
Test status
Simulation time	5868940304 ps
CPU time	760.64 seconds
Started	May 23 04:03:05 PM PDT 24
Finished	May 23 04:15:47 PM PDT 24
Peak memory	603016 kb
Host	smart-9cf0a1da-b71f-47f1-afa9-93b0d8e4310c
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508878591 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1508878591
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1920648565
Short name	T1142
Test name
Test status
Simulation time	2762607152 ps
CPU time	155.32 seconds
Started	May 23 03:58:45 PM PDT 24
Finished	May 23 04:01:22 PM PDT 24
Peak memory	600468 kb
Host	smart-025d7bb7-e4d7-43c7-9d5c-9fb87ada8b29
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920648565 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1920648565
Directory	/workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.72671341
Short name	T1031
Test name
Test status
Simulation time	20493976343 ps
CPU time	3232.67 seconds
Started	May 23 04:03:45 PM PDT 24
Finished	May 23 04:57:40 PM PDT 24
Peak memory	602284 kb
Host	smart-ef349937-0435-4e75-9307-c48151e73884
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72671341 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.72671341
Directory	/workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.525160443
Short name	T664
Test name
Test status
Simulation time	4593596500 ps
CPU time	629.31 seconds
Started	May 23 04:03:37 PM PDT 24
Finished	May 23 04:14:09 PM PDT 24
Peak memory	606644 kb
Host	smart-cc5a0618-f7c6-468c-bd19-7bc013bc2e1f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525160443 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.525160443
Directory	/workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.553297671
Short name	T1056
Test name
Test status
Simulation time	3350501345 ps
CPU time	280.68 seconds
Started	May 23 04:06:31 PM PDT 24
Finished	May 23 04:11:13 PM PDT 24
Peak memory	606284 kb
Host	smart-4b70a3ed-a634-4769-a493-cd1bead9dca8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553297671 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.553297671
Directory	/workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.192636031
Short name	T20
Test name
Test status
Simulation time	23184152310 ps
CPU time	1774.97 seconds
Started	May 23 04:03:07 PM PDT 24
Finished	May 23 04:32:43 PM PDT 24
Peak memory	606928 kb
Host	smart-36b1f733-69e9-4f8a-90aa-5010a111a5f9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19263603 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.192636031
Directory	/workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2398642181
Short name	T36
Test name
Test status
Simulation time	5227448716 ps
CPU time	433.85 seconds
Started	May 23 04:06:07 PM PDT 24
Finished	May 23 04:13:22 PM PDT 24
Peak memory	602164 kb
Host	smart-340a73ad-71ad-48c8-aaa8-f81610540875
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398642181 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2398642181
Directory	/workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_smoketest.1018940783
Short name	T383
Test name
Test status
Simulation time	3367315680 ps
CPU time	172.81 seconds
Started	May 23 04:06:50 PM PDT 24
Finished	May 23 04:09:45 PM PDT 24
Peak memory	601724 kb
Host	smart-9c21e96a-e257-4b16-978b-c70a207842dc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018940783 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.1018940783
Directory	/workspace/1.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx.386841428
Short name	T1016
Test name
Test status
Simulation time	4575985140 ps
CPU time	693.29 seconds
Started	May 23 04:00:50 PM PDT 24
Finished	May 23 04:12:27 PM PDT 24
Peak memory	616320 kb
Host	smart-66bb9a90-df64-4ef4-bf24-4cd2a36b6e43
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386841428 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.386841428
Directory	/workspace/1.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.248273070
Short name	T994
Test name
Test status
Simulation time	4154467196 ps
CPU time	634.13 seconds
Started	May 23 03:59:27 PM PDT 24
Finished	May 23 04:10:03 PM PDT 24
Peak memory	610684 kb
Host	smart-240d85ed-2a60-4c81-96c2-8c5e619e4ce5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248273070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq.248273070
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2785079346
Short name	T940
Test name
Test status
Simulation time	4014390387 ps
CPU time	493.83 seconds
Started	May 23 04:04:19 PM PDT 24
Finished	May 23 04:12:35 PM PDT 24
Peak memory	610672 kb
Host	smart-82c82056-ba03-4734-8f53-ca98721b235c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785079346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2785079346
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2197401188
Short name	T275
Test name
Test status
Simulation time	77477546135 ps
CPU time	12381.6 seconds
Started	May 23 04:07:05 PM PDT 24
Finished	May 23 07:33:29 PM PDT 24
Peak memory	632968 kb
Host	smart-36bf297b-a870-40a4-a71d-1bf017ed5218
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2197401188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2197401188
Directory	/workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.680063313
Short name	T196
Test name
Test status
Simulation time	4079263072 ps
CPU time	583.58 seconds
Started	May 23 04:00:39 PM PDT 24
Finished	May 23 04:10:24 PM PDT 24
Peak memory	608124 kb
Host	smart-ce38bf60-0a61-41ce-a463-56dc93894e98
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680063313 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.680063313
Directory	/workspace/1.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.353160134
Short name	T1144
Test name
Test status
Simulation time	4100973624 ps
CPU time	755 seconds
Started	May 23 04:04:25 PM PDT 24
Finished	May 23 04:17:01 PM PDT 24
Peak memory	608132 kb
Host	smart-557c51ca-fd5a-4794-ab61-bd45d981663a
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353160134 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.353160134
Directory	/workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2793084165
Short name	T909
Test name
Test status
Simulation time	3934883012 ps
CPU time	641.06 seconds
Started	May 23 04:03:16 PM PDT 24
Finished	May 23 04:13:59 PM PDT 24
Peak memory	608136 kb
Host	smart-a849b643-801c-42db-9fbd-283ca2c1241b
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793084165 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.2793084165
Directory	/workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_dev.4238497708
Short name	T46
Test name
Test status
Simulation time	2876186089 ps
CPU time	199.33 seconds
Started	May 23 04:03:13 PM PDT 24
Finished	May 23 04:06:33 PM PDT 24
Peak memory	611196 kb
Host	smart-61ad2ead-3532-48b7-9416-d5b29e47dece
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4238497708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.4238497708
Directory	/workspace/1.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_prod.3425358694
Short name	T1143
Test name
Test status
Simulation time	3391555473 ps
CPU time	178.51 seconds
Started	May 23 04:03:33 PM PDT 24
Finished	May 23 04:06:33 PM PDT 24
Peak memory	611196 kb
Host	smart-495f7a6f-6141-4b91-ab4d-4468159bc087
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425358694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.3425358694
Directory	/workspace/1.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_rma.2832778850
Short name	T1160
Test name
Test status
Simulation time	2388604963 ps
CPU time	234.85 seconds
Started	May 23 04:01:59 PM PDT 24
Finished	May 23 04:05:55 PM PDT 24
Peak memory	620764 kb
Host	smart-512b93d0-edea-4fa1-922a-151c00cbb708
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832778850 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.2832778850
Directory	/workspace/1.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_testunlock0.1143702235
Short name	T98
Test name
Test status
Simulation time	4143247722 ps
CPU time	404.46 seconds
Started	May 23 04:01:52 PM PDT 24
Finished	May 23 04:08:37 PM PDT 24
Peak memory	619880 kb
Host	smart-8121ac13-b320-4b73-b5be-36617e650c8f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143702235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.1143702235
Directory	/workspace/1.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_dev.3361158144
Short name	T1216
Test name
Test status
Simulation time	14429201103 ps
CPU time	3483.77 seconds
Started	May 23 04:07:42 PM PDT 24
Finished	May 23 05:05:47 PM PDT 24
Peak memory	603368 kb
Host	smart-e4fa2279-7074-470f-ab4c-306b339cf342
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361158144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.3361158144
Directory	/workspace/1.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_prod.868831819
Short name	T1240
Test name
Test status
Simulation time	14258530514 ps
CPU time	3482.13 seconds
Started	May 23 04:12:18 PM PDT 24
Finished	May 23 05:10:21 PM PDT 24
Peak memory	602100 kb
Host	smart-fcc59c59-ddf6-45ae-b69a-3755e60551a5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868831819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.868831819
Directory	/workspace/1.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3091068832
Short name	T1080
Test name
Test status
Simulation time	14347166288 ps
CPU time	3226.94 seconds
Started	May 23 04:05:00 PM PDT 24
Finished	May 23 04:58:49 PM PDT 24
Peak memory	602076 kb
Host	smart-9bc80016-2594-4aaf-a0f9-29ab183cc583
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091068832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.3091068832
Directory	/workspace/1.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_rma.247755479
Short name	T987
Test name
Test status
Simulation time	13731040664 ps
CPU time	2951.81 seconds
Started	May 23 04:03:06 PM PDT 24
Finished	May 23 04:52:19 PM PDT 24
Peak memory	603264 kb
Host	smart-0008bdbd-7493-4488-b097-ffb824682a80
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247755479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_rma.247755479
Directory	/workspace/1.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2601931513
Short name	T1122
Test name
Test status
Simulation time	10737195512 ps
CPU time	3040.57 seconds
Started	May 23 04:12:06 PM PDT 24
Finished	May 23 05:02:48 PM PDT 24
Peak memory	602212 kb
Host	smart-b56703d6-9d02-4d96-bffd-4b70847cb8cd
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601931513 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.2601931513
Directory	/workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2273141568
Short name	T1194
Test name
Test status
Simulation time	14566830190 ps
CPU time	3361.59 seconds
Started	May 23 04:07:40 PM PDT 24
Finished	May 23 05:03:43 PM PDT 24
Peak memory	601880 kb
Host	smart-f428a1fe-3db8-4e72-9c84-ef31a990d58d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273141568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2273141568
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3567992970
Short name	T1198
Test name
Test status
Simulation time	15758112400 ps
CPU time	4063.28 seconds
Started	May 23 04:07:59 PM PDT 24
Finished	May 23 05:15:44 PM PDT 24
Peak memory	603164 kb
Host	smart-b7e98404-adf6-4e5c-9ae8-4b9e048970d6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567992970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.3567992970
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1471848752
Short name	T995
Test name
Test status
Simulation time	14379601660 ps
CPU time	2880.44 seconds
Started	May 23 04:03:16 PM PDT 24
Finished	May 23 04:51:18 PM PDT 24
Peak memory	601772 kb
Host	smart-40816fad-71a8-441c-b88a-bdc78b6599cf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471848752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.1471848752
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3924242273
Short name	T1105
Test name
Test status
Simulation time	14474487076 ps
CPU time	3736.49 seconds
Started	May 23 04:08:07 PM PDT 24
Finished	May 23 05:10:24 PM PDT 24
Peak memory	603276 kb
Host	smart-92283e58-3cfc-464e-85ff-d3c4022a786e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924242273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.3924242273
Directory	/workspace/1.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/1.rom_e2e_shutdown_output.3827975182
Short name	T1162
Test name
Test status
Simulation time	27489855224 ps
CPU time	3141.48 seconds
Started	May 23 04:11:03 PM PDT 24
Finished	May 23 05:03:27 PM PDT 24
Peak memory	603376 kb
Host	smart-58e5ac72-5c50-4bb6-94b0-c533936beda0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827975182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.3827975182
Directory	/workspace/1.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/1.rom_e2e_smoke.3154086614
Short name	T854
Test name
Test status
Simulation time	14253831204 ps
CPU time	3229.81 seconds
Started	May 23 04:07:49 PM PDT 24
Finished	May 23 05:01:40 PM PDT 24
Peak memory	603160 kb
Host	smart-62df9657-e1f6-4f82-9dd6-29c2e3aac67f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3154086614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.3154086614
Directory	/workspace/1.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/1.rom_keymgr_functest.244367808
Short name	T1047
Test name
Test status
Simulation time	4498811260 ps
CPU time	703.01 seconds
Started	May 23 04:08:19 PM PDT 24
Finished	May 23 04:20:04 PM PDT 24
Peak memory	602120 kb
Host	smart-bcca8ad9-d87c-4329-9adf-c9fc16987bbd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244367808 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.244367808
Directory	/workspace/1.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1467657084
Short name	T692
Test name
Test status
Simulation time	4247532152 ps
CPU time	501.63 seconds
Started	May 23 04:19:01 PM PDT 24
Finished	May 23 04:27:25 PM PDT 24
Peak memory	637620 kb
Host	smart-16ca3c74-bec7-4584-a8e6-4bc818f08915
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467657084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1467657084
Directory	/workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2830908036
Short name	T675
Test name
Test status
Simulation time	5022030040 ps
CPU time	687.2 seconds
Started	May 23 04:19:56 PM PDT 24
Finished	May 23 04:31:25 PM PDT 24
Peak memory	638896 kb
Host	smart-697aae80-7861-4f45-ac35-f017eba5cefd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2830908036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.2830908036
Directory	/workspace/10.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.502815944
Short name	T200
Test name
Test status
Simulation time	7534155056 ps
CPU time	1463.68 seconds
Started	May 23 04:17:32 PM PDT 24
Finished	May 23 04:41:57 PM PDT 24
Peak memory	611412 kb
Host	smart-0c8b0c04-01b1-4067-9bd5-ce70b97ff37c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=502815944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.502815944
Directory	/workspace/10.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.374723407
Short name	T682
Test name
Test status
Simulation time	3739391310 ps
CPU time	420.98 seconds
Started	May 23 04:21:42 PM PDT 24
Finished	May 23 04:28:44 PM PDT 24
Peak memory	609320 kb
Host	smart-f7fd812f-efbc-435a-b7a3-5c75861a1185
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374723407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_s w_alert_handler_lpg_sleep_mode_alerts.374723407
Directory	/workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2009191423
Short name	T1161
Test name
Test status
Simulation time	3264090410 ps
CPU time	488.11 seconds
Started	May 23 04:18:57 PM PDT 24
Finished	May 23 04:27:06 PM PDT 24
Peak memory	611416 kb
Host	smart-3166d8b1-40a7-431b-92e5-544d995c0f95
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2009191423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.2009191423
Directory	/workspace/11.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3860309899
Short name	T170
Test name
Test status
Simulation time	8492267216 ps
CPU time	1581.27 seconds
Started	May 23 04:19:00 PM PDT 24
Finished	May 23 04:45:23 PM PDT 24
Peak memory	610176 kb
Host	smart-b7932a79-d791-40c9-b079-5c5a05454edb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3860309899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3860309899
Directory	/workspace/12.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3090901779
Short name	T201
Test name
Test status
Simulation time	4267784458 ps
CPU time	487.36 seconds
Started	May 23 04:17:27 PM PDT 24
Finished	May 23 04:25:35 PM PDT 24
Peak memory	611400 kb
Host	smart-09b7ec74-dca0-4953-9960-56622800fd08
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3090901779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.3090901779
Directory	/workspace/13.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.337850719
Short name	T711
Test name
Test status
Simulation time	3821423670 ps
CPU time	468.64 seconds
Started	May 23 04:21:33 PM PDT 24
Finished	May 23 04:29:23 PM PDT 24
Peak memory	637828 kb
Host	smart-c5f0fdb0-bf70-4e9b-8985-3aae466fc935
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337850719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_s w_alert_handler_lpg_sleep_mode_alerts.337850719
Directory	/workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2725554934
Short name	T929
Test name
Test status
Simulation time	8371229004 ps
CPU time	2071.31 seconds
Started	May 23 04:18:24 PM PDT 24
Finished	May 23 04:52:56 PM PDT 24
Peak memory	611180 kb
Host	smart-1fb26ac4-3dcb-430c-8da4-19c1179091a0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2725554934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2725554934
Directory	/workspace/14.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1970074542
Short name	T1117
Test name
Test status
Simulation time	3815340388 ps
CPU time	436.17 seconds
Started	May 23 04:20:52 PM PDT 24
Finished	May 23 04:28:09 PM PDT 24
Peak memory	637576 kb
Host	smart-8e1f04e4-4f7b-4862-b436-37afb1fce59b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970074542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1970074542
Directory	/workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2613719566
Short name	T15
Test name
Test status
Simulation time	8751145032 ps
CPU time	1376.57 seconds
Started	May 23 04:18:59 PM PDT 24
Finished	May 23 04:41:56 PM PDT 24
Peak memory	611200 kb
Host	smart-254a33d5-4b4e-434c-b5d4-38fd4528ac18
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2613719566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.2613719566
Directory	/workspace/15.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1306990566
Short name	T911
Test name
Test status
Simulation time	4026716984 ps
CPU time	830.41 seconds
Started	May 23 04:19:23 PM PDT 24
Finished	May 23 04:33:14 PM PDT 24
Peak memory	610160 kb
Host	smart-c1a096f6-e234-4a46-8a38-ab33a1f9ee80
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1306990566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.1306990566
Directory	/workspace/16.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3529694076
Short name	T1025
Test name
Test status
Simulation time	8541318920 ps
CPU time	2236.41 seconds
Started	May 23 04:18:34 PM PDT 24
Finished	May 23 04:55:52 PM PDT 24
Peak memory	611380 kb
Host	smart-c138fb7c-b59c-4072-bac0-52e75a11f0ad
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3529694076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.3529694076
Directory	/workspace/17.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1153954554
Short name	T1212
Test name
Test status
Simulation time	3292258460 ps
CPU time	464.82 seconds
Started	May 23 04:24:48 PM PDT 24
Finished	May 23 04:32:34 PM PDT 24
Peak memory	611164 kb
Host	smart-3d66ac19-a177-45d8-9fae-0384079e71ad
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1153954554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.1153954554
Directory	/workspace/18.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1165459476
Short name	T667
Test name
Test status
Simulation time	3304936806 ps
CPU time	407.93 seconds
Started	May 23 04:19:15 PM PDT 24
Finished	May 23 04:26:04 PM PDT 24
Peak memory	637584 kb
Host	smart-368850d0-2ddf-4fe4-9b3a-5975e5e3234d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165459476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1165459476
Directory	/workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2342803778
Short name	T942
Test name
Test status
Simulation time	3911230440 ps
CPU time	638.33 seconds
Started	May 23 04:18:53 PM PDT 24
Finished	May 23 04:29:33 PM PDT 24
Peak memory	611176 kb
Host	smart-f8a6d53e-e22c-4af1-8a1b-f5b7432c86af
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2342803778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.2342803778
Directory	/workspace/19.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_jtag_mem_access.883882250
Short name	T412
Test name
Test status
Simulation time	13220024712 ps
CPU time	1372.99 seconds
Started	May 23 04:06:10 PM PDT 24
Finished	May 23 04:29:04 PM PDT 24
Peak memory	602608 kb
Host	smart-5c42e071-a1b2-47c0-aba3-699f1ce0a8b4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883882250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.883882250
Directory	/workspace/2.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/2.chip_sival_flash_info_access.4082137725
Short name	T274
Test name
Test status
Simulation time	2473225416 ps
CPU time	275.78 seconds
Started	May 23 04:07:41 PM PDT 24
Finished	May 23 04:12:19 PM PDT 24
Peak memory	601696 kb
Host	smart-48cf2f12-135c-46c5-ba7d-68d3fee48af0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4082137725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.4082137725
Directory	/workspace/2.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3386001870
Short name	T1221
Test name
Test status
Simulation time	18579908026 ps
CPU time	592.57 seconds
Started	May 23 04:07:02 PM PDT 24
Finished	May 23 04:16:56 PM PDT 24
Peak memory	609168 kb
Host	smart-9a71dc2c-7bc3-44c3-9628-5eda2c41423a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3386001870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3386001870
Directory	/workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc.3735257850
Short name	T875
Test name
Test status
Simulation time	2766083338 ps
CPU time	201.95 seconds
Started	May 23 04:05:35 PM PDT 24
Finished	May 23 04:08:58 PM PDT 24
Peak memory	601520 kb
Host	smart-f7267b94-0651-470a-9258-9b6bc0f00e1e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735257850 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.3735257850
Directory	/workspace/2.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3075685601
Short name	T1096
Test name
Test status
Simulation time	2980636090 ps
CPU time	294.53 seconds
Started	May 23 04:05:06 PM PDT 24
Finished	May 23 04:10:01 PM PDT 24
Peak memory	601520 kb
Host	smart-840cd854-2cc8-4e11-bfc0-e5914ce1bf29
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075 685601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.3075685601
Directory	/workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2126622124
Short name	T1026
Test name
Test status
Simulation time	3003749978 ps
CPU time	278.65 seconds
Started	May 23 04:17:04 PM PDT 24
Finished	May 23 04:21:44 PM PDT 24
Peak memory	601528 kb
Host	smart-71145df9-7966-4a7f-8c03-3f88658baffc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126622124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.2126622124
Directory	/workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_entropy.4161136329
Short name	T1073
Test name
Test status
Simulation time	2701301328 ps
CPU time	224.66 seconds
Started	May 23 04:09:08 PM PDT 24
Finished	May 23 04:12:55 PM PDT 24
Peak memory	601488 kb
Host	smart-4142974c-6763-4795-ae89-ff62cf370038
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161136329 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.4161136329
Directory	/workspace/2.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_idle.1683652847
Short name	T657
Test name
Test status
Simulation time	2695288160 ps
CPU time	177.77 seconds
Started	May 23 04:06:00 PM PDT 24
Finished	May 23 04:09:00 PM PDT 24
Peak memory	601560 kb
Host	smart-79c8c64f-a3ee-414d-8e86-dd2200ea2af5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683652847 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1683652847
Directory	/workspace/2.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_masking_off.2107899377
Short name	T338
Test name
Test status
Simulation time	2669878554 ps
CPU time	327.9 seconds
Started	May 23 04:05:59 PM PDT 24
Finished	May 23 04:11:28 PM PDT 24
Peak memory	601696 kb
Host	smart-480c48f6-903a-4099-8fe1-3d49b68c374e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107899377 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2107899377
Directory	/workspace/2.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_smoketest.654424858
Short name	T343
Test name
Test status
Simulation time	3448489712 ps
CPU time	291.97 seconds
Started	May 23 04:18:08 PM PDT 24
Finished	May 23 04:23:01 PM PDT 24
Peak memory	601312 kb
Host	smart-5530f6c7-9040-43e3-9b9c-64b6e89bf0ac
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654424858 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.654424858
Directory	/workspace/2.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1683402502
Short name	T70
Test name
Test status
Simulation time	2723668845 ps
CPU time	263.32 seconds
Started	May 23 04:10:10 PM PDT 24
Finished	May 23 04:14:35 PM PDT 24
Peak memory	602516 kb
Host	smart-a39fcb0c-6796-4915-a075-cdacb2134d3c
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1683402502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1683402502
Directory	/workspace/2.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1994054544
Short name	T1037
Test name
Test status
Simulation time	5320833720 ps
CPU time	429.18 seconds
Started	May 23 04:07:25 PM PDT 24
Finished	May 23 04:14:36 PM PDT 24
Peak memory	609072 kb
Host	smart-892c0020-62b2-4767-a86d-da9047d3584b
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1994054544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1994054544
Directory	/workspace/2.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3113534334
Short name	T1035
Test name
Test status
Simulation time	7102771936 ps
CPU time	1936.93 seconds
Started	May 23 04:08:06 PM PDT 24
Finished	May 23 04:40:24 PM PDT 24
Peak memory	602948 kb
Host	smart-f9e1c151-5ab8-4f57-ae73-796d41c471d3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3113534334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.3113534334
Directory	/workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.476834560
Short name	T1052
Test name
Test status
Simulation time	8503402176 ps
CPU time	1837.72 seconds
Started	May 23 04:09:03 PM PDT 24
Finished	May 23 04:39:42 PM PDT 24
Peak memory	601856 kb
Host	smart-5e821340-df75-4970-847f-f1d2e39e9be1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476834560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.476834560
Directory	/workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.4263209544
Short name	T74
Test name
Test status
Simulation time	11448961678 ps
CPU time	1409.11 seconds
Started	May 23 04:09:30 PM PDT 24
Finished	May 23 04:33:00 PM PDT 24
Peak memory	603256 kb
Host	smart-05ca6893-c666-4919-9bc9-4bcb52b0f8f5
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263209544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.4263209544
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.229576042
Short name	T1066
Test name
Test status
Simulation time	4577871796 ps
CPU time	450.58 seconds
Started	May 23 04:06:51 PM PDT 24
Finished	May 23 04:14:23 PM PDT 24
Peak memory	601892 kb
Host	smart-6f8cc108-3924-48ef-9873-b91990947864
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=229576042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.229576042
Directory	/workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1101437531
Short name	T1027
Test name
Test status
Simulation time	255865978104 ps
CPU time	12572.4 seconds
Started	May 23 04:08:24 PM PDT 24
Finished	May 23 07:37:59 PM PDT 24
Peak memory	602328 kb
Host	smart-5d779964-cc59-42a6-873c-6799c8bc5064
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101437531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1101437531
Directory	/workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_irq.512305448
Short name	T258
Test name
Test status
Simulation time	4105206308 ps
CPU time	390.47 seconds
Started	May 23 04:00:26 PM PDT 24
Finished	May 23 04:06:58 PM PDT 24
Peak memory	601524 kb
Host	smart-76ba1e5e-eb3a-431d-bc90-b7a0b518d702
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512305448 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.512305448
Directory	/workspace/2.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3534992305
Short name	T86
Test name
Test status
Simulation time	7059200840 ps
CPU time	418.42 seconds
Started	May 23 04:04:46 PM PDT 24
Finished	May 23 04:11:45 PM PDT 24
Peak memory	602152 kb
Host	smart-e4fd3d45-cb04-4c7d-acf8-0a0c824f539d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3534992305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3534992305
Directory	/workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1693795441
Short name	T982
Test name
Test status
Simulation time	2804754940 ps
CPU time	341.22 seconds
Started	May 23 04:15:26 PM PDT 24
Finished	May 23 04:21:08 PM PDT 24
Peak memory	601444 kb
Host	smart-8aeb6fb6-0ded-4610-9d90-b5ab036b8593
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693795441 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.1693795441
Directory	/workspace/2.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1146671027
Short name	T1077
Test name
Test status
Simulation time	9082457290 ps
CPU time	700.16 seconds
Started	May 23 04:00:19 PM PDT 24
Finished	May 23 04:12:00 PM PDT 24
Peak memory	602180 kb
Host	smart-d10eb87f-34a5-43d7-b7a0-f5b8b527bbfc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1146671027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.1146671027
Directory	/workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3551288313
Short name	T1116
Test name
Test status
Simulation time	5163646872 ps
CPU time	454.36 seconds
Started	May 23 04:00:51 PM PDT 24
Finished	May 23 04:08:28 PM PDT 24
Peak memory	601952 kb
Host	smart-3d2f4bfa-3f03-4824-9bd4-e2dd8084d7a1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3551288313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3551288313
Directory	/workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.656914041
Short name	T362
Test name
Test status
Simulation time	7110995126 ps
CPU time	840.4 seconds
Started	May 23 04:14:19 PM PDT 24
Finished	May 23 04:28:21 PM PDT 24
Peak memory	609856 kb
Host	smart-05474f73-6810-47fb-9bff-30ada528a822
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656914041 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.656914041
Directory	/workspace/2.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.456784279
Short name	T950
Test name
Test status
Simulation time	3437580360 ps
CPU time	671.52 seconds
Started	May 23 04:12:45 PM PDT 24
Finished	May 23 04:23:57 PM PDT 24
Peak memory	604832 kb
Host	smart-a4484091-fe0e-48a9-ad89-1f045a82004b
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456784279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.456784279
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.906019548
Short name	T936
Test name
Test status
Simulation time	4055067982 ps
CPU time	757 seconds
Started	May 23 04:14:20 PM PDT 24
Finished	May 23 04:26:58 PM PDT 24
Peak memory	604892 kb
Host	smart-cfc5e1c2-3366-42fd-933f-4ee5aab6b0c9
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906019548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.906019548
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.815906072
Short name	T1140
Test name
Test status
Simulation time	4060223230 ps
CPU time	639.95 seconds
Started	May 23 04:14:29 PM PDT 24
Finished	May 23 04:25:11 PM PDT 24
Peak memory	604844 kb
Host	smart-50c616f0-d704-4883-9453-1b84f22ad184
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815906072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.815906072
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2832624389
Short name	T1002
Test name
Test status
Simulation time	3973265644 ps
CPU time	636.04 seconds
Started	May 23 04:12:41 PM PDT 24
Finished	May 23 04:23:18 PM PDT 24
Peak memory	604796 kb
Host	smart-bb33ceec-be10-4cc3-b76c-6c82bc4a32c7
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832624389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2832624389
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1618842141
Short name	T933
Test name
Test status
Simulation time	5253260870 ps
CPU time	612.66 seconds
Started	May 23 04:13:46 PM PDT 24
Finished	May 23 04:24:00 PM PDT 24
Peak memory	605844 kb
Host	smart-49250eca-97d4-4728-95cc-2d73f8d818a2
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618842141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1618842141
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1137125746
Short name	T69
Test name
Test status
Simulation time	4716460898 ps
CPU time	585.34 seconds
Started	May 23 04:13:33 PM PDT 24
Finished	May 23 04:23:19 PM PDT 24
Peak memory	604800 kb
Host	smart-98800113-ebac-415c-a9b0-a3677eaeface
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137125746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1137125746
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.1795599204
Short name	T855
Test name
Test status
Simulation time	2581040240 ps
CPU time	252.16 seconds
Started	May 23 04:14:59 PM PDT 24
Finished	May 23 04:19:12 PM PDT 24
Peak memory	601584 kb
Host	smart-3a15ad39-835b-4024-9b3a-a6314f24f470
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795599204 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.1795599204
Directory	/workspace/2.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2696573516
Short name	T1084
Test name
Test status
Simulation time	3127446112 ps
CPU time	385.53 seconds
Started	May 23 04:12:53 PM PDT 24
Finished	May 23 04:19:20 PM PDT 24
Peak memory	601400 kb
Host	smart-f389376f-229a-40b4-a1ce-e2c4a9513dd7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696573516 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.2696573516
Directory	/workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3712982903
Short name	T1180
Test name
Test status
Simulation time	2698394308 ps
CPU time	210.47 seconds
Started	May 23 04:16:40 PM PDT 24
Finished	May 23 04:20:11 PM PDT 24
Peak memory	601508 kb
Host	smart-a8abbc8b-4bf3-4d96-b020-43ee456afd4b
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712982903 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3712982903
Directory	/workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2878685567
Short name	T935
Test name
Test status
Simulation time	5235477030 ps
CPU time	591.86 seconds
Started	May 23 04:13:54 PM PDT 24
Finished	May 23 04:23:47 PM PDT 24
Peak memory	602152 kb
Host	smart-6285215c-49c6-40e2-a4ab-cfdf4830684e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878685567 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2878685567
Directory	/workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.345151405
Short name	T924
Test name
Test status
Simulation time	4836756108 ps
CPU time	597.6 seconds
Started	May 23 04:12:01 PM PDT 24
Finished	May 23 04:22:01 PM PDT 24
Peak memory	602116 kb
Host	smart-4d2d509b-0187-4731-9bf9-79b365f2b33a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345151405 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.345151405
Directory	/workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1799473288
Short name	T926
Test name
Test status
Simulation time	4341169584 ps
CPU time	433.89 seconds
Started	May 23 04:12:16 PM PDT 24
Finished	May 23 04:19:32 PM PDT 24
Peak memory	602156 kb
Host	smart-d8c24e4d-17d0-4b75-aa37-050876ac4fe9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799473288 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.1799473288
Directory	/workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1590046401
Short name	T986
Test name
Test status
Simulation time	4735380560 ps
CPU time	534.79 seconds
Started	May 23 04:12:47 PM PDT 24
Finished	May 23 04:21:42 PM PDT 24
Peak memory	602188 kb
Host	smart-d54074b8-8155-4253-adfe-a4f5c6b7243d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590046401 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.1590046401
Directory	/workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.940740112
Short name	T371
Test name
Test status
Simulation time	13039256920 ps
CPU time	1108.11 seconds
Started	May 23 04:12:16 PM PDT 24
Finished	May 23 04:30:46 PM PDT 24
Peak memory	603308 kb
Host	smart-a5d53305-2e7a-4766-9d75-f0e40dab8a87
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940740112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.940740112
Directory	/workspace/2.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3909827960
Short name	T249
Test name
Test status
Simulation time	3325811664 ps
CPU time	547.88 seconds
Started	May 23 04:14:44 PM PDT 24
Finished	May 23 04:23:53 PM PDT 24
Peak memory	601556 kb
Host	smart-e4039599-6ae6-458b-b465-2bfa4c8eb157
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909827960 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3909827960
Directory	/workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3962069763
Short name	T972
Test name
Test status
Simulation time	4432277544 ps
CPU time	648.08 seconds
Started	May 23 04:13:38 PM PDT 24
Finished	May 23 04:24:28 PM PDT 24
Peak memory	601900 kb
Host	smart-c41bdc6a-3eb2-4a40-86b5-495a74d66d2d
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962069763 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.3962069763
Directory	/workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2188606845
Short name	T1004
Test name
Test status
Simulation time	3151539880 ps
CPU time	265 seconds
Started	May 23 04:14:42 PM PDT 24
Finished	May 23 04:19:08 PM PDT 24
Peak memory	601452 kb
Host	smart-71fb54c6-30d9-4bc9-a975-eda1379ed6e8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188606845 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.2188606845
Directory	/workspace/2.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.852846586
Short name	T1154
Test name
Test status
Simulation time	18674966096 ps
CPU time	4403.54 seconds
Started	May 23 04:10:03 PM PDT 24
Finished	May 23 05:23:28 PM PDT 24
Peak memory	602068 kb
Host	smart-49fac491-045b-42cb-81e4-b4a9937573f1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852846586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.852846586
Directory	/workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3464640954
Short name	T141
Test name
Test status
Simulation time	27884317460 ps
CPU time	4379.82 seconds
Started	May 23 04:15:05 PM PDT 24
Finished	May 23 05:28:07 PM PDT 24
Peak memory	602164 kb
Host	smart-83f66d83-a7f2-481b-ab59-af56ef34c051
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464640954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _csrng_edn_concurrency_reduced_freq.3464640954
Directory	/workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4201512144
Short name	T883
Test name
Test status
Simulation time	5118304826 ps
CPU time	429.8 seconds
Started	May 23 04:10:01 PM PDT 24
Finished	May 23 04:17:12 PM PDT 24
Peak memory	602180 kb
Host	smart-21bd8c24-1f1f-4418-be60-57c9f3b5b3d4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42015 12144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.4201512144
Directory	/workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_kat_test.4076482032
Short name	T1103
Test name
Test status
Simulation time	2864899140 ps
CPU time	256.38 seconds
Started	May 23 04:10:09 PM PDT 24
Finished	May 23 04:14:27 PM PDT 24
Peak memory	601344 kb
Host	smart-3839aa44-d9c4-47de-9b3e-9fc8c1bbe62d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076482032 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.4076482032
Directory	/workspace/2.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1539352401
Short name	T62
Test name
Test status
Simulation time	7605486177 ps
CPU time	844.85 seconds
Started	May 23 04:10:25 PM PDT 24
Finished	May 23 04:24:31 PM PDT 24
Peak memory	603304 kb
Host	smart-99fc0a31-a5c9-441f-bfd8-3cc5ed3bee7d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539352401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.1539352401
Directory	/workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_smoketest.838189580
Short name	T1164
Test name
Test status
Simulation time	3293725880 ps
CPU time	293.66 seconds
Started	May 23 04:15:32 PM PDT 24
Finished	May 23 04:20:27 PM PDT 24
Peak memory	601516 kb
Host	smart-1fd09079-67f6-41ce-b9e5-b85ae6a7dff3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838189580 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_csrng_smoketest.838189580
Directory	/workspace/2.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2198813421
Short name	T218
Test name
Test status
Simulation time	5489244800 ps
CPU time	647.35 seconds
Started	May 23 04:07:39 PM PDT 24
Finished	May 23 04:18:27 PM PDT 24
Peak memory	602400 kb
Host	smart-726309c7-73e1-45cb-9708-416b11760003
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2198813421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.2198813421
Directory	/workspace/2.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_auto_mode.813542114
Short name	T626
Test name
Test status
Simulation time	6291584160 ps
CPU time	1798.29 seconds
Started	May 23 04:09:10 PM PDT 24
Finished	May 23 04:39:09 PM PDT 24
Peak memory	602072 kb
Host	smart-c99a90cf-6296-4fae-98c2-8301f477f35a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813542114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_a uto_mode.813542114
Directory	/workspace/2.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_boot_mode.2889273998
Short name	T627
Test name
Test status
Simulation time	2971506050 ps
CPU time	582.15 seconds
Started	May 23 04:10:14 PM PDT 24
Finished	May 23 04:19:57 PM PDT 24
Peak memory	601768 kb
Host	smart-5858468e-9b8d-494f-ae5b-bcc79de60d1e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889273998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.2889273998
Directory	/workspace/2.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2169825154
Short name	T1183
Test name
Test status
Simulation time	6068635784 ps
CPU time	962.19 seconds
Started	May 23 04:10:57 PM PDT 24
Finished	May 23 04:27:00 PM PDT 24
Peak memory	602636 kb
Host	smart-e64b6671-358a-4894-8443-97691312536a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2169825154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.2169825154
Directory	/workspace/2.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.375201276
Short name	T183
Test name
Test status
Simulation time	6544395732 ps
CPU time	1371.79 seconds
Started	May 23 04:11:16 PM PDT 24
Finished	May 23 04:34:10 PM PDT 24
Peak memory	602628 kb
Host	smart-ac2b3844-deea-4de7-a1a9-666000b7cda1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375201276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.375201276
Directory	/workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_kat.3093932990
Short name	T629
Test name
Test status
Simulation time	3041321780 ps
CPU time	610.62 seconds
Started	May 23 04:09:41 PM PDT 24
Finished	May 23 04:19:54 PM PDT 24
Peak memory	608024 kb
Host	smart-cb3f6140-7ad6-4a58-aa3f-719d22801a49
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093932990 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.3093932990
Directory	/workspace/2.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_sw_mode.10728355
Short name	T967
Test name
Test status
Simulation time	8384883524 ps
CPU time	1718.47 seconds
Started	May 23 04:09:50 PM PDT 24
Finished	May 23 04:38:30 PM PDT 24
Peak memory	601804 kb
Host	smart-7337e5dd-1882-4f3a-b28d-b4affca9a2f0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10728355 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.10728355
Directory	/workspace/2.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3414358208
Short name	T921
Test name
Test status
Simulation time	2856800168 ps
CPU time	196.8 seconds
Started	May 23 04:10:59 PM PDT 24
Finished	May 23 04:14:16 PM PDT 24
Peak memory	601500 kb
Host	smart-2029b8db-f111-4482-b10e-463265b5cd3e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34 14358208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.3414358208
Directory	/workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.4185133778
Short name	T301
Test name
Test status
Simulation time	5737035356 ps
CPU time	1232.61 seconds
Started	May 23 04:10:44 PM PDT 24
Finished	May 23 04:31:18 PM PDT 24
Peak memory	602116 kb
Host	smart-098306d8-cce0-4b0c-82e9-d5096fcf9e1a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4185133778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.4185133778
Directory	/workspace/2.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3061069867
Short name	T1242
Test name
Test status
Simulation time	2669756948 ps
CPU time	221.68 seconds
Started	May 23 04:09:35 PM PDT 24
Finished	May 23 04:13:18 PM PDT 24
Peak memory	601524 kb
Host	smart-1bda0e81-4739-4ab4-b0fe-f5d67a90f3e4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061069867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.3061069867
Directory	/workspace/2.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.214163811
Short name	T1226
Test name
Test status
Simulation time	3250833510 ps
CPU time	585.53 seconds
Started	May 23 04:17:57 PM PDT 24
Finished	May 23 04:27:43 PM PDT 24
Peak memory	601512 kb
Host	smart-80ba3007-f017-49d6-b622-155012200387
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=214163811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.214163811
Directory	/workspace/2.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_example_concurrency.4284577543
Short name	T893
Test name
Test status
Simulation time	2998591352 ps
CPU time	258.05 seconds
Started	May 23 04:08:09 PM PDT 24
Finished	May 23 04:12:28 PM PDT 24
Peak memory	601264 kb
Host	smart-8716a074-5041-42c2-ab92-00e05c265696
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284577543 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.4284577543
Directory	/workspace/2.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/2.chip_sw_example_flash.661132149
Short name	T869
Test name
Test status
Simulation time	2614694264 ps
CPU time	270.52 seconds
Started	May 23 04:07:14 PM PDT 24
Finished	May 23 04:11:47 PM PDT 24
Peak memory	601604 kb
Host	smart-d507ea1c-0138-4a32-98c5-be65b36a6cf4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661132149 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.661132149
Directory	/workspace/2.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/2.chip_sw_example_manufacturer.3715980800
Short name	T958
Test name
Test status
Simulation time	2683046784 ps
CPU time	248.48 seconds
Started	May 23 04:08:20 PM PDT 24
Finished	May 23 04:12:29 PM PDT 24
Peak memory	601512 kb
Host	smart-c7f18191-f8f5-40d6-b80c-1e0dfddb8ea4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715980800 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.3715980800
Directory	/workspace/2.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/2.chip_sw_example_rom.163083717
Short name	T1085
Test name
Test status
Simulation time	2310920328 ps
CPU time	109.24 seconds
Started	May 23 04:05:29 PM PDT 24
Finished	May 23 04:07:19 PM PDT 24
Peak memory	602520 kb
Host	smart-9f562d5e-2c8e-47b4-9c29-95c96fed5ee7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163083717 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_example_rom.163083717
Directory	/workspace/2.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_crash_alert.585215991
Short name	T1224
Test name
Test status
Simulation time	5255557380 ps
CPU time	622.64 seconds
Started	May 23 04:16:02 PM PDT 24
Finished	May 23 04:26:27 PM PDT 24
Peak memory	603884 kb
Host	smart-77520a54-3a49-440d-b5aa-f1af1c76c401
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=585215991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.585215991
Directory	/workspace/2.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.4147263563
Short name	T267
Test name
Test status
Simulation time	5066051414 ps
CPU time	966.72 seconds
Started	May 23 04:04:05 PM PDT 24
Finished	May 23 04:20:13 PM PDT 24
Peak memory	601828 kb
Host	smart-2a069389-ff80-4b43-bdec-c6baf5fefecd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147263563 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.4147263563
Directory	/workspace/2.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1772466301
Short name	T1021
Test name
Test status
Simulation time	6185187381 ps
CPU time	739.69 seconds
Started	May 23 03:59:38 PM PDT 24
Finished	May 23 04:11:58 PM PDT 24
Peak memory	601244 kb
Host	smart-86e98b97-3adc-4029-887c-467105b186ec
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772466301 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.1772466301
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2155527323
Short name	T848
Test name
Test status
Simulation time	7704951436 ps
CPU time	1118.76 seconds
Started	May 23 04:13:51 PM PDT 24
Finished	May 23 04:32:31 PM PDT 24
Peak memory	601624 kb
Host	smart-a562bbdb-7576-4b98-9e36-6006510bf7d1
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155527323 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2155527323
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.442538002
Short name	T1102
Test name
Test status
Simulation time	5846092565 ps
CPU time	976.95 seconds
Started	May 23 04:02:00 PM PDT 24
Finished	May 23 04:18:19 PM PDT 24
Peak memory	601812 kb
Host	smart-25c60df1-4ab7-4e19-96b9-86b19f831381
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442538002 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.442538002
Directory	/workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3814398836
Short name	T1112
Test name
Test status
Simulation time	3547468512 ps
CPU time	461.17 seconds
Started	May 23 04:02:53 PM PDT 24
Finished	May 23 04:10:35 PM PDT 24
Peak memory	601576 kb
Host	smart-432ee88a-718b-4b1d-ae69-8a1ccd41cbfa
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814398836 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.3814398836
Directory	/workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3015664617
Short name	T1181
Test name
Test status
Simulation time	5076313496 ps
CPU time	1213.44 seconds
Started	May 23 04:18:42 PM PDT 24
Finished	May 23 04:38:56 PM PDT 24
Peak memory	601804 kb
Host	smart-ff9343b1-10a6-4138-b660-eba11b52f67b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015664617 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.3015664617
Directory	/workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1904454247
Short name	T1193
Test name
Test status
Simulation time	3580876080 ps
CPU time	769.3 seconds
Started	May 23 04:02:20 PM PDT 24
Finished	May 23 04:15:11 PM PDT 24
Peak memory	601652 kb
Host	smart-ba7e99c0-8c02-482b-8a34-42695e35d241
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904454247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1904454247
Directory	/workspace/2.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2438451378
Short name	T328
Test name
Test status
Simulation time	4979320325 ps
CPU time	672.43 seconds
Started	May 23 04:01:05 PM PDT 24
Finished	May 23 04:12:19 PM PDT 24
Peak memory	601928 kb
Host	smart-f4640096-14ca-433b-8140-73eb8f84e87f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2438451378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2438451378
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.953605861
Short name	T297
Test name
Test status
Simulation time	4516680271 ps
CPU time	637.19 seconds
Started	May 23 04:15:35 PM PDT 24
Finished	May 23 04:26:13 PM PDT 24
Peak memory	601984 kb
Host	smart-4f13eceb-94b1-440b-976f-f5adac555ae7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=953605861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.953605861
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1593100753
Short name	T895
Test name
Test status
Simulation time	2898377884 ps
CPU time	337.05 seconds
Started	May 23 04:15:30 PM PDT 24
Finished	May 23 04:21:08 PM PDT 24
Peak memory	601656 kb
Host	smart-c534fa83-fcfd-45b2-bc14-8afe68f6c971
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593100 753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1593100753
Directory	/workspace/2.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1876788460
Short name	T122
Test name
Test status
Simulation time	2007626552 ps
CPU time	184.83 seconds
Started	May 23 04:23:07 PM PDT 24
Finished	May 23 04:26:13 PM PDT 24
Peak memory	602892 kb
Host	smart-c02517b0-1265-466e-932c-ee48ca1a6d5d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1876788460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1876788460
Directory	/workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_gpio_smoketest.370304491
Short name	T106
Test name
Test status
Simulation time	2948818178 ps
CPU time	333.56 seconds
Started	May 23 04:15:32 PM PDT 24
Finished	May 23 04:21:06 PM PDT 24
Peak memory	601880 kb
Host	smart-ead31306-b0e5-48a6-919e-c8e92ba15158
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370304491 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_gpio_smoketest.370304491
Directory	/workspace/2.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc.2199620172
Short name	T330
Test name
Test status
Simulation time	2899736348 ps
CPU time	264.18 seconds
Started	May 23 04:11:13 PM PDT 24
Finished	May 23 04:15:38 PM PDT 24
Peak memory	601496 kb
Host	smart-970b5989-0a11-4b46-bebc-8c33da91bdc2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199620172 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.2199620172
Directory	/workspace/2.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.3229144905
Short name	T1118
Test name
Test status
Simulation time	2806681520 ps
CPU time	294.99 seconds
Started	May 23 04:11:18 PM PDT 24
Finished	May 23 04:16:14 PM PDT 24
Peak memory	601576 kb
Host	smart-307d3e6e-ba83-494a-8543-648fb5167d6f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229144905 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.3229144905
Directory	/workspace/2.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1048425846
Short name	T976
Test name
Test status
Simulation time	2959161795 ps
CPU time	313.97 seconds
Started	May 23 04:11:56 PM PDT 24
Finished	May 23 04:17:11 PM PDT 24
Peak memory	601560 kb
Host	smart-18721c3f-5e85-432a-8c16-edf44bdcb12a
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048425846 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1048425846
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1911336421
Short name	T329
Test name
Test status
Simulation time	2581141888 ps
CPU time	297.61 seconds
Started	May 23 04:14:46 PM PDT 24
Finished	May 23 04:19:45 PM PDT 24
Peak memory	601532 kb
Host	smart-cad7badf-a9e2-43a9-9df7-4deea11e5c0a
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911336421 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.1911336421
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_smoketest.3109868886
Short name	T660
Test name
Test status
Simulation time	2899498326 ps
CPU time	334.53 seconds
Started	May 23 04:17:25 PM PDT 24
Finished	May 23 04:23:03 PM PDT 24
Peak memory	601528 kb
Host	smart-4f9bff87-1a8a-40f0-ab17-25d9002c8c21
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109868886 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.3109868886
Directory	/workspace/2.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2819087559
Short name	T192
Test name
Test status
Simulation time	4067636994 ps
CPU time	694.23 seconds
Started	May 23 04:01:57 PM PDT 24
Finished	May 23 04:13:32 PM PDT 24
Peak memory	602744 kb
Host	smart-4c522cad-389e-462f-aa81-14fc834b4eb6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819087559 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2819087559
Directory	/workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1431335984
Short name	T304
Test name
Test status
Simulation time	4836456292 ps
CPU time	683.63 seconds
Started	May 23 04:02:01 PM PDT 24
Finished	May 23 04:13:28 PM PDT 24
Peak memory	602120 kb
Host	smart-0072a551-6da0-4ee8-bd38-5474bcee5074
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431335984 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.1431335984
Directory	/workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2034522568
Short name	T359
Test name
Test status
Simulation time	4984912040 ps
CPU time	1044.17 seconds
Started	May 23 04:01:51 PM PDT 24
Finished	May 23 04:19:17 PM PDT 24
Peak memory	602156 kb
Host	smart-8167fefa-1f74-4def-8d84-f1bd737a9faa
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034522568 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.2034522568
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3376098062
Short name	T199
Test name
Test status
Simulation time	4463427640 ps
CPU time	677.02 seconds
Started	May 23 04:03:15 PM PDT 24
Finished	May 23 04:14:34 PM PDT 24
Peak memory	602136 kb
Host	smart-180ba88f-19aa-4cd1-a8ec-ade6610b8fd1
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376098062 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3376098062
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.4043477811
Short name	T184
Test name
Test status
Simulation time	64276441169 ps
CPU time	11410.2 seconds
Started	May 23 04:07:10 PM PDT 24
Finished	May 23 07:17:22 PM PDT 24
Peak memory	620376 kb
Host	smart-e84c27a3-5ee1-49b4-894d-12cc9fcc4209
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4043477811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.4043477811
Directory	/workspace/2.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.117650918
Short name	T1099
Test name
Test status
Simulation time	8568081713 ps
CPU time	1426.43 seconds
Started	May 23 04:12:12 PM PDT 24
Finished	May 23 04:36:01 PM PDT 24
Peak memory	609396 kb
Host	smart-245b8cc1-eef1-4114-b873-7aeaae45a9f7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=117650918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.117650918
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4249950125
Short name	T980
Test name
Test status
Simulation time	9535433977 ps
CPU time	1457.77 seconds
Started	May 23 04:15:40 PM PDT 24
Finished	May 23 04:40:00 PM PDT 24
Peak memory	610168 kb
Host	smart-a7b7b849-81e4-4a12-8dc7-22cd5f5aefa7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4249950125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.4249950125
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2777500479
Short name	T1100
Test name
Test status
Simulation time	6601025072 ps
CPU time	1033.71 seconds
Started	May 23 04:11:32 PM PDT 24
Finished	May 23 04:28:47 PM PDT 24
Peak memory	609348 kb
Host	smart-71d6b863-7202-489c-bcae-f4cf584287db
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2777500479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.2777500479
Directory	/workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4000801288
Short name	T211
Test name
Test status
Simulation time	6257038800 ps
CPU time	1208.07 seconds
Started	May 23 04:11:38 PM PDT 24
Finished	May 23 04:31:47 PM PDT 24
Peak memory	602884 kb
Host	smart-dc9abf85-562f-4b56-8788-56c16cd85502
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400080 1288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.4000801288
Directory	/workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.4150952855
Short name	T213
Test name
Test status
Simulation time	17213530832 ps
CPU time	4010.81 seconds
Started	May 23 04:14:45 PM PDT 24
Finished	May 23 05:21:38 PM PDT 24
Peak memory	602584 kb
Host	smart-4312da49-78be-4399-98c7-2f6a9df6e269
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41509 52855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.4150952855
Directory	/workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_app_rom.4144801375
Short name	T390
Test name
Test status
Simulation time	2519597996 ps
CPU time	189.28 seconds
Started	May 23 04:12:04 PM PDT 24
Finished	May 23 04:15:17 PM PDT 24
Peak memory	601300 kb
Host	smart-c7d907b6-26a4-4e2c-8763-5557eeb18a7c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144801375 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.4144801375
Directory	/workspace/2.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_entropy.2760310578
Short name	T1061
Test name
Test status
Simulation time	3090249876 ps
CPU time	323.24 seconds
Started	May 23 04:04:15 PM PDT 24
Finished	May 23 04:09:39 PM PDT 24
Peak memory	601568 kb
Host	smart-cc59cd07-f7c9-4a29-bf53-184dd5a5afd9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760310578 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.2760310578
Directory	/workspace/2.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_idle.1915877825
Short name	T1095
Test name
Test status
Simulation time	2527397272 ps
CPU time	193.71 seconds
Started	May 23 04:12:16 PM PDT 24
Finished	May 23 04:15:31 PM PDT 24
Peak memory	601480 kb
Host	smart-dd6d18b2-820f-4de9-a932-cc652c52c587
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915877825 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1915877825
Directory	/workspace/2.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2174221746
Short name	T894
Test name
Test status
Simulation time	2960629552 ps
CPU time	189.38 seconds
Started	May 23 04:14:46 PM PDT 24
Finished	May 23 04:17:57 PM PDT 24
Peak memory	601616 kb
Host	smart-caf96290-ea5f-4af3-894c-e6fe89b2c638
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174221746 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.2174221746
Directory	/workspace/2.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2090579658
Short name	T1229
Test name
Test status
Simulation time	3120449080 ps
CPU time	334.49 seconds
Started	May 23 04:12:27 PM PDT 24
Finished	May 23 04:18:03 PM PDT 24
Peak memory	601300 kb
Host	smart-3def1f52-1184-4257-b367-71b4995d1ca6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090579658 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.2090579658
Directory	/workspace/2.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2244836203
Short name	T943
Test name
Test status
Simulation time	3060364108 ps
CPU time	300.03 seconds
Started	May 23 04:11:50 PM PDT 24
Finished	May 23 04:16:52 PM PDT 24
Peak memory	601364 kb
Host	smart-fedcb8de-9d68-44c5-8e4c-b7e310c63cd4
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244836203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.2244836203
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3461798782
Short name	T1234
Test name
Test status
Simulation time	3181422227 ps
CPU time	292.83 seconds
Started	May 23 04:18:06 PM PDT 24
Finished	May 23 04:23:01 PM PDT 24
Peak memory	601552 kb
Host	smart-eba4bbb5-7b94-4d04-8ef1-70a9c10ad56b
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34617987 82 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3461798782
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_smoketest.855198619
Short name	T177
Test name
Test status
Simulation time	3277787672 ps
CPU time	267.35 seconds
Started	May 23 04:15:55 PM PDT 24
Finished	May 23 04:20:24 PM PDT 24
Peak memory	601456 kb
Host	smart-6ea52643-50fc-4928-bb93-ac1a96631a24
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855198619 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_smoketest.855198619
Directory	/workspace/2.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2930608104
Short name	T925
Test name
Test status
Simulation time	3139037390 ps
CPU time	368.65 seconds
Started	May 23 04:04:00 PM PDT 24
Finished	May 23 04:10:11 PM PDT 24
Peak memory	601492 kb
Host	smart-39ec4600-9d54-4566-b87b-22504a32541f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930608104 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.2930608104
Directory	/workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1062293472
Short name	T978
Test name
Test status
Simulation time	17714047108 ps
CPU time	3445.72 seconds
Started	May 23 04:06:28 PM PDT 24
Finished	May 23 05:03:55 PM PDT 24
Peak memory	602104 kb
Host	smart-3663f527-129e-4e7f-a2a7-34eeff444a75
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1062293472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1062293472
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1638616339
Short name	T889
Test name
Test status
Simulation time	18188590537 ps
CPU time	3686.25 seconds
Started	May 23 04:05:08 PM PDT 24
Finished	May 23 05:06:35 PM PDT 24
Peak memory	601872 kb
Host	smart-e981ff2a-24db-4f44-9fb7-8cc0485caa4d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1638616339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1638616339
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2893656062
Short name	T398
Test name
Test status
Simulation time	25291437886 ps
CPU time	3263.29 seconds
Started	May 23 04:16:41 PM PDT 24
Finished	May 23 05:11:06 PM PDT 24
Peak memory	602140 kb
Host	smart-8f21fdee-5d63-4405-a985-c309caafeed2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893656062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2893656062
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.636234431
Short name	T260
Test name
Test status
Simulation time	3503470238 ps
CPU time	502.72 seconds
Started	May 23 04:05:01 PM PDT 24
Finished	May 23 04:13:25 PM PDT 24
Peak memory	601604 kb
Host	smart-015e1a79-70b7-488e-829d-6708f5bb1dea
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636234431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.636234431
Directory	/workspace/2.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_randomness.3873742700
Short name	T1079
Test name
Test status
Simulation time	6023960676 ps
CPU time	884.09 seconds
Started	May 23 04:05:30 PM PDT 24
Finished	May 23 04:20:15 PM PDT 24
Peak memory	601884 kb
Host	smart-ce86a8fc-3658-485d-8d61-d8bdd4396942
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3873742700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.3873742700
Directory	/workspace/2.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_smoketest.950878745
Short name	T1150
Test name
Test status
Simulation time	10930513456 ps
CPU time	2204.15 seconds
Started	May 23 04:17:20 PM PDT 24
Finished	May 23 04:54:06 PM PDT 24
Peak memory	602036 kb
Host	smart-608c1563-e2ef-432a-81cd-281a579bed5a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950878745 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_smoketest.950878745
Directory	/workspace/2.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2367755189
Short name	T897
Test name
Test status
Simulation time	3043094776 ps
CPU time	306.93 seconds
Started	May 23 04:05:16 PM PDT 24
Finished	May 23 04:10:24 PM PDT 24
Peak memory	601860 kb
Host	smart-6b2394bf-6cd8-4186-82d2-837145e0a53e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367755189 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.2367755189
Directory	/workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3773270284
Short name	T210
Test name
Test status
Simulation time	8293546340 ps
CPU time	1193.42 seconds
Started	May 23 04:05:28 PM PDT 24
Finished	May 23 04:25:23 PM PDT 24
Peak memory	602424 kb
Host	smart-a4471181-6d02-41fa-9daf-6a3a3326bf56
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3773270284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.3773270284
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2160305626
Short name	T1049
Test name
Test status
Simulation time	6614448248 ps
CPU time	1185.77 seconds
Started	May 23 04:04:08 PM PDT 24
Finished	May 23 04:23:55 PM PDT 24
Peak memory	603132 kb
Host	smart-596afe14-e4ba-4acd-bec8-7f109f57ff58
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2160305626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.2160305626
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1422647323
Short name	T948
Test name
Test status
Simulation time	9176325050 ps
CPU time	1283.61 seconds
Started	May 23 04:05:13 PM PDT 24
Finished	May 23 04:26:38 PM PDT 24
Peak memory	602420 kb
Host	smart-7853059b-30ff-444c-a393-32341dfd4eb4
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1422647323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.1422647323
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4060920250
Short name	T910
Test name
Test status
Simulation time	4958024060 ps
CPU time	718.65 seconds
Started	May 23 04:04:14 PM PDT 24
Finished	May 23 04:16:14 PM PDT 24
Peak memory	601684 kb
Host	smart-493f8dc2-4e32-44b6-92b0-9f9b478e6737
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=4060920250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4060920250
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3401313122
Short name	T844
Test name
Test status
Simulation time	3299594112 ps
CPU time	248.21 seconds
Started	May 23 04:16:25 PM PDT 24
Finished	May 23 04:20:35 PM PDT 24
Peak memory	601472 kb
Host	smart-e9317505-49a3-4cc4-b57d-a7fd0a11639c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401313122 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.3401313122
Directory	/workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_plic_sw_irq.3142377379
Short name	T229
Test name
Test status
Simulation time	2972953440 ps
CPU time	274.34 seconds
Started	May 23 04:12:28 PM PDT 24
Finished	May 23 04:17:03 PM PDT 24
Peak memory	601316 kb
Host	smart-87f64ba9-4652-42f7-9cba-eba0edf8a389
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142377379 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.3142377379
Directory	/workspace/2.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_power_idle_load.1813322714
Short name	T645
Test name
Test status
Simulation time	4367560216 ps
CPU time	543.89 seconds
Started	May 23 04:17:42 PM PDT 24
Finished	May 23 04:26:46 PM PDT 24
Peak memory	602264 kb
Host	smart-982cebf0-1e61-4e44-841e-e85dc551e5f9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813322714 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.1813322714
Directory	/workspace/2.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/2.chip_sw_power_sleep_load.1030291858
Short name	T339
Test name
Test status
Simulation time	10526520056 ps
CPU time	500.29 seconds
Started	May 23 04:15:16 PM PDT 24
Finished	May 23 04:23:38 PM PDT 24
Peak memory	603760 kb
Host	smart-99e1b285-269c-4ed1-8d8c-3377e0eec0ea
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030291858 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1030291858
Directory	/workspace/2.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1800589288
Short name	T1040
Test name
Test status
Simulation time	8886974119 ps
CPU time	1515.25 seconds
Started	May 23 04:05:07 PM PDT 24
Finished	May 23 04:30:23 PM PDT 24
Peak memory	604104 kb
Host	smart-4d5a6cbe-3884-4031-a57b-7edc6a68dece
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800 589288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1800589288
Directory	/workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.560513831
Short name	T1008
Test name
Test status
Simulation time	22532864612 ps
CPU time	2063.7 seconds
Started	May 23 04:13:22 PM PDT 24
Finished	May 23 04:47:47 PM PDT 24
Peak memory	602508 kb
Host	smart-80536c48-e5c6-4d34-8699-e0369d4bf025
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560 513831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.560513831
Directory	/workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1064343694
Short name	T1088
Test name
Test status
Simulation time	13967184045 ps
CPU time	1598.56 seconds
Started	May 23 04:05:01 PM PDT 24
Finished	May 23 04:31:41 PM PDT 24
Peak memory	604168 kb
Host	smart-58b47342-90de-459f-99dd-b28bcfe97cf9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1064343694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1064343694
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.988276682
Short name	T120
Test name
Test status
Simulation time	21037463480 ps
CPU time	1299.68 seconds
Started	May 23 04:15:10 PM PDT 24
Finished	May 23 04:36:51 PM PDT 24
Peak memory	603376 kb
Host	smart-748c4711-aaac-4011-b68a-758c388172f1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 988276682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.988276682
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1824895923
Short name	T907
Test name
Test status
Simulation time	9625567658 ps
CPU time	831.51 seconds
Started	May 23 04:05:33 PM PDT 24
Finished	May 23 04:19:25 PM PDT 24
Peak memory	602500 kb
Host	smart-52708da0-1186-414a-967e-0966d3c67c91
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824895923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.1824895923
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1207477283
Short name	T842
Test name
Test status
Simulation time	6060631800 ps
CPU time	408.87 seconds
Started	May 23 04:04:11 PM PDT 24
Finished	May 23 04:11:01 PM PDT 24
Peak memory	608784 kb
Host	smart-a01f69f3-3454-42b0-9967-378cb2c67473
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1207477283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1207477283
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2675053214
Short name	T970
Test name
Test status
Simulation time	8129128835 ps
CPU time	537.35 seconds
Started	May 23 04:06:25 PM PDT 24
Finished	May 23 04:15:23 PM PDT 24
Peak memory	602480 kb
Host	smart-07b1e8bf-c88e-4d7d-a576-84882c2e006c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675053214 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2675053214
Directory	/workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3424571253
Short name	T1227
Test name
Test status
Simulation time	3825053042 ps
CPU time	263.2 seconds
Started	May 23 04:06:38 PM PDT 24
Finished	May 23 04:11:02 PM PDT 24
Peak memory	608780 kb
Host	smart-cdabf3fc-885c-4e6f-9ff1-03ace8946d00
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3424571253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3424571253
Directory	/workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4069326170
Short name	T1129
Test name
Test status
Simulation time	10461404303 ps
CPU time	1184.82 seconds
Started	May 23 04:03:06 PM PDT 24
Finished	May 23 04:22:52 PM PDT 24
Peak memory	604132 kb
Host	smart-297db7ed-dda2-4716-b39f-70193aab4190
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069326170 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4069326170
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3549863881
Short name	T387
Test name
Test status
Simulation time	6980033176 ps
CPU time	453.97 seconds
Started	May 23 04:14:32 PM PDT 24
Finished	May 23 04:22:07 PM PDT 24
Peak memory	602020 kb
Host	smart-d3df3d25-805f-4b5f-a85b-23ec21e6aa04
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549863881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3549863881
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1141262946
Short name	T1214
Test name
Test status
Simulation time	7123546340 ps
CPU time	896 seconds
Started	May 23 04:04:30 PM PDT 24
Finished	May 23 04:19:27 PM PDT 24
Peak memory	602492 kb
Host	smart-8d51df7b-ce3f-47d3-84b2-c2bd302e2de6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141262946 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.1141262946
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1625196477
Short name	T396
Test name
Test status
Simulation time	26594062860 ps
CPU time	2499.12 seconds
Started	May 23 04:05:25 PM PDT 24
Finished	May 23 04:47:05 PM PDT 24
Peak memory	604204 kb
Host	smart-d083e139-da26-4b33-9841-2cf6d8957b16
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1625196477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1625196477
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4020027305
Short name	T53
Test name
Test status
Simulation time	19073962760 ps
CPU time	1755.97 seconds
Started	May 23 04:16:11 PM PDT 24
Finished	May 23 04:45:28 PM PDT 24
Peak memory	603644 kb
Host	smart-3acb9bb9-e931-498a-90f6-08db3ff2122a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4020027305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4020027305
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2110072999
Short name	T244
Test name
Test status
Simulation time	36033238280 ps
CPU time	3502.56 seconds
Started	May 23 04:06:04 PM PDT 24
Finished	May 23 05:04:28 PM PDT 24
Peak memory	605052 kb
Host	smart-af836ece-119a-4d6d-97b3-54ebf0341622
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110072999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2110072999
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3602500275
Short name	T331
Test name
Test status
Simulation time	5246161000 ps
CPU time	380.35 seconds
Started	May 23 04:16:03 PM PDT 24
Finished	May 23 04:22:25 PM PDT 24
Peak memory	603860 kb
Host	smart-419dd1f7-051b-45d2-9ae3-213cbd9e923a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3602500275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3602500275
Directory	/workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2249728103
Short name	T367
Test name
Test status
Simulation time	2785029084 ps
CPU time	216.62 seconds
Started	May 23 04:04:08 PM PDT 24
Finished	May 23 04:07:46 PM PDT 24
Peak memory	601356 kb
Host	smart-f47a7dda-8569-40f2-a564-d72c52c3eff5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249728103 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.2249728103
Directory	/workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.630656130
Short name	T1155
Test name
Test status
Simulation time	4140017377 ps
CPU time	413.94 seconds
Started	May 23 04:06:51 PM PDT 24
Finished	May 23 04:13:46 PM PDT 24
Peak memory	608624 kb
Host	smart-e857d7e4-2cdc-44b1-aadd-f652518242f5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=630656130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.630656130
Directory	/workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.999268115
Short name	T1133
Test name
Test status
Simulation time	5029886070 ps
CPU time	431.61 seconds
Started	May 23 04:13:53 PM PDT 24
Finished	May 23 04:21:06 PM PDT 24
Peak memory	603312 kb
Host	smart-7422dc8d-46e3-4a19-8a79-44307899375a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=999268115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.999268115
Directory	/workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3419170827
Short name	T937
Test name
Test status
Simulation time	4210179008 ps
CPU time	439.42 seconds
Started	May 23 04:18:28 PM PDT 24
Finished	May 23 04:25:49 PM PDT 24
Peak memory	601616 kb
Host	smart-16cf47ad-2ee0-418e-a47e-34cab579459d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419170827 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.3419170827
Directory	/workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2460042664
Short name	T977
Test name
Test status
Simulation time	6537579660 ps
CPU time	1243.5 seconds
Started	May 23 04:03:48 PM PDT 24
Finished	May 23 04:24:33 PM PDT 24
Peak memory	602364 kb
Host	smart-d3a3c2ec-cbf6-4498-9d66-a1c2761b029c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460042664 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.2460042664
Directory	/workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1994864394
Short name	T369
Test name
Test status
Simulation time	5426834376 ps
CPU time	522.94 seconds
Started	May 23 04:04:20 PM PDT 24
Finished	May 23 04:13:05 PM PDT 24
Peak memory	602168 kb
Host	smart-d0dd7d5d-f207-46bb-ba6d-6ad2aa5bc1de
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994864394 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1994864394
Directory	/workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3014010680
Short name	T1231
Test name
Test status
Simulation time	5815332456 ps
CPU time	426.64 seconds
Started	May 23 04:17:39 PM PDT 24
Finished	May 23 04:24:46 PM PDT 24
Peak memory	602152 kb
Host	smart-c3ecb736-519e-4033-a491-1657d14b010e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014010680 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.3014010680
Directory	/workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4190399542
Short name	T1171
Test name
Test status
Simulation time	4591912802 ps
CPU time	414.86 seconds
Started	May 23 04:05:36 PM PDT 24
Finished	May 23 04:12:32 PM PDT 24
Peak memory	602156 kb
Host	smart-abb29846-b69f-4106-be2d-2fa1ae7802e7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419 0399542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.4190399542
Directory	/workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1090936718
Short name	T378
Test name
Test status
Simulation time	9452232097 ps
CPU time	663.41 seconds
Started	May 23 04:14:45 PM PDT 24
Finished	May 23 04:25:49 PM PDT 24
Peak memory	602488 kb
Host	smart-e13b7734-d1d2-4dd3-9f58-1edcf08e2cb3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090936718 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1090936718
Directory	/workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1301266375
Short name	T222
Test name
Test status
Simulation time	12131660050 ps
CPU time	1325.44 seconds
Started	May 23 04:07:02 PM PDT 24
Finished	May 23 04:29:09 PM PDT 24
Peak memory	603668 kb
Host	smart-6bf3b698-0041-47d1-93be-c8b1276c5417
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1301266375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1301266375
Directory	/workspace/2.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3494594302
Short name	T220
Test name
Test status
Simulation time	4785134248 ps
CPU time	522.79 seconds
Started	May 23 04:05:37 PM PDT 24
Finished	May 23 04:14:21 PM PDT 24
Peak memory	602260 kb
Host	smart-3a053217-2637-45c4-b7e1-b25096f8b35d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494594302 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.3494594302
Directory	/workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4061419348
Short name	T272
Test name
Test status
Simulation time	5284100194 ps
CPU time	698.71 seconds
Started	May 23 04:07:40 PM PDT 24
Finished	May 23 04:19:21 PM PDT 24
Peak memory	634580 kb
Host	smart-b3872d30-c5ee-42d8-9b66-a0e60b593828
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4061419348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.4061419348
Directory	/workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.748147521
Short name	T1072
Test name
Test status
Simulation time	2609601192 ps
CPU time	218.89 seconds
Started	May 23 04:17:04 PM PDT 24
Finished	May 23 04:20:44 PM PDT 24
Peak memory	601492 kb
Host	smart-d498ffa0-85f9-4e48-b2d6-1331db9fc73a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748147521 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_rstmgr_smoketest.748147521
Directory	/workspace/2.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2364786777
Short name	T902
Test name
Test status
Simulation time	3651947226 ps
CPU time	304.28 seconds
Started	May 23 04:02:41 PM PDT 24
Finished	May 23 04:07:47 PM PDT 24
Peak memory	601520 kb
Host	smart-27cd4de0-4f62-4de4-a9d4-ac09714650bf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364786777 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2364786777
Directory	/workspace/2.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2714100500
Short name	T358
Test name
Test status
Simulation time	2677050900 ps
CPU time	188.86 seconds
Started	May 23 04:05:24 PM PDT 24
Finished	May 23 04:08:34 PM PDT 24
Peak memory	601384 kb
Host	smart-d8f8a295-8ebc-44e0-8d2f-797f760f7657
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714100500 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.2714100500
Directory	/workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.551875955
Short name	T271
Test name
Test status
Simulation time	2954111522 ps
CPU time	286.04 seconds
Started	May 23 04:14:16 PM PDT 24
Finished	May 23 04:19:03 PM PDT 24
Peak memory	601516 kb
Host	smart-8fb197d6-2c7d-46d5-85a9-f851a0415e5a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=551875955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.551875955
Directory	/workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2017585176
Short name	T269
Test name
Test status
Simulation time	2824726535 ps
CPU time	230.09 seconds
Started	May 23 04:15:19 PM PDT 24
Finished	May 23 04:19:10 PM PDT 24
Peak memory	601540 kb
Host	smart-3c194375-c98e-4d25-88be-fc89f1ef383e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017585176 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.2017585176
Directory	/workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.289123507
Short name	T490
Test name
Test status
Simulation time	4966183120 ps
CPU time	904.3 seconds
Started	May 23 04:06:05 PM PDT 24
Finished	May 23 04:21:11 PM PDT 24
Peak memory	601848 kb
Host	smart-d1c1ef1b-dd58-418b-a0a2-c823d435066e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28912 3507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.289123507
Directory	/workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2341274541
Short name	T1215
Test name
Test status
Simulation time	5772650982 ps
CPU time	1042.34 seconds
Started	May 23 04:05:03 PM PDT 24
Finished	May 23 04:22:27 PM PDT 24
Peak memory	601804 kb
Host	smart-d3397ffe-4d51-4f27-8249-21f602bb8b67
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2341274541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.2341274541
Directory	/workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.761487624
Short name	T637
Test name
Test status
Simulation time	5284442957 ps
CPU time	497.62 seconds
Started	May 23 04:14:20 PM PDT 24
Finished	May 23 04:22:40 PM PDT 24
Peak memory	610192 kb
Host	smart-964dae97-9c46-4e4b-9b1c-6827aa7ad0d3
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761487624 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.761487624
Directory	/workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2030937896
Short name	T65
Test name
Test status
Simulation time	3354213864 ps
CPU time	460.73 seconds
Started	May 23 04:13:54 PM PDT 24
Finished	May 23 04:21:36 PM PDT 24
Peak memory	611332 kb
Host	smart-bfae7461-cd14-4fb5-abec-6a2a1e2c4cac
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203093 7896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2030937896
Directory	/workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1421576651
Short name	T1081
Test name
Test status
Simulation time	3121767848 ps
CPU time	313.06 seconds
Started	May 23 04:17:10 PM PDT 24
Finished	May 23 04:22:24 PM PDT 24
Peak memory	601380 kb
Host	smart-8fd26159-473f-4eb5-bf1c-bbaa4f74a305
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421576651 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.1421576651
Directory	/workspace/2.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_irq.582713866
Short name	T232
Test name
Test status
Simulation time	3006697200 ps
CPU time	209.05 seconds
Started	May 23 04:09:06 PM PDT 24
Finished	May 23 04:12:36 PM PDT 24
Peak memory	601580 kb
Host	smart-6b331207-6465-4c49-8d8c-77376d179b43
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582713866 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_irq.582713866
Directory	/workspace/2.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1139149085
Short name	T1048
Test name
Test status
Simulation time	2554080324 ps
CPU time	332.11 seconds
Started	May 23 04:15:24 PM PDT 24
Finished	May 23 04:20:58 PM PDT 24
Peak memory	601356 kb
Host	smart-f43f9e12-8b01-479a-a94b-68b440494872
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139149085 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.1139149085
Directory	/workspace/2.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3115143111
Short name	T160
Test name
Test status
Simulation time	4102287130 ps
CPU time	569.88 seconds
Started	May 23 04:12:34 PM PDT 24
Finished	May 23 04:22:06 PM PDT 24
Peak memory	601908 kb
Host	smart-35968efa-7062-48e7-8ee0-7e86a4804a9c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31151431 11 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3115143111
Directory	/workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.4016942613
Short name	T163
Test name
Test status
Simulation time	3044959710 ps
CPU time	210.25 seconds
Started	May 23 04:15:44 PM PDT 24
Finished	May 23 04:19:16 PM PDT 24
Peak memory	602316 kb
Host	smart-09dae661-fd95-4b25-bfe0-b191675ce7d8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016942 613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.4016942613
Directory	/workspace/2.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2744184262
Short name	T198
Test name
Test status
Simulation time	8795160080 ps
CPU time	1391.22 seconds
Started	May 23 04:05:09 PM PDT 24
Finished	May 23 04:28:22 PM PDT 24
Peak memory	602488 kb
Host	smart-bf9e9985-19a3-4e71-a25a-8687ebf31865
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744184262 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.2744184262
Directory	/workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.797227654
Short name	T1
Test name
Test status
Simulation time	8642711600 ps
CPU time	942.87 seconds
Started	May 23 04:13:07 PM PDT 24
Finished	May 23 04:28:51 PM PDT 24
Peak memory	603352 kb
Host	smart-78c8e131-d1a6-4ff2-8c59-0dbee1741aa4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797227654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sle ep_sram_ret_contents_no_scramble.797227654
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2891119228
Short name	T1108
Test name
Test status
Simulation time	6417095568 ps
CPU time	580.52 seconds
Started	May 23 04:11:36 PM PDT 24
Finished	May 23 04:21:17 PM PDT 24
Peak memory	603016 kb
Host	smart-2efb4d11-03d6-4d16-94a3-35bd665ca2a6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891119228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.2891119228
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.88835371
Short name	T186
Test name
Test status
Simulation time	6630994817 ps
CPU time	734.83 seconds
Started	May 23 04:06:12 PM PDT 24
Finished	May 23 04:18:27 PM PDT 24
Peak memory	620480 kb
Host	smart-3bf445b8-08aa-498c-aba6-f526c44200aa
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88835371 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.88835371
Directory	/workspace/2.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3731061231
Short name	T187
Test name
Test status
Simulation time	3491338157 ps
CPU time	416.66 seconds
Started	May 23 04:03:49 PM PDT 24
Finished	May 23 04:10:48 PM PDT 24
Peak memory	619524 kb
Host	smart-d50d0d21-196f-4574-948e-657ab1437318
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731061231 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.3731061231
Directory	/workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_tpm.1053752670
Short name	T39
Test name
Test status
Simulation time	3065852118 ps
CPU time	379.73 seconds
Started	May 23 04:05:12 PM PDT 24
Finished	May 23 04:11:33 PM PDT 24
Peak memory	611360 kb
Host	smart-12702694-3898-4ce3-aeca-59b2b4bd52eb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053752670 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.1053752670
Directory	/workspace/2.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1445056376
Short name	T135
Test name
Test status
Simulation time	8693542670 ps
CPU time	751.63 seconds
Started	May 23 04:11:14 PM PDT 24
Finished	May 23 04:23:47 PM PDT 24
Peak memory	602112 kb
Host	smart-0683c928-82d4-4516-86ca-4e2a9ce9d1e7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445056376 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1445056376
Directory	/workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.167486053
Short name	T265
Test name
Test status
Simulation time	5587362238 ps
CPU time	706.53 seconds
Started	May 23 04:12:00 PM PDT 24
Finished	May 23 04:23:49 PM PDT 24
Peak memory	603004 kb
Host	smart-cc952180-200b-4296-993c-28b06e63a936
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167486053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ sram_ctrl_scrambled_access.167486053
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3868726764
Short name	T261
Test name
Test status
Simulation time	4738553258 ps
CPU time	538.15 seconds
Started	May 23 04:14:37 PM PDT 24
Finished	May 23 04:23:36 PM PDT 24
Peak memory	603020 kb
Host	smart-5c7cca1b-c864-4412-95be-3bad0b5921c5
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868726764 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3868726764
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.4219159767
Short name	T1177
Test name
Test status
Simulation time	2333789012 ps
CPU time	272.06 seconds
Started	May 23 04:15:44 PM PDT 24
Finished	May 23 04:20:18 PM PDT 24
Peak memory	601380 kb
Host	smart-7bb2842c-9d9f-4107-9dda-523f9d0081d6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219159767 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.4219159767
Directory	/workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2334935564
Short name	T19
Test name
Test status
Simulation time	20023591346 ps
CPU time	3180.08 seconds
Started	May 23 04:04:32 PM PDT 24
Finished	May 23 04:57:34 PM PDT 24
Peak memory	602212 kb
Host	smart-2935af23-6483-4a95-ac3a-bf037b1bb1c2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334935564 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.2334935564
Directory	/workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3783735358
Short name	T1051
Test name
Test status
Simulation time	4516806838 ps
CPU time	686.69 seconds
Started	May 23 04:03:50 PM PDT 24
Finished	May 23 04:15:20 PM PDT 24
Peak memory	606616 kb
Host	smart-f893dd48-8b39-4e7f-8451-0227621ed872
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783735358 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.3783735358
Directory	/workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.457088029
Short name	T665
Test name
Test status
Simulation time	22073709808 ps
CPU time	1777.75 seconds
Started	May 23 04:04:52 PM PDT 24
Finished	May 23 04:34:31 PM PDT 24
Peak memory	605584 kb
Host	smart-ef3a5f93-b5b0-41df-a418-350bd4acd769
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45708802 9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.457088029
Directory	/workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.791720339
Short name	T35
Test name
Test status
Simulation time	5163584350 ps
CPU time	356.79 seconds
Started	May 23 04:11:20 PM PDT 24
Finished	May 23 04:17:19 PM PDT 24
Peak memory	602248 kb
Host	smart-afc5c4a5-ceee-4b34-8408-2dc447d38363
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791720339 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.791720339
Directory	/workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3323548143
Short name	T287
Test name
Test status
Simulation time	3258506520 ps
CPU time	615.71 seconds
Started	May 23 04:07:19 PM PDT 24
Finished	May 23 04:17:37 PM PDT 24
Peak memory	611416 kb
Host	smart-f013be05-4fd9-48f3-b7a0-bb35f2c26568
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3323548143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.3323548143
Directory	/workspace/2.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_smoketest.379812999
Short name	T1076
Test name
Test status
Simulation time	2897723172 ps
CPU time	297.56 seconds
Started	May 23 04:21:51 PM PDT 24
Finished	May 23 04:26:50 PM PDT 24
Peak memory	601648 kb
Host	smart-4e766100-57b9-4589-9c3f-9e6286689d82
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379812999 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_uart_smoketest.379812999
Directory	/workspace/2.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx.303242995
Short name	T202
Test name
Test status
Simulation time	4254155532 ps
CPU time	787.83 seconds
Started	May 23 04:02:10 PM PDT 24
Finished	May 23 04:15:20 PM PDT 24
Peak memory	608124 kb
Host	smart-c8c1373d-4d80-49ab-b0a4-dfd66302c9c8
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303242995 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.303242995
Directory	/workspace/2.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.574039736
Short name	T1236
Test name
Test status
Simulation time	4219002629 ps
CPU time	678.77 seconds
Started	May 23 04:04:16 PM PDT 24
Finished	May 23 04:15:37 PM PDT 24
Peak memory	610868 kb
Host	smart-4413f594-503d-4a82-9156-585be272715c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574039736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_ alt_clk_freq.574039736
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1644713726
Short name	T949
Test name
Test status
Simulation time	12888166564 ps
CPU time	1681.14 seconds
Started	May 23 04:07:57 PM PDT 24
Finished	May 23 04:36:00 PM PDT 24
Peak memory	611184 kb
Host	smart-ac33be3f-f2f2-4e27-8408-699f3d6dfcfb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644713726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1644713726
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1569089979
Short name	T984
Test name
Test status
Simulation time	4141437876 ps
CPU time	728.58 seconds
Started	May 23 04:07:35 PM PDT 24
Finished	May 23 04:19:45 PM PDT 24
Peak memory	608128 kb
Host	smart-d6be3e4b-cbc1-4f02-84f5-10b75185d6bc
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569089979 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1569089979
Directory	/workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3925632939
Short name	T303
Test name
Test status
Simulation time	4280631736 ps
CPU time	809.92 seconds
Started	May 23 04:02:23 PM PDT 24
Finished	May 23 04:15:54 PM PDT 24
Peak memory	608124 kb
Host	smart-5ee2b686-87b7-4e80-877f-7ab752c9ccf2
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925632939 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3925632939
Directory	/workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.4183037031
Short name	T1062
Test name
Test status
Simulation time	4397971176 ps
CPU time	684.78 seconds
Started	May 23 04:01:32 PM PDT 24
Finished	May 23 04:12:59 PM PDT 24
Peak memory	611088 kb
Host	smart-c17e6865-33f6-4117-899c-fe8dd5d51cb8
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183037031 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.4183037031
Directory	/workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_dev.54444557
Short name	T1159
Test name
Test status
Simulation time	3185535438 ps
CPU time	177.01 seconds
Started	May 23 04:13:10 PM PDT 24
Finished	May 23 04:16:08 PM PDT 24
Peak memory	612764 kb
Host	smart-52ec6b37-5ff3-4d07-9e02-07372efca4da
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=54444557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.54444557
Directory	/workspace/2.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_prod.3987407958
Short name	T66
Test name
Test status
Simulation time	2105607336 ps
CPU time	154.24 seconds
Started	May 23 04:13:08 PM PDT 24
Finished	May 23 04:15:43 PM PDT 24
Peak memory	611152 kb
Host	smart-9850b05c-6f25-4f88-beae-8fd8fcbd1499
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987407958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.3987407958
Directory	/workspace/2.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_rma.1861136181
Short name	T99
Test name
Test status
Simulation time	3045879021 ps
CPU time	194.09 seconds
Started	May 23 04:14:16 PM PDT 24
Finished	May 23 04:17:31 PM PDT 24
Peak memory	611200 kb
Host	smart-16c91067-ed9e-4cc1-8d03-82b97e768de6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861136181 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.1861136181
Directory	/workspace/2.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_dev.943259089
Short name	T872
Test name
Test status
Simulation time	14174079284 ps
CPU time	3247.33 seconds
Started	May 23 04:19:56 PM PDT 24
Finished	May 23 05:14:04 PM PDT 24
Peak memory	602016 kb
Host	smart-9041e455-9cc4-47c3-a072-7d2552e70f54
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943259089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_dev.943259089
Directory	/workspace/2.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_prod.2045490558
Short name	T1092
Test name
Test status
Simulation time	14185444540 ps
CPU time	3501.55 seconds
Started	May 23 04:21:13 PM PDT 24
Finished	May 23 05:19:35 PM PDT 24
Peak memory	603372 kb
Host	smart-76ef29e7-4829-4166-a0e3-f9d1566c4f41
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045490558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.2045490558
Directory	/workspace/2.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3738218597
Short name	T913
Test name
Test status
Simulation time	15049152645 ps
CPU time	3254.34 seconds
Started	May 23 04:21:07 PM PDT 24
Finished	May 23 05:15:23 PM PDT 24
Peak memory	603368 kb
Host	smart-eb7a333d-45cb-4547-b278-126f282234e2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738218597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.3738218597
Directory	/workspace/2.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_rma.965668273
Short name	T996
Test name
Test status
Simulation time	14052318236 ps
CPU time	3467.67 seconds
Started	May 23 04:19:38 PM PDT 24
Finished	May 23 05:17:27 PM PDT 24
Peak memory	603308 kb
Host	smart-f0f0a34d-6b13-4caa-b240-db8587484232
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965668273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_rma.965668273
Directory	/workspace/2.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3376144949
Short name	T1173
Test name
Test status
Simulation time	11214175012 ps
CPU time	3032.85 seconds
Started	May 23 04:18:35 PM PDT 24
Finished	May 23 05:09:09 PM PDT 24
Peak memory	602228 kb
Host	smart-4ca7b306-540c-489b-b77f-c9f455a58312
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376144949 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.3376144949
Directory	/workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.9391335
Short name	T1124
Test name
Test status
Simulation time	14963597508 ps
CPU time	3468.69 seconds
Started	May 23 04:24:49 PM PDT 24
Finished	May 23 05:22:39 PM PDT 24
Peak memory	603184 kb
Host	smart-a78890bd-dcea-4e02-9210-f6c4ab6e506c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9391335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_ rom_ext_invalid_meas.9391335
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2241073373
Short name	T374
Test name
Test status
Simulation time	15732279272 ps
CPU time	3209.77 seconds
Started	May 23 04:19:49 PM PDT 24
Finished	May 23 05:13:20 PM PDT 24
Peak memory	603152 kb
Host	smart-6fea1513-c607-433d-820f-201c042c4303
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241073373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.2241073373
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3584614596
Short name	T866
Test name
Test status
Simulation time	14038820700 ps
CPU time	3007.26 seconds
Started	May 23 04:25:27 PM PDT 24
Finished	May 23 05:15:36 PM PDT 24
Peak memory	603160 kb
Host	smart-7638486c-9dd0-4c34-af92-096bc2d90cb7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584614596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.3584614596
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2169330676
Short name	T251
Test name
Test status
Simulation time	14048397400 ps
CPU time	4161.35 seconds
Started	May 23 04:19:25 PM PDT 24
Finished	May 23 05:28:47 PM PDT 24
Peak memory	603256 kb
Host	smart-0fb20ae9-f6e5-4528-bc9f-d8c2160d380d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169330676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.2169330676
Directory	/workspace/2.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/2.rom_e2e_shutdown_output.1430236250
Short name	T1043
Test name
Test status
Simulation time	22317170293 ps
CPU time	2539.09 seconds
Started	May 23 04:21:49 PM PDT 24
Finished	May 23 05:04:09 PM PDT 24
Peak memory	603564 kb
Host	smart-fd791408-8a23-4dfe-a32a-00e009aa11bd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430236250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.1430236250
Directory	/workspace/2.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/2.rom_keymgr_functest.2350366333
Short name	T173
Test name
Test status
Simulation time	3723137560 ps
CPU time	597.88 seconds
Started	May 23 04:16:00 PM PDT 24
Finished	May 23 04:25:58 PM PDT 24
Peak memory	602104 kb
Host	smart-a140325c-5a80-4eb5-9044-53754fd016b6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350366333 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2350366333
Directory	/workspace/2.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196705433
Short name	T641
Test name
Test status
Simulation time	4039377040 ps
CPU time	413.97 seconds
Started	May 23 04:20:12 PM PDT 24
Finished	May 23 04:27:07 PM PDT 24
Peak memory	637544 kb
Host	smart-2240a3d4-03db-4876-aced-4a6bd0e1c84d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196705433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1196705433
Directory	/workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/21.chip_sw_all_escalation_resets.3235810076
Short name	T1134
Test name
Test status
Simulation time	5973086302 ps
CPU time	719.29 seconds
Started	May 23 04:18:27 PM PDT 24
Finished	May 23 04:30:27 PM PDT 24
Peak memory	610332 kb
Host	smart-691704cf-0609-4ce9-b080-a22eee008fff
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3235810076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3235810076
Directory	/workspace/21.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657785284
Short name	T639
Test name
Test status
Simulation time	3738555646 ps
CPU time	474.88 seconds
Started	May 23 04:21:49 PM PDT 24
Finished	May 23 04:29:45 PM PDT 24
Peak memory	637476 kb
Host	smart-05c0d52f-db3c-40a1-96c0-5800a9e1850b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657785284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3657785284
Directory	/workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2242342757
Short name	T109
Test name
Test status
Simulation time	6357446696 ps
CPU time	795.36 seconds
Started	May 23 04:21:34 PM PDT 24
Finished	May 23 04:34:50 PM PDT 24
Peak memory	639184 kb
Host	smart-0f23c865-b4c2-4da2-b3cc-a0001bdf38c7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2242342757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2242342757
Directory	/workspace/23.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2742618785
Short name	T683
Test name
Test status
Simulation time	3378234950 ps
CPU time	486.37 seconds
Started	May 23 04:20:11 PM PDT 24
Finished	May 23 04:28:19 PM PDT 24
Peak memory	609296 kb
Host	smart-216f0bbc-fad5-48cf-b52d-4ec3d1b946ce
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742618785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2742618785
Directory	/workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3948213560
Short name	T728
Test name
Test status
Simulation time	4113011112 ps
CPU time	500.92 seconds
Started	May 23 04:18:27 PM PDT 24
Finished	May 23 04:26:49 PM PDT 24
Peak memory	637560 kb
Host	smart-6fb998cd-6db5-43ea-86ba-fdb0cb36002d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948213560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3948213560
Directory	/workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2982396374
Short name	T1015
Test name
Test status
Simulation time	4512676092 ps
CPU time	711.39 seconds
Started	May 23 04:21:35 PM PDT 24
Finished	May 23 04:33:28 PM PDT 24
Peak memory	639588 kb
Host	smart-87744e50-40f9-429b-a4d6-532cfd387352
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2982396374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2982396374
Directory	/workspace/25.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1610732968
Short name	T1014
Test name
Test status
Simulation time	3465900740 ps
CPU time	345.31 seconds
Started	May 23 04:19:51 PM PDT 24
Finished	May 23 04:25:37 PM PDT 24
Peak memory	637548 kb
Host	smart-0cc64656-81f0-4244-9174-938685148074
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610732968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1610732968
Directory	/workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3011194919
Short name	T389
Test name
Test status
Simulation time	4716850800 ps
CPU time	633.69 seconds
Started	May 23 04:20:24 PM PDT 24
Finished	May 23 04:30:59 PM PDT 24
Peak memory	638792 kb
Host	smart-9253d8cd-d174-4d6f-bb7f-e05d480ba4e4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3011194919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.3011194919
Directory	/workspace/28.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2620748155
Short name	T640
Test name
Test status
Simulation time	3696961982 ps
CPU time	431.76 seconds
Started	May 23 04:20:23 PM PDT 24
Finished	May 23 04:27:36 PM PDT 24
Peak memory	637580 kb
Host	smart-b3976ffd-f358-409f-9c9a-d7e650746874
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620748155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2620748155
Directory	/workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.601079810
Short name	T871
Test name
Test status
Simulation time	6196952472 ps
CPU time	460.66 seconds
Started	May 23 04:21:12 PM PDT 24
Finished	May 23 04:28:54 PM PDT 24
Peak memory	602124 kb
Host	smart-142a8273-d250-456e-8b1c-02d276503dd0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=601079810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.601079810
Directory	/workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2968168028
Short name	T254
Test name
Test status
Simulation time	4852311918 ps
CPU time	708.85 seconds
Started	May 23 04:21:51 PM PDT 24
Finished	May 23 04:33:42 PM PDT 24
Peak memory	603740 kb
Host	smart-ba5c9077-a507-4d67-beb5-a495a8686269
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2968168028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.2968168028
Directory	/workspace/3.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.596071331
Short name	T1115
Test name
Test status
Simulation time	13589969928 ps
CPU time	2330.48 seconds
Started	May 23 04:17:18 PM PDT 24
Finished	May 23 04:56:11 PM PDT 24
Peak memory	611208 kb
Host	smart-7c48c550-afd4-4649-b0f2-2516f1a051dd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=596071331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.596071331
Directory	/workspace/3.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx.285480996
Short name	T1219
Test name
Test status
Simulation time	4214384672 ps
CPU time	708.9 seconds
Started	May 23 04:18:13 PM PDT 24
Finished	May 23 04:30:03 PM PDT 24
Peak memory	611112 kb
Host	smart-091db95c-da1f-4b54-a982-39bdc4e4209d
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285480996 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.285480996
Directory	/workspace/3.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3873226002
Short name	T313
Test name
Test status
Simulation time	13468640435 ps
CPU time	1920.99 seconds
Started	May 23 04:15:41 PM PDT 24
Finished	May 23 04:47:43 PM PDT 24
Peak memory	610196 kb
Host	smart-edd01b84-daed-462a-b097-d7e759061da3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873226002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3873226002
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2544498511
Short name	T881
Test name
Test status
Simulation time	4428970754 ps
CPU time	560.8 seconds
Started	May 23 04:22:22 PM PDT 24
Finished	May 23 04:31:44 PM PDT 24
Peak memory	609116 kb
Host	smart-5f1ed019-c787-425e-8d1e-21aa83334e23
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544498511 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.2544498511
Directory	/workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.129158176
Short name	T974
Test name
Test status
Simulation time	4443240848 ps
CPU time	805.96 seconds
Started	May 23 04:16:29 PM PDT 24
Finished	May 23 04:29:56 PM PDT 24
Peak memory	611112 kb
Host	smart-90323a19-1ca0-4918-b7ab-779ebda0ccc7
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129158176 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.129158176
Directory	/workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.470998121
Short name	T1191
Test name
Test status
Simulation time	3930734100 ps
CPU time	858.74 seconds
Started	May 23 04:15:30 PM PDT 24
Finished	May 23 04:29:50 PM PDT 24
Peak memory	608112 kb
Host	smart-0826004f-5981-492a-85b1-51dc40c13dce
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470998121 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.470998121
Directory	/workspace/3.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_prod.2873800712
Short name	T1022
Test name
Test status
Simulation time	2089807328 ps
CPU time	136.54 seconds
Started	May 23 04:16:29 PM PDT 24
Finished	May 23 04:18:47 PM PDT 24
Peak memory	610696 kb
Host	smart-cb5bab26-a311-4b9e-a2d6-d88cc8adaa5e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873800712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.2873800712
Directory	/workspace/3.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_rma.3968327729
Short name	T1023
Test name
Test status
Simulation time	4995814306 ps
CPU time	383.29 seconds
Started	May 23 04:16:22 PM PDT 24
Finished	May 23 04:22:47 PM PDT 24
Peak memory	613256 kb
Host	smart-41056c25-fe4b-49a8-a0a4-adcdca8081fc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968327729 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.3968327729
Directory	/workspace/3.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2724792344
Short name	T67
Test name
Test status
Simulation time	5214204333 ps
CPU time	462.06 seconds
Started	May 23 04:16:47 PM PDT 24
Finished	May 23 04:24:31 PM PDT 24
Peak memory	619864 kb
Host	smart-f7f173c4-06fe-445a-bffe-17e08a3c28f2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724792344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.2724792344
Directory	/workspace/3.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/30.chip_sw_all_escalation_resets.165437544
Short name	T1120
Test name
Test status
Simulation time	5587433786 ps
CPU time	625.76 seconds
Started	May 23 04:19:42 PM PDT 24
Finished	May 23 04:30:09 PM PDT 24
Peak memory	638884 kb
Host	smart-8df439b2-03df-452a-aad2-b28b22b88306
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 165437544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.165437544
Directory	/workspace/30.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/31.chip_sw_all_escalation_resets.213155711
Short name	T283
Test name
Test status
Simulation time	5261255200 ps
CPU time	398.7 seconds
Started	May 23 04:21:13 PM PDT 24
Finished	May 23 04:27:52 PM PDT 24
Peak memory	638904 kb
Host	smart-8271d5b7-ab5e-4c38-b032-2adae141745e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 213155711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.213155711
Directory	/workspace/31.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4190811626
Short name	T771
Test name
Test status
Simulation time	3816718506 ps
CPU time	446.26 seconds
Started	May 23 04:23:34 PM PDT 24
Finished	May 23 04:31:01 PM PDT 24
Peak memory	636480 kb
Host	smart-274230d2-45d1-400c-95df-8137f94112e3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190811626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4190811626
Directory	/workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.179733464
Short name	T947
Test name
Test status
Simulation time	3309964210 ps
CPU time	399.18 seconds
Started	May 23 04:20:35 PM PDT 24
Finished	May 23 04:27:16 PM PDT 24
Peak memory	636448 kb
Host	smart-a25dc420-7315-4e0d-8a8b-63a9a8c0f6f5
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179733464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_s w_alert_handler_lpg_sleep_mode_alerts.179733464
Directory	/workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/35.chip_sw_all_escalation_resets.799323449
Short name	T80
Test name
Test status
Simulation time	5608446916 ps
CPU time	598.13 seconds
Started	May 23 04:21:15 PM PDT 24
Finished	May 23 04:31:14 PM PDT 24
Peak memory	610312 kb
Host	smart-8002efa0-a9da-4183-bc6c-b644130b0716
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 799323449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.799323449
Directory	/workspace/35.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.856874938
Short name	T224
Test name
Test status
Simulation time	3646953344 ps
CPU time	355.18 seconds
Started	May 23 04:19:27 PM PDT 24
Finished	May 23 04:25:23 PM PDT 24
Peak memory	637316 kb
Host	smart-9d7833c8-1b63-4c4b-bfdd-a3a14c166678
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856874938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_s w_alert_handler_lpg_sleep_mode_alerts.856874938
Directory	/workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/36.chip_sw_all_escalation_resets.4127261854
Short name	T1039
Test name
Test status
Simulation time	5047465530 ps
CPU time	564.81 seconds
Started	May 23 04:19:56 PM PDT 24
Finished	May 23 04:29:22 PM PDT 24
Peak memory	610324 kb
Host	smart-1b32f7d4-8a70-4f32-9179-60151540ca11
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4127261854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.4127261854
Directory	/workspace/36.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2678998539
Short name	T672
Test name
Test status
Simulation time	3171270692 ps
CPU time	398.89 seconds
Started	May 23 04:20:30 PM PDT 24
Finished	May 23 04:27:11 PM PDT 24
Peak memory	637284 kb
Host	smart-cbc2c3a3-59c2-4b9c-ba73-9f12b002e75d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678998539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2678998539
Directory	/workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/37.chip_sw_all_escalation_resets.2133365788
Short name	T676
Test name
Test status
Simulation time	5911615068 ps
CPU time	634.05 seconds
Started	May 23 04:20:19 PM PDT 24
Finished	May 23 04:30:55 PM PDT 24
Peak memory	639712 kb
Host	smart-65c74043-db9d-41e8-9389-455304a26470
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2133365788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.2133365788
Directory	/workspace/37.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3579914107
Short name	T1237
Test name
Test status
Simulation time	3702674612 ps
CPU time	322.8 seconds
Started	May 23 04:19:50 PM PDT 24
Finished	May 23 04:25:14 PM PDT 24
Peak memory	609324 kb
Host	smart-e2bdf1cf-1e0f-4f22-9cd7-dcb9e93e5b50
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579914107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3579914107
Directory	/workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/38.chip_sw_all_escalation_resets.88582952
Short name	T690
Test name
Test status
Simulation time	5676174520 ps
CPU time	612.67 seconds
Started	May 23 04:20:19 PM PDT 24
Finished	May 23 04:30:32 PM PDT 24
Peak memory	639568 kb
Host	smart-09ffeb4b-4987-44c2-b3e3-814e51f9ca70
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 88582952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.88582952
Directory	/workspace/38.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/39.chip_sw_all_escalation_resets.746350166
Short name	T87
Test name
Test status
Simulation time	4351562194 ps
CPU time	693.27 seconds
Started	May 23 04:19:37 PM PDT 24
Finished	May 23 04:31:11 PM PDT 24
Peak memory	638536 kb
Host	smart-8be4ae7b-3761-4a34-83b6-9431458f184b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 746350166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.746350166
Directory	/workspace/39.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3312442062
Short name	T284
Test name
Test status
Simulation time	7305738000 ps
CPU time	681.01 seconds
Started	May 23 04:17:26 PM PDT 24
Finished	May 23 04:28:48 PM PDT 24
Peak memory	602148 kb
Host	smart-0812515b-34fc-4786-96a2-f5d52c401e55
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3312442062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3312442062
Directory	/workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1084279346
Short name	T263
Test name
Test status
Simulation time	5360736100 ps
CPU time	501.84 seconds
Started	May 23 04:15:23 PM PDT 24
Finished	May 23 04:23:46 PM PDT 24
Peak memory	603748 kb
Host	smart-e825e8dc-f26e-48a4-a0bc-77ac77178495
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1084279346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.1084279346
Directory	/workspace/4.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1830950541
Short name	T1070
Test name
Test status
Simulation time	4455057700 ps
CPU time	413.67 seconds
Started	May 23 04:16:33 PM PDT 24
Finished	May 23 04:23:27 PM PDT 24
Peak memory	602168 kb
Host	smart-5529fcfe-0f62-4c4d-a9dd-aa93e25b8265
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18309505 41 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.1830950541
Directory	/workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2594087578
Short name	T1064
Test name
Test status
Simulation time	3164193948 ps
CPU time	559.92 seconds
Started	May 23 04:17:32 PM PDT 24
Finished	May 23 04:26:53 PM PDT 24
Peak memory	611368 kb
Host	smart-342f202b-6799-4f38-901a-f9b417e6eef7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2594087578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2594087578
Directory	/workspace/4.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx.4089337965
Short name	T1228
Test name
Test status
Simulation time	4705896920 ps
CPU time	528.25 seconds
Started	May 23 04:16:16 PM PDT 24
Finished	May 23 04:25:06 PM PDT 24
Peak memory	611104 kb
Host	smart-16fb548a-ad1d-4069-8b26-704e39e287eb
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089337965 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.4089337965
Directory	/workspace/4.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1040800056
Short name	T1020
Test name
Test status
Simulation time	4533648382 ps
CPU time	629.37 seconds
Started	May 23 04:21:37 PM PDT 24
Finished	May 23 04:32:07 PM PDT 24
Peak memory	610504 kb
Host	smart-8dd83bff-3908-42d3-8ded-8f2b5919a4a8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040800056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.1040800056
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1652080670
Short name	T945
Test name
Test status
Simulation time	13978021558 ps
CPU time	2209.64 seconds
Started	May 23 04:16:59 PM PDT 24
Finished	May 23 04:53:50 PM PDT 24
Peak memory	611176 kb
Host	smart-e867e8c5-6184-4282-91b7-5d6a051be783
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652080670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1652080670
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2172844012
Short name	T194
Test name
Test status
Simulation time	4351356528 ps
CPU time	585.13 seconds
Started	May 23 04:18:36 PM PDT 24
Finished	May 23 04:28:23 PM PDT 24
Peak memory	608128 kb
Host	smart-e13401fe-0d0e-4b1c-84a0-e32b38111839
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172844012 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.2172844012
Directory	/workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3540331566
Short name	T1135
Test name
Test status
Simulation time	4167870760 ps
CPU time	693.34 seconds
Started	May 23 04:17:03 PM PDT 24
Finished	May 23 04:28:37 PM PDT 24
Peak memory	608112 kb
Host	smart-3891aeec-0876-4a1f-9096-05c9c9610d91
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540331566 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.3540331566
Directory	/workspace/4.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1987922782
Short name	T1222
Test name
Test status
Simulation time	3766326944 ps
CPU time	596.04 seconds
Started	May 23 04:17:33 PM PDT 24
Finished	May 23 04:27:30 PM PDT 24
Peak memory	611088 kb
Host	smart-2c126a16-75c5-4f57-a3da-08eb28e5029d
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987922782 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1987922782
Directory	/workspace/4.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_dev.3777265177
Short name	T939
Test name
Test status
Simulation time	6996852440 ps
CPU time	770.63 seconds
Started	May 23 04:17:38 PM PDT 24
Finished	May 23 04:30:29 PM PDT 24
Peak memory	613220 kb
Host	smart-c5fbe3b6-a0db-4cf9-83a7-b18ebdda4897
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3777265177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3777265177
Directory	/workspace/4.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_prod.4281675152
Short name	T368
Test name
Test status
Simulation time	17937215903 ps
CPU time	1987.45 seconds
Started	May 23 04:16:12 PM PDT 24
Finished	May 23 04:49:20 PM PDT 24
Peak memory	613192 kb
Host	smart-7a855d3d-e7e3-4fd5-bdef-6555f83e8355
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281675152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.4281675152
Directory	/workspace/4.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_testunlock0.3131468164
Short name	T1158
Test name
Test status
Simulation time	7857940911 ps
CPU time	651.23 seconds
Started	May 23 04:16:01 PM PDT 24
Finished	May 23 04:26:54 PM PDT 24
Peak memory	611636 kb
Host	smart-f3b7ff8a-404d-4ef6-a703-f1233fd85588
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131468164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3131468164
Directory	/workspace/4.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1280832131
Short name	T765
Test name
Test status
Simulation time	4552752740 ps
CPU time	555.62 seconds
Started	May 23 04:24:13 PM PDT 24
Finished	May 23 04:33:30 PM PDT 24
Peak memory	638560 kb
Host	smart-66efa283-ee4e-4272-acc5-19b2cfb7749e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1280832131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.1280832131
Directory	/workspace/40.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/41.chip_sw_all_escalation_resets.947087607
Short name	T1114
Test name
Test status
Simulation time	5732535260 ps
CPU time	706.05 seconds
Started	May 23 04:20:06 PM PDT 24
Finished	May 23 04:31:53 PM PDT 24
Peak memory	638864 kb
Host	smart-56ebd8dc-752b-4808-a2f0-618d2679b677
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 947087607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.947087607
Directory	/workspace/41.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/42.chip_sw_all_escalation_resets.77601485
Short name	T673
Test name
Test status
Simulation time	3967704744 ps
CPU time	572.39 seconds
Started	May 23 04:23:09 PM PDT 24
Finished	May 23 04:32:43 PM PDT 24
Peak memory	639384 kb
Host	smart-8cef4376-1a97-466e-a08b-ed02781433fa
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 77601485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.77601485
Directory	/workspace/42.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/43.chip_sw_all_escalation_resets.162259986
Short name	T1097
Test name
Test status
Simulation time	5542367540 ps
CPU time	519.08 seconds
Started	May 23 04:23:25 PM PDT 24
Finished	May 23 04:32:05 PM PDT 24
Peak memory	639556 kb
Host	smart-146c0aa7-639b-4d09-8af4-9c64ad19d534
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 162259986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.162259986
Directory	/workspace/43.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.958632931
Short name	T758
Test name
Test status
Simulation time	3594483406 ps
CPU time	484.82 seconds
Started	May 23 04:20:59 PM PDT 24
Finished	May 23 04:29:04 PM PDT 24
Peak memory	637236 kb
Host	smart-4aab7842-a984-4dd0-8c99-20c0b9b2f53a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958632931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_s w_alert_handler_lpg_sleep_mode_alerts.958632931
Directory	/workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/44.chip_sw_all_escalation_resets.745723469
Short name	T695
Test name
Test status
Simulation time	3769894070 ps
CPU time	475.4 seconds
Started	May 23 04:25:06 PM PDT 24
Finished	May 23 04:33:02 PM PDT 24
Peak memory	638388 kb
Host	smart-2e4e57a4-f1ff-4a6d-b738-3ee026b83f05
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 745723469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.745723469
Directory	/workspace/44.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2804880052
Short name	T741
Test name
Test status
Simulation time	4184231168 ps
CPU time	490.64 seconds
Started	May 23 04:19:38 PM PDT 24
Finished	May 23 04:27:50 PM PDT 24
Peak memory	637432 kb
Host	smart-e40dcbec-6339-4726-9efa-df2a1f5f6176
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804880052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2804880052
Directory	/workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.874235831
Short name	T724
Test name
Test status
Simulation time	3740262092 ps
CPU time	507.92 seconds
Started	May 23 04:21:40 PM PDT 24
Finished	May 23 04:30:10 PM PDT 24
Peak memory	637444 kb
Host	smart-fcafcbcf-41d4-4d15-9b0b-57bb84dc3f03
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874235831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_s w_alert_handler_lpg_sleep_mode_alerts.874235831
Directory	/workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2016607234
Short name	T281
Test name
Test status
Simulation time	5276737418 ps
CPU time	494.96 seconds
Started	May 23 04:20:42 PM PDT 24
Finished	May 23 04:28:58 PM PDT 24
Peak memory	638752 kb
Host	smart-e9646d9d-ffac-4f82-831a-7caff069cc60
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2016607234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2016607234
Directory	/workspace/47.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/48.chip_sw_all_escalation_resets.835652222
Short name	T701
Test name
Test status
Simulation time	5082739696 ps
CPU time	658.75 seconds
Started	May 23 04:20:58 PM PDT 24
Finished	May 23 04:31:58 PM PDT 24
Peak memory	638556 kb
Host	smart-48e4708a-b7f3-4d6e-b18e-cb0b6bdb461d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 835652222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.835652222
Directory	/workspace/48.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238605309
Short name	T1200
Test name
Test status
Simulation time	2927335190 ps
CPU time	417.08 seconds
Started	May 23 04:21:31 PM PDT 24
Finished	May 23 04:28:29 PM PDT 24
Peak memory	609292 kb
Host	smart-fb135e39-5b5f-4bf8-b0c8-1e3fae4ea07b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238605309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2238605309
Directory	/workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/49.chip_sw_all_escalation_resets.29514910
Short name	T689
Test name
Test status
Simulation time	4071182364 ps
CPU time	548.13 seconds
Started	May 23 04:20:41 PM PDT 24
Finished	May 23 04:29:50 PM PDT 24
Peak memory	639296 kb
Host	smart-b85b58fc-3a19-4ddd-9b55-5ad81a5f9b16
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 29514910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.29514910
Directory	/workspace/49.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/5.chip_sw_all_escalation_resets.999084920
Short name	T729
Test name
Test status
Simulation time	5624796210 ps
CPU time	580.87 seconds
Started	May 23 04:19:51 PM PDT 24
Finished	May 23 04:29:34 PM PDT 24
Peak memory	638600 kb
Host	smart-0ba5fd7e-0304-4473-babe-5b62f50b4514
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 999084920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.999084920
Directory	/workspace/5.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.4138604911
Short name	T1196
Test name
Test status
Simulation time	5131063850 ps
CPU time	723.8 seconds
Started	May 23 04:16:37 PM PDT 24
Finished	May 23 04:28:43 PM PDT 24
Peak memory	602376 kb
Host	smart-deeaa7a7-3799-4513-b2b0-4b797fd9f940
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4138604911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.4138604911
Directory	/workspace/5.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1608703328
Short name	T308
Test name
Test status
Simulation time	13243764648 ps
CPU time	2611.93 seconds
Started	May 23 04:17:35 PM PDT 24
Finished	May 23 05:01:09 PM PDT 24
Peak memory	610136 kb
Host	smart-e1c3a79f-2a53-4a15-8292-6a17e8e7054c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1608703328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.1608703328
Directory	/workspace/5.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.416406359
Short name	T764
Test name
Test status
Simulation time	4109026504 ps
CPU time	472.11 seconds
Started	May 23 04:21:07 PM PDT 24
Finished	May 23 04:29:00 PM PDT 24
Peak memory	637496 kb
Host	smart-003b5423-2d75-4dcc-a3b8-121882e50e35
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416406359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_s w_alert_handler_lpg_sleep_mode_alerts.416406359
Directory	/workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1596704138
Short name	T742
Test name
Test status
Simulation time	4317170800 ps
CPU time	603.51 seconds
Started	May 23 04:22:23 PM PDT 24
Finished	May 23 04:32:27 PM PDT 24
Peak memory	638868 kb
Host	smart-6256b3b3-edae-4da0-a4d6-d66b297e47a0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1596704138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.1596704138
Directory	/workspace/50.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1487383882
Short name	T1110
Test name
Test status
Simulation time	3584708228 ps
CPU time	311.84 seconds
Started	May 23 04:19:17 PM PDT 24
Finished	May 23 04:24:29 PM PDT 24
Peak memory	636668 kb
Host	smart-112e1a05-9994-4a9a-8bcc-29ba141c00ec
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487383882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1487383882
Directory	/workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/51.chip_sw_all_escalation_resets.61150651
Short name	T700
Test name
Test status
Simulation time	5510355050 ps
CPU time	772.53 seconds
Started	May 23 04:21:54 PM PDT 24
Finished	May 23 04:34:48 PM PDT 24
Peak memory	638532 kb
Host	smart-65219f48-f728-4db9-9de7-4ab6cc427074
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 61150651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.61150651
Directory	/workspace/51.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.4283496693
Short name	T716
Test name
Test status
Simulation time	3775999240 ps
CPU time	571.03 seconds
Started	May 23 04:21:19 PM PDT 24
Finished	May 23 04:30:51 PM PDT 24
Peak memory	637488 kb
Host	smart-7d8cd9e0-5a96-4e93-90e2-a2d8e72b15d5
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283496693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4283496693
Directory	/workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3617769657
Short name	T1148
Test name
Test status
Simulation time	4044889670 ps
CPU time	434.83 seconds
Started	May 23 04:23:30 PM PDT 24
Finished	May 23 04:30:46 PM PDT 24
Peak memory	636764 kb
Host	smart-f99807a0-7e12-4c6c-bd62-3e2367ce2b66
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617769657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3617769657
Directory	/workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1477593871
Short name	T684
Test name
Test status
Simulation time	3522191288 ps
CPU time	472.14 seconds
Started	May 23 04:20:47 PM PDT 24
Finished	May 23 04:28:40 PM PDT 24
Peak memory	637328 kb
Host	smart-6806a103-fc0f-4543-8de1-e53edec160f3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477593871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1477593871
Directory	/workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.4270117989
Short name	T725
Test name
Test status
Simulation time	3870258028 ps
CPU time	399.06 seconds
Started	May 23 04:21:32 PM PDT 24
Finished	May 23 04:28:12 PM PDT 24
Peak memory	637164 kb
Host	smart-09e3728a-c662-4732-addd-f16eab0a04a8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270117989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4270117989
Directory	/workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503069383
Short name	T965
Test name
Test status
Simulation time	3645020140 ps
CPU time	351.23 seconds
Started	May 23 04:19:54 PM PDT 24
Finished	May 23 04:25:47 PM PDT 24
Peak memory	636828 kb
Host	smart-92c73214-6b84-4541-9171-fac4a3e9e9fd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503069383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1503069383
Directory	/workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/58.chip_sw_all_escalation_resets.813856760
Short name	T708
Test name
Test status
Simulation time	4259126792 ps
CPU time	573.52 seconds
Started	May 23 04:21:28 PM PDT 24
Finished	May 23 04:31:02 PM PDT 24
Peak memory	639780 kb
Host	smart-8f448af1-2b17-4c22-acd0-62b24cd7ad14
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 813856760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.813856760
Directory	/workspace/58.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1612837747
Short name	T691
Test name
Test status
Simulation time	4781549480 ps
CPU time	607.85 seconds
Started	May 23 04:20:19 PM PDT 24
Finished	May 23 04:30:28 PM PDT 24
Peak memory	638556 kb
Host	smart-88026216-1809-4da9-8a5c-b24465186e87
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1612837747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.1612837747
Directory	/workspace/59.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.624642003
Short name	T104
Test name
Test status
Simulation time	3858108100 ps
CPU time	379.63 seconds
Started	May 23 04:22:18 PM PDT 24
Finished	May 23 04:28:39 PM PDT 24
Peak memory	637704 kb
Host	smart-5c0281bd-5cc2-44af-bb1c-8fc69a211335
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624642003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.624642003
Directory	/workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3532989608
Short name	T1201
Test name
Test status
Simulation time	13872711816 ps
CPU time	2569.36 seconds
Started	May 23 04:17:25 PM PDT 24
Finished	May 23 05:00:15 PM PDT 24
Peak memory	610176 kb
Host	smart-98c0bdde-ada0-45c4-b32b-78a59ab29d65
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3532989608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.3532989608
Directory	/workspace/6.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077296702
Short name	T740
Test name
Test status
Simulation time	3865649800 ps
CPU time	380.95 seconds
Started	May 23 04:24:10 PM PDT 24
Finished	May 23 04:30:32 PM PDT 24
Peak memory	636576 kb
Host	smart-7390996b-3287-46ae-bfa2-d0213e8f2b71
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077296702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4077296702
Directory	/workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4163853922
Short name	T735
Test name
Test status
Simulation time	4033796350 ps
CPU time	445.16 seconds
Started	May 23 04:21:58 PM PDT 24
Finished	May 23 04:29:24 PM PDT 24
Peak memory	636588 kb
Host	smart-cade15ed-595a-4135-8842-f7b2240e9c32
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163853922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4163853922
Directory	/workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/61.chip_sw_all_escalation_resets.375000730
Short name	T720
Test name
Test status
Simulation time	5821543250 ps
CPU time	476.59 seconds
Started	May 23 04:22:26 PM PDT 24
Finished	May 23 04:30:23 PM PDT 24
Peak memory	638816 kb
Host	smart-180e3c11-6580-4f9e-b9f9-9d1939a955cd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 375000730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.375000730
Directory	/workspace/61.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2622909359
Short name	T769
Test name
Test status
Simulation time	3831003636 ps
CPU time	408.97 seconds
Started	May 23 04:22:26 PM PDT 24
Finished	May 23 04:29:16 PM PDT 24
Peak memory	637160 kb
Host	smart-be45426c-689e-4a95-b704-0ced6895d5c4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622909359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2622909359
Directory	/workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/62.chip_sw_all_escalation_resets.2496957176
Short name	T204
Test name
Test status
Simulation time	4551817880 ps
CPU time	769.66 seconds
Started	May 23 04:24:44 PM PDT 24
Finished	May 23 04:37:35 PM PDT 24
Peak memory	640184 kb
Host	smart-b149d6ea-2eb5-4564-bd13-4e101cc2c890
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2496957176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.2496957176
Directory	/workspace/62.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.331216144
Short name	T123
Test name
Test status
Simulation time	3406515522 ps
CPU time	468.47 seconds
Started	May 23 04:22:58 PM PDT 24
Finished	May 23 04:30:48 PM PDT 24
Peak memory	637304 kb
Host	smart-6fe6ad03-c3a0-40f4-b4f8-a2222bb67b19
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331216144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s w_alert_handler_lpg_sleep_mode_alerts.331216144
Directory	/workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3959886633
Short name	T749
Test name
Test status
Simulation time	3770858308 ps
CPU time	478.3 seconds
Started	May 23 04:23:45 PM PDT 24
Finished	May 23 04:31:45 PM PDT 24
Peak memory	637508 kb
Host	smart-419475a1-d9f4-4e81-8ed9-a187a66f2c63
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959886633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3959886633
Directory	/workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/64.chip_sw_all_escalation_resets.1777248560
Short name	T643
Test name
Test status
Simulation time	4440858008 ps
CPU time	588.96 seconds
Started	May 23 04:20:57 PM PDT 24
Finished	May 23 04:30:47 PM PDT 24
Peak memory	603616 kb
Host	smart-1b1d1af6-4504-4274-b8aa-e8fcdc3d28ea
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1777248560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.1777248560
Directory	/workspace/64.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2980296865
Short name	T117
Test name
Test status
Simulation time	3736682526 ps
CPU time	414.41 seconds
Started	May 23 04:21:46 PM PDT 24
Finished	May 23 04:28:41 PM PDT 24
Peak memory	637348 kb
Host	smart-283dc176-3b1d-40c5-87b5-ed9ca93b4c85
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980296865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2980296865
Directory	/workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/65.chip_sw_all_escalation_resets.548635323
Short name	T717
Test name
Test status
Simulation time	4943271732 ps
CPU time	729.98 seconds
Started	May 23 04:25:33 PM PDT 24
Finished	May 23 04:37:44 PM PDT 24
Peak memory	638584 kb
Host	smart-1d720cbd-8eb7-4e47-aac3-2a48297a291b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 548635323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.548635323
Directory	/workspace/65.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.676831956
Short name	T721
Test name
Test status
Simulation time	4035517408 ps
CPU time	494.02 seconds
Started	May 23 04:22:14 PM PDT 24
Finished	May 23 04:30:29 PM PDT 24
Peak memory	636180 kb
Host	smart-9f3c9271-55b7-4308-bb1c-08c9f5e67a6e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676831956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_s w_alert_handler_lpg_sleep_mode_alerts.676831956
Directory	/workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/67.chip_sw_all_escalation_resets.3153509091
Short name	T75
Test name
Test status
Simulation time	5900061482 ps
CPU time	650.67 seconds
Started	May 23 04:21:53 PM PDT 24
Finished	May 23 04:32:44 PM PDT 24
Peak memory	638628 kb
Host	smart-5d65b5c5-770a-43ee-8042-37742340e237
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3153509091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.3153509091
Directory	/workspace/67.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.894910953
Short name	T699
Test name
Test status
Simulation time	3307391950 ps
CPU time	346.84 seconds
Started	May 23 04:21:39 PM PDT 24
Finished	May 23 04:27:28 PM PDT 24
Peak memory	636492 kb
Host	smart-5e8a4f6c-231e-4bab-968a-f6f07917247e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894910953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_s w_alert_handler_lpg_sleep_mode_alerts.894910953
Directory	/workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1300968896
Short name	T753
Test name
Test status
Simulation time	4799453230 ps
CPU time	646.36 seconds
Started	May 23 04:20:42 PM PDT 24
Finished	May 23 04:31:29 PM PDT 24
Peak memory	639704 kb
Host	smart-d1a881c9-8d1a-4dd1-86a8-8a281265e7bd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1300968896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.1300968896
Directory	/workspace/68.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303802127
Short name	T693
Test name
Test status
Simulation time	3578297020 ps
CPU time	359.94 seconds
Started	May 23 04:23:24 PM PDT 24
Finished	May 23 04:29:25 PM PDT 24
Peak memory	637380 kb
Host	smart-6f508fb4-ceaa-4df0-9b38-c822b1fb1f13
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303802127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2303802127
Directory	/workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3586184586
Short name	T1063
Test name
Test status
Simulation time	4413008900 ps
CPU time	614.73 seconds
Started	May 23 04:24:09 PM PDT 24
Finished	May 23 04:34:24 PM PDT 24
Peak memory	639796 kb
Host	smart-fc873668-b6a6-4d37-8c97-fc18efbb2d43
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3586184586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3586184586
Directory	/workspace/69.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1695501427
Short name	T730
Test name
Test status
Simulation time	4124088460 ps
CPU time	439.28 seconds
Started	May 23 04:22:17 PM PDT 24
Finished	May 23 04:29:38 PM PDT 24
Peak memory	637212 kb
Host	smart-ad2364e0-1316-4fe6-9c3d-10b3c94c3e78
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695501427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.1695501427
Directory	/workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3774786763
Short name	T292
Test name
Test status
Simulation time	8097495350 ps
CPU time	1306.22 seconds
Started	May 23 04:21:37 PM PDT 24
Finished	May 23 04:43:24 PM PDT 24
Peak memory	611180 kb
Host	smart-169e675f-1f6a-47b2-a328-4b1fec57cd6f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3774786763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3774786763
Directory	/workspace/7.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3019226180
Short name	T1210
Test name
Test status
Simulation time	4192292036 ps
CPU time	364.7 seconds
Started	May 23 04:24:07 PM PDT 24
Finished	May 23 04:30:12 PM PDT 24
Peak memory	637500 kb
Host	smart-cee217dc-25b8-4c45-9ea6-8dc1c6a8d17b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019226180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3019226180
Directory	/workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1512605558
Short name	T268
Test name
Test status
Simulation time	4285592364 ps
CPU time	449.56 seconds
Started	May 23 04:21:16 PM PDT 24
Finished	May 23 04:28:47 PM PDT 24
Peak memory	637468 kb
Host	smart-da01f5d5-1737-414c-9d90-48b04b17f4cf
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512605558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1512605558
Directory	/workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/71.chip_sw_all_escalation_resets.1007041117
Short name	T686
Test name
Test status
Simulation time	4472521240 ps
CPU time	705.31 seconds
Started	May 23 04:21:43 PM PDT 24
Finished	May 23 04:33:30 PM PDT 24
Peak memory	639868 kb
Host	smart-09679395-084d-4841-9e61-e2de3fb2b166
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1007041117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.1007041117
Directory	/workspace/71.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2186178903
Short name	T754
Test name
Test status
Simulation time	3288637792 ps
CPU time	391.66 seconds
Started	May 23 04:24:36 PM PDT 24
Finished	May 23 04:31:08 PM PDT 24
Peak memory	637548 kb
Host	smart-1d0a6837-8f58-4e92-8bff-55979d38fe18
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186178903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2186178903
Directory	/workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/72.chip_sw_all_escalation_resets.1609842386
Short name	T1111
Test name
Test status
Simulation time	6074244568 ps
CPU time	683.91 seconds
Started	May 23 04:23:47 PM PDT 24
Finished	May 23 04:35:12 PM PDT 24
Peak memory	639536 kb
Host	smart-ba613ab2-3291-4bdf-be41-4676f8955ed1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1609842386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.1609842386
Directory	/workspace/72.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2641865504
Short name	T105
Test name
Test status
Simulation time	3623398192 ps
CPU time	361.62 seconds
Started	May 23 04:22:51 PM PDT 24
Finished	May 23 04:28:54 PM PDT 24
Peak memory	637548 kb
Host	smart-9a8f81e1-d7bb-4cf3-9eed-0a97761db61d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641865504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2641865504
Directory	/workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/73.chip_sw_all_escalation_resets.4050158501
Short name	T1217
Test name
Test status
Simulation time	6293710218 ps
CPU time	643.27 seconds
Started	May 23 04:22:11 PM PDT 24
Finished	May 23 04:32:55 PM PDT 24
Peak memory	638876 kb
Host	smart-342956bb-8842-4ce7-8532-7f554e010960
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4050158501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.4050158501
Directory	/workspace/73.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4258294752
Short name	T732
Test name
Test status
Simulation time	3897348200 ps
CPU time	372.82 seconds
Started	May 23 04:22:19 PM PDT 24
Finished	May 23 04:28:33 PM PDT 24
Peak memory	637208 kb
Host	smart-54dbfe70-1352-4743-b7d2-2d6ddd5fedd3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258294752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4258294752
Directory	/workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626775279
Short name	T704
Test name
Test status
Simulation time	3869077628 ps
CPU time	442.75 seconds
Started	May 23 04:21:54 PM PDT 24
Finished	May 23 04:29:18 PM PDT 24
Peak memory	636476 kb
Host	smart-a7956f8f-43ab-4711-98e7-12c841f6699b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626775279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3626775279
Directory	/workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4018407714
Short name	T347
Test name
Test status
Simulation time	3247713690 ps
CPU time	427.25 seconds
Started	May 23 04:22:41 PM PDT 24
Finished	May 23 04:29:49 PM PDT 24
Peak memory	637440 kb
Host	smart-275fa6d5-1ef4-472c-82f2-51c2d4ece097
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018407714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4018407714
Directory	/workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/76.chip_sw_all_escalation_resets.1402218052
Short name	T715
Test name
Test status
Simulation time	5200940858 ps
CPU time	630.93 seconds
Started	May 23 04:21:37 PM PDT 24
Finished	May 23 04:32:09 PM PDT 24
Peak memory	637712 kb
Host	smart-9ac51699-2d80-4a0c-bfb2-93e5868b4398
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1402218052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1402218052
Directory	/workspace/76.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.793505807
Short name	T278
Test name
Test status
Simulation time	3853161226 ps
CPU time	339.53 seconds
Started	May 23 04:21:33 PM PDT 24
Finished	May 23 04:27:13 PM PDT 24
Peak memory	637532 kb
Host	smart-c2c233cb-2805-48d3-8733-42be4ccf353f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793505807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_s w_alert_handler_lpg_sleep_mode_alerts.793505807
Directory	/workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/77.chip_sw_all_escalation_resets.2948541834
Short name	T391
Test name
Test status
Simulation time	5112163088 ps
CPU time	575.29 seconds
Started	May 23 04:21:58 PM PDT 24
Finished	May 23 04:31:35 PM PDT 24
Peak memory	638824 kb
Host	smart-67b28cfb-3711-419a-8368-1010c0c97886
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2948541834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.2948541834
Directory	/workspace/77.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626547579
Short name	T111
Test name
Test status
Simulation time	3904317142 ps
CPU time	494.41 seconds
Started	May 23 04:22:55 PM PDT 24
Finished	May 23 04:31:11 PM PDT 24
Peak memory	637560 kb
Host	smart-e259991d-8894-48eb-9d07-6286c82019cd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626547579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2626547579
Directory	/workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2959182226
Short name	T737
Test name
Test status
Simulation time	3570675578 ps
CPU time	380.41 seconds
Started	May 23 04:21:35 PM PDT 24
Finished	May 23 04:27:56 PM PDT 24
Peak memory	637436 kb
Host	smart-b5b6b0f9-70d1-4a7a-a881-58d019b73165
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959182226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2959182226
Directory	/workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3242561626
Short name	T759
Test name
Test status
Simulation time	5501484900 ps
CPU time	677.98 seconds
Started	May 23 04:25:19 PM PDT 24
Finished	May 23 04:36:39 PM PDT 24
Peak memory	638932 kb
Host	smart-1b6c554e-5e74-4037-9e28-951ad4571594
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3242561626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3242561626
Directory	/workspace/79.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3798660613
Short name	T334
Test name
Test status
Simulation time	5379585192 ps
CPU time	761.09 seconds
Started	May 23 04:17:42 PM PDT 24
Finished	May 23 04:30:24 PM PDT 24
Peak memory	638612 kb
Host	smart-38acdbe8-35a9-4faa-b2d8-36e76adfaf85
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3798660613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3798660613
Directory	/workspace/8.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2367684397
Short name	T941
Test name
Test status
Simulation time	3863067210 ps
CPU time	474.64 seconds
Started	May 23 04:21:06 PM PDT 24
Finished	May 23 04:29:01 PM PDT 24
Peak memory	611416 kb
Host	smart-841b05c8-ecfc-400a-b1ed-3c2eb55ecfa5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2367684397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2367684397
Directory	/workspace/8.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3773929248
Short name	T761
Test name
Test status
Simulation time	3783463160 ps
CPU time	332.62 seconds
Started	May 23 04:22:24 PM PDT 24
Finished	May 23 04:27:58 PM PDT 24
Peak memory	637648 kb
Host	smart-5086d2e6-a4ab-4ae5-adf2-d920fe29c43b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773929248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3773929248
Directory	/workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/80.chip_sw_all_escalation_resets.1405036519
Short name	T239
Test name
Test status
Simulation time	5678349204 ps
CPU time	637.48 seconds
Started	May 23 04:24:44 PM PDT 24
Finished	May 23 04:35:23 PM PDT 24
Peak memory	638988 kb
Host	smart-2e3c7435-30bc-4c83-a182-228f87da69a1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1405036519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1405036519
Directory	/workspace/80.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1663121566
Short name	T280
Test name
Test status
Simulation time	3819831442 ps
CPU time	321.07 seconds
Started	May 23 04:22:02 PM PDT 24
Finished	May 23 04:27:24 PM PDT 24
Peak memory	636692 kb
Host	smart-ce167fea-fd3a-4592-9e78-dc11c1df9877
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663121566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1663121566
Directory	/workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/81.chip_sw_all_escalation_resets.902570413
Short name	T770
Test name
Test status
Simulation time	5602293192 ps
CPU time	746.05 seconds
Started	May 23 04:22:51 PM PDT 24
Finished	May 23 04:35:19 PM PDT 24
Peak memory	638748 kb
Host	smart-d4de65ce-8e22-4a07-bbaa-7360305d2322
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 902570413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.902570413
Directory	/workspace/81.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3646290389
Short name	T1174
Test name
Test status
Simulation time	3828638240 ps
CPU time	393.44 seconds
Started	May 23 04:26:57 PM PDT 24
Finished	May 23 04:33:31 PM PDT 24
Peak memory	637472 kb
Host	smart-9cae7da1-27a9-4bb2-ba7c-966b433a827c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646290389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3646290389
Directory	/workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/84.chip_sw_all_escalation_resets.3181781257
Short name	T678
Test name
Test status
Simulation time	5555664248 ps
CPU time	620.82 seconds
Started	May 23 04:22:25 PM PDT 24
Finished	May 23 04:32:47 PM PDT 24
Peak memory	638832 kb
Host	smart-3349d6d4-0ba0-420d-b627-e15c7ce44eef
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3181781257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3181781257
Directory	/workspace/84.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.860094906
Short name	T112
Test name
Test status
Simulation time	3744770392 ps
CPU time	438.74 seconds
Started	May 23 04:25:07 PM PDT 24
Finished	May 23 04:32:26 PM PDT 24
Peak memory	638024 kb
Host	smart-e7cfcdb8-3655-4704-9614-ada5fcca2c75
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860094906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_s w_alert_handler_lpg_sleep_mode_alerts.860094906
Directory	/workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/85.chip_sw_all_escalation_resets.807356901
Short name	T713
Test name
Test status
Simulation time	5136097720 ps
CPU time	777.69 seconds
Started	May 23 04:22:30 PM PDT 24
Finished	May 23 04:35:29 PM PDT 24
Peak memory	639024 kb
Host	smart-482a4884-561c-4d2a-add5-51ff91766a99
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 807356901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.807356901
Directory	/workspace/85.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.84507021
Short name	T1220
Test name
Test status
Simulation time	3354504562 ps
CPU time	391.52 seconds
Started	May 23 04:25:38 PM PDT 24
Finished	May 23 04:32:11 PM PDT 24
Peak memory	637280 kb
Host	smart-17e541c0-938e-484f-88a5-ecc718f4c4aa
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84507021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw _alert_handler_lpg_sleep_mode_alerts.84507021
Directory	/workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3255637349
Short name	T1068
Test name
Test status
Simulation time	5318256656 ps
CPU time	604.49 seconds
Started	May 23 04:21:45 PM PDT 24
Finished	May 23 04:31:50 PM PDT 24
Peak memory	610356 kb
Host	smart-820163f2-73ec-44aa-90b6-709ac1dae833
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3255637349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3255637349
Directory	/workspace/86.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3392890192
Short name	T118
Test name
Test status
Simulation time	3609328360 ps
CPU time	324.33 seconds
Started	May 23 04:25:09 PM PDT 24
Finished	May 23 04:30:34 PM PDT 24
Peak memory	637252 kb
Host	smart-38d96c7e-c145-459b-a301-b19070bee4aa
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392890192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3392890192
Directory	/workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/87.chip_sw_all_escalation_resets.564557584
Short name	T719
Test name
Test status
Simulation time	6044616314 ps
CPU time	782.24 seconds
Started	May 23 04:21:13 PM PDT 24
Finished	May 23 04:34:16 PM PDT 24
Peak memory	639592 kb
Host	smart-8bb67787-e993-42d5-b725-65f0e42a6d13
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 564557584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.564557584
Directory	/workspace/87.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3276336701
Short name	T752
Test name
Test status
Simulation time	3532886920 ps
CPU time	398.88 seconds
Started	May 23 04:21:45 PM PDT 24
Finished	May 23 04:28:25 PM PDT 24
Peak memory	637492 kb
Host	smart-817a46ed-cf30-4fa7-b218-1b336c15f01a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276336701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3276336701
Directory	/workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3129949206
Short name	T751
Test name
Test status
Simulation time	5322334082 ps
CPU time	630.55 seconds
Started	May 23 04:22:23 PM PDT 24
Finished	May 23 04:32:55 PM PDT 24
Peak memory	638660 kb
Host	smart-90df4e61-aa49-4410-a77f-6a3ea2352e0a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3129949206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.3129949206
Directory	/workspace/88.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3140326182
Short name	T747
Test name
Test status
Simulation time	3302783304 ps
CPU time	339.7 seconds
Started	May 23 04:22:14 PM PDT 24
Finished	May 23 04:27:55 PM PDT 24
Peak memory	636764 kb
Host	smart-a3b5a73b-8af5-4f69-a48f-05e527c5e93d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140326182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3140326182
Directory	/workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/89.chip_sw_all_escalation_resets.3783768321
Short name	T1005
Test name
Test status
Simulation time	4519196682 ps
CPU time	623.19 seconds
Started	May 23 04:25:54 PM PDT 24
Finished	May 23 04:36:18 PM PDT 24
Peak memory	638688 kb
Host	smart-2533bdac-0d83-44fe-95dc-4d58c222b166
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3783768321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.3783768321
Directory	/workspace/89.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/9.chip_sw_all_escalation_resets.3641231876
Short name	T243
Test name
Test status
Simulation time	5715081086 ps
CPU time	529.23 seconds
Started	May 23 04:18:29 PM PDT 24
Finished	May 23 04:27:20 PM PDT 24
Peak memory	639764 kb
Host	smart-b4c8ed83-b937-4bbe-8a1a-fe5945f16a24
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3641231876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.3641231876
Directory	/workspace/9.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2361851693
Short name	T908
Test name
Test status
Simulation time	3824801300 ps
CPU time	766.24 seconds
Started	May 23 04:18:07 PM PDT 24
Finished	May 23 04:30:54 PM PDT 24
Peak memory	610140 kb
Host	smart-3351e266-b27b-4a72-a82f-5244d65f6f28
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2361851693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.2361851693
Directory	/workspace/9.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3765242324
Short name	T79
Test name
Test status
Simulation time	4097941452 ps
CPU time	605.03 seconds
Started	May 23 04:22:44 PM PDT 24
Finished	May 23 04:32:50 PM PDT 24
Peak memory	610260 kb
Host	smart-2a2d6e7d-83ac-461e-aa42-36647e6d5ac3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3765242324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3765242324
Directory	/workspace/90.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1720519331
Short name	T492
Test name
Test status
Simulation time	4972898004 ps
CPU time	587.8 seconds
Started	May 23 04:25:44 PM PDT 24
Finished	May 23 04:35:33 PM PDT 24
Peak memory	638528 kb
Host	smart-239cf7ee-7909-4d34-85aa-c10de2fd88f7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1720519331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.1720519331
Directory	/workspace/91.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2803751018
Short name	T702
Test name
Test status
Simulation time	5836214076 ps
CPU time	493.46 seconds
Started	May 23 04:22:23 PM PDT 24
Finished	May 23 04:30:38 PM PDT 24
Peak memory	639592 kb
Host	smart-57e81c92-6b17-45af-93c9-e79d07f7eeed
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2803751018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.2803751018
Directory	/workspace/93.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/94.chip_sw_all_escalation_resets.1075950154
Short name	T706
Test name
Test status
Simulation time	6288025780 ps
CPU time	689.73 seconds
Started	May 23 04:25:17 PM PDT 24
Finished	May 23 04:36:47 PM PDT 24
Peak memory	638924 kb
Host	smart-f3bec2bf-fcd7-4dec-bce8-7dd7cc9a6097
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1075950154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1075950154
Directory	/workspace/94.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/96.chip_sw_all_escalation_resets.1407551357
Short name	T669
Test name
Test status
Simulation time	5971009560 ps
CPU time	769.11 seconds
Started	May 23 04:22:15 PM PDT 24
Finished	May 23 04:35:05 PM PDT 24
Peak memory	638780 kb
Host	smart-c0783a83-a1dd-4c22-9fa1-c6dbd8716934
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1407551357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1407551357
Directory	/workspace/96.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3569808005
Short name	T762
Test name
Test status
Simulation time	5026585816 ps
CPU time	577.4 seconds
Started	May 23 04:22:35 PM PDT 24
Finished	May 23 04:32:14 PM PDT 24
Peak memory	639756 kb
Host	smart-84bb9004-e9f7-4739-a661-c8c576374ce4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3569808005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3569808005
Directory	/workspace/97.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/98.chip_sw_all_escalation_resets.720291515
Short name	T110
Test name
Test status
Simulation time	4815529624 ps
CPU time	629.95 seconds
Started	May 23 04:25:22 PM PDT 24
Finished	May 23 04:35:53 PM PDT 24
Peak memory	639260 kb
Host	smart-ab4b56eb-c8c6-47c3-8bd4-f9eea63990e4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 720291515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.720291515
Directory	/workspace/98.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/99.chip_sw_all_escalation_resets.275222906
Short name	T768
Test name
Test status
Simulation time	4518117592 ps
CPU time	656.7 seconds
Started	May 23 04:24:28 PM PDT 24
Finished	May 23 04:35:26 PM PDT 24
Peak memory	639588 kb
Host	smart-f07366fe-eab2-4ec0-8642-377757f7f6c8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 275222906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.275222906
Directory	/workspace/99.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3219509846
Short name	T2797
Test name
Test status
Simulation time	5519822164 ps
CPU time	260.48 seconds
Started	May 23 04:40:42 PM PDT 24
Finished	May 23 04:45:03 PM PDT 24
Peak memory	638644 kb
Host	smart-33a2ce5f-20f3-4522-b73f-deb22382b425
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219509846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.3219509846
Directory	/workspace/0.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3529844471
Short name	T189
Test name
Test status
Simulation time	5146819965 ps
CPU time	259.94 seconds
Started	May 23 04:40:41 PM PDT 24
Finished	May 23 04:45:01 PM PDT 24
Peak memory	638724 kb
Host	smart-06ac40c6-6ec1-430e-8004-ae0eb7c8c66d
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529844471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.3529844471
Directory	/workspace/2.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2419360816
Short name	T31
Test name
Test status
Simulation time	4074999610 ps
CPU time	264.25 seconds
Started	May 23 04:40:35 PM PDT 24
Finished	May 23 04:45:01 PM PDT 24
Peak memory	655096 kb
Host	smart-df186db6-596f-4243-a884-6005dbdc84f7
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419360816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.2419360816
Directory	/workspace/3.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4147739081
Short name	T195
Test name
Test status
Simulation time	4404230390 ps
CPU time	205.11 seconds
Started	May 23 04:40:42 PM PDT 24
Finished	May 23 04:44:08 PM PDT 24
Peak memory	637768 kb
Host	smart-b2122c4e-907e-49a6-916a-186a4e974463
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147739081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.4147739081
Directory	/workspace/4.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2606616335
Short name	T2800
Test name
Test status
Simulation time	5691365858 ps
CPU time	272.36 seconds
Started	May 23 04:40:35 PM PDT 24
Finished	May 23 04:45:09 PM PDT 24
Peak memory	638600 kb
Host	smart-b2c1f043-acde-47a5-968a-ea79418f20da
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606616335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.2606616335
Directory	/workspace/5.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1597389820
Short name	T2799
Test name
Test status
Simulation time	4564350064 ps
CPU time	189.34 seconds
Started	May 23 04:40:35 PM PDT 24
Finished	May 23 04:43:46 PM PDT 24
Peak memory	638712 kb
Host	smart-274eefd5-a8fc-45b9-8d11-b6e1176410fc
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597389820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.1597389820
Directory	/workspace/6.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2689315356
Short name	T30
Test name
Test status
Simulation time	5777940747 ps
CPU time	309.56 seconds
Started	May 23 04:40:37 PM PDT 24
Finished	May 23 04:45:47 PM PDT 24
Peak memory	654948 kb
Host	smart-be58d135-b238-4864-b1a3-4f10106f8bac
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689315356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2689315356
Directory	/workspace/8.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1552525248
Short name	T2801
Test name
Test status
Simulation time	4846133745 ps
CPU time	209.49 seconds
Started	May 23 04:40:34 PM PDT 24
Finished	May 23 04:44:04 PM PDT 24
Peak memory	638704 kb
Host	smart-4730ebf5-120e-4e1e-a12b-2b5797590725
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552525248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.1552525248
Directory	/workspace/9.chip_padctrl_attributes/latest