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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.37 95.32 93.65 91.81 94.46 97.38 99.58


Total test records in report: 2801
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T671 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.131105338 May 23 04:25:03 PM PDT 24 May 23 04:31:58 PM PDT 24 3613275116 ps
T370 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2293182314 May 23 04:04:13 PM PDT 24 May 23 04:08:04 PM PDT 24 2659523814 ps
T984 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1569089979 May 23 04:07:35 PM PDT 24 May 23 04:19:45 PM PDT 24 4141437876 ps
T716 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.4283496693 May 23 04:21:19 PM PDT 24 May 23 04:30:51 PM PDT 24 3775999240 ps
T985 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2335657089 May 23 04:03:42 PM PDT 24 May 23 04:10:50 PM PDT 24 3018018968 ps
T169 /workspace/coverage/default/0.chip_jtag_csr_rw.2378952968 May 23 03:48:17 PM PDT 24 May 23 03:52:02 PM PDT 24 4182865364 ps
T986 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1590046401 May 23 04:12:47 PM PDT 24 May 23 04:21:42 PM PDT 24 4735380560 ps
T987 /workspace/coverage/default/1.rom_e2e_asm_init_rma.247755479 May 23 04:03:06 PM PDT 24 May 23 04:52:19 PM PDT 24 13731040664 ps
T988 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3475509014 May 23 04:07:50 PM PDT 24 May 23 04:31:13 PM PDT 24 9401608736 ps
T239 /workspace/coverage/default/80.chip_sw_all_escalation_resets.1405036519 May 23 04:24:44 PM PDT 24 May 23 04:35:23 PM PDT 24 5678349204 ps
T679 /workspace/coverage/default/55.chip_sw_all_escalation_resets.70506814 May 23 04:21:44 PM PDT 24 May 23 04:31:44 PM PDT 24 5650203824 ps
T989 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.636875943 May 23 04:08:14 PM PDT 24 May 23 04:58:43 PM PDT 24 10941363989 ps
T990 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2688971316 May 23 03:59:22 PM PDT 24 May 23 04:09:50 PM PDT 24 4970372268 ps
T991 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.22704047 May 23 04:00:46 PM PDT 24 May 23 04:55:41 PM PDT 24 35705687846 ps
T698 /workspace/coverage/default/22.chip_sw_all_escalation_resets.4245349686 May 23 04:19:25 PM PDT 24 May 23 04:31:25 PM PDT 24 5994554680 ps
T992 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4223056990 May 23 04:01:02 PM PDT 24 May 23 05:21:27 PM PDT 24 19651243520 ps
T673 /workspace/coverage/default/42.chip_sw_all_escalation_resets.77601485 May 23 04:23:09 PM PDT 24 May 23 04:32:43 PM PDT 24 3967704744 ps
T993 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3829487294 May 23 04:02:52 PM PDT 24 May 23 07:24:59 PM PDT 24 254995239880 ps
T994 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.248273070 May 23 03:59:27 PM PDT 24 May 23 04:10:03 PM PDT 24 4154467196 ps
T995 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1471848752 May 23 04:03:16 PM PDT 24 May 23 04:51:18 PM PDT 24 14379601660 ps
T304 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1431335984 May 23 04:02:01 PM PDT 24 May 23 04:13:28 PM PDT 24 4836456292 ps
T996 /workspace/coverage/default/2.rom_e2e_asm_init_rma.965668273 May 23 04:19:38 PM PDT 24 May 23 05:17:27 PM PDT 24 14052318236 ps
T997 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.437605257 May 23 04:04:50 PM PDT 24 May 23 05:33:06 PM PDT 24 21558950440 ps
T998 /workspace/coverage/default/0.chip_sw_usbdev_vbus.1932576586 May 23 03:58:10 PM PDT 24 May 23 04:02:14 PM PDT 24 2538865834 ps
T665 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.457088029 May 23 04:04:52 PM PDT 24 May 23 04:34:31 PM PDT 24 22073709808 ps
T999 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3084364020 May 23 04:07:24 PM PDT 24 May 23 05:16:35 PM PDT 24 14388810071 ps
T1000 /workspace/coverage/default/1.chip_sw_csrng_smoketest.3093014153 May 23 04:05:29 PM PDT 24 May 23 04:08:19 PM PDT 24 2728987290 ps
T1001 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1963728993 May 23 04:05:23 PM PDT 24 May 23 05:47:41 PM PDT 24 22181938184 ps
T356 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1135345746 May 23 04:18:06 PM PDT 24 May 23 04:21:05 PM PDT 24 2623963260 ps
T738 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3509906873 May 23 04:25:20 PM PDT 24 May 23 04:37:29 PM PDT 24 5675372590 ps
T309 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.85636251 May 23 03:59:27 PM PDT 24 May 23 04:13:06 PM PDT 24 5642340520 ps
T1002 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2832624389 May 23 04:12:41 PM PDT 24 May 23 04:23:18 PM PDT 24 3973265644 ps
T1003 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1184390219 May 23 04:00:28 PM PDT 24 May 23 04:04:58 PM PDT 24 2545567686 ps
T1004 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2188606845 May 23 04:14:42 PM PDT 24 May 23 04:19:08 PM PDT 24 3151539880 ps
T1005 /workspace/coverage/default/89.chip_sw_all_escalation_resets.3783768321 May 23 04:25:54 PM PDT 24 May 23 04:36:18 PM PDT 24 4519196682 ps
T1006 /workspace/coverage/default/0.chip_sw_uart_smoketest.2619287010 May 23 04:08:07 PM PDT 24 May 23 04:12:08 PM PDT 24 3092207948 ps
T329 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1911336421 May 23 04:14:46 PM PDT 24 May 23 04:19:45 PM PDT 24 2581141888 ps
T721 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.676831956 May 23 04:22:14 PM PDT 24 May 23 04:30:29 PM PDT 24 4035517408 ps
T1007 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.975050002 May 23 04:06:04 PM PDT 24 May 23 05:04:57 PM PDT 24 13950948245 ps
T701 /workspace/coverage/default/48.chip_sw_all_escalation_resets.835652222 May 23 04:20:58 PM PDT 24 May 23 04:31:58 PM PDT 24 5082739696 ps
T1008 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.560513831 May 23 04:13:22 PM PDT 24 May 23 04:47:47 PM PDT 24 22532864612 ps
T305 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1472795058 May 23 04:01:20 PM PDT 24 May 23 04:16:06 PM PDT 24 5657589296 ps
T1009 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3548002757 May 23 04:04:45 PM PDT 24 May 23 04:20:13 PM PDT 24 6439502164 ps
T1010 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3545724893 May 23 03:59:47 PM PDT 24 May 23 04:06:06 PM PDT 24 3172506167 ps
T725 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.4270117989 May 23 04:21:32 PM PDT 24 May 23 04:28:12 PM PDT 24 3870258028 ps
T1011 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1559051132 May 23 04:02:28 PM PDT 24 May 23 04:12:24 PM PDT 24 5627686040 ps
T1012 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2513981794 May 23 03:58:19 PM PDT 24 May 23 04:09:08 PM PDT 24 3661537888 ps
T1013 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3920815295 May 23 04:02:00 PM PDT 24 May 23 04:09:52 PM PDT 24 7239817730 ps
T1014 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1610732968 May 23 04:19:51 PM PDT 24 May 23 04:25:37 PM PDT 24 3465900740 ps
T1015 /workspace/coverage/default/25.chip_sw_all_escalation_resets.2982396374 May 23 04:21:35 PM PDT 24 May 23 04:33:28 PM PDT 24 4512676092 ps
T1016 /workspace/coverage/default/1.chip_sw_uart_tx_rx.386841428 May 23 04:00:50 PM PDT 24 May 23 04:12:27 PM PDT 24 4575985140 ps
T1017 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3826597575 May 23 03:58:10 PM PDT 24 May 23 04:16:19 PM PDT 24 6972345200 ps
T1018 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2824697594 May 23 04:08:17 PM PDT 24 May 23 04:17:49 PM PDT 24 4114323818 ps
T664 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.525160443 May 23 04:03:37 PM PDT 24 May 23 04:14:09 PM PDT 24 4593596500 ps
T704 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626775279 May 23 04:21:54 PM PDT 24 May 23 04:29:18 PM PDT 24 3869077628 ps
T1019 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.27341925 May 23 04:01:34 PM PDT 24 May 23 04:08:14 PM PDT 24 4618686760 ps
T185 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1190934379 May 23 04:05:26 PM PDT 24 May 23 04:21:42 PM PDT 24 7452262351 ps
T311 /workspace/coverage/default/2.chip_sw_pattgen_ios.2173078853 May 23 04:00:29 PM PDT 24 May 23 04:05:45 PM PDT 24 3378181248 ps
T380 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.509443396 May 23 04:08:15 PM PDT 24 May 23 04:14:44 PM PDT 24 7580257960 ps
T1020 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1040800056 May 23 04:21:37 PM PDT 24 May 23 04:32:07 PM PDT 24 4533648382 ps
T1021 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1772466301 May 23 03:59:38 PM PDT 24 May 23 04:11:58 PM PDT 24 6185187381 ps
T1022 /workspace/coverage/default/3.chip_tap_straps_prod.2873800712 May 23 04:16:29 PM PDT 24 May 23 04:18:47 PM PDT 24 2089807328 ps
T1023 /workspace/coverage/default/3.chip_tap_straps_rma.3968327729 May 23 04:16:22 PM PDT 24 May 23 04:22:47 PM PDT 24 4995814306 ps
T379 /workspace/coverage/default/45.chip_sw_all_escalation_resets.4044839943 May 23 04:21:56 PM PDT 24 May 23 04:33:19 PM PDT 24 5031754104 ps
T240 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3325321178 May 23 04:21:08 PM PDT 24 May 23 04:30:46 PM PDT 24 5850753816 ps
T706 /workspace/coverage/default/94.chip_sw_all_escalation_resets.1075950154 May 23 04:25:17 PM PDT 24 May 23 04:36:47 PM PDT 24 6288025780 ps
T1024 /workspace/coverage/default/0.chip_sw_uart_tx_rx.1350355871 May 23 03:59:44 PM PDT 24 May 23 04:08:51 PM PDT 24 4006739500 ps
T709 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2220976048 May 23 04:17:27 PM PDT 24 May 23 04:24:01 PM PDT 24 3229374620 ps
T637 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.761487624 May 23 04:14:20 PM PDT 24 May 23 04:22:40 PM PDT 24 5284442957 ps
T1025 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3529694076 May 23 04:18:34 PM PDT 24 May 23 04:55:52 PM PDT 24 8541318920 ps
T1026 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2126622124 May 23 04:17:04 PM PDT 24 May 23 04:21:44 PM PDT 24 3003749978 ps
T1027 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1101437531 May 23 04:08:24 PM PDT 24 May 23 07:37:59 PM PDT 24 255865978104 ps
T1028 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.713952513 May 23 04:08:20 PM PDT 24 May 23 04:17:30 PM PDT 24 4949233976 ps
T1029 /workspace/coverage/default/0.chip_sw_edn_kat.486297185 May 23 03:59:13 PM PDT 24 May 23 04:11:04 PM PDT 24 3628664472 ps
T1030 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.182506499 May 23 04:04:17 PM PDT 24 May 23 04:08:51 PM PDT 24 2901813708 ps
T712 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2219590571 May 23 04:20:35 PM PDT 24 May 23 04:26:15 PM PDT 24 3540236710 ps
T1031 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.72671341 May 23 04:03:45 PM PDT 24 May 23 04:57:40 PM PDT 24 20493976343 ps
T288 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.744864917 May 23 04:04:06 PM PDT 24 May 23 04:33:35 PM PDT 24 12229308686 ps
T1032 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3219374004 May 23 04:01:02 PM PDT 24 May 23 04:10:06 PM PDT 24 3732361464 ps
T34 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2408003331 May 23 04:07:14 PM PDT 24 May 23 04:12:01 PM PDT 24 2469495744 ps
T705 /workspace/coverage/default/34.chip_sw_all_escalation_resets.4254126550 May 23 04:22:10 PM PDT 24 May 23 04:32:54 PM PDT 24 5264110490 ps
T1033 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1957912068 May 23 04:04:23 PM PDT 24 May 23 04:12:33 PM PDT 24 9580238861 ps
T1034 /workspace/coverage/default/0.chip_sw_hmac_enc.502059223 May 23 04:04:38 PM PDT 24 May 23 04:09:26 PM PDT 24 2361479136 ps
T1035 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3113534334 May 23 04:08:06 PM PDT 24 May 23 04:40:24 PM PDT 24 7102771936 ps
T1036 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3014646117 May 23 04:00:46 PM PDT 24 May 23 04:06:27 PM PDT 24 2934878009 ps
T299 /workspace/coverage/default/1.chip_plic_all_irqs_20.107586058 May 23 04:01:51 PM PDT 24 May 23 04:16:06 PM PDT 24 4647899934 ps
T735 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4163853922 May 23 04:21:58 PM PDT 24 May 23 04:29:24 PM PDT 24 4033796350 ps
T1037 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1994054544 May 23 04:07:25 PM PDT 24 May 23 04:14:36 PM PDT 24 5320833720 ps
T1038 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1451385645 May 23 04:05:58 PM PDT 24 May 23 04:16:21 PM PDT 24 4973536416 ps
T279 /workspace/coverage/default/27.chip_sw_all_escalation_resets.3017383363 May 23 04:19:23 PM PDT 24 May 23 04:29:40 PM PDT 24 5155300256 ps
T1039 /workspace/coverage/default/36.chip_sw_all_escalation_resets.4127261854 May 23 04:19:56 PM PDT 24 May 23 04:29:22 PM PDT 24 5047465530 ps
T756 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3243096540 May 23 04:19:27 PM PDT 24 May 23 04:28:19 PM PDT 24 3344067324 ps
T357 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2933381791 May 23 04:01:54 PM PDT 24 May 23 04:05:45 PM PDT 24 3092204328 ps
T1040 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1800589288 May 23 04:05:07 PM PDT 24 May 23 04:30:23 PM PDT 24 8886974119 ps
T1041 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2456632187 May 23 04:06:03 PM PDT 24 May 23 04:19:18 PM PDT 24 9239191060 ps
T741 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2804880052 May 23 04:19:38 PM PDT 24 May 23 04:27:50 PM PDT 24 4184231168 ps
T1042 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3701458181 May 23 03:58:12 PM PDT 24 May 23 04:00:43 PM PDT 24 3170396967 ps
T1043 /workspace/coverage/default/2.rom_e2e_shutdown_output.1430236250 May 23 04:21:49 PM PDT 24 May 23 05:04:09 PM PDT 24 22317170293 ps
T1044 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3875723962 May 23 04:03:34 PM PDT 24 May 23 04:23:58 PM PDT 24 6510904167 ps
T1045 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3298680851 May 23 04:01:48 PM PDT 24 May 23 04:12:54 PM PDT 24 4586609908 ps
T1046 /workspace/coverage/default/1.chip_sw_aes_enc.3291152783 May 23 04:06:52 PM PDT 24 May 23 04:10:54 PM PDT 24 2771032584 ps
T672 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2678998539 May 23 04:20:30 PM PDT 24 May 23 04:27:11 PM PDT 24 3171270692 ps
T1047 /workspace/coverage/default/1.rom_keymgr_functest.244367808 May 23 04:08:19 PM PDT 24 May 23 04:20:04 PM PDT 24 4498811260 ps
T1048 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1139149085 May 23 04:15:24 PM PDT 24 May 23 04:20:58 PM PDT 24 2554080324 ps
T1049 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2160305626 May 23 04:04:08 PM PDT 24 May 23 04:23:55 PM PDT 24 6614448248 ps
T141 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3464640954 May 23 04:15:05 PM PDT 24 May 23 05:28:07 PM PDT 24 27884317460 ps
T1050 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.632188583 May 23 04:05:36 PM PDT 24 May 23 05:29:13 PM PDT 24 21708570409 ps
T241 /workspace/coverage/default/20.chip_sw_all_escalation_resets.3861259435 May 23 04:20:06 PM PDT 24 May 23 04:27:57 PM PDT 24 5268065050 ps
T1051 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3783735358 May 23 04:03:50 PM PDT 24 May 23 04:15:20 PM PDT 24 4516806838 ps
T186 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.88835371 May 23 04:06:12 PM PDT 24 May 23 04:18:27 PM PDT 24 6630994817 ps
T1052 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.476834560 May 23 04:09:03 PM PDT 24 May 23 04:39:42 PM PDT 24 8503402176 ps
T1053 /workspace/coverage/default/0.chip_sw_hmac_smoketest.4037525851 May 23 04:02:05 PM PDT 24 May 23 04:07:46 PM PDT 24 3097608246 ps
T1054 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1684345315 May 23 04:01:10 PM PDT 24 May 23 04:19:36 PM PDT 24 5362328976 ps
T1055 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.720614246 May 23 04:18:46 PM PDT 24 May 23 04:25:34 PM PDT 24 3616289232 ps
T1056 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.553297671 May 23 04:06:31 PM PDT 24 May 23 04:11:13 PM PDT 24 3350501345 ps
T1057 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4199950458 May 23 04:00:03 PM PDT 24 May 23 04:13:44 PM PDT 24 5939871720 ps
T1058 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3238810845 May 23 04:07:18 PM PDT 24 May 23 04:22:47 PM PDT 24 5133096236 ps
T1059 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1709152243 May 23 04:01:39 PM PDT 24 May 23 04:08:30 PM PDT 24 3560483994 ps
T645 /workspace/coverage/default/2.chip_sw_power_idle_load.1813322714 May 23 04:17:42 PM PDT 24 May 23 04:26:46 PM PDT 24 4367560216 ps
T1060 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.335157393 May 23 04:00:26 PM PDT 24 May 23 04:28:55 PM PDT 24 7932016192 ps
T1061 /workspace/coverage/default/2.chip_sw_kmac_entropy.2760310578 May 23 04:04:15 PM PDT 24 May 23 04:09:39 PM PDT 24 3090249876 ps
T1062 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.4183037031 May 23 04:01:32 PM PDT 24 May 23 04:12:59 PM PDT 24 4397971176 ps
T1063 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3586184586 May 23 04:24:09 PM PDT 24 May 23 04:34:24 PM PDT 24 4413008900 ps
T277 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2349711045 May 23 04:06:15 PM PDT 24 May 23 04:17:50 PM PDT 24 8528006948 ps
T765 /workspace/coverage/default/40.chip_sw_all_escalation_resets.1280832131 May 23 04:24:13 PM PDT 24 May 23 04:33:30 PM PDT 24 4552752740 ps
T638 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1227762901 May 23 04:07:04 PM PDT 24 May 23 04:16:02 PM PDT 24 4351606733 ps
T1064 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2594087578 May 23 04:17:32 PM PDT 24 May 23 04:26:53 PM PDT 24 3164193948 ps
T1065 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.404215087 May 23 03:59:49 PM PDT 24 May 23 04:06:55 PM PDT 24 2529169036 ps
T759 /workspace/coverage/default/79.chip_sw_all_escalation_resets.3242561626 May 23 04:25:19 PM PDT 24 May 23 04:36:39 PM PDT 24 5501484900 ps
T1066 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.229576042 May 23 04:06:51 PM PDT 24 May 23 04:14:23 PM PDT 24 4577871796 ps
T707 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3228772512 May 23 04:25:03 PM PDT 24 May 23 04:30:46 PM PDT 24 3480471200 ps
T1067 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1521191373 May 23 04:05:52 PM PDT 24 May 23 04:13:49 PM PDT 24 4902018800 ps
T1068 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3255637349 May 23 04:21:45 PM PDT 24 May 23 04:31:50 PM PDT 24 5318256656 ps
T1069 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3942151220 May 23 03:58:51 PM PDT 24 May 23 04:11:08 PM PDT 24 4105402781 ps
T1070 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1830950541 May 23 04:16:33 PM PDT 24 May 23 04:23:27 PM PDT 24 4455057700 ps
T1071 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2680988558 May 23 04:04:21 PM PDT 24 May 23 04:24:50 PM PDT 24 7541106363 ps
T1072 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.748147521 May 23 04:17:04 PM PDT 24 May 23 04:20:44 PM PDT 24 2609601192 ps
T1073 /workspace/coverage/default/2.chip_sw_aes_entropy.4161136329 May 23 04:09:08 PM PDT 24 May 23 04:12:55 PM PDT 24 2701301328 ps
T62 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1539352401 May 23 04:10:25 PM PDT 24 May 23 04:24:31 PM PDT 24 7605486177 ps
T1074 /workspace/coverage/default/1.chip_sw_example_concurrency.3017836690 May 23 04:05:34 PM PDT 24 May 23 04:09:58 PM PDT 24 2773744748 ps
T1075 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3339787515 May 23 04:06:45 PM PDT 24 May 23 04:19:08 PM PDT 24 4283493932 ps
T1076 /workspace/coverage/default/2.chip_sw_uart_smoketest.379812999 May 23 04:21:51 PM PDT 24 May 23 04:26:50 PM PDT 24 2897723172 ps
T1077 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1146671027 May 23 04:00:19 PM PDT 24 May 23 04:12:00 PM PDT 24 9082457290 ps
T1078 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1957607792 May 23 04:06:07 PM PDT 24 May 23 05:14:24 PM PDT 24 14460518810 ps
T1079 /workspace/coverage/default/2.chip_sw_otbn_randomness.3873742700 May 23 04:05:30 PM PDT 24 May 23 04:20:15 PM PDT 24 6023960676 ps
T1080 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3091068832 May 23 04:05:00 PM PDT 24 May 23 04:58:49 PM PDT 24 14347166288 ps
T1081 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1421576651 May 23 04:17:10 PM PDT 24 May 23 04:22:24 PM PDT 24 3121767848 ps
T724 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.874235831 May 23 04:21:40 PM PDT 24 May 23 04:30:10 PM PDT 24 3740262092 ps
T490 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.289123507 May 23 04:06:05 PM PDT 24 May 23 04:21:11 PM PDT 24 4966183120 ps
T1082 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.801352687 May 23 04:02:28 PM PDT 24 May 23 04:19:06 PM PDT 24 5785572305 ps
T1083 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3951522253 May 23 04:01:07 PM PDT 24 May 23 04:20:44 PM PDT 24 7515585772 ps
T727 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200487823 May 23 04:21:25 PM PDT 24 May 23 04:28:16 PM PDT 24 3700535486 ps
T1084 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2696573516 May 23 04:12:53 PM PDT 24 May 23 04:19:20 PM PDT 24 3127446112 ps
T1085 /workspace/coverage/default/2.chip_sw_example_rom.163083717 May 23 04:05:29 PM PDT 24 May 23 04:07:19 PM PDT 24 2310920328 ps
T1086 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.4159822668 May 23 04:01:40 PM PDT 24 May 23 04:14:47 PM PDT 24 4846380440 ps
T1087 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1508878591 May 23 04:03:05 PM PDT 24 May 23 04:15:47 PM PDT 24 5868940304 ps
T732 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4258294752 May 23 04:22:19 PM PDT 24 May 23 04:28:33 PM PDT 24 3897348200 ps
T355 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2317051093 May 23 04:02:58 PM PDT 24 May 23 04:04:58 PM PDT 24 1804766926 ps
T1088 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1064343694 May 23 04:05:01 PM PDT 24 May 23 04:31:41 PM PDT 24 13967184045 ps
T1089 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3713266087 May 23 04:07:29 PM PDT 24 May 23 05:08:24 PM PDT 24 14500799285 ps
T1090 /workspace/coverage/default/1.chip_sw_kmac_idle.1770312822 May 23 04:02:53 PM PDT 24 May 23 04:07:37 PM PDT 24 3362708816 ps
T1091 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.587148187 May 23 03:58:05 PM PDT 24 May 23 04:04:49 PM PDT 24 4414464288 ps
T1092 /workspace/coverage/default/2.rom_e2e_asm_init_prod.2045490558 May 23 04:21:13 PM PDT 24 May 23 05:19:35 PM PDT 24 14185444540 ps
T37 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.86506141 May 23 03:59:38 PM PDT 24 May 23 04:05:35 PM PDT 24 4209552596 ps
T1093 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.480853261 May 23 04:00:01 PM PDT 24 May 23 04:04:21 PM PDT 24 2906271384 ps
T80 /workspace/coverage/default/35.chip_sw_all_escalation_resets.799323449 May 23 04:21:15 PM PDT 24 May 23 04:31:14 PM PDT 24 5608446916 ps
T708 /workspace/coverage/default/58.chip_sw_all_escalation_resets.813856760 May 23 04:21:28 PM PDT 24 May 23 04:31:02 PM PDT 24 4259126792 ps
T1094 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4213235339 May 23 04:06:17 PM PDT 24 May 23 04:51:35 PM PDT 24 11139813540 ps
T280 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1663121566 May 23 04:22:02 PM PDT 24 May 23 04:27:24 PM PDT 24 3819831442 ps
T1095 /workspace/coverage/default/2.chip_sw_kmac_idle.1915877825 May 23 04:12:16 PM PDT 24 May 23 04:15:31 PM PDT 24 2527397272 ps
T1096 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3075685601 May 23 04:05:06 PM PDT 24 May 23 04:10:01 PM PDT 24 2980636090 ps
T1097 /workspace/coverage/default/43.chip_sw_all_escalation_resets.162259986 May 23 04:23:25 PM PDT 24 May 23 04:32:05 PM PDT 24 5542367540 ps
T1098 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3931358708 May 23 04:01:05 PM PDT 24 May 23 04:06:11 PM PDT 24 2572148638 ps
T1099 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.117650918 May 23 04:12:12 PM PDT 24 May 23 04:36:01 PM PDT 24 8568081713 ps
T1100 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2777500479 May 23 04:11:32 PM PDT 24 May 23 04:28:47 PM PDT 24 6601025072 ps
T1101 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3237453171 May 23 04:08:20 PM PDT 24 May 23 04:12:31 PM PDT 24 2350453742 ps
T1102 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.442538002 May 23 04:02:00 PM PDT 24 May 23 04:18:19 PM PDT 24 5846092565 ps
T1103 /workspace/coverage/default/2.chip_sw_csrng_kat_test.4076482032 May 23 04:10:09 PM PDT 24 May 23 04:14:27 PM PDT 24 2864899140 ps
T269 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2017585176 May 23 04:15:19 PM PDT 24 May 23 04:19:10 PM PDT 24 2824726535 ps
T1104 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1841969920 May 23 04:04:25 PM PDT 24 May 23 05:09:11 PM PDT 24 13515962433 ps
T302 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3743551942 May 23 04:07:01 PM PDT 24 May 23 04:44:56 PM PDT 24 7519744904 ps
T1105 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3924242273 May 23 04:08:07 PM PDT 24 May 23 05:10:24 PM PDT 24 14474487076 ps
T714 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.965878095 May 23 04:20:06 PM PDT 24 May 23 04:27:40 PM PDT 24 3849859624 ps
T361 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2761091352 May 23 04:02:52 PM PDT 24 May 23 04:14:07 PM PDT 24 4178919480 ps
T1106 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2970396935 May 23 03:58:51 PM PDT 24 May 23 04:35:29 PM PDT 24 9502833850 ps
T729 /workspace/coverage/default/5.chip_sw_all_escalation_resets.999084920 May 23 04:19:51 PM PDT 24 May 23 04:29:34 PM PDT 24 5624796210 ps
T652 /workspace/coverage/default/0.chip_sw_plic_sw_irq.2172444230 May 23 04:04:40 PM PDT 24 May 23 04:08:09 PM PDT 24 2566907928 ps
T1107 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3364920302 May 23 04:04:28 PM PDT 24 May 23 04:08:30 PM PDT 24 2210687467 ps
T387 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3549863881 May 23 04:14:32 PM PDT 24 May 23 04:22:07 PM PDT 24 6980033176 ps
T1108 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2891119228 May 23 04:11:36 PM PDT 24 May 23 04:21:17 PM PDT 24 6417095568 ps
T1109 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.574859296 May 23 03:59:01 PM PDT 24 May 23 04:24:59 PM PDT 24 7715768846 ps
T217 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2336058933 May 23 04:15:29 PM PDT 24 May 23 04:49:43 PM PDT 24 19163981816 ps
T748 /workspace/coverage/default/92.chip_sw_all_escalation_resets.2142985657 May 23 04:22:01 PM PDT 24 May 23 04:33:25 PM PDT 24 5963441440 ps
T1110 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1487383882 May 23 04:19:17 PM PDT 24 May 23 04:24:29 PM PDT 24 3584708228 ps
T1111 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1609842386 May 23 04:23:47 PM PDT 24 May 23 04:35:12 PM PDT 24 6074244568 ps
T1112 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3814398836 May 23 04:02:53 PM PDT 24 May 23 04:10:35 PM PDT 24 3547468512 ps
T760 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113966134 May 23 04:08:22 PM PDT 24 May 23 04:15:36 PM PDT 24 3334027928 ps
T1113 /workspace/coverage/default/0.rom_e2e_asm_init_rma.3506904755 May 23 04:07:14 PM PDT 24 May 23 05:08:46 PM PDT 24 14374836301 ps
T766 /workspace/coverage/default/0.chip_sw_all_escalation_resets.3576883230 May 23 04:01:35 PM PDT 24 May 23 04:12:05 PM PDT 24 5314017552 ps
T1114 /workspace/coverage/default/41.chip_sw_all_escalation_resets.947087607 May 23 04:20:06 PM PDT 24 May 23 04:31:53 PM PDT 24 5732535260 ps
T1115 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.596071331 May 23 04:17:18 PM PDT 24 May 23 04:56:11 PM PDT 24 13589969928 ps
T1116 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3551288313 May 23 04:00:51 PM PDT 24 May 23 04:08:28 PM PDT 24 5163646872 ps
T1117 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1970074542 May 23 04:20:52 PM PDT 24 May 23 04:28:09 PM PDT 24 3815340388 ps
T1118 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3229144905 May 23 04:11:18 PM PDT 24 May 23 04:16:14 PM PDT 24 2806681520 ps
T767 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2104958772 May 23 04:06:41 PM PDT 24 May 23 04:12:10 PM PDT 24 4000006776 ps
T1119 /workspace/coverage/default/0.chip_sw_flash_crash_alert.1722532746 May 23 04:04:22 PM PDT 24 May 23 04:14:25 PM PDT 24 5779949608 ps
T1120 /workspace/coverage/default/30.chip_sw_all_escalation_resets.165437544 May 23 04:19:42 PM PDT 24 May 23 04:30:09 PM PDT 24 5587433786 ps
T53 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4020027305 May 23 04:16:11 PM PDT 24 May 23 04:45:28 PM PDT 24 19073962760 ps
T719 /workspace/coverage/default/87.chip_sw_all_escalation_resets.564557584 May 23 04:21:13 PM PDT 24 May 23 04:34:16 PM PDT 24 6044616314 ps
T1121 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.200436647 May 23 04:00:20 PM PDT 24 May 23 04:36:08 PM PDT 24 11241898157 ps
T1122 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2601931513 May 23 04:12:06 PM PDT 24 May 23 05:02:48 PM PDT 24 10737195512 ps
T99 /workspace/coverage/default/2.chip_tap_straps_rma.1861136181 May 23 04:14:16 PM PDT 24 May 23 04:17:31 PM PDT 24 3045879021 ps
T1123 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.670738701 May 23 04:00:44 PM PDT 24 May 23 04:06:01 PM PDT 24 2693903888 ps
T1124 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.9391335 May 23 04:24:49 PM PDT 24 May 23 05:22:39 PM PDT 24 14963597508 ps
T211 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4000801288 May 23 04:11:38 PM PDT 24 May 23 04:31:47 PM PDT 24 6257038800 ps
T1125 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.636527198 May 23 03:59:27 PM PDT 24 May 23 04:08:55 PM PDT 24 4470474703 ps
T1126 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3114262951 May 23 04:03:39 PM PDT 24 May 23 04:13:32 PM PDT 24 4363846856 ps
T187 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3731061231 May 23 04:03:49 PM PDT 24 May 23 04:10:48 PM PDT 24 3491338157 ps
T1127 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3874999162 May 23 04:03:15 PM PDT 24 May 23 04:13:48 PM PDT 24 3451796406 ps
T754 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2186178903 May 23 04:24:36 PM PDT 24 May 23 04:31:08 PM PDT 24 3288637792 ps
T1128 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.447863625 May 23 04:08:09 PM PDT 24 May 23 04:11:07 PM PDT 24 2505850336 ps
T224 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.856874938 May 23 04:19:27 PM PDT 24 May 23 04:25:23 PM PDT 24 3646953344 ps
T1129 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4069326170 May 23 04:03:06 PM PDT 24 May 23 04:22:52 PM PDT 24 10461404303 ps
T1130 /workspace/coverage/default/0.chip_sw_usbdev_stream.3298588233 May 23 04:00:23 PM PDT 24 May 23 05:27:14 PM PDT 24 18713534936 ps
T214 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2730072494 May 23 04:04:57 PM PDT 24 May 23 05:12:13 PM PDT 24 17607146184 ps
T1131 /workspace/coverage/default/0.chip_sw_power_idle_load.3163146427 May 23 04:03:11 PM PDT 24 May 23 04:15:51 PM PDT 24 4153153388 ps
T1132 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3231807779 May 23 04:01:56 PM PDT 24 May 23 04:29:26 PM PDT 24 18182034389 ps
T1133 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.999268115 May 23 04:13:53 PM PDT 24 May 23 04:21:06 PM PDT 24 5029886070 ps
T1134 /workspace/coverage/default/21.chip_sw_all_escalation_resets.3235810076 May 23 04:18:27 PM PDT 24 May 23 04:30:27 PM PDT 24 5973086302 ps
T1135 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3540331566 May 23 04:17:03 PM PDT 24 May 23 04:28:37 PM PDT 24 4167870760 ps
T687 /workspace/coverage/default/60.chip_sw_all_escalation_resets.799456800 May 23 04:24:38 PM PDT 24 May 23 04:33:53 PM PDT 24 4900667166 ps
T1136 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2839674198 May 23 03:59:46 PM PDT 24 May 23 04:17:42 PM PDT 24 6101748080 ps
T730 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1695501427 May 23 04:22:17 PM PDT 24 May 23 04:29:38 PM PDT 24 4124088460 ps
T1137 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.4239317519 May 23 04:05:07 PM PDT 24 May 23 05:08:46 PM PDT 24 14606624684 ps
T1138 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.848166782 May 23 03:59:04 PM PDT 24 May 23 04:08:26 PM PDT 24 4182875116 ps
T1139 /workspace/coverage/default/1.chip_sw_example_flash.3322291310 May 23 04:08:47 PM PDT 24 May 23 04:13:04 PM PDT 24 2754569792 ps
T674 /workspace/coverage/default/4.chip_sw_all_escalation_resets.743227342 May 23 04:17:10 PM PDT 24 May 23 04:30:17 PM PDT 24 6380675030 ps
T1140 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.815906072 May 23 04:14:29 PM PDT 24 May 23 04:25:11 PM PDT 24 4060223230 ps
T722 /workspace/coverage/default/33.chip_sw_all_escalation_resets.3748596610 May 23 04:20:31 PM PDT 24 May 23 04:31:55 PM PDT 24 5618211800 ps
T1141 /workspace/coverage/default/0.rom_e2e_shutdown_output.1549411683 May 23 04:05:13 PM PDT 24 May 23 04:59:39 PM PDT 24 27494897432 ps
T626 /workspace/coverage/default/2.chip_sw_edn_auto_mode.813542114 May 23 04:09:10 PM PDT 24 May 23 04:39:09 PM PDT 24 6291584160 ps
T306 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.178249715 May 23 04:00:34 PM PDT 24 May 23 04:14:41 PM PDT 24 4877291254 ps
T1142 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1920648565 May 23 03:58:45 PM PDT 24 May 23 04:01:22 PM PDT 24 2762607152 ps
T1143 /workspace/coverage/default/1.chip_tap_straps_prod.3425358694 May 23 04:03:33 PM PDT 24 May 23 04:06:33 PM PDT 24 3391555473 ps
T334 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3798660613 May 23 04:17:42 PM PDT 24 May 23 04:30:24 PM PDT 24 5379585192 ps
T717 /workspace/coverage/default/65.chip_sw_all_escalation_resets.548635323 May 23 04:25:33 PM PDT 24 May 23 04:37:44 PM PDT 24 4943271732 ps
T1144 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.353160134 May 23 04:04:25 PM PDT 24 May 23 04:17:01 PM PDT 24 4100973624 ps
T1145 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2432002095 May 23 04:03:38 PM PDT 24 May 23 04:11:55 PM PDT 24 5620400040 ps
T1146 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3006687897 May 23 04:03:35 PM PDT 24 May 23 04:06:38 PM PDT 24 2486404934 ps
T744 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016091343 May 23 04:18:40 PM PDT 24 May 23 04:26:41 PM PDT 24 3401283828 ps
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