CHIP Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.509m	2.615ms	3	3	100.00
		chip_sw_example_rom	2.294m	2.578ms	3	3	100.00
		chip_sw_example_manufacturer	4.141m	2.683ms	3	3	100.00
		chip_sw_example_concurrency	4.374m	2.774ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	8.670m	6.614ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.822m	5.281ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.427h	87.432ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.940h	80.693ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.483m	2.691ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.940h	80.693ms	4	5	80.00
		chip_csr_rw	11.822m	5.281ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	13.140s	258.434us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.030m	4.150ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.030m	4.150ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.030m	4.150ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	13.131m	4.254ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	13.131m	4.254ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	12.143m	4.141ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	13.499m	4.281ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	14.312m	3.931ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	43.532m	13.244ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	28.578m	8.708ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	36.827m	13.978ms	5	5	100.00
V1		TOTAL			199	220	90.45
V2	chip_pin_mux	chip_padctrl_attributes	5.159m	5.778ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.159m	5.778ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.550m	3.317ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.779m	6.076ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.696m	3.758ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	28.103m	15.144ms	5	5	100.00
		chip_tap_straps_testunlock0	10.854m	7.858ms	5	5	100.00
		chip_tap_straps_rma	8.619m	5.268ms	4	5	80.00
		chip_tap_straps_prod	33.124m	17.937ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.244m	3.378ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	28.454m	7.932ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	12.673m	6.491ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	12.673m	6.491ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.800m	7.247ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	42.523m	19.103ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.592m	4.822ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.830m	6.245ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.294h	18.456ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.909m	2.981ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	24.203m	6.963ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.233m	2.959ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	32.566m	10.010ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	5.825m	3.280ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.345m	4.974ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.203m	2.581ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.482m	2.546ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	18.706m	8.732ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.295m	4.978ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.261m	2.898ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.295m	4.978ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.526m	2.540ms	3	3	100.00
		chip_sw_aes_smoketest	4.910m	2.959ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.656m	2.812ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.467m	2.479ms	3	3	100.00
		chip_sw_csrng_smoketest	5.500m	3.290ms	3	3	100.00
		chip_sw_entropy_src_smoketest	9.759m	3.251ms	3	3	100.00
		chip_sw_gpio_smoketest	5.559m	2.949ms	3	3	100.00
		chip_sw_hmac_smoketest	5.660m	3.098ms	3	3	100.00
		chip_sw_kmac_smoketest	4.456m	3.278ms	3	3	100.00
		chip_sw_otbn_smoketest	44.720m	11.753ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.086m	2.572ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.324m	4.210ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.822m	5.032ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.218m	3.122ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.535m	2.554ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.532m	2.205ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.903m	2.280ms	3	3	100.00
		chip_sw_uart_smoketest	4.959m	2.898ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.717m	4.499ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.718h	76.827ms	2	3	66.67
V2	chip_sw_secure_boot	rom_e2e_smoke	55.202m	14.026ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.074m	4.099ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.632m	4.153ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.690m	10.397ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	5.050m	3.523ms	0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.217h	63.175ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	10.830m	5.948ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	10.830m	5.948ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.940h	80.693ms	4	5	80.00
		chip_same_csr_outstanding	1.040h	29.698ms	20	20	100.00
		chip_csr_hw_reset	8.670m	6.614ms	5	5	100.00
		chip_csr_rw	11.822m	5.281ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.940h	80.693ms	4	5	80.00
		chip_same_csr_outstanding	1.040h	29.698ms	20	20	100.00
		chip_csr_hw_reset	8.670m	6.614ms	5	5	100.00
		chip_csr_rw	11.822m	5.281ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.800m	2.327ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.160s	55.317us	100	100	100.00
		xbar_smoke_large_delays	2.123m	9.346ms	100	100	100.00
		xbar_smoke_slow_rsp	2.259m	6.954ms	100	100	100.00
		xbar_random_zero_delays	58.660s	587.413us	100	100	100.00
		xbar_random_large_delays	21.233m	116.106ms	100	100	100.00
		xbar_random_slow_rsp	21.366m	66.994ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.205m	1.254ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.333m	1.556ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.855m	2.741ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.333m	1.556ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.010m	4.040ms	100	100	100.00
		xbar_access_same_device_slow_rsp	47.257m	166.461ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.568m	2.730ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	15.827m	22.925ms	100	100	100.00
		xbar_stress_all_with_error	12.121m	17.429ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	19.260m	20.854ms	100	100	100.00
		xbar_stress_all_with_reset_error	21.991m	16.967ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	55.202m	14.026ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	54.406m	27.495ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.156h	14.048ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	46.129m	10.909ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	57.051m	14.536ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.132h	14.350ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.009h	13.529ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.059h	14.647ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	45.293m	11.140ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.060h	14.607ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.013h	14.523ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.003h	14.152ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.138h	14.461ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.410h	17.827ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.512h	22.726ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.705h	22.182ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.611h	22.507ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.617h	22.378ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.283h	17.718ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.607h	21.474ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.471h	21.559ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.501h	22.137ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.393h	21.709ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	50.450m	10.941ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	1.020h	13.591ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	59.667m	13.375ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.085h	13.779ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	58.850m	13.951ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	55.581m	11.080ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	57.262m	13.526ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	1.079h	13.516ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	56.615m	14.062ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	1.047h	13.743ms	1	1	100.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1.005h	10.881ms	3	3	100.00
		rom_e2e_asm_init_dev	58.063m	14.429ms	3	3	100.00
		rom_e2e_asm_init_prod	1.052h	14.072ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.015h	14.501ms	3	3	100.00
		rom_e2e_asm_init_rma	1.025h	14.375ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.330h	15.770ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.136h	14.375ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.029h	14.255ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.167h	20.017ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.485m	2.799ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.909m	2.981ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.817m	2.871ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.638m	3.370ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	30.993m	8.396ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.072m	18.138ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.072m	18.138ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.588m	4.280ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.324m	4.210ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.588m	4.280ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.544m	8.954ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.544m	8.954ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	11.350m	7.306ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.778m	5.848ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.434m	5.778ms	3	3	100.00
		chip_sw_aes_idle	3.638m	3.370ms	3	3	100.00
		chip_sw_hmac_enc_idle	4.917m	2.807ms	3	3	100.00
		chip_sw_kmac_idle	4.720m	2.769ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.864m	5.235ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.749m	5.125ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.336m	5.040ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.864m	4.364ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	23.364m	9.402ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.666m	4.060ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.342m	4.283ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.192m	3.438ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.923m	4.313ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.617m	4.055ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.715m	5.086ms	3	3	100.00
		chip_sw_ast_clk_outputs	18.800m	7.247ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.086m	4.054ms	0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.192m	3.438ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.923m	4.313ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.592m	4.822ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.830m	6.245ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.294h	18.456ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.909m	2.981ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	24.203m	6.963ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.233m	2.959ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	32.566m	10.010ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	5.825m	3.280ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.345m	4.974ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.203m	2.581ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.508m	2.698ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.375m	4.619ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	20.464m	7.541ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.072h	24.953ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.644m	3.004ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.960m	2.581ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	26.134m	10.010ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.453m	3.279ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	12.677m	5.869ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	40.647m	23.208ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.217h	27.884ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.800m	7.247ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.512m	4.318ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	9.131m	3.326ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.339m	6.454ms	98	100	98.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	32.282m	7.103ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	37.885m	7.520ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	7.309m	5.205ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	16.776m	7.652ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.273m	2.865ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.725m	6.538ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	29.629m	22.074ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	4.909m	2.496ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	45.630s	10.360us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.445m	4.517ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	29.629m	22.074ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	29.629m	22.074ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.002h	19.922ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.002h	19.922ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	7.231m	5.227ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.072m	18.138ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.340h	19.651ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.243m	2.694ms	3	3	100.00
		chip_sw_edn_entropy_reqs	21.767m	7.570ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.243m	2.694ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	37.885m	7.520ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	3.846m	2.814ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	42.013m	26.317ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	17.902m	6.102ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.830m	6.245ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.679m	4.879ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.592m	4.822ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	6.550m	3.261ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	42.013m	26.317ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.686m	3.547ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	38.289m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	6.779m	3.184ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	6.550m	3.261ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	6.779m	3.184ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	6.779m	3.184ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	6.779m	3.184ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	6.779m	3.184ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.339m	6.454ms	98	100	98.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	9.552m	11.645ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.429m	4.918ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	10.377m	5.256ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	10.377m	5.256ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.365m	3.400ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.233m	2.959ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.917m	2.807ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.727m	5.658ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	17.403m	4.985ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	13.628m	5.642ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.571m	4.068ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	38.289m	10.010ms	0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	32.566m	10.010ms	2	3	66.67
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	34.691m	10.010ms	1	3	33.33
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	30.993m	8.396ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.121h	17.607ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.212m	2.767ms	3	3	100.00
		chip_sw_kmac_mode_kmac	7.267m	3.153ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.825m	3.280ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	38.289m	10.010ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.950m	4.551ms	0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.638m	3.145ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.387m	3.090ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.720m	2.769ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	8.719m	5.227ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	28.103m	15.144ms	5	5	100.00
		chip_tap_straps_rma	8.619m	5.268ms	4	5	80.00
		chip_tap_straps_prod	33.124m	17.937ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.144m	3.139ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.950m	4.551ms	0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.950m	4.551ms	0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.950m	4.551ms	0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	36.620m	9.503ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	6.779m	3.184ms	0	3	0.00
		chip_sw_flash_rma_unlocked	6.550m	3.261ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.301m	3.646ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.439m	7.528ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	19.763m	6.614ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.393m	9.176ms	3	3	100.00
		chip_sw_lc_ctrl_transition	3.950m	4.551ms	0	15	0.00
		chip_sw_keymgr_key_derivation	38.289m	10.010ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	11.057m	9.452ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	12.527m	8.694ms	3	3	100.00
		chip_prim_tl_access	9.552m	11.645ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.086m	4.054ms	0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.666m	4.060ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.342m	4.283ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.192m	3.438ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.923m	4.313ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.617m	4.055ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.715m	5.086ms	3	3	100.00
		chip_tap_straps_dev	28.103m	15.144ms	5	5	100.00
		chip_tap_straps_rma	8.619m	5.268ms	4	5	80.00
		chip_tap_straps_prod	33.124m	17.937ms	5	5	100.00
		chip_rv_dm_lc_disabled	10.268m	13.856ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	6.346m	3.456ms	0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	3.175m	3.521ms	0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.418m	2.870ms	0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	8.944m	5.265ms	0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	4.192m	3.753ms	0	3	0.00
		chip_rv_dm_lc_disabled	10.268m	13.856ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	3.486m	3.943ms	0	3	0.00
		chip_sw_lc_walkthrough_prod	4.234m	4.326ms	0	3	0.00
		chip_sw_lc_walkthrough_prodend	3.369m	3.507ms	0	3	0.00
		chip_sw_lc_walkthrough_rma	3.715m	4.037ms	0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	4.192m	3.753ms	0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	3.675m	3.761ms	0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	4.148m	4.122ms	0	3	0.00
		rom_volatile_raw_unlock	4.074m	4.441ms	0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.950m	4.551ms	0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	42.013m	26.317ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.675m	3.043ms	3	3	100.00
		chip_sw_keymgr_key_derivation	38.289m	10.010ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	12.192m	5.110ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.835m	2.825ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	42.013m	26.317ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.675m	3.043ms	3	3	100.00
		chip_sw_keymgr_key_derivation	38.289m	10.010ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	12.192m	5.110ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.835m	2.825ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.950m	4.551ms	0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.090m	14.875ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.144m	3.139ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.301m	3.646ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.439m	7.528ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	19.763m	6.614ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.393m	9.176ms	3	3	100.00
		chip_sw_lc_ctrl_transition	3.950m	4.551ms	0	15	0.00
		chip_prim_tl_access	9.552m	11.645ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.552m	11.645ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.283m	7.090ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	29.266m	19.074ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.068m	7.210ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.902m	9.279ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	14.933m	7.124ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	38.857m	21.989ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	27.495m	18.182ms	2	3	66.67
		chip_sw_aon_timer_wdog_bite_reset	13.544m	8.954ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	26.175m	10.096ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.434m	4.970ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.283m	7.090ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	7.836m	3.817ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	58.376m	36.033ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	7.827m	7.240ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.343m	4.183ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.862m	25.018ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.725m	6.538ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	35.779m	11.242ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	41.653m	23.058ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.169m	2.848ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.339m	6.454ms	98	100	98.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.057m	9.452ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.057m	9.452ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	35.779m	11.242ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.862m	25.018ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	10.434m	4.970ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.324m	4.210ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.939m	4.956ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	15.758m	6.453ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.501m	4.882ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	30.057m	9.777ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.128m	2.979ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.339m	6.454ms	98	100	98.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	30.629m	8.503ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	21.428m	6.259ms	3	3	100.00
		chip_plic_all_irqs_10	10.258m	3.875ms	3	3	100.00
		chip_plic_all_irqs_20	14.325m	4.421ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.840m	2.437ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.199m	2.598ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	55.202m	14.026ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	16.248m	7.452ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	7.668m	4.875ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.329m	3.066ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.923m	3.207ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.192m	5.110ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.345m	4.974ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	15.714m	8.643ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.660m	5.940ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.527m	8.694ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.339m	6.454ms	98	100	98.00
		chip_sw_data_integrity_escalation	12.673m	6.491ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.036m	2.539ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.413m	3.429ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.747m	3.678ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.192m	3.493ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	31.511m	8.044ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.922h	31.539ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	47.151m	11.504ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.625m	3.243ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	8.719m	5.227ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.339m	6.454ms	98	100	98.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.467m	3.303ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	30.057m	9.777ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.566m	4.464ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.517m	3.776ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	29.575m	13.076ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	32.282m	7.103ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	30.629m	8.503ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.492h	255.866ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	30.507m	18.076ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	24.618m	13.557ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.939m	4.956ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.558m	5.341ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.715m	3.424ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	8.619m	5.268ms	4	5	80.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.268m	13.856ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2540	2627	96.69
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.465m	2.670ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	18.364m	5.909ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.872m	1.660ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.906m	2.223ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.078m	1.577ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.304h	60.000ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.137h	57.960ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.283h	60.000ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.724m	3.744ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.702m	2.972ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	29.971m	6.292ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	28.641m	8.385ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.821m	3.629ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	20.224m	5.076ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	6.902m	4.827ms	0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.660m	6.209ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	7.802m	6.025ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.759m	6.023ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	35.779m	11.242ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.339m	6.454ms	98	100	98.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	13.131m	4.254ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.447h	18.714ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.872m	1.660ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.906m	2.223ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.078m	1.577ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.962m	6.018ms	3	3	100.00
V3		TOTAL			29	45	64.44
	Unmapped tests	chip_sival_flash_info_access	6.109m	3.841ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.089m	5.368ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	5.657m	2.935ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	58.790m	17.018ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	18.210m	5.383ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.072m	4.966ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.750m	5.874ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.814m	3.157ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.819m	3.092ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	5.618m	2.898ms	3	3	100.00
		TOTAL			2801	2925	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	10	10	10	100.00
V1	18	18	16	88.89
V2	281	266	234	83.27
V2S	1	1	1	100.00
V3	90	21	11	12.22

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.37	95.32	93.65	91.81	--	94.46	97.38	99.58

Failure Buckets

• UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test chip_csr_mem_rw_with_rand_reset has 20 failures.

    • 0.chip_csr_mem_rw_with_rand_reset.83577998245208657338312052283474795461253526665518788341796703095613517109277
      Line 428, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2859.631538 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2859.631538 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_csr_mem_rw_with_rand_reset.104304677027111590018901595011347271689675869468777110062073729827090826820138
      Line 373, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2691.298809 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2691.298809 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 18 failures:

  • Test chip_sw_lc_ctrl_transition has 15 failures.

    • 0.chip_sw_lc_ctrl_transition.81498020070858158305500268421477550192784259791695152249582969905032486754114
      Line 900, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log

        UVM_FATAL @ 4045.457929 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4045.457929 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_lc_ctrl_transition.11092446402157809514609256862875673926678417202528937679892380840483794591534
      Line 930, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest/run.log

        UVM_FATAL @ 4466.627203 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4466.627203 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

  • Test chip_sw_clkmgr_external_clk_src_for_lc has 3 failures.

    • 0.chip_sw_clkmgr_external_clk_src_for_lc.20876925255238196769028331722670495300806470613740534875949840404414741432593
      Line 892, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

        UVM_FATAL @ 4778.520359 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4778.520359 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_clkmgr_external_clk_src_for_lc.84506245863769584146570186070800359706802642554960565456098840508456772046663
      Line 1000, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

        UVM_FATAL @ 4332.443054 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4332.443054 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 12 failures:

  • Test chip_sw_lc_walkthrough_dev has 3 failures.

    • 0.chip_sw_lc_walkthrough_dev.28218580943236876412415145090010500524584624164145251355585830798389120461950
      Line 860, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log

        UVM_FATAL @ 3335.089904 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3335.089904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_lc_walkthrough_dev.4335535610719883549334540387497955351820736093521694112343604800102876845278
      Line 1009, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log

        UVM_FATAL @ 3943.498790 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3943.498790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test chip_sw_lc_walkthrough_prod has 3 failures.

    • 0.chip_sw_lc_walkthrough_prod.79373975495434940792857053053305654499281905095342028542028665245222656035361
      Line 850, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log

        UVM_FATAL @ 3235.812935 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3235.812935 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_lc_walkthrough_prod.26557009758491954092144235671368011259037895138482873216748226255880395348871
      Line 903, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log

        UVM_FATAL @ 4325.558313 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4325.558313 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test chip_sw_lc_walkthrough_prodend has 3 failures.

    • 0.chip_sw_lc_walkthrough_prodend.48719969394844281894748769421033416740698420868183131238408663121033036352210
      Line 857, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log

        UVM_FATAL @ 3506.918292 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3506.918292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_lc_walkthrough_prodend.93385693301962876574198767131100612027998504671084766262271823940934718548379
      Line 943, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest/run.log

        UVM_FATAL @ 4208.412976 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4208.412976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test chip_sw_lc_walkthrough_rma has 3 failures.

    • 0.chip_sw_lc_walkthrough_rma.26123086228425027032679809101383165751075961142318580270308949923099207800236
      Line 864, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log

        UVM_FATAL @ 4036.617056 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4036.617056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_lc_walkthrough_rma.41876228981321404245562129491968834106627194400343191717135593592246943736670
      Line 961, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log

        UVM_FATAL @ 3333.939601 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3333.939601 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 9 failures:

  • Test chip_sw_lc_ctrl_volatile_raw_unlock has 3 failures.

    • 0.chip_sw_lc_ctrl_volatile_raw_unlock.9260052345303696668805701362277372174651611319219859331529124820178832478755
      Line 838, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

        UVM_FATAL @ 3760.506466 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3760.506466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_lc_ctrl_volatile_raw_unlock.80318246429767744480406368468232998076568515032455454866252789469246566456936
      Line 860, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

        UVM_FATAL @ 4429.490474 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4429.490474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz has 3 failures.

    • 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.106934413362355156636207514065942892796577087795245934571233468958755152511062
      Line 964, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log

        UVM_FATAL @ 4121.674244 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4121.674244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.110711401752003100544452105540081302196724896984202702881518678154938748682673
      Line 924, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log

        UVM_FATAL @ 4683.425379 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4683.425379 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test rom_volatile_raw_unlock has 3 failures.

    • 0.rom_volatile_raw_unlock.2077139038749050616187129674704047098436312158930318374158473414705855294251
      Line 1002, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log

        UVM_FATAL @ 4415.631233 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4415.631233 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_volatile_raw_unlock.24610778301489327085371565386225644040060534104103858947258443186168976461858
      Line 1005, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log

        UVM_FATAL @ 3211.038633 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3211.038633 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:

  • Test chip_sw_rv_timer_systick_test has 3 failures.

    • 0.chip_sw_rv_timer_systick_test.109931603664806804462252519590182367356829735007270507509796255231415821849197
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:79f3bfe3-2a67-4054-8a51-d245b11ac003
      

    • 1.chip_sw_rv_timer_systick_test.35758769379906622381310249132298711194669377489569156119702505590123819785366
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:042845e0-26c0-4e28-9667-b62f6b64868b
      

    • ... and 1 more failures.

  • Test chip_sw_coremark has 1 failures.

    • 0.chip_sw_coremark.43652251536430680963003904571979969493460063531088647659003258368424516999081
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log

        Job ID: smart:3099a431-47ee-4a7a-8c1a-b460a9bfe5a7
      

  • Test chip_sw_ast_clk_rst_inputs has 2 failures.

    • 0.chip_sw_ast_clk_rst_inputs.2980315052396947451634512349114573932299078634733679145056389442230881515352
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:afc2cccc-5ffc-4cae-9dbc-25d638de393c
      

    • 1.chip_sw_ast_clk_rst_inputs.110105446087699083572078044426691509127964201818530118051806359481440082894708
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:c052823d-cd1b-4830-bc49-3dfb9737816d
      

  • Test chip_sw_power_virus has 2 failures.

    • 0.chip_sw_power_virus.15263170294054563944161679302666324059761336740804415610851424592902556018595
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log

        Job ID: smart:48b7bc6b-86b4-4f9b-87e4-91d0ced5c65f
      

    • 2.chip_sw_power_virus.95592085674992884275043555882049671088450847269116245297992990588597458149512
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log

        Job ID: smart:6c0962c3-9585-4914-b41c-ea94e9d9eaed
      

  • Test chip_sw_uart_tx_rx_bootstrap has 1 failures.

    • 2.chip_sw_uart_tx_rx_bootstrap.80772867913332715425061739961108274775077813985140358621642241720933649328432
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log

        Job ID: smart:ffe9e98a-df44-48dc-9441-dc05f7c7192c
      

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 6 failures:

  • Test chip_sw_lc_ctrl_rma_to_scrap has 1 failures.

    • 0.chip_sw_lc_ctrl_rma_to_scrap.42467341786773392306784226966383900276984727002898732019326258527678696736262
      Line 919, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log

        UVM_FATAL @ 3456.033732 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3456.033732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_lc_ctrl_raw_to_scrap has 1 failures.

    • 0.chip_sw_lc_ctrl_raw_to_scrap.85562090918081359049156379653753698049371094991832753164048165888579324980043
      Line 896, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log

        UVM_FATAL @ 3521.071637 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3521.071637 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_lc_ctrl_test_locked0_to_scrap has 1 failures.

    • 0.chip_sw_lc_ctrl_test_locked0_to_scrap.82687272058207182985229898924107342972525760205266271309861232575705992259320
      Line 949, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log

        UVM_FATAL @ 2869.972911 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 2869.972911 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_lc_ctrl_rand_to_scrap has 3 failures.

    • 0.chip_sw_lc_ctrl_rand_to_scrap.33606433834892292235516735846694416019869791945596789010894057975892909579248
      Line 873, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

        UVM_FATAL @ 4024.742937 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4024.742937 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_lc_ctrl_rand_to_scrap.5646437285927944547064551970435175063249744566784002952559030003315348147320
      Line 992, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

        UVM_FATAL @ 4469.694717 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4469.694717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_key_derivation_vseq] wait timeout occurred! has 5 failures:

  • Test chip_sw_keymgr_key_derivation has 3 failures.

    • 0.chip_sw_keymgr_key_derivation.4752815026585394822656902507722624560196478065253731436294987163301045043214
      Line 890, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest/run.log

        UVM_FATAL @ 10010.260001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
        UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_keymgr_key_derivation.45206145103678612836710529235663530241323906705732423811113641926241991841242
      Line 937, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest/run.log

        UVM_FATAL @ 10010.200001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
        UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test chip_sw_keymgr_key_derivation_jitter_en_reduced_freq has 1 failures.

    • 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.105878461178664335284001335408095174133121612810645792979552035720989085332782
      Line 959, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log

        UVM_FATAL @ 10010.380001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
        UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_keymgr_key_derivation_jitter_en has 1 failures.

    • 1.chip_sw_keymgr_key_derivation_jitter_en.54843149359823993487430566399922055749055170790902907250681400248491636315091
      Line 869, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @ 10010.360001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
        UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:

  • Test chip_sw_exit_test_unlocked_bootstrap has 3 failures.

    • 0.chip_sw_exit_test_unlocked_bootstrap.24170439303459926784298555874273857216131274695832924392887956101463242067776
      Line 877, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log

        UVM_FATAL @ 3523.203898 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3523.203898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_exit_test_unlocked_bootstrap.23689492662622161985171733607135011627958458055142050687035644657535568173011
      Line 890, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log

        UVM_FATAL @ 3516.295763 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3516.295763 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:

  • Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.

    • 0.chip_sw_flash_ctrl_lc_rw_en.112293585573402286117062955763734780794465948942402822899163008037162785017599
      Line 900, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log

        UVM_ERROR @ 3184.241074 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
        UVM_INFO @ 3184.241074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_flash_ctrl_lc_rw_en.65593511524243434038954605915203636043428161415518279530439916538560065130038
      Line 882, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log

        UVM_ERROR @ 2856.644150 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
        UVM_INFO @ 2856.644150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_flash_rma_unlocked_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:

  • Test chip_sw_flash_rma_unlocked has 3 failures.

    • 0.chip_sw_flash_rma_unlocked.98328862143426345270191137833787778550652584946309928307482047195569664467567
      Line 863, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log

        UVM_FATAL @ 3694.338511 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3694.338511 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_flash_rma_unlocked.40943778878204493116315569052685195996974574522144646775246400270195562852084
      Line 903, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log

        UVM_FATAL @ 3261.437001 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3261.437001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:

  • Test chip_sw_otp_ctrl_vendor_test_csr_access has 3 failures.

    • 0.chip_sw_otp_ctrl_vendor_test_csr_access.7517289531604710228008703493733819839858956172123434038891626248650273422614
      Line 908, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log

        UVM_FATAL @ 4551.554132 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4551.554132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_otp_ctrl_vendor_test_csr_access.17973181154174756161151922476124993302186047895040387151209393042302042881470
      Line 904, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log

        UVM_FATAL @ 2954.959244 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 2954.959244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:

  • Test chip_sw_lc_walkthrough_testunlocks has 3 failures.

    • 0.chip_sw_lc_walkthrough_testunlocks.76050148267148073907770916414647031167155170334325677312090970590712746589365
      Line 841, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log

        UVM_FATAL @ 3137.954431 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3137.954431 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_lc_walkthrough_testunlocks.44050993659772152967313389463819537100988340392280304431793053048313653264703
      Line 871, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log

        UVM_FATAL @ 3752.672075 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3752.672075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:

  • Test chip_sw_sysrst_ctrl_outputs has 3 failures.

    • 0.chip_sw_sysrst_ctrl_outputs.31305325960010362238505721985648610014187055355354479146780844778650845336737
      Line 921, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_sysrst_ctrl_outputs.96946177334308616265288953358489566649863138638668752336071327737046848454623
      Line 867, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

  • Test chip_sw_lc_ctrl_program_error has 3 failures.

    • 0.chip_sw_lc_ctrl_program_error.68560585499906261971893719322716141888647242582463957382951706277504909110283
      Line 903, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 14874.549384 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 14874.549384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.chip_sw_lc_ctrl_program_error.37139867504399964804227726845321650467135133436078596311739752974444005382118
      Line 934, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 15576.824360 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 15576.824360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:

  • Test chip_sw_rv_dm_access_after_wakeup has 3 failures.

    • 0.chip_sw_rv_dm_access_after_wakeup.11899761732014952363261267337877821745247581566649884173267583031705174479754
      Line 926, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log

        UVM_FATAL @ 4082.325800 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
        UVM_INFO @ 4082.325800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_rv_dm_access_after_wakeup.24518796786069522592002764008259030939880025315530081572859714779147205499778
      Line 926, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log

        UVM_FATAL @ 3424.363191 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
        UVM_INFO @ 3424.363191 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:

  • Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_debug_test_unlocked0.31710497552588498603117491528138956897190684321987423552401139570713114369716
      Line 821, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log

        UVM_FATAL @ 1659.722500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 1659.722500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_dev has 1 failures.

    • 0.rom_e2e_jtag_debug_dev.88030974252157937906487229842592706380549559855878511958308540539057645083138
      Line 857, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log

        UVM_FATAL @ 2223.383500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2223.383500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_rma has 1 failures.

    • 0.rom_e2e_jtag_debug_rma.19438169379081679038020456741186656860922795474458002598851229794494355413656
      Line 825, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log

        UVM_FATAL @ 1577.180000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 1577.180000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:

  • Test rom_e2e_static_critical has 3 failures.

    • 0.rom_e2e_static_critical.43053124880519714493894801706599590102522259113751789758789811443545724675297
      Line 928, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log

        UVM_ERROR @ 20016.709006 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
        
        UVM_INFO @ 20016.709006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.rom_e2e_static_critical.27728832621586490096321928243543613308016399428510163045930708188775684173303
      Line 1065, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log

        UVM_ERROR @ 20018.943220 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
        
        UVM_INFO @ 20018.943220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:

  • Test rom_raw_unlock has 3 failures.

    • 0.rom_raw_unlock.97827319287690853502273852514537364104879471236560893578300659802306934448286
      Line 993, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

        UVM_FATAL @ 4098.501887 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 4098.501887 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_raw_unlock.32434973175082623095874761910345242233430810719545381443978686609814053288519
      Line 1043, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

        UVM_FATAL @ 3133.953346 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
        UVM_INFO @ 3133.953346 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 2 failures:

  • Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_inject_test_unlocked0.106079158650661934718233821227524162964445556596352685899341838438705818496907
      Line 953, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log

        UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
        UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_rma has 1 failures.

    • 0.rom_e2e_jtag_inject_rma.9013403504685793541653436881592424340754570419009828197745123170578421124586
      Line 955, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log

        UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
        UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred! has 2 failures:

  • Test chip_sw_keymgr_sideload_kmac has 2 failures.

    • 1.chip_sw_keymgr_sideload_kmac.28493245989856877834847407807768456234908321923704822841506521900154281258491
      Line 922, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_kmac/latest/run.log

        UVM_FATAL @ 10010.400001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred!
        UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.chip_sw_keymgr_sideload_kmac.108434119123538297535673799913094549295101673720632413593329061269324009168391
      Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_kmac/latest/run.log

        UVM_FATAL @ 10010.380001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred!
        UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:

  • Test chip_sw_all_escalation_resets has 2 failures.

    • 53.chip_sw_all_escalation_resets.20247143627490142929937218796534814476667094183225255834469713440389786412901
      Line 884, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 2782.521010 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 2782.521010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 57.chip_sw_all_escalation_resets.14355500460059706673896586741396622573224378840059380932518380925244601307948
      Line 811, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 2643.953696 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 2643.953696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:

  • Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.

    • 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.81955509419671405287309112139377133322907399850551696615281626336433005913000
      Line 992, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log

            Offending '(pend_req[h2d.a_source].pend == 0)'
        UVM_ERROR @ 8851.524816 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
        UVM_INFO @ 8851.524816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:

  • Test rom_e2e_jtag_inject_dev has 1 failures.

    • 0.rom_e2e_jtag_inject_dev.80201512143229908549943369420573427981970169851367142355412703649817309804252
      Line 893, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log

        UVM_FATAL @ 57960.191050 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 57960.191050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:

  • Test chip_sw_power_virus has 1 failures.

    • 1.chip_sw_power_virus.83310050105323347194690614158195892210655175877047499258358182398723317988334
      Line 1245, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 5908.983291 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
        UVM_INFO @ 5908.983291 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test chip_csr_aliasing has 1 failures.

    • 2.chip_csr_aliasing.14760548531643297645730291236997937014861717668970944085834684498150676082810
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log

        Job ID: smart:8faa9cfe-a3e9-4092-8296-85fc35b376e7
      

• UVM_ERROR @ * us: (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:

  • Test chip_tap_straps_rma has 1 failures.

    • 4.chip_tap_straps_rma.30032394566094684958248005210407312539631375528498692158226234393370317150942
      Line 5944, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_rma/latest/run.log

        UVM_ERROR @ 5268.150433 us: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
        UVM_INFO @ 5268.150433 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.

    • 39.chip_sw_alert_handler_lpg_sleep_mode_alerts.42974069306733314540583951201991374419565804035206716335308254827815510634140
      Line 808, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 4140.117144 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
        UVM_INFO @ 4140.117144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• summary
• lint
• 2024.05.22_04.58.31
• 2024.05.20_04.30.47
• 2024.05.17_07.01.34
• 2024.05.15_03.27.27
• 2024.05.13_04.16.33