Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_invert_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.83	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T13,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T13,T14
1	1	Covered	T2,T13,T14

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T14
1	-	Covered	T2,T13,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T13,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T13,T14
1	1	Covered	T2,T13,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T2,T13,T14
0	0	1	Covered	T2,T13,T14
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T2,T13,T14
0	0	1	Covered	T2,T13,T14
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	104421	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	263	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	104421	0	0
T2	31326	678	0	0
T3	130520	0	0	0
T13	0	721	0	0
T14	0	712	0	0
T142	23192	0	0	0
T159	40673	0	0	0
T213	58624	0	0	0
T227	214748	0	0	0
T228	185399	0	0	0
T273	33658	0	0	0
T392	0	8219	0	0
T393	0	3956	0	0
T394	0	25378	0	0
T395	0	651	0	0
T396	0	253	0	0
T397	0	837	0	0
T423	0	481	0	0
T425	38437	0	0	0
T426	46198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	263	0	0
T2	31326	2	0	0
T3	130520	0	0	0
T13	0	2	0	0
T14	0	2	0	0
T142	23192	0	0	0
T159	40673	0	0	0
T213	58624	0	0	0
T227	214748	0	0	0
T228	185399	0	0	0
T273	33658	0	0	0
T392	0	20	0	0
T393	0	9	0	0
T394	0	62	0	0
T395	0	2	0	0
T396	0	1	0	0
T397	0	2	0	0
T423	0	1	0	0
T425	38437	0	0	0
T426	46198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T76,T79,T392

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T392,T393,T395
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	107625	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	270	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	107625	0	0
T392	649018	6394	0	0
T393	666297	5272	0	0
T394	149979	25376	0	0
T395	79422	720	0	0
T396	825332	328	0	0
T397	88880	859	0	0
T415	314807	2204	0	0
T417	82494	713	0	0
T423	56550	479	0	0
T424	49928	381	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	270	0	0
T392	649018	16	0	0
T393	666297	12	0	0
T394	149979	62	0	0
T395	79422	2	0	0
T396	825332	1	0	0
T397	88880	2	0	0
T415	314807	6	0	0
T417	82494	2	0	0
T423	56550	1	0	0
T424	49928	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T392,T427,T393

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T392,T393,T395
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	112100	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	283	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	112100	0	0
T392	649018	6483	0	0
T393	666297	3866	0	0
T394	149979	25302	0	0
T395	79422	765	0	0
T396	825332	289	0	0
T397	88880	792	0	0
T415	314807	326	0	0
T417	82494	504	0	0
T423	56550	470	0	0
T424	49928	366	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	283	0	0
T392	649018	16	0	0
T393	666297	9	0	0
T394	149979	62	0	0
T395	79422	2	0	0
T396	825332	1	0	0
T397	88880	2	0	0
T415	314807	1	0	0
T417	82494	2	0	0
T423	56550	1	0	0
T424	49928	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T11,T392,T428

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T11,T392,T393
1	1	Covered	T11,T392,T393

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T11,T392,T393
1	-	Covered	T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T11,T392,T393

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T392,T393
1	1	Covered	T11,T392,T393

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T11,T392,T393
0	0	1	Covered	T11,T392,T393
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T11,T392,T393
0	0	1	Covered	T11,T392,T393
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	109914	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	276	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	109914	0	0
T11	24176	884	0	0
T129	52510	0	0	0
T277	68999	0	0	0
T311	74520	0	0	0
T392	0	2274	0	0
T393	0	5275	0	0
T394	0	25323	0	0
T395	0	611	0	0
T396	0	261	0	0
T397	0	886	0	0
T415	0	1758	0	0
T417	0	624	0	0
T423	0	379	0	0
T429	116862	0	0	0
T430	15166	0	0	0
T431	57739	0	0	0
T432	31804	0	0	0
T433	20689	0	0	0
T434	62720	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	276	0	0
T11	24176	2	0	0
T129	52510	0	0	0
T277	68999	0	0	0
T311	74520	0	0	0
T392	0	6	0	0
T393	0	12	0	0
T394	0	62	0	0
T395	0	2	0	0
T396	0	1	0	0
T397	0	2	0	0
T415	0	5	0	0
T417	0	2	0	0
T423	0	1	0	0
T429	116862	0	0	0
T430	15166	0	0	0
T431	57739	0	0	0
T432	31804	0	0	0
T433	20689	0	0	0
T434	62720	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T435,T392,T428

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T392,T393,T395
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	109953	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	276	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	109953	0	0
T392	649018	4185	0	0
T393	666297	7093	0	0
T394	149979	25294	0	0
T395	79422	619	0	0
T396	825332	304	0	0
T397	88880	782	0	0
T415	314807	1377	0	0
T417	82494	603	0	0
T423	56550	393	0	0
T424	49928	481	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	276	0	0
T392	649018	10	0	0
T393	666297	16	0	0
T394	149979	62	0	0
T395	79422	2	0	0
T396	825332	1	0	0
T397	88880	2	0	0
T415	314807	4	0	0
T417	82494	2	0	0
T423	56550	1	0	0
T424	49928	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T3,T16

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T16
1	-	Covered	T1,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T3,T16
0	0	1	Covered	T1,T3,T16
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T3,T16
0	0	1	Covered	T1,T3,T16
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	111655	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	283	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	111655	0	0
T1	45289	624	0	0
T3	0	753	0	0
T9	0	1533	0	0
T10	0	1398	0	0
T16	0	653	0	0
T17	0	1667	0	0
T50	36724	0	0	0
T101	0	770	0	0
T102	53647	0	0	0
T103	46316	0	0	0
T104	120915	0	0	0
T105	26788	0	0	0
T106	29659	0	0	0
T107	56645	0	0	0
T108	69193	0	0	0
T109	34963	0	0	0
T392	0	2443	0	0
T393	0	1652	0	0
T422	0	728	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	283	0	0
T1	45289	2	0	0
T3	0	2	0	0
T9	0	4	0	0
T10	0	4	0	0
T16	0	2	0	0
T17	0	4	0	0
T50	36724	0	0	0
T101	0	2	0	0
T102	53647	0	0	0
T103	46316	0	0	0
T104	120915	0	0	0
T105	26788	0	0	0
T106	29659	0	0	0
T107	56645	0	0	0
T108	69193	0	0	0
T109	34963	0	0	0
T392	0	6	0	0
T393	0	4	0	0
T422	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T15,T392,T436

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T392,T393
1	1	Covered	T15,T392,T393

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T15,T392,T393
1	-	Covered	T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T15,T392,T393

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T392,T393
1	1	Covered	T15,T392,T393

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T15,T392,T393
0	0	1	Covered	T15,T392,T393
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T15,T392,T393
0	0	1	Covered	T15,T392,T393
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	110242	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	277	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	110242	0	0
T15	46789	950	0	0
T28	136038	0	0	0
T148	548186	0	0	0
T149	547234	0	0	0
T342	119678	0	0	0
T361	23854	0	0	0
T363	23088	0	0	0
T365	22344	0	0	0
T378	57028	0	0	0
T392	0	1373	0	0
T393	0	6836	0	0
T394	0	25350	0	0
T395	0	800	0	0
T396	0	345	0	0
T397	0	922	0	0
T415	0	3929	0	0
T417	0	647	0	0
T423	0	432	0	0
T437	68849	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	277	0	0
T15	46789	2	0	0
T28	136038	0	0	0
T148	548186	0	0	0
T149	547234	0	0	0
T342	119678	0	0	0
T361	23854	0	0	0
T363	23088	0	0	0
T365	22344	0	0	0
T378	57028	0	0	0
T392	0	4	0	0
T393	0	15	0	0
T394	0	62	0	0
T395	0	2	0	0
T396	0	1	0	0
T397	0	2	0	0
T415	0	11	0	0
T417	0	2	0	0
T423	0	1	0	0
T437	68849	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T12,T392,T438

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T12,T392,T393
1	1	Covered	T12,T392,T393

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T12,T392,T393
1	-	Covered	T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T12,T392,T393

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T392,T393
1	1	Covered	T12,T392,T393

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T12,T392,T393
0	0	1	Covered	T12,T392,T393
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T12,T392,T393
0	0	1	Covered	T12,T392,T393
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	100269	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	253	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	100269	0	0
T12	27434	938	0	0
T25	24102	0	0	0
T139	170795	0	0	0
T164	55999	0	0	0
T246	58461	0	0	0
T338	69905	0	0	0
T392	0	4445	0	0
T393	0	4840	0	0
T394	0	25277	0	0
T395	0	727	0	0
T396	0	274	0	0
T397	0	795	0	0
T415	0	308	0	0
T417	0	594	0	0
T423	0	416	0	0
T439	56656	0	0	0
T440	414115	0	0	0
T441	413101	0	0	0
T442	91968	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	253	0	0
T12	27434	2	0	0
T25	24102	0	0	0
T139	170795	0	0	0
T164	55999	0	0	0
T246	58461	0	0	0
T338	69905	0	0	0
T392	0	11	0	0
T393	0	11	0	0
T394	0	62	0	0
T395	0	2	0	0
T396	0	1	0	0
T397	0	2	0	0
T415	0	1	0	0
T417	0	2	0	0
T423	0	1	0	0
T439	56656	0	0	0
T440	414115	0	0	0
T441	413101	0	0	0
T442	91968	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T13,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T13,T14
1	1	Covered	T2,T13,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T13,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T13,T14
1	1	Covered	T2,T13,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T2,T13,T14
0	0	1	Covered	T2,T13,T14
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T2,T13,T14
0	0	1	Covered	T2,T13,T14
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	109614	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	277	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	109614	0	0
T2	31326	304	0	0
T3	130520	0	0	0
T13	0	468	0	0
T14	0	337	0	0
T142	23192	0	0	0
T159	40673	0	0	0
T213	58624	0	0	0
T227	214748	0	0	0
T228	185399	0	0	0
T273	33658	0	0	0
T392	0	3228	0	0
T393	0	4883	0	0
T394	0	26193	0	0
T395	0	706	0	0
T396	0	280	0	0
T397	0	837	0	0
T423	0	447	0	0
T425	38437	0	0	0
T426	46198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	277	0	0
T2	31326	1	0	0
T3	130520	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T142	23192	0	0	0
T159	40673	0	0	0
T213	58624	0	0	0
T227	214748	0	0	0
T228	185399	0	0	0
T273	33658	0	0	0
T392	0	8	0	0
T393	0	11	0	0
T394	0	64	0	0
T395	0	2	0	0
T396	0	1	0	0
T397	0	2	0	0
T423	0	1	0	0
T425	38437	0	0	0
T426	46198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T443,T392,T436

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	116082	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	292	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	116082	0	0
T392	649018	6043	0	0
T393	666297	4904	0	0
T394	149979	26200	0	0
T395	79422	687	0	0
T396	825332	242	0	0
T397	88880	861	0	0
T415	314807	3983	0	0
T417	82494	592	0	0
T423	56550	392	0	0
T424	49928	447	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	292	0	0
T392	649018	15	0	0
T393	666297	11	0	0
T394	149979	64	0	0
T395	79422	2	0	0
T396	825332	1	0	0
T397	88880	2	0	0
T415	314807	11	0	0
T417	82494	2	0	0
T423	56550	1	0	0
T424	49928	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T444,T445,T392

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	114714	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	287	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	114714	0	0
T392	649018	5652	0	0
T393	666297	5837	0	0
T394	149979	26140	0	0
T395	79422	773	0	0
T396	825332	283	0	0
T397	88880	899	0	0
T415	314807	624	0	0
T417	82494	616	0	0
T423	56550	440	0	0
T424	49928	451	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	287	0	0
T392	649018	14	0	0
T393	666297	13	0	0
T394	149979	64	0	0
T395	79422	2	0	0
T396	825332	1	0	0
T397	88880	2	0	0
T415	314807	2	0	0
T417	82494	2	0	0
T423	56550	1	0	0
T424	49928	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T11,T392,T428

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T11,T392,T393
1	1	Covered	T11,T392,T393

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T11,T392,T393

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T392,T393
1	1	Covered	T11,T392,T393

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T11,T392,T393
0	0	1	Covered	T11,T392,T393
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T11,T392,T393
0	0	1	Covered	T11,T392,T393
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	100187	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	252	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	100187	0	0
T11	24176	339	0	0
T129	52510	0	0	0
T277	68999	0	0	0
T311	74520	0	0	0
T392	0	4521	0	0
T393	0	5305	0	0
T394	0	26113	0	0
T395	0	697	0	0
T396	0	290	0	0
T397	0	899	0	0
T415	0	3591	0	0
T417	0	630	0	0
T423	0	450	0	0
T429	116862	0	0	0
T430	15166	0	0	0
T431	57739	0	0	0
T432	31804	0	0	0
T433	20689	0	0	0
T434	62720	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	252	0	0
T11	24176	1	0	0
T129	52510	0	0	0
T277	68999	0	0	0
T311	74520	0	0	0
T392	0	11	0	0
T393	0	12	0	0
T394	0	64	0	0
T395	0	2	0	0
T396	0	1	0	0
T397	0	2	0	0
T415	0	10	0	0
T417	0	2	0	0
T423	0	1	0	0
T429	116862	0	0	0
T430	15166	0	0	0
T431	57739	0	0	0
T432	31804	0	0	0
T433	20689	0	0	0
T434	62720	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T446,T392,T438

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	106204	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	266	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	106204	0	0
T392	649018	5365	0	0
T393	666297	6741	0	0
T394	149979	26190	0	0
T395	79422	728	0	0
T396	825332	318	0	0
T397	88880	837	0	0
T415	314807	960	0	0
T417	82494	519	0	0
T423	56550	465	0	0
T424	49928	477	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	266	0	0
T392	649018	13	0	0
T393	666297	15	0	0
T394	149979	64	0	0
T395	79422	2	0	0
T396	825332	1	0	0
T397	88880	2	0	0
T415	314807	3	0	0
T417	82494	2	0	0
T423	56550	1	0	0
T424	49928	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T3,T16
0	0	1	Covered	T1,T3,T16
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T3,T16
0	0	1	Covered	T1,T3,T16
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	109681	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	279	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	109681	0	0
T1	45289	248	0	0
T3	0	379	0	0
T9	0	666	0	0
T10	0	650	0	0
T16	0	277	0	0
T17	0	681	0	0
T50	36724	0	0	0
T101	0	273	0	0
T102	53647	0	0	0
T103	46316	0	0	0
T104	120915	0	0	0
T105	26788	0	0	0
T106	29659	0	0	0
T107	56645	0	0	0
T108	69193	0	0	0
T109	34963	0	0	0
T392	0	6067	0	0
T393	0	4952	0	0
T422	0	352	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	279	0	0
T1	45289	1	0	0
T3	0	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T16	0	1	0	0
T17	0	2	0	0
T50	36724	0	0	0
T101	0	1	0	0
T102	53647	0	0	0
T103	46316	0	0	0
T104	120915	0	0	0
T105	26788	0	0	0
T106	29659	0	0	0
T107	56645	0	0	0
T108	69193	0	0	0
T109	34963	0	0	0
T392	0	15	0	0
T393	0	11	0	0
T422	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T15,T392,T447

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T392,T393
1	1	Covered	T15,T392,T393

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T15,T392,T393

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T392,T393
1	1	Covered	T15,T392,T393

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T15,T392,T393
0	0	1	Covered	T15,T392,T393
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T15,T392,T393
0	0	1	Covered	T15,T392,T393
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	106773	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	268	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	106773	0	0
T15	46789	411	0	0
T28	136038	0	0	0
T148	548186	0	0	0
T149	547234	0	0	0
T342	119678	0	0	0
T361	23854	0	0	0
T363	23088	0	0	0
T365	22344	0	0	0
T378	57028	0	0	0
T392	0	4230	0	0
T393	0	8103	0	0
T394	0	26113	0	0
T395	0	672	0	0
T396	0	267	0	0
T397	0	857	0	0
T415	0	3654	0	0
T417	0	629	0	0
T423	0	428	0	0
T437	68849	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	268	0	0
T15	46789	1	0	0
T28	136038	0	0	0
T148	548186	0	0	0
T149	547234	0	0	0
T342	119678	0	0	0
T361	23854	0	0	0
T363	23088	0	0	0
T365	22344	0	0	0
T378	57028	0	0	0
T392	0	10	0	0
T393	0	19	0	0
T394	0	64	0	0
T395	0	2	0	0
T396	0	1	0	0
T397	0	2	0	0
T415	0	10	0	0
T417	0	2	0	0
T423	0	1	0	0
T437	68849	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T12,T392,T428

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T12,T392,T393
1	1	Covered	T12,T392,T393

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T12,T392,T393

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T392,T393
1	1	Covered	T12,T392,T393

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T12,T392,T393
0	0	1	Covered	T12,T392,T393
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T12,T392,T393
0	0	1	Covered	T12,T392,T393
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	99553	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	253	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	99553	0	0
T12	27434	395	0	0
T25	24102	0	0	0
T139	170795	0	0	0
T164	55999	0	0	0
T246	58461	0	0	0
T338	69905	0	0	0
T392	0	5637	0	0
T393	0	4341	0	0
T394	0	26105	0	0
T395	0	675	0	0
T396	0	264	0	0
T397	0	828	0	0
T415	0	2944	0	0
T417	0	682	0	0
T423	0	411	0	0
T439	56656	0	0	0
T440	414115	0	0	0
T441	413101	0	0	0
T442	91968	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	253	0	0
T12	27434	1	0	0
T25	24102	0	0	0
T139	170795	0	0	0
T164	55999	0	0	0
T246	58461	0	0	0
T338	69905	0	0	0
T392	0	14	0	0
T393	0	10	0	0
T394	0	64	0	0
T395	0	2	0	0
T396	0	1	0	0
T397	0	2	0	0
T415	0	8	0	0
T417	0	2	0	0
T423	0	1	0	0
T439	56656	0	0	0
T440	414115	0	0	0
T441	413101	0	0	0
T442	91968	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T444,T392,T438

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T392,T393,T395
1	1	Covered	T392,T393,T395

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T392,T393,T395
0	0	1	Covered	T392,T393,T395
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	98623	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	248	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	98623	0	0
T392	649018	3248	0	0
T393	666297	4400	0	0
T394	149979	26162	0	0
T395	79422	753	0	0
T396	825332	334	0	0
T397	88880	852	0	0
T415	314807	1006	0	0
T417	82494	618	0	0
T423	56550	438	0	0
T424	49928	412	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	248	0	0
T392	649018	8	0	0
T393	666297	10	0	0
T394	149979	64	0	0
T395	79422	2	0	0
T396	825332	1	0	0
T397	88880	2	0	0
T415	314807	3	0	0
T417	82494	2	0	0
T423	56550	1	0	0
T424	49928	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T421,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T8,T392
1	1	Covered	T7,T421,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T8,T392

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T421,T8
1	1	Covered	T7,T8,T392

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T421,T8
0	0	1	Covered	T7,T8,T392
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T421,T8
0	0	1	Covered	T7,T8,T392
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140759101	118457	0	0
DstReqKnown_A	1717037	1516204	0	0
SrcAckBusyChk_A	140759101	296	0	0
SrcBusyKnown_A	140759101	139997121	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	118457	0	0
T7	33224	269	0	0
T8	0	263	0	0
T87	41440	0	0	0
T128	58047	0	0	0
T371	37839	0	0	0
T392	0	4994	0	0
T393	0	7756	0	0
T394	0	26184	0	0
T395	0	720	0	0
T396	0	305	0	0
T397	0	824	0	0
T421	0	332	0	0
T423	0	392	0	0
T448	264716	0	0	0
T449	28065	0	0	0
T450	35801	0	0	0
T451	50546	0	0	0
T452	69624	0	0	0
T453	95023	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1717037	1516204	0	0
T4	353	189	0	0
T5	2728	2566	0	0
T6	348	185	0	0
T18	972	807	0	0
T19	928	766	0	0
T20	633	470	0	0
T46	980	818	0	0
T47	958	795	0	0
T63	519	355	0	0
T84	620	457	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	296	0	0
T7	33224	1	0	0
T8	0	1	0	0
T87	41440	0	0	0
T128	58047	0	0	0
T371	37839	0	0	0
T392	0	12	0	0
T393	0	18	0	0
T394	0	64	0	0
T395	0	2	0	0
T396	0	1	0	0
T397	0	2	0	0
T415	0	7	0	0
T423	0	1	0	0
T448	264716	0	0	0
T449	28065	0	0	0
T450	35801	0	0	0
T451	50546	0	0	0
T452	69624	0	0	0
T453	95023	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140759101	139997121	0	0
T4	18788	18170	0	0
T5	295590	295207	0	0
T6	22932	22161	0	0
T18	64680	64306	0	0
T19	83208	82746	0	0
T20	50429	49963	0	0
T46	65355	65003	0	0
T47	57598	57265	0	0
T63	37609	36892	0	0
T84	52928	52324	0	0