Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.42 91.02 80.63 89.66 92.13 80.42 84.65


Total test records in report: 1001
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T574 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.179372877 Jun 09 03:46:06 PM PDT 24 Jun 09 03:54:23 PM PDT 24 3759720036 ps
T575 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2557288809 Jun 09 03:18:48 PM PDT 24 Jun 09 03:59:40 PM PDT 24 9220085160 ps
T576 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2520938131 Jun 09 03:41:02 PM PDT 24 Jun 09 03:51:33 PM PDT 24 6813381824 ps
T378 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.922686751 Jun 09 03:26:26 PM PDT 24 Jun 09 03:34:23 PM PDT 24 5924718120 ps
T577 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.821609127 Jun 09 03:17:28 PM PDT 24 Jun 09 03:26:31 PM PDT 24 4738925540 ps
T389 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.4143558074 Jun 09 03:39:54 PM PDT 24 Jun 09 05:30:27 PM PDT 24 30771158800 ps
T578 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3170698731 Jun 09 03:41:03 PM PDT 24 Jun 09 03:49:20 PM PDT 24 3205752556 ps
T326 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1179775386 Jun 09 03:24:14 PM PDT 24 Jun 09 04:05:19 PM PDT 24 9252447038 ps
T579 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3167377656 Jun 09 03:28:03 PM PDT 24 Jun 09 03:33:10 PM PDT 24 3292369500 ps
T51 /workspace/coverage/default/0.chip_sw_gpio.2637072693 Jun 09 03:13:59 PM PDT 24 Jun 09 03:24:42 PM PDT 24 4412503224 ps
T580 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1314209491 Jun 09 03:19:24 PM PDT 24 Jun 09 03:38:56 PM PDT 24 5997990784 ps
T581 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1046364057 Jun 09 03:29:53 PM PDT 24 Jun 09 03:35:12 PM PDT 24 3027687970 ps
T582 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3470992441 Jun 09 03:37:09 PM PDT 24 Jun 09 03:40:42 PM PDT 24 2865387363 ps
T491 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.230182426 Jun 09 03:50:01 PM PDT 24 Jun 09 03:57:33 PM PDT 24 3903197560 ps
T583 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2903584911 Jun 09 03:12:09 PM PDT 24 Jun 09 03:24:35 PM PDT 24 7769103420 ps
T207 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.4031720725 Jun 09 03:13:56 PM PDT 24 Jun 09 03:24:40 PM PDT 24 4777738446 ps
T40 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.4174974200 Jun 09 03:32:10 PM PDT 24 Jun 09 03:46:26 PM PDT 24 7351253586 ps
T451 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1760815313 Jun 09 03:48:01 PM PDT 24 Jun 09 03:54:07 PM PDT 24 3573666182 ps
T108 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2818812578 Jun 09 03:35:57 PM PDT 24 Jun 09 03:52:12 PM PDT 24 7000189478 ps
T156 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3725786360 Jun 09 03:24:22 PM PDT 24 Jun 09 03:32:27 PM PDT 24 5034121916 ps
T369 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.950321184 Jun 09 03:42:11 PM PDT 24 Jun 09 03:54:24 PM PDT 24 4440468252 ps
T584 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3770006656 Jun 09 03:29:44 PM PDT 24 Jun 09 03:40:07 PM PDT 24 4758574172 ps
T585 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.798788951 Jun 09 03:12:24 PM PDT 24 Jun 09 03:16:42 PM PDT 24 2497828192 ps
T586 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.313701073 Jun 09 03:39:09 PM PDT 24 Jun 09 03:42:49 PM PDT 24 2672607928 ps
T587 /workspace/coverage/default/2.chip_sw_uart_smoketest.1170715017 Jun 09 03:42:11 PM PDT 24 Jun 09 03:47:00 PM PDT 24 3047754176 ps
T588 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1218990760 Jun 09 03:12:53 PM PDT 24 Jun 09 03:20:46 PM PDT 24 4167897132 ps
T589 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3426508941 Jun 09 03:40:01 PM PDT 24 Jun 09 03:51:48 PM PDT 24 4954335056 ps
T590 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2475980644 Jun 09 03:25:12 PM PDT 24 Jun 09 03:35:25 PM PDT 24 4033551090 ps
T259 /workspace/coverage/default/1.chip_sw_rv_timer_irq.2421016665 Jun 09 03:21:15 PM PDT 24 Jun 09 03:25:12 PM PDT 24 2910264344 ps
T591 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1208822409 Jun 09 03:20:14 PM PDT 24 Jun 09 03:51:19 PM PDT 24 15298540412 ps
T469 /workspace/coverage/default/38.chip_sw_all_escalation_resets.2306048903 Jun 09 03:45:19 PM PDT 24 Jun 09 03:55:08 PM PDT 24 4266531744 ps
T455 /workspace/coverage/default/26.chip_sw_all_escalation_resets.1072630940 Jun 09 03:46:24 PM PDT 24 Jun 09 03:56:45 PM PDT 24 5830621950 ps
T234 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1169068722 Jun 09 03:30:52 PM PDT 24 Jun 09 05:00:19 PM PDT 24 50904531725 ps
T475 /workspace/coverage/default/61.chip_sw_all_escalation_resets.454519771 Jun 09 03:46:40 PM PDT 24 Jun 09 03:56:58 PM PDT 24 4832200472 ps
T243 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1997368490 Jun 09 03:21:41 PM PDT 24 Jun 09 03:34:48 PM PDT 24 5678842140 ps
T310 /workspace/coverage/default/57.chip_sw_all_escalation_resets.2623951102 Jun 09 03:47:30 PM PDT 24 Jun 09 03:56:34 PM PDT 24 5092489224 ps
T224 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.903226961 Jun 09 03:23:21 PM PDT 24 Jun 09 03:28:17 PM PDT 24 2708522384 ps
T52 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3533987647 Jun 09 03:27:26 PM PDT 24 Jun 09 03:34:10 PM PDT 24 2885933957 ps
T252 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.427801783 Jun 09 03:40:32 PM PDT 24 Jun 09 03:54:41 PM PDT 24 6102116066 ps
T492 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3418722650 Jun 09 03:48:56 PM PDT 24 Jun 09 03:54:23 PM PDT 24 3402837712 ps
T275 /workspace/coverage/default/2.rom_e2e_shutdown_output.2512293494 Jun 09 03:41:38 PM PDT 24 Jun 09 04:32:56 PM PDT 24 26931971028 ps
T592 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.4083167551 Jun 09 03:40:06 PM PDT 24 Jun 09 03:53:53 PM PDT 24 12885987417 ps
T327 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1746484841 Jun 09 03:35:45 PM PDT 24 Jun 09 04:33:56 PM PDT 24 16110816824 ps
T356 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3556531712 Jun 09 03:12:51 PM PDT 24 Jun 09 03:19:43 PM PDT 24 3463838232 ps
T593 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3448164365 Jun 09 03:30:31 PM PDT 24 Jun 09 03:50:30 PM PDT 24 7286770916 ps
T594 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1264713697 Jun 09 03:24:30 PM PDT 24 Jun 09 03:30:44 PM PDT 24 3628194148 ps
T436 /workspace/coverage/default/13.chip_sw_all_escalation_resets.3610657916 Jun 09 03:44:24 PM PDT 24 Jun 09 03:55:23 PM PDT 24 6270256212 ps
T62 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3518423677 Jun 09 03:20:57 PM PDT 24 Jun 09 03:28:01 PM PDT 24 5660060040 ps
T595 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1399435383 Jun 09 03:13:22 PM PDT 24 Jun 09 03:51:20 PM PDT 24 32182444496 ps
T596 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4068138605 Jun 09 03:42:58 PM PDT 24 Jun 09 04:43:10 PM PDT 24 17145030600 ps
T597 /workspace/coverage/default/22.chip_sw_all_escalation_resets.2950411286 Jun 09 03:42:59 PM PDT 24 Jun 09 03:52:32 PM PDT 24 5401767550 ps
T362 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3843599513 Jun 09 03:16:50 PM PDT 24 Jun 09 03:26:17 PM PDT 24 3420249700 ps
T598 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.117880057 Jun 09 03:18:42 PM PDT 24 Jun 09 03:25:49 PM PDT 24 3678252020 ps
T460 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2937782671 Jun 09 03:50:13 PM PDT 24 Jun 09 04:00:26 PM PDT 24 5692626488 ps
T599 /workspace/coverage/default/0.rom_e2e_static_critical.2176408800 Jun 09 03:23:16 PM PDT 24 Jun 09 04:31:05 PM PDT 24 16879886960 ps
T600 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1606057804 Jun 09 03:21:19 PM PDT 24 Jun 09 04:20:15 PM PDT 24 14899935192 ps
T125 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.921483893 Jun 09 03:12:12 PM PDT 24 Jun 09 03:20:46 PM PDT 24 3855819952 ps
T276 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1101867712 Jun 09 03:17:46 PM PDT 24 Jun 09 04:39:37 PM PDT 24 17794200255 ps
T601 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.155908152 Jun 09 03:31:45 PM PDT 24 Jun 09 03:38:18 PM PDT 24 3891992592 ps
T376 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4232270305 Jun 09 03:20:11 PM PDT 24 Jun 09 03:23:38 PM PDT 24 2687509864 ps
T24 /workspace/coverage/default/1.chip_jtag_mem_access.2864509307 Jun 09 03:18:05 PM PDT 24 Jun 09 03:47:03 PM PDT 24 13249831544 ps
T602 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3462937929 Jun 09 03:28:40 PM PDT 24 Jun 09 03:39:43 PM PDT 24 4541358834 ps
T458 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4029429983 Jun 09 03:45:12 PM PDT 24 Jun 09 03:51:08 PM PDT 24 3796730280 ps
T182 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1149393720 Jun 09 03:11:44 PM PDT 24 Jun 09 03:15:23 PM PDT 24 2353187044 ps
T277 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3067110338 Jun 09 03:15:29 PM PDT 24 Jun 09 03:17:03 PM PDT 24 2112761860 ps
T10 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1213052936 Jun 09 03:17:33 PM PDT 24 Jun 09 03:22:18 PM PDT 24 2906230636 ps
T416 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.88118217 Jun 09 03:17:03 PM PDT 24 Jun 09 03:20:57 PM PDT 24 2303578942 ps
T417 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1445883322 Jun 09 03:35:29 PM PDT 24 Jun 09 03:44:10 PM PDT 24 4980559030 ps
T115 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3116804603 Jun 09 03:12:12 PM PDT 24 Jun 09 03:25:01 PM PDT 24 7002251441 ps
T304 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4018355121 Jun 09 03:12:40 PM PDT 24 Jun 09 03:26:30 PM PDT 24 8660207407 ps
T305 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1360874626 Jun 09 03:33:13 PM PDT 24 Jun 09 03:41:26 PM PDT 24 4892819240 ps
T78 /workspace/coverage/default/1.chip_sw_alert_test.537240937 Jun 09 03:23:50 PM PDT 24 Jun 09 03:28:23 PM PDT 24 2499507960 ps
T41 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.663936296 Jun 09 03:12:18 PM PDT 24 Jun 09 03:21:19 PM PDT 24 4410721125 ps
T109 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.360602852 Jun 09 03:37:41 PM PDT 24 Jun 09 04:25:08 PM PDT 24 21459799466 ps
T306 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.334622939 Jun 09 03:47:24 PM PDT 24 Jun 09 03:54:05 PM PDT 24 4061825472 ps
T130 /workspace/coverage/default/0.chip_sw_usbdev_vbus.872087369 Jun 09 03:11:07 PM PDT 24 Jun 09 03:15:27 PM PDT 24 3191968108 ps
T307 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2101383953 Jun 09 03:48:10 PM PDT 24 Jun 09 03:55:46 PM PDT 24 4118407942 ps
T126 /workspace/coverage/default/0.chip_sw_usbdev_pullup.2048925835 Jun 09 03:13:52 PM PDT 24 Jun 09 03:19:05 PM PDT 24 3288474704 ps
T314 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1927266838 Jun 09 03:12:02 PM PDT 24 Jun 09 03:31:54 PM PDT 24 8713369708 ps
T603 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.738396192 Jun 09 03:18:56 PM PDT 24 Jun 09 03:22:30 PM PDT 24 3034676512 ps
T253 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3906598629 Jun 09 03:40:38 PM PDT 24 Jun 09 03:52:28 PM PDT 24 6036972806 ps
T527 /workspace/coverage/default/47.chip_sw_all_escalation_resets.2040175938 Jun 09 03:45:43 PM PDT 24 Jun 09 03:54:25 PM PDT 24 4367973646 ps
T263 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1279133227 Jun 09 03:23:39 PM PDT 24 Jun 09 03:45:45 PM PDT 24 10664590816 ps
T368 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2307255133 Jun 09 03:13:53 PM PDT 24 Jun 09 03:17:53 PM PDT 24 2699294749 ps
T604 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.684193103 Jun 09 03:29:32 PM PDT 24 Jun 09 03:52:55 PM PDT 24 8518886340 ps
T236 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3236839099 Jun 09 03:26:37 PM PDT 24 Jun 09 03:56:31 PM PDT 24 19831476059 ps
T431 /workspace/coverage/default/0.rom_volatile_raw_unlock.3813764448 Jun 09 03:17:58 PM PDT 24 Jun 09 03:20:08 PM PDT 24 2615236866 ps
T605 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1975326495 Jun 09 03:33:11 PM PDT 24 Jun 09 04:02:57 PM PDT 24 6821609120 ps
T606 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.205445029 Jun 09 03:37:09 PM PDT 24 Jun 09 04:07:55 PM PDT 24 11321489583 ps
T225 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3655955318 Jun 09 03:31:49 PM PDT 24 Jun 09 03:36:45 PM PDT 24 2866686411 ps
T607 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1465198058 Jun 09 03:12:20 PM PDT 24 Jun 09 04:23:22 PM PDT 24 18474221080 ps
T248 /workspace/coverage/default/88.chip_sw_all_escalation_resets.4237097444 Jun 09 03:50:21 PM PDT 24 Jun 09 03:57:44 PM PDT 24 5607737034 ps
T194 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.65931937 Jun 09 03:12:21 PM PDT 24 Jun 09 03:16:58 PM PDT 24 2791338728 ps
T121 /workspace/coverage/default/0.chip_tap_straps_rma.3975690897 Jun 09 03:11:26 PM PDT 24 Jun 09 03:23:36 PM PDT 24 7240211946 ps
T167 /workspace/coverage/default/1.chip_sw_power_idle_load.1780645021 Jun 09 03:27:51 PM PDT 24 Jun 09 03:39:53 PM PDT 24 4925359400 ps
T199 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.375132290 Jun 09 03:33:40 PM PDT 24 Jun 09 03:41:45 PM PDT 24 4035987692 ps
T59 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3445843239 Jun 09 03:30:02 PM PDT 24 Jun 09 03:35:21 PM PDT 24 2952574660 ps
T122 /workspace/coverage/default/1.chip_tap_straps_rma.215533413 Jun 09 03:24:45 PM PDT 24 Jun 09 03:31:24 PM PDT 24 5154554604 ps
T299 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3362186685 Jun 09 03:19:34 PM PDT 24 Jun 09 03:38:04 PM PDT 24 7689585890 ps
T300 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1067843307 Jun 09 03:36:59 PM PDT 24 Jun 09 03:56:57 PM PDT 24 10438772716 ps
T301 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3281220000 Jun 09 03:21:45 PM PDT 24 Jun 09 03:23:22 PM PDT 24 2245706497 ps
T302 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1519038462 Jun 09 03:12:49 PM PDT 24 Jun 09 03:34:50 PM PDT 24 7913553130 ps
T608 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2795279484 Jun 09 03:13:53 PM PDT 24 Jun 09 03:17:54 PM PDT 24 2871997316 ps
T476 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3267179328 Jun 09 03:42:10 PM PDT 24 Jun 09 03:49:19 PM PDT 24 3570175256 ps
T173 /workspace/coverage/default/1.chip_sw_edn_boot_mode.3082126636 Jun 09 03:23:52 PM PDT 24 Jun 09 03:33:13 PM PDT 24 2902114200 ps
T318 /workspace/coverage/default/1.chip_sw_pattgen_ios.703809429 Jun 09 03:17:09 PM PDT 24 Jun 09 03:21:20 PM PDT 24 2331570420 ps
T255 /workspace/coverage/default/2.chip_sw_plic_sw_irq.379937012 Jun 09 03:35:06 PM PDT 24 Jun 09 03:39:11 PM PDT 24 2703580616 ps
T371 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.971543855 Jun 09 03:34:29 PM PDT 24 Jun 09 04:24:10 PM PDT 24 37706702838 ps
T452 /workspace/coverage/default/42.chip_sw_all_escalation_resets.2919245634 Jun 09 03:46:16 PM PDT 24 Jun 09 03:57:37 PM PDT 24 5175604994 ps
T46 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.787113894 Jun 09 03:34:31 PM PDT 24 Jun 09 04:27:01 PM PDT 24 20416157899 ps
T609 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2876803835 Jun 09 03:34:57 PM PDT 24 Jun 09 03:52:37 PM PDT 24 6823630920 ps
T289 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2478661752 Jun 09 03:13:02 PM PDT 24 Jun 09 03:21:13 PM PDT 24 3108609576 ps
T610 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3799878094 Jun 09 03:24:55 PM PDT 24 Jun 09 03:48:28 PM PDT 24 9532356024 ps
T466 /workspace/coverage/default/84.chip_sw_all_escalation_resets.915635929 Jun 09 03:50:51 PM PDT 24 Jun 09 03:59:33 PM PDT 24 5930996824 ps
T611 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1674558397 Jun 09 03:31:12 PM PDT 24 Jun 09 04:16:34 PM PDT 24 25678532507 ps
T245 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.477577754 Jun 09 03:20:42 PM PDT 24 Jun 09 03:49:49 PM PDT 24 11988234170 ps
T76 /workspace/coverage/default/2.chip_jtag_csr_rw.4149001136 Jun 09 03:28:39 PM PDT 24 Jun 09 03:59:51 PM PDT 24 16303021536 ps
T612 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2410247987 Jun 09 03:37:53 PM PDT 24 Jun 09 03:58:31 PM PDT 24 12558629976 ps
T613 /workspace/coverage/default/0.chip_tap_straps_dev.1312175715 Jun 09 03:11:57 PM PDT 24 Jun 09 03:13:59 PM PDT 24 2830728456 ps
T472 /workspace/coverage/default/76.chip_sw_all_escalation_resets.84172241 Jun 09 03:48:54 PM PDT 24 Jun 09 03:58:02 PM PDT 24 4647222452 ps
T614 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.929456889 Jun 09 03:44:55 PM PDT 24 Jun 09 04:23:45 PM PDT 24 11318305457 ps
T615 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1975418862 Jun 09 03:21:53 PM PDT 24 Jun 09 04:28:47 PM PDT 24 14655400920 ps
T388 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1320939511 Jun 09 03:23:43 PM PDT 24 Jun 09 03:38:59 PM PDT 24 6954684040 ps
T616 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2547116373 Jun 09 03:20:10 PM PDT 24 Jun 09 03:29:00 PM PDT 24 6983073800 ps
T514 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3598415291 Jun 09 03:39:26 PM PDT 24 Jun 09 03:50:45 PM PDT 24 6160134388 ps
T512 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.366265196 Jun 09 03:45:08 PM PDT 24 Jun 09 03:51:39 PM PDT 24 3707493896 ps
T386 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2483732604 Jun 09 03:36:12 PM PDT 24 Jun 09 03:44:40 PM PDT 24 5208621344 ps
T278 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.486421812 Jun 09 03:19:00 PM PDT 24 Jun 09 04:22:32 PM PDT 24 13808085050 ps
T141 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2450132724 Jun 09 03:35:58 PM PDT 24 Jun 09 04:07:24 PM PDT 24 23454497500 ps
T90 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3790878208 Jun 09 03:30:33 PM PDT 24 Jun 09 03:41:31 PM PDT 24 5372008409 ps
T617 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3670289495 Jun 09 03:35:08 PM PDT 24 Jun 09 04:11:36 PM PDT 24 27378579096 ps
T618 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3538953891 Jun 09 03:33:44 PM PDT 24 Jun 09 03:37:09 PM PDT 24 3220811400 ps
T264 /workspace/coverage/default/8.chip_sw_all_escalation_resets.368819170 Jun 09 03:41:17 PM PDT 24 Jun 09 03:55:16 PM PDT 24 6074153960 ps
T363 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.297443078 Jun 09 03:26:44 PM PDT 24 Jun 09 03:36:55 PM PDT 24 4853312896 ps
T430 /workspace/coverage/default/4.chip_tap_straps_dev.3558815318 Jun 09 03:40:36 PM PDT 24 Jun 09 03:52:59 PM PDT 24 6999280056 ps
T453 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2695519387 Jun 09 03:26:29 PM PDT 24 Jun 09 03:45:30 PM PDT 24 8210465320 ps
T619 /workspace/coverage/default/1.chip_sw_csrng_smoketest.195222583 Jun 09 03:27:35 PM PDT 24 Jun 09 03:32:13 PM PDT 24 2751483296 ps
T620 /workspace/coverage/default/2.chip_sw_kmac_idle.1988435468 Jun 09 03:35:23 PM PDT 24 Jun 09 03:39:45 PM PDT 24 3183036650 ps
T487 /workspace/coverage/default/44.chip_sw_all_escalation_resets.1345132203 Jun 09 03:47:13 PM PDT 24 Jun 09 03:59:14 PM PDT 24 4987848694 ps
T621 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3047419278 Jun 09 03:20:52 PM PDT 24 Jun 09 04:23:36 PM PDT 24 15719780464 ps
T622 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3794236679 Jun 09 03:37:25 PM PDT 24 Jun 09 03:42:19 PM PDT 24 2459245296 ps
T623 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.322515264 Jun 09 03:33:24 PM PDT 24 Jun 09 04:44:42 PM PDT 24 14774193124 ps
T624 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.553512295 Jun 09 03:19:06 PM PDT 24 Jun 09 03:37:39 PM PDT 24 5406021166 ps
T377 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.871516804 Jun 09 03:32:36 PM PDT 24 Jun 09 03:37:57 PM PDT 24 3133377224 ps
T195 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.618556569 Jun 09 03:30:41 PM PDT 24 Jun 09 03:34:45 PM PDT 24 3020983763 ps
T625 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2495004949 Jun 09 03:40:00 PM PDT 24 Jun 09 03:48:07 PM PDT 24 7780974996 ps
T231 /workspace/coverage/default/2.chip_jtag_mem_access.2700917899 Jun 09 03:28:33 PM PDT 24 Jun 09 03:55:35 PM PDT 24 14475114343 ps
T626 /workspace/coverage/default/0.chip_sw_aes_entropy.3898376377 Jun 09 03:13:56 PM PDT 24 Jun 09 03:18:33 PM PDT 24 2799158322 ps
T627 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3710154927 Jun 09 03:34:30 PM PDT 24 Jun 09 04:02:12 PM PDT 24 13581504526 ps
T312 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2256297971 Jun 09 03:22:21 PM PDT 24 Jun 09 03:37:32 PM PDT 24 5514490212 ps
T628 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.113565063 Jun 09 03:12:16 PM PDT 24 Jun 09 03:52:17 PM PDT 24 27352059525 ps
T629 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1403514937 Jun 09 03:44:33 PM PDT 24 Jun 09 03:52:40 PM PDT 24 5065509617 ps
T142 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2826356631 Jun 09 03:12:04 PM PDT 24 Jun 09 03:20:44 PM PDT 24 7572429578 ps
T630 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2096412683 Jun 09 03:41:11 PM PDT 24 Jun 09 04:26:21 PM PDT 24 13313280332 ps
T343 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.527787361 Jun 09 03:39:39 PM PDT 24 Jun 09 03:50:49 PM PDT 24 4152101072 ps
T11 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2504420360 Jun 09 03:38:10 PM PDT 24 Jun 09 04:07:16 PM PDT 24 21198391830 ps
T160 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3007960556 Jun 09 03:36:13 PM PDT 24 Jun 09 03:48:58 PM PDT 24 5591804076 ps
T335 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3324233417 Jun 09 03:32:38 PM PDT 24 Jun 09 03:39:49 PM PDT 24 18525379076 ps
T60 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1891852053 Jun 09 03:18:28 PM PDT 24 Jun 09 03:23:33 PM PDT 24 3468287880 ps
T235 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3176314128 Jun 09 03:15:26 PM PDT 24 Jun 09 03:52:47 PM PDT 24 25984765362 ps
T631 /workspace/coverage/default/68.chip_sw_all_escalation_resets.3296473028 Jun 09 03:47:16 PM PDT 24 Jun 09 03:55:40 PM PDT 24 5432295544 ps
T632 /workspace/coverage/default/0.chip_sw_kmac_smoketest.2427152054 Jun 09 03:16:59 PM PDT 24 Jun 09 03:22:03 PM PDT 24 3125319416 ps
T147 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.998645541 Jun 09 03:13:06 PM PDT 24 Jun 09 03:19:24 PM PDT 24 2984861515 ps
T633 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.559436517 Jun 09 03:49:13 PM PDT 24 Jun 09 03:54:01 PM PDT 24 3602814980 ps
T634 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.228766435 Jun 09 03:42:44 PM PDT 24 Jun 09 03:58:54 PM PDT 24 14178996086 ps
T372 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3465810268 Jun 09 03:27:59 PM PDT 24 Jun 09 03:32:34 PM PDT 24 3034748423 ps
T635 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.199664997 Jun 09 03:19:29 PM PDT 24 Jun 09 04:27:26 PM PDT 24 14361735752 ps
T176 /workspace/coverage/default/0.chip_plic_all_irqs_0.3189936612 Jun 09 03:11:22 PM PDT 24 Jun 09 03:27:16 PM PDT 24 5337978568 ps
T210 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.285510744 Jun 09 03:13:18 PM PDT 24 Jun 09 03:25:45 PM PDT 24 5565909256 ps
T84 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1349695727 Jun 09 03:24:49 PM PDT 24 Jun 09 03:36:04 PM PDT 24 9853255041 ps
T636 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3127588272 Jun 09 03:38:44 PM PDT 24 Jun 09 04:43:47 PM PDT 24 24933728409 ps
T637 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1414076074 Jun 09 03:22:35 PM PDT 24 Jun 09 03:43:27 PM PDT 24 7826192168 ps
T524 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2710363070 Jun 09 03:44:37 PM PDT 24 Jun 09 03:54:04 PM PDT 24 5198136038 ps
T265 /workspace/coverage/default/39.chip_sw_all_escalation_resets.358932714 Jun 09 03:44:57 PM PDT 24 Jun 09 03:54:23 PM PDT 24 5382047880 ps
T638 /workspace/coverage/default/1.chip_sw_csrng_kat_test.738911854 Jun 09 03:28:11 PM PDT 24 Jun 09 03:32:10 PM PDT 24 2829466092 ps
T639 /workspace/coverage/default/0.chip_sw_aes_idle.1590264753 Jun 09 03:11:29 PM PDT 24 Jun 09 03:15:27 PM PDT 24 2703318140 ps
T640 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3723074611 Jun 09 03:39:20 PM PDT 24 Jun 09 03:58:05 PM PDT 24 7347918115 ps
T319 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3338211958 Jun 09 03:14:16 PM PDT 24 Jun 09 06:57:26 PM PDT 24 77357124170 ps
T520 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630704481 Jun 09 03:49:02 PM PDT 24 Jun 09 03:55:08 PM PDT 24 4361353722 ps
T641 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2479340671 Jun 09 03:42:24 PM PDT 24 Jun 09 04:12:16 PM PDT 24 7770212404 ps
T642 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2268869737 Jun 09 03:10:56 PM PDT 24 Jun 09 03:15:18 PM PDT 24 3148411842 ps
T643 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3957720015 Jun 09 03:41:20 PM PDT 24 Jun 09 03:49:36 PM PDT 24 5235901936 ps
T644 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2685884816 Jun 09 03:46:26 PM PDT 24 Jun 09 03:53:01 PM PDT 24 4473355552 ps
T645 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3169632334 Jun 09 03:22:25 PM PDT 24 Jun 09 03:29:35 PM PDT 24 5909205608 ps
T646 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.285520711 Jun 09 03:21:12 PM PDT 24 Jun 09 04:18:06 PM PDT 24 13023003542 ps
T79 /workspace/coverage/default/2.chip_sw_alert_test.2090163868 Jun 09 03:34:24 PM PDT 24 Jun 09 03:40:26 PM PDT 24 3606065540 ps
T25 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2541049541 Jun 09 03:15:01 PM PDT 24 Jun 09 04:02:00 PM PDT 24 12693100056 ps
T493 /workspace/coverage/default/78.chip_sw_all_escalation_resets.3975656504 Jun 09 03:48:28 PM PDT 24 Jun 09 03:59:11 PM PDT 24 4972822088 ps
T315 /workspace/coverage/default/0.chip_sw_power_idle_load.3776072770 Jun 09 03:15:42 PM PDT 24 Jun 09 03:28:09 PM PDT 24 3835420282 ps
T21 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1106608441 Jun 09 03:11:59 PM PDT 24 Jun 09 03:18:20 PM PDT 24 4689433176 ps
T647 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3652247695 Jun 09 03:13:04 PM PDT 24 Jun 09 03:20:42 PM PDT 24 5542398296 ps
T648 /workspace/coverage/default/2.chip_sw_aes_enc.3905279228 Jun 09 03:32:49 PM PDT 24 Jun 09 03:36:41 PM PDT 24 2689511092 ps
T649 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1906981155 Jun 09 03:43:18 PM PDT 24 Jun 09 03:53:50 PM PDT 24 3799932824 ps
T650 /workspace/coverage/default/1.chip_sw_aes_entropy.1996109654 Jun 09 03:22:57 PM PDT 24 Jun 09 03:26:31 PM PDT 24 2827540692 ps
T651 /workspace/coverage/default/45.chip_sw_all_escalation_resets.2480688520 Jun 09 03:46:48 PM PDT 24 Jun 09 03:58:07 PM PDT 24 4690132720 ps
T652 /workspace/coverage/default/2.chip_sw_example_concurrency.554095771 Jun 09 03:28:32 PM PDT 24 Jun 09 03:31:45 PM PDT 24 3113694364 ps
T653 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1580264480 Jun 09 03:23:53 PM PDT 24 Jun 09 03:28:06 PM PDT 24 2915337312 ps
T503 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4173175435 Jun 09 03:48:19 PM PDT 24 Jun 09 03:54:14 PM PDT 24 3471786550 ps
T654 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2103975367 Jun 09 03:31:30 PM PDT 24 Jun 09 03:35:43 PM PDT 24 3094968960 ps
T655 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.520815977 Jun 09 03:31:22 PM PDT 24 Jun 09 03:40:03 PM PDT 24 6175321701 ps
T148 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3429615439 Jun 09 03:35:14 PM PDT 24 Jun 09 03:39:32 PM PDT 24 3453853083 ps
T656 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2743587877 Jun 09 03:20:48 PM PDT 24 Jun 09 03:32:10 PM PDT 24 3919511460 ps
T290 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1909286334 Jun 09 03:25:55 PM PDT 24 Jun 09 03:39:05 PM PDT 24 4609565333 ps
T85 /workspace/coverage/default/1.chip_sw_kmac_app_rom.1995403313 Jun 09 03:26:20 PM PDT 24 Jun 09 03:31:11 PM PDT 24 3147917030 ps
T196 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2722779919 Jun 09 03:37:59 PM PDT 24 Jun 09 03:43:06 PM PDT 24 2350982617 ps
T657 /workspace/coverage/default/2.chip_sw_example_manufacturer.2662793539 Jun 09 03:29:08 PM PDT 24 Jun 09 03:33:43 PM PDT 24 2934329856 ps
T479 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3326058106 Jun 09 03:44:43 PM PDT 24 Jun 09 03:53:54 PM PDT 24 3953990428 ps
T513 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1869536537 Jun 09 03:47:23 PM PDT 24 Jun 09 03:56:48 PM PDT 24 5464208642 ps
T170 /workspace/coverage/default/2.chip_plic_all_irqs_10.3165329895 Jun 09 03:37:05 PM PDT 24 Jun 09 03:50:35 PM PDT 24 3496105870 ps
T658 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2789183600 Jun 09 03:41:36 PM PDT 24 Jun 09 03:52:59 PM PDT 24 4345511050 ps
T488 /workspace/coverage/default/40.chip_sw_all_escalation_resets.209669792 Jun 09 03:47:23 PM PDT 24 Jun 09 03:59:40 PM PDT 24 6203120104 ps
T659 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3434178713 Jun 09 03:34:37 PM PDT 24 Jun 09 03:41:43 PM PDT 24 5883359302 ps
T660 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3904660971 Jun 09 03:21:04 PM PDT 24 Jun 09 04:25:29 PM PDT 24 14838802764 ps
T504 /workspace/coverage/default/49.chip_sw_all_escalation_resets.3864043189 Jun 09 03:46:29 PM PDT 24 Jun 09 03:57:25 PM PDT 24 5816715882 ps
T661 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.220644505 Jun 09 03:13:09 PM PDT 24 Jun 09 03:16:31 PM PDT 24 3033409116 ps
T662 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4264748430 Jun 09 03:21:30 PM PDT 24 Jun 09 03:41:26 PM PDT 24 5580736712 ps
T382 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3335720367 Jun 09 03:46:07 PM PDT 24 Jun 09 03:54:10 PM PDT 24 3945533592 ps
T663 /workspace/coverage/default/1.chip_sw_hmac_enc.1557486200 Jun 09 03:28:41 PM PDT 24 Jun 09 03:32:53 PM PDT 24 2848020548 ps
T664 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3052406339 Jun 09 03:22:16 PM PDT 24 Jun 09 03:33:37 PM PDT 24 5217652250 ps
T665 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3585436174 Jun 09 03:10:40 PM PDT 24 Jun 09 03:19:10 PM PDT 24 4268198084 ps
T171 /workspace/coverage/default/1.chip_plic_all_irqs_10.3310964633 Jun 09 03:27:39 PM PDT 24 Jun 09 03:38:23 PM PDT 24 3889577730 ps
T507 /workspace/coverage/default/89.chip_sw_all_escalation_resets.218958979 Jun 09 03:50:20 PM PDT 24 Jun 09 03:59:04 PM PDT 24 4129107312 ps
T291 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3908793353 Jun 09 03:34:26 PM PDT 24 Jun 09 03:44:24 PM PDT 24 4292092966 ps
T666 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.204527909 Jun 09 03:24:29 PM PDT 24 Jun 09 03:34:03 PM PDT 24 5107030560 ps
T208 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.429632482 Jun 09 03:30:11 PM PDT 24 Jun 09 03:41:01 PM PDT 24 3759729380 ps
T667 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3104055159 Jun 09 03:24:05 PM PDT 24 Jun 09 03:49:06 PM PDT 24 12644709950 ps
T668 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3040986757 Jun 09 03:13:03 PM PDT 24 Jun 09 03:29:27 PM PDT 24 6810683968 ps
T669 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3852581161 Jun 09 03:44:59 PM PDT 24 Jun 09 03:50:49 PM PDT 24 3318921482 ps
T670 /workspace/coverage/default/2.chip_tap_straps_dev.3838982230 Jun 09 03:35:29 PM PDT 24 Jun 09 03:40:42 PM PDT 24 3593517951 ps
T353 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3258977312 Jun 09 03:35:10 PM PDT 24 Jun 09 04:03:56 PM PDT 24 7910754700 ps
T671 /workspace/coverage/default/0.chip_sw_hmac_enc.2342499721 Jun 09 03:14:04 PM PDT 24 Jun 09 03:18:14 PM PDT 24 2552143996 ps
T197 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3671295428 Jun 09 03:18:53 PM PDT 24 Jun 09 04:44:45 PM PDT 24 42514378080 ps
T80 /workspace/coverage/default/0.chip_sw_alert_test.3185470369 Jun 09 03:12:09 PM PDT 24 Jun 09 03:18:06 PM PDT 24 3495291912 ps
T672 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3640533393 Jun 09 03:33:16 PM PDT 24 Jun 09 03:56:42 PM PDT 24 5256687326 ps
T673 /workspace/coverage/default/0.chip_sw_aon_timer_irq.2898546503 Jun 09 03:13:04 PM PDT 24 Jun 09 03:20:56 PM PDT 24 4155022504 ps
T674 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2628248982 Jun 09 03:33:29 PM PDT 24 Jun 09 04:31:29 PM PDT 24 14543469746 ps
T675 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3769508875 Jun 09 03:13:36 PM PDT 24 Jun 09 03:25:41 PM PDT 24 4185091976 ps
T676 /workspace/coverage/default/0.chip_sw_example_rom.857262796 Jun 09 03:11:16 PM PDT 24 Jun 09 03:13:23 PM PDT 24 2653720896 ps
T266 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4036952668 Jun 09 03:14:27 PM PDT 24 Jun 09 03:22:07 PM PDT 24 4390980130 ps
T677 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.447958823 Jun 09 03:30:13 PM PDT 24 Jun 09 04:49:59 PM PDT 24 49513547015 ps
T360 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1689254091 Jun 09 03:13:54 PM PDT 24 Jun 09 03:27:03 PM PDT 24 3708108420 ps
T678 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2835912755 Jun 09 03:26:27 PM PDT 24 Jun 09 04:32:18 PM PDT 24 24764995185 ps
T679 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2945974112 Jun 09 03:29:02 PM PDT 24 Jun 09 03:41:18 PM PDT 24 3866933214 ps
T680 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3869818710 Jun 09 03:19:44 PM PDT 24 Jun 09 04:23:03 PM PDT 24 14729047100 ps
T681 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2637876083 Jun 09 03:13:42 PM PDT 24 Jun 09 03:25:59 PM PDT 24 5574211292 ps
T116 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2081014241 Jun 09 03:24:28 PM PDT 24 Jun 09 03:39:28 PM PDT 24 8399914020 ps
T682 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.824494799 Jun 09 03:41:18 PM PDT 24 Jun 09 03:50:29 PM PDT 24 4434179780 ps
T157 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.675301943 Jun 09 03:35:21 PM PDT 24 Jun 09 03:42:53 PM PDT 24 5335422786 ps
T683 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3721981682 Jun 09 03:20:29 PM PDT 24 Jun 09 04:04:56 PM PDT 24 32419013832 ps
T684 /workspace/coverage/default/1.chip_sw_hmac_oneshot.886639366 Jun 09 03:23:49 PM PDT 24 Jun 09 03:28:44 PM PDT 24 2759537108 ps
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