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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.42 91.02 80.63 89.66 92.13 80.42 84.65


Total test records in report: 1001
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T685 /workspace/coverage/default/0.chip_sw_flash_crash_alert.1212801289 Jun 09 03:12:23 PM PDT 24 Jun 09 03:21:31 PM PDT 24 4532076576 ps
T132 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1002334582 Jun 09 03:44:36 PM PDT 24 Jun 09 03:51:04 PM PDT 24 3893366624 ps
T118 /workspace/coverage/default/4.chip_tap_straps_rma.1875952240 Jun 09 03:41:51 PM PDT 24 Jun 09 03:44:52 PM PDT 24 2419693097 ps
T686 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.981214762 Jun 09 03:19:05 PM PDT 24 Jun 09 03:23:18 PM PDT 24 3340831636 ps
T687 /workspace/coverage/default/1.chip_sw_edn_sw_mode.1546536452 Jun 09 03:24:08 PM PDT 24 Jun 09 03:51:00 PM PDT 24 5792034056 ps
T509 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423039296 Jun 09 03:45:12 PM PDT 24 Jun 09 03:54:04 PM PDT 24 3994510660 ps
T249 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4144182405 Jun 09 03:18:19 PM PDT 24 Jun 09 04:38:48 PM PDT 24 17623130920 ps
T279 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.522880565 Jun 09 03:16:38 PM PDT 24 Jun 09 03:30:31 PM PDT 24 5986423402 ps
T149 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2499806577 Jun 09 03:31:05 PM PDT 24 Jun 09 03:39:25 PM PDT 24 9652712273 ps
T48 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2361272554 Jun 09 03:13:06 PM PDT 24 Jun 09 04:01:26 PM PDT 24 12586717936 ps
T282 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3783905183 Jun 09 03:51:05 PM PDT 24 Jun 09 03:57:54 PM PDT 24 4393712058 ps
T133 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1632982748 Jun 09 03:46:40 PM PDT 24 Jun 09 03:52:43 PM PDT 24 4325556264 ps
T283 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2987334123 Jun 09 03:33:24 PM PDT 24 Jun 09 04:03:43 PM PDT 24 7881357860 ps
T284 /workspace/coverage/default/1.chip_sw_uart_tx_rx.3768718363 Jun 09 03:17:33 PM PDT 24 Jun 09 03:27:27 PM PDT 24 4659491644 ps
T285 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2846359518 Jun 09 03:19:08 PM PDT 24 Jun 09 04:31:38 PM PDT 24 14733553502 ps
T119 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3657013857 Jun 09 03:11:58 PM PDT 24 Jun 09 03:24:00 PM PDT 24 7955768879 ps
T286 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2611857761 Jun 09 03:11:21 PM PDT 24 Jun 09 03:22:39 PM PDT 24 4651240544 ps
T688 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2965105489 Jun 09 03:42:19 PM PDT 24 Jun 09 03:55:22 PM PDT 24 11258670031 ps
T320 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1757506065 Jun 09 03:11:08 PM PDT 24 Jun 09 06:23:35 PM PDT 24 64427111773 ps
T689 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1857979082 Jun 09 03:20:49 PM PDT 24 Jun 09 03:32:03 PM PDT 24 3918650220 ps
T690 /workspace/coverage/default/2.rom_e2e_asm_init_prod.2947796795 Jun 09 03:46:37 PM PDT 24 Jun 09 04:33:55 PM PDT 24 14313104520 ps
T691 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.535838386 Jun 09 03:20:42 PM PDT 24 Jun 09 03:42:52 PM PDT 24 9348235470 ps
T692 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3853504069 Jun 09 03:31:49 PM PDT 24 Jun 09 04:29:04 PM PDT 24 14502878201 ps
T8 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1406549129 Jun 09 03:13:41 PM PDT 24 Jun 09 03:21:33 PM PDT 24 4483716660 ps
T418 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2927796007 Jun 09 03:42:20 PM PDT 24 Jun 09 04:06:19 PM PDT 24 8164181380 ps
T419 /workspace/coverage/default/1.chip_sw_aes_idle.2969343567 Jun 09 03:22:00 PM PDT 24 Jun 09 03:26:07 PM PDT 24 2707024094 ps
T420 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2595456275 Jun 09 03:46:38 PM PDT 24 Jun 09 03:53:02 PM PDT 24 3657170668 ps
T421 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.222021293 Jun 09 03:50:05 PM PDT 24 Jun 09 03:56:06 PM PDT 24 3847513960 ps
T422 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3604785823 Jun 09 03:41:11 PM PDT 24 Jun 09 03:48:09 PM PDT 24 4932424981 ps
T373 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.4286656161 Jun 09 03:18:51 PM PDT 24 Jun 09 06:33:40 PM PDT 24 63823499491 ps
T423 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2280713668 Jun 09 03:14:59 PM PDT 24 Jun 09 03:33:38 PM PDT 24 7058840055 ps
T424 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3111527021 Jun 09 03:29:07 PM PDT 24 Jun 09 03:40:27 PM PDT 24 3568654160 ps
T425 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.123498901 Jun 09 03:36:57 PM PDT 24 Jun 09 03:50:26 PM PDT 24 4795522430 ps
T521 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2845287702 Jun 09 03:50:21 PM PDT 24 Jun 09 03:58:04 PM PDT 24 3312832808 ps
T505 /workspace/coverage/default/43.chip_sw_all_escalation_resets.3783317923 Jun 09 03:46:23 PM PDT 24 Jun 09 03:54:44 PM PDT 24 4630139620 ps
T693 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3579101008 Jun 09 03:11:40 PM PDT 24 Jun 09 03:33:47 PM PDT 24 14246840691 ps
T694 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2420270336 Jun 09 03:41:32 PM PDT 24 Jun 09 03:47:02 PM PDT 24 3220241744 ps
T120 /workspace/coverage/default/1.chip_tap_straps_testunlock0.3457162466 Jun 09 03:25:28 PM PDT 24 Jun 09 03:30:08 PM PDT 24 3505491728 ps
T695 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1277438188 Jun 09 03:21:29 PM PDT 24 Jun 09 04:25:03 PM PDT 24 14821223680 ps
T158 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1112399224 Jun 09 03:12:19 PM PDT 24 Jun 09 03:20:33 PM PDT 24 5854389220 ps
T696 /workspace/coverage/default/0.chip_sw_aes_masking_off.2279963692 Jun 09 03:14:30 PM PDT 24 Jun 09 03:20:39 PM PDT 24 3109487495 ps
T345 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.473529215 Jun 09 03:32:56 PM PDT 24 Jun 09 03:49:51 PM PDT 24 4702214740 ps
T697 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2433665585 Jun 09 03:39:28 PM PDT 24 Jun 09 04:10:11 PM PDT 24 13766190915 ps
T698 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.616890431 Jun 09 03:20:09 PM PDT 24 Jun 09 04:10:25 PM PDT 24 11467302362 ps
T501 /workspace/coverage/default/12.chip_sw_all_escalation_resets.3380901081 Jun 09 03:41:59 PM PDT 24 Jun 09 03:55:19 PM PDT 24 5636245350 ps
T516 /workspace/coverage/default/93.chip_sw_all_escalation_resets.1532041185 Jun 09 03:51:50 PM PDT 24 Jun 09 04:02:14 PM PDT 24 5579466220 ps
T699 /workspace/coverage/default/1.chip_sw_kmac_idle.871037522 Jun 09 03:24:29 PM PDT 24 Jun 09 03:29:11 PM PDT 24 2963673940 ps
T700 /workspace/coverage/default/1.rom_e2e_asm_init_dev.3441989970 Jun 09 03:33:03 PM PDT 24 Jun 09 04:41:08 PM PDT 24 14920584759 ps
T209 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3547506076 Jun 09 03:12:06 PM PDT 24 Jun 09 03:24:44 PM PDT 24 5032333886 ps
T214 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2741701277 Jun 09 03:18:22 PM PDT 24 Jun 09 03:33:09 PM PDT 24 7920305962 ps
T522 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1330486423 Jun 09 03:42:47 PM PDT 24 Jun 09 03:50:06 PM PDT 24 3930254332 ps
T701 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3563513648 Jun 09 03:40:49 PM PDT 24 Jun 09 03:51:08 PM PDT 24 4046348088 ps
T702 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.4239010649 Jun 09 03:29:06 PM PDT 24 Jun 09 03:38:01 PM PDT 24 6472081112 ps
T703 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2709184645 Jun 09 03:24:11 PM PDT 24 Jun 09 03:29:55 PM PDT 24 4062008280 ps
T704 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.172508695 Jun 09 03:33:05 PM PDT 24 Jun 09 04:53:24 PM PDT 24 23343221238 ps
T340 /workspace/coverage/default/2.chip_sw_pattgen_ios.2841252644 Jun 09 03:28:49 PM PDT 24 Jun 09 03:34:14 PM PDT 24 3437474110 ps
T184 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3834911078 Jun 09 03:33:52 PM PDT 24 Jun 09 03:37:25 PM PDT 24 2633986584 ps
T705 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.446375012 Jun 09 03:28:18 PM PDT 24 Jun 09 03:39:23 PM PDT 24 5132216794 ps
T706 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2833776009 Jun 09 03:31:32 PM PDT 24 Jun 09 03:34:55 PM PDT 24 2888710668 ps
T528 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2652527926 Jun 09 03:45:38 PM PDT 24 Jun 09 03:51:15 PM PDT 24 3876861270 ps
T707 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2771232701 Jun 09 03:20:29 PM PDT 24 Jun 09 04:32:19 PM PDT 24 14023133718 ps
T708 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.775766050 Jun 09 03:11:35 PM PDT 24 Jun 09 03:19:08 PM PDT 24 9782988448 ps
T709 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2991191132 Jun 09 03:30:59 PM PDT 24 Jun 09 03:55:45 PM PDT 24 8570936384 ps
T193 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1210016135 Jun 09 03:11:44 PM PDT 24 Jun 09 03:17:28 PM PDT 24 4030233341 ps
T710 /workspace/coverage/default/1.chip_tap_straps_prod.2990014576 Jun 09 03:26:35 PM PDT 24 Jun 09 03:29:19 PM PDT 24 2387304787 ps
T711 /workspace/coverage/default/2.chip_sw_example_rom.2069864108 Jun 09 03:28:40 PM PDT 24 Jun 09 03:31:05 PM PDT 24 3002658412 ps
T12 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.118335231 Jun 09 03:18:14 PM PDT 24 Jun 09 03:22:30 PM PDT 24 2604286772 ps
T403 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3706112018 Jun 09 03:47:36 PM PDT 24 Jun 09 03:56:23 PM PDT 24 6067447592 ps
T404 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2838057572 Jun 09 03:30:39 PM PDT 24 Jun 09 03:41:27 PM PDT 24 4292309965 ps
T405 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1721916053 Jun 09 03:19:42 PM PDT 24 Jun 09 03:41:14 PM PDT 24 6268925817 ps
T172 /workspace/coverage/default/0.chip_plic_all_irqs_10.1207196267 Jun 09 03:13:01 PM PDT 24 Jun 09 03:20:46 PM PDT 24 3483313800 ps
T406 /workspace/coverage/default/0.chip_sw_example_manufacturer.2356920729 Jun 09 03:11:11 PM PDT 24 Jun 09 03:15:04 PM PDT 24 2514177512 ps
T407 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1462847884 Jun 09 03:16:52 PM PDT 24 Jun 09 03:41:51 PM PDT 24 6956075992 ps
T408 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2856477770 Jun 09 03:33:03 PM PDT 24 Jun 09 03:37:13 PM PDT 24 3059309990 ps
T409 /workspace/coverage/default/2.chip_tap_straps_testunlock0.2701580428 Jun 09 03:34:54 PM PDT 24 Jun 09 03:43:01 PM PDT 24 5057101446 ps
T410 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3194590484 Jun 09 03:40:07 PM PDT 24 Jun 09 03:45:16 PM PDT 24 3340170592 ps
T712 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2216438799 Jun 09 03:23:16 PM PDT 24 Jun 09 03:27:28 PM PDT 24 2690097430 ps
T713 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3484737219 Jun 09 03:13:13 PM PDT 24 Jun 09 03:22:20 PM PDT 24 3854388540 ps
T489 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.891569978 Jun 09 03:45:36 PM PDT 24 Jun 09 03:54:30 PM PDT 24 3506178184 ps
T714 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.416871830 Jun 09 03:36:41 PM PDT 24 Jun 09 03:51:08 PM PDT 24 7569805798 ps
T715 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1258592848 Jun 09 03:12:45 PM PDT 24 Jun 09 03:20:21 PM PDT 24 5933553870 ps
T716 /workspace/coverage/default/0.rom_e2e_asm_init_rma.1130008629 Jun 09 03:17:56 PM PDT 24 Jun 09 04:16:43 PM PDT 24 14835740454 ps
T717 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3427245282 Jun 09 03:14:03 PM PDT 24 Jun 09 03:21:51 PM PDT 24 6529968624 ps
T718 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2560946172 Jun 09 03:27:42 PM PDT 24 Jun 09 03:37:38 PM PDT 24 4676737520 ps
T719 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2934948058 Jun 09 03:35:06 PM PDT 24 Jun 09 03:44:15 PM PDT 24 6711612452 ps
T720 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.588776975 Jun 09 03:33:39 PM PDT 24 Jun 09 03:50:15 PM PDT 24 7765489198 ps
T721 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1813051461 Jun 09 03:41:47 PM PDT 24 Jun 09 03:49:20 PM PDT 24 6925819020 ps
T722 /workspace/coverage/default/0.chip_tap_straps_prod.2261333962 Jun 09 03:12:00 PM PDT 24 Jun 09 03:14:26 PM PDT 24 2356647893 ps
T723 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1397445474 Jun 09 03:25:13 PM PDT 24 Jun 09 03:35:41 PM PDT 24 4256561392 ps
T724 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2287430127 Jun 09 03:32:00 PM PDT 24 Jun 09 03:52:43 PM PDT 24 6720248380 ps
T725 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1797434855 Jun 09 03:32:14 PM PDT 24 Jun 09 03:38:42 PM PDT 24 5012515114 ps
T726 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2019621925 Jun 09 03:41:04 PM PDT 24 Jun 09 04:05:18 PM PDT 24 8169613864 ps
T250 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3329531788 Jun 09 03:20:08 PM PDT 24 Jun 09 04:50:10 PM PDT 24 22934867560 ps
T36 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1012736669 Jun 09 03:32:18 PM PDT 24 Jun 09 03:37:43 PM PDT 24 2948647751 ps
T727 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2534987874 Jun 09 03:24:12 PM PDT 24 Jun 09 03:28:28 PM PDT 24 2881224921 ps
T91 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2769278183 Jun 09 03:18:39 PM PDT 24 Jun 09 03:27:59 PM PDT 24 3841638594 ps
T728 /workspace/coverage/default/1.chip_sw_aes_enc.4020812398 Jun 09 03:23:08 PM PDT 24 Jun 09 03:27:41 PM PDT 24 3145593420 ps
T427 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.448557886 Jun 09 03:38:31 PM PDT 24 Jun 09 03:47:16 PM PDT 24 4905043386 ps
T729 /workspace/coverage/default/2.chip_sw_aes_idle.4045689922 Jun 09 03:32:13 PM PDT 24 Jun 09 03:35:30 PM PDT 24 2697498520 ps
T129 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1322630430 Jun 09 03:42:14 PM PDT 24 Jun 09 03:45:21 PM PDT 24 3067960567 ps
T730 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3049049798 Jun 09 03:21:58 PM PDT 24 Jun 09 03:27:15 PM PDT 24 3748999548 ps
T731 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.957818337 Jun 09 03:13:34 PM PDT 24 Jun 09 03:23:31 PM PDT 24 6154492236 ps
T732 /workspace/coverage/default/0.chip_sw_kmac_app_rom.2836564730 Jun 09 03:14:20 PM PDT 24 Jun 09 03:17:20 PM PDT 24 2292322280 ps
T733 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3377515989 Jun 09 03:12:21 PM PDT 24 Jun 09 03:32:32 PM PDT 24 6086990989 ps
T734 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.55393660 Jun 09 03:33:29 PM PDT 24 Jun 09 03:39:31 PM PDT 24 2847628104 ps
T735 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3107001937 Jun 09 03:41:16 PM PDT 24 Jun 09 03:54:27 PM PDT 24 12976322799 ps
T201 /workspace/coverage/default/2.chip_plic_all_irqs_20.1399861764 Jun 09 03:38:43 PM PDT 24 Jun 09 03:51:58 PM PDT 24 5369989000 ps
T736 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.4091294380 Jun 09 03:31:29 PM PDT 24 Jun 09 03:48:23 PM PDT 24 4932680446 ps
T9 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3010800812 Jun 09 03:37:57 PM PDT 24 Jun 09 03:47:49 PM PDT 24 3848942204 ps
T200 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3566407008 Jun 09 03:17:48 PM PDT 24 Jun 09 04:49:32 PM PDT 24 43605023852 ps
T737 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3302068831 Jun 09 03:23:58 PM PDT 24 Jun 09 03:33:05 PM PDT 24 5705645106 ps
T237 /workspace/coverage/default/0.chip_sw_flash_init.465493512 Jun 09 03:12:39 PM PDT 24 Jun 09 03:42:57 PM PDT 24 17231944111 ps
T443 /workspace/coverage/default/17.chip_sw_all_escalation_resets.998421207 Jun 09 03:42:35 PM PDT 24 Jun 09 03:53:26 PM PDT 24 5518380872 ps
T738 /workspace/coverage/default/0.chip_sw_edn_kat.2619020099 Jun 09 03:14:13 PM PDT 24 Jun 09 03:25:33 PM PDT 24 3541876432 ps
T739 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.123257965 Jun 09 03:11:53 PM PDT 24 Jun 09 03:28:27 PM PDT 24 6125025152 ps
T740 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1018583279 Jun 09 03:41:12 PM PDT 24 Jun 09 03:51:32 PM PDT 24 3915055000 ps
T741 /workspace/coverage/default/4.chip_sw_all_escalation_resets.2316863800 Jun 09 03:42:35 PM PDT 24 Jun 09 03:52:05 PM PDT 24 4720171118 ps
T742 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3980537206 Jun 09 03:32:09 PM PDT 24 Jun 09 04:37:27 PM PDT 24 13851504725 ps
T743 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1161375708 Jun 09 03:32:51 PM PDT 24 Jun 09 03:50:28 PM PDT 24 8702756723 ps
T110 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2179470457 Jun 09 03:12:52 PM PDT 24 Jun 09 03:24:39 PM PDT 24 5857728865 ps
T63 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1404917588 Jun 09 03:12:45 PM PDT 24 Jun 09 03:23:58 PM PDT 24 6552997664 ps
T744 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.320960332 Jun 09 03:42:23 PM PDT 24 Jun 09 03:54:41 PM PDT 24 3815595058 ps
T65 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1776524253 Jun 09 03:21:41 PM PDT 24 Jun 09 03:28:00 PM PDT 24 3987868690 ps
T745 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1385056267 Jun 09 03:30:52 PM PDT 24 Jun 09 03:36:45 PM PDT 24 3694956060 ps
T746 /workspace/coverage/default/1.chip_sw_hmac_multistream.3194924243 Jun 09 03:28:32 PM PDT 24 Jun 09 03:57:04 PM PDT 24 6418165248 ps
T470 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2132696013 Jun 09 03:47:44 PM PDT 24 Jun 09 03:53:55 PM PDT 24 3561418110 ps
T747 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3610052256 Jun 09 03:28:32 PM PDT 24 Jun 09 03:37:26 PM PDT 24 3574305336 ps
T748 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1454128321 Jun 09 03:24:37 PM PDT 24 Jun 09 03:37:09 PM PDT 24 8215040978 ps
T749 /workspace/coverage/default/86.chip_sw_all_escalation_resets.372547658 Jun 09 03:49:55 PM PDT 24 Jun 09 03:57:39 PM PDT 24 4516695672 ps
T750 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3329329878 Jun 09 03:18:57 PM PDT 24 Jun 09 04:30:44 PM PDT 24 13692864072 ps
T49 /workspace/coverage/default/0.chip_sw_usbdev_config_host.488814998 Jun 09 03:13:09 PM PDT 24 Jun 09 03:47:09 PM PDT 24 7867647448 ps
T366 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2690897957 Jun 09 03:30:32 PM PDT 24 Jun 09 03:39:59 PM PDT 24 3664082822 ps
T480 /workspace/coverage/default/15.chip_sw_all_escalation_resets.3351892672 Jun 09 03:42:50 PM PDT 24 Jun 09 03:54:23 PM PDT 24 5512452000 ps
T751 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.757708958 Jun 09 03:42:38 PM PDT 24 Jun 09 03:55:49 PM PDT 24 6726656328 ps
T752 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.4047679452 Jun 09 03:30:15 PM PDT 24 Jun 09 06:27:00 PM PDT 24 64626864430 ps
T753 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4003375993 Jun 09 03:48:28 PM PDT 24 Jun 09 03:55:38 PM PDT 24 3570514712 ps
T337 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2738679695 Jun 09 03:15:07 PM PDT 24 Jun 09 03:45:18 PM PDT 24 14726369706 ps
T754 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2475155202 Jun 09 03:19:20 PM PDT 24 Jun 09 03:28:07 PM PDT 24 3728406932 ps
T511 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3464831748 Jun 09 03:23:18 PM PDT 24 Jun 09 03:30:56 PM PDT 24 3709432180 ps
T437 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.672438665 Jun 09 03:46:21 PM PDT 24 Jun 09 03:52:58 PM PDT 24 3206430080 ps
T755 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2942515044 Jun 09 03:28:56 PM PDT 24 Jun 09 03:33:18 PM PDT 24 2921929896 ps
T161 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4207543763 Jun 09 03:24:06 PM PDT 24 Jun 09 03:36:41 PM PDT 24 6591950904 ps
T483 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2577946881 Jun 09 03:50:22 PM PDT 24 Jun 09 03:57:40 PM PDT 24 3947953392 ps
T756 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4130773309 Jun 09 03:11:52 PM PDT 24 Jun 09 04:06:34 PM PDT 24 22843130646 ps
T66 /workspace/coverage/default/2.chip_sw_spi_device_tpm.2903313037 Jun 09 03:29:26 PM PDT 24 Jun 09 03:36:10 PM PDT 24 2984491534 ps
T757 /workspace/coverage/default/2.chip_sw_aes_entropy.437173807 Jun 09 03:34:31 PM PDT 24 Jun 09 03:37:52 PM PDT 24 3401884300 ps
T251 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.89192608 Jun 09 03:21:54 PM PDT 24 Jun 09 05:18:10 PM PDT 24 22475340434 ps
T758 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.917200566 Jun 09 03:30:38 PM PDT 24 Jun 09 03:42:44 PM PDT 24 7005284470 ps
T759 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3987003874 Jun 09 03:33:07 PM PDT 24 Jun 09 07:05:31 PM PDT 24 255801411092 ps
T760 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2982579814 Jun 09 03:29:35 PM PDT 24 Jun 09 04:18:40 PM PDT 24 15509159072 ps
T164 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.711324220 Jun 09 03:27:15 PM PDT 24 Jun 09 04:09:04 PM PDT 24 18823696081 ps
T523 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3280591075 Jun 09 03:50:30 PM PDT 24 Jun 09 03:57:10 PM PDT 24 4296771224 ps
T761 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.620150325 Jun 09 03:11:37 PM PDT 24 Jun 09 03:19:55 PM PDT 24 4650936348 ps
T762 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.922910976 Jun 09 03:22:45 PM PDT 24 Jun 09 04:22:34 PM PDT 24 17012422960 ps
T763 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3989363969 Jun 09 03:11:45 PM PDT 24 Jun 09 03:16:26 PM PDT 24 3776314063 ps
T764 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2475396929 Jun 09 03:13:26 PM PDT 24 Jun 09 03:46:32 PM PDT 24 9892258264 ps
T765 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3401339771 Jun 09 03:23:54 PM PDT 24 Jun 09 03:31:18 PM PDT 24 5260538456 ps
T766 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1614668980 Jun 09 03:12:15 PM PDT 24 Jun 09 03:31:38 PM PDT 24 7174171192 ps
T767 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.649675967 Jun 09 03:13:22 PM PDT 24 Jun 09 03:57:34 PM PDT 24 13615349340 ps
T768 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4087185404 Jun 09 03:31:42 PM PDT 24 Jun 09 03:56:21 PM PDT 24 10323109916 ps
T525 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2158561925 Jun 09 03:48:13 PM PDT 24 Jun 09 03:56:17 PM PDT 24 3982274520 ps
T769 /workspace/coverage/default/16.chip_sw_all_escalation_resets.213470913 Jun 09 03:42:39 PM PDT 24 Jun 09 03:51:25 PM PDT 24 4902308130 ps
T770 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4160469540 Jun 09 03:43:15 PM PDT 24 Jun 09 04:39:28 PM PDT 24 14245907871 ps
T771 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.4033566477 Jun 09 03:13:33 PM PDT 24 Jun 09 03:20:36 PM PDT 24 4168604891 ps
T772 /workspace/coverage/default/0.chip_sw_example_flash.443287996 Jun 09 03:13:01 PM PDT 24 Jun 09 03:17:57 PM PDT 24 3545095730 ps
T47 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1453777139 Jun 09 03:12:09 PM PDT 24 Jun 09 04:13:43 PM PDT 24 20223452999 ps
T773 /workspace/coverage/default/2.chip_sival_flash_info_access.3687942792 Jun 09 03:29:31 PM PDT 24 Jun 09 03:36:29 PM PDT 24 3005328000 ps
T211 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2516460650 Jun 09 03:21:20 PM PDT 24 Jun 09 03:37:39 PM PDT 24 5997962744 ps
T774 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1455070609 Jun 09 03:33:04 PM PDT 24 Jun 09 03:51:29 PM PDT 24 7021347791 ps
T775 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3028498586 Jun 09 03:11:20 PM PDT 24 Jun 09 03:23:56 PM PDT 24 6266319752 ps
T776 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.4062920786 Jun 09 03:39:20 PM PDT 24 Jun 09 03:48:27 PM PDT 24 3527094752 ps
T777 /workspace/coverage/default/0.rom_e2e_asm_init_dev.1318425969 Jun 09 03:19:31 PM PDT 24 Jun 09 04:22:16 PM PDT 24 14469083031 ps
T494 /workspace/coverage/default/90.chip_sw_all_escalation_resets.419336183 Jun 09 03:50:40 PM PDT 24 Jun 09 04:00:53 PM PDT 24 5593481428 ps
T226 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.529100747 Jun 09 03:31:53 PM PDT 24 Jun 09 03:42:10 PM PDT 24 5131368578 ps
T778 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1285523697 Jun 09 03:20:55 PM PDT 24 Jun 09 04:23:06 PM PDT 24 10880419440 ps
T779 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2531756609 Jun 09 03:12:07 PM PDT 24 Jun 09 03:20:40 PM PDT 24 4999957100 ps
T780 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.4119379017 Jun 09 03:13:24 PM PDT 24 Jun 09 03:41:36 PM PDT 24 7464807664 ps
T781 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.640171000 Jun 09 03:20:29 PM PDT 24 Jun 09 03:35:00 PM PDT 24 5083709200 ps
T782 /workspace/coverage/default/0.chip_sw_kmac_idle.2677041645 Jun 09 03:11:36 PM PDT 24 Jun 09 03:15:24 PM PDT 24 3031797536 ps
T783 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.434114449 Jun 09 03:31:52 PM PDT 24 Jun 09 03:39:37 PM PDT 24 3536066104 ps
T163 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2225773827 Jun 09 03:16:56 PM PDT 24 Jun 09 03:38:21 PM PDT 24 9651658280 ps
T500 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2092880886 Jun 09 03:46:10 PM PDT 24 Jun 09 03:54:02 PM PDT 24 3711086000 ps
T784 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1293380784 Jun 09 03:41:15 PM PDT 24 Jun 09 03:45:11 PM PDT 24 2913433620 ps
T785 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.691417885 Jun 09 03:14:20 PM PDT 24 Jun 09 03:49:47 PM PDT 24 7946520324 ps
T786 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3670128876 Jun 09 03:22:11 PM PDT 24 Jun 09 05:02:08 PM PDT 24 22418603748 ps
T787 /workspace/coverage/default/67.chip_sw_all_escalation_resets.4094645089 Jun 09 03:48:45 PM PDT 24 Jun 09 03:59:55 PM PDT 24 6556343720 ps
T471 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3641742516 Jun 09 03:44:15 PM PDT 24 Jun 09 03:51:03 PM PDT 24 3403962076 ps
T788 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3794601239 Jun 09 03:14:36 PM PDT 24 Jun 09 03:17:47 PM PDT 24 2887114685 ps
T37 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.473025265 Jun 09 03:16:36 PM PDT 24 Jun 09 03:20:53 PM PDT 24 3000346243 ps
T26 /workspace/coverage/default/0.chip_jtag_csr_rw.3290460845 Jun 09 03:04:20 PM PDT 24 Jun 09 03:32:06 PM PDT 24 13790737968 ps
T789 /workspace/coverage/default/0.chip_sw_edn_sw_mode.1500518589 Jun 09 03:13:03 PM PDT 24 Jun 09 03:48:36 PM PDT 24 7610975456 ps
T790 /workspace/coverage/default/2.chip_sw_aes_smoketest.2013553609 Jun 09 03:39:03 PM PDT 24 Jun 09 03:45:22 PM PDT 24 3165713444 ps
T791 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1309327575 Jun 09 03:17:26 PM PDT 24 Jun 09 07:08:55 PM PDT 24 77782889229 ps
T518 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1860067165 Jun 09 03:43:50 PM PDT 24 Jun 09 03:50:38 PM PDT 24 3722114632 ps
T792 /workspace/coverage/default/0.chip_sw_otbn_randomness.146109848 Jun 09 03:13:47 PM PDT 24 Jun 09 03:28:31 PM PDT 24 6170534040 ps
T793 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.83622734 Jun 09 03:18:54 PM PDT 24 Jun 09 04:43:27 PM PDT 24 21762943173 ps
T432 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1340659428 Jun 09 03:30:58 PM PDT 24 Jun 09 03:32:47 PM PDT 24 2060386857 ps
T794 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.692868400 Jun 09 03:38:59 PM PDT 24 Jun 09 03:43:01 PM PDT 24 2487793540 ps
T795 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.227452083 Jun 09 03:42:52 PM PDT 24 Jun 09 04:53:04 PM PDT 24 20889042376 ps
T796 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.385482701 Jun 09 03:36:18 PM PDT 24 Jun 09 03:47:06 PM PDT 24 4179349700 ps
T797 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.893719887 Jun 09 03:12:33 PM PDT 24 Jun 09 03:20:06 PM PDT 24 4934349330 ps
T798 /workspace/coverage/default/2.chip_sw_csrng_smoketest.886775046 Jun 09 03:39:12 PM PDT 24 Jun 09 03:44:52 PM PDT 24 2360976724 ps
T387 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3550757375 Jun 09 03:26:05 PM PDT 24 Jun 09 03:28:34 PM PDT 24 2529867152 ps
T482 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3028709314 Jun 09 03:51:20 PM PDT 24 Jun 09 03:56:56 PM PDT 24 3782070136 ps
T433 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1153218360 Jun 09 03:19:27 PM PDT 24 Jun 09 03:22:40 PM PDT 24 2955025087 ps
T799 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4240791539 Jun 09 03:28:22 PM PDT 24 Jun 09 03:33:05 PM PDT 24 3205483288 ps
T800 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2333170899 Jun 09 03:22:04 PM PDT 24 Jun 09 03:30:32 PM PDT 24 4588740120 ps
T496 /workspace/coverage/default/48.chip_sw_all_escalation_resets.4232841799 Jun 09 03:46:37 PM PDT 24 Jun 09 03:54:46 PM PDT 24 4902410344 ps
T801 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.147708181 Jun 09 03:33:18 PM PDT 24 Jun 09 04:34:37 PM PDT 24 11057227586 ps
T515 /workspace/coverage/default/81.chip_sw_all_escalation_resets.7571107 Jun 09 03:49:04 PM PDT 24 Jun 09 03:56:36 PM PDT 24 5696831514 ps
T802 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3133444149 Jun 09 03:32:10 PM PDT 24 Jun 09 03:42:13 PM PDT 24 5249537004 ps
T803 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3718153228 Jun 09 03:17:24 PM PDT 24 Jun 09 03:23:53 PM PDT 24 5603221618 ps
T804 /workspace/coverage/default/80.chip_sw_all_escalation_resets.3806599844 Jun 09 03:50:07 PM PDT 24 Jun 09 04:00:37 PM PDT 24 6107401032 ps
T177 /workspace/coverage/default/1.chip_plic_all_irqs_0.4068548709 Jun 09 03:25:43 PM PDT 24 Jun 09 03:42:46 PM PDT 24 6308868114 ps
T805 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2264724231 Jun 09 03:14:05 PM PDT 24 Jun 09 03:19:33 PM PDT 24 2964453244 ps
T296 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1276007752 Jun 09 03:14:56 PM PDT 24 Jun 09 03:19:22 PM PDT 24 2270725717 ps
T806 /workspace/coverage/default/1.rom_e2e_shutdown_output.1906399176 Jun 09 03:31:42 PM PDT 24 Jun 09 04:19:16 PM PDT 24 22043742968 ps
T807 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1121345798 Jun 09 03:13:22 PM PDT 24 Jun 09 03:23:26 PM PDT 24 4268729840 ps
T808 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1585006145 Jun 09 03:18:12 PM PDT 24 Jun 09 03:43:56 PM PDT 24 9384947296 ps
T809 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.992890421 Jun 09 03:26:43 PM PDT 24 Jun 09 03:46:10 PM PDT 24 7353164468 ps
T810 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.948545425 Jun 09 03:24:41 PM PDT 24 Jun 09 03:59:46 PM PDT 24 10195860472 ps
T811 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2506867980 Jun 09 03:11:01 PM PDT 24 Jun 09 03:31:59 PM PDT 24 6916224866 ps
T812 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3368779992 Jun 09 03:19:10 PM PDT 24 Jun 09 03:45:41 PM PDT 24 8527626372 ps
T813 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3312562108 Jun 09 03:49:03 PM PDT 24 Jun 09 03:56:03 PM PDT 24 4382612252 ps
T814 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1071025102 Jun 09 03:34:06 PM PDT 24 Jun 09 04:01:35 PM PDT 24 9254735288 ps
T815 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2676871715 Jun 09 03:43:38 PM PDT 24 Jun 09 04:46:19 PM PDT 24 18170860700 ps
T816 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3777879139 Jun 09 03:19:59 PM PDT 24 Jun 09 04:18:39 PM PDT 24 14251945092 ps
T817 /workspace/coverage/default/1.chip_tap_straps_dev.3802637410 Jun 09 03:28:30 PM PDT 24 Jun 09 03:46:49 PM PDT 24 10466228272 ps
T818 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2786291937 Jun 09 03:40:03 PM PDT 24 Jun 09 03:46:12 PM PDT 24 5474955784 ps
T497 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.987957398 Jun 09 03:44:44 PM PDT 24 Jun 09 03:52:43 PM PDT 24 3019197736 ps
T819 /workspace/coverage/default/0.rom_e2e_smoke.1176412287 Jun 09 03:16:27 PM PDT 24 Jun 09 04:16:45 PM PDT 24 13690652148 ps
T227 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1270177404 Jun 09 03:13:26 PM PDT 24 Jun 09 03:22:29 PM PDT 24 4828201388 ps
T820 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2095802569 Jun 09 03:13:43 PM PDT 24 Jun 09 03:25:27 PM PDT 24 5503648355 ps
T821 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1515374612 Jun 09 03:31:29 PM PDT 24 Jun 09 03:53:00 PM PDT 24 6847346312 ps
T822 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2608504036 Jun 09 03:17:39 PM PDT 24 Jun 09 03:29:43 PM PDT 24 5821289800 ps
T53 /workspace/coverage/default/1.chip_sw_gpio.3426837645 Jun 09 03:18:31 PM PDT 24 Jun 09 03:27:39 PM PDT 24 4118663940 ps
T823 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1604498320 Jun 09 03:33:43 PM PDT 24 Jun 09 03:55:43 PM PDT 24 7020512152 ps
T824 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3463277212 Jun 09 03:11:05 PM PDT 24 Jun 09 03:16:01 PM PDT 24 7437532960 ps
T825 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.256395234 Jun 09 03:17:32 PM PDT 24 Jun 09 03:22:24 PM PDT 24 6395675520 ps
T826 /workspace/coverage/default/3.chip_tap_straps_prod.2951722120 Jun 09 03:39:30 PM PDT 24 Jun 09 04:04:27 PM PDT 24 12747345525 ps
T827 /workspace/coverage/default/2.chip_sw_hmac_enc.1231243530 Jun 09 03:34:42 PM PDT 24 Jun 09 03:40:24 PM PDT 24 2806817630 ps
T13 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.4124296927 Jun 09 03:32:17 PM PDT 24 Jun 09 03:37:05 PM PDT 24 2808320300 ps
T828 /workspace/coverage/default/2.rom_e2e_asm_init_dev.2970021476 Jun 09 03:45:01 PM PDT 24 Jun 09 04:39:18 PM PDT 24 13662233015 ps
T829 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.406522652 Jun 09 03:20:40 PM PDT 24 Jun 09 03:41:15 PM PDT 24 11854342719 ps
T830 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3546973855 Jun 09 03:19:13 PM PDT 24 Jun 09 04:23:52 PM PDT 24 14602144300 ps
T831 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.165551977 Jun 09 03:15:07 PM PDT 24 Jun 09 03:24:33 PM PDT 24 4069868450 ps
T478 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3635623027 Jun 09 03:45:21 PM PDT 24 Jun 09 03:53:19 PM PDT 24 3879980882 ps
T832 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4200026453 Jun 09 03:26:14 PM PDT 24 Jun 09 04:00:08 PM PDT 24 12873940188 ps
T297 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2088392481 Jun 09 03:26:42 PM PDT 24 Jun 09 03:31:51 PM PDT 24 3081545364 ps
T833 /workspace/coverage/default/1.chip_sw_hmac_smoketest.3512203495 Jun 09 03:28:55 PM PDT 24 Jun 09 03:35:18 PM PDT 24 3558298274 ps
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