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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.42 91.02 80.63 89.66 92.13 80.42 84.65


Total test records in report: 1001
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T834 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1126695690 Jun 09 03:51:13 PM PDT 24 Jun 09 03:56:24 PM PDT 24 3557989370 ps
T835 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2847295737 Jun 09 03:14:42 PM PDT 24 Jun 09 04:29:42 PM PDT 24 24173539965 ps
T836 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3939274456 Jun 09 03:23:10 PM PDT 24 Jun 09 03:34:27 PM PDT 24 5649089556 ps
T338 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3293004695 Jun 09 03:33:14 PM PDT 24 Jun 09 04:01:02 PM PDT 24 13422129382 ps
T837 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2196478154 Jun 09 03:25:31 PM PDT 24 Jun 09 04:06:32 PM PDT 24 10953016096 ps
T350 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2214625707 Jun 09 03:16:27 PM PDT 24 Jun 09 03:58:26 PM PDT 24 14750453163 ps
T838 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3027803365 Jun 09 03:42:17 PM PDT 24 Jun 09 03:50:14 PM PDT 24 4517608609 ps
T839 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.490884701 Jun 09 03:39:41 PM PDT 24 Jun 09 03:43:53 PM PDT 24 2239517060 ps
T840 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2023069648 Jun 09 03:40:13 PM PDT 24 Jun 09 03:44:34 PM PDT 24 3179898780 ps
T841 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2848019663 Jun 09 03:41:16 PM PDT 24 Jun 09 04:02:43 PM PDT 24 14453965139 ps
T402 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4270265185 Jun 09 03:13:11 PM PDT 24 Jun 09 03:19:31 PM PDT 24 3804819056 ps
T842 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3002639424 Jun 09 03:23:52 PM PDT 24 Jun 09 03:26:48 PM PDT 24 2826330680 ps
T843 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2637983142 Jun 09 03:19:51 PM PDT 24 Jun 09 05:07:03 PM PDT 24 22301533524 ps
T331 /workspace/coverage/default/0.chip_sw_power_sleep_load.2336826606 Jun 09 03:13:59 PM PDT 24 Jun 09 03:27:15 PM PDT 24 10168363258 ps
T180 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2450038132 Jun 09 03:17:08 PM PDT 24 Jun 09 06:15:19 PM PDT 24 58877513935 ps
T844 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3808757522 Jun 09 03:22:28 PM PDT 24 Jun 09 03:38:07 PM PDT 24 11040309880 ps
T845 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.950685561 Jun 09 03:26:06 PM PDT 24 Jun 09 03:34:59 PM PDT 24 6442361704 ps
T846 /workspace/coverage/default/3.chip_tap_straps_rma.4014541639 Jun 09 03:41:49 PM PDT 24 Jun 09 03:48:54 PM PDT 24 5177108721 ps
T847 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.351514483 Jun 09 03:20:02 PM PDT 24 Jun 09 03:30:41 PM PDT 24 3825039286 ps
T848 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2148055211 Jun 09 03:43:23 PM PDT 24 Jun 09 03:55:38 PM PDT 24 3968890480 ps
T341 /workspace/coverage/default/0.chip_sw_pattgen_ios.3714962927 Jun 09 03:11:01 PM PDT 24 Jun 09 03:15:19 PM PDT 24 3724982320 ps
T849 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4213806934 Jun 09 03:13:50 PM PDT 24 Jun 09 03:20:44 PM PDT 24 18513882140 ps
T850 /workspace/coverage/default/0.rom_keymgr_functest.3389996513 Jun 09 03:17:31 PM PDT 24 Jun 09 03:30:09 PM PDT 24 5279833198 ps
T851 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3639947163 Jun 09 03:14:08 PM PDT 24 Jun 09 03:32:09 PM PDT 24 6810876420 ps
T852 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.693201384 Jun 09 03:35:33 PM PDT 24 Jun 09 03:43:41 PM PDT 24 4294450032 ps
T853 /workspace/coverage/default/0.chip_sw_edn_auto_mode.3411877059 Jun 09 03:12:34 PM PDT 24 Jun 09 03:45:21 PM PDT 24 6910692884 ps
T854 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.472139722 Jun 09 03:49:24 PM PDT 24 Jun 09 03:55:40 PM PDT 24 3831804140 ps
T855 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3547283103 Jun 09 03:22:51 PM PDT 24 Jun 09 07:12:37 PM PDT 24 256187187206 ps
T856 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3757013 Jun 09 03:29:13 PM PDT 24 Jun 09 03:33:20 PM PDT 24 2294688200 ps
T484 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3115822527 Jun 09 03:48:07 PM PDT 24 Jun 09 03:53:26 PM PDT 24 3482633176 ps
T857 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4021077105 Jun 09 03:31:03 PM PDT 24 Jun 09 03:55:34 PM PDT 24 10648011442 ps
T858 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.792815172 Jun 09 03:11:53 PM PDT 24 Jun 09 03:27:26 PM PDT 24 7967008008 ps
T352 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1120186874 Jun 09 03:13:15 PM PDT 24 Jun 09 03:50:48 PM PDT 24 12127921064 ps
T859 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4016342688 Jun 09 03:28:11 PM PDT 24 Jun 09 03:40:01 PM PDT 24 5072997690 ps
T517 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.772069387 Jun 09 03:48:16 PM PDT 24 Jun 09 03:54:56 PM PDT 24 3224454824 ps
T467 /workspace/coverage/default/72.chip_sw_all_escalation_resets.2829468795 Jun 09 03:48:32 PM PDT 24 Jun 09 03:59:13 PM PDT 24 4649153200 ps
T860 /workspace/coverage/default/1.chip_sw_edn_kat.1581131732 Jun 09 03:24:33 PM PDT 24 Jun 09 03:35:27 PM PDT 24 3142720052 ps
T861 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3239459848 Jun 09 03:19:23 PM PDT 24 Jun 09 04:21:58 PM PDT 24 13765033470 ps
T379 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1711460502 Jun 09 03:36:16 PM PDT 24 Jun 09 03:44:55 PM PDT 24 5687164416 ps
T54 /workspace/coverage/default/2.chip_sw_gpio.2660752716 Jun 09 03:29:01 PM PDT 24 Jun 09 03:38:38 PM PDT 24 4215384742 ps
T862 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2320213933 Jun 09 03:36:01 PM PDT 24 Jun 09 03:42:48 PM PDT 24 3675741636 ps
T332 /workspace/coverage/default/1.chip_sw_power_sleep_load.769620302 Jun 09 03:27:09 PM PDT 24 Jun 09 03:37:27 PM PDT 24 10150268200 ps
T863 /workspace/coverage/default/0.chip_sw_hmac_oneshot.3769816239 Jun 09 03:12:32 PM PDT 24 Jun 09 03:19:11 PM PDT 24 3499528500 ps
T864 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1598275357 Jun 09 03:20:34 PM PDT 24 Jun 09 04:55:15 PM PDT 24 22013551219 ps
T865 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1961792655 Jun 09 03:41:56 PM PDT 24 Jun 09 04:00:43 PM PDT 24 8796133681 ps
T393 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3697005267 Jun 09 03:47:58 PM PDT 24 Jun 09 03:54:39 PM PDT 24 3508433576 ps
T866 /workspace/coverage/default/0.chip_sw_example_concurrency.1323536789 Jun 09 03:13:19 PM PDT 24 Jun 09 03:18:51 PM PDT 24 3427760170 ps
T508 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1131756226 Jun 09 03:43:40 PM PDT 24 Jun 09 03:57:19 PM PDT 24 6425414976 ps
T867 /workspace/coverage/default/1.rom_e2e_asm_init_rma.3063373051 Jun 09 03:34:37 PM PDT 24 Jun 09 04:33:33 PM PDT 24 14555357948 ps
T868 /workspace/coverage/default/2.chip_sw_kmac_app_rom.770953257 Jun 09 03:34:09 PM PDT 24 Jun 09 03:38:45 PM PDT 24 2945148728 ps
T869 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3883524893 Jun 09 03:32:58 PM PDT 24 Jun 09 03:51:41 PM PDT 24 6314250659 ps
T870 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3592502820 Jun 09 03:10:15 PM PDT 24 Jun 09 03:12:30 PM PDT 24 2930342567 ps
T871 /workspace/coverage/default/2.chip_sw_kmac_smoketest.1522973043 Jun 09 03:38:45 PM PDT 24 Jun 09 03:42:52 PM PDT 24 2329379552 ps
T872 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1174236059 Jun 09 03:31:45 PM PDT 24 Jun 09 03:35:48 PM PDT 24 2603556504 ps
T873 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2530632159 Jun 09 03:21:18 PM PDT 24 Jun 09 03:23:30 PM PDT 24 2812693274 ps
T874 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.4125843774 Jun 09 03:21:29 PM PDT 24 Jun 09 04:56:09 PM PDT 24 22599053252 ps
T875 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.973544785 Jun 09 03:19:03 PM PDT 24 Jun 09 04:09:16 PM PDT 24 10749179941 ps
T876 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.36837439 Jun 09 03:20:52 PM PDT 24 Jun 09 03:22:22 PM PDT 24 2315360737 ps
T877 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.910397199 Jun 09 03:43:47 PM PDT 24 Jun 09 04:44:07 PM PDT 24 14854941076 ps
T878 /workspace/coverage/default/2.chip_tap_straps_prod.3584552254 Jun 09 03:36:01 PM PDT 24 Jun 09 03:45:45 PM PDT 24 5891552188 ps
T15 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1865006746 Jun 09 03:26:20 PM PDT 24 Jun 09 04:00:43 PM PDT 24 23834865022 ps
T879 /workspace/coverage/default/0.chip_sw_hmac_multistream.1612182044 Jun 09 03:12:41 PM PDT 24 Jun 09 03:41:55 PM PDT 24 7064657904 ps
T495 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3268290101 Jun 09 03:41:18 PM PDT 24 Jun 09 03:55:59 PM PDT 24 5520755856 ps
T880 /workspace/coverage/default/0.chip_sw_csrng_smoketest.358653968 Jun 09 03:16:19 PM PDT 24 Jun 09 03:20:26 PM PDT 24 2709167720 ps
T881 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1028537613 Jun 09 03:39:00 PM PDT 24 Jun 09 03:45:14 PM PDT 24 6685515760 ps
T882 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3586779219 Jun 09 03:35:42 PM PDT 24 Jun 09 03:44:31 PM PDT 24 3640946792 ps
T280 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2277915489 Jun 09 03:39:55 PM PDT 24 Jun 09 03:42:11 PM PDT 24 2941840562 ps
T50 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2461649070 Jun 09 03:14:28 PM PDT 24 Jun 09 05:11:35 PM PDT 24 31779832174 ps
T883 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2265704082 Jun 09 03:36:53 PM PDT 24 Jun 09 03:40:58 PM PDT 24 2972295082 ps
T884 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.208893501 Jun 09 03:21:36 PM PDT 24 Jun 09 04:33:25 PM PDT 24 14714744898 ps
T383 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2516631597 Jun 09 03:49:28 PM PDT 24 Jun 09 03:59:19 PM PDT 24 4105288064 ps
T212 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1503845818 Jun 09 03:30:05 PM PDT 24 Jun 09 03:42:09 PM PDT 24 5047752536 ps
T465 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2546635394 Jun 09 03:47:25 PM PDT 24 Jun 09 03:53:25 PM PDT 24 3849388296 ps
T885 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.418642024 Jun 09 03:32:52 PM PDT 24 Jun 09 03:40:08 PM PDT 24 4613448966 ps
T202 /workspace/coverage/default/1.chip_plic_all_irqs_20.3941415096 Jun 09 03:26:17 PM PDT 24 Jun 09 03:38:28 PM PDT 24 4245617508 ps
T886 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1623105451 Jun 09 03:13:45 PM PDT 24 Jun 09 04:49:59 PM PDT 24 26331728312 ps
T887 /workspace/coverage/default/1.chip_sw_example_concurrency.1379000846 Jun 09 03:17:46 PM PDT 24 Jun 09 03:21:07 PM PDT 24 2603995864 ps
T473 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2692901465 Jun 09 03:43:04 PM PDT 24 Jun 09 03:52:44 PM PDT 24 6128367088 ps
T888 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3232384187 Jun 09 03:11:10 PM PDT 24 Jun 09 06:04:27 PM PDT 24 58443351288 ps
T38 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.64473005 Jun 09 03:11:46 PM PDT 24 Jun 09 03:15:59 PM PDT 24 3098970705 ps
T889 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3901483014 Jun 09 03:31:08 PM PDT 24 Jun 09 03:36:59 PM PDT 24 3691669252 ps
T890 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4137783041 Jun 09 03:11:37 PM PDT 24 Jun 09 03:21:21 PM PDT 24 8969730820 ps
T891 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.254462241 Jun 09 03:20:21 PM PDT 24 Jun 09 03:30:26 PM PDT 24 4356894636 ps
T510 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3317455528 Jun 09 03:42:39 PM PDT 24 Jun 09 03:55:05 PM PDT 24 5051839576 ps
T222 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1521556517 Jun 09 03:13:57 PM PDT 24 Jun 09 03:23:24 PM PDT 24 4627279852 ps
T256 /workspace/coverage/default/1.chip_sw_plic_sw_irq.4055316421 Jun 09 03:26:11 PM PDT 24 Jun 09 03:30:25 PM PDT 24 3182579192 ps
T892 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2542896644 Jun 09 03:18:13 PM PDT 24 Jun 09 04:11:29 PM PDT 24 10766929000 ps
T328 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.47783613 Jun 09 03:11:54 PM PDT 24 Jun 09 04:12:51 PM PDT 24 11819991912 ps
T428 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2113427712 Jun 09 03:26:24 PM PDT 24 Jun 09 03:36:21 PM PDT 24 5941890031 ps
T893 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.623639560 Jun 09 03:23:17 PM PDT 24 Jun 09 03:33:37 PM PDT 24 7128848172 ps
T894 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2972812875 Jun 09 03:41:14 PM PDT 24 Jun 09 05:04:16 PM PDT 24 24123546784 ps
T895 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3572965507 Jun 09 03:44:07 PM PDT 24 Jun 09 04:45:23 PM PDT 24 13929856960 ps
T228 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.4146944284 Jun 09 03:21:41 PM PDT 24 Jun 09 03:32:35 PM PDT 24 4188134060 ps
T896 /workspace/coverage/default/0.rom_e2e_shutdown_output.3358689806 Jun 09 03:17:43 PM PDT 24 Jun 09 04:12:22 PM PDT 24 22927450834 ps
T897 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2922198645 Jun 09 03:33:11 PM PDT 24 Jun 09 03:39:37 PM PDT 24 4701510648 ps
T229 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3263616510 Jun 09 03:10:54 PM PDT 24 Jun 09 03:33:32 PM PDT 24 23063237850 ps
T898 /workspace/coverage/default/0.rom_e2e_asm_init_prod.2342220569 Jun 09 03:19:16 PM PDT 24 Jun 09 04:21:56 PM PDT 24 14162488034 ps
T474 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3989197752 Jun 09 03:40:51 PM PDT 24 Jun 09 03:47:21 PM PDT 24 3440024438 ps
T899 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3029778005 Jun 09 03:41:30 PM PDT 24 Jun 09 04:39:50 PM PDT 24 18828760400 ps
T502 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1667394311 Jun 09 03:40:24 PM PDT 24 Jun 09 03:50:08 PM PDT 24 4248453720 ps
T438 /workspace/coverage/default/82.chip_sw_all_escalation_resets.3497003366 Jun 09 03:49:56 PM PDT 24 Jun 09 03:59:29 PM PDT 24 5904755070 ps
T900 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4261997111 Jun 09 03:22:38 PM PDT 24 Jun 09 04:25:22 PM PDT 24 18081094169 ps
T901 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2113758653 Jun 09 03:29:35 PM PDT 24 Jun 09 03:47:55 PM PDT 24 5452054231 ps
T902 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3946754839 Jun 09 03:42:08 PM PDT 24 Jun 09 04:02:04 PM PDT 24 8314601466 ps
T486 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3789552658 Jun 09 03:50:43 PM PDT 24 Jun 09 04:01:09 PM PDT 24 4467672132 ps
T903 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.499503076 Jun 09 03:46:17 PM PDT 24 Jun 09 03:53:41 PM PDT 24 4114511908 ps
T64 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4093549658 Jun 09 03:33:34 PM PDT 24 Jun 09 03:44:16 PM PDT 24 6769616152 ps
T904 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1850431422 Jun 09 03:18:15 PM PDT 24 Jun 09 03:36:41 PM PDT 24 8010607260 ps
T905 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1027582762 Jun 09 03:25:05 PM PDT 24 Jun 09 03:32:40 PM PDT 24 3556542218 ps
T906 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1275222512 Jun 09 03:25:07 PM PDT 24 Jun 09 03:55:04 PM PDT 24 9260863800 ps
T267 /workspace/coverage/default/35.chip_sw_all_escalation_resets.2396689117 Jun 09 03:44:26 PM PDT 24 Jun 09 03:53:16 PM PDT 24 5320415938 ps
T490 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113086690 Jun 09 03:46:34 PM PDT 24 Jun 09 03:54:00 PM PDT 24 3366338200 ps
T907 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1068260634 Jun 09 03:18:17 PM PDT 24 Jun 09 03:30:33 PM PDT 24 4347455550 ps
T908 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2013870803 Jun 09 03:29:47 PM PDT 24 Jun 09 03:35:16 PM PDT 24 2883196124 ps
T909 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.342873537 Jun 09 03:23:35 PM PDT 24 Jun 09 03:28:48 PM PDT 24 2663769912 ps
T910 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1294409570 Jun 09 03:13:22 PM PDT 24 Jun 09 03:23:50 PM PDT 24 5860164719 ps
T911 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3479782842 Jun 09 03:43:44 PM PDT 24 Jun 09 04:32:44 PM PDT 24 14058434024 ps
T912 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3019455608 Jun 09 03:21:16 PM PDT 24 Jun 09 04:20:44 PM PDT 24 14473615088 ps
T485 /workspace/coverage/default/59.chip_sw_all_escalation_resets.1969855333 Jun 09 03:49:05 PM PDT 24 Jun 09 04:01:57 PM PDT 24 6159956350 ps
T913 /workspace/coverage/default/1.rom_e2e_static_critical.534473419 Jun 09 03:32:32 PM PDT 24 Jun 09 04:33:11 PM PDT 24 16814950544 ps
T97 /workspace/coverage/default/1.chip_jtag_csr_rw.1321916909 Jun 09 03:18:03 PM PDT 24 Jun 09 03:48:14 PM PDT 24 15857102904 ps
T61 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.139748060 Jun 09 03:11:17 PM PDT 24 Jun 09 03:16:27 PM PDT 24 3046551570 ps
T914 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1628486405 Jun 09 03:37:26 PM PDT 24 Jun 09 03:42:30 PM PDT 24 2916422728 ps
T915 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1473811552 Jun 09 03:18:22 PM PDT 24 Jun 09 03:23:05 PM PDT 24 2888646600 ps
T916 /workspace/coverage/default/0.chip_sw_gpio_smoketest.4201250872 Jun 09 03:17:27 PM PDT 24 Jun 09 03:21:33 PM PDT 24 2925331731 ps
T394 /workspace/coverage/default/28.chip_sw_all_escalation_resets.772444377 Jun 09 03:45:58 PM PDT 24 Jun 09 03:57:24 PM PDT 24 5287157640 ps
T14 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2882716820 Jun 09 03:11:14 PM PDT 24 Jun 09 03:16:14 PM PDT 24 3712608414 ps
T917 /workspace/coverage/default/0.chip_sw_hmac_smoketest.3927440342 Jun 09 03:17:17 PM PDT 24 Jun 09 03:21:06 PM PDT 24 2729472328 ps
T357 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3216921380 Jun 09 03:25:20 PM PDT 24 Jun 09 03:35:07 PM PDT 24 3628448528 ps
T918 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.820730752 Jun 09 03:37:27 PM PDT 24 Jun 09 03:49:38 PM PDT 24 5093698920 ps
T919 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1709278023 Jun 09 03:21:41 PM PDT 24 Jun 09 03:37:51 PM PDT 24 10047048960 ps
T920 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3221444636 Jun 09 03:13:16 PM PDT 24 Jun 09 03:18:12 PM PDT 24 3520012936 ps
T391 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1520944929 Jun 09 03:33:00 PM PDT 24 Jun 09 03:43:14 PM PDT 24 2910456348 ps
T519 /workspace/coverage/default/30.chip_sw_all_escalation_resets.3569359020 Jun 09 03:46:15 PM PDT 24 Jun 09 03:55:34 PM PDT 24 5361471240 ps
T921 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2617169905 Jun 09 03:40:57 PM PDT 24 Jun 09 03:52:56 PM PDT 24 3808250478 ps
T922 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2724252877 Jun 09 03:24:45 PM PDT 24 Jun 09 03:33:01 PM PDT 24 4443869088 ps
T923 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3230730944 Jun 09 03:19:55 PM PDT 24 Jun 09 03:25:28 PM PDT 24 3558336608 ps
T924 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.633452194 Jun 09 03:13:56 PM PDT 24 Jun 09 03:16:11 PM PDT 24 2754949400 ps
T925 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.451820383 Jun 09 03:48:46 PM PDT 24 Jun 09 03:55:12 PM PDT 24 3393635956 ps
T926 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.574064122 Jun 09 03:44:19 PM PDT 24 Jun 09 04:10:31 PM PDT 24 9479478346 ps
T927 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.470633387 Jun 09 03:36:02 PM PDT 24 Jun 09 03:49:01 PM PDT 24 4588964344 ps
T928 /workspace/coverage/default/2.chip_sw_power_sleep_load.4020249376 Jun 09 03:37:28 PM PDT 24 Jun 09 03:50:13 PM PDT 24 11397583356 ps
T929 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.707230724 Jun 09 03:12:05 PM PDT 24 Jun 09 03:21:09 PM PDT 24 3830648920 ps
T162 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4240266399 Jun 09 03:41:01 PM PDT 24 Jun 09 03:51:29 PM PDT 24 6017920350 ps
T930 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4184632085 Jun 09 03:13:12 PM PDT 24 Jun 09 03:24:11 PM PDT 24 4924579936 ps
T931 /workspace/coverage/default/2.rom_keymgr_functest.207501813 Jun 09 03:39:17 PM PDT 24 Jun 09 03:48:33 PM PDT 24 4406877936 ps
T238 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.894377423 Jun 09 03:30:47 PM PDT 24 Jun 09 04:51:29 PM PDT 24 49326921532 ps
T932 /workspace/coverage/default/0.chip_sw_uart_smoketest.2395253677 Jun 09 03:16:16 PM PDT 24 Jun 09 03:20:44 PM PDT 24 3339110272 ps
T392 /workspace/coverage/default/0.chip_sw_edn_boot_mode.435121990 Jun 09 03:10:29 PM PDT 24 Jun 09 03:17:19 PM PDT 24 2919241564 ps
T933 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1184017788 Jun 09 03:29:33 PM PDT 24 Jun 09 04:00:31 PM PDT 24 8992524077 ps
T934 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1439370016 Jun 09 03:27:47 PM PDT 24 Jun 09 03:32:15 PM PDT 24 2347469618 ps
T935 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2383028409 Jun 09 03:13:06 PM PDT 24 Jun 09 03:18:21 PM PDT 24 3504434221 ps
T936 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2674272323 Jun 09 03:20:13 PM PDT 24 Jun 09 04:12:23 PM PDT 24 13318599380 ps
T439 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2926075210 Jun 09 03:32:48 PM PDT 24 Jun 09 03:39:10 PM PDT 24 4070895412 ps
T937 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3778171504 Jun 09 03:13:12 PM PDT 24 Jun 09 03:19:51 PM PDT 24 4954634632 ps
T938 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1249574493 Jun 09 03:15:08 PM PDT 24 Jun 09 04:48:26 PM PDT 24 47985604100 ps
T939 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.508059111 Jun 09 03:32:17 PM PDT 24 Jun 09 03:40:18 PM PDT 24 4823104816 ps
T336 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2328894509 Jun 09 03:24:56 PM PDT 24 Jun 09 03:30:56 PM PDT 24 3406137924 ps
T940 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2157647669 Jun 09 03:33:10 PM PDT 24 Jun 09 03:37:12 PM PDT 24 2499244488 ps
T941 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3441531355 Jun 09 03:21:15 PM PDT 24 Jun 09 04:58:49 PM PDT 24 51932823355 ps
T942 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1183708771 Jun 09 03:39:27 PM PDT 24 Jun 09 03:48:55 PM PDT 24 4455537780 ps
T281 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3979969565 Jun 09 03:32:22 PM PDT 24 Jun 09 03:47:04 PM PDT 24 6004885028 ps
T943 /workspace/coverage/default/2.chip_sw_otbn_smoketest.2645012980 Jun 09 03:39:16 PM PDT 24 Jun 09 04:00:54 PM PDT 24 7381251708 ps
T944 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1049814040 Jun 09 03:23:19 PM PDT 24 Jun 09 04:48:07 PM PDT 24 22832410174 ps
T945 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2870070253 Jun 09 03:11:43 PM PDT 24 Jun 09 03:27:37 PM PDT 24 5705062040 ps
T946 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3751729184 Jun 09 03:10:14 PM PDT 24 Jun 09 03:15:43 PM PDT 24 5338799112 ps
T947 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1134638467 Jun 09 03:13:44 PM PDT 24 Jun 09 03:24:01 PM PDT 24 5309306000 ps
T948 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1580994610 Jun 09 03:41:09 PM PDT 24 Jun 09 03:50:59 PM PDT 24 4510791000 ps
T949 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.660472584 Jun 09 03:34:25 PM PDT 24 Jun 09 03:48:22 PM PDT 24 7257234376 ps
T950 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1368094254 Jun 09 03:19:11 PM PDT 24 Jun 09 03:27:14 PM PDT 24 5921324868 ps
T951 /workspace/coverage/default/1.chip_sw_aes_smoketest.174407353 Jun 09 03:28:46 PM PDT 24 Jun 09 03:32:17 PM PDT 24 2506773240 ps
T952 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2340414012 Jun 09 03:39:54 PM PDT 24 Jun 09 03:49:54 PM PDT 24 4215641912 ps
T358 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2295953929 Jun 09 03:35:34 PM PDT 24 Jun 09 03:43:07 PM PDT 24 4067508680 ps
T953 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.776479149 Jun 09 03:32:33 PM PDT 24 Jun 09 03:34:19 PM PDT 24 2430314722 ps
T954 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3041981510 Jun 09 03:35:46 PM PDT 24 Jun 09 03:47:51 PM PDT 24 4909622300 ps
T955 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.932336941 Jun 09 03:27:40 PM PDT 24 Jun 09 03:31:20 PM PDT 24 2850677062 ps
T956 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3219239429 Jun 09 03:26:02 PM PDT 24 Jun 09 04:07:18 PM PDT 24 12955268897 ps
T957 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.882036527 Jun 09 03:18:31 PM PDT 24 Jun 09 03:23:55 PM PDT 24 3114977096 ps
T958 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2290102397 Jun 09 03:12:38 PM PDT 24 Jun 09 03:15:45 PM PDT 24 3923689283 ps
T959 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2201749433 Jun 09 03:23:09 PM PDT 24 Jun 09 03:44:48 PM PDT 24 4681526400 ps
T960 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1305464316 Jun 09 03:20:00 PM PDT 24 Jun 09 03:25:48 PM PDT 24 3290840280 ps
T961 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.433742203 Jun 09 03:12:24 PM PDT 24 Jun 09 03:27:06 PM PDT 24 7239361520 ps
T962 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.862690168 Jun 09 03:22:30 PM PDT 24 Jun 09 03:55:23 PM PDT 24 8794754840 ps
T963 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4281941243 Jun 09 03:16:00 PM PDT 24 Jun 09 03:19:11 PM PDT 24 2533255824 ps
T964 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3459379761 Jun 09 03:43:49 PM PDT 24 Jun 09 03:49:05 PM PDT 24 3337061232 ps
T965 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4140974185 Jun 09 03:37:34 PM PDT 24 Jun 09 03:47:31 PM PDT 24 4514126040 ps
T477 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2887727384 Jun 09 03:48:22 PM PDT 24 Jun 09 03:55:25 PM PDT 24 3701772628 ps
T966 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3477395820 Jun 09 03:31:31 PM PDT 24 Jun 09 04:03:49 PM PDT 24 30022950240 ps
T67 /workspace/coverage/default/0.chip_sw_spi_device_tpm.2797419534 Jun 09 03:10:55 PM PDT 24 Jun 09 03:16:43 PM PDT 24 3544395897 ps
T967 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3112282568 Jun 09 03:22:04 PM PDT 24 Jun 09 04:24:18 PM PDT 24 20465225549 ps
T134 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3158948257 Jun 09 03:43:28 PM PDT 24 Jun 09 03:50:23 PM PDT 24 3920838840 ps
T384 /workspace/coverage/default/27.chip_sw_all_escalation_resets.3231034991 Jun 09 03:43:59 PM PDT 24 Jun 09 03:57:38 PM PDT 24 6068203108 ps
T968 /workspace/coverage/default/1.chip_sival_flash_info_access.765986466 Jun 09 03:19:06 PM PDT 24 Jun 09 03:23:50 PM PDT 24 3376545040 ps
T135 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2535401060 Jun 09 03:42:05 PM PDT 24 Jun 09 03:49:50 PM PDT 24 4053738712 ps
T969 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3921755153 Jun 09 03:26:24 PM PDT 24 Jun 09 03:32:15 PM PDT 24 3475391425 ps
T16 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1896898806 Jun 09 03:31:33 PM PDT 24 Jun 09 03:41:12 PM PDT 24 6478638216 ps
T223 /workspace/coverage/default/0.chip_sw_usbdev_stream.1609911944 Jun 09 03:13:09 PM PDT 24 Jun 09 04:31:59 PM PDT 24 18545100640 ps
T970 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.4268819999 Jun 09 03:23:00 PM PDT 24 Jun 09 03:32:20 PM PDT 24 4140182306 ps
T385 /workspace/coverage/default/46.chip_sw_all_escalation_resets.2208883562 Jun 09 03:46:17 PM PDT 24 Jun 09 03:57:17 PM PDT 24 5190773540 ps
T971 /workspace/coverage/default/2.chip_sw_power_idle_load.4204802964 Jun 09 03:37:31 PM PDT 24 Jun 09 03:47:28 PM PDT 24 4971233328 ps
T972 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2431080291 Jun 09 03:45:11 PM PDT 24 Jun 09 04:35:14 PM PDT 24 15023050424 ps
T973 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3866015148 Jun 09 03:22:04 PM PDT 24 Jun 09 03:27:04 PM PDT 24 3418509161 ps
T974 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3512276544 Jun 09 03:36:48 PM PDT 24 Jun 09 03:41:39 PM PDT 24 3103536404 ps
T975 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1836744281 Jun 09 03:21:20 PM PDT 24 Jun 09 04:54:36 PM PDT 24 22531837908 ps
T976 /workspace/coverage/default/29.chip_sw_all_escalation_resets.2195372895 Jun 09 03:43:38 PM PDT 24 Jun 09 03:54:57 PM PDT 24 5224646984 ps
T977 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3891567695 Jun 09 03:21:44 PM PDT 24 Jun 09 03:31:23 PM PDT 24 9558207481 ps
T198 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.834155184 Jun 09 03:29:37 PM PDT 24 Jun 09 04:53:59 PM PDT 24 43586790650 ps
T978 /workspace/coverage/default/33.chip_sw_all_escalation_resets.4161139392 Jun 09 03:44:53 PM PDT 24 Jun 09 03:55:58 PM PDT 24 5921838790 ps
T230 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3541811495 Jun 09 03:21:57 PM PDT 24 Jun 09 04:00:03 PM PDT 24 22653803580 ps
T298 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.523936935 Jun 09 03:38:32 PM PDT 24 Jun 09 03:43:39 PM PDT 24 3184957436 ps
T979 /workspace/coverage/default/87.chip_sw_all_escalation_resets.359350181 Jun 09 03:49:24 PM PDT 24 Jun 09 03:59:25 PM PDT 24 4934137120 ps
T980 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.900882486 Jun 09 03:20:50 PM PDT 24 Jun 09 03:29:15 PM PDT 24 5483876752 ps
T498 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1893537157 Jun 09 03:48:15 PM PDT 24 Jun 09 03:58:20 PM PDT 24 5154366622 ps
T981 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1374344697 Jun 09 03:14:04 PM PDT 24 Jun 09 03:29:00 PM PDT 24 9055980502 ps
T982 /workspace/coverage/default/2.chip_sw_otbn_randomness.4271559341 Jun 09 03:33:43 PM PDT 24 Jun 09 03:53:21 PM PDT 24 6288629504 ps
T983 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.980200080 Jun 09 03:24:30 PM PDT 24 Jun 09 03:35:47 PM PDT 24 5090510326 ps
T440 /workspace/coverage/default/69.chip_sw_all_escalation_resets.71993270 Jun 09 03:49:00 PM PDT 24 Jun 09 04:00:23 PM PDT 24 6352329960 ps
T984 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2875720440 Jun 09 03:13:32 PM PDT 24 Jun 09 03:33:09 PM PDT 24 7834212367 ps
T985 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1116421888 Jun 09 03:39:47 PM PDT 24 Jun 09 03:44:37 PM PDT 24 2839472584 ps
T380 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1704280016 Jun 09 03:17:20 PM PDT 24 Jun 09 03:25:38 PM PDT 24 6601145130 ps
T986 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3739736381 Jun 09 03:22:55 PM PDT 24 Jun 09 03:31:10 PM PDT 24 19412551118 ps
T987 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3969323462 Jun 09 03:39:21 PM PDT 24 Jun 09 03:51:45 PM PDT 24 6303183732 ps
T988 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3345645897 Jun 09 03:23:49 PM PDT 24 Jun 09 04:12:30 PM PDT 24 28736602751 ps
T989 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1097257246 Jun 09 03:35:57 PM PDT 24 Jun 09 03:50:14 PM PDT 24 4062819348 ps
T990 /workspace/coverage/default/2.chip_sw_flash_init.2324067950 Jun 09 03:31:16 PM PDT 24 Jun 09 04:00:46 PM PDT 24 24076158403 ps
T991 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3961912588 Jun 09 03:17:39 PM PDT 24 Jun 09 03:27:37 PM PDT 24 4611393073 ps
T303 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.5076519 Jun 09 03:35:04 PM PDT 24 Jun 09 03:49:40 PM PDT 24 8716503094 ps
T992 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1870417560 Jun 09 03:25:16 PM PDT 24 Jun 09 03:29:56 PM PDT 24 3093953802 ps
T993 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3804439755 Jun 09 03:12:12 PM PDT 24 Jun 09 03:16:37 PM PDT 24 3128801079 ps
T994 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2417423165 Jun 09 03:47:20 PM PDT 24 Jun 09 03:59:37 PM PDT 24 4739114208 ps
T995 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1049346914 Jun 09 03:35:07 PM PDT 24 Jun 09 03:39:10 PM PDT 24 2419550928 ps
T996 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1484916244 Jun 09 03:18:50 PM PDT 24 Jun 09 03:40:08 PM PDT 24 9368011799 ps
T997 /workspace/coverage/default/0.chip_sw_rv_timer_irq.597180874 Jun 09 03:13:53 PM PDT 24 Jun 09 03:18:36 PM PDT 24 2975629112 ps
T998 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4220786506 Jun 09 03:20:58 PM PDT 24 Jun 09 04:41:44 PM PDT 24 45327426904 ps
T429 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1047722550 Jun 09 03:16:51 PM PDT 24 Jun 09 03:27:29 PM PDT 24 6592999380 ps
T999 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.804600264 Jun 09 03:39:12 PM PDT 24 Jun 09 03:49:45 PM PDT 24 5216940868 ps
T499 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127361489 Jun 09 03:45:32 PM PDT 24 Jun 09 03:50:48 PM PDT 24 3028679084 ps
T361 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.745451600 Jun 09 03:30:25 PM PDT 24 Jun 09 03:41:23 PM PDT 24 4603342294 ps
T1000 /workspace/coverage/default/36.chip_sw_all_escalation_resets.688372856 Jun 09 03:45:46 PM PDT 24 Jun 09 03:55:18 PM PDT 24 4941146696 ps
T354 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2664024552 Jun 09 03:14:41 PM PDT 24 Jun 09 03:42:30 PM PDT 24 7266443544 ps
T1001 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.233499167 Jun 09 03:35:49 PM PDT 24 Jun 09 03:43:35 PM PDT 24 2821507416 ps
T55 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2787575849 Jun 09 03:03:44 PM PDT 24 Jun 09 03:08:19 PM PDT 24 5611101100 ps
T56 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.200449827 Jun 09 03:03:47 PM PDT 24 Jun 09 03:08:31 PM PDT 24 5286496440 ps
T57 /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1899500901 Jun 09 03:03:47 PM PDT 24 Jun 09 03:09:28 PM PDT 24 6014020566 ps
T215 /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4027666715 Jun 09 03:03:47 PM PDT 24 Jun 09 03:08:04 PM PDT 24 4618155544 ps
T217 /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3354547190 Jun 09 03:03:43 PM PDT 24 Jun 09 03:10:30 PM PDT 24 5549439785 ps
T218 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3813146683 Jun 09 03:03:45 PM PDT 24 Jun 09 03:08:36 PM PDT 24 5428235643 ps
T216 /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.666000802 Jun 09 03:03:45 PM PDT 24 Jun 09 03:08:20 PM PDT 24 4758113301 ps
T219 /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2709385384 Jun 09 03:03:48 PM PDT 24 Jun 09 03:07:30 PM PDT 24 3893820598 ps
T220 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.21299103 Jun 09 03:03:46 PM PDT 24 Jun 09 03:08:33 PM PDT 24 5418273828 ps
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