Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.42	91.02	80.63	89.66		92.13	80.42	84.65

Total test records in report: 1001

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.411659365

Jun 09 03:03:44 PM PDT 24

Jun 09 03:07:23 PM PDT 24

5675906260 ps

Test location	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2728046189
Short name	T31
Test name
Test status
Simulation time	4125973720 ps
CPU time	424.9 seconds
Started	Jun 09 03:47:35 PM PDT 24
Finished	Jun 09 03:54:40 PM PDT 24
Peak memory	646444 kb
Host	smart-df5d8de0-92e7-4b9a-92ab-00736b1a8949
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728046189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2728046189
Directory	/workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_test.537240937
Short name	T78
Test name
Test status
Simulation time	2499507960 ps
CPU time	272.63 seconds
Started	Jun 09 03:23:50 PM PDT 24
Finished	Jun 09 03:28:23 PM PDT 24
Peak memory	607312 kb
Host	smart-e2b575f5-a6de-4aa0-8672-bfebb6340e8c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537240937 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_alert_test.537240937
Directory	/workspace/1.chip_sw_alert_test/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.200449827
Short name	T56
Test name
Test status
Simulation time	5286496440 ps
CPU time	283.7 seconds
Started	Jun 09 03:03:47 PM PDT 24
Finished	Jun 09 03:08:31 PM PDT 24
Peak memory	656512 kb
Host	smart-6fcb5fb8-bdf8-486e-a8d7-1ea08e2d43e6
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200449827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 4.chip_padctrl_attributes.200449827
Directory	/workspace/4.chip_padctrl_attributes/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_0.2234053574
Short name	T175
Test name
Test status
Simulation time	6133294484 ps
CPU time	1079.13 seconds
Started	Jun 09 03:36:49 PM PDT 24
Finished	Jun 09 03:54:48 PM PDT 24
Peak memory	606736 kb
Host	smart-dee52e3b-47b8-4613-a81f-04b6f2c140d9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234053574 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.2234053574
Directory	/workspace/2.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2976225252
Short name	T6
Test name
Test status
Simulation time	10821574648 ps
CPU time	2306.66 seconds
Started	Jun 09 03:11:25 PM PDT 24
Finished	Jun 09 03:49:53 PM PDT 24
Peak memory	614960 kb
Host	smart-83a6b77a-6891-49b5-8791-33373f2645a3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976 225252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.2976225252
Directory	/workspace/0.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1012736669
Short name	T36
Test name
Test status
Simulation time	2948647751 ps
CPU time	324.59 seconds
Started	Jun 09 03:32:18 PM PDT 24
Finished	Jun 09 03:37:43 PM PDT 24
Peak memory	606080 kb
Host	smart-1e3a8cef-ee70-4c66-88ef-4f61b2169017
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012 736669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1012736669
Directory	/workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/2.chip_jtag_csr_rw.4149001136
Short name	T76
Test name
Test status
Simulation time	16303021536 ps
CPU time	1871.75 seconds
Started	Jun 09 03:28:39 PM PDT 24
Finished	Jun 09 03:59:51 PM PDT 24
Peak memory	601356 kb
Host	smart-22da1f2b-cbe3-4beb-9823-2a964f3e1aa5
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149001136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.4149001136
Directory	/workspace/2.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2684474280
Short name	T19
Test name
Test status
Simulation time	4735754304 ps
CPU time	807.14 seconds
Started	Jun 09 03:12:20 PM PDT 24
Finished	Jun 09 03:25:48 PM PDT 24
Peak memory	608280 kb
Host	smart-f3195f88-425d-457b-80a4-b4ccfe631950
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2684474280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.2684474280
Directory	/workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1075473134
Short name	T1
Test name
Test status
Simulation time	21356697338 ps
CPU time	1753.22 seconds
Started	Jun 09 03:13:51 PM PDT 24
Finished	Jun 09 03:43:05 PM PDT 24
Peak memory	608196 kb
Host	smart-1a6c0ddb-9eae-4ac1-bcd5-7f2926a74c41
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1075473134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1075473134
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_20.3565673074
Short name	T92
Test name
Test status
Simulation time	4852740274 ps
CPU time	819.39 seconds
Started	Jun 09 03:16:55 PM PDT 24
Finished	Jun 09 03:30:35 PM PDT 24
Peak memory	607380 kb
Host	smart-aa54b436-5a1d-4263-94b2-f60cc74f43a4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565673074 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.3565673074
Directory	/workspace/0.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.4222456549
Short name	T188
Test name
Test status
Simulation time	50800182216 ps
CPU time	5117.07 seconds
Started	Jun 09 03:13:36 PM PDT 24
Finished	Jun 09 04:38:54 PM PDT 24
Peak memory	614828 kb
Host	smart-89b7e1f4-2eef-44f5-8005-6b7d978a1f04
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222456549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.4222456549
Directory	/workspace/0.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.65931937
Short name	T194
Test name
Test status
Simulation time	2791338728 ps
CPU time	276.73 seconds
Started	Jun 09 03:12:21 PM PDT 24
Finished	Jun 09 03:16:58 PM PDT 24
Peak memory	606660 kb
Host	smart-72d7e9a4-85be-4e79-b12b-81b4ea3af2b2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=65931937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.65931937
Directory	/workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4235988223
Short name	T33
Test name
Test status
Simulation time	13739471000 ps
CPU time	4003.47 seconds
Started	Jun 09 03:20:17 PM PDT 24
Finished	Jun 09 04:27:01 PM PDT 24
Peak memory	607936 kb
Host	smart-3c1673f2-c516-4a4f-9a03-f7433805222f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235988223 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4235988223
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3956738708
Short name	T100
Test name
Test status
Simulation time	7854057280 ps
CPU time	1340.09 seconds
Started	Jun 09 03:34:22 PM PDT 24
Finished	Jun 09 03:56:43 PM PDT 24
Peak memory	608812 kb
Host	smart-c7368bae-b21c-46dd-a57f-2e46ee83e4e9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395673 8708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.3956738708
Directory	/workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/0.chip_jtag_csr_rw.3290460845
Short name	T26
Test name
Test status
Simulation time	13790737968 ps
CPU time	1665.18 seconds
Started	Jun 09 03:04:20 PM PDT 24
Finished	Jun 09 03:32:06 PM PDT 24
Peak memory	607132 kb
Host	smart-b44f37ff-3acc-491e-8f74-b9de1bac5eaa
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290460845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.3290460845
Directory	/workspace/0.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.118335231
Short name	T12
Test name
Test status
Simulation time	2604286772 ps
CPU time	255.83 seconds
Started	Jun 09 03:18:14 PM PDT 24
Finished	Jun 09 03:22:30 PM PDT 24
Peak memory	606688 kb
Host	smart-fdfd4caa-d85e-47cf-9ae4-55473c404cc9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118335231 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.118335231
Directory	/workspace/1.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3187679137
Short name	T29
Test name
Test status
Simulation time	13910445240 ps
CPU time	1448.82 seconds
Started	Jun 09 03:11:46 PM PDT 24
Finished	Jun 09 03:35:55 PM PDT 24
Peak memory	608664 kb
Host	smart-132b7e59-aba3-4afd-b77e-b77d5cd909ff
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187679137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.3187679137
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2749850477
Short name	T3
Test name
Test status
Simulation time	3112439290 ps
CPU time	294.54 seconds
Started	Jun 09 03:15:58 PM PDT 24
Finished	Jun 09 03:20:53 PM PDT 24
Peak memory	607736 kb
Host	smart-6081049e-9338-49d9-be7f-4430e3ed08fc
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749850477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.2749850477
Directory	/workspace/0.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1213052936
Short name	T10
Test name
Test status
Simulation time	2906230636 ps
CPU time	283.91 seconds
Started	Jun 09 03:17:33 PM PDT 24
Finished	Jun 09 03:22:18 PM PDT 24
Peak memory	607732 kb
Host	smart-ba00e312-e340-4cba-8ee9-eb95ad4c8591
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213052936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1213052936
Directory	/workspace/1.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.663936296
Short name	T41
Test name
Test status
Simulation time	4410721125 ps
CPU time	540.64 seconds
Started	Jun 09 03:12:18 PM PDT 24
Finished	Jun 09 03:21:19 PM PDT 24
Peak memory	623024 kb
Host	smart-7f281c9e-df6f-4ca9-a45b-2aeed3b07a86
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663936296 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.663936296
Directory	/workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/0.chip_sw_gpio.2637072693
Short name	T51
Test name
Test status
Simulation time	4412503224 ps
CPU time	643.03 seconds
Started	Jun 09 03:13:59 PM PDT 24
Finished	Jun 09 03:24:42 PM PDT 24
Peak memory	607440 kb
Host	smart-71a02eb1-4d1a-4c0d-926b-52b5bf2ed9e3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637072693 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.2637072693
Directory	/workspace/0.chip_sw_gpio/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.363317219
Short name	T242
Test name
Test status
Simulation time	5870704320 ps
CPU time	909.76 seconds
Started	Jun 09 03:30:58 PM PDT 24
Finished	Jun 09 03:46:08 PM PDT 24
Peak memory	607864 kb
Host	smart-30485e42-5d27-431c-9a52-58b8026e6cce
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363317219 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_rstmgr_cpu_info.363317219
Directory	/workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3513271849
Short name	T99
Test name
Test status
Simulation time	7009874056 ps
CPU time	1429.33 seconds
Started	Jun 09 03:33:13 PM PDT 24
Finished	Jun 09 03:57:03 PM PDT 24
Peak memory	607612 kb
Host	smart-448257ee-51a0-4fba-84ee-dd13fd896627
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3513271849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.3513271849
Directory	/workspace/2.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1862767508
Short name	T23
Test name
Test status
Simulation time	57531886528 ps
CPU time	9897.41 seconds
Started	Jun 09 03:29:14 PM PDT 24
Finished	Jun 09 06:14:13 PM PDT 24
Peak memory	623348 kb
Host	smart-025f4e9a-ef07-4fb7-8595-bc124fd02cdf
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1862767508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.1862767508
Directory	/workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_10.3165329895
Short name	T170
Test name
Test status
Simulation time	3496105870 ps
CPU time	808.99 seconds
Started	Jun 09 03:37:05 PM PDT 24
Finished	Jun 09 03:50:35 PM PDT 24
Peak memory	606420 kb
Host	smart-f64fc0a9-c248-4130-be5d-5ef8b95f82df
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165329895 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.3165329895
Directory	/workspace/2.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1406549129
Short name	T8
Test name
Test status
Simulation time	4483716660 ps
CPU time	471.75 seconds
Started	Jun 09 03:13:41 PM PDT 24
Finished	Jun 09 03:21:33 PM PDT 24
Peak memory	614508 kb
Host	smart-7e8d0cf8-6c45-4bd9-bec0-64d19433c663
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 406549129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.1406549129
Directory	/workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1112399224
Short name	T158
Test name
Test status
Simulation time	5854389220 ps
CPU time	493.06 seconds
Started	Jun 09 03:12:19 PM PDT 24
Finished	Jun 09 03:20:33 PM PDT 24
Peak memory	606756 kb
Host	smart-8fa9b042-5330-4031-b266-56161abbff76
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11123992 24 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1112399224
Directory	/workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.64473005
Short name	T38
Test name
Test status
Simulation time	3098970705 ps
CPU time	252.15 seconds
Started	Jun 09 03:11:46 PM PDT 24
Finished	Jun 09 03:15:59 PM PDT 24
Peak memory	606600 kb
Host	smart-5cae0e78-6e1e-400a-bdc0-a5852afec0d3
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6447 3005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.64473005
Directory	/workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/20.chip_sw_all_escalation_resets.2164230998
Short name	T313
Test name
Test status
Simulation time	5176437830 ps
CPU time	686.15 seconds
Started	Jun 09 03:43:12 PM PDT 24
Finished	Jun 09 03:54:39 PM PDT 24
Peak memory	647740 kb
Host	smart-66329a04-090b-45a2-a364-7bb1a26edde0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2164230998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.2164230998
Directory	/workspace/20.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.339655862
Short name	T45
Test name
Test status
Simulation time	22700921760 ps
CPU time	1698.82 seconds
Started	Jun 09 03:31:45 PM PDT 24
Finished	Jun 09 04:00:05 PM PDT 24
Peak memory	612152 kb
Host	smart-76773bbd-9be4-4e25-b6f1-9a5671fd64b1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33965586 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.339655862
Directory	/workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2348304781
Short name	T288
Test name
Test status
Simulation time	4176642695 ps
CPU time	513.12 seconds
Started	Jun 09 03:13:27 PM PDT 24
Finished	Jun 09 03:22:00 PM PDT 24
Peak memory	607240 kb
Host	smart-e24cdd73-73a5-429c-a5d9-cad2fe977e38
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348304781 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2348304781
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.330621963
Short name	T169
Test name
Test status
Simulation time	47265944070 ps
CPU time	4983.01 seconds
Started	Jun 09 03:14:50 PM PDT 24
Finished	Jun 09 04:37:55 PM PDT 24
Peak memory	616316 kb
Host	smart-c44c2ce3-0e2c-43e6-8f8c-5b4989149ff2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330621963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_rma.330621963
Directory	/workspace/0.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.473025265
Short name	T37
Test name
Test status
Simulation time	3000346243 ps
CPU time	256.39 seconds
Started	Jun 09 03:16:36 PM PDT 24
Finished	Jun 09 03:20:53 PM PDT 24
Peak memory	607440 kb
Host	smart-3015198b-edbd-4121-952c-7ab9f0ef1ef1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4730 25265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.473025265
Directory	/workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/88.chip_sw_all_escalation_resets.4237097444
Short name	T248
Test name
Test status
Simulation time	5607737034 ps
CPU time	442.63 seconds
Started	Jun 09 03:50:21 PM PDT 24
Finished	Jun 09 03:57:44 PM PDT 24
Peak memory	647688 kb
Host	smart-f1cd2462-459a-4b7b-ba77-c9e358aeb7c5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4237097444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.4237097444
Directory	/workspace/88.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/18.chip_sw_all_escalation_resets.132459607
Short name	T351
Test name
Test status
Simulation time	6103943946 ps
CPU time	695.44 seconds
Started	Jun 09 03:42:59 PM PDT 24
Finished	Jun 09 03:54:34 PM PDT 24
Peak memory	643264 kb
Host	smart-db81c521-f549-4871-a666-fe805fc19912
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 132459607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.132459607
Directory	/workspace/18.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_jtag_csr_rw.1321916909
Short name	T97
Test name
Test status
Simulation time	15857102904 ps
CPU time	1810.85 seconds
Started	Jun 09 03:18:03 PM PDT 24
Finished	Jun 09 03:48:14 PM PDT 24
Peak memory	601556 kb
Host	smart-28abc278-c379-4ced-8882-c5f3a68fe4c6
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321916909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1321916909
Directory	/workspace/1.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/92.chip_sw_all_escalation_resets.3512472181
Short name	T127
Test name
Test status
Simulation time	6377404024 ps
CPU time	632.5 seconds
Started	Jun 09 03:51:30 PM PDT 24
Finished	Jun 09 04:02:03 PM PDT 24
Peak memory	643772 kb
Host	smart-842d4a06-9672-4069-a647-bd31287286aa
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3512472181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.3512472181
Directory	/workspace/92.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2818812578
Short name	T108
Test name
Test status
Simulation time	7000189478 ps
CPU time	975.44 seconds
Started	Jun 09 03:35:57 PM PDT 24
Finished	Jun 09 03:52:12 PM PDT 24
Peak memory	607612 kb
Host	smart-6a3b1366-131d-48d4-940c-5bc5ffb0bb83
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818812578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.2818812578
Directory	/workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/83.chip_sw_all_escalation_resets.491970701
Short name	T412
Test name
Test status
Simulation time	5536557160 ps
CPU time	544.8 seconds
Started	Jun 09 03:51:16 PM PDT 24
Finished	Jun 09 04:00:21 PM PDT 24
Peak memory	643536 kb
Host	smart-5a191790-7cf8-4ed5-9e36-ca1b8c09e8bb
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 491970701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.491970701
Directory	/workspace/83.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1411355399
Short name	T95
Test name
Test status
Simulation time	2947712850 ps
CPU time	317.53 seconds
Started	Jun 09 03:26:38 PM PDT 24
Finished	Jun 09 03:31:56 PM PDT 24
Peak memory	606308 kb
Host	smart-130d37ce-983e-4294-989d-8a067a968d2e
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14113553 99 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1411355399
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3848219798
Short name	T233
Test name
Test status
Simulation time	18589923894 ps
CPU time	1800.54 seconds
Started	Jun 09 03:36:00 PM PDT 24
Finished	Jun 09 04:06:01 PM PDT 24
Peak memory	610764 kb
Host	smart-5bf80a83-dc39-4847-a5ef-9e8dc1a1c41b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3848219798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.3848219798
Directory	/workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2845642773
Short name	T77
Test name
Test status
Simulation time	6014751448 ps
CPU time	677.03 seconds
Started	Jun 09 03:45:33 PM PDT 24
Finished	Jun 09 03:56:50 PM PDT 24
Peak memory	643156 kb
Host	smart-77dbf2ed-997b-4f28-a413-879bda6e6e5e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2845642773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2845642773
Directory	/workspace/41.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1758303373
Short name	T154
Test name
Test status
Simulation time	27905663290 ps
CPU time	4197.48 seconds
Started	Jun 09 03:13:11 PM PDT 24
Finished	Jun 09 04:23:09 PM PDT 24
Peak memory	607592 kb
Host	smart-3cfe0d88-d9dd-4049-9ef6-9e069f49aa10
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1758303373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1758303373
Directory	/workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1891852053
Short name	T60
Test name
Test status
Simulation time	3468287880 ps
CPU time	304.53 seconds
Started	Jun 09 03:18:28 PM PDT 24
Finished	Jun 09 03:23:33 PM PDT 24
Peak memory	606828 kb
Host	smart-be940b5f-1d3a-491d-ad78-c7d208eec4b3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891852053 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1891852053
Directory	/workspace/1.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2787575849
Short name	T55
Test name
Test status
Simulation time	5611101100 ps
CPU time	274.09 seconds
Started	Jun 09 03:03:44 PM PDT 24
Finished	Jun 09 03:08:19 PM PDT 24
Peak memory	648340 kb
Host	smart-4b0c299a-9997-4f3f-a680-8bec2b2b55a1
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787575849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.2787575849
Directory	/workspace/0.chip_padctrl_attributes/latest

Test location	/workspace/coverage/default/75.chip_sw_all_escalation_resets.3151144428
Short name	T104
Test name
Test status
Simulation time	6218057862 ps
CPU time	580.99 seconds
Started	Jun 09 03:49:04 PM PDT 24
Finished	Jun 09 03:58:45 PM PDT 24
Peak memory	643188 kb
Host	smart-3d92c503-e458-4bf3-80c5-bd5c3350a7f4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3151144428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.3151144428
Directory	/workspace/75.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2384920195
Short name	T146
Test name
Test status
Simulation time	4093579662 ps
CPU time	465.24 seconds
Started	Jun 09 03:45:53 PM PDT 24
Finished	Jun 09 03:53:38 PM PDT 24
Peak memory	646404 kb
Host	smart-188defe2-aa2f-4628-a3fd-220d90f9577b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384920195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2384920195
Directory	/workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/63.chip_sw_all_escalation_resets.286471181
Short name	T86
Test name
Test status
Simulation time	5588839388 ps
CPU time	678.01 seconds
Started	Jun 09 03:47:15 PM PDT 24
Finished	Jun 09 03:58:33 PM PDT 24
Peak memory	647820 kb
Host	smart-6827ce91-d028-41c6-94af-3efeb2d79894
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 286471181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.286471181
Directory	/workspace/63.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2358917852
Short name	T28
Test name
Test status
Simulation time	3498281906 ps
CPU time	381.23 seconds
Started	Jun 09 03:50:42 PM PDT 24
Finished	Jun 09 03:57:04 PM PDT 24
Peak memory	646500 kb
Host	smart-902adb0f-f2c8-4a3f-be58-547c054765a6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358917852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2358917852
Directory	/workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3911944997
Short name	T241
Test name
Test status
Simulation time	5144322400 ps
CPU time	527.85 seconds
Started	Jun 09 03:12:20 PM PDT 24
Finished	Jun 09 03:21:09 PM PDT 24
Peak memory	643376 kb
Host	smart-3904f12a-4c8e-4bd9-b226-5e862fe6fcca
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3911944997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3911944997
Directory	/workspace/0.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2997344804
Short name	T459
Test name
Test status
Simulation time	4378912696 ps
CPU time	390.54 seconds
Started	Jun 09 03:14:43 PM PDT 24
Finished	Jun 09 03:21:14 PM PDT 24
Peak memory	646860 kb
Host	smart-088a399c-1f88-42a4-8a1b-ff5cc49d17d7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997344804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2997344804
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3464831748
Short name	T511
Test name
Test status
Simulation time	3709432180 ps
CPU time	458.03 seconds
Started	Jun 09 03:23:18 PM PDT 24
Finished	Jun 09 03:30:56 PM PDT 24
Peak memory	646520 kb
Host	smart-d5e5def3-af02-4d69-932d-a628ff0ec47a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464831748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.3464831748
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2608504036
Short name	T822
Test name
Test status
Simulation time	5821289800 ps
CPU time	723.27 seconds
Started	Jun 09 03:17:39 PM PDT 24
Finished	Jun 09 03:29:43 PM PDT 24
Peak memory	643148 kb
Host	smart-c0f503ed-258c-469e-9b6b-d8a054e8d94d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2608504036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2608504036
Directory	/workspace/1.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3168185174
Short name	T457
Test name
Test status
Simulation time	4069044832 ps
CPU time	539.04 seconds
Started	Jun 09 03:43:14 PM PDT 24
Finished	Jun 09 03:52:13 PM PDT 24
Peak memory	646468 kb
Host	smart-0cdbbda3-25ba-4bb0-b011-5863b9fafdce
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168185174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3168185174
Directory	/workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1548188118
Short name	T449
Test name
Test status
Simulation time	4972113296 ps
CPU time	574.19 seconds
Started	Jun 09 03:45:19 PM PDT 24
Finished	Jun 09 03:54:53 PM PDT 24
Peak memory	647804 kb
Host	smart-31498019-933a-4df7-99bc-d1396dfff23b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1548188118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.1548188118
Directory	/workspace/10.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3267179328
Short name	T476
Test name
Test status
Simulation time	3570175256 ps
CPU time	429.35 seconds
Started	Jun 09 03:42:10 PM PDT 24
Finished	Jun 09 03:49:19 PM PDT 24
Peak memory	646776 kb
Host	smart-4d18d91c-6b40-4c12-8657-ae3dcbc71120
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267179328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3267179328
Directory	/workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1131756226
Short name	T508
Test name
Test status
Simulation time	6425414976 ps
CPU time	817.76 seconds
Started	Jun 09 03:43:40 PM PDT 24
Finished	Jun 09 03:57:19 PM PDT 24
Peak memory	647780 kb
Host	smart-6bfd9197-e0c6-474c-b538-f8e015b2fc05
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1131756226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1131756226
Directory	/workspace/11.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1901480897
Short name	T140
Test name
Test status
Simulation time	3881380128 ps
CPU time	458.97 seconds
Started	Jun 09 03:43:49 PM PDT 24
Finished	Jun 09 03:51:29 PM PDT 24
Peak memory	646488 kb
Host	smart-a2285277-0156-40dc-9a61-965db438aead
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901480897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1901480897
Directory	/workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3380901081
Short name	T501
Test name
Test status
Simulation time	5636245350 ps
CPU time	799.43 seconds
Started	Jun 09 03:41:59 PM PDT 24
Finished	Jun 09 03:55:19 PM PDT 24
Peak memory	647864 kb
Host	smart-b6401120-8705-429a-8bae-4de8d5a06d27
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3380901081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3380901081
Directory	/workspace/12.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4008377974
Short name	T435
Test name
Test status
Simulation time	4028877724 ps
CPU time	465.54 seconds
Started	Jun 09 03:43:02 PM PDT 24
Finished	Jun 09 03:50:48 PM PDT 24
Peak memory	646540 kb
Host	smart-56cfcb30-93f7-4c01-9d8f-057531362cb6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008377974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4008377974
Directory	/workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1330486423
Short name	T522
Test name
Test status
Simulation time	3930254332 ps
CPU time	438.46 seconds
Started	Jun 09 03:42:47 PM PDT 24
Finished	Jun 09 03:50:06 PM PDT 24
Peak memory	646448 kb
Host	smart-44548728-d658-4725-9d12-c05f6713fa6a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330486423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1330486423
Directory	/workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113086690
Short name	T490
Test name
Test status
Simulation time	3366338200 ps
CPU time	446.46 seconds
Started	Jun 09 03:46:34 PM PDT 24
Finished	Jun 09 03:54:00 PM PDT 24
Peak memory	646612 kb
Host	smart-0416bbed-7155-45e1-acc4-afa411536c3c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113086690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2113086690
Directory	/workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3351892672
Short name	T480
Test name
Test status
Simulation time	5512452000 ps
CPU time	692.18 seconds
Started	Jun 09 03:42:50 PM PDT 24
Finished	Jun 09 03:54:23 PM PDT 24
Peak memory	643248 kb
Host	smart-1f7911c5-4d8d-439a-9b3a-110ed5b8c596
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3351892672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3351892672
Directory	/workspace/15.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3376496323
Short name	T138
Test name
Test status
Simulation time	4108560674 ps
CPU time	453.86 seconds
Started	Jun 09 03:44:38 PM PDT 24
Finished	Jun 09 03:52:12 PM PDT 24
Peak memory	646228 kb
Host	smart-08053693-7df7-4494-bfed-8afd6bac09af
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376496323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3376496323
Directory	/workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2529972466
Short name	T445
Test name
Test status
Simulation time	4063227010 ps
CPU time	398.48 seconds
Started	Jun 09 03:43:40 PM PDT 24
Finished	Jun 09 03:50:19 PM PDT 24
Peak memory	646148 kb
Host	smart-28faadc7-063c-4f09-91b4-c967ea3474f9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529972466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2529972466
Directory	/workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1860067165
Short name	T518
Test name
Test status
Simulation time	3722114632 ps
CPU time	407.37 seconds
Started	Jun 09 03:43:50 PM PDT 24
Finished	Jun 09 03:50:38 PM PDT 24
Peak memory	646464 kb
Host	smart-535dcd7a-7db2-45fe-8a70-06bf59b7fcda
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860067165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1860067165
Directory	/workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/19.chip_sw_all_escalation_resets.2692901465
Short name	T473
Test name
Test status
Simulation time	6128367088 ps
CPU time	580 seconds
Started	Jun 09 03:43:04 PM PDT 24
Finished	Jun 09 03:52:44 PM PDT 24
Peak memory	647828 kb
Host	smart-a467f2f9-a2cc-4ed1-b63c-6cb2503ade2e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2692901465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2692901465
Directory	/workspace/19.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2926075210
Short name	T439
Test name
Test status
Simulation time	4070895412 ps
CPU time	381.87 seconds
Started	Jun 09 03:32:48 PM PDT 24
Finished	Jun 09 03:39:10 PM PDT 24
Peak memory	646172 kb
Host	smart-d06b0acd-9be0-4921-b2e8-af53628df58f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926075210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.2926075210
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/2.chip_sw_all_escalation_resets.293915698
Short name	T333
Test name
Test status
Simulation time	5818281752 ps
CPU time	600.34 seconds
Started	Jun 09 03:30:04 PM PDT 24
Finished	Jun 09 03:40:05 PM PDT 24
Peak memory	647684 kb
Host	smart-59cf0cb5-d4af-45d5-a890-9166df17ad6a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 293915698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.293915698
Directory	/workspace/2.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2092880886
Short name	T500
Test name
Test status
Simulation time	3711086000 ps
CPU time	471.11 seconds
Started	Jun 09 03:46:10 PM PDT 24
Finished	Jun 09 03:54:02 PM PDT 24
Peak memory	646356 kb
Host	smart-3547e8a7-4e0c-49fd-bf33-597272d24fc4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092880886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2092880886
Directory	/workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.366265196
Short name	T512
Test name
Test status
Simulation time	3707493896 ps
CPU time	389.78 seconds
Started	Jun 09 03:45:08 PM PDT 24
Finished	Jun 09 03:51:39 PM PDT 24
Peak memory	646484 kb
Host	smart-26413ced-2cd5-42b4-a04d-b4e8cb260160
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366265196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_s w_alert_handler_lpg_sleep_mode_alerts.366265196
Directory	/workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3459379761
Short name	T964
Test name
Test status
Simulation time	3337061232 ps
CPU time	315 seconds
Started	Jun 09 03:43:49 PM PDT 24
Finished	Jun 09 03:49:05 PM PDT 24
Peak memory	646548 kb
Host	smart-2ca2c7df-5714-4f09-b333-1181d70a91f7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459379761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3459379761
Directory	/workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1358155807
Short name	T246
Test name
Test status
Simulation time	3870526796 ps
CPU time	490.38 seconds
Started	Jun 09 03:44:46 PM PDT 24
Finished	Jun 09 03:52:57 PM PDT 24
Peak memory	646500 kb
Host	smart-e4e1b6f2-6329-421d-b78e-2f0c1ec35ef2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358155807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1358155807
Directory	/workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3635623027
Short name	T478
Test name
Test status
Simulation time	3879980882 ps
CPU time	477.09 seconds
Started	Jun 09 03:45:21 PM PDT 24
Finished	Jun 09 03:53:19 PM PDT 24
Peak memory	646916 kb
Host	smart-514722e9-05a7-4441-9bb4-d7cde24afc86
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635623027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3635623027
Directory	/workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/26.chip_sw_all_escalation_resets.1072630940
Short name	T455
Test name
Test status
Simulation time	5830621950 ps
CPU time	620.85 seconds
Started	Jun 09 03:46:24 PM PDT 24
Finished	Jun 09 03:56:45 PM PDT 24
Peak memory	647620 kb
Host	smart-77bceb92-1b22-4253-88ba-908a8f09e92e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1072630940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.1072630940
Directory	/workspace/26.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.987957398
Short name	T497
Test name
Test status
Simulation time	3019197736 ps
CPU time	478.28 seconds
Started	Jun 09 03:44:44 PM PDT 24
Finished	Jun 09 03:52:43 PM PDT 24
Peak memory	646620 kb
Host	smart-cde248ad-83c1-4f4f-9654-5cf55f7e8024
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987957398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s w_alert_handler_lpg_sleep_mode_alerts.987957398
Directory	/workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/28.chip_sw_all_escalation_resets.772444377
Short name	T394
Test name
Test status
Simulation time	5287157640 ps
CPU time	684.19 seconds
Started	Jun 09 03:45:58 PM PDT 24
Finished	Jun 09 03:57:24 PM PDT 24
Peak memory	648032 kb
Host	smart-8fad2418-3775-4a84-829d-cd1e962351f2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 772444377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.772444377
Directory	/workspace/28.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2595456275
Short name	T420
Test name
Test status
Simulation time	3657170668 ps
CPU time	384.4 seconds
Started	Jun 09 03:46:38 PM PDT 24
Finished	Jun 09 03:53:02 PM PDT 24
Peak memory	646828 kb
Host	smart-43ab201f-51b2-4156-bc79-72585210a1d3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595456275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2595456275
Directory	/workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/3.chip_sw_all_escalation_resets.3598415291
Short name	T514
Test name
Test status
Simulation time	6160134388 ps
CPU time	678.9 seconds
Started	Jun 09 03:39:26 PM PDT 24
Finished	Jun 09 03:50:45 PM PDT 24
Peak memory	643212 kb
Host	smart-3ae1a70e-b3f1-4b5b-8ae0-234493f3fef0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3598415291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3598415291
Directory	/workspace/3.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/31.chip_sw_all_escalation_resets.2690780400
Short name	T344
Test name
Test status
Simulation time	5388028536 ps
CPU time	821.67 seconds
Started	Jun 09 03:45:46 PM PDT 24
Finished	Jun 09 03:59:28 PM PDT 24
Peak memory	647924 kb
Host	smart-70fda2e7-71c9-4467-9ac6-cde0f8af0968
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2690780400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.2690780400
Directory	/workspace/31.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3641742516
Short name	T471
Test name
Test status
Simulation time	3403962076 ps
CPU time	408.24 seconds
Started	Jun 09 03:44:15 PM PDT 24
Finished	Jun 09 03:51:03 PM PDT 24
Peak memory	646192 kb
Host	smart-ce4510d5-9611-405d-a890-6460c5cb1c21
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641742516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3641742516
Directory	/workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/32.chip_sw_all_escalation_resets.2710363070
Short name	T524
Test name
Test status
Simulation time	5198136038 ps
CPU time	565.41 seconds
Started	Jun 09 03:44:37 PM PDT 24
Finished	Jun 09 03:54:04 PM PDT 24
Peak memory	643028 kb
Host	smart-a0b1e70c-a7d2-4e45-9538-4c4a34ec3dcc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2710363070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.2710363070
Directory	/workspace/32.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1002334582
Short name	T132
Test name
Test status
Simulation time	3893366624 ps
CPU time	387.51 seconds
Started	Jun 09 03:44:36 PM PDT 24
Finished	Jun 09 03:51:04 PM PDT 24
Peak memory	647068 kb
Host	smart-fb1ac040-6703-44fd-ac76-e70129f89476
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002334582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1002334582
Directory	/workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/35.chip_sw_all_escalation_resets.2396689117
Short name	T267
Test name
Test status
Simulation time	5320415938 ps
CPU time	530.34 seconds
Started	Jun 09 03:44:26 PM PDT 24
Finished	Jun 09 03:53:16 PM PDT 24
Peak memory	648008 kb
Host	smart-6038b77f-62b0-4f10-b9f2-db10b0332043
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2396689117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2396689117
Directory	/workspace/35.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/37.chip_sw_all_escalation_resets.402827661
Short name	T461
Test name
Test status
Simulation time	5762020144 ps
CPU time	699.87 seconds
Started	Jun 09 03:46:01 PM PDT 24
Finished	Jun 09 03:57:42 PM PDT 24
Peak memory	647856 kb
Host	smart-541408c3-1915-4087-b8d5-1fa0f546f5b6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 402827661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.402827661
Directory	/workspace/37.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.772069387
Short name	T517
Test name
Test status
Simulation time	3224454824 ps
CPU time	400.12 seconds
Started	Jun 09 03:48:16 PM PDT 24
Finished	Jun 09 03:54:56 PM PDT 24
Peak memory	646560 kb
Host	smart-ba6bee16-06bd-4d8f-ab6f-dfd17dd25c3a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772069387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s w_alert_handler_lpg_sleep_mode_alerts.772069387
Directory	/workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/39.chip_sw_all_escalation_resets.358932714
Short name	T265
Test name
Test status
Simulation time	5382047880 ps
CPU time	565.13 seconds
Started	Jun 09 03:44:57 PM PDT 24
Finished	Jun 09 03:54:23 PM PDT 24
Peak memory	643560 kb
Host	smart-96f048fa-4acb-4ebd-ae4d-77dc15bec03c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 358932714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.358932714
Directory	/workspace/39.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.327899031
Short name	T447
Test name
Test status
Simulation time	3908883720 ps
CPU time	440.31 seconds
Started	Jun 09 03:44:23 PM PDT 24
Finished	Jun 09 03:51:43 PM PDT 24
Peak memory	646204 kb
Host	smart-d687472b-c3b1-448c-aa23-06507f50b032
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327899031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw _alert_handler_lpg_sleep_mode_alerts.327899031
Directory	/workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2652527926
Short name	T528
Test name
Test status
Simulation time	3876861270 ps
CPU time	336.94 seconds
Started	Jun 09 03:45:38 PM PDT 24
Finished	Jun 09 03:51:15 PM PDT 24
Peak memory	646604 kb
Host	smart-437da741-91b3-4afa-b03d-720eba9b791b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652527926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2652527926
Directory	/workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2546635394
Short name	T465
Test name
Test status
Simulation time	3849388296 ps
CPU time	359.05 seconds
Started	Jun 09 03:47:25 PM PDT 24
Finished	Jun 09 03:53:25 PM PDT 24
Peak memory	646372 kb
Host	smart-bbcd170f-61d4-4b9b-ae3c-66cc7910b6dd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546635394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2546635394
Directory	/workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2919245634
Short name	T452
Test name
Test status
Simulation time	5175604994 ps
CPU time	680.95 seconds
Started	Jun 09 03:46:16 PM PDT 24
Finished	Jun 09 03:57:37 PM PDT 24
Peak memory	647732 kb
Host	smart-6e234c48-1a61-4e2a-bb78-c90495fbdc73
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2919245634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.2919245634
Directory	/workspace/42.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/43.chip_sw_all_escalation_resets.3783317923
Short name	T505
Test name
Test status
Simulation time	4630139620 ps
CPU time	500.22 seconds
Started	Jun 09 03:46:23 PM PDT 24
Finished	Jun 09 03:54:44 PM PDT 24
Peak memory	643260 kb
Host	smart-3c23ee0f-91cd-4802-8ad5-bb704cacd3f3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3783317923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3783317923
Directory	/workspace/43.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3335720367
Short name	T382
Test name
Test status
Simulation time	3945533592 ps
CPU time	482.93 seconds
Started	Jun 09 03:46:07 PM PDT 24
Finished	Jun 09 03:54:10 PM PDT 24
Peak memory	646228 kb
Host	smart-89c5201a-1eac-4ef7-ba4e-8942eeba2934
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335720367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3335720367
Directory	/workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1869536537
Short name	T513
Test name
Test status
Simulation time	5464208642 ps
CPU time	563.53 seconds
Started	Jun 09 03:47:23 PM PDT 24
Finished	Jun 09 03:56:48 PM PDT 24
Peak memory	647832 kb
Host	smart-2d21ad32-c455-4d8a-9336-db4d1b8c3beb
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1869536537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.1869536537
Directory	/workspace/52.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/56.chip_sw_all_escalation_resets.2417423165
Short name	T994
Test name
Test status
Simulation time	4739114208 ps
CPU time	736.75 seconds
Started	Jun 09 03:47:20 PM PDT 24
Finished	Jun 09 03:59:37 PM PDT 24
Peak memory	643148 kb
Host	smart-9293b988-eaaf-4339-b627-b0fe2d21e522
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2417423165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2417423165
Directory	/workspace/56.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2101383953
Short name	T307
Test name
Test status
Simulation time	4118407942 ps
CPU time	455.12 seconds
Started	Jun 09 03:48:10 PM PDT 24
Finished	Jun 09 03:55:46 PM PDT 24
Peak memory	646244 kb
Host	smart-d45052ec-4d1b-445d-8d01-b8a42fcc61ea
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101383953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2101383953
Directory	/workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.334622939
Short name	T306
Test name
Test status
Simulation time	4061825472 ps
CPU time	400.07 seconds
Started	Jun 09 03:47:24 PM PDT 24
Finished	Jun 09 03:54:05 PM PDT 24
Peak memory	646352 kb
Host	smart-676677df-bf91-45e0-b131-107f786fc865
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334622939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_s w_alert_handler_lpg_sleep_mode_alerts.334622939
Directory	/workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3358773651
Short name	T415
Test name
Test status
Simulation time	3681664600 ps
CPU time	438.22 seconds
Started	Jun 09 03:47:33 PM PDT 24
Finished	Jun 09 03:54:52 PM PDT 24
Peak memory	646280 kb
Host	smart-3cbe2d36-775d-4aa4-9b10-ec4b5c0fb947
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358773651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3358773651
Directory	/workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2537490523
Short name	T434
Test name
Test status
Simulation time	4123690500 ps
CPU time	488.56 seconds
Started	Jun 09 03:47:51 PM PDT 24
Finished	Jun 09 03:55:59 PM PDT 24
Peak memory	646972 kb
Host	smart-a8cc16c8-3196-4218-ae8d-d1ae54de9a0e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537490523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2537490523
Directory	/workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3418722650
Short name	T492
Test name
Test status
Simulation time	3402837712 ps
CPU time	326.81 seconds
Started	Jun 09 03:48:56 PM PDT 24
Finished	Jun 09 03:54:23 PM PDT 24
Peak memory	646864 kb
Host	smart-7e12288d-6099-46dc-b4f7-0149fab2035c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418722650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3418722650
Directory	/workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2887727384
Short name	T477
Test name
Test status
Simulation time	3701772628 ps
CPU time	423.28 seconds
Started	Jun 09 03:48:22 PM PDT 24
Finished	Jun 09 03:55:25 PM PDT 24
Peak memory	646768 kb
Host	smart-931512e7-00ef-479f-a2d7-7e3f55afd698
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887727384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2887727384
Directory	/workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/7.chip_sw_all_escalation_resets.147754154
Short name	T268
Test name
Test status
Simulation time	4758271266 ps
CPU time	554.98 seconds
Started	Jun 09 03:42:10 PM PDT 24
Finished	Jun 09 03:51:25 PM PDT 24
Peak memory	647604 kb
Host	smart-24241aa3-6cfb-4bd5-8aff-9a26b153107f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 147754154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.147754154
Directory	/workspace/7.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/72.chip_sw_all_escalation_resets.2829468795
Short name	T467
Test name
Test status
Simulation time	4649153200 ps
CPU time	640.44 seconds
Started	Jun 09 03:48:32 PM PDT 24
Finished	Jun 09 03:59:13 PM PDT 24
Peak memory	647740 kb
Host	smart-6d97bdc3-2af2-4173-857d-e934f481f77b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2829468795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.2829468795
Directory	/workspace/72.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4173175435
Short name	T503
Test name
Test status
Simulation time	3471786550 ps
CPU time	354.6 seconds
Started	Jun 09 03:48:19 PM PDT 24
Finished	Jun 09 03:54:14 PM PDT 24
Peak memory	646644 kb
Host	smart-a3a77b75-7c10-4b75-b20f-d42b9b8fc342
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173175435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4173175435
Directory	/workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/77.chip_sw_all_escalation_resets.2811127344
Short name	T464
Test name
Test status
Simulation time	5403845256 ps
CPU time	699.71 seconds
Started	Jun 09 03:48:18 PM PDT 24
Finished	Jun 09 03:59:58 PM PDT 24
Peak memory	647776 kb
Host	smart-33439e50-4a61-4baa-99c5-b9b9f6c62d43
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2811127344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.2811127344
Directory	/workspace/77.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3783905183
Short name	T282
Test name
Test status
Simulation time	4393712058 ps
CPU time	409 seconds
Started	Jun 09 03:51:05 PM PDT 24
Finished	Jun 09 03:57:54 PM PDT 24
Peak memory	646844 kb
Host	smart-e1a622ae-c2a1-407e-bc0d-c9255c34d5ad
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783905183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3783905183
Directory	/workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2937782671
Short name	T460
Test name
Test status
Simulation time	5692626488 ps
CPU time	612.28 seconds
Started	Jun 09 03:50:13 PM PDT 24
Finished	Jun 09 04:00:26 PM PDT 24
Peak memory	648136 kb
Host	smart-66a8d8e6-cc60-4afc-bf72-9b6d94a74715
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2937782671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2937782671
Directory	/workspace/85.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/89.chip_sw_all_escalation_resets.218958979
Short name	T507
Test name
Test status
Simulation time	4129107312 ps
CPU time	523.2 seconds
Started	Jun 09 03:50:20 PM PDT 24
Finished	Jun 09 03:59:04 PM PDT 24
Peak memory	647348 kb
Host	smart-2b365f0c-9ce2-406c-9754-7644c02048a2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 218958979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.218958979
Directory	/workspace/89.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/96.chip_sw_all_escalation_resets.2718048753
Short name	T454
Test name
Test status
Simulation time	4542649338 ps
CPU time	597.08 seconds
Started	Jun 09 03:50:52 PM PDT 24
Finished	Jun 09 04:00:49 PM PDT 24
Peak memory	643308 kb
Host	smart-aa3c6283-cd7c-492d-80c0-67a3f49779d3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2718048753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2718048753
Directory	/workspace/96.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3789552658
Short name	T486
Test name
Test status
Simulation time	4467672132 ps
CPU time	625.79 seconds
Started	Jun 09 03:50:43 PM PDT 24
Finished	Jun 09 04:01:09 PM PDT 24
Peak memory	647668 kb
Host	smart-53f3075b-7f4f-4865-9c4d-70cd542b57aa
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3789552658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3789552658
Directory	/workspace/97.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.522880565
Short name	T279
Test name
Test status
Simulation time	5986423402 ps
CPU time	832.77 seconds
Started	Jun 09 03:16:38 PM PDT 24
Finished	Jun 09 03:30:31 PM PDT 24
Peak memory	608464 kb
Host	smart-072bcd1f-d840-4e65-8a86-f4045b5b0328
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=522880565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.522880565
Directory	/workspace/1.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_power_idle_load.3776072770
Short name	T315
Test name
Test status
Simulation time	3835420282 ps
CPU time	746.74 seconds
Started	Jun 09 03:15:42 PM PDT 24
Finished	Jun 09 03:28:09 PM PDT 24
Peak memory	606448 kb
Host	smart-e774a0ea-cc33-4073-a1b1-d4020eea63f4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776072770 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.3776072770
Directory	/workspace/0.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3566407008
Short name	T200
Test name
Test status
Simulation time	43605023852 ps
CPU time	5503.23 seconds
Started	Jun 09 03:17:48 PM PDT 24
Finished	Jun 09 04:49:32 PM PDT 24
Peak memory	621960 kb
Host	smart-af4fe55d-4b2c-46d2-9856-b0e794aecfcb
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3566407008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.3566407008
Directory	/workspace/0.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_0.3189936612
Short name	T176
Test name
Test status
Simulation time	5337978568 ps
CPU time	953.78 seconds
Started	Jun 09 03:11:22 PM PDT 24
Finished	Jun 09 03:27:16 PM PDT 24
Peak memory	607532 kb
Host	smart-5df88947-3bdb-4951-b383-b069be024d22
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189936612 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.3189936612
Directory	/workspace/0.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2225773827
Short name	T163
Test name
Test status
Simulation time	9651658280 ps
CPU time	1285.35 seconds
Started	Jun 09 03:16:56 PM PDT 24
Finished	Jun 09 03:38:21 PM PDT 24
Peak memory	607508 kb
Host	smart-1967d040-612b-4d04-b6ce-7cf699de6342
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22257738 27 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2225773827
Directory	/workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1321023714
Short name	T190
Test name
Test status
Simulation time	3582484001 ps
CPU time	258.13 seconds
Started	Jun 09 03:11:47 PM PDT 24
Finished	Jun 09 03:16:06 PM PDT 24
Peak memory	617956 kb
Host	smart-bf01e3b4-36b5-4013-ba3c-427e4210d5bd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13210237 14 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.1321023714
Directory	/workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_testunlock0.3457162466
Short name	T120
Test name
Test status
Simulation time	3505491728 ps
CPU time	279.96 seconds
Started	Jun 09 03:25:28 PM PDT 24
Finished	Jun 09 03:30:08 PM PDT 24
Peak memory	620080 kb
Host	smart-49d4f589-cdaa-47a2-abbc-b86e168baf8a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457162466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.3457162466
Directory	/workspace/1.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.651993880
Short name	T72
Test name
Test status
Simulation time	4839088792 ps
CPU time	562.02 seconds
Started	Jun 09 03:12:34 PM PDT 24
Finished	Jun 09 03:21:56 PM PDT 24
Peak memory	610604 kb
Host	smart-2719e487-4ac2-4adb-8495-165349cea37f
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651993880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.651993880
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2541049541
Short name	T25
Test name
Test status
Simulation time	12693100056 ps
CPU time	2816.85 seconds
Started	Jun 09 03:15:01 PM PDT 24
Finished	Jun 09 04:02:00 PM PDT 24
Peak memory	616964 kb
Host	smart-8cc35b6c-8c16-490f-8fab-7538cf5ef6b0
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410 49541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.2541049541
Directory	/workspace/0.rom_e2e_jtag_debug_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_app_rom.2836564730
Short name	T732
Test name
Test status
Simulation time	2292322280 ps
CPU time	179.29 seconds
Started	Jun 09 03:14:20 PM PDT 24
Finished	Jun 09 03:17:20 PM PDT 24
Peak memory	606316 kb
Host	smart-206011ca-aa4e-4848-9c7b-39f70dce6a5f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836564730 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.2836564730
Directory	/workspace/0.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_20.1399861764
Short name	T201
Test name
Test status
Simulation time	5369989000 ps
CPU time	794.83 seconds
Started	Jun 09 03:38:43 PM PDT 24
Finished	Jun 09 03:51:58 PM PDT 24
Peak memory	607344 kb
Host	smart-575201cd-cf35-4984-abf0-5744dab86101
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399861764 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.1399861764
Directory	/workspace/2.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3671295428
Short name	T197
Test name
Test status
Simulation time	42514378080 ps
CPU time	5150.8 seconds
Started	Jun 09 03:18:53 PM PDT 24
Finished	Jun 09 04:44:45 PM PDT 24
Peak memory	621048 kb
Host	smart-5fdbce92-d087-4f21-af7b-51136bddea3f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3671295428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.3671295428
Directory	/workspace/1.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2461649070
Short name	T50
Test name
Test status
Simulation time	31779832174 ps
CPU time	7026.55 seconds
Started	Jun 09 03:14:28 PM PDT 24
Finished	Jun 09 05:11:35 PM PDT 24
Peak memory	606996 kb
Host	smart-2ae49658-d4f9-4900-8679-130db36feb5e
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2461649070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2461649070
Directory	/workspace/0.chip_sw_usbdev_pincfg/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1404917588
Short name	T63
Test name
Test status
Simulation time	6552997664 ps
CPU time	672.25 seconds
Started	Jun 09 03:12:45 PM PDT 24
Finished	Jun 09 03:23:58 PM PDT 24
Peak memory	607360 kb
Host	smart-26e5c4f7-88b8-4c6a-9554-73cb166d87a8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404917588 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1404917588
Directory	/workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_0.4068548709
Short name	T177
Test name
Test status
Simulation time	6308868114 ps
CPU time	1022.66 seconds
Started	Jun 09 03:25:43 PM PDT 24
Finished	Jun 09 03:42:46 PM PDT 24
Peak memory	606724 kb
Host	smart-ff537ebe-1759-48db-a1a0-e396765455e8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068548709 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.4068548709
Directory	/workspace/1.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/21.chip_sw_all_escalation_resets.1978810847
Short name	T309
Test name
Test status
Simulation time	5619101322 ps
CPU time	774.03 seconds
Started	Jun 09 03:44:03 PM PDT 24
Finished	Jun 09 03:56:58 PM PDT 24
Peak memory	608152 kb
Host	smart-f0309804-dca9-4974-afaf-41cea7352148
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1978810847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1978810847
Directory	/workspace/21.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2882716820
Short name	T14
Test name
Test status
Simulation time	3712608414 ps
CPU time	299.43 seconds
Started	Jun 09 03:11:14 PM PDT 24
Finished	Jun 09 03:16:14 PM PDT 24
Peak memory	606676 kb
Host	smart-cc990e91-54d1-476e-b13f-e4da54f53d12
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882716820 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.2882716820
Directory	/workspace/0.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1169068722
Short name	T234
Test name
Test status
Simulation time	50904531725 ps
CPU time	5366.74 seconds
Started	Jun 09 03:30:52 PM PDT 24
Finished	Jun 09 05:00:19 PM PDT 24
Peak memory	614868 kb
Host	smart-91078af5-35ae-47e3-b2c6-9afd6a5e231c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169068722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.1169068722
Directory	/workspace/2.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1896898806
Short name	T16
Test name
Test status
Simulation time	6478638216 ps
CPU time	579.5 seconds
Started	Jun 09 03:31:33 PM PDT 24
Finished	Jun 09 03:41:12 PM PDT 24
Peak memory	608096 kb
Host	smart-9f869651-dbea-43aa-a4e1-92d4f72cea68
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896898806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.1896898806
Directory	/workspace/2.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.4066237491
Short name	T32
Test name
Test status
Simulation time	4651224848 ps
CPU time	547.39 seconds
Started	Jun 09 03:18:08 PM PDT 24
Finished	Jun 09 03:27:15 PM PDT 24
Peak memory	615632 kb
Host	smart-617ebb6a-6fe4-4ff7-8bf7-72a64dca3514
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066237491 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.4066237491
Directory	/workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4207543763
Short name	T161
Test name
Test status
Simulation time	6591950904 ps
CPU time	754.52 seconds
Started	Jun 09 03:24:06 PM PDT 24
Finished	Jun 09 03:36:41 PM PDT 24
Peak memory	608336 kb
Host	smart-033c9ef5-15c6-4f3a-881f-69a2f6d8ecac
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42075437 63 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.4207543763
Directory	/workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3338211958
Short name	T319
Test name
Test status
Simulation time	77357124170 ps
CPU time	13387.5 seconds
Started	Jun 09 03:14:16 PM PDT 24
Finished	Jun 09 06:57:26 PM PDT 24
Peak memory	633168 kb
Host	smart-48f30300-7f14-4c89-9b72-0a135b71721e
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3338211958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.3338211958
Directory	/workspace/0.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_10.3310964633
Short name	T171
Test name
Test status
Simulation time	3889577730 ps
CPU time	643.38 seconds
Started	Jun 09 03:27:39 PM PDT 24
Finished	Jun 09 03:38:23 PM PDT 24
Peak memory	606412 kb
Host	smart-711246d6-8bfa-424f-aa75-9ce444f5b66c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310964633 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.3310964633
Directory	/workspace/1.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1149393720
Short name	T182
Test name
Test status
Simulation time	2353187044 ps
CPU time	218.84 seconds
Started	Jun 09 03:11:44 PM PDT 24
Finished	Jun 09 03:15:23 PM PDT 24
Peak memory	617916 kb
Host	smart-8d3ae59d-4d0c-416b-81e6-133fa2769dff
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149393720 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1149393720
Directory	/workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.711324220
Short name	T164
Test name
Test status
Simulation time	18823696081 ps
CPU time	2508.18 seconds
Started	Jun 09 03:27:15 PM PDT 24
Finished	Jun 09 04:09:04 PM PDT 24
Peak memory	608304 kb
Host	smart-7a587474-183d-40eb-ac99-49802e66ce42
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711324220 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.711324220
Directory	/workspace/1.chip_sw_ast_clk_rst_inputs/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2797419534
Short name	T67
Test name
Test status
Simulation time	3544395897 ps
CPU time	347.09 seconds
Started	Jun 09 03:10:55 PM PDT 24
Finished	Jun 09 03:16:43 PM PDT 24
Peak memory	614812 kb
Host	smart-e8b2119b-4ab0-45da-90f2-3f42f2be039f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797419534 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2797419534
Directory	/workspace/0.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2611857761
Short name	T286
Test name
Test status
Simulation time	4651240544 ps
CPU time	677.48 seconds
Started	Jun 09 03:11:21 PM PDT 24
Finished	Jun 09 03:22:39 PM PDT 24
Peak memory	615444 kb
Host	smart-ef96dd82-b131-44c9-bea4-f28020e5f122
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611857761 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2611857761
Directory	/workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1039856610
Short name	T34
Test name
Test status
Simulation time	4694601650 ps
CPU time	536.18 seconds
Started	Jun 09 03:16:14 PM PDT 24
Finished	Jun 09 03:25:12 PM PDT 24
Peak memory	607344 kb
Host	smart-7f5bbb1c-fada-466d-8ba9-6dd4bf6ae47e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10 39856610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.1039856610
Directory	/workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.834155184
Short name	T198
Test name
Test status
Simulation time	43586790650 ps
CPU time	5060.25 seconds
Started	Jun 09 03:29:37 PM PDT 24
Finished	Jun 09 04:53:59 PM PDT 24
Peak memory	616044 kb
Host	smart-e5ab3812-9ccd-4166-b849-d7346300e21e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=834155184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.834155184
Directory	/workspace/2.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.988083379
Short name	T89
Test name
Test status
Simulation time	2506447710 ps
CPU time	289.22 seconds
Started	Jun 09 03:20:33 PM PDT 24
Finished	Jun 09 03:25:23 PM PDT 24
Peak memory	606328 kb
Host	smart-bc4ac335-d0ae-420f-8f24-a3c9b271e387
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988083379 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.988083379
Directory	/workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.360468655
Short name	T183
Test name
Test status
Simulation time	2978402240 ps
CPU time	169.78 seconds
Started	Jun 09 03:20:24 PM PDT 24
Finished	Jun 09 03:23:14 PM PDT 24
Peak memory	617868 kb
Host	smart-823c7c6b-eed2-4f1f-9cc5-f1fc2b7ed09b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360468655 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.360468655
Directory	/workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.921483893
Short name	T125
Test name
Test status
Simulation time	3855819952 ps
CPU time	514.1 seconds
Started	Jun 09 03:12:12 PM PDT 24
Finished	Jun 09 03:20:46 PM PDT 24
Peak memory	606460 kb
Host	smart-c4783ee5-1164-4945-8301-81e905de30de
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921483 893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.921483893
Directory	/workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.745451600
Short name	T361
Test name
Test status
Simulation time	4603342294 ps
CPU time	658.16 seconds
Started	Jun 09 03:30:25 PM PDT 24
Finished	Jun 09 03:41:23 PM PDT 24
Peak memory	606976 kb
Host	smart-a347d206-002c-4a7e-8b21-ae5ed23ce169
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745451600 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.745451600
Directory	/workspace/2.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.429632482
Short name	T208
Test name
Test status
Simulation time	3759729380 ps
CPU time	649.5 seconds
Started	Jun 09 03:30:11 PM PDT 24
Finished	Jun 09 03:41:01 PM PDT 24
Peak memory	607492 kb
Host	smart-40f36ac3-9b93-40a3-8dbc-ada325c92bce
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429632482 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.429632482
Directory	/workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2455586025
Short name	T560
Test name
Test status
Simulation time	4255960000 ps
CPU time	607.69 seconds
Started	Jun 09 03:12:12 PM PDT 24
Finished	Jun 09 03:22:20 PM PDT 24
Peak memory	615236 kb
Host	smart-81ab709f-1b9e-455d-ae36-e4b1ee4d46e7
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455586025 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.2455586025
Directory	/workspace/0.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.546890483
Short name	T152
Test name
Test status
Simulation time	8355543182 ps
CPU time	2085.1 seconds
Started	Jun 09 03:24:34 PM PDT 24
Finished	Jun 09 03:59:20 PM PDT 24
Peak memory	606776 kb
Host	smart-7fc72d7d-b29a-4fb8-8d70-32bce6ae204e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=546890483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.546890483
Directory	/workspace/1.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1047722550
Short name	T429
Test name
Test status
Simulation time	6592999380 ps
CPU time	637.97 seconds
Started	Jun 09 03:16:51 PM PDT 24
Finished	Jun 09 03:27:29 PM PDT 24
Peak memory	617548 kb
Host	smart-4ed45f4e-ada6-4316-83cc-0e0d75c8e733
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047722550 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.1047722550
Directory	/workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1865006746
Short name	T15
Test name
Test status
Simulation time	23834865022 ps
CPU time	2062.51 seconds
Started	Jun 09 03:26:20 PM PDT 24
Finished	Jun 09 04:00:43 PM PDT 24
Peak memory	608456 kb
Host	smart-c4292858-c850-4d5a-9f4a-c644b6f1a40e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1865006746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1865006746
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_jtag_mem_access.349220838
Short name	T22
Test name
Test status
Simulation time	14065553752 ps
CPU time	1406.77 seconds
Started	Jun 09 03:04:25 PM PDT 24
Finished	Jun 09 03:27:52 PM PDT 24
Peak memory	606972 kb
Host	smart-8ca59005-a19a-4ae0-953c-ce137f58c368
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349220838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.349220838
Directory	/workspace/0.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/0.chip_sw_plic_sw_irq.113880480
Short name	T254
Test name
Test status
Simulation time	2980974272 ps
CPU time	243.37 seconds
Started	Jun 09 03:13:44 PM PDT 24
Finished	Jun 09 03:17:48 PM PDT 24
Peak memory	607008 kb
Host	smart-e0bc366e-539a-491e-b58f-37bdc10d204a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113880480 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_plic_sw_irq.113880480
Directory	/workspace/0.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_boot_mode.435121990
Short name	T392
Test name
Test status
Simulation time	2919241564 ps
CPU time	409.24 seconds
Started	Jun 09 03:10:29 PM PDT 24
Finished	Jun 09 03:17:19 PM PDT 24
Peak memory	607628 kb
Host	smart-fdcff878-e493-4a01-8f2c-1715797c7300
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435121990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_b oot_mode.435121990
Directory	/workspace/0.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1797541957
Short name	T346
Test name
Test status
Simulation time	10072260642 ps
CPU time	1759.74 seconds
Started	Jun 09 03:11:29 PM PDT 24
Finished	Jun 09 03:40:49 PM PDT 24
Peak memory	608652 kb
Host	smart-cac50e01-8ee5-4410-8449-b7816eb4d538
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797 541957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.1797541957
Directory	/workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.285510744
Short name	T210
Test name
Test status
Simulation time	5565909256 ps
CPU time	746.93 seconds
Started	Jun 09 03:13:18 PM PDT 24
Finished	Jun 09 03:25:45 PM PDT 24
Peak memory	606512 kb
Host	smart-dc9a78ef-057e-41e2-95ba-4a26c3cd830c
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285510744 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.285510744
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1373621355
Short name	T205
Test name
Test status
Simulation time	4751926900 ps
CPU time	699.35 seconds
Started	Jun 09 03:13:10 PM PDT 24
Finished	Jun 09 03:24:51 PM PDT 24
Peak memory	607748 kb
Host	smart-caf1f1cc-9402-4cda-9495-85d62a287b38
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373621355 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1373621355
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1704280016
Short name	T380
Test name
Test status
Simulation time	6601145130 ps
CPU time	497.16 seconds
Started	Jun 09 03:17:20 PM PDT 24
Finished	Jun 09 03:25:38 PM PDT 24
Peak memory	608652 kb
Host	smart-148c6bfc-7d0b-49d3-b5f8-feec5a336570
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1704280016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1704280016
Directory	/workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_20.3941415096
Short name	T202
Test name
Test status
Simulation time	4245617508 ps
CPU time	730.37 seconds
Started	Jun 09 03:26:17 PM PDT 24
Finished	Jun 09 03:38:28 PM PDT 24
Peak memory	606392 kb
Host	smart-78111833-a0cd-4cee-8ad0-42ca127278df
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941415096 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.3941415096
Directory	/workspace/1.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.979977673
Short name	T395
Test name
Test status
Simulation time	2764254714 ps
CPU time	264.92 seconds
Started	Jun 09 03:13:14 PM PDT 24
Finished	Jun 09 03:17:39 PM PDT 24
Peak memory	606308 kb
Host	smart-4d6ccb79-4fcc-49ff-99cd-9e35538f6f8b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979977673 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_hmac_enc_idle.979977673
Directory	/workspace/0.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3463277212
Short name	T824
Test name
Test status
Simulation time	7437532960 ps
CPU time	295.69 seconds
Started	Jun 09 03:11:05 PM PDT 24
Finished	Jun 09 03:16:01 PM PDT 24
Peak memory	607272 kb
Host	smart-8e55bfb7-09b1-4152-827b-629fd60cc08b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463277212 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3463277212
Directory	/workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2934948058
Short name	T719
Test name
Test status
Simulation time	6711612452 ps
CPU time	549.43 seconds
Started	Jun 09 03:35:06 PM PDT 24
Finished	Jun 09 03:44:15 PM PDT 24
Peak memory	607280 kb
Host	smart-b2cf5596-79d0-4897-9a61-4ae1b90a924f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2934948058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2934948058
Directory	/workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.929456889
Short name	T614
Test name
Test status
Simulation time	11318305457 ps
CPU time	2329.03 seconds
Started	Jun 09 03:44:55 PM PDT 24
Finished	Jun 09 04:23:45 PM PDT 24
Peak memory	607680 kb
Host	smart-3dc53862-b0e0-4cea-b030-2ee9a7b38a4e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929456889 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.rom_e2e_asm_init_test_unlocked0.929456889
Directory	/workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_dev.3558815318
Short name	T430
Test name
Test status
Simulation time	6999280056 ps
CPU time	742.9 seconds
Started	Jun 09 03:40:36 PM PDT 24
Finished	Jun 09 03:52:59 PM PDT 24
Peak memory	620072 kb
Host	smart-117e5734-9db4-4e56-9a57-ddf693610928
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3558815318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3558815318
Directory	/workspace/4.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3556531712
Short name	T356
Test name
Test status
Simulation time	3463838232 ps
CPU time	412.1 seconds
Started	Jun 09 03:12:51 PM PDT 24
Finished	Jun 09 03:19:43 PM PDT 24
Peak memory	606996 kb
Host	smart-b971305f-65a5-4d7b-ba04-63b6ed193cb9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556531712 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.3556531712
Directory	/workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest

Test location	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4213806934
Short name	T849
Test name
Test status
Simulation time	18513882140 ps
CPU time	413.09 seconds
Started	Jun 09 03:13:50 PM PDT 24
Finished	Jun 09 03:20:44 PM PDT 24
Peak memory	617288 kb
Host	smart-596f576c-f980-438c-8985-e39bb5c2865c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4213806934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4213806934
Directory	/workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3040986757
Short name	T668
Test name
Test status
Simulation time	6810683968 ps
CPU time	984.2 seconds
Started	Jun 09 03:13:03 PM PDT 24
Finished	Jun 09 03:29:27 PM PDT 24
Peak memory	608644 kb
Host	smart-e82b2c85-ab9f-4336-935b-1f104d408560
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3040986757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.3040986757
Directory	/workspace/0.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3116804603
Short name	T115
Test name
Test status
Simulation time	7002251441 ps
CPU time	767.52 seconds
Started	Jun 09 03:12:12 PM PDT 24
Finished	Jun 09 03:25:01 PM PDT 24
Peak memory	607956 kb
Host	smart-c399eb0a-e4d7-47f9-a3d5-904005ee501e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116804603 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3116804603
Directory	/workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.792815172
Short name	T858
Test name
Test status
Simulation time	7967008008 ps
CPU time	933.08 seconds
Started	Jun 09 03:11:53 PM PDT 24
Finished	Jun 09 03:27:26 PM PDT 24
Peak memory	613688 kb
Host	smart-10ae0ee3-52c8-4a8c-9cbc-d513ea4e2db7
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792815172 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.792815172
Directory	/workspace/0.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3067110338
Short name	T277
Test name
Test status
Simulation time	2112761860 ps
CPU time	93.22 seconds
Started	Jun 09 03:15:29 PM PDT 24
Finished	Jun 09 03:17:03 PM PDT 24
Peak memory	614020 kb
Host	smart-b90c64f9-4d45-4edb-9e8a-28e2fdf23efc
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3067110338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3067110338
Directory	/workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2243381566
Short name	T563
Test name
Test status
Simulation time	6402239336 ps
CPU time	493.54 seconds
Started	Jun 09 03:13:24 PM PDT 24
Finished	Jun 09 03:21:38 PM PDT 24
Peak memory	613996 kb
Host	smart-4b045e4e-a6a2-4081-86ae-75907cfaebae
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2243381566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2243381566
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3834911078
Short name	T184
Test name
Test status
Simulation time	2633986584 ps
CPU time	212.48 seconds
Started	Jun 09 03:33:52 PM PDT 24
Finished	Jun 09 03:37:25 PM PDT 24
Peak memory	619276 kb
Host	smart-bf908e23-6a11-4608-ad73-14da826a30c0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834911078 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.3834911078
Directory	/workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_10.1207196267
Short name	T172
Test name
Test status
Simulation time	3483313800 ps
CPU time	464.12 seconds
Started	Jun 09 03:13:01 PM PDT 24
Finished	Jun 09 03:20:46 PM PDT 24
Peak memory	606416 kb
Host	smart-7b8011c4-dbe5-41ab-922e-4e4a4e738228
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207196267 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.1207196267
Directory	/workspace/0.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3052513447
Short name	T311
Test name
Test status
Simulation time	5046620192 ps
CPU time	750.29 seconds
Started	Jun 09 03:12:36 PM PDT 24
Finished	Jun 09 03:25:08 PM PDT 24
Peak memory	606660 kb
Host	smart-34e22a74-260e-4366-9bff-4a09ffa41370
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30525 13447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.3052513447
Directory	/workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_gpio.2660752716
Short name	T54
Test name
Test status
Simulation time	4215384742 ps
CPU time	577.1 seconds
Started	Jun 09 03:29:01 PM PDT 24
Finished	Jun 09 03:38:38 PM PDT 24
Peak memory	607044 kb
Host	smart-4e3c5cb9-1284-4e70-8ee5-1f6843e0e00a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660752716 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.2660752716
Directory	/workspace/2.chip_sw_gpio/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2277915489
Short name	T280
Test name
Test status
Simulation time	2941840562 ps
CPU time	134.74 seconds
Started	Jun 09 03:39:55 PM PDT 24
Finished	Jun 09 03:42:11 PM PDT 24
Peak memory	643096 kb
Host	smart-aafb29fd-fc97-4d6c-9742-350e1fde97ca
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277915489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.2277915489
Directory	/workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.47783613
Short name	T328
Test name
Test status
Simulation time	11819991912 ps
CPU time	3655.87 seconds
Started	Jun 09 03:11:54 PM PDT 24
Finished	Jun 09 04:12:51 PM PDT 24
Peak memory	607784 kb
Host	smart-c3497d73-6f61-4439-9dc1-80f933de130e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47783 613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.47783613
Directory	/workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3463593087
Short name	T426
Test name
Test status
Simulation time	16866733846 ps
CPU time	3711.48 seconds
Started	Jun 09 03:12:04 PM PDT 24
Finished	Jun 09 04:13:57 PM PDT 24
Peak memory	606764 kb
Host	smart-3884281b-771c-497b-a176-3a77c177715c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3463593087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.3463593087
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2478661752
Short name	T289
Test name
Test status
Simulation time	3108609576 ps
CPU time	490.2 seconds
Started	Jun 09 03:13:02 PM PDT 24
Finished	Jun 09 03:21:13 PM PDT 24
Peak memory	606388 kb
Host	smart-3fb12183-ec96-4d54-8cd7-fac20c978ef0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478661752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2478661752
Directory	/workspace/0.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1374344697
Short name	T981
Test name
Test status
Simulation time	9055980502 ps
CPU time	894.9 seconds
Started	Jun 09 03:14:04 PM PDT 24
Finished	Jun 09 03:29:00 PM PDT 24
Peak memory	608388 kb
Host	smart-6e4f63e9-205e-49d8-9698-19225ddc0c2b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374344697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.1374344697
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.89192608
Short name	T251
Test name
Test status
Simulation time	22475340434 ps
CPU time	6975.39 seconds
Started	Jun 09 03:21:54 PM PDT 24
Finished	Jun 09 05:18:10 PM PDT 24
Peak memory	607680 kb
Host	smart-ffc74a60-60fa-404a-9b03-12c3ad385c27
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=89192608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.89192608
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

Test location	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.4143558074
Short name	T389
Test name
Test status
Simulation time	30771158800 ps
CPU time	6632.59 seconds
Started	Jun 09 03:39:54 PM PDT 24
Finished	Jun 09 05:30:27 PM PDT 24
Peak memory	607160 kb
Host	smart-2f91177c-313a-4fc9-9546-ddc130a2579e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143558074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.4143558074
Directory	/workspace/3.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1689805637
Short name	T244
Test name
Test status
Simulation time	2230202338 ps
CPU time	194.89 seconds
Started	Jun 09 03:12:10 PM PDT 24
Finished	Jun 09 03:15:25 PM PDT 24
Peak memory	607304 kb
Host	smart-18b661a6-f5f6-4c7f-a7b5-31de844ea5b9
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689805637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.1689805637
Directory	/workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/0.chip_sival_flash_info_access.3965050275
Short name	T144
Test name
Test status
Simulation time	3024859576 ps
CPU time	410.58 seconds
Started	Jun 09 03:12:08 PM PDT 24
Finished	Jun 09 03:18:59 PM PDT 24
Peak memory	606160 kb
Host	smart-c2afd105-1eaa-47e5-a184-02d37ef50862
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3965050275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3965050275
Directory	/workspace/0.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc.97604710
Short name	T541
Test name
Test status
Simulation time	2738592184 ps
CPU time	262.53 seconds
Started	Jun 09 03:11:05 PM PDT 24
Finished	Jun 09 03:15:28 PM PDT 24
Peak memory	606708 kb
Host	smart-f5c64159-0992-4cce-9fc1-19b59d7768c3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97604710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.97604710
Directory	/workspace/0.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2795279484
Short name	T608
Test name
Test status
Simulation time	2871997316 ps
CPU time	240.29 seconds
Started	Jun 09 03:13:53 PM PDT 24
Finished	Jun 09 03:17:54 PM PDT 24
Peak memory	606668 kb
Host	smart-de80e616-6620-4e60-ba0b-6f7254166ad3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795 279484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2795279484
Directory	/workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.220644505
Short name	T661
Test name
Test status
Simulation time	3033409116 ps
CPU time	201.55 seconds
Started	Jun 09 03:13:09 PM PDT 24
Finished	Jun 09 03:16:31 PM PDT 24
Peak memory	606860 kb
Host	smart-c8a10fce-09db-4b57-b768-1e60299de620
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220644505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.220644505
Directory	/workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_entropy.3898376377
Short name	T626
Test name
Test status
Simulation time	2799158322 ps
CPU time	276.85 seconds
Started	Jun 09 03:13:56 PM PDT 24
Finished	Jun 09 03:18:33 PM PDT 24
Peak memory	606712 kb
Host	smart-2e52175f-995f-4e2a-9890-909c1d8e0329
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898376377 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.3898376377
Directory	/workspace/0.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_idle.1590264753
Short name	T639
Test name
Test status
Simulation time	2703318140 ps
CPU time	237.05 seconds
Started	Jun 09 03:11:29 PM PDT 24
Finished	Jun 09 03:15:27 PM PDT 24
Peak memory	606304 kb
Host	smart-3f555ea3-43dd-447c-ac10-603d66d1f2ac
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590264753 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1590264753
Directory	/workspace/0.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_masking_off.2279963692
Short name	T696
Test name
Test status
Simulation time	3109487495 ps
CPU time	367.8 seconds
Started	Jun 09 03:14:30 PM PDT 24
Finished	Jun 09 03:20:39 PM PDT 24
Peak memory	607364 kb
Host	smart-9ae4ef94-2cd9-48bc-9a7f-fe1673000e98
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279963692 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2279963692
Directory	/workspace/0.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_smoketest.1223551971
Short name	T105
Test name
Test status
Simulation time	3009250416 ps
CPU time	188.47 seconds
Started	Jun 09 03:15:59 PM PDT 24
Finished	Jun 09 03:19:08 PM PDT 24
Peak memory	606496 kb
Host	smart-a1339b42-848a-4ccc-9fef-afa1ef5fa462
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223551971 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.1223551971
Directory	/workspace/0.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2268869737
Short name	T642
Test name
Test status
Simulation time	3148411842 ps
CPU time	261.44 seconds
Started	Jun 09 03:10:56 PM PDT 24
Finished	Jun 09 03:15:18 PM PDT 24
Peak memory	607532 kb
Host	smart-ba1060a2-bf99-46bb-b06c-ae3e10771dc2
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2268869737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.2268869737
Directory	/workspace/0.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3751729184
Short name	T946
Test name
Test status
Simulation time	5338799112 ps
CPU time	328.36 seconds
Started	Jun 09 03:10:14 PM PDT 24
Finished	Jun 09 03:15:43 PM PDT 24
Peak memory	614664 kb
Host	smart-662709af-d64f-4c1e-aa4d-76d084c1a951
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3751729184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3751729184
Directory	/workspace/0.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.691417885
Short name	T785
Test name
Test status
Simulation time	7946520324 ps
CPU time	2125.39 seconds
Started	Jun 09 03:14:20 PM PDT 24
Finished	Jun 09 03:49:47 PM PDT 24
Peak memory	608000 kb
Host	smart-78f12a48-6fec-43d4-8877-85f14218aee1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=691417885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.691417885
Directory	/workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.4119379017
Short name	T780
Test name
Test status
Simulation time	7464807664 ps
CPU time	1691.14 seconds
Started	Jun 09 03:13:24 PM PDT 24
Finished	Jun 09 03:41:36 PM PDT 24
Peak memory	606764 kb
Host	smart-bc50efcf-cc0b-4004-b348-69b304e87235
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119379017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.4119379017
Directory	/workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1519038462
Short name	T302
Test name
Test status
Simulation time	7913553130 ps
CPU time	1320.52 seconds
Started	Jun 09 03:12:49 PM PDT 24
Finished	Jun 09 03:34:50 PM PDT 24
Peak memory	606772 kb
Host	smart-d9aaec55-10f1-47cc-bfa5-808cf9522b16
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1519038462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.1519038462
Directory	/workspace/0.chip_sw_alert_handler_ping_ok/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.893719887
Short name	T797
Test name
Test status
Simulation time	4934349330 ps
CPU time	452.74 seconds
Started	Jun 09 03:12:33 PM PDT 24
Finished	Jun 09 03:20:06 PM PDT 24
Peak memory	607872 kb
Host	smart-fb776640-3e7e-4e8b-bc8b-b2000c1470f9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=893719887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.893719887
Directory	/workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.454126651
Short name	T567
Test name
Test status
Simulation time	254190688800 ps
CPU time	13298.5 seconds
Started	Jun 09 03:12:35 PM PDT 24
Finished	Jun 09 06:54:15 PM PDT 24
Peak memory	608236 kb
Host	smart-475500d0-e749-4e45-9fe3-e65de77eebb7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454126651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.454126651
Directory	/workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_test.3185470369
Short name	T80
Test name
Test status
Simulation time	3495291912 ps
CPU time	356.66 seconds
Started	Jun 09 03:12:09 PM PDT 24
Finished	Jun 09 03:18:06 PM PDT 24
Peak memory	606656 kb
Host	smart-fbf4be80-b57e-413c-9577-51bc24c13bdc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185470369 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.3185470369
Directory	/workspace/0.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_irq.2898546503
Short name	T673
Test name
Test status
Simulation time	4155022504 ps
CPU time	470.64 seconds
Started	Jun 09 03:13:04 PM PDT 24
Finished	Jun 09 03:20:56 PM PDT 24
Peak memory	606436 kb
Host	smart-6b173f16-8975-46b3-9cfc-d50300500a1d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898546503 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.2898546503
Directory	/workspace/0.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3427245282
Short name	T717
Test name
Test status
Simulation time	6529968624 ps
CPU time	467 seconds
Started	Jun 09 03:14:03 PM PDT 24
Finished	Jun 09 03:21:51 PM PDT 24
Peak memory	607232 kb
Host	smart-6b5f6726-ebac-42f3-af99-7316ce1958a6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3427245282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3427245282
Directory	/workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.882036527
Short name	T957
Test name
Test status
Simulation time	3114977096 ps
CPU time	323.54 seconds
Started	Jun 09 03:18:31 PM PDT 24
Finished	Jun 09 03:23:55 PM PDT 24
Peak memory	606396 kb
Host	smart-81c27053-6fc8-4952-bfa7-68f47a130125
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882036527 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_aon_timer_smoketest.882036527
Directory	/workspace/0.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2903584911
Short name	T583
Test name
Test status
Simulation time	7769103420 ps
CPU time	745.97 seconds
Started	Jun 09 03:12:09 PM PDT 24
Finished	Jun 09 03:24:35 PM PDT 24
Peak memory	608048 kb
Host	smart-4ca2c4e8-85f4-4099-889e-f5963302e1aa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2903584911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2903584911
Directory	/workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3028498586
Short name	T775
Test name
Test status
Simulation time	6266319752 ps
CPU time	754.74 seconds
Started	Jun 09 03:11:20 PM PDT 24
Finished	Jun 09 03:23:56 PM PDT 24
Peak memory	607372 kb
Host	smart-279ad7f6-ea00-473d-8cc2-698ce16e0d39
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3028498586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3028498586
Directory	/workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4018355121
Short name	T304
Test name
Test status
Simulation time	8660207407 ps
CPU time	829.48 seconds
Started	Jun 09 03:12:40 PM PDT 24
Finished	Jun 09 03:26:30 PM PDT 24
Peak memory	620828 kb
Host	smart-c7f37b8b-4e71-43f1-926e-7a0315114035
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=4018355121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.4018355121
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.707230724
Short name	T929
Test name
Test status
Simulation time	3830648920 ps
CPU time	543.34 seconds
Started	Jun 09 03:12:05 PM PDT 24
Finished	Jun 09 03:21:09 PM PDT 24
Peak memory	610272 kb
Host	smart-e0bb4f5f-05e2-47e9-affa-cdb7f836e9e0
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707230724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.707230724
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1315874408
Short name	T565
Test name
Test status
Simulation time	3797115800 ps
CPU time	660.34 seconds
Started	Jun 09 03:15:00 PM PDT 24
Finished	Jun 09 03:26:01 PM PDT 24
Peak memory	610260 kb
Host	smart-33938d89-141a-4899-bc92-9237295c9428
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315874408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1315874408
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2743587877
Short name	T656
Test name
Test status
Simulation time	3919511460 ps
CPU time	681.58 seconds
Started	Jun 09 03:20:48 PM PDT 24
Finished	Jun 09 03:32:10 PM PDT 24
Peak memory	610532 kb
Host	smart-984b1774-4e52-4be4-ba0e-02dbd98c8ee4
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743587877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2743587877
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3769508875
Short name	T675
Test name
Test status
Simulation time	4185091976 ps
CPU time	725.05 seconds
Started	Jun 09 03:13:36 PM PDT 24
Finished	Jun 09 03:25:41 PM PDT 24
Peak memory	610264 kb
Host	smart-9b8be7f2-06b2-4560-b5bf-f75c01f26eeb
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769508875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3769508875
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4184632085
Short name	T930
Test name
Test status
Simulation time	4924579936 ps
CPU time	658.57 seconds
Started	Jun 09 03:13:12 PM PDT 24
Finished	Jun 09 03:24:11 PM PDT 24
Peak memory	610284 kb
Host	smart-f6ed7dc2-414c-49c2-b265-88fcde1e5fe5
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184632085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.4184632085
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3592502820
Short name	T870
Test name
Test status
Simulation time	2930342567 ps
CPU time	134.22 seconds
Started	Jun 09 03:10:15 PM PDT 24
Finished	Jun 09 03:12:30 PM PDT 24
Peak memory	606332 kb
Host	smart-4c340107-1542-4110-bcd9-d1d4aa9c6830
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592502820 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.3592502820
Directory	/workspace/0.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3836179602
Short name	T293
Test name
Test status
Simulation time	3622852220 ps
CPU time	604.6 seconds
Started	Jun 09 03:14:25 PM PDT 24
Finished	Jun 09 03:24:31 PM PDT 24
Peak memory	606300 kb
Host	smart-79a7ae81-995b-4faa-a671-46a239fba3df
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836179602 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.3836179602
Directory	/workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3794601239
Short name	T788
Test name
Test status
Simulation time	2887114685 ps
CPU time	190.61 seconds
Started	Jun 09 03:14:36 PM PDT 24
Finished	Jun 09 03:17:47 PM PDT 24
Peak memory	606320 kb
Host	smart-34688865-d12c-46b2-bf3f-d859bd5c11b0
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794601239 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.3794601239
Directory	/workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.900882486
Short name	T980
Test name
Test status
Simulation time	5483876752 ps
CPU time	504.92 seconds
Started	Jun 09 03:20:50 PM PDT 24
Finished	Jun 09 03:29:15 PM PDT 24
Peak memory	606976 kb
Host	smart-9ed10424-6b3c-4002-9273-249f05d4acf0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900882486 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.900882486
Directory	/workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1388992254
Short name	T102
Test name
Test status
Simulation time	4369693496 ps
CPU time	567.29 seconds
Started	Jun 09 03:14:49 PM PDT 24
Finished	Jun 09 03:24:16 PM PDT 24
Peak memory	607000 kb
Host	smart-07864e63-c8f5-4ef8-8c41-70b03340e736
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388992254 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.1388992254
Directory	/workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.165551977
Short name	T831
Test name
Test status
Simulation time	4069868450 ps
CPU time	565.43 seconds
Started	Jun 09 03:15:07 PM PDT 24
Finished	Jun 09 03:24:33 PM PDT 24
Peak memory	606704 kb
Host	smart-3d122767-1760-4923-adc9-fab7b53e0658
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165551977 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.165551977
Directory	/workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3652247695
Short name	T647
Test name
Test status
Simulation time	5542398296 ps
CPU time	457.24 seconds
Started	Jun 09 03:13:04 PM PDT 24
Finished	Jun 09 03:20:42 PM PDT 24
Peak memory	607708 kb
Host	smart-979c8844-e756-4923-87af-e104d0fb58b7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652247695 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.3652247695
Directory	/workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3035114811
Short name	T553
Test name
Test status
Simulation time	8605101692 ps
CPU time	1000.87 seconds
Started	Jun 09 03:12:30 PM PDT 24
Finished	Jun 09 03:29:11 PM PDT 24
Peak memory	608404 kb
Host	smart-d748494a-e8a7-4014-b1a9-e03887771e16
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035114811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.3035114811
Directory	/workspace/0.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.895480765
Short name	T339
Test name
Test status
Simulation time	3861779136 ps
CPU time	569.3 seconds
Started	Jun 09 03:14:57 PM PDT 24
Finished	Jun 09 03:24:27 PM PDT 24
Peak memory	606384 kb
Host	smart-2b3d25eb-d9cb-46cf-9655-989fb7fa8f06
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895480765 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.895480765
Directory	/workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.38385689
Short name	T413
Test name
Test status
Simulation time	4679892608 ps
CPU time	564.73 seconds
Started	Jun 09 03:11:43 PM PDT 24
Finished	Jun 09 03:21:08 PM PDT 24
Peak memory	607392 kb
Host	smart-9ea761e9-9182-4dbb-8d49-563af0d5de72
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38385689 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.38385689
Directory	/workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4281941243
Short name	T963
Test name
Test status
Simulation time	2533255824 ps
CPU time	191.08 seconds
Started	Jun 09 03:16:00 PM PDT 24
Finished	Jun 09 03:19:11 PM PDT 24
Peak memory	606996 kb
Host	smart-688b0a73-0c80-4730-884b-3a0a7e0c88c6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281941243 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.4281941243
Directory	/workspace/0.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1623105451
Short name	T886
Test name
Test status
Simulation time	26331728312 ps
CPU time	5773.62 seconds
Started	Jun 09 03:13:45 PM PDT 24
Finished	Jun 09 04:49:59 PM PDT 24
Peak memory	607156 kb
Host	smart-d4f65381-b3f7-47d7-8067-2db203846074
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623105451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.1623105451
Directory	/workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3484737219
Short name	T713
Test name
Test status
Simulation time	3854388540 ps
CPU time	546.46 seconds
Started	Jun 09 03:13:13 PM PDT 24
Finished	Jun 09 03:22:20 PM PDT 24
Peak memory	606968 kb
Host	smart-00c5e1a1-126f-44b1-89b9-0af8e08687d9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34847 37219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.3484737219
Directory	/workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_kat_test.2653690937
Short name	T548
Test name
Test status
Simulation time	2474449064 ps
CPU time	227.13 seconds
Started	Jun 09 03:10:55 PM PDT 24
Finished	Jun 09 03:14:42 PM PDT 24
Peak memory	606740 kb
Host	smart-4f751936-7323-4982-be43-0b7056ab7174
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653690937 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.2653690937
Directory	/workspace/0.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2179470457
Short name	T110
Test name
Test status
Simulation time	5857728865 ps
CPU time	707.19 seconds
Started	Jun 09 03:12:52 PM PDT 24
Finished	Jun 09 03:24:39 PM PDT 24
Peak memory	609092 kb
Host	smart-283a32de-ba9f-4253-9e03-8e2cf49e20de
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179470457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.2179470457
Directory	/workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_smoketest.358653968
Short name	T880
Test name
Test status
Simulation time	2709167720 ps
CPU time	246.59 seconds
Started	Jun 09 03:16:19 PM PDT 24
Finished	Jun 09 03:20:26 PM PDT 24
Peak memory	606368 kb
Host	smart-2605c0de-84f9-40e8-9328-10c1c3993a22
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358653968 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_csrng_smoketest.358653968
Directory	/workspace/0.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2637876083
Short name	T681
Test name
Test status
Simulation time	5574211292 ps
CPU time	735.59 seconds
Started	Jun 09 03:13:42 PM PDT 24
Finished	Jun 09 03:25:59 PM PDT 24
Peak memory	608204 kb
Host	smart-9d5e1657-2816-4d68-ac34-9f29df7c6987
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2637876083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.2637876083
Directory	/workspace/0.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_auto_mode.3411877059
Short name	T853
Test name
Test status
Simulation time	6910692884 ps
CPU time	1966.77 seconds
Started	Jun 09 03:12:34 PM PDT 24
Finished	Jun 09 03:45:21 PM PDT 24
Peak memory	607208 kb
Host	smart-312f13af-514e-4a73-92ae-03ab5bd1ee5b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411877059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.3411877059
Directory	/workspace/0.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2280713668
Short name	T423
Test name
Test status
Simulation time	7058840055 ps
CPU time	1118.74 seconds
Started	Jun 09 03:14:59 PM PDT 24
Finished	Jun 09 03:33:38 PM PDT 24
Peak memory	608672 kb
Host	smart-7b644b1a-135d-4aa6-88a2-2b67e8fb251d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280713668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2280713668
Directory	/workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_kat.2619020099
Short name	T738
Test name
Test status
Simulation time	3541876432 ps
CPU time	678.31 seconds
Started	Jun 09 03:14:13 PM PDT 24
Finished	Jun 09 03:25:33 PM PDT 24
Peak memory	613160 kb
Host	smart-5157bec2-34d0-4bdc-a8fa-d67af6c74fbd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619020099 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2619020099
Directory	/workspace/0.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_sw_mode.1500518589
Short name	T789
Test name
Test status
Simulation time	7610975456 ps
CPU time	2132.25 seconds
Started	Jun 09 03:13:03 PM PDT 24
Finished	Jun 09 03:48:36 PM PDT 24
Peak memory	607692 kb
Host	smart-971105c5-753c-47b6-94f7-3698f10c9430
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500518589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.1500518589
Directory	/workspace/0.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3221444636
Short name	T920
Test name
Test status
Simulation time	3520012936 ps
CPU time	295.27 seconds
Started	Jun 09 03:13:16 PM PDT 24
Finished	Jun 09 03:18:12 PM PDT 24
Peak memory	606536 kb
Host	smart-dd1dd0e7-d98f-4f4b-9fe6-025a00cd0c7f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32 21444636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.3221444636
Directory	/workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2664024552
Short name	T354
Test name
Test status
Simulation time	7266443544 ps
CPU time	1668.14 seconds
Started	Jun 09 03:14:41 PM PDT 24
Finished	Jun 09 03:42:30 PM PDT 24
Peak memory	607016 kb
Host	smart-26849bb2-521c-48fc-b83a-5a82257bf6c9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2664024552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2664024552
Directory	/workspace/0.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4037449388
Short name	T555
Test name
Test status
Simulation time	3641837648 ps
CPU time	281.1 seconds
Started	Jun 09 03:14:31 PM PDT 24
Finished	Jun 09 03:19:13 PM PDT 24
Peak memory	606588 kb
Host	smart-25e67074-36ea-4d16-ba66-0a9587e998f8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037449388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.4037449388
Directory	/workspace/0.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.117880057
Short name	T598
Test name
Test status
Simulation time	3678252020 ps
CPU time	426.86 seconds
Started	Jun 09 03:18:42 PM PDT 24
Finished	Jun 09 03:25:49 PM PDT 24
Peak memory	606028 kb
Host	smart-8548916c-6b93-47b5-b22c-ba3cea85fac9
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=117880057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.117880057
Directory	/workspace/0.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_example_concurrency.1323536789
Short name	T866
Test name
Test status
Simulation time	3427760170 ps
CPU time	331.03 seconds
Started	Jun 09 03:13:19 PM PDT 24
Finished	Jun 09 03:18:51 PM PDT 24
Peak memory	606368 kb
Host	smart-9b123e64-f46f-4739-b22c-5863284ae339
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323536789 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.1323536789
Directory	/workspace/0.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_example_flash.443287996
Short name	T772
Test name
Test status
Simulation time	3545095730 ps
CPU time	294.79 seconds
Started	Jun 09 03:13:01 PM PDT 24
Finished	Jun 09 03:17:57 PM PDT 24
Peak memory	607000 kb
Host	smart-19608e77-4942-4ef8-8543-e1cff6884a2a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443287996 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.443287996
Directory	/workspace/0.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/0.chip_sw_example_manufacturer.2356920729
Short name	T406
Test name
Test status
Simulation time	2514177512 ps
CPU time	232.87 seconds
Started	Jun 09 03:11:11 PM PDT 24
Finished	Jun 09 03:15:04 PM PDT 24
Peak memory	607192 kb
Host	smart-af526eb6-ef35-40f9-bf6f-8e7a5e8bbd48
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356920729 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2356920729
Directory	/workspace/0.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/0.chip_sw_example_rom.857262796
Short name	T676
Test name
Test status
Simulation time	2653720896 ps
CPU time	127.09 seconds
Started	Jun 09 03:11:16 PM PDT 24
Finished	Jun 09 03:13:23 PM PDT 24
Peak memory	606028 kb
Host	smart-d9e3024d-9822-429a-bbc4-d5e6e5fe67d0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857262796 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_example_rom.857262796
Directory	/workspace/0.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3232384187
Short name	T888
Test name
Test status
Simulation time	58443351288 ps
CPU time	10395.7 seconds
Started	Jun 09 03:11:10 PM PDT 24
Finished	Jun 09 06:04:27 PM PDT 24
Peak memory	623108 kb
Host	smart-cb7a45d5-fd7d-4f4a-8649-7618ec746021
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3232384187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.3232384187
Directory	/workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1212801289
Short name	T685
Test name
Test status
Simulation time	4532076576 ps
CPU time	546.94 seconds
Started	Jun 09 03:12:23 PM PDT 24
Finished	Jun 09 03:21:31 PM PDT 24
Peak memory	608540 kb
Host	smart-4c8d86d2-86e8-41cf-83ca-599c783b34e3
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1212801289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1212801289
Directory	/workspace/0.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2173486183
Short name	T539
Test name
Test status
Simulation time	6036407600 ps
CPU time	1258.01 seconds
Started	Jun 09 03:13:22 PM PDT 24
Finished	Jun 09 03:34:21 PM PDT 24
Peak memory	606748 kb
Host	smart-0dcefc6f-55c4-4344-869f-d334ac208252
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173486183 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.2173486183
Directory	/workspace/0.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3377515989
Short name	T733
Test name
Test status
Simulation time	6086990989 ps
CPU time	1210.78 seconds
Started	Jun 09 03:12:21 PM PDT 24
Finished	Jun 09 03:32:32 PM PDT 24
Peak memory	606820 kb
Host	smart-c0222de1-93b2-4a6b-987e-0e450919ec55
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377515989 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.3377515989
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3639947163
Short name	T851
Test name
Test status
Simulation time	6810876420 ps
CPU time	1080.38 seconds
Started	Jun 09 03:14:08 PM PDT 24
Finished	Jun 09 03:32:09 PM PDT 24
Peak memory	606680 kb
Host	smart-c7ef0d83-aac1-450f-8870-236c06be7f84
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639947163 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3639947163
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2870070253
Short name	T945
Test name
Test status
Simulation time	5705062040 ps
CPU time	953.97 seconds
Started	Jun 09 03:11:43 PM PDT 24
Finished	Jun 09 03:27:37 PM PDT 24
Peak memory	607468 kb
Host	smart-e80b2d6e-7c6c-4cf8-b498-a040ff801b0d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870070253 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.2870070253
Directory	/workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2967537737
Short name	T273
Test name
Test status
Simulation time	3488250614 ps
CPU time	291.63 seconds
Started	Jun 09 03:13:44 PM PDT 24
Finished	Jun 09 03:18:36 PM PDT 24
Peak memory	607092 kb
Host	smart-2e2cf9e6-31b1-4676-869a-f8da1f2657f9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967537737 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.2967537737
Directory	/workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.959226421
Short name	T530
Test name
Test status
Simulation time	5983371910 ps
CPU time	1200.32 seconds
Started	Jun 09 03:15:46 PM PDT 24
Finished	Jun 09 03:35:47 PM PDT 24
Peak memory	607396 kb
Host	smart-cc0c607b-4ae8-40cd-a7ac-288b5d7ff45b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959226421 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.959226421
Directory	/workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3843599513
Short name	T362
Test name
Test status
Simulation time	3420249700 ps
CPU time	565.76 seconds
Started	Jun 09 03:16:50 PM PDT 24
Finished	Jun 09 03:26:17 PM PDT 24
Peak memory	606712 kb
Host	smart-7858f631-415d-43a3-82cd-32fda5effac1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843599513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.3843599513
Directory	/workspace/0.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1689254091
Short name	T360
Test name
Test status
Simulation time	3708108420 ps
CPU time	789.54 seconds
Started	Jun 09 03:13:54 PM PDT 24
Finished	Jun 09 03:27:03 PM PDT 24
Peak memory	606276 kb
Host	smart-72eb5655-7371-4da9-8691-79379e4cc48d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1689254091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.1689254091
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2095802569
Short name	T820
Test name
Test status
Simulation time	5503648355 ps
CPU time	703.95 seconds
Started	Jun 09 03:13:43 PM PDT 24
Finished	Jun 09 03:25:27 PM PDT 24
Peak memory	607004 kb
Host	smart-f9816f6e-2f73-4cbc-9b20-46705e265cdc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2095802569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2095802569
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2264724231
Short name	T805
Test name
Test status
Simulation time	2964453244 ps
CPU time	327.63 seconds
Started	Jun 09 03:14:05 PM PDT 24
Finished	Jun 09 03:19:33 PM PDT 24
Peak memory	606304 kb
Host	smart-b6280902-eee0-410a-8db2-5ccfc2df2b96
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264724 231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.2264724231
Directory	/workspace/0.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_init.465493512
Short name	T237
Test name
Test status
Simulation time	17231944111 ps
CPU time	1816.95 seconds
Started	Jun 09 03:12:39 PM PDT 24
Finished	Jun 09 03:42:57 PM PDT 24
Peak memory	611656 kb
Host	smart-12135cd6-ccd4-4495-97ad-52783b97a579
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465493512 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.465493512
Directory	/workspace/0.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3176314128
Short name	T235
Test name
Test status
Simulation time	25984765362 ps
CPU time	2240.6 seconds
Started	Jun 09 03:15:26 PM PDT 24
Finished	Jun 09 03:52:47 PM PDT 24
Peak memory	610024 kb
Host	smart-caeb2850-fef4-4e8d-bd67-9e2125cc5c74
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3176314128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.3176314128
Directory	/workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.88118217
Short name	T416
Test name
Test status
Simulation time	2303578942 ps
CPU time	234.24 seconds
Started	Jun 09 03:17:03 PM PDT 24
Finished	Jun 09 03:20:57 PM PDT 24
Peak memory	606880 kb
Host	smart-3bef104d-08dd-410b-bdfb-a6f583321e02
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=88118217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.88118217
Directory	/workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_gpio_smoketest.4201250872
Short name	T916
Test name
Test status
Simulation time	2925331731 ps
CPU time	245.68 seconds
Started	Jun 09 03:17:27 PM PDT 24
Finished	Jun 09 03:21:33 PM PDT 24
Peak memory	606708 kb
Host	smart-5b8e7f1f-08e1-4020-b905-fec544eb2655
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201250872 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.4201250872
Directory	/workspace/0.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc.2342499721
Short name	T671
Test name
Test status
Simulation time	2552143996 ps
CPU time	250.3 seconds
Started	Jun 09 03:14:04 PM PDT 24
Finished	Jun 09 03:18:14 PM PDT 24
Peak memory	606488 kb
Host	smart-84adbc51-554d-4ef4-b835-f7386ee378a6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342499721 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.2342499721
Directory	/workspace/0.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3804439755
Short name	T993
Test name
Test status
Simulation time	3128801079 ps
CPU time	264.68 seconds
Started	Jun 09 03:12:12 PM PDT 24
Finished	Jun 09 03:16:37 PM PDT 24
Peak memory	606420 kb
Host	smart-b7d71ba3-e262-4080-ba8e-fe6fc185fc5d
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804439755 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3804439755
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2307255133
Short name	T368
Test name
Test status
Simulation time	2699294749 ps
CPU time	239.2 seconds
Started	Jun 09 03:13:53 PM PDT 24
Finished	Jun 09 03:17:53 PM PDT 24
Peak memory	606172 kb
Host	smart-f1f540b0-93f7-4536-b957-aae2c4282366
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307255133 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.2307255133
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_multistream.1612182044
Short name	T879
Test name
Test status
Simulation time	7064657904 ps
CPU time	1753.27 seconds
Started	Jun 09 03:12:41 PM PDT 24
Finished	Jun 09 03:41:55 PM PDT 24
Peak memory	606572 kb
Host	smart-7e434b58-e134-49ed-90ce-e57c633cadc9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612182044 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.1612182044
Directory	/workspace/0.chip_sw_hmac_multistream/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_oneshot.3769816239
Short name	T863
Test name
Test status
Simulation time	3499528500 ps
CPU time	399.13 seconds
Started	Jun 09 03:12:32 PM PDT 24
Finished	Jun 09 03:19:11 PM PDT 24
Peak memory	606512 kb
Host	smart-b609a0b1-1d69-4bf8-bcf8-0cf9285fa473
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769816239 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.3769816239
Directory	/workspace/0.chip_sw_hmac_oneshot/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_smoketest.3927440342
Short name	T917
Test name
Test status
Simulation time	2729472328 ps
CPU time	228.67 seconds
Started	Jun 09 03:17:17 PM PDT 24
Finished	Jun 09 03:21:06 PM PDT 24
Peak memory	606292 kb
Host	smart-7e36b2c0-2aef-423b-9a38-f651f171eb7c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927440342 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.3927440342
Directory	/workspace/0.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.4031720725
Short name	T207
Test name
Test status
Simulation time	4777738446 ps
CPU time	643.46 seconds
Started	Jun 09 03:13:56 PM PDT 24
Finished	Jun 09 03:24:40 PM PDT 24
Peak memory	607184 kb
Host	smart-7eae21b9-500f-4177-ab47-b629477d41f3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031720725 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.4031720725
Directory	/workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3547506076
Short name	T209
Test name
Test status
Simulation time	5032333886 ps
CPU time	757.77 seconds
Started	Jun 09 03:12:06 PM PDT 24
Finished	Jun 09 03:24:44 PM PDT 24
Peak memory	607796 kb
Host	smart-686a9f13-72ae-456f-a061-dd2a2305ca7d
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547506076 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.3547506076
Directory	/workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.1757506065
Short name	T320
Test name
Test status
Simulation time	64427111773 ps
CPU time	11544.8 seconds
Started	Jun 09 03:11:08 PM PDT 24
Finished	Jun 09 06:23:35 PM PDT 24
Peak memory	623944 kb
Host	smart-57006639-023a-443c-930f-bfdb0f9f4886
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1757506065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.1757506065
Directory	/workspace/0.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2475396929
Short name	T764
Test name
Test status
Simulation time	9892258264 ps
CPU time	1985.07 seconds
Started	Jun 09 03:13:26 PM PDT 24
Finished	Jun 09 03:46:32 PM PDT 24
Peak memory	614348 kb
Host	smart-47fa059f-71fb-4ab8-898e-ab2d88359265
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2475396929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.2475396929
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2875720440
Short name	T984
Test name
Test status
Simulation time	7834212367 ps
CPU time	1176.63 seconds
Started	Jun 09 03:13:32 PM PDT 24
Finished	Jun 09 03:33:09 PM PDT 24
Peak memory	614288 kb
Host	smart-2076f0bc-c114-4424-8033-2dc972c939f4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2875720440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2875720440
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2506867980
Short name	T811
Test name
Test status
Simulation time	6916224866 ps
CPU time	1257.57 seconds
Started	Jun 09 03:11:01 PM PDT 24
Finished	Jun 09 03:31:59 PM PDT 24
Peak memory	615544 kb
Host	smart-e3f430a2-5a6b-41a6-ad90-225cf3dad50e
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2506867980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.2506867980
Directory	/workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.4013236686
Short name	T271
Test name
Test status
Simulation time	12981388476 ps
CPU time	2625.92 seconds
Started	Jun 09 03:12:19 PM PDT 24
Finished	Jun 09 03:56:06 PM PDT 24
Peak memory	608740 kb
Host	smart-3ce28028-c07c-4a8f-8d6c-6b2cfa457af3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401323 6686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.4013236686
Directory	/workspace/0.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1462847884
Short name	T407
Test name
Test status
Simulation time	6956075992 ps
CPU time	1497.77 seconds
Started	Jun 09 03:16:52 PM PDT 24
Finished	Jun 09 03:41:51 PM PDT 24
Peak memory	607868 kb
Host	smart-c0be608d-a20d-4ca2-b7f7-2a1ac1eb0213
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14628 47884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.1462847884
Directory	/workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_entropy.3450178886
Short name	T537
Test name
Test status
Simulation time	2927865550 ps
CPU time	258.35 seconds
Started	Jun 09 03:17:23 PM PDT 24
Finished	Jun 09 03:21:42 PM PDT 24
Peak memory	606320 kb
Host	smart-bd39aa9c-ab4e-4fe6-a4ed-0ed95735d22d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450178886 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.3450178886
Directory	/workspace/0.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_idle.2677041645
Short name	T782
Test name
Test status
Simulation time	3031797536 ps
CPU time	227.56 seconds
Started	Jun 09 03:11:36 PM PDT 24
Finished	Jun 09 03:15:24 PM PDT 24
Peak memory	606364 kb
Host	smart-1b4fff3f-77e5-4a4e-9958-e30349022135
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677041645 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2677041645
Directory	/workspace/0.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2135131414
Short name	T139
Test name
Test status
Simulation time	2819681048 ps
CPU time	267.35 seconds
Started	Jun 09 03:16:36 PM PDT 24
Finished	Jun 09 03:21:04 PM PDT 24
Peak memory	607300 kb
Host	smart-cebe1462-6e36-4d78-aabe-138985af7187
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135131414 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.2135131414
Directory	/workspace/0.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2866331182
Short name	T292
Test name
Test status
Simulation time	2343899936 ps
CPU time	329.77 seconds
Started	Jun 09 03:16:29 PM PDT 24
Finished	Jun 09 03:22:00 PM PDT 24
Peak memory	607000 kb
Host	smart-048c1b41-36ff-4d83-8c80-1d1d7fde8f93
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866331182 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.2866331182
Directory	/workspace/0.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3989363969
Short name	T763
Test name
Test status
Simulation time	3776314063 ps
CPU time	280.53 seconds
Started	Jun 09 03:11:45 PM PDT 24
Finished	Jun 09 03:16:26 PM PDT 24
Peak memory	607112 kb
Host	smart-4d2a2c39-e326-4a88-8db3-7657dbec0e0c
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989363969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.3989363969
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2383028409
Short name	T935
Test name
Test status
Simulation time	3504434221 ps
CPU time	315.08 seconds
Started	Jun 09 03:13:06 PM PDT 24
Finished	Jun 09 03:18:21 PM PDT 24
Peak memory	606492 kb
Host	smart-9c90d844-35d7-47db-a9a3-db4d522c9091
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23830284 09 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2383028409
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_smoketest.2427152054
Short name	T632
Test name
Test status
Simulation time	3125319416 ps
CPU time	303.89 seconds
Started	Jun 09 03:16:59 PM PDT 24
Finished	Jun 09 03:22:03 PM PDT 24
Peak memory	606368 kb
Host	smart-60dc16f3-6e5e-4212-861e-73722f16b976
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427152054 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.2427152054
Directory	/workspace/0.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.554163527
Short name	T532
Test name
Test status
Simulation time	3118193252 ps
CPU time	394.26 seconds
Started	Jun 09 03:12:08 PM PDT 24
Finished	Jun 09 03:18:43 PM PDT 24
Peak memory	607012 kb
Host	smart-ecfa1405-a823-407b-9a29-9def0ccb6ca0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554163527 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.554163527
Directory	/workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.633452194
Short name	T924
Test name
Test status
Simulation time	2754949400 ps
CPU time	135.08 seconds
Started	Jun 09 03:13:56 PM PDT 24
Finished	Jun 09 03:16:11 PM PDT 24
Peak memory	616112 kb
Host	smart-7c56d6c5-fcdf-44f6-802d-b91fd5691480
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633452194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.633452194
Directory	/workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1210016135
Short name	T193
Test name
Test status
Simulation time	4030233341 ps
CPU time	343.19 seconds
Started	Jun 09 03:11:44 PM PDT 24
Finished	Jun 09 03:17:28 PM PDT 24
Peak memory	617900 kb
Host	smart-3f2b3c88-63c4-4b89-b2d1-f986f2d5b170
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210016135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1210016135
Directory	/workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2290102397
Short name	T958
Test name
Test status
Simulation time	3923689283 ps
CPU time	185.4 seconds
Started	Jun 09 03:12:38 PM PDT 24
Finished	Jun 09 03:15:45 PM PDT 24
Peak memory	617404 kb
Host	smart-4f50f12e-3baa-4e5d-b6a7-e04e7f706198
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290102397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.2290102397
Directory	/workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1294409570
Short name	T910
Test name
Test status
Simulation time	5860164719 ps
CPU time	627.29 seconds
Started	Jun 09 03:13:22 PM PDT 24
Finished	Jun 09 03:23:50 PM PDT 24
Peak memory	618996 kb
Host	smart-94776b7d-0eea-47d6-86a4-73d8b8f8f56b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294409570 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.1294409570
Directory	/workspace/0.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.36837439
Short name	T876
Test name
Test status
Simulation time	2315360737 ps
CPU time	90.22 seconds
Started	Jun 09 03:20:52 PM PDT 24
Finished	Jun 09 03:22:22 PM PDT 24
Peak memory	614684 kb
Host	smart-cb7772c1-70b5-45f5-9002-ef7ba046e620
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36837439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.36837439
Directory	/workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1249574493
Short name	T938
Test name
Test status
Simulation time	47985604100 ps
CPU time	5595.69 seconds
Started	Jun 09 03:15:08 PM PDT 24
Finished	Jun 09 04:48:26 PM PDT 24
Peak memory	614812 kb
Host	smart-410a3b68-2858-45d6-bd01-4fc0988a5e9d
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249574493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.1249574493
Directory	/workspace/0.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2633596683
Short name	T570
Test name
Test status
Simulation time	11786450225 ps
CPU time	1101.57 seconds
Started	Jun 09 03:12:13 PM PDT 24
Finished	Jun 09 03:30:35 PM PDT 24
Peak memory	614592 kb
Host	smart-4e5205a8-6fcf-4c18-aec6-efbf84c5f7bc
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633596683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.2633596683
Directory	/workspace/0.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1399435383
Short name	T595
Test name
Test status
Simulation time	32182444496 ps
CPU time	2277.52 seconds
Started	Jun 09 03:13:22 PM PDT 24
Finished	Jun 09 03:51:20 PM PDT 24
Peak memory	618088 kb
Host	smart-8f40b11e-7f6a-4364-b78f-109e5d940d55
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1399435383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.1399435383
Directory	/workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1465198058
Short name	T607
Test name
Test status
Simulation time	18474221080 ps
CPU time	4261.02 seconds
Started	Jun 09 03:12:20 PM PDT 24
Finished	Jun 09 04:23:22 PM PDT 24
Peak memory	607876 kb
Host	smart-46f5cc12-765f-48e6-9fa1-0823bb6ac1ea
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1465198058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1465198058
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2847295737
Short name	T835
Test name
Test status
Simulation time	24173539965 ps
CPU time	4498.56 seconds
Started	Jun 09 03:14:42 PM PDT 24
Finished	Jun 09 04:29:42 PM PDT 24
Peak memory	607572 kb
Host	smart-a296bba6-87c8-4b73-997b-42dffaf2c3b2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847295737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2847295737
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_randomness.146109848
Short name	T792
Test name
Test status
Simulation time	6170534040 ps
CPU time	883.67 seconds
Started	Jun 09 03:13:47 PM PDT 24
Finished	Jun 09 03:28:31 PM PDT 24
Peak memory	607144 kb
Host	smart-f1086a2b-c4d5-407f-a25f-e922bffee1c4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=146109848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.146109848
Directory	/workspace/0.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_smoketest.2557288809
Short name	T575
Test name
Test status
Simulation time	9220085160 ps
CPU time	2450.96 seconds
Started	Jun 09 03:18:48 PM PDT 24
Finished	Jun 09 03:59:40 PM PDT 24
Peak memory	606896 kb
Host	smart-ac096dbf-3d0c-45cb-b404-b843e15dd3dd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557288809 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.2557288809
Directory	/workspace/0.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1165026457
Short name	T533
Test name
Test status
Simulation time	26444295378 ps
CPU time	6217.8 seconds
Started	Jun 09 03:12:29 PM PDT 24
Finished	Jun 09 04:56:08 PM PDT 24
Peak memory	608020 kb
Host	smart-331ece50-c7b4-4e4c-806d-d9aea0065f71
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116502 6457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.1165026457
Directory	/workspace/0.chip_sw_otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.798788951
Short name	T585
Test name
Test status
Simulation time	2497828192 ps
CPU time	257.79 seconds
Started	Jun 09 03:12:24 PM PDT 24
Finished	Jun 09 03:16:42 PM PDT 24
Peak memory	607088 kb
Host	smart-80cdd311-d58f-4e7e-ae73-eb303660c0d3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798788951 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.798788951
Directory	/workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1614668980
Short name	T766
Test name
Test status
Simulation time	7174171192 ps
CPU time	1162.98 seconds
Started	Jun 09 03:12:15 PM PDT 24
Finished	Jun 09 03:31:38 PM PDT 24
Peak memory	608128 kb
Host	smart-32976845-5d2b-4cc4-8060-d8b534b85558
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1614668980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1614668980
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3915758704
Short name	T18
Test name
Test status
Simulation time	8827128116 ps
CPU time	1397.04 seconds
Started	Jun 09 03:18:28 PM PDT 24
Finished	Jun 09 03:41:45 PM PDT 24
Peak memory	608128 kb
Host	smart-ec6a14a6-e59c-4ea3-8e9b-63e095dda153
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3915758704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.3915758704
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3368779992
Short name	T812
Test name
Test status
Simulation time	8527626372 ps
CPU time	1590.16 seconds
Started	Jun 09 03:19:10 PM PDT 24
Finished	Jun 09 03:45:41 PM PDT 24
Peak memory	607816 kb
Host	smart-97e0759b-31d9-4197-9bd4-928378b6dee0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3368779992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3368779992
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.821609127
Short name	T577
Test name
Test status
Simulation time	4738925540 ps
CPU time	542.87 seconds
Started	Jun 09 03:17:28 PM PDT 24
Finished	Jun 09 03:26:31 PM PDT 24
Peak memory	606684 kb
Host	smart-e5b9c3b0-aa43-4faf-b0c8-01b7df050f69
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=821609127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.821609127
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2075603070
Short name	T400
Test name
Test status
Simulation time	3074708392 ps
CPU time	290.78 seconds
Started	Jun 09 03:17:15 PM PDT 24
Finished	Jun 09 03:22:06 PM PDT 24
Peak memory	607004 kb
Host	smart-a677a755-3cd8-477e-b3a7-041ad0244cee
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075603070 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.2075603070
Directory	/workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pattgen_ios.3714962927
Short name	T341
Test name
Test status
Simulation time	3724982320 ps
CPU time	256.93 seconds
Started	Jun 09 03:11:01 PM PDT 24
Finished	Jun 09 03:15:19 PM PDT 24
Peak memory	606580 kb
Host	smart-e043f40e-edca-4815-b276-8b20d85fa911
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714962927 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3714962927
Directory	/workspace/0.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/0.chip_sw_power_sleep_load.2336826606
Short name	T331
Test name
Test status
Simulation time	10168363258 ps
CPU time	795.85 seconds
Started	Jun 09 03:13:59 PM PDT 24
Finished	Jun 09 03:27:15 PM PDT 24
Peak memory	607156 kb
Host	smart-af784372-1269-42b5-8e1e-a6b348a178fc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336826606 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2336826606
Directory	/workspace/0.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4130773309
Short name	T756
Test name
Test status
Simulation time	22843130646 ps
CPU time	3280.98 seconds
Started	Jun 09 03:11:52 PM PDT 24
Finished	Jun 09 04:06:34 PM PDT 24
Peak memory	608312 kb
Host	smart-08f14b7c-727d-4bcc-81d0-8a8db5a7798c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413 0773309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.4130773309
Directory	/workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3344698729
Short name	T334
Test name
Test status
Simulation time	16118882434 ps
CPU time	1620.43 seconds
Started	Jun 09 03:14:59 PM PDT 24
Finished	Jun 09 03:42:00 PM PDT 24
Peak memory	608996 kb
Host	smart-b4cad570-2e61-4ee8-8794-74865fe49dcf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3344698729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3344698729
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4137783041
Short name	T890
Test name
Test status
Simulation time	8969730820 ps
CPU time	583.4 seconds
Started	Jun 09 03:11:37 PM PDT 24
Finished	Jun 09 03:21:21 PM PDT 24
Peak memory	608076 kb
Host	smart-4c18e3cb-0df7-48d6-ad32-56d436d0116e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137783041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.4137783041
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.4033566477
Short name	T771
Test name
Test status
Simulation time	4168604891 ps
CPU time	422.49 seconds
Started	Jun 09 03:13:33 PM PDT 24
Finished	Jun 09 03:20:36 PM PDT 24
Peak memory	613720 kb
Host	smart-ca5a87ef-53e3-42f9-ad0e-437ee1832d74
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4033566477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.4033566477
Directory	/workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3579101008
Short name	T693
Test name
Test status
Simulation time	14246840691 ps
CPU time	1327.27 seconds
Started	Jun 09 03:11:40 PM PDT 24
Finished	Jun 09 03:33:47 PM PDT 24
Peak memory	608980 kb
Host	smart-38b20f30-02ec-4065-84a3-ee1b12961160
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579101008 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3579101008
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2826356631
Short name	T142
Test name
Test status
Simulation time	7572429578 ps
CPU time	520.11 seconds
Started	Jun 09 03:12:04 PM PDT 24
Finished	Jun 09 03:20:44 PM PDT 24
Peak memory	608096 kb
Host	smart-ee88f533-8fb6-4a00-9d36-9699ea354057
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826356631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2826356631
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.957818337
Short name	T731
Test name
Test status
Simulation time	6154492236 ps
CPU time	596.87 seconds
Started	Jun 09 03:13:34 PM PDT 24
Finished	Jun 09 03:23:31 PM PDT 24
Peak memory	607320 kb
Host	smart-317545ea-b134-45c8-9ffd-f5f195507f8f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957818337 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.957818337
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.113565063
Short name	T628
Test name
Test status
Simulation time	27352059525 ps
CPU time	2400.39 seconds
Started	Jun 09 03:12:16 PM PDT 24
Finished	Jun 09 03:52:17 PM PDT 24
Peak memory	608992 kb
Host	smart-9db7ecbd-5e51-4a50-83d0-67d50c9c5a57
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=113565063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.113565063
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2353297332
Short name	T559
Test name
Test status
Simulation time	34366125125 ps
CPU time	3150.66 seconds
Started	Jun 09 03:14:41 PM PDT 24
Finished	Jun 09 04:07:13 PM PDT 24
Peak memory	610048 kb
Host	smart-34ceee21-99a3-43bb-a05b-1e61da8dc48b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353297332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2353297332
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.436897904
Short name	T359
Test name
Test status
Simulation time	3098117950 ps
CPU time	296.37 seconds
Started	Jun 09 03:11:48 PM PDT 24
Finished	Jun 09 03:16:45 PM PDT 24
Peak memory	607112 kb
Host	smart-8af42454-2c37-48bd-a3ac-0a40d3680b01
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436897904 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.436897904
Directory	/workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2531756609
Short name	T779
Test name
Test status
Simulation time	4999957100 ps
CPU time	512.16 seconds
Started	Jun 09 03:12:07 PM PDT 24
Finished	Jun 09 03:20:40 PM PDT 24
Peak memory	614020 kb
Host	smart-b0e54cd3-84e6-44b0-a6b9-63c038bceb2e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2531756609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.2531756609
Directory	/workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1258592848
Short name	T715
Test name
Test status
Simulation time	5933553870 ps
CPU time	455.58 seconds
Started	Jun 09 03:12:45 PM PDT 24
Finished	Jun 09 03:20:21 PM PDT 24
Peak memory	608620 kb
Host	smart-e9b31e77-91c5-47a6-9318-486f901b5a0d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1258592848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1258592848
Directory	/workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3718153228
Short name	T803
Test name
Test status
Simulation time	5603221618 ps
CPU time	388.09 seconds
Started	Jun 09 03:17:24 PM PDT 24
Finished	Jun 09 03:23:53 PM PDT 24
Peak memory	607976 kb
Host	smart-eb9ebe25-02f6-4450-9268-8eac7bba170c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718153228 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3718153228
Directory	/workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2532578947
Short name	T260
Test name
Test status
Simulation time	5699624576 ps
CPU time	792.79 seconds
Started	Jun 09 03:14:21 PM PDT 24
Finished	Jun 09 03:27:35 PM PDT 24
Peak memory	607164 kb
Host	smart-f958efd5-0a66-463f-a6ab-4bd7a6d0c4bb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532578947 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2532578947
Directory	/workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3778171504
Short name	T937
Test name
Test status
Simulation time	4954634632 ps
CPU time	399.05 seconds
Started	Jun 09 03:13:12 PM PDT 24
Finished	Jun 09 03:19:51 PM PDT 24
Peak memory	606976 kb
Host	smart-44c4e081-b33c-47c0-95e7-dae2538698a8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778171504 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3778171504
Directory	/workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.256395234
Short name	T825
Test name
Test status
Simulation time	6395675520 ps
CPU time	291.19 seconds
Started	Jun 09 03:17:32 PM PDT 24
Finished	Jun 09 03:22:24 PM PDT 24
Peak memory	608008 kb
Host	smart-8820bcd1-43e1-411e-821c-e313e435b67f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256395234 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.256395234
Directory	/workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.620150325
Short name	T761
Test name
Test status
Simulation time	4650936348 ps
CPU time	497.37 seconds
Started	Jun 09 03:11:37 PM PDT 24
Finished	Jun 09 03:19:55 PM PDT 24
Peak memory	607196 kb
Host	smart-4ddde0cd-4cde-4889-a8f5-0a0ab30acace
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620 150325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.620150325
Directory	/workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.775766050
Short name	T708
Test name
Test status
Simulation time	9782988448 ps
CPU time	453.5 seconds
Started	Jun 09 03:11:35 PM PDT 24
Finished	Jun 09 03:19:08 PM PDT 24
Peak memory	614196 kb
Host	smart-b12c0a83-6755-4995-b52b-62f1961aac26
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775766050 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.775766050
Directory	/workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1120186874
Short name	T352
Test name
Test status
Simulation time	12127921064 ps
CPU time	2252.32 seconds
Started	Jun 09 03:13:15 PM PDT 24
Finished	Jun 09 03:50:48 PM PDT 24
Peak memory	608668 kb
Host	smart-8a55fd3b-db6e-4b8b-895c-201035b4affe
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1120186874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.1120186874
Directory	/workspace/0.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4036952668
Short name	T266
Test name
Test status
Simulation time	4390980130 ps
CPU time	459.3 seconds
Started	Jun 09 03:14:27 PM PDT 24
Finished	Jun 09 03:22:07 PM PDT 24
Peak memory	607108 kb
Host	smart-9be95764-498d-4417-9dc9-343ed5250b3a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036952668 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.4036952668
Directory	/workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1121345798
Short name	T807
Test name
Test status
Simulation time	4268729840 ps
CPU time	603.5 seconds
Started	Jun 09 03:13:22 PM PDT 24
Finished	Jun 09 03:23:26 PM PDT 24
Peak memory	639088 kb
Host	smart-a68e7cb8-9e7f-46a5-b2ab-c624ae195530
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1121345798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.1121345798
Directory	/workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.393112952
Short name	T564
Test name
Test status
Simulation time	3394366150 ps
CPU time	265.67 seconds
Started	Jun 09 03:19:00 PM PDT 24
Finished	Jun 09 03:23:26 PM PDT 24
Peak memory	607188 kb
Host	smart-399f45d7-f75f-45d4-a1e2-5782d6f42c54
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393112952 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_rstmgr_smoketest.393112952
Directory	/workspace/0.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1218990760
Short name	T588
Test name
Test status
Simulation time	4167897132 ps
CPU time	472.01 seconds
Started	Jun 09 03:12:53 PM PDT 24
Finished	Jun 09 03:20:46 PM PDT 24
Peak memory	606688 kb
Host	smart-4344ce33-9894-4c32-a0b6-351b5cd1b0f4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218990760 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.1218990760
Directory	/workspace/0.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1276007752
Short name	T296
Test name
Test status
Simulation time	2270725717 ps
CPU time	266.6 seconds
Started	Jun 09 03:14:56 PM PDT 24
Finished	Jun 09 03:19:22 PM PDT 24
Peak memory	606360 kb
Host	smart-b22e4c73-c816-4293-b8d2-893f50641e83
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276007752 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.1276007752
Directory	/workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.123257965
Short name	T739
Test name
Test status
Simulation time	6125025152 ps
CPU time	992.96 seconds
Started	Jun 09 03:11:53 PM PDT 24
Finished	Jun 09 03:28:27 PM PDT 24
Peak memory	606944 kb
Host	smart-fbbef1f3-97b0-4cdc-ab16-4b245e4a8235
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=123257965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.123257965
Directory	/workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1106608441
Short name	T21
Test name
Test status
Simulation time	4689433176 ps
CPU time	380.86 seconds
Started	Jun 09 03:11:59 PM PDT 24
Finished	Jun 09 03:18:20 PM PDT 24
Peak memory	616736 kb
Host	smart-3d139382-f47b-4d2d-a432-94b7605352a8
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110660 8441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1106608441
Directory	/workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3474850449
Short name	T550
Test name
Test status
Simulation time	2793537264 ps
CPU time	345.28 seconds
Started	Jun 09 03:17:52 PM PDT 24
Finished	Jun 09 03:23:37 PM PDT 24
Peak memory	606352 kb
Host	smart-4502df53-bfa4-4ff8-a1a2-833c2c6eed1c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474850449 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.3474850449
Directory	/workspace/0.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_irq.597180874
Short name	T997
Test name
Test status
Simulation time	2975629112 ps
CPU time	282.23 seconds
Started	Jun 09 03:13:53 PM PDT 24
Finished	Jun 09 03:18:36 PM PDT 24
Peak memory	606312 kb
Host	smart-be253cac-eace-4554-896b-09ee80f19e3b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597180874 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_irq.597180874
Directory	/workspace/0.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2685055073
Short name	T258
Test name
Test status
Simulation time	3389746556 ps
CPU time	294.88 seconds
Started	Jun 09 03:16:13 PM PDT 24
Finished	Jun 09 03:21:08 PM PDT 24
Peak memory	606320 kb
Host	smart-9627c153-49a5-4ea3-b19c-f0954eafbef2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685055073 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.2685055073
Directory	/workspace/0.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.998645541
Short name	T147
Test name
Test status
Simulation time	2984861515 ps
CPU time	377.67 seconds
Started	Jun 09 03:13:06 PM PDT 24
Finished	Jun 09 03:19:24 PM PDT 24
Peak memory	608712 kb
Host	smart-38af76f4-9c35-4906-aad6-ea0d7d64e5ab
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9986455 41 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.998645541
Directory	/workspace/0.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1927266838
Short name	T314
Test name
Test status
Simulation time	8713369708 ps
CPU time	1191.29 seconds
Started	Jun 09 03:12:02 PM PDT 24
Finished	Jun 09 03:31:54 PM PDT 24
Peak memory	607548 kb
Host	smart-4a173bc0-314c-435d-8bf7-ed00d9fca0f8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927266838 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.1927266838
Directory	/workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.433742203
Short name	T961
Test name
Test status
Simulation time	7239361520 ps
CPU time	881.36 seconds
Started	Jun 09 03:12:24 PM PDT 24
Finished	Jun 09 03:27:06 PM PDT 24
Peak memory	608328 kb
Host	smart-94140289-1af9-4188-a911-b3bb365daaae
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433742203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sle ep_sram_ret_contents_no_scramble.433742203
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3338772578
Short name	T39
Test name
Test status
Simulation time	7372652144 ps
CPU time	882.26 seconds
Started	Jun 09 03:12:30 PM PDT 24
Finished	Jun 09 03:27:13 PM PDT 24
Peak memory	623852 kb
Host	smart-3c13ebb9-e98e-441f-8649-d7e36b1b51ba
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338772578 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.3338772578
Directory	/workspace/0.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.139748060
Short name	T61
Test name
Test status
Simulation time	3046551570 ps
CPU time	310.32 seconds
Started	Jun 09 03:11:17 PM PDT 24
Finished	Jun 09 03:16:27 PM PDT 24
Peak memory	607028 kb
Host	smart-8a95d080-bcbe-4523-9e81-2e703e35a9ee
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139748060 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.139748060
Directory	/workspace/0.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1134638467
Short name	T947
Test name
Test status
Simulation time	5309306000 ps
CPU time	616.23 seconds
Started	Jun 09 03:13:44 PM PDT 24
Finished	Jun 09 03:24:01 PM PDT 24
Peak memory	607560 kb
Host	smart-afd1619c-8e2e-4598-b388-4206cd59d37b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134638467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.1134638467
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3934648475
Short name	T287
Test name
Test status
Simulation time	3997028412 ps
CPU time	647.06 seconds
Started	Jun 09 03:20:30 PM PDT 24
Finished	Jun 09 03:31:19 PM PDT 24
Peak memory	607280 kb
Host	smart-0ae0c7ce-baa5-4a1e-abbe-076843f102a2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934648475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3934648475
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3230730944
Short name	T923
Test name
Test status
Simulation time	3558336608 ps
CPU time	332.62 seconds
Started	Jun 09 03:19:55 PM PDT 24
Finished	Jun 09 03:25:28 PM PDT 24
Peak memory	606328 kb
Host	smart-1fbde32e-d382-4dc6-a28a-42b61806568b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230730944 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3230730944
Directory	/workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1453777139
Short name	T47
Test name
Test status
Simulation time	20223452999 ps
CPU time	3693.79 seconds
Started	Jun 09 03:12:09 PM PDT 24
Finished	Jun 09 04:13:43 PM PDT 24
Peak memory	607332 kb
Host	smart-39ce9f01-7053-4a7a-9316-a30f94d90f94
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453777139 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.1453777139
Directory	/workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1270177404
Short name	T227
Test name
Test status
Simulation time	4828201388 ps
CPU time	541.79 seconds
Started	Jun 09 03:13:26 PM PDT 24
Finished	Jun 09 03:22:29 PM PDT 24
Peak memory	611400 kb
Host	smart-302a8af7-78c5-44cd-b7ec-308dd8915a04
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270177404 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1270177404
Directory	/workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1072124806
Short name	T213
Test name
Test status
Simulation time	3145154702 ps
CPU time	353.07 seconds
Started	Jun 09 03:16:13 PM PDT 24
Finished	Jun 09 03:22:08 PM PDT 24
Peak memory	610760 kb
Host	smart-81878033-ed0e-4c83-9a6d-fb0c4a72c25a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072124806 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.1072124806
Directory	/workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3263616510
Short name	T229
Test name
Test status
Simulation time	23063237850 ps
CPU time	1357.54 seconds
Started	Jun 09 03:10:54 PM PDT 24
Finished	Jun 09 03:33:32 PM PDT 24
Peak memory	611588 kb
Host	smart-b1f28f35-2a96-4f72-8a6f-345df4efa5f9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32636165 10 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.3263616510
Directory	/workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1038131046
Short name	T166
Test name
Test status
Simulation time	4126454434 ps
CPU time	607.22 seconds
Started	Jun 09 03:12:04 PM PDT 24
Finished	Jun 09 03:22:12 PM PDT 24
Peak memory	617572 kb
Host	smart-132e2afe-bda5-4e92-83e5-8231f7390b57
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1038131046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1038131046
Directory	/workspace/0.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_smoketest.2395253677
Short name	T932
Test name
Test status
Simulation time	3339110272 ps
CPU time	268.24 seconds
Started	Jun 09 03:16:16 PM PDT 24
Finished	Jun 09 03:20:44 PM PDT 24
Peak memory	607636 kb
Host	smart-77d7bd9b-ddbe-4aaf-9e8c-4fb97faceccd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395253677 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.2395253677
Directory	/workspace/0.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.649675967
Short name	T767
Test name
Test status
Simulation time	13615349340 ps
CPU time	2651.4 seconds
Started	Jun 09 03:13:22 PM PDT 24
Finished	Jun 09 03:57:34 PM PDT 24
Peak memory	619620 kb
Host	smart-4daecd4c-58bb-4a1a-a62a-dbb3e1e9a8a6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649675967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq.649675967
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1217652044
Short name	T42
Test name
Test status
Simulation time	4672447200 ps
CPU time	450.87 seconds
Started	Jun 09 03:16:53 PM PDT 24
Finished	Jun 09 03:24:26 PM PDT 24
Peak memory	615644 kb
Host	smart-32567f15-3684-4037-99ee-25a6207b289b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217652044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1217652044
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3585436174
Short name	T665
Test name
Test status
Simulation time	4268198084 ps
CPU time	509.56 seconds
Started	Jun 09 03:10:40 PM PDT 24
Finished	Jun 09 03:19:10 PM PDT 24
Peak memory	615276 kb
Host	smart-d0206fc5-c095-4dbb-b1c3-239b466b3bf7
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585436174 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3585436174
Directory	/workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.523200838
Short name	T370
Test name
Test status
Simulation time	4507224984 ps
CPU time	740.45 seconds
Started	Jun 09 03:12:04 PM PDT 24
Finished	Jun 09 03:24:25 PM PDT 24
Peak memory	615528 kb
Host	smart-a98daa9b-26e1-43d4-b36e-cd1f5d68c24d
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523200838 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.523200838
Directory	/workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4270265185
Short name	T402
Test name
Test status
Simulation time	3804819056 ps
CPU time	379.37 seconds
Started	Jun 09 03:13:11 PM PDT 24
Finished	Jun 09 03:19:31 PM PDT 24
Peak memory	606884 kb
Host	smart-74623dbf-bf18-4440-845c-09fba47d23b9
User	root
Command	/workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270265185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.4270265185
Directory	/workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_config_host.488814998
Short name	T49
Test name
Test status
Simulation time	7867647448 ps
CPU time	2038.56 seconds
Started	Jun 09 03:13:09 PM PDT 24
Finished	Jun 09 03:47:09 PM PDT 24
Peak memory	606412 kb
Host	smart-2458f316-760c-4dc6-a48f-6b72439d85b7
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48881 4998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.488814998
Directory	/workspace/0.chip_sw_usbdev_config_host/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_dpi.2361272554
Short name	T48
Test name
Test status
Simulation time	12586717936 ps
CPU time	2900.28 seconds
Started	Jun 09 03:13:06 PM PDT 24
Finished	Jun 09 04:01:26 PM PDT 24
Peak memory	607068 kb
Host	smart-cce8e27f-0bc0-43c3-88ab-ed6e0a935ff1
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2361272554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.2361272554
Directory	/workspace/0.chip_sw_usbdev_dpi/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pullup.2048925835
Short name	T126
Test name
Test status
Simulation time	3288474704 ps
CPU time	311.78 seconds
Started	Jun 09 03:13:52 PM PDT 24
Finished	Jun 09 03:19:05 PM PDT 24
Peak memory	606384 kb
Host	smart-da2d0fd1-b9da-4651-a23f-0a6fcf5cb1d8
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048925835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2048925835
Directory	/workspace/0.chip_sw_usbdev_pullup/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1521556517
Short name	T222
Test name
Test status
Simulation time	4627279852 ps
CPU time	566.73 seconds
Started	Jun 09 03:13:57 PM PDT 24
Finished	Jun 09 03:23:24 PM PDT 24
Peak memory	606940 kb
Host	smart-9e386b7e-8685-4716-90d0-02c157981266
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152155651 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.1521556517
Directory	/workspace/0.chip_sw_usbdev_setuprx/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_stream.1609911944
Short name	T223
Test name
Test status
Simulation time	18545100640 ps
CPU time	4729.11 seconds
Started	Jun 09 03:13:09 PM PDT 24
Finished	Jun 09 04:31:59 PM PDT 24
Peak memory	607056 kb
Host	smart-3d4aaeac-467f-4633-8dba-feecc0aedee3
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1609911944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.1609911944
Directory	/workspace/0.chip_sw_usbdev_stream/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_vbus.872087369
Short name	T130
Test name
Test status
Simulation time	3191968108 ps
CPU time	259.82 seconds
Started	Jun 09 03:11:07 PM PDT 24
Finished	Jun 09 03:15:27 PM PDT 24
Peak memory	606508 kb
Host	smart-f61bb7bb-8b5b-4ad7-ba2b-9913e23ff6da
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872087369 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.872087369
Directory	/workspace/0.chip_sw_usbdev_vbus/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_dev.1312175715
Short name	T613
Test name
Test status
Simulation time	2830728456 ps
CPU time	120.87 seconds
Started	Jun 09 03:11:57 PM PDT 24
Finished	Jun 09 03:13:59 PM PDT 24
Peak memory	617660 kb
Host	smart-be79757d-8c4a-493d-bde3-9a51a3b18760
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1312175715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.1312175715
Directory	/workspace/0.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_prod.2261333962
Short name	T722
Test name
Test status
Simulation time	2356647893 ps
CPU time	145.67 seconds
Started	Jun 09 03:12:00 PM PDT 24
Finished	Jun 09 03:14:26 PM PDT 24
Peak memory	617348 kb
Host	smart-88ac13a5-f2ad-4ca9-ac8c-b1235ab0a48a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261333962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2261333962
Directory	/workspace/0.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_rma.3975690897
Short name	T121
Test name
Test status
Simulation time	7240211946 ps
CPU time	729.49 seconds
Started	Jun 09 03:11:26 PM PDT 24
Finished	Jun 09 03:23:36 PM PDT 24
Peak memory	622060 kb
Host	smart-edcdf1ac-e60a-43ab-92d1-3bcfef50f334
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975690897 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3975690897
Directory	/workspace/0.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_testunlock0.3657013857
Short name	T119
Test name
Test status
Simulation time	7955768879 ps
CPU time	722.04 seconds
Started	Jun 09 03:11:58 PM PDT 24
Finished	Jun 09 03:24:00 PM PDT 24
Peak memory	620076 kb
Host	smart-989dd914-e430-468d-ae08-2f7da89478df
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3657013857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.3657013857
Directory	/workspace/0.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_dev.1318425969
Short name	T777
Test name
Test status
Simulation time	14469083031 ps
CPU time	3764.13 seconds
Started	Jun 09 03:19:31 PM PDT 24
Finished	Jun 09 04:22:16 PM PDT 24
Peak memory	607144 kb
Host	smart-4348081f-df79-4241-86a9-4ae412181a5e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318425969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.1318425969
Directory	/workspace/0.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_prod.2342220569
Short name	T898
Test name
Test status
Simulation time	14162488034 ps
CPU time	3759.02 seconds
Started	Jun 09 03:19:16 PM PDT 24
Finished	Jun 09 04:21:56 PM PDT 24
Peak memory	607128 kb
Host	smart-cfe94b02-155e-4b82-9dc8-00bd186cf060
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342220569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.2342220569
Directory	/workspace/0.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3777879139
Short name	T816
Test name
Test status
Simulation time	14251945092 ps
CPU time	3519.32 seconds
Started	Jun 09 03:19:59 PM PDT 24
Finished	Jun 09 04:18:39 PM PDT 24
Peak memory	607136 kb
Host	smart-e719c048-3114-466e-acf2-cfd299d893e6
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777879139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.3777879139
Directory	/workspace/0.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_rma.1130008629
Short name	T716
Test name
Test status
Simulation time	14835740454 ps
CPU time	3526.14 seconds
Started	Jun 09 03:17:56 PM PDT 24
Finished	Jun 09 04:16:43 PM PDT 24
Peak memory	606692 kb
Host	smart-0afad9a9-5faf-4f8a-a084-743a99ee38e9
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130008629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.1130008629
Directory	/workspace/0.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.616890431
Short name	T698
Test name
Test status
Simulation time	11467302362 ps
CPU time	3015.46 seconds
Started	Jun 09 03:20:09 PM PDT 24
Finished	Jun 09 04:10:25 PM PDT 24
Peak memory	607704 kb
Host	smart-96af20eb-ab97-4186-b06e-fbc45cd810c9
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616890431 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.rom_e2e_asm_init_test_unlocked0.616890431
Directory	/workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3329531788
Short name	T250
Test name
Test status
Simulation time	22934867560 ps
CPU time	5401.22 seconds
Started	Jun 09 03:20:08 PM PDT 24
Finished	Jun 09 04:50:10 PM PDT 24
Peak memory	607292 kb
Host	smart-f6ad6c64-0def-41e3-aa7b-88ef2573ec94
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3329531788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3329531788
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1836744281
Short name	T975
Test name
Test status
Simulation time	22531837908 ps
CPU time	5595.02 seconds
Started	Jun 09 03:21:20 PM PDT 24
Finished	Jun 09 04:54:36 PM PDT 24
Peak memory	607192 kb
Host	smart-4e537826-ede1-4e53-8511-7724600c8a3f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1836744281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1836744281
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2637983142
Short name	T843
Test name
Test status
Simulation time	22301533524 ps
CPU time	6430.08 seconds
Started	Jun 09 03:19:51 PM PDT 24
Finished	Jun 09 05:07:03 PM PDT 24
Peak memory	607172 kb
Host	smart-60e2c7fb-7b82-44c1-bb72-b08eed8a4fa6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2637983142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2637983142
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4144182405
Short name	T249
Test name
Test status
Simulation time	17623130920 ps
CPU time	4827.68 seconds
Started	Jun 09 03:18:19 PM PDT 24
Finished	Jun 09 04:38:48 PM PDT 24
Peak memory	607092 kb
Host	smart-4c795284-5ea6-404e-a5ca-9f5758aaa921
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144182405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4144182405
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1975418862
Short name	T615
Test name
Test status
Simulation time	14655400920 ps
CPU time	4013.4 seconds
Started	Jun 09 03:21:53 PM PDT 24
Finished	Jun 09 04:28:47 PM PDT 24
Peak memory	607780 kb
Host	smart-22be1d81-8f06-4291-a2aa-5ec4af734ece
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1975418862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1975418862
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3019455608
Short name	T912
Test name
Test status
Simulation time	14473615088 ps
CPU time	3567.04 seconds
Started	Jun 09 03:21:16 PM PDT 24
Finished	Jun 09 04:20:44 PM PDT 24
Peak memory	607648 kb
Host	smart-bcb9a915-fdb5-400b-86e9-81dc4343fcd7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3019455608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3019455608
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.208893501
Short name	T884
Test name
Test status
Simulation time	14714744898 ps
CPU time	4307.59 seconds
Started	Jun 09 03:21:36 PM PDT 24
Finished	Jun 09 04:33:25 PM PDT 24
Peak memory	607296 kb
Host	smart-7ef42a38-b15a-4f43-8dcc-490505c47823
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=208893501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.208893501
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1277438188
Short name	T695
Test name
Test status
Simulation time	14821223680 ps
CPU time	3812.86 seconds
Started	Jun 09 03:21:29 PM PDT 24
Finished	Jun 09 04:25:03 PM PDT 24
Peak memory	607140 kb
Host	smart-80ba4bd3-338e-4502-bbd4-846c4beda05c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1277438188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1277438188
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2542896644
Short name	T892
Test name
Test status
Simulation time	10766929000 ps
CPU time	3195.24 seconds
Started	Jun 09 03:18:13 PM PDT 24
Finished	Jun 09 04:11:29 PM PDT 24
Peak memory	607104 kb
Host	smart-05410559-4be7-4804-81f9-743eae6be26d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542896644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2542896644
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1826070973
Short name	T561
Test name
Test status
Simulation time	14099134852 ps
CPU time	3522.94 seconds
Started	Jun 09 03:20:38 PM PDT 24
Finished	Jun 09 04:19:21 PM PDT 24
Peak memory	607576 kb
Host	smart-fb89e468-698b-4e6b-a126-a4c2aad0ed59
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826070973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1826070973
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2846359518
Short name	T285
Test name
Test status
Simulation time	14733553502 ps
CPU time	4348.66 seconds
Started	Jun 09 03:19:08 PM PDT 24
Finished	Jun 09 04:31:38 PM PDT 24
Peak memory	607008 kb
Host	smart-b4883b41-96b2-4847-ac67-f451a00aeeb2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846359518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2846359518
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1606057804
Short name	T600
Test name
Test status
Simulation time	14899935192 ps
CPU time	3535.96 seconds
Started	Jun 09 03:21:19 PM PDT 24
Finished	Jun 09 04:20:15 PM PDT 24
Peak memory	607044 kb
Host	smart-99e3bf87-53fd-42a1-8047-493377f261bc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160605 7804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1606057804
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3546973855
Short name	T830
Test name
Test status
Simulation time	14602144300 ps
CPU time	3878.85 seconds
Started	Jun 09 03:19:13 PM PDT 24
Finished	Jun 09 04:23:52 PM PDT 24
Peak memory	607604 kb
Host	smart-79a499d9-69d4-4e1d-983c-413ab37d076a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546973855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3546973855
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1285523697
Short name	T778
Test name
Test status
Simulation time	10880419440 ps
CPU time	3729.98 seconds
Started	Jun 09 03:20:55 PM PDT 24
Finished	Jun 09 04:23:06 PM PDT 24
Peak memory	607480 kb
Host	smart-24b13767-2459-43c7-804d-e79a1bd6697f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1285523697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1285523697
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2214625707
Short name	T350
Test name
Test status
Simulation time	14750453163 ps
CPU time	2517.9 seconds
Started	Jun 09 03:16:27 PM PDT 24
Finished	Jun 09 03:58:26 PM PDT 24
Peak memory	616996 kb
Host	smart-ad6ce093-bd90-49f6-9732-df752db2f795
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22146 25707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.2214625707
Directory	/workspace/0.rom_e2e_jtag_debug_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2738679695
Short name	T337
Test name
Test status
Simulation time	14726369706 ps
CPU time	1809.72 seconds
Started	Jun 09 03:15:07 PM PDT 24
Finished	Jun 09 03:45:18 PM PDT 24
Peak memory	617144 kb
Host	smart-f735992b-d62d-41b9-b113-c83f105b8a9f
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2738679695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.2738679695
Directory	/workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2771232701
Short name	T707
Test name
Test status
Simulation time	14023133718 ps
CPU time	4308.51 seconds
Started	Jun 09 03:20:29 PM PDT 24
Finished	Jun 09 04:32:19 PM PDT 24
Peak memory	607088 kb
Host	smart-bc5af374-747b-4a46-80a3-2a6f6c0a36bc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771232701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2771232701
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3047419278
Short name	T621
Test name
Test status
Simulation time	15719780464 ps
CPU time	3763.55 seconds
Started	Jun 09 03:20:52 PM PDT 24
Finished	Jun 09 04:23:36 PM PDT 24
Peak memory	606940 kb
Host	smart-37d808f5-2697-4266-9e5c-6503a3e88323
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047419278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.3047419278
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3904660971
Short name	T660
Test name
Test status
Simulation time	14838802764 ps
CPU time	3863.56 seconds
Started	Jun 09 03:21:04 PM PDT 24
Finished	Jun 09 04:25:29 PM PDT 24
Peak memory	606704 kb
Host	smart-b104bd06-565e-407b-b8d9-f1b31d8584ff
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904660971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.3904660971
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.199664997
Short name	T635
Test name
Test status
Simulation time	14361735752 ps
CPU time	4076.6 seconds
Started	Jun 09 03:19:29 PM PDT 24
Finished	Jun 09 04:27:26 PM PDT 24
Peak memory	606960 kb
Host	smart-06f8b876-d49e-4b05-971e-ea6a1d1aaf39
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199664997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_s hutdown_exception_c.199664997
Directory	/workspace/0.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/0.rom_e2e_shutdown_output.3358689806
Short name	T896
Test name
Test status
Simulation time	22927450834 ps
CPU time	3278.47 seconds
Started	Jun 09 03:17:43 PM PDT 24
Finished	Jun 09 04:12:22 PM PDT 24
Peak memory	608148 kb
Host	smart-45c0a9ea-4f07-4f6f-8bfe-5ebbd1295220
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358689806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.3358689806
Directory	/workspace/0.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.4125843774
Short name	T874
Test name
Test status
Simulation time	22599053252 ps
CPU time	5678.72 seconds
Started	Jun 09 03:21:29 PM PDT 24
Finished	Jun 09 04:56:09 PM PDT 24
Peak memory	607620 kb
Host	smart-68854543-fd02-49f2-b294-d97ecfdd4348
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4125843774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.4125843774
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3670128876
Short name	T786
Test name
Test status
Simulation time	22418603748 ps
CPU time	5996.4 seconds
Started	Jun 09 03:22:11 PM PDT 24
Finished	Jun 09 05:02:08 PM PDT 24
Peak memory	607140 kb
Host	smart-98702882-a984-4113-939a-454d74d2bb73
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3670128876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.3670128876
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1598275357
Short name	T864
Test name
Test status
Simulation time	22013551219 ps
CPU time	5679.93 seconds
Started	Jun 09 03:20:34 PM PDT 24
Finished	Jun 09 04:55:15 PM PDT 24
Peak memory	607168 kb
Host	smart-7e386703-ce2d-4c8b-bb56-ced41fb40858
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1598275357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.1598275357
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.83622734
Short name	T793
Test name
Test status
Simulation time	21762943173 ps
CPU time	5072.15 seconds
Started	Jun 09 03:18:54 PM PDT 24
Finished	Jun 09 04:43:27 PM PDT 24
Peak memory	607236 kb
Host	smart-52eca88a-8d52-4c58-addb-122427483d51
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=83622734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.83622734
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1101867712
Short name	T276
Test name
Test status
Simulation time	17794200255 ps
CPU time	4910.93 seconds
Started	Jun 09 03:17:46 PM PDT 24
Finished	Jun 09 04:39:37 PM PDT 24
Peak memory	607228 kb
Host	smart-65959b52-6209-4d30-b2ab-c0afb1aa4e68
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1101867712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.1101867712
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2674272323
Short name	T936
Test name
Test status
Simulation time	13318599380 ps
CPU time	3128.78 seconds
Started	Jun 09 03:20:13 PM PDT 24
Finished	Jun 09 04:12:23 PM PDT 24
Peak memory	607268 kb
Host	smart-00016902-e67d-4339-91ec-ee1f1f36921a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674272323 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2674272323
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3239459848
Short name	T861
Test name
Test status
Simulation time	13765033470 ps
CPU time	3754.49 seconds
Started	Jun 09 03:19:23 PM PDT 24
Finished	Jun 09 04:21:58 PM PDT 24
Peak memory	608024 kb
Host	smart-278accc5-509f-4394-bc09-c850bef477e4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239459848 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3239459848
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.285520711
Short name	T646
Test name
Test status
Simulation time	13023003542 ps
CPU time	3413.52 seconds
Started	Jun 09 03:21:12 PM PDT 24
Finished	Jun 09 04:18:06 PM PDT 24
Peak memory	608176 kb
Host	smart-14a2c530-e58f-447d-9e73-f3c9f63249ef
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285520711 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.285520711
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.973544785
Short name	T875
Test name
Test status
Simulation time	10749179941 ps
CPU time	3011.78 seconds
Started	Jun 09 03:19:03 PM PDT 24
Finished	Jun 09 04:09:16 PM PDT 24
Peak memory	607064 kb
Host	smart-6e1ef193-35e6-44f9-818e-3edc583a4939
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973544785 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.973544785
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3329329878
Short name	T750
Test name
Test status
Simulation time	13692864072 ps
CPU time	4306.91 seconds
Started	Jun 09 03:18:57 PM PDT 24
Finished	Jun 09 04:30:44 PM PDT 24
Peak memory	606924 kb
Host	smart-2b0b79b4-ce9f-43e0-a293-bce89438b2e2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329329878 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3329329878
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3869818710
Short name	T680
Test name
Test status
Simulation time	14729047100 ps
CPU time	3797.69 seconds
Started	Jun 09 03:19:44 PM PDT 24
Finished	Jun 09 04:23:03 PM PDT 24
Peak memory	606972 kb
Host	smart-76fff0e7-1e36-46c0-aab8-696d0c04988f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869818710 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3869818710
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.112404879
Short name	T68
Test name
Test status
Simulation time	13780549656 ps
CPU time	3277.99 seconds
Started	Jun 09 03:19:22 PM PDT 24
Finished	Jun 09 04:14:01 PM PDT 24
Peak memory	606988 kb
Host	smart-10aa8023-d12d-4a93-a097-44b60cb96933
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112404879 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.112404879
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.486421812
Short name	T278
Test name
Test status
Simulation time	13808085050 ps
CPU time	3812.06 seconds
Started	Jun 09 03:19:00 PM PDT 24
Finished	Jun 09 04:22:32 PM PDT 24
Peak memory	608000 kb
Host	smart-b8e9c0b7-8e28-449e-9f59-069200f4c3c6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486421812 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.486421812
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.772901831
Short name	T69
Test name
Test status
Simulation time	10886158137 ps
CPU time	2754.23 seconds
Started	Jun 09 03:21:37 PM PDT 24
Finished	Jun 09 04:07:31 PM PDT 24
Peak memory	608124 kb
Host	smart-46968e53-5eea-4149-845f-9020ccebc0cf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772901831 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.772901831
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_smoke.1176412287
Short name	T819
Test name
Test status
Simulation time	13690652148 ps
CPU time	3616.93 seconds
Started	Jun 09 03:16:27 PM PDT 24
Finished	Jun 09 04:16:45 PM PDT 24
Peak memory	607084 kb
Host	smart-a441731b-f43e-4bda-b39e-c890b43858c6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1176412287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.1176412287
Directory	/workspace/0.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/0.rom_e2e_static_critical.2176408800
Short name	T599
Test name
Test status
Simulation time	16879886960 ps
CPU time	4067.81 seconds
Started	Jun 09 03:23:16 PM PDT 24
Finished	Jun 09 04:31:05 PM PDT 24
Peak memory	607112 kb
Host	smart-bfddca5a-88fd-4110-974e-44bab0bb39b0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176408800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2176408800
Directory	/workspace/0.rom_e2e_static_critical/latest

Test location	/workspace/coverage/default/0.rom_keymgr_functest.3389996513
Short name	T850
Test name
Test status
Simulation time	5279833198 ps
CPU time	757.72 seconds
Started	Jun 09 03:17:31 PM PDT 24
Finished	Jun 09 03:30:09 PM PDT 24
Peak memory	608208 kb
Host	smart-376561e1-b137-44e7-b6cb-01417d27e49c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389996513 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.3389996513
Directory	/workspace/0.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/0.rom_volatile_raw_unlock.3813764448
Short name	T431
Test name
Test status
Simulation time	2615236866 ps
CPU time	129.22 seconds
Started	Jun 09 03:17:58 PM PDT 24
Finished	Jun 09 03:20:08 PM PDT 24
Peak memory	614260 kb
Host	smart-257ec7c1-f849-4df7-8749-7e2b63443a96
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813764448 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.3813764448
Directory	/workspace/0.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/1.chip_jtag_mem_access.2864509307
Short name	T24
Test name
Test status
Simulation time	13249831544 ps
CPU time	1736.87 seconds
Started	Jun 09 03:18:05 PM PDT 24
Finished	Jun 09 03:47:03 PM PDT 24
Peak memory	601908 kb
Host	smart-a675bf55-9230-4fce-a678-c71ed2241363
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864509307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.2 864509307
Directory	/workspace/1.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2328894509
Short name	T336
Test name
Test status
Simulation time	3406137924 ps
CPU time	360.4 seconds
Started	Jun 09 03:24:56 PM PDT 24
Finished	Jun 09 03:30:56 PM PDT 24
Peak memory	617420 kb
Host	smart-6718e4f1-ca0c-40cf-a98f-3746aa762205
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 328894509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2328894509
Directory	/workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/1.chip_sival_flash_info_access.765986466
Short name	T968
Test name
Test status
Simulation time	3376545040 ps
CPU time	283.58 seconds
Started	Jun 09 03:19:06 PM PDT 24
Finished	Jun 09 03:23:50 PM PDT 24
Peak memory	606376 kb
Host	smart-6d2d1134-414e-411b-9450-86156470ed2c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=765986466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.765986466
Directory	/workspace/1.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3739736381
Short name	T986
Test name
Test status
Simulation time	19412551118 ps
CPU time	493.9 seconds
Started	Jun 09 03:22:55 PM PDT 24
Finished	Jun 09 03:31:10 PM PDT 24
Peak memory	614548 kb
Host	smart-b05d99a4-5984-44e0-8bc9-5b3c7f041163
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3739736381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3739736381
Directory	/workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc.4020812398
Short name	T728
Test name
Test status
Simulation time	3145593420 ps
CPU time	273.02 seconds
Started	Jun 09 03:23:08 PM PDT 24
Finished	Jun 09 03:27:41 PM PDT 24
Peak memory	606744 kb
Host	smart-9ee183cf-3ad0-4df3-a6f5-81aee9208180
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020812398 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.4020812398
Directory	/workspace/1.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3866015148
Short name	T973
Test name
Test status
Simulation time	3418509161 ps
CPU time	299.46 seconds
Started	Jun 09 03:22:04 PM PDT 24
Finished	Jun 09 03:27:04 PM PDT 24
Peak memory	606676 kb
Host	smart-3e26dedc-fee3-48fa-b6dd-404a3778049c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866 015148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.3866015148
Directory	/workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3921755153
Short name	T969
Test name
Test status
Simulation time	3475391425 ps
CPU time	350.5 seconds
Started	Jun 09 03:26:24 PM PDT 24
Finished	Jun 09 03:32:15 PM PDT 24
Peak memory	606680 kb
Host	smart-10865a60-3fc6-4242-a4a2-05f0a718422b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921755153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.3921755153
Directory	/workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_entropy.1996109654
Short name	T650
Test name
Test status
Simulation time	2827540692 ps
CPU time	214.01 seconds
Started	Jun 09 03:22:57 PM PDT 24
Finished	Jun 09 03:26:31 PM PDT 24
Peak memory	606732 kb
Host	smart-55831205-696b-49ca-be6a-44d397062ba2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996109654 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.1996109654
Directory	/workspace/1.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_idle.2969343567
Short name	T419
Test name
Test status
Simulation time	2707024094 ps
CPU time	245.88 seconds
Started	Jun 09 03:22:00 PM PDT 24
Finished	Jun 09 03:26:07 PM PDT 24
Peak memory	606736 kb
Host	smart-e9a9e0fd-e80e-407e-9025-5cc54367e365
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969343567 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.2969343567
Directory	/workspace/1.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_masking_off.1505536084
Short name	T390
Test name
Test status
Simulation time	2915605751 ps
CPU time	318.37 seconds
Started	Jun 09 03:21:57 PM PDT 24
Finished	Jun 09 03:27:16 PM PDT 24
Peak memory	607340 kb
Host	smart-6628e2d3-987a-4f29-9a3c-328f91e77a5b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505536084 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.1505536084
Directory	/workspace/1.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_smoketest.174407353
Short name	T951
Test name
Test status
Simulation time	2506773240 ps
CPU time	210.9 seconds
Started	Jun 09 03:28:46 PM PDT 24
Finished	Jun 09 03:32:17 PM PDT 24
Peak memory	606500 kb
Host	smart-5461af06-b8f2-4e23-914f-81c40431985c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174407353 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.174407353
Directory	/workspace/1.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3049049798
Short name	T730
Test name
Test status
Simulation time	3748999548 ps
CPU time	316.34 seconds
Started	Jun 09 03:21:58 PM PDT 24
Finished	Jun 09 03:27:15 PM PDT 24
Peak memory	607644 kb
Host	smart-697be650-b85d-4724-97a9-e686e1e09944
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3049049798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3049049798
Directory	/workspace/1.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3939274456
Short name	T836
Test name
Test status
Simulation time	5649089556 ps
CPU time	677.45 seconds
Started	Jun 09 03:23:10 PM PDT 24
Finished	Jun 09 03:34:27 PM PDT 24
Peak memory	614624 kb
Host	smart-b04b4b0c-42c3-451d-8ce6-cc101a8ee461
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3939274456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.3939274456
Directory	/workspace/1.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2518868479
Short name	T401
Test name
Test status
Simulation time	7804599550 ps
CPU time	1819.15 seconds
Started	Jun 09 03:22:57 PM PDT 24
Finished	Jun 09 03:53:16 PM PDT 24
Peak memory	608144 kb
Host	smart-36435eb7-bc98-4aa1-b985-18ef4ccb31ce
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2518868479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.2518868479
Directory	/workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.862690168
Short name	T962
Test name
Test status
Simulation time	8794754840 ps
CPU time	1972.73 seconds
Started	Jun 09 03:22:30 PM PDT 24
Finished	Jun 09 03:55:23 PM PDT 24
Peak memory	606988 kb
Host	smart-27c75915-7733-4353-9ec0-da62dc2f4f6c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862690168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.862690168
Directory	/workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1279133227
Short name	T263
Test name
Test status
Simulation time	10664590816 ps
CPU time	1325.07 seconds
Started	Jun 09 03:23:39 PM PDT 24
Finished	Jun 09 03:45:45 PM PDT 24
Peak memory	608696 kb
Host	smart-1a9f8673-5d48-453c-885c-3d6921324081
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279133227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1279133227
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1414076074
Short name	T637
Test name
Test status
Simulation time	7826192168 ps
CPU time	1251.75 seconds
Started	Jun 09 03:22:35 PM PDT 24
Finished	Jun 09 03:43:27 PM PDT 24
Peak memory	606948 kb
Host	smart-12eb075b-7845-4e6b-ae0b-8b3d4ccf3c34
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1414076074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.1414076074
Directory	/workspace/1.chip_sw_alert_handler_ping_ok/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.342873537
Short name	T909
Test name
Test status
Simulation time	2663769912 ps
CPU time	313.17 seconds
Started	Jun 09 03:23:35 PM PDT 24
Finished	Jun 09 03:28:48 PM PDT 24
Peak memory	606628 kb
Host	smart-daff9163-d11a-429f-b522-ea2302f0a37e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=342873537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.342873537
Directory	/workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3547283103
Short name	T855
Test name
Test status
Simulation time	256187187206 ps
CPU time	13784.9 seconds
Started	Jun 09 03:22:51 PM PDT 24
Finished	Jun 09 07:12:37 PM PDT 24
Peak memory	608560 kb
Host	smart-e5bc76a5-693b-4d0a-b137-e5cc7685f0e3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3547283103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3547283103
Directory	/workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_irq.2333170899
Short name	T800
Test name
Test status
Simulation time	4588740120 ps
CPU time	507.42 seconds
Started	Jun 09 03:22:04 PM PDT 24
Finished	Jun 09 03:30:32 PM PDT 24
Peak memory	606868 kb
Host	smart-4813b716-63c1-4f2e-bffe-37854a2f099b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333170899 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2333170899
Directory	/workspace/1.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.623639560
Short name	T893
Test name
Test status
Simulation time	7128848172 ps
CPU time	619.02 seconds
Started	Jun 09 03:23:17 PM PDT 24
Finished	Jun 09 03:33:37 PM PDT 24
Peak memory	607260 kb
Host	smart-ed9157e1-fc78-4604-9a33-f92147a0f77f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=623639560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.623639560
Directory	/workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.932336941
Short name	T955
Test name
Test status
Simulation time	2850677062 ps
CPU time	220.49 seconds
Started	Jun 09 03:27:40 PM PDT 24
Finished	Jun 09 03:31:20 PM PDT 24
Peak memory	606336 kb
Host	smart-012de6f4-cf5e-4a80-a851-1ce28905088a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932336941 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_aon_timer_smoketest.932336941
Directory	/workspace/1.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.655030902
Short name	T261
Test name
Test status
Simulation time	8747120150 ps
CPU time	641.6 seconds
Started	Jun 09 03:21:35 PM PDT 24
Finished	Jun 09 03:32:17 PM PDT 24
Peak memory	608016 kb
Host	smart-e1690870-819b-4be7-9398-01bb8d63e0dd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 655030902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.655030902
Directory	/workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3052406339
Short name	T664
Test name
Test status
Simulation time	5217652250 ps
CPU time	680.03 seconds
Started	Jun 09 03:22:16 PM PDT 24
Finished	Jun 09 03:33:37 PM PDT 24
Peak memory	607328 kb
Host	smart-9ac2f186-c6fb-4451-8c94-b87ee251a586
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3052406339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.3052406339
Directory	/workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2695519387
Short name	T453
Test name
Test status
Simulation time	8210465320 ps
CPU time	1139.57 seconds
Started	Jun 09 03:26:29 PM PDT 24
Finished	Jun 09 03:45:30 PM PDT 24
Peak memory	613808 kb
Host	smart-3fdb00eb-b5ea-43c8-b379-0f0bca28495f
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695519387 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2695519387
Directory	/workspace/1.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3401339771
Short name	T765
Test name
Test status
Simulation time	5260538456 ps
CPU time	443.36 seconds
Started	Jun 09 03:23:54 PM PDT 24
Finished	Jun 09 03:31:18 PM PDT 24
Peak memory	618876 kb
Host	smart-b8af2ef3-c7e6-441d-97ce-fbb8f6cde041
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3401339771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.3401339771
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2566780943
Short name	T168
Test name
Test status
Simulation time	4774525200 ps
CPU time	792.64 seconds
Started	Jun 09 03:27:46 PM PDT 24
Finished	Jun 09 03:40:59 PM PDT 24
Peak memory	610524 kb
Host	smart-7c240671-fc75-4d0b-9150-fd90c828415d
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566780943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2566780943
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1397445474
Short name	T723
Test name
Test status
Simulation time	4256561392 ps
CPU time	627 seconds
Started	Jun 09 03:25:13 PM PDT 24
Finished	Jun 09 03:35:41 PM PDT 24
Peak memory	610508 kb
Host	smart-101f5363-1637-412e-a6ee-140043337645
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397445474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1397445474
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2475980644
Short name	T590
Test name
Test status
Simulation time	4033551090 ps
CPU time	612.72 seconds
Started	Jun 09 03:25:12 PM PDT 24
Finished	Jun 09 03:35:25 PM PDT 24
Peak memory	610576 kb
Host	smart-1a969340-8e95-449d-8034-1780d8b5f606
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475980644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2475980644
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3207540175
Short name	T562
Test name
Test status
Simulation time	4878058556 ps
CPU time	822.38 seconds
Started	Jun 09 03:25:19 PM PDT 24
Finished	Jun 09 03:39:02 PM PDT 24
Peak memory	610540 kb
Host	smart-26b27cbe-5473-4631-8d51-0c83d2324223
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207540175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3207540175
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.446375012
Short name	T705
Test name
Test status
Simulation time	5132216794 ps
CPU time	664.84 seconds
Started	Jun 09 03:28:18 PM PDT 24
Finished	Jun 09 03:39:23 PM PDT 24
Peak memory	610276 kb
Host	smart-cf0472e9-dd2f-4a51-8d02-5464a7b79b8b
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446375012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.446375012
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.980200080
Short name	T983
Test name
Test status
Simulation time	5090510326 ps
CPU time	676.64 seconds
Started	Jun 09 03:24:30 PM PDT 24
Finished	Jun 09 03:35:47 PM PDT 24
Peak memory	610544 kb
Host	smart-6fa3c058-c6ce-415d-b15c-07accf299b81
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980200080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.980200080
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.339133536
Short name	T572
Test name
Test status
Simulation time	2212665374 ps
CPU time	166.65 seconds
Started	Jun 09 03:28:17 PM PDT 24
Finished	Jun 09 03:31:04 PM PDT 24
Peak memory	606376 kb
Host	smart-6e7dd476-fcfa-4a1a-bee2-9d0def6f62d3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339133536 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_clkmgr_jitter.339133536
Directory	/workspace/1.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3610052256
Short name	T747
Test name
Test status
Simulation time	3574305336 ps
CPU time	533.69 seconds
Started	Jun 09 03:28:32 PM PDT 24
Finished	Jun 09 03:37:26 PM PDT 24
Peak memory	606332 kb
Host	smart-dacb34b8-17f4-4beb-a320-686ddbb01876
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610052256 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.3610052256
Directory	/workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.328080984
Short name	T136
Test name
Test status
Simulation time	2739313247 ps
CPU time	185.97 seconds
Started	Jun 09 03:26:38 PM PDT 24
Finished	Jun 09 03:29:44 PM PDT 24
Peak memory	606012 kb
Host	smart-0d4023ef-c23b-400b-ad6c-1599d247e574
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328080984 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.328080984
Directory	/workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1543408833
Short name	T545
Test name
Test status
Simulation time	4112957076 ps
CPU time	546.72 seconds
Started	Jun 09 03:27:51 PM PDT 24
Finished	Jun 09 03:36:58 PM PDT 24
Peak memory	606660 kb
Host	smart-ad61f616-ca95-440f-98c3-8ccba123c09b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543408833 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1543408833
Directory	/workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2709184645
Short name	T703
Test name
Test status
Simulation time	4062008280 ps
CPU time	343.69 seconds
Started	Jun 09 03:24:11 PM PDT 24
Finished	Jun 09 03:29:55 PM PDT 24
Peak memory	607560 kb
Host	smart-0088822b-110a-4fee-81ad-a1028f9609a3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709184645 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2709184645
Directory	/workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2724252877
Short name	T922
Test name
Test status
Simulation time	4443869088 ps
CPU time	496.54 seconds
Started	Jun 09 03:24:45 PM PDT 24
Finished	Jun 09 03:33:01 PM PDT 24
Peak memory	606956 kb
Host	smart-ad1d2bfd-1dac-4ca1-bb73-d10b5f0bc279
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724252877 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.2724252877
Directory	/workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1605253366
Short name	T568
Test name
Test status
Simulation time	4913146988 ps
CPU time	397.96 seconds
Started	Jun 09 03:24:55 PM PDT 24
Finished	Jun 09 03:31:34 PM PDT 24
Peak memory	607676 kb
Host	smart-ab6bfc8b-4014-4379-b78a-8fad17ed5bde
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605253366 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.1605253366
Directory	/workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3799878094
Short name	T610
Test name
Test status
Simulation time	9532356024 ps
CPU time	1412.54 seconds
Started	Jun 09 03:24:55 PM PDT 24
Finished	Jun 09 03:48:28 PM PDT 24
Peak memory	607372 kb
Host	smart-9e0d7553-bc4e-4e8b-93c9-f48d45ef8359
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799878094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3799878094
Directory	/workspace/1.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1027582762
Short name	T905
Test name
Test status
Simulation time	3556542218 ps
CPU time	454.08 seconds
Started	Jun 09 03:25:05 PM PDT 24
Finished	Jun 09 03:32:40 PM PDT 24
Peak memory	606412 kb
Host	smart-9dedd5a4-700c-406c-b7c5-1b5a3226dd45
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027582762 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.1027582762
Directory	/workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3462937929
Short name	T602
Test name
Test status
Simulation time	4541358834 ps
CPU time	663.11 seconds
Started	Jun 09 03:28:40 PM PDT 24
Finished	Jun 09 03:39:43 PM PDT 24
Peak memory	607696 kb
Host	smart-e9a018da-6f3b-4f90-9a0e-bbd147250e36
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462937929 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.3462937929
Directory	/workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2013870803
Short name	T908
Test name
Test status
Simulation time	2883196124 ps
CPU time	328.96 seconds
Started	Jun 09 03:29:47 PM PDT 24
Finished	Jun 09 03:35:16 PM PDT 24
Peak memory	606368 kb
Host	smart-9f4c3520-a637-4f02-afa9-8717b050cc28
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013870803 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.2013870803
Directory	/workspace/1.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1049814040
Short name	T944
Test name
Test status
Simulation time	22832410174 ps
CPU time	5087.48 seconds
Started	Jun 09 03:23:19 PM PDT 24
Finished	Jun 09 04:48:07 PM PDT 24
Peak memory	607184 kb
Host	smart-fd0d2358-f4f2-4036-9a0b-97fdcdbbad54
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049814040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.1049814040
Directory	/workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2385169396
Short name	T155
Test name
Test status
Simulation time	24196874215 ps
CPU time	4060.22 seconds
Started	Jun 09 03:27:46 PM PDT 24
Finished	Jun 09 04:35:27 PM PDT 24
Peak memory	607160 kb
Host	smart-d6217373-bf66-4482-b6f4-65873b3c87c1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2385169396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.2385169396
Directory	/workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.204527909
Short name	T666
Test name
Test status
Simulation time	5107030560 ps
CPU time	573.4 seconds
Started	Jun 09 03:24:29 PM PDT 24
Finished	Jun 09 03:34:03 PM PDT 24
Peak memory	607216 kb
Host	smart-bc64809d-e37c-4ae7-aa6a-53a1b5d83d85
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20452 7909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.204527909
Directory	/workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_kat_test.738911854
Short name	T638
Test name
Test status
Simulation time	2829466092 ps
CPU time	238.09 seconds
Started	Jun 09 03:28:11 PM PDT 24
Finished	Jun 09 03:32:10 PM PDT 24
Peak memory	606748 kb
Host	smart-33d45b6b-f6ae-4bd1-af82-53394199f532
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738911854 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.738911854
Directory	/workspace/1.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4016342688
Short name	T859
Test name
Test status
Simulation time	5072997690 ps
CPU time	709.24 seconds
Started	Jun 09 03:28:11 PM PDT 24
Finished	Jun 09 03:40:01 PM PDT 24
Peak memory	608116 kb
Host	smart-c7c353a8-a95e-429f-a91a-c9f539296d2b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016342688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.4016342688
Directory	/workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_smoketest.195222583
Short name	T619
Test name
Test status
Simulation time	2751483296 ps
CPU time	277.85 seconds
Started	Jun 09 03:27:35 PM PDT 24
Finished	Jun 09 03:32:13 PM PDT 24
Peak memory	606360 kb
Host	smart-44683483-52f2-4887-a147-e5b9befe44fd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195222583 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_csrng_smoketest.195222583
Directory	/workspace/1.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2201749433
Short name	T959
Test name
Test status
Simulation time	4681526400 ps
CPU time	1298.58 seconds
Started	Jun 09 03:23:09 PM PDT 24
Finished	Jun 09 03:44:48 PM PDT 24
Peak memory	607208 kb
Host	smart-4687b1a4-4609-4453-b913-18d73b53267b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201749433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.2201749433
Directory	/workspace/1.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_boot_mode.3082126636
Short name	T173
Test name
Test status
Simulation time	2902114200 ps
CPU time	559.79 seconds
Started	Jun 09 03:23:52 PM PDT 24
Finished	Jun 09 03:33:13 PM PDT 24
Peak memory	607540 kb
Host	smart-b81e14e5-ea85-40d5-97da-ca803e8d3413
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082126636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.3082126636
Directory	/workspace/1.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1320939511
Short name	T388
Test name
Test status
Simulation time	6954684040 ps
CPU time	915.87 seconds
Started	Jun 09 03:23:43 PM PDT 24
Finished	Jun 09 03:38:59 PM PDT 24
Peak memory	608368 kb
Host	smart-f84d23b7-6d2d-4efb-8384-a001791a7c99
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1320939511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.1320939511
Directory	/workspace/1.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.127183346
Short name	T101
Test name
Test status
Simulation time	6362882238 ps
CPU time	1501.86 seconds
Started	Jun 09 03:28:18 PM PDT 24
Finished	Jun 09 03:53:20 PM PDT 24
Peak memory	608672 kb
Host	smart-113e177b-0996-47c2-bf4b-1f2783f77b77
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127183346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.127183346
Directory	/workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_kat.1581131732
Short name	T860
Test name
Test status
Simulation time	3142720052 ps
CPU time	653.58 seconds
Started	Jun 09 03:24:33 PM PDT 24
Finished	Jun 09 03:35:27 PM PDT 24
Peak memory	613188 kb
Host	smart-4faedd31-f381-41c6-a454-c138ac53b461
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581131732 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.1581131732
Directory	/workspace/1.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_sw_mode.1546536452
Short name	T687
Test name
Test status
Simulation time	5792034056 ps
CPU time	1611.54 seconds
Started	Jun 09 03:24:08 PM PDT 24
Finished	Jun 09 03:51:00 PM PDT 24
Peak memory	607016 kb
Host	smart-b0e98398-8f16-4df4-86cb-230c007272f7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546536452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1546536452
Directory	/workspace/1.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4240791539
Short name	T799
Test name
Test status
Simulation time	3205483288 ps
CPU time	281.55 seconds
Started	Jun 09 03:28:22 PM PDT 24
Finished	Jun 09 03:33:05 PM PDT 24
Peak memory	607364 kb
Host	smart-690eccea-ed65-451e-a1ac-17ea01faa89a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42 40791539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.4240791539
Directory	/workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2216438799
Short name	T712
Test name
Test status
Simulation time	2690097430 ps
CPU time	250.44 seconds
Started	Jun 09 03:23:16 PM PDT 24
Finished	Jun 09 03:27:28 PM PDT 24
Peak memory	606540 kb
Host	smart-df181acc-6a22-48b0-877c-30c7705761c4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216438799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2216438799
Directory	/workspace/1.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3111527021
Short name	T424
Test name
Test status
Simulation time	3568654160 ps
CPU time	680.06 seconds
Started	Jun 09 03:29:07 PM PDT 24
Finished	Jun 09 03:40:27 PM PDT 24
Peak memory	606024 kb
Host	smart-1b0eb1de-843d-47e2-a4ff-da441010bf32
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3111527021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.3111527021
Directory	/workspace/1.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_example_concurrency.1379000846
Short name	T887
Test name
Test status
Simulation time	2603995864 ps
CPU time	200.38 seconds
Started	Jun 09 03:17:46 PM PDT 24
Finished	Jun 09 03:21:07 PM PDT 24
Peak memory	606352 kb
Host	smart-bb988927-a2e7-4f48-8628-cea2944115ba
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379000846 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.1379000846
Directory	/workspace/1.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/1.chip_sw_example_flash.638197275
Short name	T536
Test name
Test status
Simulation time	2631198106 ps
CPU time	241.91 seconds
Started	Jun 09 03:17:18 PM PDT 24
Finished	Jun 09 03:21:20 PM PDT 24
Peak memory	607080 kb
Host	smart-1710a88e-e9c0-4a6b-93eb-8f3ff73728db
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638197275 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.638197275
Directory	/workspace/1.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/1.chip_sw_example_manufacturer.3519503926
Short name	T531
Test name
Test status
Simulation time	2376392004 ps
CPU time	149.66 seconds
Started	Jun 09 03:16:14 PM PDT 24
Finished	Jun 09 03:18:44 PM PDT 24
Peak memory	606384 kb
Host	smart-3b2fdcec-94c1-4f10-bc62-f958ffd5fded
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519503926 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.3519503926
Directory	/workspace/1.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/1.chip_sw_example_rom.2272734528
Short name	T329
Test name
Test status
Simulation time	2595045888 ps
CPU time	121.07 seconds
Started	Jun 09 03:15:08 PM PDT 24
Finished	Jun 09 03:17:10 PM PDT 24
Peak memory	606664 kb
Host	smart-c8e3042d-b7a0-43d0-8b03-5291a7cdcaee
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272734528 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.2272734528
Directory	/workspace/1.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2450038132
Short name	T180
Test name
Test status
Simulation time	58877513935 ps
CPU time	10689.7 seconds
Started	Jun 09 03:17:08 PM PDT 24
Finished	Jun 09 06:15:19 PM PDT 24
Peak memory	623384 kb
Host	smart-b94e8eb2-0e93-472f-b04b-9154384b4eaf
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2450038132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.2450038132
Directory	/workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_crash_alert.2560946172
Short name	T718
Test name
Test status
Simulation time	4676737520 ps
CPU time	595.08 seconds
Started	Jun 09 03:27:42 PM PDT 24
Finished	Jun 09 03:37:38 PM PDT 24
Peak memory	608376 kb
Host	smart-c8d1ce6e-f8f2-40e2-9c40-b352ae45ec0b
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2560946172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2560946172
Directory	/workspace/1.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1314209491
Short name	T580
Test name
Test status
Simulation time	5997990784 ps
CPU time	1171.22 seconds
Started	Jun 09 03:19:24 PM PDT 24
Finished	Jun 09 03:38:56 PM PDT 24
Peak memory	606736 kb
Host	smart-27a811d2-c304-4f43-ac1c-d546e3ad4c11
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314209491 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.1314209491
Directory	/workspace/1.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1721916053
Short name	T405
Test name
Test status
Simulation time	6268925817 ps
CPU time	1291.25 seconds
Started	Jun 09 03:19:42 PM PDT 24
Finished	Jun 09 03:41:14 PM PDT 24
Peak memory	606812 kb
Host	smart-2ca844d8-cb01-4062-b580-a7a271133c48
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721916053 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1721916053
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.992890421
Short name	T809
Test name
Test status
Simulation time	7353164468 ps
CPU time	1166.92 seconds
Started	Jun 09 03:26:43 PM PDT 24
Finished	Jun 09 03:46:10 PM PDT 24
Peak memory	606672 kb
Host	smart-dd0585db-9008-4267-ae16-3a54bdf1568f
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992890421 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.992890421
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.553512295
Short name	T624
Test name
Test status
Simulation time	5406021166 ps
CPU time	1112.46 seconds
Started	Jun 09 03:19:06 PM PDT 24
Finished	Jun 09 03:37:39 PM PDT 24
Peak memory	607448 kb
Host	smart-008db488-8a91-48f2-a827-99a030b6a875
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553512295 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.553512295
Directory	/workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.981214762
Short name	T686
Test name
Test status
Simulation time	3340831636 ps
CPU time	252.06 seconds
Started	Jun 09 03:19:05 PM PDT 24
Finished	Jun 09 03:23:18 PM PDT 24
Peak memory	606388 kb
Host	smart-499f52c6-34c2-4652-9b84-29e20f3cb1f2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981214762 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.981214762
Directory	/workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1368094254
Short name	T950
Test name
Test status
Simulation time	5921324868 ps
CPU time	483.09 seconds
Started	Jun 09 03:19:11 PM PDT 24
Finished	Jun 09 03:27:14 PM PDT 24
Peak memory	608532 kb
Host	smart-e3cfc2e9-8e95-41c3-9cea-f831aa2953ee
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13 68094254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1368094254
Directory	/workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2835778916
Short name	T462
Test name
Test status
Simulation time	5037769248 ps
CPU time	1482.23 seconds
Started	Jun 09 03:27:45 PM PDT 24
Finished	Jun 09 03:52:27 PM PDT 24
Peak memory	606712 kb
Host	smart-53727152-7966-4d29-a977-b0c4775ebb60
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835778916 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2835778916
Directory	/workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.351514483
Short name	T847
Test name
Test status
Simulation time	3825039286 ps
CPU time	639.26 seconds
Started	Jun 09 03:20:02 PM PDT 24
Finished	Jun 09 03:30:41 PM PDT 24
Peak memory	606708 kb
Host	smart-9d862b74-730c-44dc-bb5f-ccf6e8371b62
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351514483 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.351514483
Directory	/workspace/1.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2689247060
Short name	T239
Test name
Test status
Simulation time	3843378901 ps
CPU time	826.03 seconds
Started	Jun 09 03:19:14 PM PDT 24
Finished	Jun 09 03:33:00 PM PDT 24
Peak memory	606608 kb
Host	smart-d3f2523c-2d4b-4053-bd9f-c31ae38ac349
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2689247060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.2689247060
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.297443078
Short name	T363
Test name
Test status
Simulation time	4853312896 ps
CPU time	609.92 seconds
Started	Jun 09 03:26:44 PM PDT 24
Finished	Jun 09 03:36:55 PM PDT 24
Peak memory	606816 kb
Host	smart-b689956b-3efa-412a-befe-115d70379b0b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=297443078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.297443078
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1536752792
Short name	T396
Test name
Test status
Simulation time	3071410664 ps
CPU time	341.3 seconds
Started	Jun 09 03:30:25 PM PDT 24
Finished	Jun 09 03:36:06 PM PDT 24
Peak memory	606328 kb
Host	smart-03278e78-aab6-4de1-aaa6-d2b8966d915d
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536752 792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.1536752792
Directory	/workspace/1.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_init.4207931967
Short name	T191
Test name
Test status
Simulation time	16422658275 ps
CPU time	2320.56 seconds
Started	Jun 09 03:18:21 PM PDT 24
Finished	Jun 09 03:57:03 PM PDT 24
Peak memory	610636 kb
Host	smart-1f2026f6-7ba9-4658-b2b3-7cc8a4108512
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207931967 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.4207931967
Directory	/workspace/1.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3236839099
Short name	T236
Test name
Test status
Simulation time	19831476059 ps
CPU time	1792.9 seconds
Started	Jun 09 03:26:37 PM PDT 24
Finished	Jun 09 03:56:31 PM PDT 24
Peak memory	611836 kb
Host	smart-11139b42-641b-4268-9999-90167532ad89
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3236839099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3236839099
Directory	/workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2833776009
Short name	T706
Test name
Test status
Simulation time	2888710668 ps
CPU time	202.31 seconds
Started	Jun 09 03:31:32 PM PDT 24
Finished	Jun 09 03:34:55 PM PDT 24
Peak memory	606900 kb
Host	smart-fccdf484-6ecf-42a8-8509-181c77ce3041
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2833776009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.2833776009
Directory	/workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_gpio.3426837645
Short name	T53
Test name
Test status
Simulation time	4118663940 ps
CPU time	547.49 seconds
Started	Jun 09 03:18:31 PM PDT 24
Finished	Jun 09 03:27:39 PM PDT 24
Peak memory	607060 kb
Host	smart-8f82d563-59fa-447c-8a5e-434a04bcd8fe
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426837645 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.3426837645
Directory	/workspace/1.chip_sw_gpio/latest

Test location	/workspace/coverage/default/1.chip_sw_gpio_smoketest.3533987647
Short name	T52
Test name
Test status
Simulation time	2885933957 ps
CPU time	403.22 seconds
Started	Jun 09 03:27:26 PM PDT 24
Finished	Jun 09 03:34:10 PM PDT 24
Peak memory	606472 kb
Host	smart-d004b24e-e205-4cdc-953c-56f7f72bd565
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533987647 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.3533987647
Directory	/workspace/1.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc.1557486200
Short name	T663
Test name
Test status
Simulation time	2848020548 ps
CPU time	252.37 seconds
Started	Jun 09 03:28:41 PM PDT 24
Finished	Jun 09 03:32:53 PM PDT 24
Peak memory	606500 kb
Host	smart-f56b2f78-6e16-4994-93e0-a99ae4b7caa7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557486200 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.1557486200
Directory	/workspace/1.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1264713697
Short name	T594
Test name
Test status
Simulation time	3628194148 ps
CPU time	373.19 seconds
Started	Jun 09 03:24:30 PM PDT 24
Finished	Jun 09 03:30:44 PM PDT 24
Peak memory	606360 kb
Host	smart-7bed1743-52b2-4daa-9bde-9334fb6d8abc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264713697 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1264713697
Directory	/workspace/1.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2534987874
Short name	T727
Test name
Test status
Simulation time	2881224921 ps
CPU time	255.6 seconds
Started	Jun 09 03:24:12 PM PDT 24
Finished	Jun 09 03:28:28 PM PDT 24
Peak memory	606440 kb
Host	smart-b0321977-76fd-4934-9e3a-bae2fc38a08d
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534987874 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.2534987874
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3465810268
Short name	T372
Test name
Test status
Simulation time	3034748423 ps
CPU time	274.14 seconds
Started	Jun 09 03:27:59 PM PDT 24
Finished	Jun 09 03:32:34 PM PDT 24
Peak memory	606148 kb
Host	smart-038d50d6-f98a-44b3-8a5f-f6f1ec91be69
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465810268 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.3465810268
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_multistream.3194924243
Short name	T746
Test name
Test status
Simulation time	6418165248 ps
CPU time	1712.12 seconds
Started	Jun 09 03:28:32 PM PDT 24
Finished	Jun 09 03:57:04 PM PDT 24
Peak memory	607348 kb
Host	smart-1338d634-ba13-43f5-87d1-06de55ab5135
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194924243 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.3194924243
Directory	/workspace/1.chip_sw_hmac_multistream/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_oneshot.886639366
Short name	T684
Test name
Test status
Simulation time	2759537108 ps
CPU time	294.51 seconds
Started	Jun 09 03:23:49 PM PDT 24
Finished	Jun 09 03:28:44 PM PDT 24
Peak memory	607136 kb
Host	smart-1742b5eb-974d-4504-a02a-ad7976084b3a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886639366 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.886639366
Directory	/workspace/1.chip_sw_hmac_oneshot/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_smoketest.3512203495
Short name	T833
Test name
Test status
Simulation time	3558298274 ps
CPU time	382.48 seconds
Started	Jun 09 03:28:55 PM PDT 24
Finished	Jun 09 03:35:18 PM PDT 24
Peak memory	606372 kb
Host	smart-e7a1fffd-13df-430b-afb8-f4fcabee8762
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512203495 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.3512203495
Directory	/workspace/1.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.562629667
Short name	T203
Test name
Test status
Simulation time	3348727266 ps
CPU time	520.74 seconds
Started	Jun 09 03:21:36 PM PDT 24
Finished	Jun 09 03:30:17 PM PDT 24
Peak memory	607268 kb
Host	smart-5f428734-6649-46c6-bfdf-4d0fd110ad15
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562629667 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.562629667
Directory	/workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2196636435
Short name	T206
Test name
Test status
Simulation time	4393484260 ps
CPU time	794.23 seconds
Started	Jun 09 03:19:10 PM PDT 24
Finished	Jun 09 03:32:25 PM PDT 24
Peak memory	606720 kb
Host	smart-e01e00aa-af72-4260-be2a-b7337aea7bac
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196636435 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.2196636435
Directory	/workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2516460650
Short name	T211
Test name
Test status
Simulation time	5997962744 ps
CPU time	978.57 seconds
Started	Jun 09 03:21:20 PM PDT 24
Finished	Jun 09 03:37:39 PM PDT 24
Peak memory	607732 kb
Host	smart-34d2fa34-cd14-4158-8ca3-ce372df73e25
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516460650 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.2516460650
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.908395197
Short name	T204
Test name
Test status
Simulation time	6507194440 ps
CPU time	1029.72 seconds
Started	Jun 09 03:18:48 PM PDT 24
Finished	Jun 09 03:35:58 PM PDT 24
Peak memory	607760 kb
Host	smart-2b3db30d-58fe-40d8-94b6-c3ee02acedfd
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908395197 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.908395197
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.4286656161
Short name	T373
Test name
Test status
Simulation time	63823499491 ps
CPU time	11687.7 seconds
Started	Jun 09 03:18:51 PM PDT 24
Finished	Jun 09 06:33:40 PM PDT 24
Peak memory	623904 kb
Host	smart-2c903652-a4d8-4111-a38f-0f7f5548dd8d
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4286656161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.4286656161
Directory	/workspace/1.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1275222512
Short name	T906
Test name
Test status
Simulation time	9260863800 ps
CPU time	1796.03 seconds
Started	Jun 09 03:25:07 PM PDT 24
Finished	Jun 09 03:55:04 PM PDT 24
Peak memory	614328 kb
Host	smart-fbcc641a-e3a7-41d6-b427-bd059c6a5aad
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275 222512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1275222512
Directory	/workspace/1.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3219239429
Short name	T956
Test name
Test status
Simulation time	12955268897 ps
CPU time	2475.57 seconds
Started	Jun 09 03:26:02 PM PDT 24
Finished	Jun 09 04:07:18 PM PDT 24
Peak memory	615320 kb
Host	smart-2f0066f1-810c-4134-abe7-81aa2675f400
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3219239429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.3219239429
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4200026453
Short name	T832
Test name
Test status
Simulation time	12873940188 ps
CPU time	2033.82 seconds
Started	Jun 09 03:26:14 PM PDT 24
Finished	Jun 09 04:00:08 PM PDT 24
Peak memory	614332 kb
Host	smart-8d4c6d83-d0d7-4724-805e-0f1da2a2b0ef
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4200026453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.4200026453
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.948545425
Short name	T810
Test name
Test status
Simulation time	10195860472 ps
CPU time	2104.21 seconds
Started	Jun 09 03:24:41 PM PDT 24
Finished	Jun 09 03:59:46 PM PDT 24
Peak memory	613952 kb
Host	smart-ddf0dbeb-41b0-44f0-8ed5-997d566c2993
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=948545425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.948545425
Directory	/workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1179775386
Short name	T326
Test name
Test status
Simulation time	9252447038 ps
CPU time	2464.21 seconds
Started	Jun 09 03:24:14 PM PDT 24
Finished	Jun 09 04:05:19 PM PDT 24
Peak memory	607440 kb
Host	smart-e3a09d75-9b6e-48e0-8b81-496085fbd0e8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117977 5386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.1179775386
Directory	/workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2196478154
Short name	T837
Test name
Test status
Simulation time	10953016096 ps
CPU time	2460.84 seconds
Started	Jun 09 03:25:31 PM PDT 24
Finished	Jun 09 04:06:32 PM PDT 24
Peak memory	608408 kb
Host	smart-e7f4072e-2187-4cea-98a6-4201e2ef228d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21964 78154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2196478154
Directory	/workspace/1.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1927534147
Short name	T325
Test name
Test status
Simulation time	17815975756 ps
CPU time	3672.61 seconds
Started	Jun 09 03:25:16 PM PDT 24
Finished	Jun 09 04:26:29 PM PDT 24
Peak memory	608400 kb
Host	smart-83b6fa64-b325-47d9-b136-a09d6751b911
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19275 34147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.1927534147
Directory	/workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_app_rom.1995403313
Short name	T85
Test name
Test status
Simulation time	3147917030 ps
CPU time	290.3 seconds
Started	Jun 09 03:26:20 PM PDT 24
Finished	Jun 09 03:31:11 PM PDT 24
Peak memory	606316 kb
Host	smart-42387373-2c52-4a03-aa8f-fa095756f9f9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995403313 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.1995403313
Directory	/workspace/1.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_entropy.2523643926
Short name	T295
Test name
Test status
Simulation time	2785394312 ps
CPU time	220.49 seconds
Started	Jun 09 03:19:38 PM PDT 24
Finished	Jun 09 03:23:19 PM PDT 24
Peak memory	607116 kb
Host	smart-371be090-b6a2-48c8-8a9b-6ef959067ed3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523643926 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2523643926
Directory	/workspace/1.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_idle.871037522
Short name	T699
Test name
Test status
Simulation time	2963673940 ps
CPU time	281.23 seconds
Started	Jun 09 03:24:29 PM PDT 24
Finished	Jun 09 03:29:11 PM PDT 24
Peak memory	606376 kb
Host	smart-2edfb4aa-6aa6-42e4-9863-ac64b089c05b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871037522 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_idle.871037522
Directory	/workspace/1.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3002639424
Short name	T842
Test name
Test status
Simulation time	2826330680 ps
CPU time	175.27 seconds
Started	Jun 09 03:23:52 PM PDT 24
Finished	Jun 09 03:26:48 PM PDT 24
Peak memory	606324 kb
Host	smart-7aa8cd27-c5fb-4ec5-b12f-0731c58090cd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002639424 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3002639424
Directory	/workspace/1.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1580264480
Short name	T653
Test name
Test status
Simulation time	2915337312 ps
CPU time	251.97 seconds
Started	Jun 09 03:23:53 PM PDT 24
Finished	Jun 09 03:28:06 PM PDT 24
Peak memory	606344 kb
Host	smart-46072a17-79fe-4c57-9222-b9b96feff67f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580264480 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1580264480
Directory	/workspace/1.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1870417560
Short name	T992
Test name
Test status
Simulation time	3093953802 ps
CPU time	279.69 seconds
Started	Jun 09 03:25:16 PM PDT 24
Finished	Jun 09 03:29:56 PM PDT 24
Peak memory	606308 kb
Host	smart-283bc722-e7e3-4002-839b-79113d37447a
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870417560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.1870417560
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_smoketest.3167377656
Short name	T579
Test name
Test status
Simulation time	3292369500 ps
CPU time	306.4 seconds
Started	Jun 09 03:28:03 PM PDT 24
Finished	Jun 09 03:33:10 PM PDT 24
Peak memory	607100 kb
Host	smart-28ecb709-e2c4-4769-ac9f-7d2df71301f0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167377656 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.3167377656
Directory	/workspace/1.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1473811552
Short name	T915
Test name
Test status
Simulation time	2888646600 ps
CPU time	283.01 seconds
Started	Jun 09 03:18:22 PM PDT 24
Finished	Jun 09 03:23:05 PM PDT 24
Peak memory	606372 kb
Host	smart-a4ef625e-f1c1-4174-9c53-78a9b646ed08
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473811552 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.1473811552
Directory	/workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1153218360
Short name	T433
Test name
Test status
Simulation time	2955025087 ps
CPU time	192.92 seconds
Started	Jun 09 03:19:27 PM PDT 24
Finished	Jun 09 03:22:40 PM PDT 24
Peak memory	616676 kb
Host	smart-f8bd6b45-156e-408b-be7f-af32eb371239
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11532183 60 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.1153218360
Directory	/workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.406522652
Short name	T829
Test name
Test status
Simulation time	11854342719 ps
CPU time	1234.13 seconds
Started	Jun 09 03:20:40 PM PDT 24
Finished	Jun 09 03:41:15 PM PDT 24
Peak memory	617884 kb
Host	smart-5ea8408b-485e-4e2e-b736-cc6abd917897
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406522652 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.406522652
Directory	/workspace/1.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3281220000
Short name	T301
Test name
Test status
Simulation time	2245706497 ps
CPU time	97.25 seconds
Started	Jun 09 03:21:45 PM PDT 24
Finished	Jun 09 03:23:22 PM PDT 24
Peak memory	613176 kb
Host	smart-3f615dcd-cb3d-47ad-8772-cdde0c8ee801
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3281220000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.3281220000
Directory	/workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2530632159
Short name	T873
Test name
Test status
Simulation time	2812693274 ps
CPU time	131.78 seconds
Started	Jun 09 03:21:18 PM PDT 24
Finished	Jun 09 03:23:30 PM PDT 24
Peak memory	614572 kb
Host	smart-768ec84b-5ba5-4b53-b498-52d0f6c9276f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530632159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2530632159
Directory	/workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2588247905
Short name	T232
Test name
Test status
Simulation time	50008803417 ps
CPU time	6106.26 seconds
Started	Jun 09 03:20:23 PM PDT 24
Finished	Jun 09 05:02:10 PM PDT 24
Peak memory	618320 kb
Host	smart-c7735473-88dd-41b2-afcb-18a999179f25
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588247905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.2588247905
Directory	/workspace/1.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3441531355
Short name	T941
Test name
Test status
Simulation time	51932823355 ps
CPU time	5852.75 seconds
Started	Jun 09 03:21:15 PM PDT 24
Finished	Jun 09 04:58:49 PM PDT 24
Peak memory	616900 kb
Host	smart-f18946f4-b5b6-4583-ad25-65270711994d
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441531355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.3441531355
Directory	/workspace/1.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1709278023
Short name	T919
Test name
Test status
Simulation time	10047048960 ps
CPU time	969.51 seconds
Started	Jun 09 03:21:41 PM PDT 24
Finished	Jun 09 03:37:51 PM PDT 24
Peak memory	616340 kb
Host	smart-0007efaa-6f59-4d17-ae61-ec02d6da7d35
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709278023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1709278023
Directory	/workspace/1.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4220786506
Short name	T998
Test name
Test status
Simulation time	45327426904 ps
CPU time	4844.7 seconds
Started	Jun 09 03:20:58 PM PDT 24
Finished	Jun 09 04:41:44 PM PDT 24
Peak memory	613820 kb
Host	smart-364e8c23-22a2-4370-85d3-727f14a37b89
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220786506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.4220786506
Directory	/workspace/1.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3929122010
Short name	T192
Test name
Test status
Simulation time	23356843568 ps
CPU time	2094.48 seconds
Started	Jun 09 03:20:42 PM PDT 24
Finished	Jun 09 03:55:37 PM PDT 24
Peak memory	614656 kb
Host	smart-f31e2e3a-5f6a-47f5-848b-a3f14f18fd20
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3929122010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.3929122010
Directory	/workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.922910976
Short name	T762
Test name
Test status
Simulation time	17012422960 ps
CPU time	3587.73 seconds
Started	Jun 09 03:22:45 PM PDT 24
Finished	Jun 09 04:22:34 PM PDT 24
Peak memory	608072 kb
Host	smart-c421128a-7dfd-4a56-a642-cf8673099fd6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=922910976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.922910976
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4261997111
Short name	T900
Test name
Test status
Simulation time	18081094169 ps
CPU time	3763.52 seconds
Started	Jun 09 03:22:38 PM PDT 24
Finished	Jun 09 04:25:22 PM PDT 24
Peak memory	607032 kb
Host	smart-130426cd-9c08-4772-afd8-87de7b9d7275
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4261997111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4261997111
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2835912755
Short name	T678
Test name
Test status
Simulation time	24764995185 ps
CPU time	3951.41 seconds
Started	Jun 09 03:26:27 PM PDT 24
Finished	Jun 09 04:32:18 PM PDT 24
Peak memory	607628 kb
Host	smart-44d021a4-7fa6-4fa4-a8c1-f0778dd9e3a3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835912755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2835912755
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.4268819999
Short name	T970
Test name
Test status
Simulation time	4140182306 ps
CPU time	559.04 seconds
Started	Jun 09 03:23:00 PM PDT 24
Finished	Jun 09 03:32:20 PM PDT 24
Peak memory	607696 kb
Host	smart-b6b14a58-0475-43a6-8fd1-9e86b2f5145d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268819999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.4268819999
Directory	/workspace/1.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_randomness.495032760
Short name	T355
Test name
Test status
Simulation time	6735333770 ps
CPU time	733.2 seconds
Started	Jun 09 03:21:31 PM PDT 24
Finished	Jun 09 03:33:45 PM PDT 24
Peak memory	607328 kb
Host	smart-342a8648-5705-4c21-890c-22ff79e860f8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=495032760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.495032760
Directory	/workspace/1.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_smoketest.4154405821
Short name	T179
Test name
Test status
Simulation time	5029537000 ps
CPU time	1062.7 seconds
Started	Jun 09 03:31:36 PM PDT 24
Finished	Jun 09 03:49:19 PM PDT 24
Peak memory	606860 kb
Host	smart-032e3628-b2e8-435c-bedb-f928fe4c099d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154405821 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.4154405821
Directory	/workspace/1.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.738396192
Short name	T603
Test name
Test status
Simulation time	3034676512 ps
CPU time	213.49 seconds
Started	Jun 09 03:18:56 PM PDT 24
Finished	Jun 09 03:22:30 PM PDT 24
Peak memory	607396 kb
Host	smart-988609b0-be04-4e5b-b0bf-d12d560ba645
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738396192 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.738396192
Directory	/workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1850431422
Short name	T904
Test name
Test status
Simulation time	8010607260 ps
CPU time	1105.45 seconds
Started	Jun 09 03:18:15 PM PDT 24
Finished	Jun 09 03:36:41 PM PDT 24
Peak memory	608116 kb
Host	smart-8549581e-928e-4597-a58c-44507395e35f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1850431422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.1850431422
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3947893103
Short name	T189
Test name
Test status
Simulation time	8836613018 ps
CPU time	1463.13 seconds
Started	Jun 09 03:20:04 PM PDT 24
Finished	Jun 09 03:44:27 PM PDT 24
Peak memory	607132 kb
Host	smart-8fbcc870-a86a-4105-8418-c8f0921dd55a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3947893103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3947893103
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3362186685
Short name	T299
Test name
Test status
Simulation time	7689585890 ps
CPU time	1109.13 seconds
Started	Jun 09 03:19:34 PM PDT 24
Finished	Jun 09 03:38:04 PM PDT 24
Peak memory	607128 kb
Host	smart-b2194daa-dd13-4fc2-8524-cd5de7411a3d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3362186685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3362186685
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1857979082
Short name	T689
Test name
Test status
Simulation time	3918650220 ps
CPU time	673.26 seconds
Started	Jun 09 03:20:49 PM PDT 24
Finished	Jun 09 03:32:03 PM PDT 24
Peak memory	606148 kb
Host	smart-a5b54183-e519-4e1a-bc7e-015b8d6b2b13
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1857979082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1857979082
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1174236059
Short name	T872
Test name
Test status
Simulation time	2603556504 ps
CPU time	242.48 seconds
Started	Jun 09 03:31:45 PM PDT 24
Finished	Jun 09 03:35:48 PM PDT 24
Peak memory	606316 kb
Host	smart-4a4fd417-966a-46b8-af08-3e2c4afd83f9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174236059 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.1174236059
Directory	/workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pattgen_ios.703809429
Short name	T318
Test name
Test status
Simulation time	2331570420 ps
CPU time	249.6 seconds
Started	Jun 09 03:17:09 PM PDT 24
Finished	Jun 09 03:21:20 PM PDT 24
Peak memory	608508 kb
Host	smart-242cfb74-91ab-472c-b308-d7a50ce18dd8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703809429 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.703809429
Directory	/workspace/1.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/1.chip_sw_plic_sw_irq.4055316421
Short name	T256
Test name
Test status
Simulation time	3182579192 ps
CPU time	253.5 seconds
Started	Jun 09 03:26:11 PM PDT 24
Finished	Jun 09 03:30:25 PM PDT 24
Peak memory	606356 kb
Host	smart-b8fff95e-32bc-4e7b-98ed-83189b168213
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055316421 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.4055316421
Directory	/workspace/1.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_power_idle_load.1780645021
Short name	T167
Test name
Test status
Simulation time	4925359400 ps
CPU time	721.91 seconds
Started	Jun 09 03:27:51 PM PDT 24
Finished	Jun 09 03:39:53 PM PDT 24
Peak memory	607948 kb
Host	smart-0cfa45ca-ee91-4198-b1d1-cca463d4a9fc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780645021 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.1780645021
Directory	/workspace/1.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/1.chip_sw_power_sleep_load.769620302
Short name	T332
Test name
Test status
Simulation time	10150268200 ps
CPU time	617.54 seconds
Started	Jun 09 03:27:09 PM PDT 24
Finished	Jun 09 03:37:27 PM PDT 24
Peak memory	608508 kb
Host	smart-c45d72cc-8b68-4722-bef8-1a479dd5db66
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769620302 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.769620302
Directory	/workspace/1.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.535838386
Short name	T691
Test name
Test status
Simulation time	9348235470 ps
CPU time	1329.39 seconds
Started	Jun 09 03:20:42 PM PDT 24
Finished	Jun 09 03:42:52 PM PDT 24
Peak memory	608624 kb
Host	smart-2c72fdec-22b3-4479-8e8c-73a12ee8a9e1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5358 38386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.535838386
Directory	/workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1173468312
Short name	T294
Test name
Test status
Simulation time	26419210081 ps
CPU time	2704.76 seconds
Started	Jun 09 03:26:00 PM PDT 24
Finished	Jun 09 04:11:06 PM PDT 24
Peak memory	608276 kb
Host	smart-45f7cc14-0a6e-4a9f-b9c1-1805e3e28e50
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117 3468312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1173468312
Directory	/workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1208822409
Short name	T591
Test name
Test status
Simulation time	15298540412 ps
CPU time	1864.25 seconds
Started	Jun 09 03:20:14 PM PDT 24
Finished	Jun 09 03:51:19 PM PDT 24
Peak memory	608980 kb
Host	smart-1d17677e-ae55-44de-950c-1d2046077e4d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1208822409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1208822409
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1230311841
Short name	T7
Test name
Test status
Simulation time	24124752516 ps
CPU time	2157.39 seconds
Started	Jun 09 03:26:05 PM PDT 24
Finished	Jun 09 04:02:03 PM PDT 24
Peak memory	608212 kb
Host	smart-10b4bfc6-abed-4d56-ae9d-f8cf6952aa26
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1230311841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1230311841
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3808757522
Short name	T844
Test name
Test status
Simulation time	11040309880 ps
CPU time	938.61 seconds
Started	Jun 09 03:22:28 PM PDT 24
Finished	Jun 09 03:38:07 PM PDT 24
Peak memory	607356 kb
Host	smart-416b9013-eb6f-4c67-98dd-bcc3acda7b6e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808757522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.3808757522
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3302068831
Short name	T737
Test name
Test status
Simulation time	5705645106 ps
CPU time	546.05 seconds
Started	Jun 09 03:23:58 PM PDT 24
Finished	Jun 09 03:33:05 PM PDT 24
Peak memory	613728 kb
Host	smart-fd434764-3f27-43af-bacc-8c6e43d5b999
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3302068831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3302068831
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3891567695
Short name	T977
Test name
Test status
Simulation time	9558207481 ps
CPU time	578.1 seconds
Started	Jun 09 03:21:44 PM PDT 24
Finished	Jun 09 03:31:23 PM PDT 24
Peak memory	607480 kb
Host	smart-55474f61-4911-412e-a0d8-c0365e4a5e4e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891567695 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.3891567695
Directory	/workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3216921380
Short name	T357
Test name
Test status
Simulation time	3628448528 ps
CPU time	587.02 seconds
Started	Jun 09 03:25:20 PM PDT 24
Finished	Jun 09 03:35:07 PM PDT 24
Peak memory	606348 kb
Host	smart-a6758d35-87e0-47a4-8d12-8ad4ceaf9580
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216921380 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.3216921380
Directory	/workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1305464316
Short name	T960
Test name
Test status
Simulation time	3290840280 ps
CPU time	347.94 seconds
Started	Jun 09 03:20:00 PM PDT 24
Finished	Jun 09 03:25:48 PM PDT 24
Peak memory	613348 kb
Host	smart-1b4d7a45-f805-45d5-991b-1340e47ae515
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1305464316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.1305464316
Directory	/workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3104055159
Short name	T667
Test name
Test status
Simulation time	12644709950 ps
CPU time	1500.54 seconds
Started	Jun 09 03:24:05 PM PDT 24
Finished	Jun 09 03:49:06 PM PDT 24
Peak memory	609020 kb
Host	smart-094a36c3-3b46-49d8-9d76-458ae4d7f582
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104055159 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3104055159
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2547116373
Short name	T616
Test name
Test status
Simulation time	6983073800 ps
CPU time	529.52 seconds
Started	Jun 09 03:20:10 PM PDT 24
Finished	Jun 09 03:29:00 PM PDT 24
Peak memory	607324 kb
Host	smart-8b378b8d-2663-422e-bc3e-f384cf2caf0e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547116373 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.2547116373
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3345645897
Short name	T988
Test name
Test status
Simulation time	28736602751 ps
CPU time	2920.52 seconds
Started	Jun 09 03:23:49 PM PDT 24
Finished	Jun 09 04:12:30 PM PDT 24
Peak memory	608704 kb
Host	smart-fba8c401-91ae-48b3-991b-04fd246964fd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3345645897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3345645897
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3721981682
Short name	T683
Test name
Test status
Simulation time	32419013832 ps
CPU time	2665.91 seconds
Started	Jun 09 03:20:29 PM PDT 24
Finished	Jun 09 04:04:56 PM PDT 24
Peak memory	607728 kb
Host	smart-c657512d-e246-47a0-a939-63de4a1f3ed4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721981682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.3721981682
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.922686751
Short name	T378
Test name
Test status
Simulation time	5924718120 ps
CPU time	476.12 seconds
Started	Jun 09 03:26:26 PM PDT 24
Finished	Jun 09 03:34:23 PM PDT 24
Peak memory	608188 kb
Host	smart-777e6183-2923-41da-afd0-4716b045f53b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=922686751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.922686751
Directory	/workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4232270305
Short name	T376
Test name
Test status
Simulation time	2687509864 ps
CPU time	207.52 seconds
Started	Jun 09 03:20:11 PM PDT 24
Finished	Jun 09 03:23:38 PM PDT 24
Peak memory	606368 kb
Host	smart-c9a97af5-5c7a-4c7e-abd6-a4c2d255a809
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232270305 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.4232270305
Directory	/workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3169632334
Short name	T645
Test name
Test status
Simulation time	5909205608 ps
CPU time	428.39 seconds
Started	Jun 09 03:22:25 PM PDT 24
Finished	Jun 09 03:29:35 PM PDT 24
Peak memory	613872 kb
Host	smart-d32b9b04-451d-42c1-8d53-4bef8f9edade
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3169632334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.3169632334
Directory	/workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3725786360
Short name	T156
Test name
Test status
Simulation time	5034121916 ps
CPU time	483.83 seconds
Started	Jun 09 03:24:22 PM PDT 24
Finished	Jun 09 03:32:27 PM PDT 24
Peak memory	606744 kb
Host	smart-6778185c-a9f7-4830-bc5a-ce853721220a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37257863 60 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3725786360
Directory	/workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.950685561
Short name	T845
Test name
Test status
Simulation time	6442361704 ps
CPU time	532.37 seconds
Started	Jun 09 03:26:06 PM PDT 24
Finished	Jun 09 03:34:59 PM PDT 24
Peak memory	608140 kb
Host	smart-062cf3d5-16d0-4a2b-a54c-ae31d93cadb0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=950685561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.950685561
Directory	/workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.4239010649
Short name	T702
Test name
Test status
Simulation time	6472081112 ps
CPU time	535.22 seconds
Started	Jun 09 03:29:06 PM PDT 24
Finished	Jun 09 03:38:01 PM PDT 24
Peak memory	607744 kb
Host	smart-d3a5d1eb-da6c-488a-a0b1-648a1f179712
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239010649 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.4239010649
Directory	/workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.640171000
Short name	T781
Test name
Test status
Simulation time	5083709200 ps
CPU time	870.43 seconds
Started	Jun 09 03:20:29 PM PDT 24
Finished	Jun 09 03:35:00 PM PDT 24
Peak memory	607108 kb
Host	smart-6d7ce228-d588-480b-b178-3441f9eecef3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640171000 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.640171000
Directory	/workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1953819183
Short name	T573
Test name
Test status
Simulation time	5044993856 ps
CPU time	572.83 seconds
Started	Jun 09 03:21:11 PM PDT 24
Finished	Jun 09 03:30:44 PM PDT 24
Peak memory	608036 kb
Host	smart-65875c21-dc73-44d2-8345-8b7a22faa87a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953819183 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1953819183
Directory	/workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1620901552
Short name	T44
Test name
Test status
Simulation time	4781028346 ps
CPU time	411.52 seconds
Started	Jun 09 03:28:57 PM PDT 24
Finished	Jun 09 03:35:49 PM PDT 24
Peak memory	607044 kb
Host	smart-bec6576e-c1e9-4d5b-b2d4-929752cb49f1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620901552 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.1620901552
Directory	/workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1086622051
Short name	T556
Test name
Test status
Simulation time	5510622464 ps
CPU time	649.48 seconds
Started	Jun 09 03:22:15 PM PDT 24
Finished	Jun 09 03:33:05 PM PDT 24
Peak memory	607216 kb
Host	smart-0133e5f0-b1e3-44cb-bfaf-bf53158d6448
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108 6622051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1086622051
Directory	/workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1349695727
Short name	T84
Test name
Test status
Simulation time	9853255041 ps
CPU time	674.86 seconds
Started	Jun 09 03:24:49 PM PDT 24
Finished	Jun 09 03:36:04 PM PDT 24
Peak memory	614188 kb
Host	smart-4f38eb65-9b1a-4b03-8ee0-6894d22486b9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349695727 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1349695727
Directory	/workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.477577754
Short name	T245
Test name
Test status
Simulation time	11988234170 ps
CPU time	1746.92 seconds
Started	Jun 09 03:20:42 PM PDT 24
Finished	Jun 09 03:49:49 PM PDT 24
Peak memory	608692 kb
Host	smart-8c4209e1-2dbb-4481-90c0-34c58bfa6479
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=477577754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.477577754
Directory	/workspace/1.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1997368490
Short name	T243
Test name
Test status
Simulation time	5678842140 ps
CPU time	786.4 seconds
Started	Jun 09 03:21:41 PM PDT 24
Finished	Jun 09 03:34:48 PM PDT 24
Peak memory	608344 kb
Host	smart-91b670f7-5ded-42de-8d33-499076eae17e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997368490 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.1997368490
Directory	/workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1068260634
Short name	T907
Test name
Test status
Simulation time	4347455550 ps
CPU time	735.37 seconds
Started	Jun 09 03:18:17 PM PDT 24
Finished	Jun 09 03:30:33 PM PDT 24
Peak memory	639056 kb
Host	smart-5335dc48-1ccd-4135-b424-8c8e4a3bb1cf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1068260634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1068260634
Directory	/workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.447112070
Short name	T529
Test name
Test status
Simulation time	2748457316 ps
CPU time	231.14 seconds
Started	Jun 09 03:28:29 PM PDT 24
Finished	Jun 09 03:32:21 PM PDT 24
Peak memory	606540 kb
Host	smart-da663932-c266-4dd4-8169-1a042eac5273
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447112070 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_rstmgr_smoketest.447112070
Directory	/workspace/1.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2015403779
Short name	T557
Test name
Test status
Simulation time	3863423292 ps
CPU time	332.9 seconds
Started	Jun 09 03:20:50 PM PDT 24
Finished	Jun 09 03:26:23 PM PDT 24
Peak memory	607372 kb
Host	smart-bc3a9b50-c19b-45b5-a9e1-248bcdfd21e0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015403779 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.2015403779
Directory	/workspace/1.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2275976561
Short name	T87
Test name
Test status
Simulation time	3032609000 ps
CPU time	279.98 seconds
Started	Jun 09 03:22:59 PM PDT 24
Finished	Jun 09 03:27:39 PM PDT 24
Peak memory	606336 kb
Host	smart-23b63a3a-4ed9-4325-9e74-3a5a8391d8d4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275976561 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2275976561
Directory	/workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2088392481
Short name	T297
Test name
Test status
Simulation time	3081545364 ps
CPU time	308.7 seconds
Started	Jun 09 03:26:42 PM PDT 24
Finished	Jun 09 03:31:51 PM PDT 24
Peak memory	606332 kb
Host	smart-f3b95704-0125-4afc-ad53-0a45006a35ce
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2088392481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.2088392481
Directory	/workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.618556569
Short name	T195
Test name
Test status
Simulation time	3020983763 ps
CPU time	243.72 seconds
Started	Jun 09 03:30:41 PM PDT 24
Finished	Jun 09 03:34:45 PM PDT 24
Peak memory	606676 kb
Host	smart-bc2ba659-5a96-4ad0-87ae-b463bc0eb233
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618556569 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.618556569
Directory	/workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3550757375
Short name	T387
Test name
Test status
Simulation time	2529867152 ps
CPU time	148.24 seconds
Started	Jun 09 03:26:05 PM PDT 24
Finished	Jun 09 03:28:34 PM PDT 24
Peak memory	635676 kb
Host	smart-52a0417a-4e26-4724-a3a6-0c01150fb3d6
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550757375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.3550757375
Directory	/workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2256297971
Short name	T312
Test name
Test status
Simulation time	5514490212 ps
CPU time	910.19 seconds
Started	Jun 09 03:22:21 PM PDT 24
Finished	Jun 09 03:37:32 PM PDT 24
Peak memory	606668 kb
Host	smart-044d9e3c-ff1c-43b3-88a9-a7b045599578
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22562 97971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2256297971
Directory	/workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4264748430
Short name	T662
Test name
Test status
Simulation time	5580736712 ps
CPU time	1195.36 seconds
Started	Jun 09 03:21:30 PM PDT 24
Finished	Jun 09 03:41:26 PM PDT 24
Peak memory	606940 kb
Host	smart-5d59bd73-2ecd-41fb-8b8d-d005cec86e2f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4264748430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.4264748430
Directory	/workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2113427712
Short name	T428
Test name
Test status
Simulation time	5941890031 ps
CPU time	596.73 seconds
Started	Jun 09 03:26:24 PM PDT 24
Finished	Jun 09 03:36:21 PM PDT 24
Peak memory	617876 kb
Host	smart-b9e6e072-2be2-465a-beed-f77ec318f356
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113427712 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.2113427712
Directory	/workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.284543567
Short name	T20
Test name
Test status
Simulation time	4532847106 ps
CPU time	539.7 seconds
Started	Jun 09 03:26:11 PM PDT 24
Finished	Jun 09 03:35:11 PM PDT 24
Peak memory	614648 kb
Host	smart-5db486a8-f537-447b-afa0-22b8d5e3c7ed
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284543 567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.284543567
Directory	/workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2103975367
Short name	T654
Test name
Test status
Simulation time	3094968960 ps
CPU time	252.17 seconds
Started	Jun 09 03:31:30 PM PDT 24
Finished	Jun 09 03:35:43 PM PDT 24
Peak memory	606324 kb
Host	smart-ca0b6976-86d8-435f-8832-5cb0f53921ad
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103975367 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.2103975367
Directory	/workspace/1.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_irq.2421016665
Short name	T259
Test name
Test status
Simulation time	2910264344 ps
CPU time	236.98 seconds
Started	Jun 09 03:21:15 PM PDT 24
Finished	Jun 09 03:25:12 PM PDT 24
Peak memory	607000 kb
Host	smart-cd96c5c4-e943-4859-bdc7-813f268f8c3e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421016665 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.2421016665
Directory	/workspace/1.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2942515044
Short name	T755
Test name
Test status
Simulation time	2921929896 ps
CPU time	261.87 seconds
Started	Jun 09 03:28:56 PM PDT 24
Finished	Jun 09 03:33:18 PM PDT 24
Peak memory	606360 kb
Host	smart-c325793d-e172-4869-8920-18acbce8092e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942515044 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2942515044
Directory	/workspace/1.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1439370016
Short name	T934
Test name
Test status
Simulation time	2347469618 ps
CPU time	267.43 seconds
Started	Jun 09 03:27:47 PM PDT 24
Finished	Jun 09 03:32:15 PM PDT 24
Peak memory	608396 kb
Host	smart-24a96ce5-dd3e-4fde-b9b3-b7d0ad83a3de
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439370 016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1439370016
Directory	/workspace/1.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1585006145
Short name	T808
Test name
Test status
Simulation time	9384947296 ps
CPU time	1543.4 seconds
Started	Jun 09 03:18:12 PM PDT 24
Finished	Jun 09 03:43:56 PM PDT 24
Peak memory	607328 kb
Host	smart-625db165-e783-40f0-8d61-9e1182db44a1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585006145 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1585006145
Directory	/workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1020821563
Short name	T540
Test name
Test status
Simulation time	7680894008 ps
CPU time	562.13 seconds
Started	Jun 09 03:24:26 PM PDT 24
Finished	Jun 09 03:33:48 PM PDT 24
Peak memory	608380 kb
Host	smart-3d021a8b-ea53-4241-b6a0-35342c861ce1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020821563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.1020821563
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1454128321
Short name	T748
Test name
Test status
Simulation time	8215040978 ps
CPU time	751.51 seconds
Started	Jun 09 03:24:37 PM PDT 24
Finished	Jun 09 03:37:09 PM PDT 24
Peak memory	608412 kb
Host	smart-98a1df0b-c2a6-4bd2-a29c-58b9b7372b13
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454128321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1454128321
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.2741701277
Short name	T214
Test name
Test status
Simulation time	7920305962 ps
CPU time	886.79 seconds
Started	Jun 09 03:18:22 PM PDT 24
Finished	Jun 09 03:33:09 PM PDT 24
Peak memory	623096 kb
Host	smart-fa4a60cc-9894-43fc-8c5f-02110802244d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741701277 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.2741701277
Directory	/workspace/1.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2769278183
Short name	T91
Test name
Test status
Simulation time	3841638594 ps
CPU time	559.13 seconds
Started	Jun 09 03:18:39 PM PDT 24
Finished	Jun 09 03:27:59 PM PDT 24
Peak memory	623004 kb
Host	smart-0c85dcd0-1f34-4cab-81bb-78e22d835aa1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769278183 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.2769278183
Directory	/workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_tpm.1776524253
Short name	T65
Test name
Test status
Simulation time	3987868690 ps
CPU time	379.06 seconds
Started	Jun 09 03:21:41 PM PDT 24
Finished	Jun 09 03:28:00 PM PDT 24
Peak memory	614784 kb
Host	smart-a2f8c6b5-8824-43ea-894e-611f9253c293
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776524253 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1776524253
Directory	/workspace/1.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2081014241
Short name	T116
Test name
Test status
Simulation time	8399914020 ps
CPU time	899.21 seconds
Started	Jun 09 03:24:28 PM PDT 24
Finished	Jun 09 03:39:28 PM PDT 24
Peak memory	607956 kb
Host	smart-7d1ffe49-034b-47fb-a20e-17efc4a23f55
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081014241 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.2081014241
Directory	/workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3234801199
Short name	T17
Test name
Test status
Simulation time	5348555950 ps
CPU time	800.25 seconds
Started	Jun 09 03:24:05 PM PDT 24
Finished	Jun 09 03:37:26 PM PDT 24
Peak memory	608360 kb
Host	smart-ab8efb5f-ae21-4b7c-a924-1df418e81e96
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234801199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.3234801199
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1909286334
Short name	T290
Test name
Test status
Simulation time	4609565333 ps
CPU time	788.56 seconds
Started	Jun 09 03:25:55 PM PDT 24
Finished	Jun 09 03:39:05 PM PDT 24
Peak memory	607556 kb
Host	smart-195e1f3b-2955-4b5e-b151-193f90540b71
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909286334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1909286334
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4099730650
Short name	T113
Test name
Test status
Simulation time	4481341535 ps
CPU time	545.96 seconds
Started	Jun 09 03:26:46 PM PDT 24
Finished	Jun 09 03:35:52 PM PDT 24
Peak memory	607532 kb
Host	smart-e40ecbba-52bd-49e1-b7a5-786fa9583870
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099730650 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4099730650
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3757013
Short name	T856
Test name
Test status
Simulation time	2294688200 ps
CPU time	246.6 seconds
Started	Jun 09 03:29:13 PM PDT 24
Finished	Jun 09 03:33:20 PM PDT 24
Peak memory	607252 kb
Host	smart-6b4320d4-aabd-47f2-8d91-59b30fbdf7eb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757013 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_sram_ctrl_smoketest.3757013
Directory	/workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3112282568
Short name	T967
Test name
Test status
Simulation time	20465225549 ps
CPU time	3732.15 seconds
Started	Jun 09 03:22:04 PM PDT 24
Finished	Jun 09 04:24:18 PM PDT 24
Peak memory	608024 kb
Host	smart-04952da7-f406-4a19-9197-70aaec35ed55
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112282568 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3112282568
Directory	/workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.4146944284
Short name	T228
Test name
Test status
Simulation time	4188134060 ps
CPU time	652.42 seconds
Started	Jun 09 03:21:41 PM PDT 24
Finished	Jun 09 03:32:35 PM PDT 24
Peak memory	610796 kb
Host	smart-ae52f010-f0f3-4f3f-8c75-420904af4ea6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146944284 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.4146944284
Directory	/workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.903226961
Short name	T224
Test name
Test status
Simulation time	2708522384 ps
CPU time	294.01 seconds
Started	Jun 09 03:23:21 PM PDT 24
Finished	Jun 09 03:28:17 PM PDT 24
Peak memory	610648 kb
Host	smart-0dcfb169-49bd-49ec-8449-dc9302102548
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903226961 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.903226961
Directory	/workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3541811495
Short name	T230
Test name
Test status
Simulation time	22653803580 ps
CPU time	2285.05 seconds
Started	Jun 09 03:21:57 PM PDT 24
Finished	Jun 09 04:00:03 PM PDT 24
Peak memory	611648 kb
Host	smart-660b9ca0-2544-4ab0-8527-9d98b8ff33b9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35418114 95 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.3541811495
Directory	/workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3518423677
Short name	T62
Test name
Test status
Simulation time	5660060040 ps
CPU time	423.08 seconds
Started	Jun 09 03:20:57 PM PDT 24
Finished	Jun 09 03:28:01 PM PDT 24
Peak memory	607388 kb
Host	smart-d93f88f8-9883-46ef-bd69-6ef920257e4e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518423677 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3518423677
Directory	/workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3710912799
Short name	T274
Test name
Test status
Simulation time	8740897904 ps
CPU time	1634.65 seconds
Started	Jun 09 03:17:37 PM PDT 24
Finished	Jun 09 03:44:52 PM PDT 24
Peak memory	617576 kb
Host	smart-2fb38f60-665d-484a-bc45-01be26961582
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3710912799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.3710912799
Directory	/workspace/1.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_smoketest.678415687
Short name	T571
Test name
Test status
Simulation time	2951668030 ps
CPU time	250.19 seconds
Started	Jun 09 03:30:41 PM PDT 24
Finished	Jun 09 03:34:52 PM PDT 24
Peak memory	607640 kb
Host	smart-1e44ca4f-0643-4198-9a12-fc00bc392a36
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678415687 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.678415687
Directory	/workspace/1.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx.3768718363
Short name	T284
Test name
Test status
Simulation time	4659491644 ps
CPU time	593.39 seconds
Started	Jun 09 03:17:33 PM PDT 24
Finished	Jun 09 03:27:27 PM PDT 24
Peak memory	623872 kb
Host	smart-bd0ae90f-423c-42e8-8259-528b7593a4e4
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768718363 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.3768718363
Directory	/workspace/1.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3961912588
Short name	T991
Test name
Test status
Simulation time	4611393073 ps
CPU time	597.88 seconds
Started	Jun 09 03:17:39 PM PDT 24
Finished	Jun 09 03:27:37 PM PDT 24
Peak memory	620356 kb
Host	smart-96b5084e-af90-4ba6-9219-42fd72f0e30f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961912588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.3961912588
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1484916244
Short name	T996
Test name
Test status
Simulation time	9368011799 ps
CPU time	1277.59 seconds
Started	Jun 09 03:18:50 PM PDT 24
Finished	Jun 09 03:40:08 PM PDT 24
Peak memory	619600 kb
Host	smart-2b2d58bc-2549-47af-8876-e9625c071efa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484916244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1484916244
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1309327575
Short name	T791
Test name
Test status
Simulation time	77782889229 ps
CPU time	13887.6 seconds
Started	Jun 09 03:17:26 PM PDT 24
Finished	Jun 09 07:08:55 PM PDT 24
Peak memory	634348 kb
Host	smart-487f5094-44c7-43cb-8c25-22585fc3e981
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1309327575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.1309327575
Directory	/workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2475155202
Short name	T754
Test name
Test status
Simulation time	3728406932 ps
CPU time	526.45 seconds
Started	Jun 09 03:19:20 PM PDT 24
Finished	Jun 09 03:28:07 PM PDT 24
Peak memory	615624 kb
Host	smart-4e49c89d-6dd2-4641-9a21-d4f4030b03e8
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475155202 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2475155202
Directory	/workspace/1.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.254462241
Short name	T891
Test name
Test status
Simulation time	4356894636 ps
CPU time	604.9 seconds
Started	Jun 09 03:20:21 PM PDT 24
Finished	Jun 09 03:30:26 PM PDT 24
Peak memory	615204 kb
Host	smart-841c15b7-cfce-4c41-9452-1c7e535e3104
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254462241 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.254462241
Directory	/workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_dev.3802637410
Short name	T817
Test name
Test status
Simulation time	10466228272 ps
CPU time	1098.5 seconds
Started	Jun 09 03:28:30 PM PDT 24
Finished	Jun 09 03:46:49 PM PDT 24
Peak memory	620044 kb
Host	smart-e446cdca-035e-474e-9cf6-f884762374ee
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3802637410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.3802637410
Directory	/workspace/1.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_prod.2990014576
Short name	T710
Test name
Test status
Simulation time	2387304787 ps
CPU time	163.74 seconds
Started	Jun 09 03:26:35 PM PDT 24
Finished	Jun 09 03:29:19 PM PDT 24
Peak memory	617772 kb
Host	smart-5beecbea-a390-4b87-911c-0f5f4b37ee58
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990014576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.2990014576
Directory	/workspace/1.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_rma.215533413
Short name	T122
Test name
Test status
Simulation time	5154554604 ps
CPU time	398.02 seconds
Started	Jun 09 03:24:45 PM PDT 24
Finished	Jun 09 03:31:24 PM PDT 24
Peak memory	620104 kb
Host	smart-808480ad-20fd-422d-b0c7-dfad42c7be9d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215533413 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.215533413
Directory	/workspace/1.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_dev.3441989970
Short name	T700
Test name
Test status
Simulation time	14920584759 ps
CPU time	4084.02 seconds
Started	Jun 09 03:33:03 PM PDT 24
Finished	Jun 09 04:41:08 PM PDT 24
Peak memory	606680 kb
Host	smart-d35a0f6e-40fc-46b5-bb20-df63aadee7bf
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441989970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.3441989970
Directory	/workspace/1.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_prod.3853504069
Short name	T692
Test name
Test status
Simulation time	14502878201 ps
CPU time	3434.8 seconds
Started	Jun 09 03:31:49 PM PDT 24
Finished	Jun 09 04:29:04 PM PDT 24
Peak memory	606688 kb
Host	smart-3f380596-e156-4519-8bd9-5551f9a2886e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853504069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.3853504069
Directory	/workspace/1.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2628248982
Short name	T674
Test name
Test status
Simulation time	14543469746 ps
CPU time	3478.68 seconds
Started	Jun 09 03:33:29 PM PDT 24
Finished	Jun 09 04:31:29 PM PDT 24
Peak memory	607108 kb
Host	smart-09f0053c-8ece-48a7-afc0-84305b71929d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628248982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.2628248982
Directory	/workspace/1.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_rma.3063373051
Short name	T867
Test name
Test status
Simulation time	14555357948 ps
CPU time	3536.2 seconds
Started	Jun 09 03:34:37 PM PDT 24
Finished	Jun 09 04:33:33 PM PDT 24
Peak memory	607148 kb
Host	smart-c8065a1e-0cf8-4d47-95a9-87ed7ce4695a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063373051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.3063373051
Directory	/workspace/1.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.147708181
Short name	T801
Test name
Test status
Simulation time	11057227586 ps
CPU time	3679.37 seconds
Started	Jun 09 03:33:18 PM PDT 24
Finished	Jun 09 04:34:37 PM PDT 24
Peak memory	607128 kb
Host	smart-3c82ef9d-b05d-467c-a59b-81cabc36f7db
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147708181 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.rom_e2e_asm_init_test_unlocked0.147708181
Directory	/workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.322515264
Short name	T623
Test name
Test status
Simulation time	14774193124 ps
CPU time	4276.91 seconds
Started	Jun 09 03:33:24 PM PDT 24
Finished	Jun 09 04:44:42 PM PDT 24
Peak memory	606760 kb
Host	smart-acffbe56-f1d7-47a7-8f33-eaa32b0ab1f8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322515264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.322515264
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2982579814
Short name	T760
Test name
Test status
Simulation time	15509159072 ps
CPU time	2943.84 seconds
Started	Jun 09 03:29:35 PM PDT 24
Finished	Jun 09 04:18:40 PM PDT 24
Peak memory	606988 kb
Host	smart-fd4c868b-7250-41d1-adb6-9689c883210f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982579814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.2982579814
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.469621679
Short name	T558
Test name
Test status
Simulation time	14602349480 ps
CPU time	3467.47 seconds
Started	Jun 09 03:32:11 PM PDT 24
Finished	Jun 09 04:29:59 PM PDT 24
Peak memory	607020 kb
Host	smart-438796d6-895a-4005-b5c2-a45d1684bd2c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469621679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_ no_meas.469621679
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3980537206
Short name	T742
Test name
Test status
Simulation time	13851504725 ps
CPU time	3916.91 seconds
Started	Jun 09 03:32:09 PM PDT 24
Finished	Jun 09 04:37:27 PM PDT 24
Peak memory	608112 kb
Host	smart-7411d9ba-2104-4aab-a2f8-711f8224a79e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980537206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.3980537206
Directory	/workspace/1.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/1.rom_e2e_shutdown_output.1906399176
Short name	T806
Test name
Test status
Simulation time	22043742968 ps
CPU time	2852.34 seconds
Started	Jun 09 03:31:42 PM PDT 24
Finished	Jun 09 04:19:16 PM PDT 24
Peak memory	607984 kb
Host	smart-215f74f7-f51b-4ce1-b008-0d17fe844c66
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906399176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.1906399176
Directory	/workspace/1.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/1.rom_e2e_smoke.1522831419
Short name	T5
Test name
Test status
Simulation time	14545538550 ps
CPU time	3691.68 seconds
Started	Jun 09 03:33:05 PM PDT 24
Finished	Jun 09 04:34:38 PM PDT 24
Peak memory	607072 kb
Host	smart-36ec4c87-63c5-4ac5-8e3d-80ea6d856541
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1522831419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.1522831419
Directory	/workspace/1.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/1.rom_e2e_static_critical.534473419
Short name	T913
Test name
Test status
Simulation time	16814950544 ps
CPU time	3638.68 seconds
Started	Jun 09 03:32:32 PM PDT 24
Finished	Jun 09 04:33:11 PM PDT 24
Peak memory	607068 kb
Host	smart-276f3a55-7084-4898-9b54-77e1818b17a8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534473419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.534473419
Directory	/workspace/1.rom_e2e_static_critical/latest

Test location	/workspace/coverage/default/1.rom_keymgr_functest.3800436678
Short name	T111
Test name
Test status
Simulation time	4909788830 ps
CPU time	462.66 seconds
Started	Jun 09 03:29:28 PM PDT 24
Finished	Jun 09 03:37:11 PM PDT 24
Peak memory	607200 kb
Host	smart-988da428-0c99-499e-b14c-c8cdc457bfaa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800436678 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.3800436678
Directory	/workspace/1.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/1.rom_volatile_raw_unlock.1533734009
Short name	T71
Test name
Test status
Simulation time	1956937077 ps
CPU time	123.93 seconds
Started	Jun 09 03:30:05 PM PDT 24
Finished	Jun 09 03:32:10 PM PDT 24
Peak memory	614632 kb
Host	smart-cf550cf3-2813-49ff-9e09-24a1c5cbe0b5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533734009 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.1533734009
Directory	/workspace/1.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3107001937
Short name	T735
Test name
Test status
Simulation time	12976322799 ps
CPU time	790.93 seconds
Started	Jun 09 03:41:16 PM PDT 24
Finished	Jun 09 03:54:27 PM PDT 24
Peak memory	617836 kb
Host	smart-23e8c940-77ce-4755-9f5a-62db652dd6fa
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107001937 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3107001937
Directory	/workspace/10.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3923820485
Short name	T43
Test name
Test status
Simulation time	4098997920 ps
CPU time	414.76 seconds
Started	Jun 09 03:45:24 PM PDT 24
Finished	Jun 09 03:52:19 PM PDT 24
Peak memory	617588 kb
Host	smart-a4803b97-49c4-4f69-8132-59ccf8189265
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3923820485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3923820485
Directory	/workspace/10.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2979156272
Short name	T117
Test name
Test status
Simulation time	10581242850 ps
CPU time	1096.35 seconds
Started	Jun 09 03:42:17 PM PDT 24
Finished	Jun 09 04:00:34 PM PDT 24
Peak memory	617976 kb
Host	smart-59d3da92-9489-4b9f-bd8b-662fd440e39e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979156272 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2979156272
Directory	/workspace/11.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1029654665
Short name	T321
Test name
Test status
Simulation time	4365235064 ps
CPU time	554.6 seconds
Started	Jun 09 03:44:15 PM PDT 24
Finished	Jun 09 03:53:30 PM PDT 24
Peak memory	617332 kb
Host	smart-d63322f1-a001-403d-ad67-8df68ba4da7a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1029654665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1029654665
Directory	/workspace/11.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1813051461
Short name	T721
Test name
Test status
Simulation time	6925819020 ps
CPU time	453.34 seconds
Started	Jun 09 03:41:47 PM PDT 24
Finished	Jun 09 03:49:20 PM PDT 24
Peak memory	617928 kb
Host	smart-34ed11f0-5545-46b4-8233-043ad6923d3f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813051461 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.1813051461
Directory	/workspace/12.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2019621925
Short name	T726
Test name
Test status
Simulation time	8169613864 ps
CPU time	1453.02 seconds
Started	Jun 09 03:41:04 PM PDT 24
Finished	Jun 09 04:05:18 PM PDT 24
Peak memory	617292 kb
Host	smart-6b93aa10-954f-4546-83ed-a61bc01c604d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2019621925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.2019621925
Directory	/workspace/12.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/13.chip_sw_all_escalation_resets.3610657916
Short name	T436
Test name
Test status
Simulation time	6270256212 ps
CPU time	659.01 seconds
Started	Jun 09 03:44:24 PM PDT 24
Finished	Jun 09 03:55:23 PM PDT 24
Peak memory	643104 kb
Host	smart-c16eb95c-2086-4376-947f-50f6189f0d6a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3610657916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3610657916
Directory	/workspace/13.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1403514937
Short name	T629
Test name
Test status
Simulation time	5065509617 ps
CPU time	486.46 seconds
Started	Jun 09 03:44:33 PM PDT 24
Finished	Jun 09 03:52:40 PM PDT 24
Peak memory	617984 kb
Host	smart-ec80fd46-4e18-4956-805c-db58317d19b7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403514937 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.1403514937
Directory	/workspace/13.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.950321184
Short name	T369
Test name
Test status
Simulation time	4440468252 ps
CPU time	733.47 seconds
Started	Jun 09 03:42:11 PM PDT 24
Finished	Jun 09 03:54:24 PM PDT 24
Peak memory	617476 kb
Host	smart-4f6f47ea-2871-40b9-8a18-849707d40cb8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=950321184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.950321184
Directory	/workspace/13.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3317455528
Short name	T510
Test name
Test status
Simulation time	5051839576 ps
CPU time	745.71 seconds
Started	Jun 09 03:42:39 PM PDT 24
Finished	Jun 09 03:55:05 PM PDT 24
Peak memory	647832 kb
Host	smart-7721458b-1713-441e-9ef5-8ddfea10df5c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3317455528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.3317455528
Directory	/workspace/14.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1961792655
Short name	T865
Test name
Test status
Simulation time	8796133681 ps
CPU time	1126.53 seconds
Started	Jun 09 03:41:56 PM PDT 24
Finished	Jun 09 04:00:43 PM PDT 24
Peak memory	617976 kb
Host	smart-3c5d7c3c-4674-47dd-b46d-bbed81f9c161
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961792655 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1961792655
Directory	/workspace/14.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2789183600
Short name	T658
Test name
Test status
Simulation time	4345511050 ps
CPU time	683 seconds
Started	Jun 09 03:41:36 PM PDT 24
Finished	Jun 09 03:52:59 PM PDT 24
Peak memory	617948 kb
Host	smart-ac91ac88-40da-4bbb-8592-3126f0e34261
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2789183600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2789183600
Directory	/workspace/14.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2148055211
Short name	T848
Test name
Test status
Simulation time	3968890480 ps
CPU time	734.91 seconds
Started	Jun 09 03:43:23 PM PDT 24
Finished	Jun 09 03:55:38 PM PDT 24
Peak memory	617276 kb
Host	smart-93a6e5b8-0fe0-4e10-9b7f-a6711eade921
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2148055211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.2148055211
Directory	/workspace/15.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3158948257
Short name	T134
Test name
Test status
Simulation time	3920838840 ps
CPU time	414.1 seconds
Started	Jun 09 03:43:28 PM PDT 24
Finished	Jun 09 03:50:23 PM PDT 24
Peak memory	647052 kb
Host	smart-aa8b7168-3cc7-433d-b1dd-bd03dd1bfe63
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158948257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3158948257
Directory	/workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/16.chip_sw_all_escalation_resets.213470913
Short name	T769
Test name
Test status
Simulation time	4902308130 ps
CPU time	525.91 seconds
Started	Jun 09 03:42:39 PM PDT 24
Finished	Jun 09 03:51:25 PM PDT 24
Peak memory	614832 kb
Host	smart-c71036f2-9377-4475-9b27-82c5b1a96462
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 213470913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.213470913
Directory	/workspace/16.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.750945750
Short name	T543
Test name
Test status
Simulation time	9253517174 ps
CPU time	1456.4 seconds
Started	Jun 09 03:42:50 PM PDT 24
Finished	Jun 09 04:07:07 PM PDT 24
Peak memory	618284 kb
Host	smart-fc3f2992-e151-4f5d-b311-06260daab4cd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=750945750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.750945750
Directory	/workspace/16.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/17.chip_sw_all_escalation_resets.998421207
Short name	T443
Test name
Test status
Simulation time	5518380872 ps
CPU time	651.01 seconds
Started	Jun 09 03:42:35 PM PDT 24
Finished	Jun 09 03:53:26 PM PDT 24
Peak memory	647792 kb
Host	smart-f4f6be79-c909-4bf1-9d22-88d5491c1813
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 998421207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.998421207
Directory	/workspace/17.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1906981155
Short name	T649
Test name
Test status
Simulation time	3799932824 ps
CPU time	631.19 seconds
Started	Jun 09 03:43:18 PM PDT 24
Finished	Jun 09 03:53:50 PM PDT 24
Peak memory	617256 kb
Host	smart-eeac55cb-3bd0-4818-a7f5-040cbd96ff34
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1906981155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1906981155
Directory	/workspace/17.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4105281175
Short name	T317
Test name
Test status
Simulation time	12749208980 ps
CPU time	2093.9 seconds
Started	Jun 09 03:44:04 PM PDT 24
Finished	Jun 09 04:18:58 PM PDT 24
Peak memory	618012 kb
Host	smart-2ecbbdd2-6079-4823-85c4-4b18cf37897e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4105281175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.4105281175
Directory	/workspace/18.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.574064122
Short name	T926
Test name
Test status
Simulation time	9479478346 ps
CPU time	1571.82 seconds
Started	Jun 09 03:44:19 PM PDT 24
Finished	Jun 09 04:10:31 PM PDT 24
Peak memory	617580 kb
Host	smart-44c5f5df-fc4f-45db-bb5b-9425da9ce39a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=574064122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.574064122
Directory	/workspace/19.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_jtag_mem_access.2700917899
Short name	T231
Test name
Test status
Simulation time	14475114343 ps
CPU time	1621.91 seconds
Started	Jun 09 03:28:33 PM PDT 24
Finished	Jun 09 03:55:35 PM PDT 24
Peak memory	606420 kb
Host	smart-e365379c-9b56-498f-b106-fe734756bc01
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700917899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.2 700917899
Directory	/workspace/2.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3010800812
Short name	T9
Test name
Test status
Simulation time	3848942204 ps
CPU time	591.24 seconds
Started	Jun 09 03:37:57 PM PDT 24
Finished	Jun 09 03:47:49 PM PDT 24
Peak memory	616428 kb
Host	smart-ef486140-6ed5-4736-809a-6cd0dcf019cb
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 010800812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3010800812
Directory	/workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/2.chip_sival_flash_info_access.3687942792
Short name	T773
Test name
Test status
Simulation time	3005328000 ps
CPU time	417.95 seconds
Started	Jun 09 03:29:31 PM PDT 24
Finished	Jun 09 03:36:29 PM PDT 24
Peak memory	606392 kb
Host	smart-cb61bada-bf4e-4f26-8610-99275cd3ad77
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3687942792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3687942792
Directory	/workspace/2.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3324233417
Short name	T335
Test name
Test status
Simulation time	18525379076 ps
CPU time	429.57 seconds
Started	Jun 09 03:32:38 PM PDT 24
Finished	Jun 09 03:39:49 PM PDT 24
Peak memory	614592 kb
Host	smart-4948e4b9-504a-4241-8299-b6016f46f1cc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3324233417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3324233417
Directory	/workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc.3905279228
Short name	T648
Test name
Test status
Simulation time	2689511092 ps
CPU time	232.43 seconds
Started	Jun 09 03:32:49 PM PDT 24
Finished	Jun 09 03:36:41 PM PDT 24
Peak memory	606748 kb
Host	smart-c64805c8-6cb2-412c-aec8-14d89b822fa2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905279228 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.3905279228
Directory	/workspace/2.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2856477770
Short name	T408
Test name
Test status
Simulation time	3059309990 ps
CPU time	250.09 seconds
Started	Jun 09 03:33:03 PM PDT 24
Finished	Jun 09 03:37:13 PM PDT 24
Peak memory	606664 kb
Host	smart-b2255040-6529-4071-b2c1-50ae86913dab
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856 477770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2856477770
Directory	/workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2265704082
Short name	T883
Test name
Test status
Simulation time	2972295082 ps
CPU time	244.68 seconds
Started	Jun 09 03:36:53 PM PDT 24
Finished	Jun 09 03:40:58 PM PDT 24
Peak memory	606672 kb
Host	smart-e008a0b8-a621-4519-be3f-1db24fa39760
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265704082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.2265704082
Directory	/workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_entropy.437173807
Short name	T757
Test name
Test status
Simulation time	3401884300 ps
CPU time	200.24 seconds
Started	Jun 09 03:34:31 PM PDT 24
Finished	Jun 09 03:37:52 PM PDT 24
Peak memory	607496 kb
Host	smart-75545b83-c510-4d3f-a412-74de4f4b4835
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437173807 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.437173807
Directory	/workspace/2.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_idle.4045689922
Short name	T729
Test name
Test status
Simulation time	2697498520 ps
CPU time	197.05 seconds
Started	Jun 09 03:32:13 PM PDT 24
Finished	Jun 09 03:35:30 PM PDT 24
Peak memory	606304 kb
Host	smart-495d295e-2693-46f9-8582-be2bc4250073
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045689922 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.4045689922
Directory	/workspace/2.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_masking_off.1337077929
Short name	T106
Test name
Test status
Simulation time	2624455015 ps
CPU time	277.87 seconds
Started	Jun 09 03:32:55 PM PDT 24
Finished	Jun 09 03:37:33 PM PDT 24
Peak memory	607048 kb
Host	smart-aefc9a3b-9657-4422-a0dd-a17ec3643a00
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337077929 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1337077929
Directory	/workspace/2.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_smoketest.2013553609
Short name	T790
Test name
Test status
Simulation time	3165713444 ps
CPU time	379.48 seconds
Started	Jun 09 03:39:03 PM PDT 24
Finished	Jun 09 03:45:22 PM PDT 24
Peak memory	607112 kb
Host	smart-f4d5b7cc-df61-45db-b392-5f6e473b61f0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013553609 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.2013553609
Directory	/workspace/2.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1245787598
Short name	T27
Test name
Test status
Simulation time	3358439025 ps
CPU time	461.26 seconds
Started	Jun 09 03:33:40 PM PDT 24
Finished	Jun 09 03:41:22 PM PDT 24
Peak memory	607628 kb
Host	smart-a0a0e26c-91c0-430e-b638-d2193d8e9b97
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1245787598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1245787598
Directory	/workspace/2.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.418642024
Short name	T885
Test name
Test status
Simulation time	4613448966 ps
CPU time	435.19 seconds
Started	Jun 09 03:32:52 PM PDT 24
Finished	Jun 09 03:40:08 PM PDT 24
Peak memory	616980 kb
Host	smart-4ad2914b-8742-4be1-b431-af77465da471
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=418642024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.418642024
Directory	/workspace/2.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1975326495
Short name	T605
Test name
Test status
Simulation time	6821609120 ps
CPU time	1785.4 seconds
Started	Jun 09 03:33:11 PM PDT 24
Finished	Jun 09 04:02:57 PM PDT 24
Peak memory	607996 kb
Host	smart-d0af9abe-413a-4c7e-a400-039f24273d21
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1975326495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.1975326495
Directory	/workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2987334123
Short name	T283
Test name
Test status
Simulation time	7881357860 ps
CPU time	1818.61 seconds
Started	Jun 09 03:33:24 PM PDT 24
Finished	Jun 09 04:03:43 PM PDT 24
Peak memory	607016 kb
Host	smart-5b18a110-6e3a-4a65-ab5e-6f29303aa98f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987334123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2987334123
Directory	/workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.667967623
Short name	T128
Test name
Test status
Simulation time	11057625550 ps
CPU time	1382.24 seconds
Started	Jun 09 03:33:17 PM PDT 24
Finished	Jun 09 03:56:20 PM PDT 24
Peak memory	608688 kb
Host	smart-77b1f373-feff-4400-b317-303d48ebc7d2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667967623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.667967623
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3616147236
Short name	T330
Test name
Test status
Simulation time	7731258146 ps
CPU time	1441.81 seconds
Started	Jun 09 03:32:12 PM PDT 24
Finished	Jun 09 03:56:14 PM PDT 24
Peak memory	606800 kb
Host	smart-ef8b8e0d-e535-4f9a-a787-d12c9fd84129
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3616147236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.3616147236
Directory	/workspace/2.chip_sw_alert_handler_ping_ok/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1400973591
Short name	T547
Test name
Test status
Simulation time	4456084914 ps
CPU time	434.25 seconds
Started	Jun 09 03:34:12 PM PDT 24
Finished	Jun 09 03:41:27 PM PDT 24
Peak memory	606948 kb
Host	smart-6e36c1d6-bfc7-4e03-b5e4-0656f7cc9357
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1400973591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.1400973591
Directory	/workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3987003874
Short name	T759
Test name
Test status
Simulation time	255801411092 ps
CPU time	12742.1 seconds
Started	Jun 09 03:33:07 PM PDT 24
Finished	Jun 09 07:05:31 PM PDT 24
Peak memory	608504 kb
Host	smart-341d73a8-6964-4ce6-be56-5a825c9ae09d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987003874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3987003874
Directory	/workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_test.2090163868
Short name	T79
Test name
Test status
Simulation time	3606065540 ps
CPU time	361.15 seconds
Started	Jun 09 03:34:24 PM PDT 24
Finished	Jun 09 03:40:26 PM PDT 24
Peak memory	606668 kb
Host	smart-af7cd428-e92f-410d-b8dc-1c43e46c676f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090163868 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.2090163868
Directory	/workspace/2.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_irq.2795737436
Short name	T143
Test name
Test status
Simulation time	3122161688 ps
CPU time	426.08 seconds
Started	Jun 09 03:31:59 PM PDT 24
Finished	Jun 09 03:39:06 PM PDT 24
Peak memory	606592 kb
Host	smart-6ae22bcc-1ec5-426e-a4e2-9280b361ffed
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795737436 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.2795737436
Directory	/workspace/2.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.692868400
Short name	T794
Test name
Test status
Simulation time	2487793540 ps
CPU time	241.97 seconds
Started	Jun 09 03:38:59 PM PDT 24
Finished	Jun 09 03:43:01 PM PDT 24
Peak memory	606344 kb
Host	smart-a236b0ec-8182-406b-ae48-74412411fba8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692868400 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_aon_timer_smoketest.692868400
Directory	/workspace/2.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.588776975
Short name	T720
Test name
Test status
Simulation time	7765489198 ps
CPU time	995.49 seconds
Started	Jun 09 03:33:39 PM PDT 24
Finished	Jun 09 03:50:15 PM PDT 24
Peak memory	608032 kb
Host	smart-f61ec5c9-236c-4983-9999-dee5e79c1aca
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 588776975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.588776975
Directory	/workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.508059111
Short name	T939
Test name
Test status
Simulation time	4823104816 ps
CPU time	480.92 seconds
Started	Jun 09 03:32:17 PM PDT 24
Finished	Jun 09 03:40:18 PM PDT 24
Peak memory	607400 kb
Host	smart-d7af7668-4770-48bb-8131-91daf6a2a1f3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =508059111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.508059111
Directory	/workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.416871830
Short name	T714
Test name
Test status
Simulation time	7569805798 ps
CPU time	866.78 seconds
Started	Jun 09 03:36:41 PM PDT 24
Finished	Jun 09 03:51:08 PM PDT 24
Peak memory	613456 kb
Host	smart-d65febc0-7efd-4676-9c1e-ac802551bf1c
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416871830 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.416871830
Directory	/workspace/2.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.360602852
Short name	T109
Test name
Test status
Simulation time	21459799466 ps
CPU time	2845.67 seconds
Started	Jun 09 03:37:41 PM PDT 24
Finished	Jun 09 04:25:08 PM PDT 24
Peak memory	608256 kb
Host	smart-2d60a956-0177-4808-9e7a-f8ea81f95f15
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360602852 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.360602852
Directory	/workspace/2.chip_sw_ast_clk_rst_inputs/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3434178713
Short name	T659
Test name
Test status
Simulation time	5883359302 ps
CPU time	426.23 seconds
Started	Jun 09 03:34:37 PM PDT 24
Finished	Jun 09 03:41:43 PM PDT 24
Peak memory	617856 kb
Host	smart-9fe68444-e6af-43d6-999c-e27f516e461e
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3434178713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.3434178713
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.123498901
Short name	T425
Test name
Test status
Simulation time	4795522430 ps
CPU time	808.2 seconds
Started	Jun 09 03:36:57 PM PDT 24
Finished	Jun 09 03:50:26 PM PDT 24
Peak memory	610268 kb
Host	smart-de18cfc1-f855-4d31-bef1-c5d4fa4feb58
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123498901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.123498901
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.385482701
Short name	T796
Test name
Test status
Simulation time	4179349700 ps
CPU time	648.06 seconds
Started	Jun 09 03:36:18 PM PDT 24
Finished	Jun 09 03:47:06 PM PDT 24
Peak memory	609440 kb
Host	smart-c190c885-27ce-4b6a-84d9-c4ab793b6131
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385482701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.385482701
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1097257246
Short name	T989
Test name
Test status
Simulation time	4062819348 ps
CPU time	856.35 seconds
Started	Jun 09 03:35:57 PM PDT 24
Finished	Jun 09 03:50:14 PM PDT 24
Peak memory	610556 kb
Host	smart-c4883d15-2fc2-4bee-bdd5-e13f0a55a2d2
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097257246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1097257246
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1023967359
Short name	T151
Test name
Test status
Simulation time	4303340474 ps
CPU time	614.52 seconds
Started	Jun 09 03:36:19 PM PDT 24
Finished	Jun 09 03:46:34 PM PDT 24
Peak memory	610500 kb
Host	smart-d8ad6f02-7d38-4402-8785-6c3f50701453
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023967359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1023967359
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.470633387
Short name	T927
Test name
Test status
Simulation time	4588964344 ps
CPU time	777.97 seconds
Started	Jun 09 03:36:02 PM PDT 24
Finished	Jun 09 03:49:01 PM PDT 24
Peak memory	608412 kb
Host	smart-c60dd0e0-6577-4936-ab7b-0e124d4c0aad
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470633387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.470633387
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4140974185
Short name	T965
Test name
Test status
Simulation time	4514126040 ps
CPU time	597.23 seconds
Started	Jun 09 03:37:34 PM PDT 24
Finished	Jun 09 03:47:31 PM PDT 24
Peak memory	610316 kb
Host	smart-90e05239-7d6e-4870-9b44-ceeb46c7c780
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140974185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4140974185
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3512276544
Short name	T974
Test name
Test status
Simulation time	3103536404 ps
CPU time	290.46 seconds
Started	Jun 09 03:36:48 PM PDT 24
Finished	Jun 09 03:41:39 PM PDT 24
Peak memory	606488 kb
Host	smart-7843c8da-eb2a-4ba8-b8d1-c42b2538b4fe
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512276544 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.3512276544
Directory	/workspace/2.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.233499167
Short name	T1001
Test name
Test status
Simulation time	2821507416 ps
CPU time	465.06 seconds
Started	Jun 09 03:35:49 PM PDT 24
Finished	Jun 09 03:43:35 PM PDT 24
Peak memory	606992 kb
Host	smart-6a854fc6-0694-4f0e-8198-030f2a31e717
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233499167 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.233499167
Directory	/workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3470992441
Short name	T582
Test name
Test status
Simulation time	2865387363 ps
CPU time	212.98 seconds
Started	Jun 09 03:37:09 PM PDT 24
Finished	Jun 09 03:40:42 PM PDT 24
Peak memory	606316 kb
Host	smart-c1439f2a-dc43-4ca1-9aff-79fa12fd5009
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470992441 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3470992441
Directory	/workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3562964784
Short name	T554
Test name
Test status
Simulation time	4176126956 ps
CPU time	587.5 seconds
Started	Jun 09 03:38:07 PM PDT 24
Finished	Jun 09 03:47:55 PM PDT 24
Peak memory	607748 kb
Host	smart-6b3371ed-4784-4d09-8a7b-1df1a222037f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562964784 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3562964784
Directory	/workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.963271750
Short name	T103
Test name
Test status
Simulation time	4383035948 ps
CPU time	399.12 seconds
Started	Jun 09 03:35:11 PM PDT 24
Finished	Jun 09 03:41:50 PM PDT 24
Peak memory	606952 kb
Host	smart-5d99bf1b-4733-43c1-8e39-df81e60c0ccf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963271750 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.963271750
Directory	/workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.693201384
Short name	T852
Test name
Test status
Simulation time	4294450032 ps
CPU time	487.03 seconds
Started	Jun 09 03:35:33 PM PDT 24
Finished	Jun 09 03:43:41 PM PDT 24
Peak memory	607384 kb
Host	smart-6ea5228b-ae49-460f-b419-3c079166d3d2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693201384 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.693201384
Directory	/workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1445883322
Short name	T417
Test name
Test status
Simulation time	4980559030 ps
CPU time	520.16 seconds
Started	Jun 09 03:35:29 PM PDT 24
Finished	Jun 09 03:44:10 PM PDT 24
Peak memory	606944 kb
Host	smart-dfed10e4-85d6-4379-a7f6-68f1e62c159e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445883322 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.1445883322
Directory	/workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2410247987
Short name	T612
Test name
Test status
Simulation time	12558629976 ps
CPU time	1237.35 seconds
Started	Jun 09 03:37:53 PM PDT 24
Finished	Jun 09 03:58:31 PM PDT 24
Peak memory	608360 kb
Host	smart-4a510984-d56b-4d64-8bb0-2795b4dfa98c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410247987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.2410247987
Directory	/workspace/2.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3586779219
Short name	T882
Test name
Test status
Simulation time	3640946792 ps
CPU time	528.98 seconds
Started	Jun 09 03:35:42 PM PDT 24
Finished	Jun 09 03:44:31 PM PDT 24
Peak memory	606408 kb
Host	smart-90d94b6e-7b97-4e5d-b254-2d57e9881730
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586779219 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3586779219
Directory	/workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.820730752
Short name	T918
Test name
Test status
Simulation time	5093698920 ps
CPU time	730.34 seconds
Started	Jun 09 03:37:27 PM PDT 24
Finished	Jun 09 03:49:38 PM PDT 24
Peak memory	607760 kb
Host	smart-c3bd54e9-95fe-495e-b48b-45a5915ddebf
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820730752 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.820730752
Directory	/workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.313701073
Short name	T586
Test name
Test status
Simulation time	2672607928 ps
CPU time	219.17 seconds
Started	Jun 09 03:39:09 PM PDT 24
Finished	Jun 09 03:42:49 PM PDT 24
Peak memory	606380 kb
Host	smart-235cab0d-1e74-4096-ae77-1b6f39478879
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313701073 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_clkmgr_smoketest.313701073
Directory	/workspace/2.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.172508695
Short name	T704
Test name
Test status
Simulation time	23343221238 ps
CPU time	4818.07 seconds
Started	Jun 09 03:33:05 PM PDT 24
Finished	Jun 09 04:53:24 PM PDT 24
Peak memory	607128 kb
Host	smart-28346163-d7b1-48fc-ab7d-1e23cc683141
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172508695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.172508695
Directory	/workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.375132290
Short name	T199
Test name
Test status
Simulation time	4035987692 ps
CPU time	484.55 seconds
Started	Jun 09 03:33:40 PM PDT 24
Finished	Jun 09 03:41:45 PM PDT 24
Peak memory	606988 kb
Host	smart-e7f4997e-90a6-409a-9d32-7f815f88170d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37513 2290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.375132290
Directory	/workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_kat_test.3538953891
Short name	T618
Test name
Test status
Simulation time	3220811400 ps
CPU time	204.7 seconds
Started	Jun 09 03:33:44 PM PDT 24
Finished	Jun 09 03:37:09 PM PDT 24
Peak memory	607456 kb
Host	smart-dd7aba1b-ec37-49ca-b2fd-161c158274f2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538953891 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.3538953891
Directory	/workspace/2.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_smoketest.886775046
Short name	T798
Test name
Test status
Simulation time	2360976724 ps
CPU time	339.25 seconds
Started	Jun 09 03:39:12 PM PDT 24
Finished	Jun 09 03:44:52 PM PDT 24
Peak memory	606380 kb
Host	smart-be92e043-3686-4ffd-b30e-a5ec3089f6f9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886775046 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_csrng_smoketest.886775046
Directory	/workspace/2.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3979969565
Short name	T281
Test name
Test status
Simulation time	6004885028 ps
CPU time	881.01 seconds
Started	Jun 09 03:32:22 PM PDT 24
Finished	Jun 09 03:47:04 PM PDT 24
Peak memory	608496 kb
Host	smart-4b8c7961-7d16-4b21-beae-2b35fb8b0ead
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3979969565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3979969565
Directory	/workspace/2.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_auto_mode.3640533393
Short name	T672
Test name
Test status
Simulation time	5256687326 ps
CPU time	1405.8 seconds
Started	Jun 09 03:33:16 PM PDT 24
Finished	Jun 09 03:56:42 PM PDT 24
Peak memory	607216 kb
Host	smart-3a27d9ed-700e-46e0-b2d2-6970668c5c6a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640533393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3640533393
Directory	/workspace/2.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_boot_mode.1520944929
Short name	T391
Test name
Test status
Simulation time	2910456348 ps
CPU time	612.92 seconds
Started	Jun 09 03:33:00 PM PDT 24
Finished	Jun 09 03:43:14 PM PDT 24
Peak memory	607072 kb
Host	smart-8320dd26-79a7-48be-b147-07dbf35cf771
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520944929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.1520944929
Directory	/workspace/2.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1455070609
Short name	T774
Test name
Test status
Simulation time	7021347791 ps
CPU time	1105.14 seconds
Started	Jun 09 03:33:04 PM PDT 24
Finished	Jun 09 03:51:29 PM PDT 24
Peak memory	608648 kb
Host	smart-6f35e506-0dc8-4d01-95df-21b496769e47
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455070609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.1455070609
Directory	/workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_kat.4216701023
Short name	T153
Test name
Test status
Simulation time	3340543888 ps
CPU time	622.89 seconds
Started	Jun 09 03:33:50 PM PDT 24
Finished	Jun 09 03:44:13 PM PDT 24
Peak memory	613160 kb
Host	smart-7fadaff0-792c-4a44-b106-0e87653fa6bf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216701023 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.4216701023
Directory	/workspace/2.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_sw_mode.1536284757
Short name	T544
Test name
Test status
Simulation time	7144976218 ps
CPU time	1359.15 seconds
Started	Jun 09 03:34:38 PM PDT 24
Finished	Jun 09 03:57:18 PM PDT 24
Peak memory	607876 kb
Host	smart-0f48e708-76e9-4d67-9158-0ce03f24d999
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536284757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1536284757
Directory	/workspace/2.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1049346914
Short name	T995
Test name
Test status
Simulation time	2419550928 ps
CPU time	241.87 seconds
Started	Jun 09 03:35:07 PM PDT 24
Finished	Jun 09 03:39:10 PM PDT 24
Peak memory	606580 kb
Host	smart-ba1f2538-a655-4000-b819-8060c6171f53
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10 49346914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1049346914
Directory	/workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3258977312
Short name	T353
Test name
Test status
Simulation time	7910754700 ps
CPU time	1726.04 seconds
Started	Jun 09 03:35:10 PM PDT 24
Finished	Jun 09 04:03:56 PM PDT 24
Peak memory	607104 kb
Host	smart-850c1b37-9f1a-4d82-8e88-9177c1d879e6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3258977312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.3258977312
Directory	/workspace/2.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2157647669
Short name	T940
Test name
Test status
Simulation time	2499244488 ps
CPU time	241.41 seconds
Started	Jun 09 03:33:10 PM PDT 24
Finished	Jun 09 03:37:12 PM PDT 24
Peak memory	606544 kb
Host	smart-282a7f26-7a51-44fd-b134-49b68fd7154c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157647669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2157647669
Directory	/workspace/2.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.4062920786
Short name	T776
Test name
Test status
Simulation time	3527094752 ps
CPU time	546.5 seconds
Started	Jun 09 03:39:20 PM PDT 24
Finished	Jun 09 03:48:27 PM PDT 24
Peak memory	606012 kb
Host	smart-eaa13944-ccca-4ee5-be49-1a91f49450ea
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4062920786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.4062920786
Directory	/workspace/2.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_example_concurrency.554095771
Short name	T652
Test name
Test status
Simulation time	3113694364 ps
CPU time	192.88 seconds
Started	Jun 09 03:28:32 PM PDT 24
Finished	Jun 09 03:31:45 PM PDT 24
Peak memory	606336 kb
Host	smart-f580e1b6-0417-41e0-931a-b2d2e2c800a3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554095771 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.554095771
Directory	/workspace/2.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/2.chip_sw_example_flash.3275069260
Short name	T308
Test name
Test status
Simulation time	2493129492 ps
CPU time	269.32 seconds
Started	Jun 09 03:28:20 PM PDT 24
Finished	Jun 09 03:32:50 PM PDT 24
Peak memory	606316 kb
Host	smart-b8d040eb-9b8f-41f0-8136-7393ab165844
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275069260 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.3275069260
Directory	/workspace/2.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/2.chip_sw_example_manufacturer.2662793539
Short name	T657
Test name
Test status
Simulation time	2934329856 ps
CPU time	275.54 seconds
Started	Jun 09 03:29:08 PM PDT 24
Finished	Jun 09 03:33:43 PM PDT 24
Peak memory	606380 kb
Host	smart-f8332fb3-7e75-4cb1-ac95-d3f7e59de8d7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662793539 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2662793539
Directory	/workspace/2.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/2.chip_sw_example_rom.2069864108
Short name	T711
Test name
Test status
Simulation time	3002658412 ps
CPU time	144.44 seconds
Started	Jun 09 03:28:40 PM PDT 24
Finished	Jun 09 03:31:05 PM PDT 24
Peak memory	606656 kb
Host	smart-08af9185-3f42-4a36-938e-047bcff8c61c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069864108 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.2069864108
Directory	/workspace/2.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_crash_alert.732411615
Short name	T535
Test name
Test status
Simulation time	5752106728 ps
CPU time	561.1 seconds
Started	Jun 09 03:37:15 PM PDT 24
Finished	Jun 09 03:46:37 PM PDT 24
Peak memory	608612 kb
Host	smart-b3b3dac7-08cf-4271-99dd-c27aa0d5f462
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=732411615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.732411615
Directory	/workspace/2.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.843283516
Short name	T538
Test name
Test status
Simulation time	5580678640 ps
CPU time	1142.39 seconds
Started	Jun 09 03:30:51 PM PDT 24
Finished	Jun 09 03:49:53 PM PDT 24
Peak memory	606736 kb
Host	smart-4f4181be-4618-4f2e-8aa2-cc2b7717351c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843283516 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_flash_ctrl_access.843283516
Directory	/workspace/2.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3883524893
Short name	T869
Test name
Test status
Simulation time	6314250659 ps
CPU time	1123.09 seconds
Started	Jun 09 03:32:58 PM PDT 24
Finished	Jun 09 03:51:41 PM PDT 24
Peak memory	606812 kb
Host	smart-d23f6415-74ee-4696-93dc-3aeba2a782ae
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883524893 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.3883524893
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3723074611
Short name	T640
Test name
Test status
Simulation time	7347918115 ps
CPU time	1124.66 seconds
Started	Jun 09 03:39:20 PM PDT 24
Finished	Jun 09 03:58:05 PM PDT 24
Peak memory	606632 kb
Host	smart-7b5c97e0-cbe1-4586-a1db-00f1ca03333c
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723074611 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3723074611
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2113758653
Short name	T901
Test name
Test status
Simulation time	5452054231 ps
CPU time	1099.51 seconds
Started	Jun 09 03:29:35 PM PDT 24
Finished	Jun 09 03:47:55 PM PDT 24
Peak memory	606684 kb
Host	smart-21f52420-38f8-4ec9-af02-4253683c8ed1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113758653 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.2113758653
Directory	/workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1385056267
Short name	T745
Test name
Test status
Simulation time	3694956060 ps
CPU time	352.72 seconds
Started	Jun 09 03:30:52 PM PDT 24
Finished	Jun 09 03:36:45 PM PDT 24
Peak memory	607040 kb
Host	smart-8c4b4277-63f7-4677-b825-45342f5bf714
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385056267 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.1385056267
Directory	/workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3331538276
Short name	T112
Test name
Test status
Simulation time	5518701617 ps
CPU time	494.41 seconds
Started	Jun 09 03:29:14 PM PDT 24
Finished	Jun 09 03:37:30 PM PDT 24
Peak memory	608256 kb
Host	smart-6285a088-0bb8-4c34-bd6d-6bf7a65f93c2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33 31538276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.3331538276
Directory	/workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.22527068
Short name	T549
Test name
Test status
Simulation time	5413073304 ps
CPU time	1329.09 seconds
Started	Jun 09 03:37:16 PM PDT 24
Finished	Jun 09 03:59:25 PM PDT 24
Peak memory	606720 kb
Host	smart-ba9cf5bd-b9ea-4637-9f8d-c060f1730be6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527068 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.22527068
Directory	/workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2838057572
Short name	T404
Test name
Test status
Simulation time	4292309965 ps
CPU time	646.9 seconds
Started	Jun 09 03:30:39 PM PDT 24
Finished	Jun 09 03:41:27 PM PDT 24
Peak memory	606608 kb
Host	smart-01ee5b65-ff23-4baf-9ea9-d789501a388c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2838057572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2838057572
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2885383522
Short name	T150
Test name
Test status
Simulation time	5097458791 ps
CPU time	752.44 seconds
Started	Jun 09 03:37:16 PM PDT 24
Finished	Jun 09 03:49:48 PM PDT 24
Peak memory	606888 kb
Host	smart-17d87179-18af-4ffd-abf9-952275158213
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2885383522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2885383522
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1628486405
Short name	T914
Test name
Test status
Simulation time	2916422728 ps
CPU time	304.05 seconds
Started	Jun 09 03:37:26 PM PDT 24
Finished	Jun 09 03:42:30 PM PDT 24
Peak memory	606484 kb
Host	smart-b59b2ece-430c-419b-abe5-0699dd66b24a
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628486 405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1628486405
Directory	/workspace/2.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_init.2324067950
Short name	T990
Test name
Test status
Simulation time	24076158403 ps
CPU time	1769.62 seconds
Started	Jun 09 03:31:16 PM PDT 24
Finished	Jun 09 04:00:46 PM PDT 24
Peak memory	609892 kb
Host	smart-a1ef9497-b4f3-485f-ace6-f258b5723849
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324067950 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2324067950
Directory	/workspace/2.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1293380784
Short name	T784
Test name
Test status
Simulation time	2913433620 ps
CPU time	235.4 seconds
Started	Jun 09 03:41:15 PM PDT 24
Finished	Jun 09 03:45:11 PM PDT 24
Peak memory	606888 kb
Host	smart-d79f6d13-8d2f-4425-8c55-fd7c1f827020
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1293380784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1293380784
Directory	/workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_gpio_smoketest.1322630430
Short name	T129
Test name
Test status
Simulation time	3067960567 ps
CPU time	186.25 seconds
Started	Jun 09 03:42:14 PM PDT 24
Finished	Jun 09 03:45:21 PM PDT 24
Peak memory	606428 kb
Host	smart-7cb46505-6b0e-46ef-a36f-f08ffbcae081
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322630430 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.1322630430
Directory	/workspace/2.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc.1231243530
Short name	T827
Test name
Test status
Simulation time	2806817630 ps
CPU time	342.37 seconds
Started	Jun 09 03:34:42 PM PDT 24
Finished	Jun 09 03:40:24 PM PDT 24
Peak memory	606500 kb
Host	smart-15e85d12-8071-4beb-b187-f6b3ab9cb6c9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231243530 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.1231243530
Directory	/workspace/2.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.55393660
Short name	T734
Test name
Test status
Simulation time	2847628104 ps
CPU time	362.07 seconds
Started	Jun 09 03:33:29 PM PDT 24
Finished	Jun 09 03:39:31 PM PDT 24
Peak memory	606252 kb
Host	smart-55edabc6-ec0b-4e97-a6cf-47cf6e138b5b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55393660 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_hmac_enc_idle.55393660
Directory	/workspace/2.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.217616891
Short name	T178
Test name
Test status
Simulation time	2763550664 ps
CPU time	206.24 seconds
Started	Jun 09 03:32:54 PM PDT 24
Finished	Jun 09 03:36:20 PM PDT 24
Peak memory	607056 kb
Host	smart-fbef12ca-31f8-49f0-8c32-add12a0f4cfc
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217616891 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.217616891
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.913887750
Short name	T94
Test name
Test status
Simulation time	2729121615 ps
CPU time	289.07 seconds
Started	Jun 09 03:41:08 PM PDT 24
Finished	Jun 09 03:45:58 PM PDT 24
Peak memory	606412 kb
Host	smart-e1eb21be-b492-4436-9d87-ac19d86df492
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913887750 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.913887750
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_multistream.138198770
Short name	T93
Test name
Test status
Simulation time	6727936976 ps
CPU time	1532.41 seconds
Started	Jun 09 03:34:35 PM PDT 24
Finished	Jun 09 04:00:08 PM PDT 24
Peak memory	606652 kb
Host	smart-a579dd8c-5675-4451-a219-348a4687dccd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138198770 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_hmac_multistream.138198770
Directory	/workspace/2.chip_sw_hmac_multistream/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_oneshot.339051995
Short name	T58
Test name
Test status
Simulation time	3345640434 ps
CPU time	400.43 seconds
Started	Jun 09 03:35:08 PM PDT 24
Finished	Jun 09 03:41:49 PM PDT 24
Peak memory	606504 kb
Host	smart-b485dffb-3583-4cdf-8af4-4fcb8f54920e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339051995 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.339051995
Directory	/workspace/2.chip_sw_hmac_oneshot/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_smoketest.2510084593
Short name	T534
Test name
Test status
Simulation time	3260004160 ps
CPU time	349.49 seconds
Started	Jun 09 03:42:10 PM PDT 24
Finished	Jun 09 03:48:00 PM PDT 24
Peak memory	606328 kb
Host	smart-3681c098-e820-49d8-8d65-2ef1b3ce72eb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510084593 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2510084593
Directory	/workspace/2.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2690897957
Short name	T366
Test name
Test status
Simulation time	3664082822 ps
CPU time	566.3 seconds
Started	Jun 09 03:30:32 PM PDT 24
Finished	Jun 09 03:39:59 PM PDT 24
Peak memory	607548 kb
Host	smart-f88f5877-e6d6-46c9-b4f9-3af9a9aa9b9d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690897957 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2690897957
Directory	/workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2790005428
Short name	T30
Test name
Test status
Simulation time	4546676290 ps
CPU time	959.35 seconds
Started	Jun 09 03:29:06 PM PDT 24
Finished	Jun 09 03:45:06 PM PDT 24
Peak memory	607736 kb
Host	smart-9106177b-3233-4035-b1ed-57dc9dabce36
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790005428 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.2790005428
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1503845818
Short name	T212
Test name
Test status
Simulation time	5047752536 ps
CPU time	724.01 seconds
Started	Jun 09 03:30:05 PM PDT 24
Finished	Jun 09 03:42:09 PM PDT 24
Peak memory	606736 kb
Host	smart-ceba3c68-6ffc-4878-8c69-811f8ebaa4c5
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503845818 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.1503845818
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.4047679452
Short name	T752
Test name
Test status
Simulation time	64626864430 ps
CPU time	10604 seconds
Started	Jun 09 03:30:15 PM PDT 24
Finished	Jun 09 06:27:00 PM PDT 24
Peak memory	623760 kb
Host	smart-709b16ff-74a3-4450-8bea-97250677b54b
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4047679452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.4047679452
Directory	/workspace/2.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1071025102
Short name	T814
Test name
Test status
Simulation time	9254735288 ps
CPU time	1648.66 seconds
Started	Jun 09 03:34:06 PM PDT 24
Finished	Jun 09 04:01:35 PM PDT 24
Peak memory	613988 kb
Host	smart-16e80f41-ac03-406c-b882-d2d2e2bda59e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071 025102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1071025102
Directory	/workspace/2.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.205445029
Short name	T606
Test name
Test status
Simulation time	11321489583 ps
CPU time	1845.12 seconds
Started	Jun 09 03:37:09 PM PDT 24
Finished	Jun 09 04:07:55 PM PDT 24
Peak memory	613980 kb
Host	smart-14f3c35a-2a70-41be-88c5-f73d8682e0b9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=205445029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.205445029
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1067843307
Short name	T300
Test name
Test status
Simulation time	10438772716 ps
CPU time	1198.34 seconds
Started	Jun 09 03:36:59 PM PDT 24
Finished	Jun 09 03:56:57 PM PDT 24
Peak memory	615328 kb
Host	smart-91b34276-8c82-4623-ae09-02489bda5b7e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1067843307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1067843307
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1604498320
Short name	T823
Test name
Test status
Simulation time	7020512152 ps
CPU time	1319.79 seconds
Started	Jun 09 03:33:43 PM PDT 24
Finished	Jun 09 03:55:43 PM PDT 24
Peak memory	614604 kb
Host	smart-a560cf4c-32a3-4bca-8e2c-15bb835e6747
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1604498320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.1604498320
Directory	/workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2876803835
Short name	T609
Test name
Test status
Simulation time	6823630920 ps
CPU time	1059.92 seconds
Started	Jun 09 03:34:57 PM PDT 24
Finished	Jun 09 03:52:37 PM PDT 24
Peak memory	608972 kb
Host	smart-7b9807ed-fbb7-420d-aa99-3f512ee31b21
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28768 03835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.2876803835
Directory	/workspace/2.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1746484841
Short name	T327
Test name
Test status
Simulation time	16110816824 ps
CPU time	3489.83 seconds
Started	Jun 09 03:35:45 PM PDT 24
Finished	Jun 09 04:33:56 PM PDT 24
Peak memory	608704 kb
Host	smart-83ea6b16-047e-471f-99f8-e22eba5dd4d0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17464 84841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.1746484841
Directory	/workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_app_rom.770953257
Short name	T868
Test name
Test status
Simulation time	2945148728 ps
CPU time	276.11 seconds
Started	Jun 09 03:34:09 PM PDT 24
Finished	Jun 09 03:38:45 PM PDT 24
Peak memory	607012 kb
Host	smart-ec450f97-09ee-4ef3-bb3f-289fe8b67c2f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770953257 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_app_rom.770953257
Directory	/workspace/2.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_entropy.288690235
Short name	T98
Test name
Test status
Simulation time	2812103304 ps
CPU time	316.12 seconds
Started	Jun 09 03:30:56 PM PDT 24
Finished	Jun 09 03:36:13 PM PDT 24
Peak memory	607128 kb
Host	smart-35848dc2-2b25-42b0-9141-c626d4b056d8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288690235 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_entropy.288690235
Directory	/workspace/2.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_idle.1988435468
Short name	T620
Test name
Test status
Simulation time	3183036650 ps
CPU time	262.12 seconds
Started	Jun 09 03:35:23 PM PDT 24
Finished	Jun 09 03:39:45 PM PDT 24
Peak memory	606380 kb
Host	smart-73ed048a-3b2f-468d-93d2-61c3d02b0cb5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988435468 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1988435468
Directory	/workspace/2.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1557127510
Short name	T96
Test name
Test status
Simulation time	2799902346 ps
CPU time	331.45 seconds
Started	Jun 09 03:34:54 PM PDT 24
Finished	Jun 09 03:40:26 PM PDT 24
Peak memory	606320 kb
Host	smart-f9076cd8-89d8-490c-926b-99c1398ce91e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557127510 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.1557127510
Directory	/workspace/2.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2320213933
Short name	T862
Test name
Test status
Simulation time	3675741636 ps
CPU time	407.05 seconds
Started	Jun 09 03:36:01 PM PDT 24
Finished	Jun 09 03:42:48 PM PDT 24
Peak memory	606956 kb
Host	smart-986c749d-5050-4c20-a9f3-d5e37cb08f19
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320213933 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.2320213933
Directory	/workspace/2.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.4220088165
Short name	T546
Test name
Test status
Simulation time	3211576148 ps
CPU time	330.64 seconds
Started	Jun 09 03:35:50 PM PDT 24
Finished	Jun 09 03:41:21 PM PDT 24
Peak memory	607000 kb
Host	smart-7bf19429-c3bb-4687-a5ad-45d6d1482465
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220088165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.4220088165
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3794236679
Short name	T622
Test name
Test status
Simulation time	2459245296 ps
CPU time	292.8 seconds
Started	Jun 09 03:37:25 PM PDT 24
Finished	Jun 09 03:42:19 PM PDT 24
Peak memory	606464 kb
Host	smart-3c7449b0-1a15-4685-95c0-46df5b8fdecf
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37942366 79 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3794236679
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_smoketest.1522973043
Short name	T871
Test name
Test status
Simulation time	2329379552 ps
CPU time	246.63 seconds
Started	Jun 09 03:38:45 PM PDT 24
Finished	Jun 09 03:42:52 PM PDT 24
Peak memory	606344 kb
Host	smart-fbc91453-4a2e-4068-9e1a-ebcb7130902e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522973043 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.1522973043
Directory	/workspace/2.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3901483014
Short name	T889
Test name
Test status
Simulation time	3691669252 ps
CPU time	350.55 seconds
Started	Jun 09 03:31:08 PM PDT 24
Finished	Jun 09 03:36:59 PM PDT 24
Peak memory	607000 kb
Host	smart-6ed6322d-89e5-4523-aa3b-ba0aa1379a4f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901483014 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.3901483014
Directory	/workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2504842137
Short name	T70
Test name
Test status
Simulation time	3688872492 ps
CPU time	158.08 seconds
Started	Jun 09 03:31:12 PM PDT 24
Finished	Jun 09 03:33:50 PM PDT 24
Peak memory	617644 kb
Host	smart-7089bc50-534c-4115-ac64-c4dbcb548605
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25048421 37 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.2504842137
Directory	/workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.520815977
Short name	T655
Test name
Test status
Simulation time	6175321701 ps
CPU time	520.41 seconds
Started	Jun 09 03:31:22 PM PDT 24
Finished	Jun 09 03:40:03 PM PDT 24
Peak memory	617972 kb
Host	smart-227ca4aa-d8a5-4936-9254-79cd9e8d810e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520815977 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.520815977
Directory	/workspace/2.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.776479149
Short name	T953
Test name
Test status
Simulation time	2430314722 ps
CPU time	105.11 seconds
Started	Jun 09 03:32:33 PM PDT 24
Finished	Jun 09 03:34:19 PM PDT 24
Peak memory	613156 kb
Host	smart-93f3f412-9373-4cda-9221-cb970d13fe7e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=776479149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.776479149
Directory	/workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1340659428
Short name	T432
Test name
Test status
Simulation time	2060386857 ps
CPU time	107.09 seconds
Started	Jun 09 03:30:58 PM PDT 24
Finished	Jun 09 03:32:47 PM PDT 24
Peak memory	614652 kb
Host	smart-56fdef4c-f084-4f28-a140-236b967001fe
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340659428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1340659428
Directory	/workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.894377423
Short name	T238
Test name
Test status
Simulation time	49326921532 ps
CPU time	4840.84 seconds
Started	Jun 09 03:30:47 PM PDT 24
Finished	Jun 09 04:51:29 PM PDT 24
Peak memory	618152 kb
Host	smart-ee7d67d9-4031-4758-88d7-9d3928f327e7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894377423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_dev.894377423
Directory	/workspace/2.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1161375708
Short name	T743
Test name
Test status
Simulation time	8702756723 ps
CPU time	1056.4 seconds
Started	Jun 09 03:32:51 PM PDT 24
Finished	Jun 09 03:50:28 PM PDT 24
Peak memory	614648 kb
Host	smart-8d1fc8b6-7dc3-42b4-867b-8ea492283576
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161375708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1161375708
Directory	/workspace/2.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.447958823
Short name	T677
Test name
Test status
Simulation time	49513547015 ps
CPU time	4784.26 seconds
Started	Jun 09 03:30:13 PM PDT 24
Finished	Jun 09 04:49:59 PM PDT 24
Peak memory	614856 kb
Host	smart-f62657f1-5e61-4bff-9f40-cc10eb287568
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447958823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_rma.447958823
Directory	/workspace/2.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3477395820
Short name	T966
Test name
Test status
Simulation time	30022950240 ps
CPU time	1937.71 seconds
Started	Jun 09 03:31:31 PM PDT 24
Finished	Jun 09 04:03:49 PM PDT 24
Peak memory	614624 kb
Host	smart-79c6cc18-c37d-49b8-9bee-a777b7c83641
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3477395820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.3477395820
Directory	/workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.378296768
Short name	T174
Test name
Test status
Simulation time	17300227060 ps
CPU time	3317.66 seconds
Started	Jun 09 03:32:20 PM PDT 24
Finished	Jun 09 04:27:38 PM PDT 24
Peak memory	608060 kb
Host	smart-64ac444b-d292-4b0e-b7de-e19685c8d003
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=378296768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.378296768
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.4091558444
Short name	T107
Test name
Test status
Simulation time	18751091972 ps
CPU time	4036.54 seconds
Started	Jun 09 03:31:48 PM PDT 24
Finished	Jun 09 04:39:06 PM PDT 24
Peak memory	606996 kb
Host	smart-a02ab12f-0e5f-49eb-85bf-05c761b205b8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4091558444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.4091558444
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3127588272
Short name	T636
Test name
Test status
Simulation time	24933728409 ps
CPU time	3901.69 seconds
Started	Jun 09 03:38:44 PM PDT 24
Finished	Jun 09 04:43:47 PM PDT 24
Peak memory	607608 kb
Host	smart-c63a97a9-a78f-4e9d-82a0-92b29ec31062
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127588272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3127588272
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.434114449
Short name	T783
Test name
Test status
Simulation time	3536066104 ps
CPU time	464.08 seconds
Started	Jun 09 03:31:52 PM PDT 24
Finished	Jun 09 03:39:37 PM PDT 24
Peak memory	606732 kb
Host	smart-c0288d6c-6ab8-4617-847e-24d9a3028136
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434114449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.434114449
Directory	/workspace/2.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_randomness.4271559341
Short name	T982
Test name
Test status
Simulation time	6288629504 ps
CPU time	1177.23 seconds
Started	Jun 09 03:33:43 PM PDT 24
Finished	Jun 09 03:53:21 PM PDT 24
Peak memory	606808 kb
Host	smart-811eed66-46e3-421c-b35f-8ce60e48d393
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4271559341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.4271559341
Directory	/workspace/2.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_smoketest.2645012980
Short name	T943
Test name
Test status
Simulation time	7381251708 ps
CPU time	1297.29 seconds
Started	Jun 09 03:39:16 PM PDT 24
Finished	Jun 09 04:00:54 PM PDT 24
Peak memory	607592 kb
Host	smart-5b129ff4-7339-44d3-8f73-d4a5016e6ee9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645012980 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.2645012980
Directory	/workspace/2.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1046364057
Short name	T581
Test name
Test status
Simulation time	3027687970 ps
CPU time	317.9 seconds
Started	Jun 09 03:29:53 PM PDT 24
Finished	Jun 09 03:35:12 PM PDT 24
Peak memory	607472 kb
Host	smart-6d57721e-b935-4e08-8b56-cb908691f154
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046364057 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.1046364057
Directory	/workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3448164365
Short name	T593
Test name
Test status
Simulation time	7286770916 ps
CPU time	1199.26 seconds
Started	Jun 09 03:30:31 PM PDT 24
Finished	Jun 09 03:50:30 PM PDT 24
Peak memory	606792 kb
Host	smart-090eebce-0b92-4c24-a02a-0766a0677cd7
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3448164365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.3448164365
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.684193103
Short name	T604
Test name
Test status
Simulation time	8518886340 ps
CPU time	1402.44 seconds
Started	Jun 09 03:29:32 PM PDT 24
Finished	Jun 09 03:52:55 PM PDT 24
Peak memory	608120 kb
Host	smart-06183dfc-4211-4de6-ae90-38cbaa27a822
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=684193103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.684193103
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1515374612
Short name	T821
Test name
Test status
Simulation time	6847346312 ps
CPU time	1290.76 seconds
Started	Jun 09 03:31:29 PM PDT 24
Finished	Jun 09 03:53:00 PM PDT 24
Peak memory	607796 kb
Host	smart-6b4be052-2a10-4255-80ee-b34b1841e8d1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1515374612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.1515374612
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3271894842
Short name	T187
Test name
Test status
Simulation time	4775360872 ps
CPU time	850.03 seconds
Started	Jun 09 03:30:36 PM PDT 24
Finished	Jun 09 03:44:47 PM PDT 24
Peak memory	606688 kb
Host	smart-fbc2a468-1497-496a-b324-165bd3168728
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3271894842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3271894842
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2420270336
Short name	T694
Test name
Test status
Simulation time	3220241744 ps
CPU time	329.74 seconds
Started	Jun 09 03:41:32 PM PDT 24
Finished	Jun 09 03:47:02 PM PDT 24
Peak memory	606320 kb
Host	smart-4e9cce74-acca-461e-8244-0ee78c616786
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420270336 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.2420270336
Directory	/workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pattgen_ios.2841252644
Short name	T340
Test name
Test status
Simulation time	3437474110 ps
CPU time	323.8 seconds
Started	Jun 09 03:28:49 PM PDT 24
Finished	Jun 09 03:34:14 PM PDT 24
Peak memory	608500 kb
Host	smart-b2203d86-4724-4276-a771-502f181fc10c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841252644 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2841252644
Directory	/workspace/2.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/2.chip_sw_plic_sw_irq.379937012
Short name	T255
Test name
Test status
Simulation time	2703580616 ps
CPU time	244.41 seconds
Started	Jun 09 03:35:06 PM PDT 24
Finished	Jun 09 03:39:11 PM PDT 24
Peak memory	606540 kb
Host	smart-4165c6f4-53da-49f5-bbb5-1065b73393db
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379937012 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_plic_sw_irq.379937012
Directory	/workspace/2.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_power_idle_load.4204802964
Short name	T971
Test name
Test status
Simulation time	4971233328 ps
CPU time	596.7 seconds
Started	Jun 09 03:37:31 PM PDT 24
Finished	Jun 09 03:47:28 PM PDT 24
Peak memory	607036 kb
Host	smart-fac8aec0-5941-49ae-905d-d43c406e6719
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204802964 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.4204802964
Directory	/workspace/2.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/2.chip_sw_power_sleep_load.4020249376
Short name	T928
Test name
Test status
Simulation time	11397583356 ps
CPU time	764.62 seconds
Started	Jun 09 03:37:28 PM PDT 24
Finished	Jun 09 03:50:13 PM PDT 24
Peak memory	608528 kb
Host	smart-ebada1fa-8a0d-4f72-b4a9-435e07db755a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020249376 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.4020249376
Directory	/workspace/2.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4021077105
Short name	T857
Test name
Test status
Simulation time	10648011442 ps
CPU time	1470.48 seconds
Started	Jun 09 03:31:03 PM PDT 24
Finished	Jun 09 03:55:34 PM PDT 24
Peak memory	609172 kb
Host	smart-5d7ddc51-9a65-422e-98f3-ec68028553b0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021 077105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.4021077105
Directory	/workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3670289495
Short name	T617
Test name
Test status
Simulation time	27378579096 ps
CPU time	2187.63 seconds
Started	Jun 09 03:35:08 PM PDT 24
Finished	Jun 09 04:11:36 PM PDT 24
Peak memory	608004 kb
Host	smart-0a569daf-acc1-4da2-95a0-604ba2879bc1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367 0289495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.3670289495
Directory	/workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3710154927
Short name	T627
Test name
Test status
Simulation time	13581504526 ps
CPU time	1662.01 seconds
Started	Jun 09 03:34:30 PM PDT 24
Finished	Jun 09 04:02:12 PM PDT 24
Peak memory	608608 kb
Host	smart-e1e693cc-5bbb-4333-86db-108a16935810
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3710154927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3710154927
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2450132724
Short name	T141
Test name
Test status
Simulation time	23454497500 ps
CPU time	1884.99 seconds
Started	Jun 09 03:35:58 PM PDT 24
Finished	Jun 09 04:07:24 PM PDT 24
Peak memory	608160 kb
Host	smart-21f99bf1-4e19-42bc-af68-c33332af354f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2450132724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2450132724
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.917200566
Short name	T758
Test name
Test status
Simulation time	7005284470 ps
CPU time	726.22 seconds
Started	Jun 09 03:30:38 PM PDT 24
Finished	Jun 09 03:42:44 PM PDT 24
Peak memory	608020 kb
Host	smart-0019a24a-3641-4aa8-be6f-1c1b5b75e266
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917200566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.917200566
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.515684093
Short name	T542
Test name
Test status
Simulation time	6566004824 ps
CPU time	402.34 seconds
Started	Jun 09 03:32:36 PM PDT 24
Finished	Jun 09 03:39:19 PM PDT 24
Peak memory	613724 kb
Host	smart-ad9afc8e-d05e-4b4d-aaa3-a6040d37a799
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=515684093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.515684093
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2499806577
Short name	T149
Test name
Test status
Simulation time	9652712273 ps
CPU time	500.38 seconds
Started	Jun 09 03:31:05 PM PDT 24
Finished	Jun 09 03:39:25 PM PDT 24
Peak memory	608312 kb
Host	smart-a3e3edbd-f265-4321-81cf-501114f71c7d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499806577 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2499806577
Directory	/workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2295953929
Short name	T358
Test name
Test status
Simulation time	4067508680 ps
CPU time	452.45 seconds
Started	Jun 09 03:35:34 PM PDT 24
Finished	Jun 09 03:43:07 PM PDT 24
Peak memory	606384 kb
Host	smart-12a392de-6d95-464c-bcbf-0745513a55fc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295953929 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.2295953929
Directory	/workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.155908152
Short name	T601
Test name
Test status
Simulation time	3891992592 ps
CPU time	392.08 seconds
Started	Jun 09 03:31:45 PM PDT 24
Finished	Jun 09 03:38:18 PM PDT 24
Peak memory	613708 kb
Host	smart-cb136442-00b0-4f33-8273-b3c871c83b2f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=155908152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.155908152
Directory	/workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4087185404
Short name	T768
Test name
Test status
Simulation time	10323109916 ps
CPU time	1477.55 seconds
Started	Jun 09 03:31:42 PM PDT 24
Finished	Jun 09 03:56:21 PM PDT 24
Peak memory	609000 kb
Host	smart-605c0e8d-4210-42ce-8f41-ff7bcfe64387
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087185404 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4087185404
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3116819383
Short name	T2
Test name
Test status
Simulation time	6852887266 ps
CPU time	537.32 seconds
Started	Jun 09 03:37:23 PM PDT 24
Finished	Jun 09 03:46:21 PM PDT 24
Peak memory	607124 kb
Host	smart-5a5db9d8-4176-4ab5-be12-0b37048bc47e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116819383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3116819383
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1720501100
Short name	T35
Test name
Test status
Simulation time	7009049128 ps
CPU time	622.19 seconds
Started	Jun 09 03:30:41 PM PDT 24
Finished	Jun 09 03:41:03 PM PDT 24
Peak memory	607388 kb
Host	smart-05a381b8-d826-46f3-a629-3d1c5c65d917
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720501100 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.1720501100
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1674558397
Short name	T611
Test name
Test status
Simulation time	25678532507 ps
CPU time	2721.5 seconds
Started	Jun 09 03:31:12 PM PDT 24
Finished	Jun 09 04:16:34 PM PDT 24
Peak memory	609008 kb
Host	smart-1c0511fd-07f3-453e-8636-65e67fe838a1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1674558397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1674558397
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2504420360
Short name	T11
Test name
Test status
Simulation time	21198391830 ps
CPU time	1745.07 seconds
Started	Jun 09 03:38:10 PM PDT 24
Finished	Jun 09 04:07:16 PM PDT 24
Peak memory	608472 kb
Host	smart-8825d275-0eb5-487b-a046-1055f06cb35f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2504420360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2504420360
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.971543855
Short name	T371
Test name
Test status
Simulation time	37706702838 ps
CPU time	2980.01 seconds
Started	Jun 09 03:34:29 PM PDT 24
Finished	Jun 09 04:24:10 PM PDT 24
Peak memory	608780 kb
Host	smart-d82eaa69-3b2b-46bc-ae47-ec6ceaadf504
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971543855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.971543855
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1711460502
Short name	T379
Test name
Test status
Simulation time	5687164416 ps
CPU time	518.88 seconds
Started	Jun 09 03:36:16 PM PDT 24
Finished	Jun 09 03:44:55 PM PDT 24
Peak memory	607460 kb
Host	smart-e2032d16-f259-4249-9e5c-e1aaa1924ef4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1711460502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1711460502
Directory	/workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.871516804
Short name	T377
Test name
Test status
Simulation time	3133377224 ps
CPU time	320.6 seconds
Started	Jun 09 03:32:36 PM PDT 24
Finished	Jun 09 03:37:57 PM PDT 24
Peak memory	606316 kb
Host	smart-5d5f250f-272a-44c4-b007-34b38901b0d6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871516804 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.871516804
Directory	/workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1797434855
Short name	T725
Test name
Test status
Simulation time	5012515114 ps
CPU time	387.15 seconds
Started	Jun 09 03:32:14 PM PDT 24
Finished	Jun 09 03:38:42 PM PDT 24
Peak memory	613420 kb
Host	smart-1b1d77c0-42c6-425d-bc1a-cc768719532b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1797434855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1797434855
Directory	/workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.675301943
Short name	T157
Test name
Test status
Simulation time	5335422786 ps
CPU time	452.48 seconds
Started	Jun 09 03:35:21 PM PDT 24
Finished	Jun 09 03:42:53 PM PDT 24
Peak memory	606768 kb
Host	smart-5a768568-dfc2-4401-8249-e7f525f80efe
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67530194 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.675301943
Directory	/workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2483732604
Short name	T386
Test name
Test status
Simulation time	5208621344 ps
CPU time	508.06 seconds
Started	Jun 09 03:36:12 PM PDT 24
Finished	Jun 09 03:44:40 PM PDT 24
Peak memory	608188 kb
Host	smart-e2c8281a-d0c8-462c-884a-7e743b36d558
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2483732604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.2483732604
Directory	/workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2786291937
Short name	T818
Test name
Test status
Simulation time	5474955784 ps
CPU time	368.52 seconds
Started	Jun 09 03:40:03 PM PDT 24
Finished	Jun 09 03:46:12 PM PDT 24
Peak memory	607028 kb
Host	smart-2edef2c0-66f5-4849-9382-95e8fa133f3e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786291937 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.2786291937
Directory	/workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2287430127
Short name	T724
Test name
Test status
Simulation time	6720248380 ps
CPU time	1242.85 seconds
Started	Jun 09 03:32:00 PM PDT 24
Finished	Jun 09 03:52:43 PM PDT 24
Peak memory	608420 kb
Host	smart-ee4916cb-1fdc-4670-aaa7-93cee214dc50
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287430127 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.2287430127
Directory	/workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1360874626
Short name	T305
Test name
Test status
Simulation time	4892819240 ps
CPU time	491.69 seconds
Started	Jun 09 03:33:13 PM PDT 24
Finished	Jun 09 03:41:26 PM PDT 24
Peak memory	606988 kb
Host	smart-decc4848-53e0-4b9c-8c7f-9773ff1ab4f3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360874626 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1360874626
Directory	/workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1028537613
Short name	T881
Test name
Test status
Simulation time	6685515760 ps
CPU time	372.55 seconds
Started	Jun 09 03:39:00 PM PDT 24
Finished	Jun 09 03:45:14 PM PDT 24
Peak memory	606988 kb
Host	smart-09327a9a-253d-48b1-9b0f-0edc914972a9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028537613 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1028537613
Directory	/workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3498295759
Short name	T566
Test name
Test status
Simulation time	4561584230 ps
CPU time	735.75 seconds
Started	Jun 09 03:33:54 PM PDT 24
Finished	Jun 09 03:46:11 PM PDT 24
Peak memory	607248 kb
Host	smart-40c38f85-6597-4ef4-b0b8-d3a2d10a6101
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349 8295759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.3498295759
Directory	/workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1478192079
Short name	T82
Test name
Test status
Simulation time	9802504200 ps
CPU time	458.49 seconds
Started	Jun 09 03:34:21 PM PDT 24
Finished	Jun 09 03:42:00 PM PDT 24
Peak memory	608228 kb
Host	smart-32553aa8-340c-43e1-a52d-f459443e2b72
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478192079 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1478192079
Directory	/workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3293004695
Short name	T338
Test name
Test status
Simulation time	13422129382 ps
CPU time	1667.01 seconds
Started	Jun 09 03:33:14 PM PDT 24
Finished	Jun 09 04:01:02 PM PDT 24
Peak memory	608664 kb
Host	smart-74f1dba8-1602-4b7c-97d7-16dda59ef35f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3293004695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.3293004695
Directory	/workspace/2.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3133444149
Short name	T802
Test name
Test status
Simulation time	5249537004 ps
CPU time	602.35 seconds
Started	Jun 09 03:32:10 PM PDT 24
Finished	Jun 09 03:42:13 PM PDT 24
Peak memory	639352 kb
Host	smart-31911db2-f4f5-4d24-ae70-2b92bc25047f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3133444149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.3133444149
Directory	/workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.490884701
Short name	T839
Test name
Test status
Simulation time	2239517060 ps
CPU time	251.79 seconds
Started	Jun 09 03:39:41 PM PDT 24
Finished	Jun 09 03:43:53 PM PDT 24
Peak memory	606368 kb
Host	smart-f35bb27a-52d3-44a3-9c3d-2cf38cc6499c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490884701 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_rstmgr_smoketest.490884701
Directory	/workspace/2.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2922198645
Short name	T897
Test name
Test status
Simulation time	4701510648 ps
CPU time	385.03 seconds
Started	Jun 09 03:33:11 PM PDT 24
Finished	Jun 09 03:39:37 PM PDT 24
Peak memory	606924 kb
Host	smart-92ba4239-28e6-42e5-8be2-4470c068645c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922198645 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2922198645
Directory	/workspace/2.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1999370960
Short name	T88
Test name
Test status
Simulation time	2093381184 ps
CPU time	184.6 seconds
Started	Jun 09 03:30:04 PM PDT 24
Finished	Jun 09 03:33:08 PM PDT 24
Peak memory	606276 kb
Host	smart-adde9d81-5425-4461-91ee-fdc529e082d1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999370960 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.1999370960
Directory	/workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.523936935
Short name	T298
Test name
Test status
Simulation time	3184957436 ps
CPU time	306.02 seconds
Started	Jun 09 03:38:32 PM PDT 24
Finished	Jun 09 03:43:39 PM PDT 24
Peak memory	606632 kb
Host	smart-738c64ce-7864-4227-864e-9bc8a0c1c848
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=523936935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.523936935
Directory	/workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2722779919
Short name	T196
Test name
Test status
Simulation time	2350982617 ps
CPU time	306.79 seconds
Started	Jun 09 03:37:59 PM PDT 24
Finished	Jun 09 03:43:06 PM PDT 24
Peak memory	606344 kb
Host	smart-9fd6662a-6aa6-4249-8caa-fcf394eea1ee
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722779919 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.2722779919
Directory	/workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.473529215
Short name	T345
Test name
Test status
Simulation time	4702214740 ps
CPU time	1015.18 seconds
Started	Jun 09 03:32:56 PM PDT 24
Finished	Jun 09 03:49:51 PM PDT 24
Peak memory	606344 kb
Host	smart-7c7226dd-b34e-46b3-ba3e-d419d7013329
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47352 9215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.473529215
Directory	/workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.4091294380
Short name	T736
Test name
Test status
Simulation time	4932680446 ps
CPU time	1013.46 seconds
Started	Jun 09 03:31:29 PM PDT 24
Finished	Jun 09 03:48:23 PM PDT 24
Peak memory	606940 kb
Host	smart-52aefa26-f7cc-4fab-9000-53a0c7068b69
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4091294380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.4091294380
Directory	/workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.448557886
Short name	T427
Test name
Test status
Simulation time	4905043386 ps
CPU time	524.89 seconds
Started	Jun 09 03:38:31 PM PDT 24
Finished	Jun 09 03:47:16 PM PDT 24
Peak memory	617848 kb
Host	smart-ba427d64-7572-4d96-a39d-f934c2ddef34
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448557886 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.448557886
Directory	/workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3041981510
Short name	T954
Test name
Test status
Simulation time	4909622300 ps
CPU time	724.8 seconds
Started	Jun 09 03:35:46 PM PDT 24
Finished	Jun 09 03:47:51 PM PDT 24
Peak memory	616692 kb
Host	smart-bc31a31d-2672-4bd5-848a-87f6f4e0434f
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304198 1510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3041981510
Directory	/workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2023069648
Short name	T840
Test name
Test status
Simulation time	3179898780 ps
CPU time	260.36 seconds
Started	Jun 09 03:40:13 PM PDT 24
Finished	Jun 09 03:44:34 PM PDT 24
Peak memory	606320 kb
Host	smart-bcbe82b3-97ac-48a9-89b0-83bb984d7fb6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023069648 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.2023069648
Directory	/workspace/2.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_irq.3274020643
Short name	T257
Test name
Test status
Simulation time	2877007796 ps
CPU time	291.15 seconds
Started	Jun 09 03:30:39 PM PDT 24
Finished	Jun 09 03:35:30 PM PDT 24
Peak memory	607032 kb
Host	smart-3697f08f-4fec-4bdb-a06d-38d1480de478
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274020643 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.3274020643
Directory	/workspace/2.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3194590484
Short name	T410
Test name
Test status
Simulation time	3340170592 ps
CPU time	308.2 seconds
Started	Jun 09 03:40:07 PM PDT 24
Finished	Jun 09 03:45:16 PM PDT 24
Peak memory	606400 kb
Host	smart-0ed97489-18f0-4adb-be1c-adb406a9851a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194590484 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.3194590484
Directory	/workspace/2.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3007960556
Short name	T160
Test name
Test status
Simulation time	5591804076 ps
CPU time	765.13 seconds
Started	Jun 09 03:36:13 PM PDT 24
Finished	Jun 09 03:48:58 PM PDT 24
Peak memory	608388 kb
Host	smart-cc8277bc-a4e9-4b97-a66c-d3fb2e8f0dbb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30079605 56 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3007960556
Directory	/workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3429615439
Short name	T148
Test name
Test status
Simulation time	3453853083 ps
CPU time	257.92 seconds
Started	Jun 09 03:35:14 PM PDT 24
Finished	Jun 09 03:39:32 PM PDT 24
Peak memory	608760 kb
Host	smart-83a4335f-760d-4bb0-88e1-596a26540b53
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429615 439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3429615439
Directory	/workspace/2.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.4124296927
Short name	T13
Test name
Test status
Simulation time	2808320300 ps
CPU time	286.91 seconds
Started	Jun 09 03:32:17 PM PDT 24
Finished	Jun 09 03:37:05 PM PDT 24
Peak memory	606460 kb
Host	smart-c935a1ae-b63a-4592-a173-0a19b1b495b1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124296927 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.4124296927
Directory	/workspace/2.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2991191132
Short name	T709
Test name
Test status
Simulation time	8570936384 ps
CPU time	1486.08 seconds
Started	Jun 09 03:30:59 PM PDT 24
Finished	Jun 09 03:55:45 PM PDT 24
Peak memory	608400 kb
Host	smart-cfbc1ed2-95b2-4577-a178-a5c1a688792e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991191132 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.2991191132
Directory	/workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3135466587
Short name	T414
Test name
Test status
Simulation time	6785438538 ps
CPU time	878.43 seconds
Started	Jun 09 03:35:05 PM PDT 24
Finished	Jun 09 03:49:44 PM PDT 24
Peak memory	608368 kb
Host	smart-90d692d1-5905-4787-a86a-af1bcd74f195
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135466587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3135466587
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.660472584
Short name	T949
Test name
Test status
Simulation time	7257234376 ps
CPU time	836.73 seconds
Started	Jun 09 03:34:25 PM PDT 24
Finished	Jun 09 03:48:22 PM PDT 24
Peak memory	608388 kb
Host	smart-71caeb0e-851c-411c-95f3-4f97248bf7f4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660472584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_ sram_ret_contents_scramble.660472584
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.4174974200
Short name	T40
Test name
Test status
Simulation time	7351253586 ps
CPU time	856.3 seconds
Started	Jun 09 03:32:10 PM PDT 24
Finished	Jun 09 03:46:26 PM PDT 24
Peak memory	623104 kb
Host	smart-6abb1102-6357-4ef8-91da-5bbd1d71c74d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174974200 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.4174974200
Directory	/workspace/2.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3790878208
Short name	T90
Test name
Test status
Simulation time	5372008409 ps
CPU time	658.24 seconds
Started	Jun 09 03:30:33 PM PDT 24
Finished	Jun 09 03:41:31 PM PDT 24
Peak memory	623968 kb
Host	smart-27dc6a7b-9fae-470d-86dd-c412a477e749
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790878208 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.3790878208
Directory	/workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_tpm.2903313037
Short name	T66
Test name
Test status
Simulation time	2984491534 ps
CPU time	403.69 seconds
Started	Jun 09 03:29:26 PM PDT 24
Finished	Jun 09 03:36:10 PM PDT 24
Peak memory	614704 kb
Host	smart-76ecaf85-21cc-4240-802a-c2ffa6f50fca
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903313037 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.2903313037
Directory	/workspace/2.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3445843239
Short name	T59
Test name
Test status
Simulation time	2952574660 ps
CPU time	317.96 seconds
Started	Jun 09 03:30:02 PM PDT 24
Finished	Jun 09 03:35:21 PM PDT 24
Peak memory	606764 kb
Host	smart-ac0cb7ed-bb3c-4363-be95-9fd80a8474d3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445843239 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3445843239
Directory	/workspace/2.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.5076519
Short name	T303
Test name
Test status
Simulation time	8716503094 ps
CPU time	876.16 seconds
Started	Jun 09 03:35:04 PM PDT 24
Finished	Jun 09 03:49:40 PM PDT 24
Peak memory	607972 kb
Host	smart-21c2f514-accb-45f5-88d5-d8ce2a33bd14
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5076519 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.5076519
Directory	/workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3908793353
Short name	T291
Test name
Test status
Simulation time	4292092966 ps
CPU time	597.85 seconds
Started	Jun 09 03:34:26 PM PDT 24
Finished	Jun 09 03:44:24 PM PDT 24
Peak memory	607636 kb
Host	smart-9cad38af-6d8b-4290-9f5a-4469b62a2fae
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908793353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.3908793353
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3443602695
Short name	T114
Test name
Test status
Simulation time	3985762015 ps
CPU time	690.63 seconds
Started	Jun 09 03:35:23 PM PDT 24
Finished	Jun 09 03:46:55 PM PDT 24
Peak memory	607560 kb
Host	smart-4ee2414c-7084-4e75-a39e-5d8d11395448
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443602695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3443602695
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.804600264
Short name	T999
Test name
Test status
Simulation time	5216940868 ps
CPU time	631.62 seconds
Started	Jun 09 03:39:12 PM PDT 24
Finished	Jun 09 03:49:45 PM PDT 24
Peak memory	607212 kb
Host	smart-1612f999-4978-4f84-919d-797c30711211
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804600264 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.804600264
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1116421888
Short name	T985
Test name
Test status
Simulation time	2839472584 ps
CPU time	289.63 seconds
Started	Jun 09 03:39:47 PM PDT 24
Finished	Jun 09 03:44:37 PM PDT 24
Peak memory	606360 kb
Host	smart-aaed8480-ea89-444b-8315-2001af1547c6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116421888 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1116421888
Directory	/workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.787113894
Short name	T46
Test name
Test status
Simulation time	20416157899 ps
CPU time	3149.76 seconds
Started	Jun 09 03:34:31 PM PDT 24
Finished	Jun 09 04:27:01 PM PDT 24
Peak memory	607292 kb
Host	smart-b29c14a5-86f8-46f3-91f9-cadf059fd654
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787113894 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.787113894
Directory	/workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.529100747
Short name	T226
Test name
Test status
Simulation time	5131368578 ps
CPU time	614.69 seconds
Started	Jun 09 03:31:53 PM PDT 24
Finished	Jun 09 03:42:10 PM PDT 24
Peak memory	611072 kb
Host	smart-cf60c92c-d44c-4f01-96aa-4f29f91c4c65
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529100747 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.529100747
Directory	/workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3655955318
Short name	T225
Test name
Test status
Simulation time	2866686411 ps
CPU time	293.99 seconds
Started	Jun 09 03:31:49 PM PDT 24
Finished	Jun 09 03:36:45 PM PDT 24
Peak memory	610912 kb
Host	smart-87bbff5b-a696-44bd-9f3a-4012633275c6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655955318 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.3655955318
Directory	/workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4093549658
Short name	T64
Test name
Test status
Simulation time	6769616152 ps
CPU time	642.3 seconds
Started	Jun 09 03:33:34 PM PDT 24
Finished	Jun 09 03:44:16 PM PDT 24
Peak memory	607328 kb
Host	smart-1291aee3-e301-4df7-ba85-f4796bdb4298
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093549658 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4093549658
Directory	/workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2945974112
Short name	T679
Test name
Test status
Simulation time	3866933214 ps
CPU time	735.6 seconds
Started	Jun 09 03:29:02 PM PDT 24
Finished	Jun 09 03:41:18 PM PDT 24
Peak memory	617996 kb
Host	smart-0ecbc132-08ae-4ead-b6d4-9e1db73a0492
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2945974112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.2945974112
Directory	/workspace/2.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_smoketest.1170715017
Short name	T587
Test name
Test status
Simulation time	3047754176 ps
CPU time	288.04 seconds
Started	Jun 09 03:42:11 PM PDT 24
Finished	Jun 09 03:47:00 PM PDT 24
Peak memory	607868 kb
Host	smart-05d339d4-2793-48f6-892a-47e555a89ac8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170715017 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.1170715017
Directory	/workspace/2.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx.1831439174
Short name	T365
Test name
Test status
Simulation time	4190247988 ps
CPU time	657.25 seconds
Started	Jun 09 03:28:55 PM PDT 24
Finished	Jun 09 03:39:53 PM PDT 24
Peak memory	615640 kb
Host	smart-571784bf-8c26-41b0-a725-b24cf0c19454
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831439174 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.1831439174
Directory	/workspace/2.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1184017788
Short name	T933
Test name
Test status
Simulation time	8992524077 ps
CPU time	1856.01 seconds
Started	Jun 09 03:29:33 PM PDT 24
Finished	Jun 09 04:00:31 PM PDT 24
Peak memory	619632 kb
Host	smart-caf9ec2f-3e02-4491-9873-7deda7101426
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184017788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.1184017788
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1908491021
Short name	T364
Test name
Test status
Simulation time	7913024256 ps
CPU time	1222.19 seconds
Started	Jun 09 03:30:11 PM PDT 24
Finished	Jun 09 03:50:34 PM PDT 24
Peak memory	619360 kb
Host	smart-e716ac93-4ec7-462e-a5e6-6fa080888365
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908491021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1908491021
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.308390682
Short name	T316
Test name
Test status
Simulation time	4353446032 ps
CPU time	513.36 seconds
Started	Jun 09 03:29:39 PM PDT 24
Finished	Jun 09 03:38:12 PM PDT 24
Peak memory	615628 kb
Host	smart-93daca65-9414-4a87-8ed9-d891a7eee0b6
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308390682 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.308390682
Directory	/workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3969462727
Short name	T165
Test name
Test status
Simulation time	4132308000 ps
CPU time	656.39 seconds
Started	Jun 09 03:28:54 PM PDT 24
Finished	Jun 09 03:39:51 PM PDT 24
Peak memory	615252 kb
Host	smart-7c0e15c1-b141-4f60-9ac6-17e5685c792a
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969462727 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3969462727
Directory	/workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3770006656
Short name	T584
Test name
Test status
Simulation time	4758574172 ps
CPU time	622.56 seconds
Started	Jun 09 03:29:44 PM PDT 24
Finished	Jun 09 03:40:07 PM PDT 24
Peak memory	615528 kb
Host	smart-e70d8129-55bb-4db4-8984-edfe8f6f3d2b
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770006656 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.3770006656
Directory	/workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_dev.3838982230
Short name	T670
Test name
Test status
Simulation time	3593517951 ps
CPU time	313.2 seconds
Started	Jun 09 03:35:29 PM PDT 24
Finished	Jun 09 03:40:42 PM PDT 24
Peak memory	617844 kb
Host	smart-16445aa6-3833-426c-873f-fafabaa55028
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3838982230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.3838982230
Directory	/workspace/2.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_prod.3584552254
Short name	T878
Test name
Test status
Simulation time	5891552188 ps
CPU time	583.83 seconds
Started	Jun 09 03:36:01 PM PDT 24
Finished	Jun 09 03:45:45 PM PDT 24
Peak memory	620056 kb
Host	smart-80ca4b75-e4c3-47b8-9505-b7bd73913e1e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584552254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.3584552254
Directory	/workspace/2.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2701580428
Short name	T409
Test name
Test status
Simulation time	5057101446 ps
CPU time	486.24 seconds
Started	Jun 09 03:34:54 PM PDT 24
Finished	Jun 09 03:43:01 PM PDT 24
Peak memory	619456 kb
Host	smart-5d21c9cf-8a7e-45da-8e5d-9945ee85fe22
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2701580428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.2701580428
Directory	/workspace/2.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_dev.2970021476
Short name	T828
Test name
Test status
Simulation time	13662233015 ps
CPU time	3256.07 seconds
Started	Jun 09 03:45:01 PM PDT 24
Finished	Jun 09 04:39:18 PM PDT 24
Peak memory	607208 kb
Host	smart-d4f0e28b-19ec-4aef-8ac5-ee59cd0b1cc2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970021476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.2970021476
Directory	/workspace/2.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_prod.2947796795
Short name	T690
Test name
Test status
Simulation time	14313104520 ps
CPU time	2837.35 seconds
Started	Jun 09 03:46:37 PM PDT 24
Finished	Jun 09 04:33:55 PM PDT 24
Peak memory	608044 kb
Host	smart-0651fa25-fca5-479e-8058-1e930944d7b4
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947796795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.2947796795
Directory	/workspace/2.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3479782842
Short name	T911
Test name
Test status
Simulation time	14058434024 ps
CPU time	2939 seconds
Started	Jun 09 03:43:44 PM PDT 24
Finished	Jun 09 04:32:44 PM PDT 24
Peak memory	606900 kb
Host	smart-5e7e07ee-d5b1-4e00-8d81-d407f378ce37
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479782842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.3479782842
Directory	/workspace/2.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_rma.4070209315
Short name	T552
Test name
Test status
Simulation time	13850215240 ps
CPU time	3186.02 seconds
Started	Jun 09 03:43:04 PM PDT 24
Finished	Jun 09 04:36:10 PM PDT 24
Peak memory	607220 kb
Host	smart-dd0f00a3-1738-4ea1-95fe-644cb40824cf
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070209315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.4070209315
Directory	/workspace/2.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3572965507
Short name	T895
Test name
Test status
Simulation time	13929856960 ps
CPU time	3674.89 seconds
Started	Jun 09 03:44:07 PM PDT 24
Finished	Jun 09 04:45:23 PM PDT 24
Peak memory	607088 kb
Host	smart-48c30d06-ea06-4ffa-94c4-475a13823cf1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572965507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3572965507
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2431080291
Short name	T972
Test name
Test status
Simulation time	15023050424 ps
CPU time	3001.87 seconds
Started	Jun 09 03:45:11 PM PDT 24
Finished	Jun 09 04:35:14 PM PDT 24
Peak memory	606976 kb
Host	smart-0ea3ee82-80c0-4dea-bfbd-cad254c4c76c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431080291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.2431080291
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.910397199
Short name	T877
Test name
Test status
Simulation time	14854941076 ps
CPU time	3619.63 seconds
Started	Jun 09 03:43:47 PM PDT 24
Finished	Jun 09 04:44:07 PM PDT 24
Peak memory	606748 kb
Host	smart-3ccea20a-f5c1-4e61-a321-2c92d8075fa3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910397199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_ no_meas.910397199
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4160469540
Short name	T770
Test name
Test status
Simulation time	14245907871 ps
CPU time	3372.57 seconds
Started	Jun 09 03:43:15 PM PDT 24
Finished	Jun 09 04:39:28 PM PDT 24
Peak memory	607832 kb
Host	smart-3d02c68b-b801-4162-a721-98e07370c0fa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160469540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.4160469540
Directory	/workspace/2.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/2.rom_e2e_shutdown_output.2512293494
Short name	T275
Test name
Test status
Simulation time	26931971028 ps
CPU time	3078.07 seconds
Started	Jun 09 03:41:38 PM PDT 24
Finished	Jun 09 04:32:56 PM PDT 24
Peak memory	608332 kb
Host	smart-8dc35d6d-6ad0-45a9-bd5e-a91a4fe6e6d4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512293494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.2512293494
Directory	/workspace/2.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/2.rom_e2e_smoke.933778657
Short name	T137
Test name
Test status
Simulation time	14494342376 ps
CPU time	3363.71 seconds
Started	Jun 09 03:40:25 PM PDT 24
Finished	Jun 09 04:36:29 PM PDT 24
Peak memory	606756 kb
Host	smart-d07656f2-a4f7-4cdd-8f3d-2a54784c0d57
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=933778657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.933778657
Directory	/workspace/2.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/2.rom_e2e_static_critical.1864716746
Short name	T4
Test name
Test status
Simulation time	15716683310 ps
CPU time	3239.49 seconds
Started	Jun 09 03:43:31 PM PDT 24
Finished	Jun 09 04:37:31 PM PDT 24
Peak memory	607096 kb
Host	smart-093842c7-812c-4878-9050-dc41aafec9e3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864716746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.1864716746
Directory	/workspace/2.rom_e2e_static_critical/latest

Test location	/workspace/coverage/default/2.rom_keymgr_functest.207501813
Short name	T931
Test name
Test status
Simulation time	4406877936 ps
CPU time	555.17 seconds
Started	Jun 09 03:39:17 PM PDT 24
Finished	Jun 09 03:48:33 PM PDT 24
Peak memory	607880 kb
Host	smart-a3fdacec-764f-4a76-ac45-9deec32c3b59
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207501813 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.207501813
Directory	/workspace/2.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/2.rom_volatile_raw_unlock.3820174111
Short name	T185
Test name
Test status
Simulation time	2935242012 ps
CPU time	118.29 seconds
Started	Jun 09 03:40:26 PM PDT 24
Finished	Jun 09 03:42:26 PM PDT 24
Peak memory	614716 kb
Host	smart-7adcf541-9815-4b82-9132-fc2b1864f45b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820174111 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.3820174111
Directory	/workspace/2.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/22.chip_sw_all_escalation_resets.2950411286
Short name	T597
Test name
Test status
Simulation time	5401767550 ps
CPU time	572.65 seconds
Started	Jun 09 03:42:59 PM PDT 24
Finished	Jun 09 03:52:32 PM PDT 24
Peak memory	647768 kb
Host	smart-48d2786d-3f44-49cc-96e7-61a64ed7c96e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2950411286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.2950411286
Directory	/workspace/22.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/24.chip_sw_all_escalation_resets.3599466476
Short name	T75
Test name
Test status
Simulation time	4366575258 ps
CPU time	660.64 seconds
Started	Jun 09 03:43:18 PM PDT 24
Finished	Jun 09 03:54:19 PM PDT 24
Peak memory	643132 kb
Host	smart-b5a00fdd-1dd9-4c73-94b2-3ccd48ba4117
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3599466476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.3599466476
Directory	/workspace/24.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2838347986
Short name	T342
Test name
Test status
Simulation time	3092779864 ps
CPU time	375.7 seconds
Started	Jun 09 03:43:30 PM PDT 24
Finished	Jun 09 03:49:46 PM PDT 24
Peak memory	646572 kb
Host	smart-c4a149ad-7fdc-407d-8e08-e604d399a018
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838347986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2838347986
Directory	/workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2348489367
Short name	T441
Test name
Test status
Simulation time	5038282472 ps
CPU time	543.62 seconds
Started	Jun 09 03:44:52 PM PDT 24
Finished	Jun 09 03:53:56 PM PDT 24
Peak memory	647788 kb
Host	smart-abe68cdd-e7a4-4476-89fe-789ed30f2a6a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2348489367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2348489367
Directory	/workspace/25.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3231034991
Short name	T384
Test name
Test status
Simulation time	6068203108 ps
CPU time	818.09 seconds
Started	Jun 09 03:43:59 PM PDT 24
Finished	Jun 09 03:57:38 PM PDT 24
Peak memory	643160 kb
Host	smart-5bd78c97-105c-43f1-9fbb-ca7ae2d86ae3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3231034991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3231034991
Directory	/workspace/27.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423039296
Short name	T509
Test name
Test status
Simulation time	3994510660 ps
CPU time	531.06 seconds
Started	Jun 09 03:45:12 PM PDT 24
Finished	Jun 09 03:54:04 PM PDT 24
Peak memory	646420 kb
Host	smart-402866fa-bff1-476c-b9f1-5f60c1659120
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423039296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3423039296
Directory	/workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/29.chip_sw_all_escalation_resets.2195372895
Short name	T976
Test name
Test status
Simulation time	5224646984 ps
CPU time	677.96 seconds
Started	Jun 09 03:43:38 PM PDT 24
Finished	Jun 09 03:54:57 PM PDT 24
Peak memory	643108 kb
Host	smart-b3279b7b-891f-4c25-8243-b7a225ed9bb5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2195372895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.2195372895
Directory	/workspace/29.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1667394311
Short name	T502
Test name
Test status
Simulation time	4248453720 ps
CPU time	583.57 seconds
Started	Jun 09 03:40:24 PM PDT 24
Finished	Jun 09 03:50:08 PM PDT 24
Peak memory	646612 kb
Host	smart-8844d1b6-6b4f-49c3-be8f-7c5ffcf00b04
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667394311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.1667394311
Directory	/workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2495004949
Short name	T625
Test name
Test status
Simulation time	7780974996 ps
CPU time	486.2 seconds
Started	Jun 09 03:40:00 PM PDT 24
Finished	Jun 09 03:48:07 PM PDT 24
Peak memory	607252 kb
Host	smart-efd6a94d-cfd6-410f-bebe-89f674034c52
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2495004949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2495004949
Directory	/workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3906598629
Short name	T253
Test name
Test status
Simulation time	6036972806 ps
CPU time	709.06 seconds
Started	Jun 09 03:40:38 PM PDT 24
Finished	Jun 09 03:52:28 PM PDT 24
Peak memory	607180 kb
Host	smart-465c4d19-96f7-4072-ad87-2c8e3dea5e65
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3906598629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.3906598629
Directory	/workspace/3.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3604785823
Short name	T422
Test name
Test status
Simulation time	4932424981 ps
CPU time	418.33 seconds
Started	Jun 09 03:41:11 PM PDT 24
Finished	Jun 09 03:48:09 PM PDT 24
Peak memory	618596 kb
Host	smart-a84dc911-2dac-45f7-beb6-781faaf94c42
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604785823 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.3604785823
Directory	/workspace/3.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2116461149
Short name	T159
Test name
Test status
Simulation time	7868664640 ps
CPU time	872.64 seconds
Started	Jun 09 03:41:22 PM PDT 24
Finished	Jun 09 03:55:55 PM PDT 24
Peak memory	607336 kb
Host	smart-9328f6bb-c53b-46b0-bdff-5d6d73db087a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21164611 49 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.2116461149
Directory	/workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3426508941
Short name	T589
Test name
Test status
Simulation time	4954335056 ps
CPU time	707.04 seconds
Started	Jun 09 03:40:01 PM PDT 24
Finished	Jun 09 03:51:48 PM PDT 24
Peak memory	617568 kb
Host	smart-54d93ba5-8b63-4970-90df-c91c595c7eef
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3426508941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3426508941
Directory	/workspace/3.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx.1183708771
Short name	T942
Test name
Test status
Simulation time	4455537780 ps
CPU time	567.9 seconds
Started	Jun 09 03:39:27 PM PDT 24
Finished	Jun 09 03:48:55 PM PDT 24
Peak memory	615640 kb
Host	smart-e9840697-8893-49e3-b49c-e196dacaacb7
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183708771 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1183708771
Directory	/workspace/3.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1722602587
Short name	T551
Test name
Test status
Simulation time	8415763520 ps
CPU time	1500.99 seconds
Started	Jun 09 03:41:00 PM PDT 24
Finished	Jun 09 04:06:02 PM PDT 24
Peak memory	619324 kb
Host	smart-bb8a4404-fcab-4f05-8ebe-b8524d88e168
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722602587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.1722602587
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2433665585
Short name	T697
Test name
Test status
Simulation time	13766190915 ps
CPU time	1841.73 seconds
Started	Jun 09 03:39:28 PM PDT 24
Finished	Jun 09 04:10:11 PM PDT 24
Peak memory	619840 kb
Host	smart-da2844fd-23e8-4033-9d22-689bf0e42ae2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433665585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2433665585
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.320960332
Short name	T744
Test name
Test status
Simulation time	3815595058 ps
CPU time	737.97 seconds
Started	Jun 09 03:42:23 PM PDT 24
Finished	Jun 09 03:54:41 PM PDT 24
Peak memory	615296 kb
Host	smart-431859ae-d2b4-423e-adcc-e18d660027a5
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320960332 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.320960332
Directory	/workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.527787361
Short name	T343
Test name
Test status
Simulation time	4152101072 ps
CPU time	670.24 seconds
Started	Jun 09 03:39:39 PM PDT 24
Finished	Jun 09 03:50:49 PM PDT 24
Peak memory	615288 kb
Host	smart-933552a8-ff59-4241-9730-430678a6cd99
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527787361 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.527787361
Directory	/workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2340414012
Short name	T952
Test name
Test status
Simulation time	4215641912 ps
CPU time	598.86 seconds
Started	Jun 09 03:39:54 PM PDT 24
Finished	Jun 09 03:49:54 PM PDT 24
Peak memory	615248 kb
Host	smart-782a5c99-19b0-4469-83c6-cb7c69e89571
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340414012 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2340414012
Directory	/workspace/3.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_dev.2092529107
Short name	T123
Test name
Test status
Simulation time	14590638073 ps
CPU time	1656.16 seconds
Started	Jun 09 03:39:14 PM PDT 24
Finished	Jun 09 04:06:50 PM PDT 24
Peak memory	620088 kb
Host	smart-ea44afb4-9372-490a-90bc-e1897670df99
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2092529107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.2092529107
Directory	/workspace/3.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_prod.2951722120
Short name	T826
Test name
Test status
Simulation time	12747345525 ps
CPU time	1495.89 seconds
Started	Jun 09 03:39:30 PM PDT 24
Finished	Jun 09 04:04:27 PM PDT 24
Peak memory	620064 kb
Host	smart-4383e7c7-a29f-4c6c-af0d-07aeed953d35
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951722120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.2951722120
Directory	/workspace/3.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_rma.4014541639
Short name	T846
Test name
Test status
Simulation time	5177108721 ps
CPU time	424.53 seconds
Started	Jun 09 03:41:49 PM PDT 24
Finished	Jun 09 03:48:54 PM PDT 24
Peak memory	620064 kb
Host	smart-4531eea2-ce9f-4d4f-a4a7-6bd2e2beb548
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014541639 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.4014541639
Directory	/workspace/3.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_testunlock0.3969323462
Short name	T987
Test name
Test status
Simulation time	6303183732 ps
CPU time	743.22 seconds
Started	Jun 09 03:39:21 PM PDT 24
Finished	Jun 09 03:51:45 PM PDT 24
Peak memory	620096 kb
Host	smart-6f745794-4c7a-45bd-8b51-839b6562a45c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969323462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.3969323462
Directory	/workspace/3.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416166225
Short name	T442
Test name
Test status
Simulation time	4265809944 ps
CPU time	407.94 seconds
Started	Jun 09 03:46:27 PM PDT 24
Finished	Jun 09 03:53:15 PM PDT 24
Peak memory	646612 kb
Host	smart-afb43f04-23d4-4ae3-b529-796215218009
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416166225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1416166225
Directory	/workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/30.chip_sw_all_escalation_resets.3569359020
Short name	T519
Test name
Test status
Simulation time	5361471240 ps
CPU time	558.46 seconds
Started	Jun 09 03:46:15 PM PDT 24
Finished	Jun 09 03:55:34 PM PDT 24
Peak memory	647736 kb
Host	smart-ac2007c7-4b74-429b-b2c2-fa7a392d962e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3569359020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.3569359020
Directory	/workspace/30.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2685884816
Short name	T644
Test name
Test status
Simulation time	4473355552 ps
CPU time	394.62 seconds
Started	Jun 09 03:46:26 PM PDT 24
Finished	Jun 09 03:53:01 PM PDT 24
Peak memory	646788 kb
Host	smart-822f9b00-5bc3-4f08-b676-103cdda8f5c7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685884816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2685884816
Directory	/workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3326058106
Short name	T479
Test name
Test status
Simulation time	3953990428 ps
CPU time	550.77 seconds
Started	Jun 09 03:44:43 PM PDT 24
Finished	Jun 09 03:53:54 PM PDT 24
Peak memory	646568 kb
Host	smart-76988a73-aeae-49a5-acb9-79c3365dc910
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326058106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3326058106
Directory	/workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/33.chip_sw_all_escalation_resets.4161139392
Short name	T978
Test name
Test status
Simulation time	5921838790 ps
CPU time	664.25 seconds
Started	Jun 09 03:44:53 PM PDT 24
Finished	Jun 09 03:55:58 PM PDT 24
Peak memory	643180 kb
Host	smart-dbd89d16-ea38-4886-97eb-8d7f5dfa4130
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4161139392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.4161139392
Directory	/workspace/33.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3852581161
Short name	T669
Test name
Test status
Simulation time	3318921482 ps
CPU time	350.53 seconds
Started	Jun 09 03:44:59 PM PDT 24
Finished	Jun 09 03:50:49 PM PDT 24
Peak memory	646764 kb
Host	smart-025dcb25-439f-4bc7-a648-9977e229d218
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852581161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3852581161
Directory	/workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/34.chip_sw_all_escalation_resets.366652482
Short name	T411
Test name
Test status
Simulation time	6019587114 ps
CPU time	721.2 seconds
Started	Jun 09 03:45:21 PM PDT 24
Finished	Jun 09 03:57:23 PM PDT 24
Peak memory	647676 kb
Host	smart-da49c8af-67d3-450a-bbac-05758a93a0e4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 366652482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.366652482
Directory	/workspace/34.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.179372877
Short name	T574
Test name
Test status
Simulation time	3759720036 ps
CPU time	496.25 seconds
Started	Jun 09 03:46:06 PM PDT 24
Finished	Jun 09 03:54:23 PM PDT 24
Peak memory	646564 kb
Host	smart-53e7e7cb-758a-452f-a8b4-bec63fa72840
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179372877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_s w_alert_handler_lpg_sleep_mode_alerts.179372877
Directory	/workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/36.chip_sw_all_escalation_resets.688372856
Short name	T1000
Test name
Test status
Simulation time	4941146696 ps
CPU time	571.24 seconds
Started	Jun 09 03:45:46 PM PDT 24
Finished	Jun 09 03:55:18 PM PDT 24
Peak memory	647724 kb
Host	smart-05fa72fc-8936-493a-91e5-3c795b8a6dc2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 688372856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.688372856
Directory	/workspace/36.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127361489
Short name	T499
Test name
Test status
Simulation time	3028679084 ps
CPU time	315.83 seconds
Started	Jun 09 03:45:32 PM PDT 24
Finished	Jun 09 03:50:48 PM PDT 24
Peak memory	646604 kb
Host	smart-d40ff057-edcd-4b49-a5dc-449190c68f27
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127361489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2127361489
Directory	/workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/38.chip_sw_all_escalation_resets.2306048903
Short name	T469
Test name
Test status
Simulation time	4266531744 ps
CPU time	587.95 seconds
Started	Jun 09 03:45:19 PM PDT 24
Finished	Jun 09 03:55:08 PM PDT 24
Peak memory	647364 kb
Host	smart-a77b733c-d812-4f8f-87b2-38a9d159e621
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2306048903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.2306048903
Directory	/workspace/38.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4029429983
Short name	T458
Test name
Test status
Simulation time	3796730280 ps
CPU time	356.08 seconds
Started	Jun 09 03:45:12 PM PDT 24
Finished	Jun 09 03:51:08 PM PDT 24
Peak memory	646324 kb
Host	smart-72728d9d-1928-4a04-aaec-12a76c1212a6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029429983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4029429983
Directory	/workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2316863800
Short name	T741
Test name
Test status
Simulation time	4720171118 ps
CPU time	569.28 seconds
Started	Jun 09 03:42:35 PM PDT 24
Finished	Jun 09 03:52:05 PM PDT 24
Peak memory	608428 kb
Host	smart-ddd97b81-50f9-4a84-a7b7-4d4aa75306ed
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2316863800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2316863800
Directory	/workspace/4.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1572869367
Short name	T569
Test name
Test status
Simulation time	6690731082 ps
CPU time	382.36 seconds
Started	Jun 09 03:39:54 PM PDT 24
Finished	Jun 09 03:46:17 PM PDT 24
Peak memory	608188 kb
Host	smart-d96efa85-716e-4830-9e94-5409ef14d756
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1572869367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1572869367
Directory	/workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2451847423
Short name	T262
Test name
Test status
Simulation time	22636680310 ps
CPU time	4651.1 seconds
Started	Jun 09 03:42:28 PM PDT 24
Finished	Jun 09 05:00:00 PM PDT 24
Peak memory	607612 kb
Host	smart-53cb1641-3a75-4741-840b-555cf538f1e8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451847423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.2451847423
Directory	/workspace/4.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.757708958
Short name	T751
Test name
Test status
Simulation time	6726656328 ps
CPU time	790.42 seconds
Started	Jun 09 03:42:38 PM PDT 24
Finished	Jun 09 03:55:49 PM PDT 24
Peak memory	608524 kb
Host	smart-a098aa86-3849-4f10-923f-8c4ff37266e6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=757708958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.757708958
Directory	/workspace/4.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2848019663
Short name	T841
Test name
Test status
Simulation time	14453965139 ps
CPU time	1287.16 seconds
Started	Jun 09 03:41:16 PM PDT 24
Finished	Jun 09 04:02:43 PM PDT 24
Peak memory	617976 kb
Host	smart-f8752df4-7946-49a4-9361-5a37d1c9c74f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848019663 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.2848019663
Directory	/workspace/4.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4240266399
Short name	T162
Test name
Test status
Simulation time	6017920350 ps
CPU time	628.01 seconds
Started	Jun 09 03:41:01 PM PDT 24
Finished	Jun 09 03:51:29 PM PDT 24
Peak memory	608324 kb
Host	smart-0dda27bf-4713-4b49-92f0-b410b4456e2e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42402663 99 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.4240266399
Directory	/workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2927796007
Short name	T418
Test name
Test status
Simulation time	8164181380 ps
CPU time	1437.97 seconds
Started	Jun 09 03:42:20 PM PDT 24
Finished	Jun 09 04:06:19 PM PDT 24
Peak memory	617228 kb
Host	smart-855506b7-bae1-4afb-bb99-fda138eaac76
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2927796007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2927796007
Directory	/workspace/4.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx.1580994610
Short name	T948
Test name
Test status
Simulation time	4510791000 ps
CPU time	588.69 seconds
Started	Jun 09 03:41:09 PM PDT 24
Finished	Jun 09 03:50:59 PM PDT 24
Peak memory	615720 kb
Host	smart-3a99a3ee-3bb5-42a9-88a2-3cdfc1032886
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580994610 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.1580994610
Directory	/workspace/4.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2479340671
Short name	T641
Test name
Test status
Simulation time	7770212404 ps
CPU time	1791.55 seconds
Started	Jun 09 03:42:24 PM PDT 24
Finished	Jun 09 04:12:16 PM PDT 24
Peak memory	619332 kb
Host	smart-332cad8a-8031-485e-87d7-945af05f1419
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479340671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.2479340671
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3946754839
Short name	T902
Test name
Test status
Simulation time	8314601466 ps
CPU time	1194.89 seconds
Started	Jun 09 03:42:08 PM PDT 24
Finished	Jun 09 04:02:04 PM PDT 24
Peak memory	619292 kb
Host	smart-07554479-b349-44e3-b210-72a496989094
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946754839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3946754839
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2617169905
Short name	T921
Test name
Test status
Simulation time	3808250478 ps
CPU time	718.38 seconds
Started	Jun 09 03:40:57 PM PDT 24
Finished	Jun 09 03:52:56 PM PDT 24
Peak memory	615608 kb
Host	smart-74e56b2a-c370-47a9-99f4-52cf7396d2bd
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617169905 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.2617169905
Directory	/workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.824494799
Short name	T682
Test name
Test status
Simulation time	4434179780 ps
CPU time	550.49 seconds
Started	Jun 09 03:41:18 PM PDT 24
Finished	Jun 09 03:50:29 PM PDT 24
Peak memory	615536 kb
Host	smart-6ba3a8ee-420b-4c37-99c7-52b890e53478
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824494799 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.824494799
Directory	/workspace/4.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3563513648
Short name	T701
Test name
Test status
Simulation time	4046348088 ps
CPU time	618.79 seconds
Started	Jun 09 03:40:49 PM PDT 24
Finished	Jun 09 03:51:08 PM PDT 24
Peak memory	615228 kb
Host	smart-507628dc-482e-42a7-913e-927cd5339d4a
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563513648 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.3563513648
Directory	/workspace/4.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_prod.4008030826
Short name	T124
Test name
Test status
Simulation time	8610399085 ps
CPU time	956.13 seconds
Started	Jun 09 03:40:42 PM PDT 24
Finished	Jun 09 03:56:38 PM PDT 24
Peak memory	621836 kb
Host	smart-f6e43213-ee66-4ed4-a908-fbdfd380ea14
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008030826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.4008030826
Directory	/workspace/4.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_rma.1875952240
Short name	T118
Test name
Test status
Simulation time	2419693097 ps
CPU time	180.03 seconds
Started	Jun 09 03:41:51 PM PDT 24
Finished	Jun 09 03:44:52 PM PDT 24
Peak memory	619712 kb
Host	smart-07faae25-e4ab-4699-98d7-4534979a56fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875952240 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.1875952240
Directory	/workspace/4.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_testunlock0.3957720015
Short name	T643
Test name
Test status
Simulation time	5235901936 ps
CPU time	495.07 seconds
Started	Jun 09 03:41:20 PM PDT 24
Finished	Jun 09 03:49:36 PM PDT 24
Peak memory	620008 kb
Host	smart-c7a49d06-3772-4b73-aed5-f29c99cf9647
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3957720015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3957720015
Directory	/workspace/4.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/40.chip_sw_all_escalation_resets.209669792
Short name	T488
Test name
Test status
Simulation time	6203120104 ps
CPU time	736.44 seconds
Started	Jun 09 03:47:23 PM PDT 24
Finished	Jun 09 03:59:40 PM PDT 24
Peak memory	643188 kb
Host	smart-c1503498-22ec-413c-b4ca-2330b8bfaafc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 209669792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.209669792
Directory	/workspace/40.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.891569978
Short name	T489
Test name
Test status
Simulation time	3506178184 ps
CPU time	533.81 seconds
Started	Jun 09 03:45:36 PM PDT 24
Finished	Jun 09 03:54:30 PM PDT 24
Peak memory	646220 kb
Host	smart-ae60c397-6861-4d2c-a52e-2ee774bab449
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891569978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_s w_alert_handler_lpg_sleep_mode_alerts.891569978
Directory	/workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3432608077
Short name	T526
Test name
Test status
Simulation time	3432785724 ps
CPU time	361.41 seconds
Started	Jun 09 03:46:11 PM PDT 24
Finished	Jun 09 03:52:13 PM PDT 24
Peak memory	646268 kb
Host	smart-fdf54e06-9e81-476a-9a16-c12de40b0422
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432608077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3432608077
Directory	/workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/44.chip_sw_all_escalation_resets.1345132203
Short name	T487
Test name
Test status
Simulation time	4987848694 ps
CPU time	720.82 seconds
Started	Jun 09 03:47:13 PM PDT 24
Finished	Jun 09 03:59:14 PM PDT 24
Peak memory	647820 kb
Host	smart-c9f7e67f-ba72-41b8-9723-fc5aff63ee5f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1345132203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1345132203
Directory	/workspace/44.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2480688520
Short name	T651
Test name
Test status
Simulation time	4690132720 ps
CPU time	678.23 seconds
Started	Jun 09 03:46:48 PM PDT 24
Finished	Jun 09 03:58:07 PM PDT 24
Peak memory	647788 kb
Host	smart-f6da99f1-9ba9-4183-a5ab-0b8fa21357bd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2480688520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.2480688520
Directory	/workspace/45.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/46.chip_sw_all_escalation_resets.2208883562
Short name	T385
Test name
Test status
Simulation time	5190773540 ps
CPU time	659.95 seconds
Started	Jun 09 03:46:17 PM PDT 24
Finished	Jun 09 03:57:17 PM PDT 24
Peak memory	647736 kb
Host	smart-1a48f781-9a75-47ec-98c1-904e7b7debfa
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2208883562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.2208883562
Directory	/workspace/46.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1632982748
Short name	T133
Test name
Test status
Simulation time	4325556264 ps
CPU time	362.3 seconds
Started	Jun 09 03:46:40 PM PDT 24
Finished	Jun 09 03:52:43 PM PDT 24
Peak memory	647332 kb
Host	smart-4ee76cc0-1833-46bd-a0ad-333f91d4811d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632982748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1632982748
Directory	/workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2040175938
Short name	T527
Test name
Test status
Simulation time	4367973646 ps
CPU time	521.92 seconds
Started	Jun 09 03:45:43 PM PDT 24
Finished	Jun 09 03:54:25 PM PDT 24
Peak memory	643208 kb
Host	smart-e82353ad-fa5f-42a2-9ade-a11e0432d6f4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2040175938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2040175938
Directory	/workspace/47.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3379176044
Short name	T450
Test name
Test status
Simulation time	3747903730 ps
CPU time	362.5 seconds
Started	Jun 09 03:46:41 PM PDT 24
Finished	Jun 09 03:52:44 PM PDT 24
Peak memory	646488 kb
Host	smart-44853ba8-6858-437b-8cab-b59202845b07
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379176044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3379176044
Directory	/workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/48.chip_sw_all_escalation_resets.4232841799
Short name	T496
Test name
Test status
Simulation time	4902410344 ps
CPU time	488.32 seconds
Started	Jun 09 03:46:37 PM PDT 24
Finished	Jun 09 03:54:46 PM PDT 24
Peak memory	647840 kb
Host	smart-bdf8487f-8cd0-41d7-950a-40e607e902c7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4232841799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.4232841799
Directory	/workspace/48.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3357371119
Short name	T145
Test name
Test status
Simulation time	3313640750 ps
CPU time	312.48 seconds
Started	Jun 09 03:46:06 PM PDT 24
Finished	Jun 09 03:51:18 PM PDT 24
Peak memory	646672 kb
Host	smart-1b1a6b9c-af22-46da-beb1-39d621597cea
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357371119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3357371119
Directory	/workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3864043189
Short name	T504
Test name
Test status
Simulation time	5816715882 ps
CPU time	656.02 seconds
Started	Jun 09 03:46:29 PM PDT 24
Finished	Jun 09 03:57:25 PM PDT 24
Peak memory	643236 kb
Host	smart-0ddaa05f-f540-440d-a188-292bc1b643ff
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3864043189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.3864043189
Directory	/workspace/49.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2085311215
Short name	T463
Test name
Test status
Simulation time	3951942330 ps
CPU time	506.63 seconds
Started	Jun 09 03:40:23 PM PDT 24
Finished	Jun 09 03:48:50 PM PDT 24
Peak memory	646236 kb
Host	smart-0eeca4c9-58df-444f-932b-765772ecf6f5
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085311215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.2085311215
Directory	/workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/5.chip_sw_all_escalation_resets.781823856
Short name	T247
Test name
Test status
Simulation time	4488692660 ps
CPU time	552.71 seconds
Started	Jun 09 03:41:53 PM PDT 24
Finished	Jun 09 03:51:06 PM PDT 24
Peak memory	643120 kb
Host	smart-92997ba0-64de-4136-a580-195636e79991
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 781823856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.781823856
Directory	/workspace/5.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2972812875
Short name	T894
Test name
Test status
Simulation time	24123546784 ps
CPU time	4981.8 seconds
Started	Jun 09 03:41:14 PM PDT 24
Finished	Jun 09 05:04:16 PM PDT 24
Peak memory	607144 kb
Host	smart-a5dad5c8-dc34-409d-a2e2-54855054744a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972812875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.2972812875
Directory	/workspace/5.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.427801783
Short name	T252
Test name
Test status
Simulation time	6102116066 ps
CPU time	848.81 seconds
Started	Jun 09 03:40:32 PM PDT 24
Finished	Jun 09 03:54:41 PM PDT 24
Peak memory	608472 kb
Host	smart-7da2fa3f-541b-4fa7-aa8e-8884889252d0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=427801783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.427801783
Directory	/workspace/5.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.4083167551
Short name	T592
Test name
Test status
Simulation time	12885987417 ps
CPU time	827.03 seconds
Started	Jun 09 03:40:06 PM PDT 24
Finished	Jun 09 03:53:53 PM PDT 24
Peak memory	617952 kb
Host	smart-24355da6-21c2-418a-b19a-183d9703ad0c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083167551 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.4083167551
Directory	/workspace/5.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1559383184
Short name	T269
Test name
Test status
Simulation time	3889709032 ps
CPU time	553.52 seconds
Started	Jun 09 03:40:14 PM PDT 24
Finished	Jun 09 03:49:29 PM PDT 24
Peak memory	617260 kb
Host	smart-280ffe70-f36e-47e7-8a68-4dac651d741f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1559383184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.1559383184
Directory	/workspace/5.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.590784413
Short name	T270
Test name
Test status
Simulation time	4542839936 ps
CPU time	497.35 seconds
Started	Jun 09 03:47:25 PM PDT 24
Finished	Jun 09 03:55:43 PM PDT 24
Peak memory	646592 kb
Host	smart-99909d55-3517-437a-a65f-2ba23410e615
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590784413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_s w_alert_handler_lpg_sleep_mode_alerts.590784413
Directory	/workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/50.chip_sw_all_escalation_resets.126928794
Short name	T446
Test name
Test status
Simulation time	4230754536 ps
CPU time	563.44 seconds
Started	Jun 09 03:45:53 PM PDT 24
Finished	Jun 09 03:55:17 PM PDT 24
Peak memory	647536 kb
Host	smart-5b352f01-746f-46a9-9eb9-0ee749d66ac7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 126928794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.126928794
Directory	/workspace/50.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3035221998
Short name	T81
Test name
Test status
Simulation time	5476201928 ps
CPU time	722.55 seconds
Started	Jun 09 03:47:25 PM PDT 24
Finished	Jun 09 03:59:28 PM PDT 24
Peak memory	648004 kb
Host	smart-ad842af3-8d06-4167-9790-6f74bfabcd6d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3035221998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3035221998
Directory	/workspace/51.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.499503076
Short name	T903
Test name
Test status
Simulation time	4114511908 ps
CPU time	443.54 seconds
Started	Jun 09 03:46:17 PM PDT 24
Finished	Jun 09 03:53:41 PM PDT 24
Peak memory	646404 kb
Host	smart-96dd43f6-6f3f-472f-9bd9-6a63d8442c2f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499503076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_s w_alert_handler_lpg_sleep_mode_alerts.499503076
Directory	/workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1796264285
Short name	T456
Test name
Test status
Simulation time	4333633512 ps
CPU time	340.59 seconds
Started	Jun 09 03:46:51 PM PDT 24
Finished	Jun 09 03:52:32 PM PDT 24
Peak memory	646720 kb
Host	smart-61ae2092-f171-4396-b088-9d025a4849b6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796264285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1796264285
Directory	/workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/53.chip_sw_all_escalation_resets.2011746154
Short name	T186
Test name
Test status
Simulation time	4840289446 ps
CPU time	585.22 seconds
Started	Jun 09 03:47:47 PM PDT 24
Finished	Jun 09 03:57:33 PM PDT 24
Peak memory	617236 kb
Host	smart-24dae405-296c-4155-923f-b9849f0c5aa7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2011746154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.2011746154
Directory	/workspace/53.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.672438665
Short name	T437
Test name
Test status
Simulation time	3206430080 ps
CPU time	397.37 seconds
Started	Jun 09 03:46:21 PM PDT 24
Finished	Jun 09 03:52:58 PM PDT 24
Peak memory	646492 kb
Host	smart-3e8ebd81-6c53-452d-b6a6-7d83d3a05662
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672438665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_s w_alert_handler_lpg_sleep_mode_alerts.672438665
Directory	/workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/54.chip_sw_all_escalation_resets.3315748558
Short name	T73
Test name
Test status
Simulation time	5164787892 ps
CPU time	763.75 seconds
Started	Jun 09 03:47:13 PM PDT 24
Finished	Jun 09 03:59:58 PM PDT 24
Peak memory	608360 kb
Host	smart-0c9d9fc5-f9cd-4e8f-9d86-7003da6fc790
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3315748558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.3315748558
Directory	/workspace/54.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3697005267
Short name	T393
Test name
Test status
Simulation time	3508433576 ps
CPU time	401.07 seconds
Started	Jun 09 03:47:58 PM PDT 24
Finished	Jun 09 03:54:39 PM PDT 24
Peak memory	646368 kb
Host	smart-3915b4f9-472d-4db9-9003-11499c10d739
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697005267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3697005267
Directory	/workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/55.chip_sw_all_escalation_resets.2973391715
Short name	T381
Test name
Test status
Simulation time	5089173134 ps
CPU time	755.17 seconds
Started	Jun 09 03:46:47 PM PDT 24
Finished	Jun 09 03:59:22 PM PDT 24
Peak memory	643112 kb
Host	smart-890ef75f-4de5-4f92-aa1b-76dbb06334ac
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2973391715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.2973391715
Directory	/workspace/55.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3115822527
Short name	T484
Test name
Test status
Simulation time	3482633176 ps
CPU time	318.43 seconds
Started	Jun 09 03:48:07 PM PDT 24
Finished	Jun 09 03:53:26 PM PDT 24
Peak memory	646520 kb
Host	smart-44a4dd10-7365-4789-80e9-1d718734c713
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115822527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3115822527
Directory	/workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/57.chip_sw_all_escalation_resets.2623951102
Short name	T310
Test name
Test status
Simulation time	5092489224 ps
CPU time	543.8 seconds
Started	Jun 09 03:47:30 PM PDT 24
Finished	Jun 09 03:56:34 PM PDT 24
Peak memory	608380 kb
Host	smart-5f0453fc-5800-425b-af10-c24f30b1ad72
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2623951102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.2623951102
Directory	/workspace/57.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2201471196
Short name	T240
Test name
Test status
Simulation time	3008435924 ps
CPU time	325.98 seconds
Started	Jun 09 03:47:17 PM PDT 24
Finished	Jun 09 03:52:44 PM PDT 24
Peak memory	646776 kb
Host	smart-be70072e-f9aa-4381-a482-db7938cbc8b3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201471196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2201471196
Directory	/workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1358030738
Short name	T347
Test name
Test status
Simulation time	5679696552 ps
CPU time	625.56 seconds
Started	Jun 09 03:47:25 PM PDT 24
Finished	Jun 09 03:57:50 PM PDT 24
Peak memory	643168 kb
Host	smart-78cdffb7-cbaf-42ad-9333-9a18aa74f3f1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1358030738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1358030738
Directory	/workspace/58.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1969855333
Short name	T485
Test name
Test status
Simulation time	6159956350 ps
CPU time	771.46 seconds
Started	Jun 09 03:49:05 PM PDT 24
Finished	Jun 09 04:01:57 PM PDT 24
Peak memory	647888 kb
Host	smart-9ae3bf1d-7dcc-402d-a30e-d901e4012529
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1969855333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.1969855333
Directory	/workspace/59.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3989197752
Short name	T474
Test name
Test status
Simulation time	3440024438 ps
CPU time	389.5 seconds
Started	Jun 09 03:40:51 PM PDT 24
Finished	Jun 09 03:47:21 PM PDT 24
Peak memory	646248 kb
Host	smart-ff88c3a5-3cd7-424e-b50f-0d352f5c15cb
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989197752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3989197752
Directory	/workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/6.chip_sw_all_escalation_resets.1848601622
Short name	T348
Test name
Test status
Simulation time	6107539560 ps
CPU time	789.39 seconds
Started	Jun 09 03:40:51 PM PDT 24
Finished	Jun 09 03:54:01 PM PDT 24
Peak memory	647904 kb
Host	smart-eaf94f25-ce52-4dfe-8162-a0893442088b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1848601622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1848601622
Directory	/workspace/6.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4068138605
Short name	T596
Test name
Test status
Simulation time	17145030600 ps
CPU time	3611.97 seconds
Started	Jun 09 03:42:58 PM PDT 24
Finished	Jun 09 04:43:10 PM PDT 24
Peak memory	607148 kb
Host	smart-43e262a4-3df5-40af-a841-0ad57b741291
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068138605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.4068138605
Directory	/workspace/6.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3027803365
Short name	T838
Test name
Test status
Simulation time	4517608609 ps
CPU time	476.14 seconds
Started	Jun 09 03:42:17 PM PDT 24
Finished	Jun 09 03:50:14 PM PDT 24
Peak memory	617904 kb
Host	smart-b8620335-a293-4b5c-9c82-3c48f83967af
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027803365 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.3027803365
Directory	/workspace/6.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3170698731
Short name	T578
Test name
Test status
Simulation time	3205752556 ps
CPU time	496.6 seconds
Started	Jun 09 03:41:03 PM PDT 24
Finished	Jun 09 03:49:20 PM PDT 24
Peak memory	617304 kb
Host	smart-e650b1b5-4837-43ae-bc89-6cc901e2531d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3170698731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.3170698731
Directory	/workspace/6.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2158561925
Short name	T525
Test name
Test status
Simulation time	3982274520 ps
CPU time	483.27 seconds
Started	Jun 09 03:48:13 PM PDT 24
Finished	Jun 09 03:56:17 PM PDT 24
Peak memory	646104 kb
Host	smart-8a086083-b4f6-4268-9652-6141f2579f67
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158561925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2158561925
Directory	/workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/60.chip_sw_all_escalation_resets.696142526
Short name	T324
Test name
Test status
Simulation time	4968385586 ps
CPU time	862.75 seconds
Started	Jun 09 03:47:04 PM PDT 24
Finished	Jun 09 04:01:28 PM PDT 24
Peak memory	647788 kb
Host	smart-23b20ebe-3198-4e88-b8c5-dfd5e7cb2a30
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 696142526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.696142526
Directory	/workspace/60.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/61.chip_sw_all_escalation_resets.454519771
Short name	T475
Test name
Test status
Simulation time	4832200472 ps
CPU time	617.03 seconds
Started	Jun 09 03:46:40 PM PDT 24
Finished	Jun 09 03:56:58 PM PDT 24
Peak memory	643396 kb
Host	smart-7b1db550-2864-4105-b412-c2032184234f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 454519771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.454519771
Directory	/workspace/61.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/62.chip_sw_all_escalation_resets.2259968851
Short name	T468
Test name
Test status
Simulation time	5878318308 ps
CPU time	632.6 seconds
Started	Jun 09 03:48:56 PM PDT 24
Finished	Jun 09 03:59:29 PM PDT 24
Peak memory	647788 kb
Host	smart-f8e4e643-c0ea-4b93-bf40-f6e5be627f29
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2259968851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.2259968851
Directory	/workspace/62.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1760815313
Short name	T451
Test name
Test status
Simulation time	3573666182 ps
CPU time	365.86 seconds
Started	Jun 09 03:48:01 PM PDT 24
Finished	Jun 09 03:54:07 PM PDT 24
Peak memory	646476 kb
Host	smart-46397fbf-3a18-49f1-b4bb-f938d9f3b6a4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760815313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1760815313
Directory	/workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.451820383
Short name	T925
Test name
Test status
Simulation time	3393635956 ps
CPU time	385.77 seconds
Started	Jun 09 03:48:46 PM PDT 24
Finished	Jun 09 03:55:12 PM PDT 24
Peak memory	646292 kb
Host	smart-747f4dde-a7df-478b-86ad-e58a1018920a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451820383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_s w_alert_handler_lpg_sleep_mode_alerts.451820383
Directory	/workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/64.chip_sw_all_escalation_resets.3565498765
Short name	T374
Test name
Test status
Simulation time	6420984920 ps
CPU time	589.09 seconds
Started	Jun 09 03:47:41 PM PDT 24
Finished	Jun 09 03:57:31 PM PDT 24
Peak memory	643432 kb
Host	smart-b5aec8c5-baef-4953-9030-b4b3854a16fd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3565498765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3565498765
Directory	/workspace/64.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/65.chip_sw_all_escalation_resets.1897763136
Short name	T323
Test name
Test status
Simulation time	6044340136 ps
CPU time	625.6 seconds
Started	Jun 09 03:48:26 PM PDT 24
Finished	Jun 09 03:58:52 PM PDT 24
Peak memory	643116 kb
Host	smart-be701572-6e3d-4330-b1f7-2b28b635c6cb
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1897763136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.1897763136
Directory	/workspace/65.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.222021293
Short name	T421
Test name
Test status
Simulation time	3847513960 ps
CPU time	360.16 seconds
Started	Jun 09 03:50:05 PM PDT 24
Finished	Jun 09 03:56:06 PM PDT 24
Peak memory	616184 kb
Host	smart-d0fbb638-e46d-4fec-8dc9-c148bf7558b7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222021293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_s w_alert_handler_lpg_sleep_mode_alerts.222021293
Directory	/workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/66.chip_sw_all_escalation_resets.1893537157
Short name	T498
Test name
Test status
Simulation time	5154366622 ps
CPU time	604.39 seconds
Started	Jun 09 03:48:15 PM PDT 24
Finished	Jun 09 03:58:20 PM PDT 24
Peak memory	647816 kb
Host	smart-2a5bf234-bbb6-4a82-8058-2eed1191b309
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1893537157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.1893537157
Directory	/workspace/66.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/67.chip_sw_all_escalation_resets.4094645089
Short name	T787
Test name
Test status
Simulation time	6556343720 ps
CPU time	670 seconds
Started	Jun 09 03:48:45 PM PDT 24
Finished	Jun 09 03:59:55 PM PDT 24
Peak memory	647840 kb
Host	smart-81dfc812-ed48-493b-843f-86d0796a0ab6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4094645089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.4094645089
Directory	/workspace/67.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2495567478
Short name	T272
Test name
Test status
Simulation time	4289716918 ps
CPU time	452.62 seconds
Started	Jun 09 03:48:11 PM PDT 24
Finished	Jun 09 03:55:44 PM PDT 24
Peak memory	646512 kb
Host	smart-e7adcb30-61ad-4ff8-bb46-a90aaf5ab081
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495567478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2495567478
Directory	/workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/68.chip_sw_all_escalation_resets.3296473028
Short name	T631
Test name
Test status
Simulation time	5432295544 ps
CPU time	503.41 seconds
Started	Jun 09 03:47:16 PM PDT 24
Finished	Jun 09 03:55:40 PM PDT 24
Peak memory	614828 kb
Host	smart-b781225a-ff44-4be9-8f0e-98589c409b6a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3296473028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.3296473028
Directory	/workspace/68.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/69.chip_sw_all_escalation_resets.71993270
Short name	T440
Test name
Test status
Simulation time	6352329960 ps
CPU time	682.29 seconds
Started	Jun 09 03:49:00 PM PDT 24
Finished	Jun 09 04:00:23 PM PDT 24
Peak memory	643076 kb
Host	smart-e38b5957-4c0e-4b3a-9729-59a9d5b3da47
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 71993270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.71993270
Directory	/workspace/69.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2535401060
Short name	T135
Test name
Test status
Simulation time	4053738712 ps
CPU time	464.12 seconds
Started	Jun 09 03:42:05 PM PDT 24
Finished	Jun 09 03:49:50 PM PDT 24
Peak memory	647240 kb
Host	smart-c0cf06e9-c614-43c2-9fe9-54ba8539fb52
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535401060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.2535401060
Directory	/workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.227452083
Short name	T795
Test name
Test status
Simulation time	20889042376 ps
CPU time	4210.95 seconds
Started	Jun 09 03:42:52 PM PDT 24
Finished	Jun 09 04:53:04 PM PDT 24
Peak memory	607616 kb
Host	smart-c2a20389-3854-45ef-b61f-c7cb1a20f170
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227452083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.227452083
Directory	/workspace/7.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2520938131
Short name	T576
Test name
Test status
Simulation time	6813381824 ps
CPU time	629.74 seconds
Started	Jun 09 03:41:02 PM PDT 24
Finished	Jun 09 03:51:33 PM PDT 24
Peak memory	617888 kb
Host	smart-2eb529c6-7abe-4d9e-8b1a-ea49cc4c0560
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520938131 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2520938131
Directory	/workspace/7.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2096412683
Short name	T630
Test name
Test status
Simulation time	13313280332 ps
CPU time	2709.69 seconds
Started	Jun 09 03:41:11 PM PDT 24
Finished	Jun 09 04:26:21 PM PDT 24
Peak memory	617576 kb
Host	smart-37556cdc-9a91-4753-9c3d-75f3e78c3f3c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2096412683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2096412683
Directory	/workspace/7.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2845287702
Short name	T521
Test name
Test status
Simulation time	3312832808 ps
CPU time	461.93 seconds
Started	Jun 09 03:50:21 PM PDT 24
Finished	Jun 09 03:58:04 PM PDT 24
Peak memory	646548 kb
Host	smart-28931c4b-5b18-425f-a700-2bf38adb4679
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845287702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2845287702
Directory	/workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/70.chip_sw_all_escalation_resets.3706112018
Short name	T403
Test name
Test status
Simulation time	6067447592 ps
CPU time	525.98 seconds
Started	Jun 09 03:47:36 PM PDT 24
Finished	Jun 09 03:56:23 PM PDT 24
Peak memory	617268 kb
Host	smart-1dcfa5dc-8a65-49e0-a40c-faa08e1d5320
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3706112018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.3706112018
Directory	/workspace/70.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4003375993
Short name	T753
Test name
Test status
Simulation time	3570514712 ps
CPU time	429.11 seconds
Started	Jun 09 03:48:28 PM PDT 24
Finished	Jun 09 03:55:38 PM PDT 24
Peak memory	646556 kb
Host	smart-841faa30-03f7-407f-9f01-daf61a8991d1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003375993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4003375993
Directory	/workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/71.chip_sw_all_escalation_resets.2698083973
Short name	T349
Test name
Test status
Simulation time	5347212300 ps
CPU time	947.18 seconds
Started	Jun 09 03:47:52 PM PDT 24
Finished	Jun 09 04:03:40 PM PDT 24
Peak memory	643140 kb
Host	smart-5608878c-9955-47cb-8c5f-a356ac821d58
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2698083973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2698083973
Directory	/workspace/71.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2577946881
Short name	T483
Test name
Test status
Simulation time	3947953392 ps
CPU time	437.28 seconds
Started	Jun 09 03:50:22 PM PDT 24
Finished	Jun 09 03:57:40 PM PDT 24
Peak memory	646596 kb
Host	smart-2d6b2408-f14a-4576-8391-e6b37a5fe1a7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577946881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2577946881
Directory	/workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2132696013
Short name	T470
Test name
Test status
Simulation time	3561418110 ps
CPU time	370.8 seconds
Started	Jun 09 03:47:44 PM PDT 24
Finished	Jun 09 03:53:55 PM PDT 24
Peak memory	646192 kb
Host	smart-a660db98-fae1-402a-a160-f1c00397cd65
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132696013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2132696013
Directory	/workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/74.chip_sw_all_escalation_resets.3703085482
Short name	T397
Test name
Test status
Simulation time	4802824660 ps
CPU time	444.91 seconds
Started	Jun 09 03:48:03 PM PDT 24
Finished	Jun 09 03:55:28 PM PDT 24
Peak memory	647728 kb
Host	smart-26571976-a023-4400-8469-37d9e855f965
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3703085482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.3703085482
Directory	/workspace/74.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3382145726
Short name	T375
Test name
Test status
Simulation time	4521301560 ps
CPU time	383.57 seconds
Started	Jun 09 03:49:04 PM PDT 24
Finished	Jun 09 03:55:28 PM PDT 24
Peak memory	646644 kb
Host	smart-d916d13d-3089-4a4e-bda8-ecf4b9d08686
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382145726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3382145726
Directory	/workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3085489949
Short name	T444
Test name
Test status
Simulation time	3082146600 ps
CPU time	345.57 seconds
Started	Jun 09 03:48:36 PM PDT 24
Finished	Jun 09 03:54:23 PM PDT 24
Peak memory	646324 kb
Host	smart-260ec623-90d0-4850-b432-03f4efbd61cb
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085489949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3085489949
Directory	/workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/76.chip_sw_all_escalation_resets.84172241
Short name	T472
Test name
Test status
Simulation time	4647222452 ps
CPU time	547.49 seconds
Started	Jun 09 03:48:54 PM PDT 24
Finished	Jun 09 03:58:02 PM PDT 24
Peak memory	647912 kb
Host	smart-84b0ea23-3634-4935-abaf-044cb0fbd818
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 84172241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.84172241
Directory	/workspace/76.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3312562108
Short name	T813
Test name
Test status
Simulation time	4382612252 ps
CPU time	419.45 seconds
Started	Jun 09 03:49:03 PM PDT 24
Finished	Jun 09 03:56:03 PM PDT 24
Peak memory	616668 kb
Host	smart-773739ba-5e3f-41c6-9005-e04d3fcd6b20
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312562108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3312562108
Directory	/workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.472139722
Short name	T854
Test name
Test status
Simulation time	3831804140 ps
CPU time	375.89 seconds
Started	Jun 09 03:49:24 PM PDT 24
Finished	Jun 09 03:55:40 PM PDT 24
Peak memory	646556 kb
Host	smart-c7186807-ee14-4f02-84eb-64a8d33cc760
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472139722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_s w_alert_handler_lpg_sleep_mode_alerts.472139722
Directory	/workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/78.chip_sw_all_escalation_resets.3975656504
Short name	T493
Test name
Test status
Simulation time	4972822088 ps
CPU time	642.51 seconds
Started	Jun 09 03:48:28 PM PDT 24
Finished	Jun 09 03:59:11 PM PDT 24
Peak memory	643488 kb
Host	smart-9e6204d6-c9c0-46f8-8f2a-0a72ab1bbf9a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3975656504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.3975656504
Directory	/workspace/78.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.559436517
Short name	T633
Test name
Test status
Simulation time	3602814980 ps
CPU time	287.75 seconds
Started	Jun 09 03:49:13 PM PDT 24
Finished	Jun 09 03:54:01 PM PDT 24
Peak memory	646708 kb
Host	smart-8f2d5f6d-7452-4c5d-a9eb-6f1d3d881d5d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559436517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_s w_alert_handler_lpg_sleep_mode_alerts.559436517
Directory	/workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/79.chip_sw_all_escalation_resets.480777596
Short name	T367
Test name
Test status
Simulation time	5968189704 ps
CPU time	576.4 seconds
Started	Jun 09 03:49:25 PM PDT 24
Finished	Jun 09 03:59:02 PM PDT 24
Peak memory	643100 kb
Host	smart-aae63510-9cc9-4d3b-8124-16ff9d7e71fd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 480777596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.480777596
Directory	/workspace/79.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3306665085
Short name	T131
Test name
Test status
Simulation time	4374194540 ps
CPU time	505.94 seconds
Started	Jun 09 03:41:00 PM PDT 24
Finished	Jun 09 03:49:27 PM PDT 24
Peak memory	647360 kb
Host	smart-8d1de94c-f6ba-4dfd-9f35-41432741352a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306665085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.3306665085
Directory	/workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/8.chip_sw_all_escalation_resets.368819170
Short name	T264
Test name
Test status
Simulation time	6074153960 ps
CPU time	839.46 seconds
Started	Jun 09 03:41:17 PM PDT 24
Finished	Jun 09 03:55:16 PM PDT 24
Peak memory	643340 kb
Host	smart-04d5b417-7f52-4dd4-8634-952052ba0e07
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 368819170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.368819170
Directory	/workspace/8.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3029778005
Short name	T899
Test name
Test status
Simulation time	18828760400 ps
CPU time	3499.6 seconds
Started	Jun 09 03:41:30 PM PDT 24
Finished	Jun 09 04:39:50 PM PDT 24
Peak memory	607160 kb
Host	smart-8d696b08-2cc9-4ef0-a9e9-542d28de7967
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029778005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.3029778005
Directory	/workspace/8.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.228766435
Short name	T634
Test name
Test status
Simulation time	14178996086 ps
CPU time	969.8 seconds
Started	Jun 09 03:42:44 PM PDT 24
Finished	Jun 09 03:58:54 PM PDT 24
Peak memory	617920 kb
Host	smart-cbe47647-9e80-4fcd-b26a-ea2ce421c3ec
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228766435 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.228766435
Directory	/workspace/8.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.369429004
Short name	T322
Test name
Test status
Simulation time	3885037644 ps
CPU time	506.27 seconds
Started	Jun 09 03:41:00 PM PDT 24
Finished	Jun 09 03:49:27 PM PDT 24
Peak memory	617264 kb
Host	smart-685f2a2c-a2ab-42a4-a3c0-5f6f429aac6a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=369429004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.369429004
Directory	/workspace/8.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1097498993
Short name	T506
Test name
Test status
Simulation time	3556458960 ps
CPU time	472.45 seconds
Started	Jun 09 03:49:59 PM PDT 24
Finished	Jun 09 03:57:52 PM PDT 24
Peak memory	646188 kb
Host	smart-c9d02500-3990-4b5f-842c-8df13b8dfe81
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097498993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1097498993
Directory	/workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/80.chip_sw_all_escalation_resets.3806599844
Short name	T804
Test name
Test status
Simulation time	6107401032 ps
CPU time	630.2 seconds
Started	Jun 09 03:50:07 PM PDT 24
Finished	Jun 09 04:00:37 PM PDT 24
Peak memory	617288 kb
Host	smart-02fb49ce-16c5-4e7a-ace6-7e886048aad9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3806599844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.3806599844
Directory	/workspace/80.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/81.chip_sw_all_escalation_resets.7571107
Short name	T515
Test name
Test status
Simulation time	5696831514 ps
CPU time	452.22 seconds
Started	Jun 09 03:49:04 PM PDT 24
Finished	Jun 09 03:56:36 PM PDT 24
Peak memory	643524 kb
Host	smart-a9d5de0d-3888-45db-aa94-92cd37b534a9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 7571107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.7571107
Directory	/workspace/81.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1908908697
Short name	T398
Test name
Test status
Simulation time	4557125332 ps
CPU time	388.72 seconds
Started	Jun 09 03:49:09 PM PDT 24
Finished	Jun 09 03:55:38 PM PDT 24
Peak memory	646920 kb
Host	smart-aa44dc3d-bdc5-4aef-bc40-b83fdbb8da22
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908908697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1908908697
Directory	/workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3497003366
Short name	T438
Test name
Test status
Simulation time	5904755070 ps
CPU time	572.5 seconds
Started	Jun 09 03:49:56 PM PDT 24
Finished	Jun 09 03:59:29 PM PDT 24
Peak memory	647676 kb
Host	smart-af30deed-cee6-4b3e-a4c8-07d96eb1ec2d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3497003366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3497003366
Directory	/workspace/82.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1126695690
Short name	T834
Test name
Test status
Simulation time	3557989370 ps
CPU time	311.11 seconds
Started	Jun 09 03:51:13 PM PDT 24
Finished	Jun 09 03:56:24 PM PDT 24
Peak memory	646512 kb
Host	smart-49cb62b0-874b-464e-88bf-0ea6b2b05581
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126695690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1126695690
Directory	/workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630704481
Short name	T520
Test name
Test status
Simulation time	4361353722 ps
CPU time	365.64 seconds
Started	Jun 09 03:49:02 PM PDT 24
Finished	Jun 09 03:55:08 PM PDT 24
Peak memory	646508 kb
Host	smart-30be363a-36cc-4ac0-8605-76027ad0c339
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630704481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1630704481
Directory	/workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/84.chip_sw_all_escalation_resets.915635929
Short name	T466
Test name
Test status
Simulation time	5930996824 ps
CPU time	521.18 seconds
Started	Jun 09 03:50:51 PM PDT 24
Finished	Jun 09 03:59:33 PM PDT 24
Peak memory	647792 kb
Host	smart-30ff6074-1ca6-4f26-a3b1-2dd3852dbd03
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 915635929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.915635929
Directory	/workspace/84.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3280591075
Short name	T523
Test name
Test status
Simulation time	4296771224 ps
CPU time	399.93 seconds
Started	Jun 09 03:50:30 PM PDT 24
Finished	Jun 09 03:57:10 PM PDT 24
Peak memory	646724 kb
Host	smart-f0a05475-7a76-423e-a723-706527369be6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280591075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3280591075
Directory	/workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/86.chip_sw_all_escalation_resets.372547658
Short name	T749
Test name
Test status
Simulation time	4516695672 ps
CPU time	463.48 seconds
Started	Jun 09 03:49:55 PM PDT 24
Finished	Jun 09 03:57:39 PM PDT 24
Peak memory	647836 kb
Host	smart-ab5a70a9-d045-4536-9708-968976a871d5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 372547658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.372547658
Directory	/workspace/86.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.230182426
Short name	T491
Test name
Test status
Simulation time	3903197560 ps
CPU time	451.65 seconds
Started	Jun 09 03:50:01 PM PDT 24
Finished	Jun 09 03:57:33 PM PDT 24
Peak memory	646524 kb
Host	smart-a9d586f0-0eb0-44fe-938a-7705305b2874
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230182426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.230182426
Directory	/workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/87.chip_sw_all_escalation_resets.359350181
Short name	T979
Test name
Test status
Simulation time	4934137120 ps
CPU time	600.74 seconds
Started	Jun 09 03:49:24 PM PDT 24
Finished	Jun 09 03:59:25 PM PDT 24
Peak memory	647872 kb
Host	smart-c90bbb67-b179-43c0-b49f-ae70bad19554
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 359350181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.359350181
Directory	/workspace/87.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3028709314
Short name	T482
Test name
Test status
Simulation time	3782070136 ps
CPU time	335.48 seconds
Started	Jun 09 03:51:20 PM PDT 24
Finished	Jun 09 03:56:56 PM PDT 24
Peak memory	646628 kb
Host	smart-52aeeb8d-5f5f-4ccf-944f-f053f392cc60
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028709314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3028709314
Directory	/workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137430877
Short name	T399
Test name
Test status
Simulation time	3773131336 ps
CPU time	365.37 seconds
Started	Jun 09 03:50:45 PM PDT 24
Finished	Jun 09 03:56:51 PM PDT 24
Peak memory	646436 kb
Host	smart-2e832972-cb1b-4b9a-966b-bd6ba06718f0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137430877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2137430877
Directory	/workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2121451923
Short name	T181
Test name
Test status
Simulation time	3652459320 ps
CPU time	407.64 seconds
Started	Jun 09 03:41:37 PM PDT 24
Finished	Jun 09 03:48:25 PM PDT 24
Peak memory	616104 kb
Host	smart-a946dadd-d08c-4ed9-a8d8-65214b8fba40
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121451923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.2121451923
Directory	/workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/9.chip_sw_all_escalation_resets.3268290101
Short name	T495
Test name
Test status
Simulation time	5520755856 ps
CPU time	880.37 seconds
Started	Jun 09 03:41:18 PM PDT 24
Finished	Jun 09 03:55:59 PM PDT 24
Peak memory	648028 kb
Host	smart-1e88d200-e9d2-4b30-b4fc-b3450a4bf84a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3268290101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.3268290101
Directory	/workspace/9.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2676871715
Short name	T815
Test name
Test status
Simulation time	18170860700 ps
CPU time	3759.9 seconds
Started	Jun 09 03:43:38 PM PDT 24
Finished	Jun 09 04:46:19 PM PDT 24
Peak memory	607580 kb
Host	smart-43f78624-2fb2-4752-a572-20028522f3d0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676871715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.2676871715
Directory	/workspace/9.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2965105489
Short name	T688
Test name
Test status
Simulation time	11258670031 ps
CPU time	782.6 seconds
Started	Jun 09 03:42:19 PM PDT 24
Finished	Jun 09 03:55:22 PM PDT 24
Peak memory	617916 kb
Host	smart-3219fb25-b5d4-4407-b7a8-0dd4c1b0b898
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965105489 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.2965105489
Directory	/workspace/9.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1018583279
Short name	T740
Test name
Test status
Simulation time	3915055000 ps
CPU time	619.47 seconds
Started	Jun 09 03:41:12 PM PDT 24
Finished	Jun 09 03:51:32 PM PDT 24
Peak memory	617244 kb
Host	smart-6013bf73-1adc-4f70-8b8a-c89207e20c98
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1018583279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1018583279
Directory	/workspace/9.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/90.chip_sw_all_escalation_resets.419336183
Short name	T494
Test name
Test status
Simulation time	5593481428 ps
CPU time	612.47 seconds
Started	Jun 09 03:50:40 PM PDT 24
Finished	Jun 09 04:00:53 PM PDT 24
Peak memory	647968 kb
Host	smart-d16170c9-cee8-4cae-825d-820ae6923c0c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 419336183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.419336183
Directory	/workspace/90.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/91.chip_sw_all_escalation_resets.2747087568
Short name	T448
Test name
Test status
Simulation time	4880989568 ps
CPU time	648.65 seconds
Started	Jun 09 03:51:59 PM PDT 24
Finished	Jun 09 04:02:48 PM PDT 24
Peak memory	647996 kb
Host	smart-ec481d75-8a20-4c5a-9d2c-d50978fe06e4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2747087568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.2747087568
Directory	/workspace/91.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/93.chip_sw_all_escalation_resets.1532041185
Short name	T516
Test name
Test status
Simulation time	5579466220 ps
CPU time	624.22 seconds
Started	Jun 09 03:51:50 PM PDT 24
Finished	Jun 09 04:02:14 PM PDT 24
Peak memory	643140 kb
Host	smart-6b265f63-735c-475e-98d2-7d55d864e1ad
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1532041185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.1532041185
Directory	/workspace/93.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/94.chip_sw_all_escalation_resets.1197271083
Short name	T481
Test name
Test status
Simulation time	6088063932 ps
CPU time	604.27 seconds
Started	Jun 09 03:51:52 PM PDT 24
Finished	Jun 09 04:01:57 PM PDT 24
Peak memory	647784 kb
Host	smart-71fee300-4266-4bda-888d-c0371ce2d21a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1197271083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1197271083
Directory	/workspace/94.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3150134221
Short name	T74
Test name
Test status
Simulation time	5138842804 ps
CPU time	567.35 seconds
Started	Jun 09 03:50:03 PM PDT 24
Finished	Jun 09 03:59:31 PM PDT 24
Peak memory	647788 kb
Host	smart-0d3afa82-2ea8-46d0-8b36-0aa605a73dbf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3150134221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.3150134221
Directory	/workspace/95.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/98.chip_sw_all_escalation_resets.4088655025
Short name	T83
Test name
Test status
Simulation time	6067063728 ps
CPU time	594.56 seconds
Started	Jun 09 03:49:40 PM PDT 24
Finished	Jun 09 03:59:34 PM PDT 24
Peak memory	643472 kb
Host	smart-d28e6b92-9de3-4360-8eb1-ec8304dae307
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4088655025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.4088655025
Directory	/workspace/98.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/99.chip_sw_all_escalation_resets.2516631597
Short name	T383
Test name
Test status
Simulation time	4105288064 ps
CPU time	590.96 seconds
Started	Jun 09 03:49:28 PM PDT 24
Finished	Jun 09 03:59:19 PM PDT 24
Peak memory	647544 kb
Host	smart-5fb10942-7c1e-4125-b99b-27ebd61aa139
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2516631597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2516631597
Directory	/workspace/99.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.21299103
Short name	T220
Test name
Test status
Simulation time	5418273828 ps
CPU time	286.68 seconds
Started	Jun 09 03:03:46 PM PDT 24
Finished	Jun 09 03:08:33 PM PDT 24
Peak memory	648800 kb
Host	smart-7c87f0f9-61c5-44cc-a747-8206abdf3d2b
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21299103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 1.chip_padctrl_attributes.21299103
Directory	/workspace/1.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3813146683
Short name	T218
Test name
Test status
Simulation time	5428235643 ps
CPU time	290.71 seconds
Started	Jun 09 03:03:45 PM PDT 24
Finished	Jun 09 03:08:36 PM PDT 24
Peak memory	640056 kb
Host	smart-274821de-8d93-49d2-b7d1-294f5e531a75
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813146683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.3813146683
Directory	/workspace/2.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.666000802
Short name	T216
Test name
Test status
Simulation time	4758113301 ps
CPU time	274.03 seconds
Started	Jun 09 03:03:45 PM PDT 24
Finished	Jun 09 03:08:20 PM PDT 24
Peak memory	640212 kb
Host	smart-53dc1851-6fd2-415d-8ccf-29de09ff233f
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666000802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 3.chip_padctrl_attributes.666000802
Directory	/workspace/3.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3354547190
Short name	T217
Test name
Test status
Simulation time	5549439785 ps
CPU time	407.1 seconds
Started	Jun 09 03:03:43 PM PDT 24
Finished	Jun 09 03:10:30 PM PDT 24
Peak memory	648328 kb
Host	smart-9c765666-11a5-4e46-8a05-5a26f35b1742
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354547190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.3354547190
Directory	/workspace/5.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.411659365
Short name	T221
Test name
Test status
Simulation time	5675906260 ps
CPU time	218.56 seconds
Started	Jun 09 03:03:44 PM PDT 24
Finished	Jun 09 03:07:23 PM PDT 24
Peak memory	640136 kb
Host	smart-df70183a-f4bf-425a-918e-ca85db8e1f4c
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411659365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 6.chip_padctrl_attributes.411659365
Directory	/workspace/6.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2709385384
Short name	T219
Test name
Test status
Simulation time	3893820598 ps
CPU time	221.6 seconds
Started	Jun 09 03:03:48 PM PDT 24
Finished	Jun 09 03:07:30 PM PDT 24
Peak memory	641804 kb
Host	smart-cd3415ff-dfc5-4c1d-b5b3-423d369aa99b
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709385384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.2709385384
Directory	/workspace/7.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1899500901
Short name	T57
Test name
Test status
Simulation time	6014020566 ps
CPU time	340.74 seconds
Started	Jun 09 03:03:47 PM PDT 24
Finished	Jun 09 03:09:28 PM PDT 24
Peak memory	648948 kb
Host	smart-abfe0b3d-a6f9-4051-b92f-d02c115f6d20
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899500901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.1899500901
Directory	/workspace/8.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4027666715
Short name	T215
Test name
Test status
Simulation time	4618155544 ps
CPU time	256.28 seconds
Started	Jun 09 03:03:47 PM PDT 24
Finished	Jun 09 03:08:04 PM PDT 24
Peak memory	656516 kb
Host	smart-6581b84d-6e69-458f-a03a-34c37fddd737
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027666715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.4027666715
Directory	/workspace/9.chip_padctrl_attributes/latest

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