Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.26 96.47 89.29 87.38 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 84.62 100.00 100.00 u_edn_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00

Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Module : prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 990331138 4301 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 990331138 4301 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 990331138 4301 0 0
T4 91079 1 0 0
T5 124600 15 0 0
T6 97881 1 0 0
T16 131328 2 0 0
T19 260880 1 0 0
T20 546848 2 0 0
T31 169694 0 0 0
T41 945757 2 0 0
T42 72475 1 0 0
T54 125836 15 0 0
T85 162295 2 0 0
T124 821243 0 0 0
T148 225982 0 0 0
T213 59916 2 0 0
T214 0 10 0 0
T215 0 5 0 0
T269 614820 0 0 0
T270 217016 0 0 0
T287 199883 0 0 0
T332 0 8 0 0
T336 0 8 0 0
T337 0 8 0 0
T338 93142 0 0 0
T339 376977 0 0 0
T340 146990 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 990331138 4301 0 0
T4 91079 1 0 0
T5 124600 15 0 0
T6 97881 1 0 0
T16 131328 2 0 0
T19 260880 1 0 0
T20 546848 2 0 0
T31 169694 0 0 0
T41 945757 2 0 0
T42 72475 1 0 0
T54 125836 15 0 0
T85 162295 2 0 0
T124 821243 0 0 0
T148 225982 0 0 0
T213 59916 2 0 0
T214 0 10 0 0
T215 0 5 0 0
T269 614820 0 0 0
T270 217016 0 0 0
T287 199883 0 0 0
T332 0 8 0 0
T336 0 8 0 0
T337 0 8 0 0
T338 93142 0 0 0
T339 376977 0 0 0
T340 146990 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 495165569 41 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 495165569 41 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 495165569 41 0 0
T31 169694 0 0 0
T124 821243 0 0 0
T148 225982 0 0 0
T213 59916 2 0 0
T214 0 10 0 0
T215 0 5 0 0
T269 614820 0 0 0
T270 217016 0 0 0
T287 199883 0 0 0
T332 0 8 0 0
T336 0 8 0 0
T337 0 8 0 0
T338 93142 0 0 0
T339 376977 0 0 0
T340 146990 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 495165569 41 0 0
T31 169694 0 0 0
T124 821243 0 0 0
T148 225982 0 0 0
T213 59916 2 0 0
T214 0 10 0 0
T215 0 5 0 0
T269 614820 0 0 0
T270 217016 0 0 0
T287 199883 0 0 0
T332 0 8 0 0
T336 0 8 0 0
T337 0 8 0 0
T338 93142 0 0 0
T339 376977 0 0 0
T340 146990 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 495165569 4260 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 495165569 4260 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 495165569 4260 0 0
T4 91079 1 0 0
T5 124600 15 0 0
T6 97881 1 0 0
T16 131328 2 0 0
T19 260880 1 0 0
T20 546848 2 0 0
T41 945757 2 0 0
T42 72475 1 0 0
T54 125836 15 0 0
T85 162295 2 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 495165569 4260 0 0
T4 91079 1 0 0
T5 124600 15 0 0
T6 97881 1 0 0
T16 131328 2 0 0
T19 260880 1 0 0
T20 546848 2 0 0
T41 945757 2 0 0
T42 72475 1 0 0
T54 125836 15 0 0
T85 162295 2 0 0

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