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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.56 92.77 82.83 90.06 94.87 97.53 85.31


Total test records in report: 1002
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T596 /workspace/coverage/default/2.chip_sw_aes_smoketest.759143970 Jun 13 04:04:27 PM PDT 24 Jun 13 04:10:04 PM PDT 24 3126504326 ps
T470 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2919686250 Jun 13 04:11:44 PM PDT 24 Jun 13 04:18:52 PM PDT 24 4555610560 ps
T365 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1025521183 Jun 13 03:44:45 PM PDT 24 Jun 13 04:13:24 PM PDT 24 7988462968 ps
T597 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3671118957 Jun 13 03:58:23 PM PDT 24 Jun 13 04:02:44 PM PDT 24 3143116168 ps
T598 /workspace/coverage/default/2.chip_sw_example_flash.668060511 Jun 13 03:53:52 PM PDT 24 Jun 13 03:58:22 PM PDT 24 2395417162 ps
T599 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1436271988 Jun 13 04:04:33 PM PDT 24 Jun 13 04:10:13 PM PDT 24 3038255800 ps
T600 /workspace/coverage/default/1.chip_sw_aes_enc.3987028044 Jun 13 03:43:39 PM PDT 24 Jun 13 03:48:26 PM PDT 24 3095921080 ps
T129 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2989546973 Jun 13 03:40:36 PM PDT 24 Jun 13 03:51:25 PM PDT 24 8803621509 ps
T397 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2721018999 Jun 13 03:56:27 PM PDT 24 Jun 13 04:19:22 PM PDT 24 8983801479 ps
T99 /workspace/coverage/default/3.chip_tap_straps_rma.522659319 Jun 13 04:05:25 PM PDT 24 Jun 13 04:09:09 PM PDT 24 3145986521 ps
T601 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2836905821 Jun 13 04:03:58 PM PDT 24 Jun 13 04:09:13 PM PDT 24 3528443846 ps
T602 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.20145536 Jun 13 04:12:30 PM PDT 24 Jun 13 04:20:38 PM PDT 24 4232713408 ps
T168 /workspace/coverage/default/44.chip_sw_all_escalation_resets.3277592786 Jun 13 04:11:48 PM PDT 24 Jun 13 04:22:08 PM PDT 24 4965079704 ps
T469 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3952845242 Jun 13 04:09:45 PM PDT 24 Jun 13 04:17:48 PM PDT 24 4210887304 ps
T541 /workspace/coverage/default/11.chip_sw_all_escalation_resets.227094057 Jun 13 04:07:51 PM PDT 24 Jun 13 04:22:46 PM PDT 24 5756087296 ps
T603 /workspace/coverage/default/1.chip_sw_aes_entropy.630379287 Jun 13 03:44:35 PM PDT 24 Jun 13 03:48:42 PM PDT 24 2846721012 ps
T427 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.805392822 Jun 13 03:38:50 PM PDT 24 Jun 13 03:44:51 PM PDT 24 3709918929 ps
T509 /workspace/coverage/default/25.chip_sw_all_escalation_resets.4207435002 Jun 13 04:11:45 PM PDT 24 Jun 13 04:21:24 PM PDT 24 5879351288 ps
T604 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4134985480 Jun 13 03:38:13 PM PDT 24 Jun 13 03:46:40 PM PDT 24 4665047100 ps
T467 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1412441156 Jun 13 03:42:26 PM PDT 24 Jun 13 04:00:35 PM PDT 24 8482055792 ps
T498 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4236087461 Jun 13 04:09:21 PM PDT 24 Jun 13 04:16:38 PM PDT 24 3848697460 ps
T391 /workspace/coverage/default/87.chip_sw_all_escalation_resets.1207702744 Jun 13 04:15:32 PM PDT 24 Jun 13 04:23:47 PM PDT 24 5492887336 ps
T400 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.556288102 Jun 13 04:02:51 PM PDT 24 Jun 13 04:11:56 PM PDT 24 6132189992 ps
T605 /workspace/coverage/default/0.rom_e2e_asm_init_rma.1378348056 Jun 13 03:43:34 PM PDT 24 Jun 13 04:51:38 PM PDT 24 14206413326 ps
T606 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.933612132 Jun 13 03:44:40 PM PDT 24 Jun 13 04:34:44 PM PDT 24 10523233533 ps
T607 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4023054517 Jun 13 04:01:14 PM PDT 24 Jun 13 04:05:01 PM PDT 24 2866766026 ps
T551 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.493131034 Jun 13 04:13:40 PM PDT 24 Jun 13 04:21:27 PM PDT 24 3283643948 ps
T281 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3399357036 Jun 13 03:49:44 PM PDT 24 Jun 13 03:56:45 PM PDT 24 4434064512 ps
T608 /workspace/coverage/default/0.rom_e2e_asm_init_dev.696507689 Jun 13 03:45:46 PM PDT 24 Jun 13 04:46:08 PM PDT 24 13981766843 ps
T609 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3677701193 Jun 13 03:47:49 PM PDT 24 Jun 13 03:58:57 PM PDT 24 5901404900 ps
T610 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3796560639 Jun 13 03:38:21 PM PDT 24 Jun 13 03:56:23 PM PDT 24 5967534441 ps
T611 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3326628423 Jun 13 03:51:44 PM PDT 24 Jun 13 03:57:26 PM PDT 24 2570613674 ps
T612 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2493581260 Jun 13 03:37:04 PM PDT 24 Jun 13 03:43:44 PM PDT 24 3670255783 ps
T291 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1498178538 Jun 13 03:44:18 PM PDT 24 Jun 13 05:25:11 PM PDT 24 22342001670 ps
T613 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3021685948 Jun 13 03:39:42 PM PDT 24 Jun 13 03:44:33 PM PDT 24 2855991004 ps
T35 /workspace/coverage/default/0.chip_sw_usbdev_dpi.874297375 Jun 13 03:38:10 PM PDT 24 Jun 13 04:31:59 PM PDT 24 12680079462 ps
T614 /workspace/coverage/default/3.chip_tap_straps_testunlock0.4035384125 Jun 13 04:05:27 PM PDT 24 Jun 13 04:10:45 PM PDT 24 3579163288 ps
T615 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.75352972 Jun 13 03:38:13 PM PDT 24 Jun 13 03:45:30 PM PDT 24 4307440790 ps
T87 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1091462474 Jun 13 04:02:36 PM PDT 24 Jun 13 04:56:50 PM PDT 24 24532077694 ps
T2 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1864887797 Jun 13 03:44:44 PM PDT 24 Jun 13 03:49:41 PM PDT 24 5878321860 ps
T442 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.794709132 Jun 13 04:15:04 PM PDT 24 Jun 13 04:21:26 PM PDT 24 3914737720 ps
T373 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.758075287 Jun 13 04:03:53 PM PDT 24 Jun 13 04:18:59 PM PDT 24 5371677314 ps
T443 /workspace/coverage/default/0.chip_sw_hmac_enc.3832650444 Jun 13 03:42:11 PM PDT 24 Jun 13 03:46:52 PM PDT 24 2897048774 ps
T225 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1214313176 Jun 13 03:38:56 PM PDT 24 Jun 13 03:52:22 PM PDT 24 4264331206 ps
T78 /workspace/coverage/default/0.chip_sw_power_sleep_load.142001579 Jun 13 03:43:12 PM PDT 24 Jun 13 03:52:33 PM PDT 24 9769049972 ps
T444 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3495254330 Jun 13 04:14:58 PM PDT 24 Jun 13 04:20:36 PM PDT 24 3527411520 ps
T394 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2235002642 Jun 13 03:42:51 PM PDT 24 Jun 13 03:55:06 PM PDT 24 4607228464 ps
T445 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.230788073 Jun 13 03:52:34 PM PDT 24 Jun 13 04:00:19 PM PDT 24 3253322506 ps
T446 /workspace/coverage/default/2.chip_sw_aes_enc.1806084989 Jun 13 03:56:54 PM PDT 24 Jun 13 04:02:24 PM PDT 24 3474286288 ps
T3 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.162038381 Jun 13 03:53:50 PM PDT 24 Jun 13 04:01:52 PM PDT 24 6809966020 ps
T435 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3485852038 Jun 13 04:14:17 PM PDT 24 Jun 13 04:23:58 PM PDT 24 4973995868 ps
T436 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3775282359 Jun 13 03:53:14 PM PDT 24 Jun 13 04:00:34 PM PDT 24 3604840250 ps
T437 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2217829312 Jun 13 03:45:17 PM PDT 24 Jun 13 03:49:51 PM PDT 24 2645604640 ps
T438 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2702571538 Jun 13 03:41:37 PM PDT 24 Jun 13 03:49:30 PM PDT 24 4288342600 ps
T22 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1373576097 Jun 13 03:52:56 PM PDT 24 Jun 13 03:56:47 PM PDT 24 3718403754 ps
T439 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4111584989 Jun 13 04:17:15 PM PDT 24 Jun 13 04:23:08 PM PDT 24 3469139188 ps
T73 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.859780185 Jun 13 03:59:53 PM PDT 24 Jun 13 04:09:30 PM PDT 24 5088973646 ps
T440 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1851114822 Jun 13 04:00:30 PM PDT 24 Jun 13 04:10:23 PM PDT 24 4297859160 ps
T441 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3400840541 Jun 13 03:59:13 PM PDT 24 Jun 13 04:07:51 PM PDT 24 7233193600 ps
T616 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.176202910 Jun 13 03:49:18 PM PDT 24 Jun 13 03:56:01 PM PDT 24 3775024628 ps
T617 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.819852579 Jun 13 03:37:25 PM PDT 24 Jun 13 03:48:55 PM PDT 24 4157162244 ps
T618 /workspace/coverage/default/2.chip_sw_aes_masking_off.3867896580 Jun 13 03:58:11 PM PDT 24 Jun 13 04:02:14 PM PDT 24 3060617764 ps
T619 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2969291230 Jun 13 04:08:44 PM PDT 24 Jun 13 04:48:37 PM PDT 24 10820988142 ps
T221 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4202767035 Jun 13 03:40:43 PM PDT 24 Jun 13 04:12:00 PM PDT 24 14249653388 ps
T620 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2425278648 Jun 13 03:50:36 PM PDT 24 Jun 13 04:40:40 PM PDT 24 11321079260 ps
T621 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3732981805 Jun 13 03:36:28 PM PDT 24 Jun 13 03:43:59 PM PDT 24 3959528288 ps
T622 /workspace/coverage/default/0.chip_sw_hmac_multistream.2277966148 Jun 13 03:39:36 PM PDT 24 Jun 13 04:09:28 PM PDT 24 6601854670 ps
T623 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2990721279 Jun 13 03:57:42 PM PDT 24 Jun 13 04:26:45 PM PDT 24 8336710562 ps
T624 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3083972760 Jun 13 03:52:43 PM PDT 24 Jun 13 03:58:29 PM PDT 24 2918539576 ps
T36 /workspace/coverage/default/0.chip_sw_gpio.3029264500 Jun 13 03:37:45 PM PDT 24 Jun 13 03:45:58 PM PDT 24 3750853600 ps
T209 /workspace/coverage/default/0.rom_e2e_shutdown_output.1327218785 Jun 13 03:44:09 PM PDT 24 Jun 13 04:34:41 PM PDT 24 20723549020 ps
T7 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3521582568 Jun 13 03:50:13 PM PDT 24 Jun 13 04:31:20 PM PDT 24 25279922784 ps
T625 /workspace/coverage/default/0.chip_sw_hmac_smoketest.3622843175 Jun 13 03:41:21 PM PDT 24 Jun 13 03:47:22 PM PDT 24 3766784464 ps
T169 /workspace/coverage/default/42.chip_sw_all_escalation_resets.2303610399 Jun 13 04:12:45 PM PDT 24 Jun 13 04:22:08 PM PDT 24 5631539452 ps
T626 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2836740875 Jun 13 03:38:35 PM PDT 24 Jun 13 03:42:21 PM PDT 24 3233435193 ps
T395 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138980151 Jun 13 04:13:50 PM PDT 24 Jun 13 04:21:25 PM PDT 24 3585625908 ps
T344 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3550959125 Jun 13 03:47:35 PM PDT 24 Jun 13 04:09:21 PM PDT 24 8042146600 ps
T259 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3660955542 Jun 13 03:54:31 PM PDT 24 Jun 13 04:01:23 PM PDT 24 4189434313 ps
T256 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3782728592 Jun 13 04:01:32 PM PDT 24 Jun 13 04:30:15 PM PDT 24 26940336311 ps
T79 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2033857127 Jun 13 03:46:49 PM PDT 24 Jun 13 03:58:27 PM PDT 24 18896292250 ps
T341 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2033935111 Jun 13 04:09:35 PM PDT 24 Jun 13 04:16:39 PM PDT 24 4108958168 ps
T627 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1009728643 Jun 13 03:42:21 PM PDT 24 Jun 13 03:51:34 PM PDT 24 8036785258 ps
T456 /workspace/coverage/default/77.chip_sw_all_escalation_resets.857764935 Jun 13 04:14:27 PM PDT 24 Jun 13 04:26:21 PM PDT 24 5496374260 ps
T350 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3780500015 Jun 13 03:41:10 PM PDT 24 Jun 13 03:59:47 PM PDT 24 7062319900 ps
T628 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2169812896 Jun 13 03:45:37 PM PDT 24 Jun 13 04:06:59 PM PDT 24 5044049058 ps
T629 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.341146098 Jun 13 04:02:14 PM PDT 24 Jun 13 04:37:35 PM PDT 24 12316095010 ps
T630 /workspace/coverage/default/2.chip_sw_aes_entropy.887665208 Jun 13 03:58:37 PM PDT 24 Jun 13 04:03:39 PM PDT 24 3494983568 ps
T282 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.708444178 Jun 13 04:01:44 PM PDT 24 Jun 13 04:11:50 PM PDT 24 4636814076 ps
T631 /workspace/coverage/default/1.chip_sw_aon_timer_irq.4120498721 Jun 13 03:46:01 PM PDT 24 Jun 13 03:51:25 PM PDT 24 4367023000 ps
T383 /workspace/coverage/default/28.chip_sw_all_escalation_resets.3476160010 Jun 13 04:14:20 PM PDT 24 Jun 13 04:27:44 PM PDT 24 5229788460 ps
T632 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1443813050 Jun 13 03:47:32 PM PDT 24 Jun 13 03:51:43 PM PDT 24 3080548060 ps
T74 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.60242398 Jun 13 03:41:30 PM PDT 24 Jun 13 03:50:34 PM PDT 24 4658267761 ps
T86 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.4219797813 Jun 13 03:51:46 PM PDT 24 Jun 13 04:21:30 PM PDT 24 15102389465 ps
T384 /workspace/coverage/default/53.chip_sw_all_escalation_resets.671372649 Jun 13 04:14:48 PM PDT 24 Jun 13 04:24:51 PM PDT 24 5213922034 ps
T415 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1985252376 Jun 13 03:44:50 PM PDT 24 Jun 13 03:59:59 PM PDT 24 6404458968 ps
T353 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2658611546 Jun 13 03:46:53 PM PDT 24 Jun 13 04:15:24 PM PDT 24 8068228306 ps
T276 /workspace/coverage/default/0.chip_sw_plic_sw_irq.927227567 Jun 13 03:38:02 PM PDT 24 Jun 13 03:41:23 PM PDT 24 3411561080 ps
T295 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3149867301 Jun 13 03:40:39 PM PDT 24 Jun 13 03:49:21 PM PDT 24 5187288548 ps
T633 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4073085045 Jun 13 03:44:02 PM PDT 24 Jun 13 04:47:26 PM PDT 24 14206358256 ps
T452 /workspace/coverage/default/2.rom_volatile_raw_unlock.721143160 Jun 13 04:03:00 PM PDT 24 Jun 13 04:04:51 PM PDT 24 1916953983 ps
T324 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1318954533 Jun 13 03:51:06 PM PDT 24 Jun 13 03:59:51 PM PDT 24 4386816256 ps
T231 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.758618989 Jun 13 03:36:29 PM PDT 24 Jun 13 03:47:57 PM PDT 24 4204412576 ps
T11 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.249165580 Jun 13 03:50:08 PM PDT 24 Jun 13 04:09:49 PM PDT 24 22944424982 ps
T255 /workspace/coverage/default/1.chip_sw_flash_init.2950209471 Jun 13 03:39:09 PM PDT 24 Jun 13 04:05:37 PM PDT 24 17089790362 ps
T634 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2648419434 Jun 13 03:44:15 PM PDT 24 Jun 13 04:49:07 PM PDT 24 14702316400 ps
T537 /workspace/coverage/default/72.chip_sw_all_escalation_resets.2498254023 Jun 13 04:14:01 PM PDT 24 Jun 13 04:25:49 PM PDT 24 5112531048 ps
T635 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2276593803 Jun 13 04:02:44 PM PDT 24 Jun 13 04:14:00 PM PDT 24 4485517128 ps
T636 /workspace/coverage/default/0.chip_sw_example_rom.3623009120 Jun 13 03:34:48 PM PDT 24 Jun 13 03:36:46 PM PDT 24 1770220644 ps
T637 /workspace/coverage/default/0.chip_tap_straps_prod.3467477934 Jun 13 03:42:38 PM PDT 24 Jun 13 03:45:23 PM PDT 24 3385038018 ps
T210 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.25460142 Jun 13 03:56:34 PM PDT 24 Jun 13 04:15:29 PM PDT 24 7816044630 ps
T363 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.587093192 Jun 13 03:38:48 PM PDT 24 Jun 13 03:49:47 PM PDT 24 3777539624 ps
T165 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.939854623 Jun 13 03:49:14 PM PDT 24 Jun 13 04:06:42 PM PDT 24 11018660780 ps
T638 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.472244963 Jun 13 03:37:06 PM PDT 24 Jun 13 03:55:54 PM PDT 24 7202549880 ps
T639 /workspace/coverage/default/0.chip_sw_aes_idle.4123447898 Jun 13 03:41:08 PM PDT 24 Jun 13 03:46:32 PM PDT 24 3700416864 ps
T640 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3656496606 Jun 13 04:08:13 PM PDT 24 Jun 13 04:16:59 PM PDT 24 4194828960 ps
T381 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2310569757 Jun 13 03:53:55 PM PDT 24 Jun 13 04:03:13 PM PDT 24 3685295078 ps
T641 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3797628301 Jun 13 04:08:09 PM PDT 24 Jun 13 04:17:14 PM PDT 24 4261342314 ps
T205 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3843067753 Jun 13 03:38:52 PM PDT 24 Jun 13 03:42:44 PM PDT 24 2732693963 ps
T642 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.310610968 Jun 13 03:51:19 PM PDT 24 Jun 13 03:54:15 PM PDT 24 2823722379 ps
T368 /workspace/coverage/default/2.chip_sw_otbn_randomness.1666215775 Jun 13 03:57:34 PM PDT 24 Jun 13 04:16:38 PM PDT 24 6385158524 ps
T643 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.169683818 Jun 13 03:46:18 PM PDT 24 Jun 13 04:49:08 PM PDT 24 14104567250 ps
T644 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2315445339 Jun 13 03:52:43 PM PDT 24 Jun 13 03:57:09 PM PDT 24 3087866200 ps
T345 /workspace/coverage/default/2.chip_sw_power_sleep_load.3172062252 Jun 13 04:02:38 PM PDT 24 Jun 13 04:13:34 PM PDT 24 10336077390 ps
T527 /workspace/coverage/default/57.chip_sw_all_escalation_resets.3457831124 Jun 13 04:13:16 PM PDT 24 Jun 13 04:21:24 PM PDT 24 4304959584 ps
T645 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1907690970 Jun 13 03:38:04 PM PDT 24 Jun 13 04:02:00 PM PDT 24 8777702280 ps
T646 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2577476669 Jun 13 03:40:54 PM PDT 24 Jun 13 03:50:55 PM PDT 24 4716199962 ps
T647 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3653047354 Jun 13 03:49:18 PM PDT 24 Jun 13 03:52:11 PM PDT 24 3057816686 ps
T648 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2097007303 Jun 13 03:42:50 PM PDT 24 Jun 13 03:51:36 PM PDT 24 4459686584 ps
T492 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836195201 Jun 13 04:08:22 PM PDT 24 Jun 13 04:16:27 PM PDT 24 3572694020 ps
T206 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2511935619 Jun 13 03:38:04 PM PDT 24 Jun 13 04:22:05 PM PDT 24 30810767695 ps
T649 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.959817230 Jun 13 03:48:47 PM PDT 24 Jun 13 03:51:55 PM PDT 24 2630325384 ps
T650 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2962247672 Jun 13 03:40:54 PM PDT 24 Jun 13 03:48:09 PM PDT 24 3001199252 ps
T417 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2203263357 Jun 13 03:43:28 PM PDT 24 Jun 13 04:59:59 PM PDT 24 25009516585 ps
T651 /workspace/coverage/default/1.chip_sw_hmac_multistream.1152220299 Jun 13 03:45:33 PM PDT 24 Jun 13 04:10:01 PM PDT 24 6071316600 ps
T652 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1439762628 Jun 13 03:42:35 PM PDT 24 Jun 13 04:19:35 PM PDT 24 26042010135 ps
T653 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3066918339 Jun 13 03:52:06 PM PDT 24 Jun 13 04:01:52 PM PDT 24 4512007980 ps
T247 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.472021904 Jun 13 03:37:12 PM PDT 24 Jun 13 06:55:57 PM PDT 24 65617441740 ps
T379 /workspace/coverage/default/14.chip_sw_all_escalation_resets.370471726 Jun 13 04:09:46 PM PDT 24 Jun 13 04:17:08 PM PDT 24 5038518098 ps
T654 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.256542105 Jun 13 03:45:38 PM PDT 24 Jun 13 04:41:02 PM PDT 24 10928070002 ps
T497 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1377720305 Jun 13 04:14:03 PM PDT 24 Jun 13 04:23:16 PM PDT 24 4612182374 ps
T655 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2472669453 Jun 13 04:03:02 PM PDT 24 Jun 13 04:11:52 PM PDT 24 5034092040 ps
T403 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.733215926 Jun 13 04:15:23 PM PDT 24 Jun 13 04:22:02 PM PDT 24 3736073096 ps
T277 /workspace/coverage/default/2.chip_sw_plic_sw_irq.1653762740 Jun 13 04:00:20 PM PDT 24 Jun 13 04:05:51 PM PDT 24 2315614360 ps
T656 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.596932748 Jun 13 04:05:58 PM PDT 24 Jun 13 04:17:26 PM PDT 24 6105350784 ps
T657 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.848156102 Jun 13 04:06:24 PM PDT 24 Jun 13 04:28:32 PM PDT 24 13648479269 ps
T658 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2196499040 Jun 13 03:43:41 PM PDT 24 Jun 13 03:51:01 PM PDT 24 4215934904 ps
T463 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3404462411 Jun 13 04:11:12 PM PDT 24 Jun 13 04:17:34 PM PDT 24 4272686856 ps
T110 /workspace/coverage/default/1.chip_plic_all_irqs_10.2747512555 Jun 13 03:47:44 PM PDT 24 Jun 13 03:57:50 PM PDT 24 3878540384 ps
T659 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.4033083896 Jun 13 04:00:11 PM PDT 24 Jun 13 04:08:16 PM PDT 24 3217985048 ps
T156 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1607079902 Jun 13 03:59:41 PM PDT 24 Jun 13 04:08:32 PM PDT 24 7756615620 ps
T118 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.656023663 Jun 13 03:39:55 PM PDT 24 Jun 13 04:36:30 PM PDT 24 43990582271 ps
T249 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.272116303 Jun 13 03:57:05 PM PDT 24 Jun 13 04:08:44 PM PDT 24 4388931813 ps
T292 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1571739326 Jun 13 03:43:30 PM PDT 24 Jun 13 04:53:47 PM PDT 24 17546845548 ps
T458 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1208980247 Jun 13 04:16:05 PM PDT 24 Jun 13 04:22:52 PM PDT 24 3977176662 ps
T554 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2371009102 Jun 13 04:18:04 PM PDT 24 Jun 13 04:23:47 PM PDT 24 4526365200 ps
T64 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1080007332 Jun 13 03:43:49 PM PDT 24 Jun 13 03:50:42 PM PDT 24 7661336046 ps
T660 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.4233768934 Jun 13 03:41:03 PM PDT 24 Jun 13 03:56:02 PM PDT 24 5721611720 ps
T661 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1232837217 Jun 13 04:07:59 PM PDT 24 Jun 13 04:58:49 PM PDT 24 14487441496 ps
T65 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.226731117 Jun 13 03:59:13 PM PDT 24 Jun 13 04:02:46 PM PDT 24 3035067831 ps
T465 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.701306333 Jun 13 03:43:59 PM PDT 24 Jun 13 03:54:06 PM PDT 24 4197193860 ps
T215 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1217390570 Jun 13 04:00:39 PM PDT 24 Jun 13 04:06:41 PM PDT 24 2897924557 ps
T662 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2548646491 Jun 13 03:36:17 PM PDT 24 Jun 13 03:45:27 PM PDT 24 5580892512 ps
T663 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2065340237 Jun 13 04:16:03 PM PDT 24 Jun 13 04:21:38 PM PDT 24 3763391152 ps
T664 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1797980117 Jun 13 03:38:54 PM PDT 24 Jun 13 04:35:38 PM PDT 24 31221566190 ps
T665 /workspace/coverage/default/2.chip_sw_kmac_entropy.434108459 Jun 13 03:55:57 PM PDT 24 Jun 13 04:02:08 PM PDT 24 3609980880 ps
T475 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2838672318 Jun 13 04:14:36 PM PDT 24 Jun 13 04:22:04 PM PDT 24 3342765480 ps
T666 /workspace/coverage/default/1.chip_sw_kmac_idle.2218864074 Jun 13 03:45:52 PM PDT 24 Jun 13 03:49:12 PM PDT 24 2325796290 ps
T416 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1212711556 Jun 13 04:01:15 PM PDT 24 Jun 13 04:20:15 PM PDT 24 4960366108 ps
T166 /workspace/coverage/default/0.chip_sw_gpio_smoketest.1684942016 Jun 13 03:46:01 PM PDT 24 Jun 13 03:50:54 PM PDT 24 3162815263 ps
T535 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3592987446 Jun 13 04:08:16 PM PDT 24 Jun 13 04:16:30 PM PDT 24 3602745080 ps
T667 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2948812631 Jun 13 03:51:29 PM PDT 24 Jun 13 04:03:31 PM PDT 24 5065016148 ps
T668 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2992006079 Jun 13 04:04:17 PM PDT 24 Jun 13 04:37:22 PM PDT 24 8159570044 ps
T669 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3602836626 Jun 13 03:54:37 PM PDT 24 Jun 13 04:00:48 PM PDT 24 3390263168 ps
T263 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.4277009956 Jun 13 03:56:37 PM PDT 24 Jun 13 05:20:14 PM PDT 24 50809174432 ps
T312 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1280198755 Jun 13 03:45:11 PM PDT 24 Jun 13 04:52:42 PM PDT 24 13136623862 ps
T670 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2761176917 Jun 13 04:09:39 PM PDT 24 Jun 13 04:22:15 PM PDT 24 7087259652 ps
T13 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.822500959 Jun 13 04:02:40 PM PDT 24 Jun 13 04:28:16 PM PDT 24 22708754776 ps
T671 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2895250661 Jun 13 03:40:02 PM PDT 24 Jun 13 03:48:49 PM PDT 24 17718822392 ps
T672 /workspace/coverage/default/0.chip_sw_edn_auto_mode.3675596190 Jun 13 03:38:41 PM PDT 24 Jun 13 04:05:00 PM PDT 24 6292533258 ps
T358 /workspace/coverage/default/1.chip_sw_pattgen_ios.3022226590 Jun 13 03:44:24 PM PDT 24 Jun 13 03:49:03 PM PDT 24 3178578090 ps
T673 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3617288263 Jun 13 03:45:57 PM PDT 24 Jun 13 03:51:42 PM PDT 24 3846750219 ps
T674 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3977942889 Jun 13 03:38:44 PM PDT 24 Jun 13 03:50:10 PM PDT 24 5709342480 ps
T48 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1207242844 Jun 13 03:42:51 PM PDT 24 Jun 13 03:48:46 PM PDT 24 2584750839 ps
T313 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2509192231 Jun 13 03:46:02 PM PDT 24 Jun 13 04:43:52 PM PDT 24 13968245814 ps
T675 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1981508099 Jun 13 04:05:04 PM PDT 24 Jun 13 04:18:05 PM PDT 24 4431462752 ps
T126 /workspace/coverage/default/2.chip_sw_alert_test.921448945 Jun 13 03:58:25 PM PDT 24 Jun 13 04:03:36 PM PDT 24 2852484540 ps
T676 /workspace/coverage/default/2.chip_sw_hmac_oneshot.1489704913 Jun 13 04:00:25 PM PDT 24 Jun 13 04:07:27 PM PDT 24 3189791760 ps
T677 /workspace/coverage/default/1.chip_sw_edn_kat.1266573486 Jun 13 03:42:47 PM PDT 24 Jun 13 03:54:10 PM PDT 24 3565743612 ps
T547 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1926364830 Jun 13 04:14:55 PM PDT 24 Jun 13 04:19:59 PM PDT 24 2994817612 ps
T678 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3130606605 Jun 13 03:36:12 PM PDT 24 Jun 13 03:42:14 PM PDT 24 5103027406 ps
T111 /workspace/coverage/default/2.chip_plic_all_irqs_10.4216156415 Jun 13 04:03:06 PM PDT 24 Jun 13 04:13:41 PM PDT 24 3886510208 ps
T679 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2465129811 Jun 13 03:39:46 PM PDT 24 Jun 13 03:43:31 PM PDT 24 2670513290 ps
T375 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.4228049576 Jun 13 03:41:05 PM PDT 24 Jun 13 03:50:50 PM PDT 24 4020637984 ps
T250 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2467405025 Jun 13 03:36:36 PM PDT 24 Jun 13 03:44:09 PM PDT 24 4006422518 ps
T680 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.900087509 Jun 13 04:09:01 PM PDT 24 Jun 13 04:32:53 PM PDT 24 7972057304 ps
T681 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2321774018 Jun 13 03:51:42 PM PDT 24 Jun 13 03:56:01 PM PDT 24 2885762478 ps
T544 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3862993682 Jun 13 04:11:25 PM PDT 24 Jun 13 04:21:36 PM PDT 24 5991851492 ps
T479 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3916392309 Jun 13 04:11:13 PM PDT 24 Jun 13 04:17:51 PM PDT 24 3245386450 ps
T682 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2788947722 Jun 13 04:06:06 PM PDT 24 Jun 13 04:11:55 PM PDT 24 6942424816 ps
T130 /workspace/coverage/default/58.chip_sw_all_escalation_resets.654916671 Jun 13 04:14:07 PM PDT 24 Jun 13 04:23:13 PM PDT 24 5720833840 ps
T683 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3460165791 Jun 13 03:54:27 PM PDT 24 Jun 13 04:27:12 PM PDT 24 13365151841 ps
T684 /workspace/coverage/default/1.rom_e2e_asm_init_dev.1024346687 Jun 13 03:58:30 PM PDT 24 Jun 13 05:02:58 PM PDT 24 14419172816 ps
T539 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2265764643 Jun 13 04:14:32 PM PDT 24 Jun 13 04:20:35 PM PDT 24 3585463796 ps
T685 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2724758367 Jun 13 04:05:15 PM PDT 24 Jun 13 05:09:26 PM PDT 24 15118136012 ps
T686 /workspace/coverage/default/0.chip_sw_otbn_randomness.2578842344 Jun 13 03:37:51 PM PDT 24 Jun 13 03:55:41 PM PDT 24 6179442202 ps
T687 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2863747328 Jun 13 03:41:42 PM PDT 24 Jun 13 03:46:18 PM PDT 24 3408317068 ps
T390 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1658748950 Jun 13 03:41:42 PM PDT 24 Jun 13 03:54:39 PM PDT 24 4485847499 ps
T688 /workspace/coverage/default/1.rom_keymgr_functest.3624535209 Jun 13 03:58:16 PM PDT 24 Jun 13 04:05:59 PM PDT 24 4273122172 ps
T207 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.29860773 Jun 13 03:42:37 PM PDT 24 Jun 13 03:45:38 PM PDT 24 3424373538 ps
T9 /workspace/coverage/default/2.chip_jtag_csr_rw.1353314733 Jun 13 03:53:22 PM PDT 24 Jun 13 04:29:01 PM PDT 24 18559515468 ps
T429 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1293299090 Jun 13 03:44:05 PM PDT 24 Jun 13 03:53:03 PM PDT 24 5907172490 ps
T430 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3027241713 Jun 13 03:49:58 PM PDT 24 Jun 13 03:57:29 PM PDT 24 4478888238 ps
T431 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1941550886 Jun 13 03:56:02 PM PDT 24 Jun 13 04:02:28 PM PDT 24 4931215975 ps
T404 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2484139737 Jun 13 04:09:17 PM PDT 24 Jun 13 04:15:41 PM PDT 24 3921971666 ps
T61 /workspace/coverage/default/0.chip_jtag_csr_rw.3635235682 Jun 13 03:29:58 PM PDT 24 Jun 13 03:48:47 PM PDT 24 11095027748 ps
T432 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.213640848 Jun 13 03:41:26 PM PDT 24 Jun 13 03:57:55 PM PDT 24 9472401436 ps
T257 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1089541668 Jun 13 03:36:23 PM PDT 24 Jun 13 05:12:02 PM PDT 24 48826092840 ps
T433 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.728485820 Jun 13 03:57:58 PM PDT 24 Jun 13 04:07:16 PM PDT 24 4692695356 ps
T434 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.196175272 Jun 13 03:57:50 PM PDT 24 Jun 13 04:00:17 PM PDT 24 2290849011 ps
T689 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1495662994 Jun 13 04:05:39 PM PDT 24 Jun 13 04:38:16 PM PDT 24 8904394768 ps
T371 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.4121091243 Jun 13 04:01:21 PM PDT 24 Jun 13 04:08:30 PM PDT 24 4423289544 ps
T690 /workspace/coverage/default/2.rom_e2e_asm_init_rma.1081279092 Jun 13 04:07:21 PM PDT 24 Jun 13 05:09:22 PM PDT 24 14977190640 ps
T14 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3321047864 Jun 13 03:40:46 PM PDT 24 Jun 13 03:46:22 PM PDT 24 4396466568 ps
T226 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.158150200 Jun 13 03:54:26 PM PDT 24 Jun 13 04:04:07 PM PDT 24 3853444648 ps
T691 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1140336103 Jun 13 03:37:46 PM PDT 24 Jun 13 04:25:48 PM PDT 24 13426491580 ps
T692 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.875165111 Jun 13 03:46:21 PM PDT 24 Jun 13 05:01:11 PM PDT 24 14736779848 ps
T693 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.851419742 Jun 13 03:46:15 PM PDT 24 Jun 13 03:50:34 PM PDT 24 2613077308 ps
T694 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2651026424 Jun 13 03:42:30 PM PDT 24 Jun 13 04:11:10 PM PDT 24 9493335244 ps
T401 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1940990416 Jun 13 03:45:07 PM PDT 24 Jun 13 03:53:28 PM PDT 24 6125490096 ps
T695 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4290636979 Jun 13 03:56:36 PM PDT 24 Jun 13 04:36:37 PM PDT 24 36473951460 ps
T696 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2073681347 Jun 13 04:09:21 PM PDT 24 Jun 13 04:24:16 PM PDT 24 11372045027 ps
T412 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.751748511 Jun 13 03:50:49 PM PDT 24 Jun 13 03:53:44 PM PDT 24 2400457376 ps
T453 /workspace/coverage/default/1.rom_volatile_raw_unlock.2427345779 Jun 13 03:53:11 PM PDT 24 Jun 13 03:55:00 PM PDT 24 1877203405 ps
T697 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2013727495 Jun 13 03:42:36 PM PDT 24 Jun 13 03:52:07 PM PDT 24 8260695710 ps
T698 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2149012644 Jun 13 03:45:29 PM PDT 24 Jun 13 04:06:17 PM PDT 24 5477034115 ps
T372 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2855463967 Jun 13 03:49:53 PM PDT 24 Jun 13 03:58:13 PM PDT 24 3649934856 ps
T699 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.4199238087 Jun 13 03:57:54 PM PDT 24 Jun 13 05:03:54 PM PDT 24 14177991392 ps
T700 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1958490321 Jun 13 04:04:30 PM PDT 24 Jun 13 04:08:23 PM PDT 24 2787902083 ps
T106 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4148430536 Jun 13 03:53:42 PM PDT 24 Jun 13 04:03:09 PM PDT 24 3913552609 ps
T701 /workspace/coverage/default/1.rom_e2e_shutdown_output.3840513297 Jun 13 03:57:02 PM PDT 24 Jun 13 04:49:45 PM PDT 24 24789382856 ps
T702 /workspace/coverage/default/0.chip_sw_aes_entropy.4041234948 Jun 13 03:41:16 PM PDT 24 Jun 13 03:44:33 PM PDT 24 2665441344 ps
T459 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.372459992 Jun 13 04:11:18 PM PDT 24 Jun 13 04:17:52 PM PDT 24 3725336028 ps
T248 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3282714624 Jun 13 03:55:01 PM PDT 24 Jun 13 07:11:55 PM PDT 24 65354321367 ps
T703 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.405009570 Jun 13 04:03:33 PM PDT 24 Jun 13 04:09:13 PM PDT 24 6228655656 ps
T704 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1027445533 Jun 13 03:38:22 PM PDT 24 Jun 13 03:44:50 PM PDT 24 5835608206 ps
T705 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2524419444 Jun 13 03:44:08 PM PDT 24 Jun 13 03:54:09 PM PDT 24 4376646608 ps
T706 /workspace/coverage/default/2.rom_e2e_asm_init_dev.2588221841 Jun 13 04:07:32 PM PDT 24 Jun 13 05:15:28 PM PDT 24 14276747461 ps
T135 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2617834322 Jun 13 03:38:02 PM PDT 24 Jun 13 03:55:46 PM PDT 24 8798846716 ps
T543 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.398004831 Jun 13 04:15:05 PM PDT 24 Jun 13 04:22:17 PM PDT 24 3820637100 ps
T707 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3814370885 Jun 13 03:38:23 PM PDT 24 Jun 13 03:46:57 PM PDT 24 6887825408 ps
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