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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.56 92.77 82.83 90.06 94.87 97.53 85.31


Total test records in report: 1002
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T849 /workspace/coverage/default/3.chip_tap_straps_dev.3515345298 Jun 13 04:04:42 PM PDT 24 Jun 13 04:07:52 PM PDT 24 2891956172 ps
T314 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2871024537 Jun 13 03:36:34 PM PDT 24 Jun 13 03:51:09 PM PDT 24 5992022392 ps
T315 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.696597289 Jun 13 03:38:06 PM PDT 24 Jun 13 03:51:00 PM PDT 24 5042346776 ps
T316 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1163367482 Jun 13 03:44:34 PM PDT 24 Jun 13 04:14:17 PM PDT 24 8550224312 ps
T317 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2030465341 Jun 13 04:05:50 PM PDT 24 Jun 13 04:12:12 PM PDT 24 6975043320 ps
T318 /workspace/coverage/default/1.chip_sw_uart_tx_rx.3180308091 Jun 13 03:41:00 PM PDT 24 Jun 13 03:51:14 PM PDT 24 4300549220 ps
T319 /workspace/coverage/default/0.rom_e2e_static_critical.1688077446 Jun 13 03:45:52 PM PDT 24 Jun 13 04:45:58 PM PDT 24 16363918510 ps
T320 /workspace/coverage/default/47.chip_sw_all_escalation_resets.807326723 Jun 13 04:12:08 PM PDT 24 Jun 13 04:22:31 PM PDT 24 6558499496 ps
T321 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1619994369 Jun 13 04:06:22 PM PDT 24 Jun 13 05:09:18 PM PDT 24 13440858633 ps
T274 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3116849242 Jun 13 03:57:35 PM PDT 24 Jun 13 04:02:09 PM PDT 24 2871814340 ps
T322 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3094062127 Jun 13 03:44:52 PM PDT 24 Jun 13 03:50:42 PM PDT 24 4214673800 ps
T108 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3337405918 Jun 13 03:42:42 PM PDT 24 Jun 13 03:52:23 PM PDT 24 4445992721 ps
T455 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3627950847 Jun 13 04:13:38 PM PDT 24 Jun 13 04:20:25 PM PDT 24 3937507470 ps
T850 /workspace/coverage/default/2.chip_sw_example_manufacturer.347591757 Jun 13 03:54:03 PM PDT 24 Jun 13 03:58:40 PM PDT 24 2779429788 ps
T851 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.4013950440 Jun 13 04:01:22 PM PDT 24 Jun 13 04:10:01 PM PDT 24 5407081240 ps
T852 /workspace/coverage/default/0.chip_tap_straps_testunlock0.147327327 Jun 13 03:37:12 PM PDT 24 Jun 13 03:43:03 PM PDT 24 5156124639 ps
T336 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1486679326 Jun 13 04:01:50 PM PDT 24 Jun 13 04:05:53 PM PDT 24 2786172908 ps
T853 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3921160098 Jun 13 03:51:18 PM PDT 24 Jun 13 04:04:13 PM PDT 24 5274540360 ps
T515 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1896603075 Jun 13 04:11:58 PM PDT 24 Jun 13 04:18:30 PM PDT 24 3447867190 ps
T854 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3011939581 Jun 13 04:00:16 PM PDT 24 Jun 13 04:38:27 PM PDT 24 13045382164 ps
T855 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2881071036 Jun 13 03:36:33 PM PDT 24 Jun 13 03:54:34 PM PDT 24 5433714540 ps
T856 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1031203442 Jun 13 03:43:34 PM PDT 24 Jun 13 03:48:26 PM PDT 24 2706023688 ps
T857 /workspace/coverage/default/1.chip_sw_example_concurrency.2804297066 Jun 13 03:42:03 PM PDT 24 Jun 13 03:46:24 PM PDT 24 3271162276 ps
T858 /workspace/coverage/default/1.chip_sw_hmac_smoketest.3112139395 Jun 13 03:53:10 PM PDT 24 Jun 13 03:59:16 PM PDT 24 3679464578 ps
T859 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3209660887 Jun 13 03:50:35 PM PDT 24 Jun 13 04:01:31 PM PDT 24 3603314716 ps
T510 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.246161943 Jun 13 04:07:34 PM PDT 24 Jun 13 04:16:32 PM PDT 24 4436761000 ps
T860 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2219336608 Jun 13 03:44:36 PM PDT 24 Jun 13 04:41:49 PM PDT 24 14663165328 ps
T512 /workspace/coverage/default/69.chip_sw_all_escalation_resets.1125875542 Jun 13 04:15:23 PM PDT 24 Jun 13 04:23:55 PM PDT 24 4921138860 ps
T861 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.844403727 Jun 13 03:58:12 PM PDT 24 Jun 13 04:06:01 PM PDT 24 3563520894 ps
T862 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1017099195 Jun 13 03:55:57 PM PDT 24 Jun 13 04:00:47 PM PDT 24 3469854122 ps
T176 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1764523956 Jun 13 03:45:07 PM PDT 24 Jun 13 04:10:02 PM PDT 24 23974977600 ps
T233 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.4273159289 Jun 13 03:41:22 PM PDT 24 Jun 13 03:52:00 PM PDT 24 3775392108 ps
T863 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1309171793 Jun 13 03:43:40 PM PDT 24 Jun 13 03:48:47 PM PDT 24 3227549876 ps
T12 /workspace/coverage/default/1.chip_jtag_csr_rw.4210584816 Jun 13 03:42:10 PM PDT 24 Jun 13 04:01:26 PM PDT 24 12526780400 ps
T556 /workspace/coverage/default/91.chip_sw_all_escalation_resets.2404123462 Jun 13 04:17:39 PM PDT 24 Jun 13 04:26:10 PM PDT 24 4273895744 ps
T477 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2954486443 Jun 13 04:15:20 PM PDT 24 Jun 13 04:26:08 PM PDT 24 4873276040 ps
T864 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1742785568 Jun 13 03:36:27 PM PDT 24 Jun 13 03:44:09 PM PDT 24 6957593406 ps
T234 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2342184833 Jun 13 03:44:36 PM PDT 24 Jun 13 03:57:03 PM PDT 24 4826036918 ps
T413 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.4276356887 Jun 13 03:42:54 PM PDT 24 Jun 13 03:45:36 PM PDT 24 2481628176 ps
T37 /workspace/coverage/default/2.chip_sw_gpio.3168635938 Jun 13 03:53:29 PM PDT 24 Jun 13 04:00:49 PM PDT 24 4156888200 ps
T865 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.363958107 Jun 13 04:06:12 PM PDT 24 Jun 13 04:16:21 PM PDT 24 4544134408 ps
T245 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2714993796 Jun 13 03:35:29 PM PDT 24 Jun 13 03:44:32 PM PDT 24 6184711298 ps
T553 /workspace/coverage/default/33.chip_sw_all_escalation_resets.1090546064 Jun 13 04:10:16 PM PDT 24 Jun 13 04:20:17 PM PDT 24 5329518856 ps
T866 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2076138073 Jun 13 03:43:17 PM PDT 24 Jun 13 03:54:38 PM PDT 24 4211090100 ps
T235 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1569748897 Jun 13 03:54:21 PM PDT 24 Jun 13 04:04:22 PM PDT 24 4618512192 ps
T867 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.513062573 Jun 13 03:43:43 PM PDT 24 Jun 13 03:48:19 PM PDT 24 3223334506 ps
T495 /workspace/coverage/default/13.chip_sw_all_escalation_resets.1129400607 Jun 13 04:09:18 PM PDT 24 Jun 13 04:18:58 PM PDT 24 5743808216 ps
T868 /workspace/coverage/default/2.rom_keymgr_functest.1005736781 Jun 13 04:06:54 PM PDT 24 Jun 13 04:15:05 PM PDT 24 4956452470 ps
T869 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1929028301 Jun 13 03:49:44 PM PDT 24 Jun 13 03:56:32 PM PDT 24 4385786798 ps
T486 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.329637946 Jun 13 04:16:47 PM PDT 24 Jun 13 04:22:59 PM PDT 24 4057346060 ps
T870 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2862238338 Jun 13 03:59:42 PM PDT 24 Jun 13 04:06:45 PM PDT 24 4186039650 ps
T871 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1594437398 Jun 13 03:39:21 PM PDT 24 Jun 13 03:47:45 PM PDT 24 7079502384 ps
T872 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3988376539 Jun 13 03:45:44 PM PDT 24 Jun 13 03:48:53 PM PDT 24 2449916979 ps
T873 /workspace/coverage/default/2.chip_sw_kmac_smoketest.3576053594 Jun 13 04:04:05 PM PDT 24 Jun 13 04:08:34 PM PDT 24 2973862952 ps
T874 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2194311629 Jun 13 03:58:27 PM PDT 24 Jun 13 04:03:00 PM PDT 24 3163098960 ps
T875 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1104960918 Jun 13 04:06:22 PM PDT 24 Jun 13 04:14:23 PM PDT 24 6902723269 ps
T876 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1197770897 Jun 13 04:14:44 PM PDT 24 Jun 13 04:20:15 PM PDT 24 3505530400 ps
T877 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.959285125 Jun 13 03:40:15 PM PDT 24 Jun 13 03:44:45 PM PDT 24 3031146136 ps
T361 /workspace/coverage/default/2.chip_sw_pattgen_ios.2911519279 Jun 13 03:54:21 PM PDT 24 Jun 13 03:57:45 PM PDT 24 2803271336 ps
T878 /workspace/coverage/default/0.chip_sw_power_idle_load.2115434541 Jun 13 03:39:51 PM PDT 24 Jun 13 03:51:14 PM PDT 24 4462753976 ps
T513 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771327730 Jun 13 04:15:01 PM PDT 24 Jun 13 04:22:10 PM PDT 24 3562335342 ps
T531 /workspace/coverage/default/40.chip_sw_all_escalation_resets.2862688721 Jun 13 04:11:30 PM PDT 24 Jun 13 04:22:02 PM PDT 24 5268121968 ps
T879 /workspace/coverage/default/1.chip_sw_otbn_randomness.3416380279 Jun 13 03:43:03 PM PDT 24 Jun 13 03:58:42 PM PDT 24 5728619800 ps
T93 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1921701205 Jun 13 03:46:28 PM PDT 24 Jun 13 03:52:44 PM PDT 24 4676630212 ps
T880 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1101973880 Jun 13 04:00:36 PM PDT 24 Jun 13 04:10:31 PM PDT 24 3358408294 ps
T881 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.661547198 Jun 13 03:45:23 PM PDT 24 Jun 13 04:24:56 PM PDT 24 10080543000 ps
T882 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2030901797 Jun 13 03:39:35 PM PDT 24 Jun 13 03:45:23 PM PDT 24 5394698562 ps
T493 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.4081019908 Jun 13 04:11:26 PM PDT 24 Jun 13 04:17:21 PM PDT 24 4372991792 ps
T883 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2369939018 Jun 13 03:40:53 PM PDT 24 Jun 13 04:17:56 PM PDT 24 18372296854 ps
T884 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2757838326 Jun 13 03:40:41 PM PDT 24 Jun 13 03:50:36 PM PDT 24 3945527384 ps
T885 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1512485723 Jun 13 04:03:18 PM PDT 24 Jun 13 04:09:18 PM PDT 24 3109155240 ps
T886 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4188035166 Jun 13 03:35:29 PM PDT 24 Jun 13 03:43:04 PM PDT 24 4647901916 ps
T260 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2651506454 Jun 13 03:41:19 PM PDT 24 Jun 13 05:16:35 PM PDT 24 50293990616 ps
T887 /workspace/coverage/default/2.rom_e2e_smoke.1481288748 Jun 13 04:07:08 PM PDT 24 Jun 13 05:03:37 PM PDT 24 14559593720 ps
T888 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2125124359 Jun 13 03:43:48 PM PDT 24 Jun 13 04:34:22 PM PDT 24 9833826816 ps
T889 /workspace/coverage/default/0.chip_sw_aes_enc.2335212978 Jun 13 03:39:33 PM PDT 24 Jun 13 03:45:03 PM PDT 24 2753995312 ps
T890 /workspace/coverage/default/1.chip_sw_csrng_kat_test.3509616324 Jun 13 03:44:21 PM PDT 24 Jun 13 03:48:02 PM PDT 24 2780318840 ps
T299 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3124425901 Jun 13 03:40:12 PM PDT 24 Jun 13 04:09:26 PM PDT 24 12061830848 ps
T505 /workspace/coverage/default/79.chip_sw_all_escalation_resets.3330391496 Jun 13 04:15:04 PM PDT 24 Jun 13 04:24:01 PM PDT 24 4477012370 ps
T891 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2092449082 Jun 13 03:38:02 PM PDT 24 Jun 13 03:58:25 PM PDT 24 7632941440 ps
T503 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2206724034 Jun 13 04:14:57 PM PDT 24 Jun 13 04:22:43 PM PDT 24 4130301538 ps
T892 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.365072534 Jun 13 03:46:00 PM PDT 24 Jun 13 03:53:11 PM PDT 24 3937607610 ps
T893 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.4050228539 Jun 13 04:06:37 PM PDT 24 Jun 13 05:26:27 PM PDT 24 22975147800 ps
T894 /workspace/coverage/default/0.chip_sw_csrng_kat_test.2328098010 Jun 13 03:37:06 PM PDT 24 Jun 13 03:42:22 PM PDT 24 2520497914 ps
T47 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1164177037 Jun 13 03:35:17 PM PDT 24 Jun 13 03:39:59 PM PDT 24 5995455780 ps
T895 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2644631751 Jun 13 03:43:50 PM PDT 24 Jun 13 03:55:25 PM PDT 24 4307781126 ps
T896 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3003630651 Jun 13 03:58:15 PM PDT 24 Jun 13 04:24:03 PM PDT 24 7019014236 ps
T289 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4098376262 Jun 13 04:14:45 PM PDT 24 Jun 13 04:21:59 PM PDT 24 3961321772 ps
T897 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.644696559 Jun 13 03:39:59 PM PDT 24 Jun 13 03:59:27 PM PDT 24 8948606904 ps
T898 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1920949470 Jun 13 03:42:38 PM PDT 24 Jun 13 03:47:00 PM PDT 24 2694025808 ps
T899 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2051914011 Jun 13 03:56:51 PM PDT 24 Jun 13 04:04:32 PM PDT 24 6354696580 ps
T511 /workspace/coverage/default/48.chip_sw_all_escalation_resets.841740479 Jun 13 04:11:50 PM PDT 24 Jun 13 04:22:19 PM PDT 24 5581963632 ps
T900 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2522633056 Jun 13 04:07:23 PM PDT 24 Jun 13 05:02:28 PM PDT 24 16931712910 ps
T191 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3467343906 Jun 13 03:44:22 PM PDT 24 Jun 13 06:50:52 PM PDT 24 59158054104 ps
T901 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3869733091 Jun 13 03:45:58 PM PDT 24 Jun 13 05:25:13 PM PDT 24 22474144148 ps
T902 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.315613081 Jun 13 03:46:18 PM PDT 24 Jun 13 03:54:24 PM PDT 24 5295871618 ps
T903 /workspace/coverage/default/1.chip_sw_example_rom.1663342494 Jun 13 03:38:45 PM PDT 24 Jun 13 03:41:09 PM PDT 24 2688909696 ps
T904 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2454401986 Jun 13 03:38:10 PM PDT 24 Jun 13 04:09:08 PM PDT 24 7624937076 ps
T905 /workspace/coverage/default/0.chip_sw_usbdev_stream.3214161179 Jun 13 03:39:18 PM PDT 24 Jun 13 04:51:56 PM PDT 24 18985998504 ps
T337 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.617217562 Jun 13 03:38:02 PM PDT 24 Jun 13 03:42:10 PM PDT 24 2137838532 ps
T906 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1210692029 Jun 13 03:43:25 PM PDT 24 Jun 13 03:52:56 PM PDT 24 4370038728 ps
T907 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3185845191 Jun 13 03:44:03 PM PDT 24 Jun 13 04:07:24 PM PDT 24 8461338907 ps
T908 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1672708081 Jun 13 03:57:56 PM PDT 24 Jun 13 04:32:54 PM PDT 24 26110785340 ps
T909 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3972863759 Jun 13 04:08:01 PM PDT 24 Jun 13 05:09:11 PM PDT 24 16508861946 ps
T94 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2692949227 Jun 13 03:38:12 PM PDT 24 Jun 13 03:46:05 PM PDT 24 5188706840 ps
T910 /workspace/coverage/default/2.chip_tap_straps_prod.2171809664 Jun 13 04:00:37 PM PDT 24 Jun 13 04:04:25 PM PDT 24 3483296865 ps
T911 /workspace/coverage/default/0.chip_sw_example_concurrency.797847047 Jun 13 03:36:43 PM PDT 24 Jun 13 03:42:13 PM PDT 24 2904029208 ps
T912 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3158210110 Jun 13 03:57:44 PM PDT 24 Jun 13 04:01:18 PM PDT 24 2389669128 ps
T913 /workspace/coverage/default/0.chip_sw_hmac_oneshot.2753344504 Jun 13 03:42:12 PM PDT 24 Jun 13 03:48:07 PM PDT 24 2934865780 ps
T914 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.806757868 Jun 13 03:45:35 PM PDT 24 Jun 13 03:50:24 PM PDT 24 2516364012 ps
T915 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3233089753 Jun 13 04:03:53 PM PDT 24 Jun 13 04:11:28 PM PDT 24 5349121796 ps
T916 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1551289372 Jun 13 03:41:29 PM PDT 24 Jun 13 03:44:39 PM PDT 24 2631388080 ps
T917 /workspace/coverage/default/1.chip_sw_aes_smoketest.3471442132 Jun 13 03:51:42 PM PDT 24 Jun 13 03:57:53 PM PDT 24 3597102150 ps
T918 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2675773360 Jun 13 04:01:15 PM PDT 24 Jun 13 04:13:04 PM PDT 24 3958384634 ps
T154 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3079474988 Jun 13 03:40:20 PM PDT 24 Jun 13 04:49:23 PM PDT 24 42876664922 ps
T919 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3339698575 Jun 13 04:04:27 PM PDT 24 Jun 13 04:14:28 PM PDT 24 4239110888 ps
T920 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.532258801 Jun 13 03:35:55 PM PDT 24 Jun 13 03:51:10 PM PDT 24 10230740472 ps
T921 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1208418681 Jun 13 03:51:21 PM PDT 24 Jun 13 04:11:36 PM PDT 24 6736457570 ps
T922 /workspace/coverage/default/2.chip_sw_power_idle_load.2129848071 Jun 13 04:02:33 PM PDT 24 Jun 13 04:14:45 PM PDT 24 3717378932 ps
T923 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3077440194 Jun 13 03:53:13 PM PDT 24 Jun 13 06:45:34 PM PDT 24 58238158164 ps
T924 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2295560133 Jun 13 04:05:12 PM PDT 24 Jun 13 04:09:02 PM PDT 24 2737862840 ps
T925 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3705719628 Jun 13 03:41:35 PM PDT 24 Jun 13 03:47:59 PM PDT 24 5554647676 ps
T290 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1334019453 Jun 13 04:04:55 PM PDT 24 Jun 13 04:15:47 PM PDT 24 5509885318 ps
T926 /workspace/coverage/default/98.chip_sw_all_escalation_resets.1081749616 Jun 13 04:16:31 PM PDT 24 Jun 13 04:26:27 PM PDT 24 5315077624 ps
T927 /workspace/coverage/default/66.chip_sw_all_escalation_resets.4093620974 Jun 13 04:13:30 PM PDT 24 Jun 13 04:22:47 PM PDT 24 5961776520 ps
T928 /workspace/coverage/default/2.chip_tap_straps_testunlock0.4134285778 Jun 13 04:02:03 PM PDT 24 Jun 13 04:07:58 PM PDT 24 4443559344 ps
T516 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3233344041 Jun 13 04:15:29 PM PDT 24 Jun 13 04:22:36 PM PDT 24 3901048320 ps
T929 /workspace/coverage/default/1.chip_tap_straps_prod.1021111719 Jun 13 03:51:38 PM PDT 24 Jun 13 03:54:33 PM PDT 24 3592846365 ps
T198 /workspace/coverage/default/22.chip_sw_all_escalation_resets.3362802857 Jun 13 04:10:09 PM PDT 24 Jun 13 04:19:35 PM PDT 24 4392695616 ps
T930 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2491596112 Jun 13 04:04:50 PM PDT 24 Jun 13 04:09:06 PM PDT 24 2540586216 ps
T931 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3876469786 Jun 13 03:36:52 PM PDT 24 Jun 13 03:41:13 PM PDT 24 2602958172 ps
T932 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3767790982 Jun 13 03:55:05 PM PDT 24 Jun 13 04:07:49 PM PDT 24 4820262748 ps
T933 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.637297387 Jun 13 03:56:29 PM PDT 24 Jun 13 04:10:35 PM PDT 24 10010446568 ps
T934 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.943944062 Jun 13 03:38:21 PM PDT 24 Jun 13 03:40:22 PM PDT 24 1880610508 ps
T935 /workspace/coverage/default/86.chip_sw_all_escalation_resets.1367522105 Jun 13 04:15:57 PM PDT 24 Jun 13 04:26:21 PM PDT 24 4856375124 ps
T532 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1498695560 Jun 13 04:11:16 PM PDT 24 Jun 13 04:18:36 PM PDT 24 3832086024 ps
T936 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2832111372 Jun 13 03:38:39 PM PDT 24 Jun 13 04:15:44 PM PDT 24 26057808453 ps
T393 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2213113126 Jun 13 04:20:12 PM PDT 24 Jun 13 04:27:11 PM PDT 24 4245385808 ps
T937 /workspace/coverage/default/1.rom_e2e_asm_init_prod.352471655 Jun 13 03:56:51 PM PDT 24 Jun 13 05:07:18 PM PDT 24 14493613033 ps
T938 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4090546372 Jun 13 03:41:10 PM PDT 24 Jun 13 03:48:32 PM PDT 24 4180132655 ps
T939 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.994160206 Jun 13 03:37:50 PM PDT 24 Jun 13 03:43:42 PM PDT 24 2901576960 ps
T940 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2378615250 Jun 13 03:47:17 PM PDT 24 Jun 13 04:17:58 PM PDT 24 23259289522 ps
T941 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4150725101 Jun 13 03:36:17 PM PDT 24 Jun 13 03:59:24 PM PDT 24 7232137776 ps
T942 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1828838066 Jun 13 03:44:23 PM PDT 24 Jun 13 03:53:01 PM PDT 24 3231579028 ps
T943 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2320833713 Jun 13 03:45:47 PM PDT 24 Jun 13 04:39:05 PM PDT 24 20261896099 ps
T944 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3936289584 Jun 13 04:01:29 PM PDT 24 Jun 13 04:11:46 PM PDT 24 4911304180 ps
T945 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3327858466 Jun 13 03:55:47 PM PDT 24 Jun 13 03:58:50 PM PDT 24 3025470756 ps
T946 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3790606672 Jun 13 03:48:49 PM PDT 24 Jun 13 04:54:19 PM PDT 24 14467116536 ps
T517 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.832266021 Jun 13 04:12:35 PM PDT 24 Jun 13 04:20:12 PM PDT 24 4089915900 ps
T947 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.821757432 Jun 13 03:36:47 PM PDT 24 Jun 13 03:47:07 PM PDT 24 4334202376 ps
T948 /workspace/coverage/default/0.chip_sw_aon_timer_irq.234414111 Jun 13 03:37:23 PM PDT 24 Jun 13 03:46:26 PM PDT 24 4588853000 ps
T230 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3569833941 Jun 13 03:41:04 PM PDT 24 Jun 13 03:51:53 PM PDT 24 4818708860 ps
T949 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3734956831 Jun 13 04:14:07 PM PDT 24 Jun 13 04:25:49 PM PDT 24 5411202832 ps
T489 /workspace/coverage/default/1.chip_sw_all_escalation_resets.3979193389 Jun 13 03:42:13 PM PDT 24 Jun 13 03:56:02 PM PDT 24 6397162142 ps
T950 /workspace/coverage/default/0.chip_sw_edn_sw_mode.1893650798 Jun 13 03:37:38 PM PDT 24 Jun 13 04:11:28 PM PDT 24 8458291432 ps
T488 /workspace/coverage/default/78.chip_sw_all_escalation_resets.675244550 Jun 13 04:14:23 PM PDT 24 Jun 13 04:26:04 PM PDT 24 6397890150 ps
T951 /workspace/coverage/default/1.chip_sw_power_idle_load.371070039 Jun 13 03:51:32 PM PDT 24 Jun 13 04:00:55 PM PDT 24 4252226766 ps
T520 /workspace/coverage/default/93.chip_sw_all_escalation_resets.1849548942 Jun 13 04:16:16 PM PDT 24 Jun 13 04:27:27 PM PDT 24 5665458648 ps
T952 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.77945224 Jun 13 03:44:21 PM PDT 24 Jun 13 04:06:34 PM PDT 24 8218519377 ps
T953 /workspace/coverage/default/0.chip_sw_uart_smoketest.3290718569 Jun 13 03:41:25 PM PDT 24 Jun 13 03:46:16 PM PDT 24 3591581724 ps
T954 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.431116075 Jun 13 04:00:06 PM PDT 24 Jun 13 04:13:25 PM PDT 24 4715037880 ps
T955 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.781599221 Jun 13 03:36:28 PM PDT 24 Jun 13 03:42:40 PM PDT 24 2866760391 ps
T24 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3023554050 Jun 13 03:43:09 PM PDT 24 Jun 13 03:48:49 PM PDT 24 3599218902 ps
T177 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1057197158 Jun 13 04:00:31 PM PDT 24 Jun 13 04:22:15 PM PDT 24 22478303228 ps
T187 /workspace/coverage/default/1.chip_plic_all_irqs_0.1998922770 Jun 13 03:48:18 PM PDT 24 Jun 13 04:10:55 PM PDT 24 6734247266 ps
T956 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.734064704 Jun 13 03:56:00 PM PDT 24 Jun 13 04:01:14 PM PDT 24 4801121305 ps
T155 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2043133568 Jun 13 03:41:13 PM PDT 24 Jun 13 04:43:05 PM PDT 24 41828507240 ps
T957 /workspace/coverage/default/0.rom_volatile_raw_unlock.3003345466 Jun 13 03:46:10 PM PDT 24 Jun 13 03:48:07 PM PDT 24 1854211389 ps
T217 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1581951420 Jun 13 03:37:28 PM PDT 24 Jun 13 05:01:23 PM PDT 24 42563343297 ps
T958 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.500937454 Jun 13 03:37:38 PM PDT 24 Jun 13 03:52:15 PM PDT 24 5913969294 ps
T959 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1945253964 Jun 13 03:42:26 PM PDT 24 Jun 13 03:46:49 PM PDT 24 2653952834 ps
T960 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.607939485 Jun 13 04:14:53 PM PDT 24 Jun 13 04:20:35 PM PDT 24 2917036160 ps
T300 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1593522173 Jun 13 03:55:59 PM PDT 24 Jun 13 04:04:55 PM PDT 24 5630962740 ps
T457 /workspace/coverage/default/83.chip_sw_all_escalation_resets.2891441675 Jun 13 04:15:17 PM PDT 24 Jun 13 04:23:27 PM PDT 24 5664338152 ps
T961 /workspace/coverage/default/1.chip_sw_hmac_oneshot.2246844261 Jun 13 03:47:31 PM PDT 24 Jun 13 03:52:33 PM PDT 24 3089055010 ps
T962 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2497302881 Jun 13 03:56:16 PM PDT 24 Jun 13 04:20:26 PM PDT 24 8139498968 ps
T963 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3664420071 Jun 13 03:36:08 PM PDT 24 Jun 13 03:53:46 PM PDT 24 5513638112 ps
T964 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1208811317 Jun 13 03:47:14 PM PDT 24 Jun 13 05:34:15 PM PDT 24 21638219338 ps
T965 /workspace/coverage/default/0.chip_sw_rv_timer_irq.579426022 Jun 13 03:42:36 PM PDT 24 Jun 13 03:48:29 PM PDT 24 3326624392 ps
T966 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2455937572 Jun 13 03:57:00 PM PDT 24 Jun 13 04:10:39 PM PDT 24 5093467448 ps
T967 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.974547386 Jun 13 04:01:21 PM PDT 24 Jun 13 04:05:13 PM PDT 24 2989730134 ps
T968 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.26544617 Jun 13 03:39:43 PM PDT 24 Jun 13 03:49:44 PM PDT 24 4890317432 ps
T969 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1826161531 Jun 13 03:37:18 PM PDT 24 Jun 13 04:04:41 PM PDT 24 8801883100 ps
T355 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3619087192 Jun 13 03:38:57 PM PDT 24 Jun 13 04:50:32 PM PDT 24 14392558336 ps
T970 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2850755742 Jun 13 04:03:34 PM PDT 24 Jun 13 04:08:41 PM PDT 24 3054022498 ps
T483 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3778846323 Jun 13 04:13:25 PM PDT 24 Jun 13 04:20:11 PM PDT 24 3831858366 ps
T971 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.407257020 Jun 13 03:41:23 PM PDT 24 Jun 13 04:00:26 PM PDT 24 5977835865 ps
T525 /workspace/coverage/default/49.chip_sw_all_escalation_resets.556110521 Jun 13 04:14:02 PM PDT 24 Jun 13 04:22:51 PM PDT 24 5291830104 ps
T972 /workspace/coverage/default/3.chip_tap_straps_prod.3292167573 Jun 13 04:04:20 PM PDT 24 Jun 13 04:32:43 PM PDT 24 14376590160 ps
T301 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2221801429 Jun 13 03:36:59 PM PDT 24 Jun 13 03:46:13 PM PDT 24 7007845400 ps
T162 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.3950665566 Jun 13 03:38:14 PM PDT 24 Jun 13 05:42:06 PM PDT 24 31853826984 ps
T973 /workspace/coverage/default/2.chip_sw_csrng_smoketest.368440579 Jun 13 04:05:24 PM PDT 24 Jun 13 04:09:06 PM PDT 24 2988275820 ps
T974 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.92043467 Jun 13 03:52:51 PM PDT 24 Jun 13 04:03:18 PM PDT 24 6310800336 ps
T975 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2228012999 Jun 13 03:39:50 PM PDT 24 Jun 13 03:47:19 PM PDT 24 2889723328 ps
T428 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1826090393 Jun 13 03:42:30 PM PDT 24 Jun 13 04:10:29 PM PDT 24 21886464850 ps
T976 /workspace/coverage/default/41.chip_sw_all_escalation_resets.1284489816 Jun 13 04:11:05 PM PDT 24 Jun 13 04:21:35 PM PDT 24 6030460180 ps
T480 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3900859765 Jun 13 04:13:14 PM PDT 24 Jun 13 04:20:34 PM PDT 24 4188075212 ps
T977 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2874624701 Jun 13 03:37:59 PM PDT 24 Jun 13 04:41:51 PM PDT 24 18721646126 ps
T978 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2161825031 Jun 13 03:40:04 PM PDT 24 Jun 13 03:59:43 PM PDT 24 12067688120 ps
T163 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3400191649 Jun 13 03:38:45 PM PDT 24 Jun 13 03:45:54 PM PDT 24 3739030612 ps
T521 /workspace/coverage/default/54.chip_sw_all_escalation_resets.1855673189 Jun 13 04:13:31 PM PDT 24 Jun 13 04:22:09 PM PDT 24 5878745132 ps
T979 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2769447546 Jun 13 04:07:23 PM PDT 24 Jun 13 04:27:30 PM PDT 24 12326462234 ps
T980 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2508900019 Jun 13 03:45:26 PM PDT 24 Jun 13 04:29:37 PM PDT 24 11403264658 ps
T981 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.4156013635 Jun 13 04:04:30 PM PDT 24 Jun 13 04:07:58 PM PDT 24 2871657404 ps
T536 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1506857850 Jun 13 04:16:06 PM PDT 24 Jun 13 04:29:02 PM PDT 24 4934954418 ps
T116 /workspace/coverage/default/2.chip_jtag_mem_access.774336207 Jun 13 03:53:48 PM PDT 24 Jun 13 04:21:23 PM PDT 24 13236364665 ps
T982 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2733437726 Jun 13 04:06:18 PM PDT 24 Jun 13 04:17:15 PM PDT 24 4517183328 ps
T302 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2609043433 Jun 13 03:41:50 PM PDT 24 Jun 13 03:53:20 PM PDT 24 6561430452 ps
T983 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2977017451 Jun 13 03:39:51 PM PDT 24 Jun 13 03:43:30 PM PDT 24 2917868566 ps
T183 /workspace/coverage/default/1.chip_plic_all_irqs_20.3677500910 Jun 13 03:49:10 PM PDT 24 Jun 13 04:04:38 PM PDT 24 5179087464 ps
T984 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.479561697 Jun 13 04:07:14 PM PDT 24 Jun 13 04:13:54 PM PDT 24 5420413170 ps
T500 /workspace/coverage/default/9.chip_sw_all_escalation_resets.998341023 Jun 13 04:07:49 PM PDT 24 Jun 13 04:17:45 PM PDT 24 4420099624 ps
T218 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1260497 Jun 13 03:40:05 PM PDT 24 Jun 13 05:01:09 PM PDT 24 43974011807 ps
T985 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.4103001310 Jun 13 03:49:03 PM PDT 24 Jun 13 03:58:03 PM PDT 24 3314342412 ps
T549 /workspace/coverage/default/34.chip_sw_all_escalation_resets.873950732 Jun 13 04:11:48 PM PDT 24 Jun 13 04:20:15 PM PDT 24 5921895336 ps
T986 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3346081928 Jun 13 03:43:38 PM PDT 24 Jun 13 04:55:17 PM PDT 24 14288646286 ps
T987 /workspace/coverage/default/0.chip_sw_kmac_idle.3831703966 Jun 13 03:37:23 PM PDT 24 Jun 13 03:41:27 PM PDT 24 2790395480 ps
T988 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3100302798 Jun 13 03:43:01 PM PDT 24 Jun 13 04:40:35 PM PDT 24 14669207890 ps
T989 /workspace/coverage/default/1.chip_sw_uart_smoketest.565806363 Jun 13 03:53:55 PM PDT 24 Jun 13 03:58:22 PM PDT 24 2509993874 ps
T990 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.995116619 Jun 13 03:40:34 PM PDT 24 Jun 13 03:47:53 PM PDT 24 4972588024 ps
T275 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3951367566 Jun 13 03:37:28 PM PDT 24 Jun 13 03:41:54 PM PDT 24 2789477500 ps
T991 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1521584214 Jun 13 03:37:07 PM PDT 24 Jun 13 03:52:55 PM PDT 24 5640801028 ps
T15 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3782325641 Jun 13 03:54:33 PM PDT 24 Jun 13 03:58:34 PM PDT 24 2725173272 ps
T992 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4037089720 Jun 13 03:49:17 PM PDT 24 Jun 13 07:27:14 PM PDT 24 256232404490 ps
T356 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.121816013 Jun 13 03:45:25 PM PDT 24 Jun 13 04:34:25 PM PDT 24 11865671896 ps
T993 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2498068759 Jun 13 03:56:46 PM PDT 24 Jun 13 04:05:29 PM PDT 24 7466064360 ps
T526 /workspace/coverage/default/12.chip_sw_all_escalation_resets.3339095870 Jun 13 04:10:15 PM PDT 24 Jun 13 04:23:27 PM PDT 24 5745186488 ps
T487 /workspace/coverage/default/23.chip_sw_all_escalation_resets.3929541245 Jun 13 04:12:33 PM PDT 24 Jun 13 04:21:00 PM PDT 24 4546301000 ps
T262 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.36252514 Jun 13 03:55:00 PM PDT 24 Jun 13 05:35:36 PM PDT 24 48200929767 ps
T232 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.477546887 Jun 13 03:54:32 PM PDT 24 Jun 13 04:04:26 PM PDT 24 5202308596 ps
T994 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.118265173 Jun 13 04:05:42 PM PDT 24 Jun 13 04:15:19 PM PDT 24 4221443595 ps
T995 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2358896710 Jun 13 03:58:25 PM PDT 24 Jun 13 04:23:37 PM PDT 24 8100782410 ps
T996 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1242510502 Jun 13 03:47:48 PM PDT 24 Jun 13 04:56:05 PM PDT 24 14576362534 ps
T997 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3283792039 Jun 13 04:04:10 PM PDT 24 Jun 13 04:29:48 PM PDT 24 10212242164 ps
T491 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2431743322 Jun 13 04:09:19 PM PDT 24 Jun 13 04:15:59 PM PDT 24 3728617608 ps
T998 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2764622354 Jun 13 03:50:48 PM PDT 24 Jun 13 04:48:31 PM PDT 24 14489188650 ps
T523 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1824757753 Jun 13 04:09:10 PM PDT 24 Jun 13 04:18:49 PM PDT 24 5142829766 ps
T411 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3734791585 Jun 13 04:01:09 PM PDT 24 Jun 13 04:04:33 PM PDT 24 2539577808 ps
T999 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2218985689 Jun 13 03:50:15 PM PDT 24 Jun 13 04:06:20 PM PDT 24 8170077052 ps
T1000 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3263529230 Jun 13 04:00:34 PM PDT 24 Jun 13 04:10:49 PM PDT 24 3982790042 ps
T1001 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2727505043 Jun 13 04:10:00 PM PDT 24 Jun 13 04:50:00 PM PDT 24 13002173436 ps
T1002 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.686208211 Jun 13 03:55:28 PM PDT 24 Jun 13 04:01:27 PM PDT 24 2795983544 ps
T38 /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.107457228 Jun 13 03:28:13 PM PDT 24 Jun 13 03:31:07 PM PDT 24 4469066753 ps
T39 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1161616707 Jun 13 03:28:12 PM PDT 24 Jun 13 03:32:43 PM PDT 24 4850336750 ps
T40 /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3522921108 Jun 13 03:28:12 PM PDT 24 Jun 13 03:33:08 PM PDT 24 4590785521 ps
T237 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2394387384 Jun 13 03:28:15 PM PDT 24 Jun 13 03:32:44 PM PDT 24 4303864066 ps
T238 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3208144006 Jun 13 03:28:13 PM PDT 24 Jun 13 03:31:38 PM PDT 24 4433348312 ps
T239 /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2825504370 Jun 13 03:28:14 PM PDT 24 Jun 13 03:34:02 PM PDT 24 5642527405 ps
T244 /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.104823513 Jun 13 03:28:14 PM PDT 24 Jun 13 03:31:13 PM PDT 24 4192209841 ps
T240 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.239407007 Jun 13 03:28:14 PM PDT 24 Jun 13 03:32:01 PM PDT 24 4488268188 ps
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