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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.23 95.53 94.17 95.47 95.13 97.53 99.57


Total test records in report: 2882
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T371 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1514826973 Jun 23 07:51:31 PM PDT 24 Jun 23 08:03:57 PM PDT 24 4826176378 ps
T113 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.643944229 Jun 23 07:51:41 PM PDT 24 Jun 23 08:01:30 PM PDT 24 4032257642 ps
T372 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2998252499 Jun 23 08:07:06 PM PDT 24 Jun 23 08:27:09 PM PDT 24 9178963660 ps
T51 /workspace/coverage/default/1.chip_sw_spi_device_tpm.2879249743 Jun 23 07:54:48 PM PDT 24 Jun 23 08:01:43 PM PDT 24 3572956984 ps
T373 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4064854950 Jun 23 08:08:45 PM PDT 24 Jun 23 08:26:39 PM PDT 24 16411254300 ps
T374 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1054636685 Jun 23 08:09:47 PM PDT 24 Jun 23 08:19:31 PM PDT 24 5343688472 ps
T266 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1820269566 Jun 23 08:01:10 PM PDT 24 Jun 23 08:10:28 PM PDT 24 9159383599 ps
T375 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.770904407 Jun 23 08:01:48 PM PDT 24 Jun 23 08:15:08 PM PDT 24 4752481096 ps
T376 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2372364681 Jun 23 08:02:41 PM PDT 24 Jun 23 09:02:03 PM PDT 24 15428570488 ps
T36 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2664720526 Jun 23 07:57:06 PM PDT 24 Jun 23 08:28:30 PM PDT 24 21522728410 ps
T841 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.352954739 Jun 23 08:21:23 PM PDT 24 Jun 23 08:27:17 PM PDT 24 3224808038 ps
T736 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1962635643 Jun 23 08:21:51 PM PDT 24 Jun 23 08:29:07 PM PDT 24 3858321368 ps
T201 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2138434576 Jun 23 08:09:32 PM PDT 24 Jun 23 08:20:52 PM PDT 24 4795646371 ps
T961 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.971987484 Jun 23 07:49:06 PM PDT 24 Jun 23 08:22:26 PM PDT 24 32594221247 ps
T962 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3330678207 Jun 23 08:24:25 PM PDT 24 Jun 23 08:30:43 PM PDT 24 3590988190 ps
T963 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.606977518 Jun 23 07:48:38 PM PDT 24 Jun 23 08:04:33 PM PDT 24 9504294183 ps
T327 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.4191567260 Jun 23 08:13:45 PM PDT 24 Jun 23 08:20:49 PM PDT 24 3834291070 ps
T804 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1959006135 Jun 23 08:24:47 PM PDT 24 Jun 23 08:29:56 PM PDT 24 3440760200 ps
T964 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.4291140225 Jun 23 07:51:24 PM PDT 24 Jun 23 08:18:53 PM PDT 24 6961601756 ps
T965 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1982672620 Jun 23 08:26:16 PM PDT 24 Jun 23 08:32:41 PM PDT 24 4243640102 ps
T966 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1057370979 Jun 23 08:09:13 PM PDT 24 Jun 23 08:24:25 PM PDT 24 5864984677 ps
T967 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3320097698 Jun 23 08:10:25 PM PDT 24 Jun 23 08:16:49 PM PDT 24 4071572840 ps
T502 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2799951982 Jun 23 07:59:58 PM PDT 24 Jun 23 08:14:09 PM PDT 24 5534019718 ps
T173 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3411054041 Jun 23 07:52:56 PM PDT 24 Jun 23 07:58:13 PM PDT 24 3494556456 ps
T775 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.362371457 Jun 23 08:18:51 PM PDT 24 Jun 23 08:26:33 PM PDT 24 3819805756 ps
T968 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2767348155 Jun 23 08:16:16 PM PDT 24 Jun 23 08:22:36 PM PDT 24 2809108632 ps
T332 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2530366058 Jun 23 07:50:55 PM PDT 24 Jun 23 08:03:17 PM PDT 24 4619299364 ps
T349 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2843941030 Jun 23 07:52:27 PM PDT 24 Jun 23 08:47:10 PM PDT 24 30524148090 ps
T969 /workspace/coverage/default/2.chip_sw_hmac_oneshot.3828680036 Jun 23 08:11:03 PM PDT 24 Jun 23 08:17:13 PM PDT 24 3380578560 ps
T970 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3888089716 Jun 23 08:14:29 PM PDT 24 Jun 23 08:19:17 PM PDT 24 3085920870 ps
T334 /workspace/coverage/default/2.chip_sw_uart_tx_rx.2552102932 Jun 23 08:06:34 PM PDT 24 Jun 23 08:16:54 PM PDT 24 3425809740 ps
T971 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3487049386 Jun 23 08:08:44 PM PDT 24 Jun 23 09:07:11 PM PDT 24 17028112050 ps
T105 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.759578929 Jun 23 08:04:41 PM PDT 24 Jun 23 09:23:43 PM PDT 24 27551139765 ps
T972 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3505898334 Jun 23 08:10:24 PM PDT 24 Jun 23 08:49:57 PM PDT 24 24007728243 ps
T973 /workspace/coverage/default/0.rom_e2e_smoke.4249011476 Jun 23 07:57:01 PM PDT 24 Jun 23 09:20:04 PM PDT 24 15119255900 ps
T394 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2016876700 Jun 23 08:06:55 PM PDT 24 Jun 23 08:13:09 PM PDT 24 5542304632 ps
T65 /workspace/coverage/default/3.chip_tap_straps_rma.2840726137 Jun 23 08:17:35 PM PDT 24 Jun 23 08:24:37 PM PDT 24 4759462346 ps
T974 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.931377270 Jun 23 08:18:35 PM PDT 24 Jun 23 08:28:48 PM PDT 24 4625737420 ps
T975 /workspace/coverage/default/1.rom_keymgr_functest.2676868115 Jun 23 08:04:36 PM PDT 24 Jun 23 08:12:59 PM PDT 24 5313343560 ps
T244 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2796952970 Jun 23 07:53:24 PM PDT 24 Jun 23 07:56:59 PM PDT 24 2804930870 ps
T976 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3782430195 Jun 23 08:10:00 PM PDT 24 Jun 23 08:19:04 PM PDT 24 5258255744 ps
T977 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3152072444 Jun 23 08:11:45 PM PDT 24 Jun 23 08:22:49 PM PDT 24 3583297090 ps
T759 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4259008418 Jun 23 08:20:24 PM PDT 24 Jun 23 08:27:33 PM PDT 24 3987569032 ps
T978 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.117294025 Jun 23 08:18:40 PM PDT 24 Jun 23 09:18:16 PM PDT 24 16873471210 ps
T979 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3166040886 Jun 23 07:59:12 PM PDT 24 Jun 23 08:55:54 PM PDT 24 11687546927 ps
T267 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.409655681 Jun 23 08:17:26 PM PDT 24 Jun 23 08:31:07 PM PDT 24 6083014088 ps
T272 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.4013552339 Jun 23 08:12:21 PM PDT 24 Jun 23 08:15:27 PM PDT 24 2710941192 ps
T273 /workspace/coverage/default/91.chip_sw_all_escalation_resets.4273377335 Jun 23 08:25:41 PM PDT 24 Jun 23 08:35:24 PM PDT 24 5054670440 ps
T262 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3840636194 Jun 23 07:55:12 PM PDT 24 Jun 23 07:59:26 PM PDT 24 3821555683 ps
T274 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3965812430 Jun 23 08:23:20 PM PDT 24 Jun 23 08:29:27 PM PDT 24 3469409160 ps
T275 /workspace/coverage/default/0.chip_sw_uart_smoketest.114044959 Jun 23 07:54:55 PM PDT 24 Jun 23 08:00:22 PM PDT 24 3272712136 ps
T197 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2355719681 Jun 23 07:56:44 PM PDT 24 Jun 23 11:41:50 PM PDT 24 78885691572 ps
T276 /workspace/coverage/default/93.chip_sw_all_escalation_resets.4128635685 Jun 23 08:26:15 PM PDT 24 Jun 23 08:33:35 PM PDT 24 3941052192 ps
T277 /workspace/coverage/default/2.chip_sw_example_manufacturer.2992880857 Jun 23 08:06:14 PM PDT 24 Jun 23 08:09:48 PM PDT 24 2846862696 ps
T278 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2544621468 Jun 23 08:03:08 PM PDT 24 Jun 23 08:19:54 PM PDT 24 7234423378 ps
T216 /workspace/coverage/default/0.chip_tap_straps_prod.573762975 Jun 23 07:51:01 PM PDT 24 Jun 23 08:10:21 PM PDT 24 10024493795 ps
T52 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1604899124 Jun 23 07:50:56 PM PDT 24 Jun 23 07:58:57 PM PDT 24 3259138842 ps
T980 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3145385797 Jun 23 08:19:20 PM PDT 24 Jun 23 08:42:24 PM PDT 24 8783494660 ps
T40 /workspace/coverage/default/0.chip_sw_gpio.832503055 Jun 23 07:50:07 PM PDT 24 Jun 23 07:59:10 PM PDT 24 3782581620 ps
T803 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3056980687 Jun 23 08:19:08 PM PDT 24 Jun 23 08:25:57 PM PDT 24 3434432460 ps
T369 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1841653087 Jun 23 08:04:33 PM PDT 24 Jun 23 08:12:56 PM PDT 24 6226397960 ps
T981 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.612626345 Jun 23 08:10:47 PM PDT 24 Jun 23 08:20:15 PM PDT 24 4973328350 ps
T982 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3922866742 Jun 23 08:19:29 PM PDT 24 Jun 23 08:34:22 PM PDT 24 11413506212 ps
T398 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.219204703 Jun 23 08:03:04 PM PDT 24 Jun 23 08:12:40 PM PDT 24 5000864264 ps
T412 /workspace/coverage/default/23.chip_sw_all_escalation_resets.4029105751 Jun 23 08:20:59 PM PDT 24 Jun 23 08:29:42 PM PDT 24 6129843280 ps
T413 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1172645732 Jun 23 08:16:09 PM PDT 24 Jun 23 08:20:37 PM PDT 24 3028867844 ps
T414 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2763501695 Jun 23 08:24:56 PM PDT 24 Jun 23 08:30:52 PM PDT 24 3459111604 ps
T384 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1234909831 Jun 23 07:58:37 PM PDT 24 Jun 23 09:31:45 PM PDT 24 24748686800 ps
T415 /workspace/coverage/default/27.chip_sw_all_escalation_resets.3100150675 Jun 23 08:21:18 PM PDT 24 Jun 23 08:34:48 PM PDT 24 5572123288 ps
T24 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2453059250 Jun 23 07:55:43 PM PDT 24 Jun 23 08:00:12 PM PDT 24 2905612827 ps
T247 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1300400211 Jun 23 07:58:18 PM PDT 24 Jun 23 08:55:07 PM PDT 24 44994565119 ps
T28 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1454133861 Jun 23 08:09:29 PM PDT 24 Jun 23 08:19:05 PM PDT 24 5174962334 ps
T313 /workspace/coverage/default/2.chip_plic_all_irqs_0.1348436019 Jun 23 08:13:03 PM PDT 24 Jun 23 08:32:25 PM PDT 24 6059751650 ps
T769 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3770902201 Jun 23 08:23:08 PM PDT 24 Jun 23 08:37:01 PM PDT 24 5319729160 ps
T983 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2588355704 Jun 23 07:57:22 PM PDT 24 Jun 23 09:16:23 PM PDT 24 15026505470 ps
T984 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1168227714 Jun 23 08:05:49 PM PDT 24 Jun 23 08:10:04 PM PDT 24 3225471988 ps
T316 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.869149777 Jun 23 08:00:55 PM PDT 24 Jun 23 08:29:10 PM PDT 24 13026484168 ps
T176 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1153700142 Jun 23 07:58:19 PM PDT 24 Jun 23 08:08:27 PM PDT 24 6878859963 ps
T177 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1508012402 Jun 23 08:00:32 PM PDT 24 Jun 23 08:09:00 PM PDT 24 3718816572 ps
T985 /workspace/coverage/default/2.rom_e2e_static_critical.1217354549 Jun 23 08:19:55 PM PDT 24 Jun 23 09:21:57 PM PDT 24 17319659910 ps
T986 /workspace/coverage/default/1.chip_sw_aes_entropy.3113650552 Jun 23 07:58:09 PM PDT 24 Jun 23 08:02:07 PM PDT 24 3428729182 ps
T987 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1253133335 Jun 23 07:53:43 PM PDT 24 Jun 23 07:58:54 PM PDT 24 3273131064 ps
T988 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.91167136 Jun 23 08:18:05 PM PDT 24 Jun 23 08:28:26 PM PDT 24 4158195870 ps
T9 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1765907013 Jun 23 07:52:16 PM PDT 24 Jun 23 08:25:59 PM PDT 24 22917396864 ps
T989 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.865759415 Jun 23 08:21:43 PM PDT 24 Jun 23 08:37:10 PM PDT 24 12763398704 ps
T114 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3222313245 Jun 23 08:03:54 PM PDT 24 Jun 23 08:14:07 PM PDT 24 4943487170 ps
T339 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1955660457 Jun 23 07:58:39 PM PDT 24 Jun 23 08:07:18 PM PDT 24 17963694304 ps
T829 /workspace/coverage/default/4.chip_sw_all_escalation_resets.3146168057 Jun 23 08:18:02 PM PDT 24 Jun 23 08:27:27 PM PDT 24 4370102180 ps
T990 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.112607697 Jun 23 07:49:58 PM PDT 24 Jun 23 07:55:06 PM PDT 24 2676406054 ps
T161 /workspace/coverage/default/61.chip_sw_all_escalation_resets.1909012696 Jun 23 08:22:50 PM PDT 24 Jun 23 08:30:18 PM PDT 24 4915989638 ps
T991 /workspace/coverage/default/2.chip_sw_edn_sw_mode.4037780078 Jun 23 08:10:37 PM PDT 24 Jun 23 08:36:47 PM PDT 24 9016653984 ps
T992 /workspace/coverage/default/4.chip_tap_straps_dev.1659472855 Jun 23 08:17:22 PM PDT 24 Jun 23 08:19:30 PM PDT 24 2307840530 ps
T263 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2456091035 Jun 23 07:50:08 PM PDT 24 Jun 23 07:58:42 PM PDT 24 3572142957 ps
T755 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2336238842 Jun 23 08:21:54 PM PDT 24 Jun 23 08:28:14 PM PDT 24 3763177420 ps
T993 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2765044720 Jun 23 07:56:07 PM PDT 24 Jun 23 08:21:34 PM PDT 24 6319208756 ps
T994 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1379523889 Jun 23 08:01:42 PM PDT 24 Jun 23 08:12:29 PM PDT 24 4188551264 ps
T995 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3679817385 Jun 23 08:05:14 PM PDT 24 Jun 23 08:08:42 PM PDT 24 2703088600 ps
T996 /workspace/coverage/default/0.chip_sw_example_concurrency.1491799065 Jun 23 07:49:55 PM PDT 24 Jun 23 07:54:19 PM PDT 24 2262598096 ps
T139 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.312441131 Jun 23 07:49:51 PM PDT 24 Jun 23 07:53:58 PM PDT 24 2590755273 ps
T997 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2044325006 Jun 23 08:08:39 PM PDT 24 Jun 23 08:31:00 PM PDT 24 8847962600 ps
T226 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3557418272 Jun 23 07:54:05 PM PDT 24 Jun 23 08:33:02 PM PDT 24 10545196504 ps
T998 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.298109574 Jun 23 07:49:34 PM PDT 24 Jun 23 08:20:40 PM PDT 24 9932316911 ps
T298 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.609877708 Jun 23 07:59:56 PM PDT 24 Jun 23 08:11:27 PM PDT 24 8323410076 ps
T999 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.808500312 Jun 23 07:57:43 PM PDT 24 Jun 23 08:59:16 PM PDT 24 12246810500 ps
T844 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3370384623 Jun 23 08:21:01 PM PDT 24 Jun 23 08:26:45 PM PDT 24 3653410858 ps
T1000 /workspace/coverage/default/0.chip_sw_usbdev_stream.3923677813 Jun 23 07:48:44 PM PDT 24 Jun 23 09:04:20 PM PDT 24 18755934760 ps
T1001 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.783807772 Jun 23 07:57:12 PM PDT 24 Jun 23 08:01:45 PM PDT 24 3047787826 ps
T1002 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2834352882 Jun 23 08:06:12 PM PDT 24 Jun 23 08:15:28 PM PDT 24 3681105640 ps
T1003 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2347882193 Jun 23 08:12:38 PM PDT 24 Jun 23 08:37:27 PM PDT 24 21505821824 ps
T818 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2402023033 Jun 23 08:21:52 PM PDT 24 Jun 23 08:28:07 PM PDT 24 4446302604 ps
T1004 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2297063076 Jun 23 08:09:24 PM PDT 24 Jun 23 08:27:07 PM PDT 24 5341149434 ps
T1005 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3730568755 Jun 23 07:50:34 PM PDT 24 Jun 23 07:59:44 PM PDT 24 6489038541 ps
T1006 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2689234310 Jun 23 08:02:27 PM PDT 24 Jun 23 08:13:03 PM PDT 24 4294957364 ps
T264 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1055446685 Jun 23 07:48:56 PM PDT 24 Jun 23 07:51:31 PM PDT 24 3596340525 ps
T1007 /workspace/coverage/default/1.chip_sw_hmac_smoketest.4057951210 Jun 23 08:05:58 PM PDT 24 Jun 23 08:11:17 PM PDT 24 2649520280 ps
T1008 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3254815670 Jun 23 08:28:06 PM PDT 24 Jun 23 08:31:51 PM PDT 24 2682870358 ps
T695 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.4051078800 Jun 23 07:50:06 PM PDT 24 Jun 23 07:51:51 PM PDT 24 2027870803 ps
T1009 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1654099453 Jun 23 07:54:53 PM PDT 24 Jun 23 08:02:25 PM PDT 24 2906319760 ps
T1010 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.4159215310 Jun 23 08:22:56 PM PDT 24 Jun 23 08:29:03 PM PDT 24 3150679030 ps
T1011 /workspace/coverage/default/0.chip_sw_aes_entropy.3588398239 Jun 23 07:52:57 PM PDT 24 Jun 23 07:58:13 PM PDT 24 2638786180 ps
T279 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2364594424 Jun 23 08:09:02 PM PDT 24 Jun 23 08:17:45 PM PDT 24 3623066160 ps
T1012 /workspace/coverage/default/4.chip_tap_straps_prod.2458681303 Jun 23 08:17:01 PM PDT 24 Jun 23 08:19:43 PM PDT 24 3263667460 ps
T360 /workspace/coverage/default/67.chip_sw_all_escalation_resets.1856885643 Jun 23 08:23:46 PM PDT 24 Jun 23 08:33:23 PM PDT 24 5469126240 ps
T301 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.937885045 Jun 23 08:23:13 PM PDT 24 Jun 23 08:29:27 PM PDT 24 3751130162 ps
T109 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3653559079 Jun 23 08:08:54 PM PDT 24 Jun 23 09:04:53 PM PDT 24 18891018382 ps
T12 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1385416794 Jun 23 08:08:23 PM PDT 24 Jun 23 08:14:45 PM PDT 24 3538633410 ps
T303 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3131582020 Jun 23 07:57:42 PM PDT 24 Jun 23 08:59:30 PM PDT 24 17353413002 ps
T304 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1895538472 Jun 23 07:51:17 PM PDT 24 Jun 23 08:15:37 PM PDT 24 6193859496 ps
T305 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1051355480 Jun 23 08:12:14 PM PDT 24 Jun 23 08:15:27 PM PDT 24 1864043061 ps
T306 /workspace/coverage/default/0.chip_sw_kmac_idle.3984083112 Jun 23 07:50:55 PM PDT 24 Jun 23 07:55:12 PM PDT 24 2728492392 ps
T307 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.401731567 Jun 23 08:01:14 PM PDT 24 Jun 23 08:07:24 PM PDT 24 2660918048 ps
T308 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.7799188 Jun 23 08:11:30 PM PDT 24 Jun 23 08:35:04 PM PDT 24 10379861726 ps
T309 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.375122105 Jun 23 08:21:23 PM PDT 24 Jun 23 08:29:27 PM PDT 24 3885021300 ps
T402 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1360504183 Jun 23 08:00:27 PM PDT 24 Jun 23 08:11:03 PM PDT 24 4574862760 ps
T155 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3447181746 Jun 23 07:58:37 PM PDT 24 Jun 23 11:12:55 PM PDT 24 254835628384 ps
T1013 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.306319944 Jun 23 08:20:17 PM PDT 24 Jun 23 09:12:24 PM PDT 24 15631964120 ps
T1014 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.762132923 Jun 23 07:53:43 PM PDT 24 Jun 23 08:10:24 PM PDT 24 8680493312 ps
T1015 /workspace/coverage/default/2.rom_keymgr_functest.1981183193 Jun 23 08:14:54 PM PDT 24 Jun 23 08:22:49 PM PDT 24 4157855400 ps
T37 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.947665012 Jun 23 07:50:21 PM PDT 24 Jun 23 08:47:20 PM PDT 24 20415660587 ps
T761 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.222023550 Jun 23 08:24:19 PM PDT 24 Jun 23 08:29:35 PM PDT 24 3370999096 ps
T1016 /workspace/coverage/default/3.chip_tap_straps_prod.3485843569 Jun 23 08:16:27 PM PDT 24 Jun 23 08:19:13 PM PDT 24 2785762025 ps
T340 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2864555442 Jun 23 08:08:12 PM PDT 24 Jun 23 08:19:47 PM PDT 24 4581184347 ps
T1017 /workspace/coverage/default/1.rom_e2e_asm_init_rma.1166545041 Jun 23 08:10:12 PM PDT 24 Jun 23 09:12:47 PM PDT 24 15730380670 ps
T280 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.491994942 Jun 23 08:27:49 PM PDT 24 Jun 23 08:36:27 PM PDT 24 5774841976 ps
T1018 /workspace/coverage/default/0.chip_sw_aes_smoketest.68103662 Jun 23 07:56:12 PM PDT 24 Jun 23 08:01:18 PM PDT 24 3735187856 ps
T766 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3567969089 Jun 23 08:18:44 PM PDT 24 Jun 23 08:24:39 PM PDT 24 3875923762 ps
T189 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.189116497 Jun 23 07:56:48 PM PDT 24 Jun 23 08:05:03 PM PDT 24 3631711685 ps
T1019 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1277338755 Jun 23 08:10:59 PM PDT 24 Jun 23 08:30:58 PM PDT 24 8541691724 ps
T1020 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.513449859 Jun 23 08:12:30 PM PDT 24 Jun 23 08:21:16 PM PDT 24 6248135782 ps
T1021 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.30103640 Jun 23 07:57:24 PM PDT 24 Jun 23 08:14:46 PM PDT 24 8033932800 ps
T321 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1699784331 Jun 23 07:55:49 PM PDT 24 Jun 23 08:09:46 PM PDT 24 5185799832 ps
T237 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2822067159 Jun 23 08:01:32 PM PDT 24 Jun 23 08:14:36 PM PDT 24 6305868544 ps
T1022 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1917991305 Jun 23 08:18:40 PM PDT 24 Jun 23 08:27:18 PM PDT 24 6086828115 ps
T1023 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3607757539 Jun 23 08:09:45 PM PDT 24 Jun 23 09:06:07 PM PDT 24 15732084168 ps
T1024 /workspace/coverage/default/2.chip_sw_otbn_smoketest.1460232240 Jun 23 08:16:27 PM PDT 24 Jun 23 08:33:44 PM PDT 24 6024333008 ps
T233 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3743511720 Jun 23 08:02:53 PM PDT 24 Jun 23 08:33:55 PM PDT 24 18255924643 ps
T223 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3649089419 Jun 23 08:12:55 PM PDT 24 Jun 23 08:49:20 PM PDT 24 12375971716 ps
T215 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3505550336 Jun 23 07:57:38 PM PDT 24 Jun 23 08:52:13 PM PDT 24 20335276313 ps
T808 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.598524828 Jun 23 08:25:18 PM PDT 24 Jun 23 08:31:00 PM PDT 24 4119940272 ps
T1025 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2221659280 Jun 23 08:09:02 PM PDT 24 Jun 23 08:19:22 PM PDT 24 4321869912 ps
T1026 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1030269431 Jun 23 08:02:01 PM PDT 24 Jun 23 08:11:02 PM PDT 24 5294637790 ps
T423 /workspace/coverage/default/1.chip_sw_kmac_entropy.2071512260 Jun 23 07:55:53 PM PDT 24 Jun 23 08:00:19 PM PDT 24 2687208140 ps
T816 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2360162071 Jun 23 08:20:45 PM PDT 24 Jun 23 08:30:24 PM PDT 24 6193275186 ps
T424 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2080854730 Jun 23 07:53:14 PM PDT 24 Jun 23 08:12:37 PM PDT 24 6248238624 ps
T1027 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4075584065 Jun 23 07:51:43 PM PDT 24 Jun 23 08:05:21 PM PDT 24 6220812000 ps
T503 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.694246588 Jun 23 08:09:45 PM PDT 24 Jun 23 08:22:39 PM PDT 24 5090137050 ps
T319 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2514421495 Jun 23 07:54:06 PM PDT 24 Jun 23 08:07:36 PM PDT 24 4733574584 ps
T1028 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3796315531 Jun 23 07:50:50 PM PDT 24 Jun 23 08:14:26 PM PDT 24 7705632880 ps
T1029 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.586408679 Jun 23 08:08:29 PM PDT 24 Jun 23 08:15:45 PM PDT 24 6714534002 ps
T1030 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1460844961 Jun 23 08:07:14 PM PDT 24 Jun 23 08:13:56 PM PDT 24 3195358126 ps
T202 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3669882981 Jun 23 07:51:59 PM PDT 24 Jun 23 08:25:00 PM PDT 24 24868335090 ps
T1031 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2513474277 Jun 23 07:48:31 PM PDT 24 Jun 23 10:51:26 PM PDT 24 64591546326 ps
T1032 /workspace/coverage/default/0.chip_sw_uart_tx_rx.886637274 Jun 23 07:48:05 PM PDT 24 Jun 23 07:57:07 PM PDT 24 3719590568 ps
T800 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.16803027 Jun 23 08:23:04 PM PDT 24 Jun 23 08:29:25 PM PDT 24 4195342540 ps
T825 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3099275490 Jun 23 08:22:04 PM PDT 24 Jun 23 08:33:26 PM PDT 24 4654214668 ps
T1033 /workspace/coverage/default/2.chip_sw_example_flash.392389746 Jun 23 08:05:18 PM PDT 24 Jun 23 08:09:52 PM PDT 24 3190209032 ps
T1034 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3711031154 Jun 23 08:05:17 PM PDT 24 Jun 23 08:08:43 PM PDT 24 2591648980 ps
T1035 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1306904617 Jun 23 08:08:41 PM PDT 24 Jun 23 08:13:57 PM PDT 24 3249190240 ps
T1036 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.185252055 Jun 23 08:17:40 PM PDT 24 Jun 23 08:24:26 PM PDT 24 4676344057 ps
T756 /workspace/coverage/default/70.chip_sw_all_escalation_resets.4291037514 Jun 23 08:24:41 PM PDT 24 Jun 23 08:34:41 PM PDT 24 6649187176 ps
T1037 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3556047978 Jun 23 08:20:53 PM PDT 24 Jun 23 09:06:49 PM PDT 24 13456725736 ps
T1038 /workspace/coverage/default/0.chip_sw_edn_auto_mode.2442696711 Jun 23 07:52:16 PM PDT 24 Jun 23 08:12:47 PM PDT 24 5071449216 ps
T347 /workspace/coverage/default/83.chip_sw_all_escalation_resets.2043570555 Jun 23 08:24:57 PM PDT 24 Jun 23 08:37:25 PM PDT 24 5098536016 ps
T805 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1967197796 Jun 23 08:24:17 PM PDT 24 Jun 23 08:34:15 PM PDT 24 4942883912 ps
T190 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2500170700 Jun 23 07:52:48 PM PDT 24 Jun 23 08:06:50 PM PDT 24 7800492892 ps
T1039 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.321342670 Jun 23 07:52:30 PM PDT 24 Jun 23 08:23:00 PM PDT 24 20861397606 ps
T784 /workspace/coverage/default/22.chip_sw_all_escalation_resets.909466842 Jun 23 08:20:30 PM PDT 24 Jun 23 08:32:25 PM PDT 24 5112834178 ps
T1040 /workspace/coverage/default/2.chip_sw_csrng_kat_test.2781890340 Jun 23 08:12:04 PM PDT 24 Jun 23 08:15:49 PM PDT 24 2149100282 ps
T1041 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.142083179 Jun 23 07:49:08 PM PDT 24 Jun 23 07:55:37 PM PDT 24 2703482200 ps
T1042 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2779307468 Jun 23 08:22:55 PM PDT 24 Jun 23 08:29:24 PM PDT 24 3424719760 ps
T767 /workspace/coverage/default/35.chip_sw_all_escalation_resets.719794742 Jun 23 08:21:02 PM PDT 24 Jun 23 08:30:05 PM PDT 24 5413940470 ps
T357 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2863734810 Jun 23 07:53:16 PM PDT 24 Jun 23 08:01:51 PM PDT 24 4623328728 ps
T1043 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1721876741 Jun 23 07:53:03 PM PDT 24 Jun 23 07:57:00 PM PDT 24 3559293517 ps
T330 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1687294715 Jun 23 08:14:11 PM PDT 24 Jun 23 08:25:48 PM PDT 24 5049774633 ps
T422 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.548251223 Jun 23 07:51:07 PM PDT 24 Jun 23 08:12:54 PM PDT 24 6349505902 ps
T1044 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1261395442 Jun 23 07:54:32 PM PDT 24 Jun 23 07:59:04 PM PDT 24 3050868392 ps
T358 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3894366222 Jun 23 08:17:25 PM PDT 24 Jun 23 08:25:43 PM PDT 24 4416841536 ps
T1045 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2055862398 Jun 23 08:01:57 PM PDT 24 Jun 23 08:31:36 PM PDT 24 6157405024 ps
T819 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3827758591 Jun 23 08:25:07 PM PDT 24 Jun 23 08:30:39 PM PDT 24 4013410528 ps
T1046 /workspace/coverage/default/1.rom_volatile_raw_unlock.869210453 Jun 23 08:05:23 PM PDT 24 Jun 23 08:07:22 PM PDT 24 2550939127 ps
T235 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.228275517 Jun 23 07:57:51 PM PDT 24 Jun 23 09:32:27 PM PDT 24 50165106956 ps
T230 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.110332956 Jun 23 08:09:07 PM PDT 24 Jun 23 09:53:26 PM PDT 24 48788066988 ps
T154 /workspace/coverage/default/1.chip_plic_all_irqs_10.2895396233 Jun 23 08:01:11 PM PDT 24 Jun 23 08:09:39 PM PDT 24 3891958476 ps
T1047 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.783626711 Jun 23 08:18:00 PM PDT 24 Jun 23 09:09:40 PM PDT 24 12148922642 ps
T791 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.841911589 Jun 23 08:18:59 PM PDT 24 Jun 23 08:27:33 PM PDT 24 3800789960 ps
T106 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2030925660 Jun 23 08:15:56 PM PDT 24 Jun 23 08:41:30 PM PDT 24 14600002499 ps
T1048 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.966648644 Jun 23 08:18:06 PM PDT 24 Jun 23 08:36:13 PM PDT 24 8583620672 ps
T361 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2515260215 Jun 23 08:25:36 PM PDT 24 Jun 23 08:34:11 PM PDT 24 4513917152 ps
T1049 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.374973567 Jun 23 08:03:45 PM PDT 24 Jun 23 09:00:26 PM PDT 24 25339515591 ps
T238 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3107724480 Jun 23 08:09:19 PM PDT 24 Jun 23 08:24:50 PM PDT 24 7476912080 ps
T317 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1148856491 Jun 23 07:50:22 PM PDT 24 Jun 23 08:19:26 PM PDT 24 10515768552 ps
T1050 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1599300063 Jun 23 07:56:59 PM PDT 24 Jun 23 07:58:50 PM PDT 24 2468466420 ps
T1051 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2146315705 Jun 23 08:24:50 PM PDT 24 Jun 23 08:34:32 PM PDT 24 6266475472 ps
T1052 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2351556336 Jun 23 08:01:16 PM PDT 24 Jun 23 09:13:03 PM PDT 24 15828912824 ps
T299 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3963971877 Jun 23 08:12:15 PM PDT 24 Jun 23 08:26:13 PM PDT 24 8468626253 ps
T268 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.4048434226 Jun 23 08:18:51 PM PDT 24 Jun 23 08:28:01 PM PDT 24 5846083460 ps
T1053 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1933468786 Jun 23 07:50:19 PM PDT 24 Jun 23 07:54:06 PM PDT 24 2460541704 ps
T395 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1379543287 Jun 23 07:55:16 PM PDT 24 Jun 23 08:04:07 PM PDT 24 6193382884 ps
T1054 /workspace/coverage/default/0.rom_volatile_raw_unlock.2842900714 Jun 23 07:52:45 PM PDT 24 Jun 23 07:54:27 PM PDT 24 2566912102 ps
T746 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4036962598 Jun 23 07:49:01 PM PDT 24 Jun 23 08:00:09 PM PDT 24 4932494080 ps
T770 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1869941676 Jun 23 08:23:21 PM PDT 24 Jun 23 08:32:31 PM PDT 24 4656070840 ps
T1055 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3314193660 Jun 23 07:49:56 PM PDT 24 Jun 23 08:00:01 PM PDT 24 5914161880 ps
T382 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2732593787 Jun 23 07:49:09 PM PDT 24 Jun 23 08:06:42 PM PDT 24 5747309574 ps
T806 /workspace/coverage/default/49.chip_sw_all_escalation_resets.2113120223 Jun 23 08:23:28 PM PDT 24 Jun 23 08:34:56 PM PDT 24 5375186494 ps
T1056 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.558576637 Jun 23 07:52:54 PM PDT 24 Jun 23 08:03:33 PM PDT 24 4571498892 ps
T1057 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2718953907 Jun 23 07:56:36 PM PDT 24 Jun 23 08:08:46 PM PDT 24 4522499502 ps
T1058 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2474760277 Jun 23 08:19:04 PM PDT 24 Jun 23 08:47:23 PM PDT 24 7501857432 ps
T1059 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1107440293 Jun 23 08:19:04 PM PDT 24 Jun 23 08:27:29 PM PDT 24 3110459160 ps
T140 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1421443609 Jun 23 08:03:47 PM PDT 24 Jun 23 08:08:35 PM PDT 24 3327190097 ps
T1060 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3487197702 Jun 23 08:16:13 PM PDT 24 Jun 23 09:26:57 PM PDT 24 16312102156 ps
T832 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4056800036 Jun 23 08:19:58 PM PDT 24 Jun 23 08:26:54 PM PDT 24 3545758140 ps
T1061 /workspace/coverage/default/2.rom_e2e_asm_init_dev.3484718716 Jun 23 08:28:22 PM PDT 24 Jun 23 09:21:21 PM PDT 24 15828817113 ps
T693 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3437964759 Jun 23 08:02:27 PM PDT 24 Jun 23 08:10:04 PM PDT 24 5978582658 ps
T53 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1118319691 Jun 23 08:07:53 PM PDT 24 Jun 23 08:16:18 PM PDT 24 3423147601 ps
T798 /workspace/coverage/default/62.chip_sw_all_escalation_resets.962274016 Jun 23 08:28:01 PM PDT 24 Jun 23 08:38:06 PM PDT 24 5698948374 ps
T1062 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2853457762 Jun 23 07:58:58 PM PDT 24 Jun 23 08:25:26 PM PDT 24 7884803896 ps
T1063 /workspace/coverage/default/2.chip_sw_kmac_entropy.3924086234 Jun 23 08:07:55 PM PDT 24 Jun 23 08:13:13 PM PDT 24 2624341624 ps
T1064 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1286054753 Jun 23 07:58:45 PM PDT 24 Jun 23 08:44:48 PM PDT 24 23689846564 ps
T1065 /workspace/coverage/default/1.rom_e2e_smoke.3800835666 Jun 23 08:15:57 PM PDT 24 Jun 23 09:23:37 PM PDT 24 15268310076 ps
T1066 /workspace/coverage/default/1.chip_tap_straps_prod.1990057135 Jun 23 08:02:29 PM PDT 24 Jun 23 08:05:10 PM PDT 24 2186811763 ps
T66 /workspace/coverage/default/0.chip_tap_straps_rma.1932155803 Jun 23 07:50:24 PM PDT 24 Jun 23 08:05:34 PM PDT 24 8269191212 ps
T1067 /workspace/coverage/default/0.rom_keymgr_functest.2229161384 Jun 23 07:53:42 PM PDT 24 Jun 23 08:04:45 PM PDT 24 5758627240 ps
T1068 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1632164628 Jun 23 08:00:47 PM PDT 24 Jun 23 09:10:57 PM PDT 24 15225563448 ps
T753 /workspace/coverage/default/53.chip_sw_all_escalation_resets.4264518190 Jun 23 08:22:05 PM PDT 24 Jun 23 08:30:45 PM PDT 24 5198366550 ps
T1069 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2351453786 Jun 23 07:59:13 PM PDT 24 Jun 23 08:03:42 PM PDT 24 2756368544 ps
T1070 /workspace/coverage/default/0.chip_tap_straps_dev.3608279044 Jun 23 07:49:55 PM PDT 24 Jun 23 07:52:21 PM PDT 24 2865631657 ps
T1071 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3588413362 Jun 23 07:59:53 PM PDT 24 Jun 23 08:41:47 PM PDT 24 10933546470 ps
T1072 /workspace/coverage/default/2.chip_sw_aes_entropy.3042016119 Jun 23 08:09:32 PM PDT 24 Jun 23 08:13:28 PM PDT 24 2796894140 ps
T1073 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1072528442 Jun 23 08:27:07 PM PDT 24 Jun 23 08:34:26 PM PDT 24 3784061446 ps
T1074 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4247637899 Jun 23 08:08:52 PM PDT 24 Jun 23 08:32:20 PM PDT 24 11010259469 ps
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