Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.23 95.53 94.17 95.47 95.13 97.53 99.57


Total test records in report: 2882
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html
T271 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2382657562 Jun 23 08:07:34 PM PDT 24 Jun 23 08:21:44 PM PDT 24 4771786618 ps
T1216 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1928539292 Jun 23 08:18:56 PM PDT 24 Jun 23 08:32:58 PM PDT 24 6052894989 ps
T1217 /workspace/coverage/default/0.chip_sw_aes_enc.3963853614 Jun 23 07:49:17 PM PDT 24 Jun 23 07:55:08 PM PDT 24 3301336754 ps
T1218 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2167074740 Jun 23 07:59:39 PM PDT 24 Jun 23 08:30:15 PM PDT 24 8662101350 ps
T335 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3106357790 Jun 23 08:07:50 PM PDT 24 Jun 23 08:24:09 PM PDT 24 5613912050 ps
T1219 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2132975824 Jun 23 07:51:03 PM PDT 24 Jun 23 07:55:39 PM PDT 24 2819079908 ps
T1220 /workspace/coverage/default/1.chip_sw_hmac_multistream.3885661963 Jun 23 08:01:20 PM PDT 24 Jun 23 08:27:40 PM PDT 24 6862470500 ps
T504 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1797541771 Jun 23 07:52:14 PM PDT 24 Jun 23 08:01:38 PM PDT 24 4028748024 ps
T256 /workspace/coverage/default/88.chip_sw_all_escalation_resets.956638913 Jun 23 08:26:19 PM PDT 24 Jun 23 08:32:22 PM PDT 24 4762537280 ps
T1221 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1502224679 Jun 23 07:50:42 PM PDT 24 Jun 23 08:02:18 PM PDT 24 4524907832 ps
T809 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028738323 Jun 23 08:18:23 PM PDT 24 Jun 23 08:27:15 PM PDT 24 3859775810 ps
T1222 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1560974890 Jun 23 08:03:11 PM PDT 24 Jun 23 08:10:05 PM PDT 24 4997334500 ps
T1223 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1167977819 Jun 23 08:20:54 PM PDT 24 Jun 23 08:45:39 PM PDT 24 8281827908 ps
T41 /workspace/coverage/default/2.chip_sw_gpio.257734246 Jun 23 08:09:14 PM PDT 24 Jun 23 08:17:35 PM PDT 24 3311980370 ps
T1224 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3140326878 Jun 23 07:59:07 PM PDT 24 Jun 23 08:22:05 PM PDT 24 12118259736 ps
T1225 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2077365730 Jun 23 08:22:58 PM PDT 24 Jun 23 08:30:10 PM PDT 24 3234449108 ps
T1226 /workspace/coverage/default/0.chip_sw_rv_timer_irq.558902060 Jun 23 07:52:57 PM PDT 24 Jun 23 07:58:17 PM PDT 24 2723711096 ps
T370 /workspace/coverage/default/65.chip_sw_all_escalation_resets.2855747933 Jun 23 08:22:57 PM PDT 24 Jun 23 08:33:20 PM PDT 24 4694758888 ps
T1227 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2644289645 Jun 23 08:24:30 PM PDT 24 Jun 23 08:32:05 PM PDT 24 5043212760 ps
T1228 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1644867747 Jun 23 08:19:47 PM PDT 24 Jun 23 08:29:01 PM PDT 24 3802086452 ps
T1229 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1588805747 Jun 23 07:53:36 PM PDT 24 Jun 23 08:02:19 PM PDT 24 6804290678 ps
T1230 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1077212491 Jun 23 08:07:26 PM PDT 24 Jun 23 08:27:27 PM PDT 24 6254168745 ps
T1231 /workspace/coverage/default/1.rom_e2e_asm_init_dev.3538699351 Jun 23 08:10:36 PM PDT 24 Jun 23 09:10:19 PM PDT 24 16115561706 ps
T811 /workspace/coverage/default/18.chip_sw_all_escalation_resets.2270199618 Jun 23 08:20:23 PM PDT 24 Jun 23 08:32:24 PM PDT 24 5701131870 ps
T836 /workspace/coverage/default/39.chip_sw_all_escalation_resets.3813788762 Jun 23 08:20:44 PM PDT 24 Jun 23 08:30:17 PM PDT 24 4442019740 ps
T689 /workspace/coverage/default/1.chip_sw_edn_boot_mode.745374970 Jun 23 07:58:14 PM PDT 24 Jun 23 08:10:08 PM PDT 24 3270529456 ps
T1232 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2655521822 Jun 23 07:51:42 PM PDT 24 Jun 23 08:02:06 PM PDT 24 5349262360 ps
T1233 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2987731281 Jun 23 07:52:28 PM PDT 24 Jun 23 07:58:58 PM PDT 24 3948578792 ps
T1234 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4236576562 Jun 23 08:09:53 PM PDT 24 Jun 23 08:16:29 PM PDT 24 3894279528 ps
T1235 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4108743590 Jun 23 08:26:55 PM PDT 24 Jun 23 08:34:59 PM PDT 24 3455999338 ps
T1236 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3862777899 Jun 23 08:18:38 PM PDT 24 Jun 23 08:26:53 PM PDT 24 5828866022 ps
T1237 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1447254384 Jun 23 08:17:12 PM PDT 24 Jun 23 08:25:09 PM PDT 24 5827617640 ps
T1238 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1853876437 Jun 23 08:08:21 PM PDT 24 Jun 23 08:15:09 PM PDT 24 3905172952 ps
T1239 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3807448884 Jun 23 07:54:54 PM PDT 24 Jun 23 07:59:18 PM PDT 24 3244709176 ps
T1240 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2371065405 Jun 23 07:55:48 PM PDT 24 Jun 23 08:09:49 PM PDT 24 5221969800 ps
T15 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1332030092 Jun 23 08:06:17 PM PDT 24 Jun 23 08:09:56 PM PDT 24 2885972164 ps
T1241 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.212072301 Jun 23 08:14:35 PM PDT 24 Jun 23 08:45:58 PM PDT 24 10342940483 ps
T1242 /workspace/coverage/default/3.chip_tap_straps_dev.2065809439 Jun 23 08:17:33 PM PDT 24 Jun 23 08:20:10 PM PDT 24 3120998552 ps
T252 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3264091323 Jun 23 07:58:33 PM PDT 24 Jun 23 08:03:33 PM PDT 24 3280396578 ps
T1243 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3160036666 Jun 23 07:59:39 PM PDT 24 Jun 23 08:30:49 PM PDT 24 8937908412 ps
T1244 /workspace/coverage/default/1.chip_sw_example_rom.363003678 Jun 23 07:57:08 PM PDT 24 Jun 23 07:59:23 PM PDT 24 1932464040 ps
T61 /workspace/coverage/default/2.chip_sw_alert_test.2140942070 Jun 23 08:09:50 PM PDT 24 Jun 23 08:15:06 PM PDT 24 2921861470 ps
T801 /workspace/coverage/default/0.chip_sw_all_escalation_resets.2220271400 Jun 23 07:49:40 PM PDT 24 Jun 23 08:02:00 PM PDT 24 5690693644 ps
T1245 /workspace/coverage/default/89.chip_sw_all_escalation_resets.4274678252 Jun 23 08:26:30 PM PDT 24 Jun 23 08:35:59 PM PDT 24 5618640774 ps
T1246 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2423347586 Jun 23 07:58:33 PM PDT 24 Jun 23 08:09:46 PM PDT 24 6729110200 ps
T1247 /workspace/coverage/default/2.chip_sw_example_rom.3512746131 Jun 23 08:05:54 PM PDT 24 Jun 23 08:08:34 PM PDT 24 2507186210 ps
T1248 /workspace/coverage/default/2.chip_tap_straps_testunlock0.3920971997 Jun 23 08:13:25 PM PDT 24 Jun 23 08:24:24 PM PDT 24 7708867416 ps
T1249 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.283953145 Jun 23 08:14:50 PM PDT 24 Jun 23 09:20:40 PM PDT 24 25008371648 ps
T131 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.676085397 Jun 23 08:19:51 PM PDT 24 Jun 23 08:32:52 PM PDT 24 5570303398 ps
T1250 /workspace/coverage/default/0.chip_sw_usbdev_vbus.2271947665 Jun 23 07:49:53 PM PDT 24 Jun 23 07:54:38 PM PDT 24 3654672232 ps
T1251 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3528911423 Jun 23 08:20:35 PM PDT 24 Jun 23 08:56:13 PM PDT 24 13115529650 ps
T1252 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.837980896 Jun 23 07:49:54 PM PDT 24 Jun 23 07:57:52 PM PDT 24 10041035109 ps
T758 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.364486512 Jun 23 08:24:19 PM PDT 24 Jun 23 08:31:41 PM PDT 24 4113851500 ps
T1253 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3891631694 Jun 23 08:18:54 PM PDT 24 Jun 23 08:31:23 PM PDT 24 10466062180 ps
T1254 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3701040479 Jun 23 08:04:07 PM PDT 24 Jun 23 08:12:49 PM PDT 24 5858087382 ps
T1255 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3300007096 Jun 23 08:08:38 PM PDT 24 Jun 23 09:41:04 PM PDT 24 50826212108 ps
T1256 /workspace/coverage/default/2.rom_e2e_asm_init_prod.2150519360 Jun 23 08:21:44 PM PDT 24 Jun 23 09:26:15 PM PDT 24 15952976855 ps
T1257 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1814948180 Jun 23 08:21:25 PM PDT 24 Jun 23 09:17:10 PM PDT 24 10976615216 ps
T257 /workspace/coverage/default/40.chip_sw_all_escalation_resets.2431955149 Jun 23 08:21:29 PM PDT 24 Jun 23 08:34:04 PM PDT 24 5625877882 ps
T1258 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2537954970 Jun 23 08:08:49 PM PDT 24 Jun 23 08:14:01 PM PDT 24 2788170278 ps
T797 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.163189696 Jun 23 08:22:15 PM PDT 24 Jun 23 08:29:34 PM PDT 24 4159059800 ps
T1259 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.969437041 Jun 23 07:50:19 PM PDT 24 Jun 23 08:20:21 PM PDT 24 9816512084 ps
T1260 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2936473846 Jun 23 08:07:21 PM PDT 24 Jun 23 08:09:18 PM PDT 24 2555431395 ps
T1261 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462464434 Jun 23 08:21:00 PM PDT 24 Jun 23 08:28:14 PM PDT 24 3206063032 ps
T729 /workspace/coverage/default/2.chip_sw_pattgen_ios.3201966054 Jun 23 08:07:58 PM PDT 24 Jun 23 08:11:54 PM PDT 24 2951596560 ps
T1262 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.595283259 Jun 23 07:48:35 PM PDT 24 Jun 23 08:00:53 PM PDT 24 4278559320 ps
T1263 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3256260851 Jun 23 08:23:13 PM PDT 24 Jun 23 08:29:02 PM PDT 24 3162648320 ps
T243 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2378955222 Jun 23 08:11:24 PM PDT 24 Jun 23 08:16:54 PM PDT 24 3459033800 ps
T328 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3339363715 Jun 23 08:02:12 PM PDT 24 Jun 23 08:09:38 PM PDT 24 3778445234 ps
T771 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1797429567 Jun 23 08:26:34 PM PDT 24 Jun 23 08:33:26 PM PDT 24 3428744728 ps
T763 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3385906020 Jun 23 08:22:51 PM PDT 24 Jun 23 08:29:22 PM PDT 24 4005028872 ps
T1264 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.772498358 Jun 23 07:59:43 PM PDT 24 Jun 23 08:03:38 PM PDT 24 2366562144 ps
T740 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2118169032 Jun 23 08:23:38 PM PDT 24 Jun 23 08:30:58 PM PDT 24 4211289560 ps
T1265 /workspace/coverage/default/0.chip_sw_hmac_multistream.2104429311 Jun 23 07:50:06 PM PDT 24 Jun 23 08:19:10 PM PDT 24 6996800484 ps
T1266 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3105774394 Jun 23 07:56:54 PM PDT 24 Jun 23 08:08:47 PM PDT 24 4499527124 ps
T295 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3222246103 Jun 23 07:54:11 PM PDT 24 Jun 23 07:58:57 PM PDT 24 3008748216 ps
T833 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.283126643 Jun 23 08:19:21 PM PDT 24 Jun 23 08:24:41 PM PDT 24 3774705206 ps
T1267 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2404405088 Jun 23 08:04:46 PM PDT 24 Jun 23 08:09:27 PM PDT 24 3236650280 ps
T774 /workspace/coverage/default/46.chip_sw_all_escalation_resets.3929904019 Jun 23 08:23:20 PM PDT 24 Jun 23 08:31:49 PM PDT 24 6045396848 ps
T1268 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1594812969 Jun 23 08:08:00 PM PDT 24 Jun 23 09:32:36 PM PDT 24 47432139073 ps
T1269 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1980230045 Jun 23 08:17:01 PM PDT 24 Jun 23 08:26:46 PM PDT 24 6456696930 ps
T1270 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.121453967 Jun 23 07:56:33 PM PDT 24 Jun 23 08:20:02 PM PDT 24 9482524696 ps
T1271 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2746196340 Jun 23 08:12:25 PM PDT 24 Jun 23 08:27:32 PM PDT 24 5762231756 ps
T1272 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3490955955 Jun 23 07:50:47 PM PDT 24 Jun 23 08:03:20 PM PDT 24 3846878772 ps
T1273 /workspace/coverage/default/0.chip_sw_csrng_smoketest.1463523862 Jun 23 07:52:31 PM PDT 24 Jun 23 07:56:29 PM PDT 24 2883975600 ps
T1274 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1244942178 Jun 23 08:10:07 PM PDT 24 Jun 23 08:15:41 PM PDT 24 2374648660 ps
T1275 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.989088190 Jun 23 08:24:29 PM PDT 24 Jun 23 08:32:07 PM PDT 24 3682577352 ps
T25 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2403994906 Jun 23 07:48:58 PM PDT 24 Jun 23 07:53:56 PM PDT 24 2757676618 ps
T1276 /workspace/coverage/default/2.chip_tap_straps_prod.1233908845 Jun 23 08:13:13 PM PDT 24 Jun 23 08:25:20 PM PDT 24 7224186351 ps
T778 /workspace/coverage/default/32.chip_sw_all_escalation_resets.843298918 Jun 23 08:20:44 PM PDT 24 Jun 23 08:28:35 PM PDT 24 6427191028 ps
T1277 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.632831929 Jun 23 08:21:55 PM PDT 24 Jun 23 09:35:20 PM PDT 24 15968920636 ps
T815 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538347165 Jun 23 08:20:39 PM PDT 24 Jun 23 08:27:27 PM PDT 24 3852518990 ps
T1278 /workspace/coverage/default/0.chip_sw_kmac_entropy.2587749886 Jun 23 07:50:04 PM PDT 24 Jun 23 07:54:42 PM PDT 24 3178858980 ps
T835 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1319230482 Jun 23 08:29:53 PM PDT 24 Jun 23 08:36:11 PM PDT 24 3473366812 ps
T136 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3974010274 Jun 23 07:50:49 PM PDT 24 Jun 23 08:37:15 PM PDT 24 18777149045 ps
T132 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2836231831 Jun 23 07:50:53 PM PDT 24 Jun 23 08:06:50 PM PDT 24 7313708186 ps
T1279 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.913852376 Jun 23 08:00:33 PM PDT 24 Jun 23 08:12:28 PM PDT 24 8894499712 ps
T799 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2004707538 Jun 23 08:25:11 PM PDT 24 Jun 23 08:30:48 PM PDT 24 3847892712 ps
T1280 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1947056762 Jun 23 08:23:29 PM PDT 24 Jun 23 08:30:35 PM PDT 24 4162385100 ps
T1281 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3659392892 Jun 23 07:52:16 PM PDT 24 Jun 23 07:59:38 PM PDT 24 5943136167 ps
T84 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1982594264 Jun 23 08:25:21 PM PDT 24 Jun 23 08:31:57 PM PDT 24 3682724152 ps
T86 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890658937 Jun 23 08:22:03 PM PDT 24 Jun 23 08:29:15 PM PDT 24 3618379460 ps
T87 /workspace/coverage/default/1.chip_sw_example_concurrency.2263230679 Jun 23 07:58:01 PM PDT 24 Jun 23 08:03:04 PM PDT 24 2398084272 ps
T88 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4033584230 Jun 23 07:58:02 PM PDT 24 Jun 23 08:09:21 PM PDT 24 5699430572 ps
T89 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.331952383 Jun 23 08:10:57 PM PDT 24 Jun 23 08:33:58 PM PDT 24 11365457512 ps
T90 /workspace/coverage/default/1.chip_sival_flash_info_access.3149954804 Jun 23 07:54:28 PM PDT 24 Jun 23 07:59:33 PM PDT 24 3791040536 ps
T91 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.633337308 Jun 23 08:17:13 PM PDT 24 Jun 23 08:25:18 PM PDT 24 3633238998 ps
T92 /workspace/coverage/default/2.rom_e2e_asm_init_rma.2918190395 Jun 23 08:19:06 PM PDT 24 Jun 23 09:18:43 PM PDT 24 15356787802 ps
T93 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.412411396 Jun 23 07:53:05 PM PDT 24 Jun 23 08:05:07 PM PDT 24 4858353030 ps
T94 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2252395505 Jun 23 08:23:35 PM PDT 24 Jun 23 08:35:17 PM PDT 24 6143706200 ps
T812 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3341359085 Jun 23 08:21:10 PM PDT 24 Jun 23 08:32:37 PM PDT 24 5144382980 ps
T1282 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.791435664 Jun 23 08:03:59 PM PDT 24 Jun 23 08:06:59 PM PDT 24 2821750316 ps
T846 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3529836022 Jun 23 08:25:01 PM PDT 24 Jun 23 08:31:31 PM PDT 24 3311979464 ps
T788 /workspace/coverage/default/10.chip_sw_all_escalation_resets.2354238969 Jun 23 08:20:35 PM PDT 24 Jun 23 08:32:35 PM PDT 24 5389787150 ps
T1283 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.291960218 Jun 23 07:51:33 PM PDT 24 Jun 23 09:31:20 PM PDT 24 26846494896 ps
T1284 /workspace/coverage/default/0.chip_sw_gpio_smoketest.961048903 Jun 23 07:54:36 PM PDT 24 Jun 23 07:58:21 PM PDT 24 2668691510 ps
T17 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1285471188 Jun 23 07:48:33 PM PDT 24 Jun 23 07:52:32 PM PDT 24 3342690392 ps
T1285 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2187429610 Jun 23 07:58:54 PM PDT 24 Jun 23 08:03:02 PM PDT 24 2898389706 ps
T1286 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3732277910 Jun 23 08:03:02 PM PDT 24 Jun 23 08:13:27 PM PDT 24 4348501272 ps
T1287 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.903335604 Jun 23 07:57:32 PM PDT 24 Jun 23 09:33:04 PM PDT 24 24718608404 ps
T752 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3262914389 Jun 23 08:19:21 PM PDT 24 Jun 23 08:25:42 PM PDT 24 3711868370 ps
T1288 /workspace/coverage/default/2.chip_sw_kmac_app_rom.2845747875 Jun 23 08:11:49 PM PDT 24 Jun 23 08:16:40 PM PDT 24 2937361978 ps
T1289 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2677412561 Jun 23 08:07:27 PM PDT 24 Jun 23 08:18:49 PM PDT 24 3756604056 ps
T85 /workspace/coverage/default/12.chip_sw_all_escalation_resets.2017361009 Jun 23 08:21:14 PM PDT 24 Jun 23 08:33:17 PM PDT 24 5214509032 ps
T790 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3123822389 Jun 23 08:26:10 PM PDT 24 Jun 23 08:35:34 PM PDT 24 5081093848 ps
T714 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1467654044 Jun 23 07:57:33 PM PDT 24 Jun 23 08:03:02 PM PDT 24 2616894886 ps
T1290 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.755737267 Jun 23 08:23:22 PM PDT 24 Jun 23 08:28:45 PM PDT 24 3877663440 ps
T1291 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.563637324 Jun 23 08:18:24 PM PDT 24 Jun 23 08:26:15 PM PDT 24 5279145506 ps
T1292 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1686640077 Jun 23 08:04:25 PM PDT 24 Jun 23 08:10:07 PM PDT 24 2740720736 ps
T1293 /workspace/coverage/default/2.chip_tap_straps_rma.1407286602 Jun 23 08:12:11 PM PDT 24 Jun 23 08:22:29 PM PDT 24 5807204454 ps
T822 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3704355534 Jun 23 08:16:27 PM PDT 24 Jun 23 08:28:38 PM PDT 24 5235136244 ps
T1294 /workspace/coverage/default/54.chip_sw_all_escalation_resets.3822909254 Jun 23 08:22:53 PM PDT 24 Jun 23 08:32:21 PM PDT 24 5440338892 ps
T1295 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1606442839 Jun 23 08:17:50 PM PDT 24 Jun 23 08:32:01 PM PDT 24 4815545416 ps
T1296 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3265680409 Jun 23 07:49:29 PM PDT 24 Jun 23 08:00:21 PM PDT 24 5874334512 ps
T1297 /workspace/coverage/default/0.rom_e2e_asm_init_prod.2183822783 Jun 23 07:59:46 PM PDT 24 Jun 23 09:04:28 PM PDT 24 16440744276 ps
T225 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3136353832 Jun 23 07:50:15 PM PDT 24 Jun 23 08:10:35 PM PDT 24 6787678984 ps
T793 /workspace/coverage/default/45.chip_sw_all_escalation_resets.1441132396 Jun 23 08:23:09 PM PDT 24 Jun 23 08:36:33 PM PDT 24 4594508796 ps
T772 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2716969236 Jun 23 08:22:53 PM PDT 24 Jun 23 08:31:06 PM PDT 24 4418046450 ps
T157 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2491310126 Jun 23 07:51:57 PM PDT 24 Jun 23 07:56:11 PM PDT 24 3100276298 ps
T1298 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2925730573 Jun 23 08:09:48 PM PDT 24 Jun 23 08:16:11 PM PDT 24 4345181169 ps
T1299 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.575008970 Jun 23 08:00:30 PM PDT 24 Jun 23 08:40:31 PM PDT 24 32814308684 ps
T1300 /workspace/coverage/default/0.chip_sw_power_sleep_load.2865230364 Jun 23 07:51:16 PM PDT 24 Jun 23 08:00:25 PM PDT 24 9512724358 ps
T1301 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1738790061 Jun 23 08:12:10 PM PDT 24 Jun 23 08:16:08 PM PDT 24 2223113271 ps
T1302 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.722849876 Jun 23 08:18:43 PM PDT 24 Jun 23 08:26:18 PM PDT 24 6178014919 ps
T193 /workspace/coverage/default/2.chip_jtag_mem_access.2854716068 Jun 23 08:05:51 PM PDT 24 Jun 23 08:27:14 PM PDT 24 13455548240 ps
T1303 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1066713962 Jun 23 08:02:45 PM PDT 24 Jun 23 08:07:20 PM PDT 24 2983722307 ps
T1304 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1109264878 Jun 23 08:01:33 PM PDT 24 Jun 23 08:19:29 PM PDT 24 7284203788 ps
T1305 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2630277002 Jun 23 07:56:52 PM PDT 24 Jun 23 09:05:05 PM PDT 24 16171181776 ps
T1306 /workspace/coverage/default/0.chip_sw_example_manufacturer.2107005480 Jun 23 07:48:06 PM PDT 24 Jun 23 07:51:19 PM PDT 24 2727991728 ps
T1307 /workspace/coverage/default/1.chip_sw_flash_crash_alert.1376215943 Jun 23 08:03:45 PM PDT 24 Jun 23 08:16:34 PM PDT 24 4995841208 ps
T1308 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.742859268 Jun 23 07:49:33 PM PDT 24 Jun 23 07:52:44 PM PDT 24 2623211057 ps
T1309 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3879024241 Jun 23 08:05:52 PM PDT 24 Jun 23 08:17:26 PM PDT 24 4521214860 ps
T8 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4265873937 Jun 23 08:13:27 PM PDT 24 Jun 23 08:20:44 PM PDT 24 3587631504 ps
T1310 /workspace/coverage/default/1.chip_tap_straps_dev.319602096 Jun 23 08:02:28 PM PDT 24 Jun 23 08:08:17 PM PDT 24 3660002726 ps
T1311 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3542478900 Jun 23 08:00:42 PM PDT 24 Jun 23 08:03:56 PM PDT 24 2691343400 ps
T194 /workspace/coverage/default/0.chip_jtag_mem_access.2143663275 Jun 23 07:43:13 PM PDT 24 Jun 23 08:07:48 PM PDT 24 13253440278 ps
T705 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2893475402 Jun 23 08:22:52 PM PDT 24 Jun 23 08:32:32 PM PDT 24 4890833620 ps
T1312 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1097617137 Jun 23 07:56:10 PM PDT 24 Jun 23 08:09:15 PM PDT 24 4153108914 ps
T351 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3117409283 Jun 23 07:49:35 PM PDT 24 Jun 23 07:56:34 PM PDT 24 3033840836 ps
T1313 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.299695544 Jun 23 07:59:37 PM PDT 24 Jun 23 08:59:21 PM PDT 24 36064797713 ps
T1314 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3351210996 Jun 23 08:16:07 PM PDT 24 Jun 23 09:21:38 PM PDT 24 15321651542 ps
T1315 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1674761542 Jun 23 08:17:25 PM PDT 24 Jun 23 08:22:49 PM PDT 24 2780470780 ps
T1316 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2123060103 Jun 23 07:57:46 PM PDT 24 Jun 23 08:06:07 PM PDT 24 6118350504 ps
T353 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1941467730 Jun 23 08:07:23 PM PDT 24 Jun 23 08:18:02 PM PDT 24 3687507448 ps
T1317 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1475460033 Jun 23 08:07:31 PM PDT 24 Jun 23 08:27:56 PM PDT 24 5651561790 ps
T411 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3029311359 Jun 23 08:12:57 PM PDT 24 Jun 23 08:40:42 PM PDT 24 26687129050 ps
T1318 /workspace/coverage/default/2.chip_sw_uart_smoketest.231844481 Jun 23 08:15:59 PM PDT 24 Jun 23 08:19:46 PM PDT 24 2856523910 ps
T1319 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2799582994 Jun 23 07:48:47 PM PDT 24 Jun 23 08:06:49 PM PDT 24 13068128112 ps
T1320 /workspace/coverage/default/2.rom_volatile_raw_unlock.1220820237 Jun 23 08:15:30 PM PDT 24 Jun 23 08:17:12 PM PDT 24 2269089559 ps
T1321 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2261417920 Jun 23 08:10:20 PM PDT 24 Jun 23 08:34:00 PM PDT 24 6627101340 ps
T1322 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1329884285 Jun 23 07:50:27 PM PDT 24 Jun 23 08:00:44 PM PDT 24 5495786456 ps
T765 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2512384598 Jun 23 08:23:51 PM PDT 24 Jun 23 08:33:22 PM PDT 24 5670803464 ps
T1323 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3055447329 Jun 23 08:19:09 PM PDT 24 Jun 23 08:41:41 PM PDT 24 8260154946 ps
T1324 /workspace/coverage/default/2.chip_sw_rv_timer_irq.2781461198 Jun 23 08:14:26 PM PDT 24 Jun 23 08:17:43 PM PDT 24 2756011660 ps
T810 /workspace/coverage/default/87.chip_sw_all_escalation_resets.508494012 Jun 23 08:26:26 PM PDT 24 Jun 23 08:35:29 PM PDT 24 4991385292 ps
T1325 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1441725862 Jun 23 08:10:05 PM PDT 24 Jun 23 08:20:35 PM PDT 24 18174074298 ps
T355 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1260934644 Jun 23 08:13:09 PM PDT 24 Jun 23 08:18:54 PM PDT 24 3174261664 ps
T16 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3202334990 Jun 23 07:54:36 PM PDT 24 Jun 23 08:02:03 PM PDT 24 6518194696 ps
T1326 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1071429804 Jun 23 08:17:23 PM PDT 24 Jun 23 08:39:42 PM PDT 24 8681672360 ps
T1327 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2291115550 Jun 23 07:50:23 PM PDT 24 Jun 23 08:09:38 PM PDT 24 12812675665 ps
T715 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1072087137 Jun 23 07:50:24 PM PDT 24 Jun 23 07:54:03 PM PDT 24 2566143640 ps
T737 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2078029048 Jun 23 08:21:05 PM PDT 24 Jun 23 08:29:17 PM PDT 24 3689015128 ps
T1328 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4011552442 Jun 23 08:12:14 PM PDT 24 Jun 23 08:53:39 PM PDT 24 12682109762 ps
T1329 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.847712887 Jun 23 07:48:43 PM PDT 24 Jun 23 08:06:52 PM PDT 24 5847302897 ps
T1330 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1567130908 Jun 23 07:50:29 PM PDT 24 Jun 23 07:56:45 PM PDT 24 3117355204 ps
T1331 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.790151158 Jun 23 07:53:55 PM PDT 24 Jun 23 08:03:20 PM PDT 24 3174893756 ps
T341 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2654478397 Jun 23 08:04:04 PM PDT 24 Jun 23 08:16:05 PM PDT 24 4112057960 ps
T1332 /workspace/coverage/default/2.chip_sw_otbn_randomness.2850953147 Jun 23 08:09:46 PM PDT 24 Jun 23 08:24:45 PM PDT 24 5886795564 ps
T324 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2758562248 Jun 23 08:06:06 PM PDT 24 Jun 23 08:14:15 PM PDT 24 3253217704 ps
T1333 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3622831719 Jun 23 08:12:10 PM PDT 24 Jun 23 08:21:53 PM PDT 24 3762820860 ps
T1334 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.182849705 Jun 23 07:57:12 PM PDT 24 Jun 23 08:01:00 PM PDT 24 2635048408 ps
T1335 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1971426117 Jun 23 08:13:18 PM PDT 24 Jun 23 08:26:37 PM PDT 24 7313037274 ps
T725 /workspace/coverage/default/1.chip_sw_power_sleep_load.157621993 Jun 23 08:06:03 PM PDT 24 Jun 23 08:13:48 PM PDT 24 4562930668 ps
T1336 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3690294223 Jun 23 08:11:58 PM PDT 24 Jun 23 08:22:00 PM PDT 24 5152483432 ps
T1337 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2333507187 Jun 23 08:01:24 PM PDT 24 Jun 23 08:20:19 PM PDT 24 9446432760 ps
T1338 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1615411869 Jun 23 08:26:29 PM PDT 24 Jun 23 08:31:07 PM PDT 24 2575937212 ps
T1339 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1978126927 Jun 23 07:52:28 PM PDT 24 Jun 23 08:28:41 PM PDT 24 9763322672 ps
T1340 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1399051257 Jun 23 08:14:26 PM PDT 24 Jun 23 08:20:52 PM PDT 24 3604010312 ps
T14 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2648504751 Jun 23 07:50:29 PM PDT 24 Jun 23 07:55:33 PM PDT 24 4250414800 ps
T300 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3807038759 Jun 23 07:50:55 PM PDT 24 Jun 23 08:05:12 PM PDT 24 7631932061 ps
T1341 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2946239039 Jun 23 07:53:33 PM PDT 24 Jun 23 07:58:12 PM PDT 24 2841437444 ps
T1342 /workspace/coverage/default/1.chip_sw_csrng_smoketest.1420750971 Jun 23 08:10:17 PM PDT 24 Jun 23 08:14:53 PM PDT 24 2565869032 ps
T192 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3354234175 Jun 23 08:07:15 PM PDT 24 Jun 23 08:24:14 PM PDT 24 7768114023 ps
T1343 /workspace/coverage/default/26.chip_sw_all_escalation_resets.2770000037 Jun 23 08:21:26 PM PDT 24 Jun 23 08:33:00 PM PDT 24 6029675948 ps
T789 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3877118948 Jun 23 08:12:10 PM PDT 24 Jun 23 08:19:15 PM PDT 24 3840647170 ps
T1344 /workspace/coverage/default/1.chip_sw_uart_tx_rx.2816532122 Jun 23 07:55:21 PM PDT 24 Jun 23 08:06:55 PM PDT 24 4424730264 ps
T47 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.234764600 Jun 23 07:54:32 PM PDT 24 Jun 23 07:58:48 PM PDT 24 3028211644 ps
T777 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1883108817 Jun 23 08:22:02 PM PDT 24 Jun 23 08:30:20 PM PDT 24 3961289450 ps
T1345 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3867030469 Jun 23 07:53:54 PM PDT 24 Jun 23 08:03:38 PM PDT 24 7033265680 ps
T1346 /workspace/coverage/default/4.chip_sw_uart_tx_rx.838736692 Jun 23 08:18:10 PM PDT 24 Jun 23 08:28:20 PM PDT 24 3733577472 ps
T1347 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2581183217 Jun 23 07:50:04 PM PDT 24 Jun 23 08:51:06 PM PDT 24 16997104900 ps
T1348 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3947447974 Jun 23 08:02:26 PM PDT 24 Jun 23 08:11:34 PM PDT 24 6910719232 ps
T1349 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.701179381 Jun 23 08:11:09 PM PDT 24 Jun 23 11:21:18 PM PDT 24 255062603848 ps
T302 /workspace/coverage/default/60.chip_sw_all_escalation_resets.148507752 Jun 23 08:22:29 PM PDT 24 Jun 23 08:29:47 PM PDT 24 5599175000 ps
T1350 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3455791561 Jun 23 07:56:17 PM PDT 24 Jun 23 09:28:47 PM PDT 24 49858907280 ps
T1351 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3779281745 Jun 23 08:23:09 PM PDT 24 Jun 23 08:30:06 PM PDT 24 2947612376 ps
T1352 /workspace/coverage/default/80.chip_sw_all_escalation_resets.878294883 Jun 23 08:24:13 PM PDT 24 Jun 23 08:34:07 PM PDT 24 5947678096 ps
T1353 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2220097966 Jun 23 07:49:24 PM PDT 24 Jun 23 08:01:15 PM PDT 24 3961065920 ps
T1354 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1789676523 Jun 23 08:00:14 PM PDT 24 Jun 23 08:09:47 PM PDT 24 5061026327 ps
T1355 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1592532293 Jun 23 07:52:04 PM PDT 24 Jun 23 08:04:36 PM PDT 24 4790673007 ps
T1356 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.974140250 Jun 23 08:09:40 PM PDT 24 Jun 23 08:22:04 PM PDT 24 6021730036 ps
T1357 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3459502726 Jun 23 07:58:11 PM PDT 24 Jun 23 08:03:18 PM PDT 24 2951693410 ps
T754 /workspace/coverage/default/2.chip_sw_all_escalation_resets.1762327017 Jun 23 08:08:18 PM PDT 24 Jun 23 08:21:51 PM PDT 24 5889617250 ps
T1358 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4211725010 Jun 23 08:12:02 PM PDT 24 Jun 23 08:23:26 PM PDT 24 4490712452 ps
T1359 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.875391545 Jun 23 07:50:43 PM PDT 24 Jun 23 08:00:02 PM PDT 24 7844062010 ps
T151 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3032822130 Jun 23 07:49:00 PM PDT 24 Jun 23 10:46:51 PM PDT 24 58428127193 ps
T821 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.828252162 Jun 23 08:25:38 PM PDT 24 Jun 23 08:32:07 PM PDT 24 4026138682 ps
T1360 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.154957224 Jun 23 07:57:15 PM PDT 24 Jun 23 09:01:36 PM PDT 24 17907021038 ps
T133 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4037338814 Jun 23 08:18:15 PM PDT 24 Jun 23 08:27:28 PM PDT 24 5132628904 ps
T158 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4137467222 Jun 23 07:56:47 PM PDT 24 Jun 23 07:58:32 PM PDT 24 1735400771 ps
T1361 /workspace/coverage/default/0.chip_sw_csrng_kat_test.1254610896 Jun 23 07:51:06 PM PDT 24 Jun 23 07:55:31 PM PDT 24 2229062096 ps
T70 /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.3414349258 Jun 23 07:32:40 PM PDT 24 Jun 23 07:32:46 PM PDT 24 67598428 ps
T71 /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.811485543 Jun 23 07:23:41 PM PDT 24 Jun 23 07:25:18 PM PDT 24 1361280336 ps
T72 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2806978679 Jun 23 07:29:34 PM PDT 24 Jun 23 07:38:14 PM PDT 24 9525862440 ps
T77 /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.4140877733 Jun 23 07:40:52 PM PDT 24 Jun 23 07:42:27 PM PDT 24 1369960181 ps
T356 /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1390979639 Jun 23 07:33:52 PM PDT 24 Jun 23 07:39:49 PM PDT 24 11214660913 ps
T416 /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3714974541 Jun 23 07:37:35 PM PDT 24 Jun 23 07:57:38 PM PDT 24 120747645853 ps
T704 /workspace/coverage/cover_reg_top/89.xbar_access_same_device.221964565 Jun 23 07:39:33 PM PDT 24 Jun 23 07:40:25 PM PDT 24 632176402 ps
T510 /workspace/coverage/cover_reg_top/22.xbar_error_random.3614890981 Jun 23 07:26:57 PM PDT 24 Jun 23 07:27:36 PM PDT 24 961246676 ps
T426 /workspace/coverage/cover_reg_top/32.xbar_same_source.2505837527 Jun 23 07:29:16 PM PDT 24 Jun 23 07:29:51 PM PDT 24 1137611142 ps
T142 /workspace/coverage/cover_reg_top/4.chip_csr_rw.2071467829 Jun 23 07:21:30 PM PDT 24 Jun 23 07:33:02 PM PDT 24 6207831214 ps
T507 /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.4274348097 Jun 23 07:30:39 PM PDT 24 Jun 23 07:35:42 PM PDT 24 2982662058 ps
T750 /workspace/coverage/cover_reg_top/7.xbar_access_same_device.4230256588 Jun 23 07:22:20 PM PDT 24 Jun 23 07:22:31 PM PDT 24 153032520 ps
T509 /workspace/coverage/cover_reg_top/66.xbar_access_same_device.614109404 Jun 23 07:35:41 PM PDT 24 Jun 23 07:37:52 PM PDT 24 3308314125 ps
T512 /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.310217614 Jun 23 07:41:00 PM PDT 24 Jun 23 07:41:28 PM PDT 24 564085483 ps
T427 /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.3272871854 Jun 23 07:22:08 PM PDT 24 Jun 23 07:23:41 PM PDT 24 8746043385 ps
T514 /workspace/coverage/cover_reg_top/47.xbar_same_source.303281252 Jun 23 07:32:35 PM PDT 24 Jun 23 07:32:43 PM PDT 24 80227538 ps
T466 /workspace/coverage/cover_reg_top/77.xbar_random.3659507439 Jun 23 07:37:33 PM PDT 24 Jun 23 07:37:48 PM PDT 24 118276306 ps
T484 /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1312950101 Jun 23 07:30:41 PM PDT 24 Jun 23 07:37:27 PM PDT 24 5204545946 ps
T513 /workspace/coverage/cover_reg_top/68.xbar_smoke.2347124354 Jun 23 07:35:51 PM PDT 24 Jun 23 07:36:00 PM PDT 24 215811514 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%