Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.23 95.53 94.17 95.47 95.13 97.53 99.57


Total test records in report: 2882
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html
T1075 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3508184694 Jun 23 07:48:46 PM PDT 24 Jun 23 08:00:30 PM PDT 24 4430561512 ps
T231 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1251449701 Jun 23 07:49:52 PM PDT 24 Jun 23 09:27:55 PM PDT 24 47352733012 ps
T69 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1145513768 Jun 23 07:50:25 PM PDT 24 Jun 23 07:59:13 PM PDT 24 4019199308 ps
T1076 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2987402794 Jun 23 07:51:47 PM PDT 24 Jun 23 08:01:14 PM PDT 24 4849190096 ps
T95 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1849802299 Jun 23 07:53:31 PM PDT 24 Jun 23 08:24:05 PM PDT 24 22433639400 ps
T1077 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1300630106 Jun 23 07:50:46 PM PDT 24 Jun 23 09:04:19 PM PDT 24 18728886007 ps
T1078 /workspace/coverage/default/0.chip_sw_edn_kat.1028734396 Jun 23 07:53:34 PM PDT 24 Jun 23 08:02:26 PM PDT 24 3499621560 ps
T1079 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1834677012 Jun 23 07:50:50 PM PDT 24 Jun 23 07:59:15 PM PDT 24 5137317760 ps
T322 /workspace/coverage/default/1.chip_plic_all_irqs_0.1361554494 Jun 23 08:01:00 PM PDT 24 Jun 23 08:22:05 PM PDT 24 6190159480 ps
T757 /workspace/coverage/default/92.chip_sw_all_escalation_resets.4081456634 Jun 23 08:25:51 PM PDT 24 Jun 23 08:36:11 PM PDT 24 5577066936 ps
T1080 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.872364535 Jun 23 07:49:00 PM PDT 24 Jun 23 07:53:34 PM PDT 24 2555921004 ps
T1081 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3413186443 Jun 23 08:01:52 PM PDT 24 Jun 23 08:10:02 PM PDT 24 3341619920 ps
T10 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3780664540 Jun 23 08:02:50 PM PDT 24 Jun 23 08:31:51 PM PDT 24 23576378440 ps
T1082 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2901084806 Jun 23 08:11:41 PM PDT 24 Jun 23 08:19:41 PM PDT 24 5514857686 ps
T141 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2550857264 Jun 23 08:08:33 PM PDT 24 Jun 23 08:17:17 PM PDT 24 6480817906 ps
T241 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3124656342 Jun 23 08:01:06 PM PDT 24 Jun 23 08:07:00 PM PDT 24 3253566190 ps
T1083 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3790903198 Jun 23 07:50:25 PM PDT 24 Jun 23 07:56:08 PM PDT 24 3606226176 ps
T1084 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.310692781 Jun 23 08:11:27 PM PDT 24 Jun 23 08:15:46 PM PDT 24 2842118596 ps
T780 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3593791923 Jun 23 08:22:21 PM PDT 24 Jun 23 08:28:17 PM PDT 24 3913464240 ps
T240 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2002544495 Jun 23 08:22:12 PM PDT 24 Jun 23 08:28:28 PM PDT 24 3763978120 ps
T286 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1166062577 Jun 23 08:21:14 PM PDT 24 Jun 23 08:29:25 PM PDT 24 4335298752 ps
T287 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3277381054 Jun 23 07:55:31 PM PDT 24 Jun 23 08:00:46 PM PDT 24 3247732280 ps
T288 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1596258016 Jun 23 07:59:02 PM PDT 24 Jun 23 08:12:21 PM PDT 24 8301149208 ps
T289 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2679750455 Jun 23 07:48:29 PM PDT 24 Jun 23 07:58:12 PM PDT 24 3684824984 ps
T290 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.487932865 Jun 23 08:08:25 PM PDT 24 Jun 23 09:07:40 PM PDT 24 30615852294 ps
T232 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1829648203 Jun 23 08:09:28 PM PDT 24 Jun 23 08:16:55 PM PDT 24 5167871444 ps
T291 /workspace/coverage/default/97.chip_sw_all_escalation_resets.393219507 Jun 23 08:26:47 PM PDT 24 Jun 23 08:37:18 PM PDT 24 5062841206 ps
T292 /workspace/coverage/default/0.chip_sw_example_flash.1609772428 Jun 23 07:50:57 PM PDT 24 Jun 23 07:57:27 PM PDT 24 2882487150 ps
T175 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1148975318 Jun 23 08:06:19 PM PDT 24 Jun 23 09:29:18 PM PDT 24 43550818231 ps
T425 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3690717566 Jun 23 07:50:23 PM PDT 24 Jun 23 08:10:06 PM PDT 24 7585996781 ps
T1085 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.497561646 Jun 23 07:57:55 PM PDT 24 Jun 23 08:02:56 PM PDT 24 5604361740 ps
T1086 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2040478884 Jun 23 07:53:46 PM PDT 24 Jun 23 08:11:32 PM PDT 24 5635294050 ps
T1087 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1333456828 Jun 23 08:11:16 PM PDT 24 Jun 23 08:52:23 PM PDT 24 11303207592 ps
T1088 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2209023606 Jun 23 08:12:05 PM PDT 24 Jun 23 08:20:35 PM PDT 24 4632868450 ps
T727 /workspace/coverage/default/2.chip_sw_power_idle_load.443875803 Jun 23 08:15:09 PM PDT 24 Jun 23 08:25:44 PM PDT 24 4531590704 ps
T359 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3261422602 Jun 23 08:02:41 PM PDT 24 Jun 23 08:13:12 PM PDT 24 5644968528 ps
T1089 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3701620502 Jun 23 07:59:16 PM PDT 24 Jun 23 08:22:08 PM PDT 24 7834438624 ps
T179 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4243746210 Jun 23 07:48:22 PM PDT 24 Jun 23 09:14:24 PM PDT 24 44948653016 ps
T745 /workspace/coverage/default/94.chip_sw_all_escalation_resets.1034393469 Jun 23 08:25:52 PM PDT 24 Jun 23 08:35:21 PM PDT 24 5687671944 ps
T794 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.698969877 Jun 23 08:28:04 PM PDT 24 Jun 23 08:35:57 PM PDT 24 3335376936 ps
T323 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2036270891 Jun 23 07:48:55 PM PDT 24 Jun 23 08:00:34 PM PDT 24 4576761976 ps
T1090 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.238708483 Jun 23 08:10:04 PM PDT 24 Jun 23 08:28:44 PM PDT 24 5572911448 ps
T773 /workspace/coverage/default/30.chip_sw_all_escalation_resets.3597894717 Jun 23 08:20:29 PM PDT 24 Jun 23 08:29:36 PM PDT 24 5283860516 ps
T1091 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.909889531 Jun 23 08:19:58 PM PDT 24 Jun 23 08:37:22 PM PDT 24 9870115977 ps
T386 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.4088477256 Jun 23 08:14:02 PM PDT 24 Jun 23 08:16:34 PM PDT 24 2341865970 ps
T1092 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1237781199 Jun 23 07:50:49 PM PDT 24 Jun 23 08:00:08 PM PDT 24 5213582220 ps
T1093 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3443113366 Jun 23 07:49:07 PM PDT 24 Jun 23 08:39:48 PM PDT 24 29076454284 ps
T253 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3127719896 Jun 23 08:20:22 PM PDT 24 Jun 23 08:29:02 PM PDT 24 4800446736 ps
T826 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2050254851 Jun 23 08:21:33 PM PDT 24 Jun 23 08:28:45 PM PDT 24 3804629632 ps
T834 /workspace/coverage/default/36.chip_sw_all_escalation_resets.1935175148 Jun 23 08:23:06 PM PDT 24 Jun 23 08:35:01 PM PDT 24 4288344620 ps
T1094 /workspace/coverage/default/2.chip_sw_flash_crash_alert.425059218 Jun 23 08:15:04 PM PDT 24 Jun 23 08:27:43 PM PDT 24 5435801650 ps
T1095 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4034181342 Jun 23 08:19:48 PM PDT 24 Jun 23 08:40:14 PM PDT 24 8809613756 ps
T1096 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1889245484 Jun 23 08:10:57 PM PDT 24 Jun 23 08:14:55 PM PDT 24 2233819288 ps
T1097 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3109038846 Jun 23 07:49:53 PM PDT 24 Jun 23 08:29:56 PM PDT 24 11723485573 ps
T1098 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1477763523 Jun 23 08:10:05 PM PDT 24 Jun 23 08:40:55 PM PDT 24 7754488736 ps
T730 /workspace/coverage/default/1.chip_sw_pattgen_ios.167637279 Jun 23 07:55:16 PM PDT 24 Jun 23 08:00:42 PM PDT 24 3076058212 ps
T1099 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1185047600 Jun 23 07:55:57 PM PDT 24 Jun 23 08:01:10 PM PDT 24 3473386054 ps
T817 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2716253757 Jun 23 08:24:43 PM PDT 24 Jun 23 08:29:29 PM PDT 24 3700142400 ps
T227 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3061439386 Jun 23 07:59:42 PM PDT 24 Jun 23 09:11:38 PM PDT 24 16341086838 ps
T1100 /workspace/coverage/default/2.chip_tap_straps_dev.2580106971 Jun 23 08:12:00 PM PDT 24 Jun 23 08:25:07 PM PDT 24 7042326081 ps
T1101 /workspace/coverage/default/1.chip_sw_aes_masking_off.3265872113 Jun 23 07:57:03 PM PDT 24 Jun 23 08:03:39 PM PDT 24 3081092181 ps
T162 /workspace/coverage/default/68.chip_sw_all_escalation_resets.3748133657 Jun 23 08:23:20 PM PDT 24 Jun 23 08:35:17 PM PDT 24 6202462800 ps
T1102 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.469416449 Jun 23 08:06:05 PM PDT 24 Jun 23 08:36:36 PM PDT 24 7514751044 ps
T1103 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3168137584 Jun 23 08:17:24 PM PDT 24 Jun 23 08:24:09 PM PDT 24 4432088590 ps
T1104 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1562988129 Jun 23 08:11:01 PM PDT 24 Jun 23 08:32:48 PM PDT 24 7670867080 ps
T1105 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2920377546 Jun 23 07:53:57 PM PDT 24 Jun 23 07:59:36 PM PDT 24 2778155940 ps
T236 /workspace/coverage/default/0.chip_sw_flash_init.2431965513 Jun 23 07:52:02 PM PDT 24 Jun 23 08:24:18 PM PDT 24 22284981460 ps
T839 /workspace/coverage/default/5.chip_sw_all_escalation_resets.197199633 Jun 23 08:18:47 PM PDT 24 Jun 23 08:32:21 PM PDT 24 6093559852 ps
T281 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1295573952 Jun 23 08:10:36 PM PDT 24 Jun 23 08:20:43 PM PDT 24 4632370121 ps
T320 /workspace/coverage/default/0.chip_plic_all_irqs_0.101973462 Jun 23 07:50:53 PM PDT 24 Jun 23 08:12:51 PM PDT 24 5703618116 ps
T352 /workspace/coverage/default/2.chip_sival_flash_info_access.3201655005 Jun 23 08:06:28 PM PDT 24 Jun 23 08:11:33 PM PDT 24 3353379568 ps
T1106 /workspace/coverage/default/33.chip_sw_all_escalation_resets.1301984200 Jun 23 08:21:50 PM PDT 24 Jun 23 08:31:01 PM PDT 24 4251113408 ps
T1107 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.626264188 Jun 23 07:55:56 PM PDT 24 Jun 23 08:02:51 PM PDT 24 4507313037 ps
T686 /workspace/coverage/default/0.chip_sw_edn_boot_mode.1802039309 Jun 23 07:51:26 PM PDT 24 Jun 23 07:58:39 PM PDT 24 2988688400 ps
T191 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.654439096 Jun 23 07:53:42 PM PDT 24 Jun 23 08:07:02 PM PDT 24 6251980967 ps
T1108 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.44697278 Jun 23 07:49:53 PM PDT 24 Jun 23 07:59:58 PM PDT 24 19118432028 ps
T1109 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3938685262 Jun 23 08:07:46 PM PDT 24 Jun 23 08:19:56 PM PDT 24 10247774061 ps
T785 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2734008785 Jun 23 08:26:11 PM PDT 24 Jun 23 08:32:51 PM PDT 24 3679758600 ps
T1110 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3393268508 Jun 23 08:05:44 PM PDT 24 Jun 23 08:23:55 PM PDT 24 8177185876 ps
T11 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4293870131 Jun 23 08:12:56 PM PDT 24 Jun 23 08:41:35 PM PDT 24 21299407688 ps
T1111 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.283559549 Jun 23 07:52:24 PM PDT 24 Jun 23 08:13:46 PM PDT 24 7217685003 ps
T1112 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1140957707 Jun 23 07:51:34 PM PDT 24 Jun 23 08:10:54 PM PDT 24 6073245868 ps
T1113 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3649245229 Jun 23 07:58:34 PM PDT 24 Jun 23 08:15:06 PM PDT 24 6251411283 ps
T1114 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1516113929 Jun 23 07:50:46 PM PDT 24 Jun 23 08:01:56 PM PDT 24 8786327466 ps
T1115 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2433613666 Jun 23 08:11:42 PM PDT 24 Jun 23 08:36:05 PM PDT 24 8199364232 ps
T1116 /workspace/coverage/default/1.chip_sw_kmac_idle.4193092825 Jun 23 08:02:30 PM PDT 24 Jun 23 08:07:02 PM PDT 24 2660950360 ps
T203 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3785956311 Jun 23 08:10:00 PM PDT 24 Jun 23 08:41:47 PM PDT 24 23953671534 ps
T1117 /workspace/coverage/default/1.chip_sw_kmac_smoketest.2929937581 Jun 23 08:05:26 PM PDT 24 Jun 23 08:10:41 PM PDT 24 2461649270 ps
T1118 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2399559484 Jun 23 08:23:03 PM PDT 24 Jun 23 08:29:48 PM PDT 24 4093811748 ps
T1119 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3781743401 Jun 23 08:21:51 PM PDT 24 Jun 23 08:31:28 PM PDT 24 5261618248 ps
T1120 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2939287343 Jun 23 08:01:53 PM PDT 24 Jun 23 08:13:15 PM PDT 24 5423784586 ps
T1121 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.321522239 Jun 23 08:03:41 PM PDT 24 Jun 23 08:10:40 PM PDT 24 3557225564 ps
T751 /workspace/coverage/default/58.chip_sw_all_escalation_resets.1911579033 Jun 23 08:25:19 PM PDT 24 Jun 23 08:34:13 PM PDT 24 5375657208 ps
T1122 /workspace/coverage/default/0.rom_e2e_static_critical.3558813285 Jun 23 08:02:27 PM PDT 24 Jun 23 09:25:51 PM PDT 24 16997192028 ps
T1123 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3026351209 Jun 23 07:57:03 PM PDT 24 Jun 23 08:55:22 PM PDT 24 15524171432 ps
T1124 /workspace/coverage/default/0.chip_sw_edn_sw_mode.194976417 Jun 23 07:52:20 PM PDT 24 Jun 23 08:32:59 PM PDT 24 10115802650 ps
T1125 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.236636851 Jun 23 08:11:14 PM PDT 24 Jun 23 09:39:01 PM PDT 24 25869495420 ps
T1126 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.260737737 Jun 23 08:08:00 PM PDT 24 Jun 23 08:32:09 PM PDT 24 8551829800 ps
T107 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3609068799 Jun 23 07:54:10 PM PDT 24 Jun 23 09:20:19 PM PDT 24 26153387251 ps
T1127 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1881399541 Jun 23 08:04:33 PM PDT 24 Jun 23 08:08:55 PM PDT 24 2550297876 ps
T1128 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.7112867 Jun 23 07:55:12 PM PDT 24 Jun 23 08:06:57 PM PDT 24 4067391608 ps
T1129 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4030163986 Jun 23 08:10:54 PM PDT 24 Jun 23 08:31:09 PM PDT 24 6582710153 ps
T269 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3746265323 Jun 23 07:55:33 PM PDT 24 Jun 23 08:10:06 PM PDT 24 5854065840 ps
T350 /workspace/coverage/default/1.chip_sw_aon_timer_irq.3695999329 Jun 23 07:57:28 PM PDT 24 Jun 23 08:04:35 PM PDT 24 3776783208 ps
T81 /workspace/coverage/default/1.chip_sw_gpio_smoketest.291921532 Jun 23 08:04:47 PM PDT 24 Jun 23 08:09:03 PM PDT 24 2676265225 ps
T1130 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3576691288 Jun 23 08:05:50 PM PDT 24 Jun 23 08:10:25 PM PDT 24 5758999020 ps
T781 /workspace/coverage/default/38.chip_sw_all_escalation_resets.1903769 Jun 23 08:21:00 PM PDT 24 Jun 23 08:32:26 PM PDT 24 6065723446 ps
T776 /workspace/coverage/default/75.chip_sw_all_escalation_resets.3346171568 Jun 23 08:26:38 PM PDT 24 Jun 23 08:35:36 PM PDT 24 4978371352 ps
T126 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2782830091 Jun 23 08:01:24 PM PDT 24 Jun 23 08:10:42 PM PDT 24 5400997260 ps
T96 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1368576667 Jun 23 08:13:02 PM PDT 24 Jun 23 08:21:53 PM PDT 24 7930394396 ps
T1131 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1233129043 Jun 23 08:11:08 PM PDT 24 Jun 23 08:16:43 PM PDT 24 2898827930 ps
T130 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2519033464 Jun 23 08:11:35 PM PDT 24 Jun 23 08:25:07 PM PDT 24 7679327900 ps
T1132 /workspace/coverage/default/1.chip_sw_example_manufacturer.1128903285 Jun 23 07:55:57 PM PDT 24 Jun 23 07:59:31 PM PDT 24 2541731672 ps
T1133 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3255765977 Jun 23 08:14:47 PM PDT 24 Jun 23 08:38:22 PM PDT 24 10402949701 ps
T204 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.401704278 Jun 23 07:56:35 PM PDT 24 Jun 23 08:05:07 PM PDT 24 4912010600 ps
T1134 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1428830587 Jun 23 07:50:46 PM PDT 24 Jun 23 08:14:46 PM PDT 24 9753197676 ps
T1135 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.655660619 Jun 23 08:08:39 PM PDT 24 Jun 23 08:22:40 PM PDT 24 8361215784 ps
T1136 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.683811973 Jun 23 08:01:22 PM PDT 24 Jun 23 09:28:24 PM PDT 24 18563218544 ps
T1137 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3251355464 Jun 23 08:22:50 PM PDT 24 Jun 23 08:31:40 PM PDT 24 5162039320 ps
T1138 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2385312583 Jun 23 07:53:00 PM PDT 24 Jun 23 08:06:15 PM PDT 24 7604546636 ps
T1139 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2128598425 Jun 23 07:49:36 PM PDT 24 Jun 23 08:13:10 PM PDT 24 8417120727 ps
T1140 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3062203211 Jun 23 08:01:32 PM PDT 24 Jun 23 08:13:18 PM PDT 24 6885105146 ps
T1141 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1394430817 Jun 23 07:50:09 PM PDT 24 Jun 23 07:57:33 PM PDT 24 4067131428 ps
T787 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1438455082 Jun 23 08:25:30 PM PDT 24 Jun 23 08:31:35 PM PDT 24 3747722040 ps
T1142 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3114405589 Jun 23 07:57:54 PM PDT 24 Jun 23 08:19:36 PM PDT 24 5469705800 ps
T1143 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1891662873 Jun 23 08:00:02 PM PDT 24 Jun 23 08:19:07 PM PDT 24 6282715221 ps
T1144 /workspace/coverage/default/0.chip_sw_otbn_randomness.3544508001 Jun 23 07:53:36 PM PDT 24 Jun 23 08:10:48 PM PDT 24 5597102312 ps
T1145 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1887831050 Jun 23 08:21:01 PM PDT 24 Jun 23 08:28:15 PM PDT 24 3984412100 ps
T1146 /workspace/coverage/default/2.chip_sw_kmac_smoketest.575877067 Jun 23 08:15:41 PM PDT 24 Jun 23 08:19:59 PM PDT 24 3112483430 ps
T315 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.758302498 Jun 23 08:10:36 PM PDT 24 Jun 23 08:39:08 PM PDT 24 9828667838 ps
T254 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1853995375 Jun 23 07:52:27 PM PDT 24 Jun 23 08:05:03 PM PDT 24 7361992056 ps
T1147 /workspace/coverage/default/1.chip_sw_hmac_enc.1698215591 Jun 23 08:00:09 PM PDT 24 Jun 23 08:04:46 PM PDT 24 2742828830 ps
T1148 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.817416814 Jun 23 08:18:33 PM PDT 24 Jun 23 09:48:17 PM PDT 24 25950176484 ps
T1149 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.32134886 Jun 23 07:53:37 PM PDT 24 Jun 23 08:27:10 PM PDT 24 17732152121 ps
T1150 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2608998057 Jun 23 08:09:17 PM PDT 24 Jun 23 08:14:28 PM PDT 24 2948634672 ps
T1151 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3743163652 Jun 23 08:15:26 PM PDT 24 Jun 23 08:20:49 PM PDT 24 3111776540 ps
T1152 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1117134493 Jun 23 08:15:45 PM PDT 24 Jun 23 08:20:10 PM PDT 24 2686621212 ps
T1153 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1792312694 Jun 23 08:17:45 PM PDT 24 Jun 23 08:25:52 PM PDT 24 6587741376 ps
T1154 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.52750882 Jun 23 07:55:32 PM PDT 24 Jun 23 09:32:28 PM PDT 24 49370933242 ps
T1155 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1463747335 Jun 23 08:00:19 PM PDT 24 Jun 23 08:04:08 PM PDT 24 2644933940 ps
T74 /workspace/coverage/default/0.chip_jtag_csr_rw.1926883117 Jun 23 07:43:09 PM PDT 24 Jun 23 08:04:47 PM PDT 24 10610563248 ps
T270 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3594035845 Jun 23 07:48:09 PM PDT 24 Jun 23 08:05:51 PM PDT 24 6131926412 ps
T354 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1067457542 Jun 23 07:54:53 PM PDT 24 Jun 23 08:00:09 PM PDT 24 2789816788 ps
T1156 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2141647163 Jun 23 07:51:47 PM PDT 24 Jun 23 07:56:29 PM PDT 24 3310237178 ps
T820 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441708908 Jun 23 08:21:49 PM PDT 24 Jun 23 08:27:11 PM PDT 24 3126931640 ps
T1157 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.58730862 Jun 23 08:03:25 PM PDT 24 Jun 23 08:07:36 PM PDT 24 3212790287 ps
T1158 /workspace/coverage/default/0.rom_e2e_asm_init_rma.1870896744 Jun 23 07:59:15 PM PDT 24 Jun 23 08:57:38 PM PDT 24 14939155260 ps
T1159 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.224970432 Jun 23 07:50:57 PM PDT 24 Jun 23 08:16:53 PM PDT 24 7432183548 ps
T1160 /workspace/coverage/default/1.chip_sw_rv_timer_irq.3597770252 Jun 23 07:56:55 PM PDT 24 Jun 23 08:00:13 PM PDT 24 2411346600 ps
T1161 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1788702025 Jun 23 07:51:51 PM PDT 24 Jun 23 08:00:34 PM PDT 24 7922146312 ps
T242 /workspace/coverage/default/0.chip_sw_plic_sw_irq.2233088734 Jun 23 07:50:34 PM PDT 24 Jun 23 07:54:15 PM PDT 24 2703449780 ps
T50 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2158420050 Jun 23 07:57:44 PM PDT 24 Jun 23 08:05:01 PM PDT 24 7041203440 ps
T318 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1718232508 Jun 23 08:11:31 PM PDT 24 Jun 23 08:38:57 PM PDT 24 7847646168 ps
T1162 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1705119152 Jun 23 08:02:17 PM PDT 24 Jun 23 08:13:59 PM PDT 24 3841102284 ps
T1163 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.965458414 Jun 23 07:50:17 PM PDT 24 Jun 23 08:01:45 PM PDT 24 4114740100 ps
T830 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1985500727 Jun 23 08:20:53 PM PDT 24 Jun 23 08:28:47 PM PDT 24 4248926056 ps
T1164 /workspace/coverage/default/1.chip_sw_power_idle_load.3129218458 Jun 23 08:04:17 PM PDT 24 Jun 23 08:17:30 PM PDT 24 4400033460 ps
T1165 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1159288511 Jun 23 07:51:01 PM PDT 24 Jun 23 08:00:58 PM PDT 24 5732210836 ps
T1166 /workspace/coverage/default/1.chip_tap_straps_testunlock0.115579398 Jun 23 08:03:18 PM PDT 24 Jun 23 08:08:43 PM PDT 24 4009128540 ps
T1167 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2743926190 Jun 23 08:17:25 PM PDT 24 Jun 23 08:37:12 PM PDT 24 8810737062 ps
T1168 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1681439861 Jun 23 07:53:51 PM PDT 24 Jun 23 07:58:09 PM PDT 24 2775067066 ps
T228 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3852040573 Jun 23 08:13:17 PM PDT 24 Jun 23 09:13:54 PM PDT 24 16552398596 ps
T13 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1276105281 Jun 23 07:56:06 PM PDT 24 Jun 23 08:02:42 PM PDT 24 3557061972 ps
T1169 /workspace/coverage/default/0.chip_sw_aes_masking_off.378682440 Jun 23 07:50:49 PM PDT 24 Jun 23 07:56:53 PM PDT 24 2444610158 ps
T1170 /workspace/coverage/default/1.chip_sw_example_flash.3319224325 Jun 23 07:54:23 PM PDT 24 Jun 23 07:57:38 PM PDT 24 2535369368 ps
T1171 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3448219224 Jun 23 08:08:04 PM PDT 24 Jun 23 08:11:35 PM PDT 24 2452628444 ps
T1172 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.235175809 Jun 23 08:18:57 PM PDT 24 Jun 23 09:36:43 PM PDT 24 20466417480 ps
T1173 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2369113776 Jun 23 07:57:40 PM PDT 24 Jun 23 08:02:47 PM PDT 24 2996796092 ps
T224 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.4224430941 Jun 23 08:01:03 PM PDT 24 Jun 23 08:18:26 PM PDT 24 6799733352 ps
T1174 /workspace/coverage/default/2.chip_sw_aes_smoketest.1259568785 Jun 23 08:16:36 PM PDT 24 Jun 23 08:20:50 PM PDT 24 2850076696 ps
T739 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3117342423 Jun 23 08:24:14 PM PDT 24 Jun 23 08:29:07 PM PDT 24 3434636104 ps
T1175 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2336497577 Jun 23 07:50:19 PM PDT 24 Jun 23 08:00:30 PM PDT 24 7904484738 ps
T1176 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3385187469 Jun 23 07:58:02 PM PDT 24 Jun 23 09:07:37 PM PDT 24 15129716420 ps
T1177 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.841426542 Jun 23 07:57:50 PM PDT 24 Jun 23 08:03:06 PM PDT 24 2776528977 ps
T762 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119656700 Jun 23 08:24:51 PM PDT 24 Jun 23 08:31:43 PM PDT 24 4437730960 ps
T1178 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3044640506 Jun 23 08:00:02 PM PDT 24 Jun 23 09:07:52 PM PDT 24 15908011124 ps
T399 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1100899691 Jun 23 07:51:37 PM PDT 24 Jun 23 07:58:06 PM PDT 24 5030509714 ps
T1179 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4089985898 Jun 23 07:50:17 PM PDT 24 Jun 23 07:56:42 PM PDT 24 4220747544 ps
T694 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.462781592 Jun 23 07:49:25 PM PDT 24 Jun 23 07:55:46 PM PDT 24 5862490572 ps
T823 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2993453734 Jun 23 08:23:54 PM PDT 24 Jun 23 08:31:18 PM PDT 24 3695238280 ps
T831 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2001947310 Jun 23 08:25:11 PM PDT 24 Jun 23 08:32:45 PM PDT 24 3605829484 ps
T1180 /workspace/coverage/default/1.chip_sw_otbn_randomness.2800147790 Jun 23 07:57:59 PM PDT 24 Jun 23 08:14:49 PM PDT 24 6297334162 ps
T1181 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.664103768 Jun 23 08:19:54 PM PDT 24 Jun 23 08:41:50 PM PDT 24 8337209992 ps
T1182 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.276864809 Jun 23 07:54:18 PM PDT 24 Jun 23 08:11:41 PM PDT 24 8375877936 ps
T1183 /workspace/coverage/default/2.chip_sw_flash_init.3349383884 Jun 23 08:06:55 PM PDT 24 Jun 23 08:33:51 PM PDT 24 21868819304 ps
T837 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3708630039 Jun 23 08:21:30 PM PDT 24 Jun 23 08:29:06 PM PDT 24 3663522832 ps
T75 /workspace/coverage/default/1.chip_jtag_mem_access.3813473439 Jun 23 07:55:20 PM PDT 24 Jun 23 08:20:30 PM PDT 24 13736176971 ps
T255 /workspace/coverage/default/9.chip_sw_all_escalation_resets.182295088 Jun 23 08:18:14 PM PDT 24 Jun 23 08:26:58 PM PDT 24 5037805160 ps
T1184 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.4024449169 Jun 23 08:28:19 PM PDT 24 Jun 23 08:36:35 PM PDT 24 4921713028 ps
T1185 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4239682963 Jun 23 07:52:08 PM PDT 24 Jun 23 08:18:32 PM PDT 24 9204714448 ps
T1186 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3656397504 Jun 23 07:55:54 PM PDT 24 Jun 23 08:01:34 PM PDT 24 4630362232 ps
T282 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1616693347 Jun 23 08:14:21 PM PDT 24 Jun 23 08:23:13 PM PDT 24 4868773300 ps
T1187 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1819581038 Jun 23 07:50:48 PM PDT 24 Jun 23 08:23:54 PM PDT 24 11068848232 ps
T1188 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3454600735 Jun 23 08:07:32 PM PDT 24 Jun 23 08:31:11 PM PDT 24 8801879236 ps
T1189 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3956641280 Jun 23 08:04:09 PM PDT 24 Jun 23 08:23:32 PM PDT 24 5794113240 ps
T1190 /workspace/coverage/default/1.chip_sw_uart_smoketest.1690249105 Jun 23 08:06:52 PM PDT 24 Jun 23 08:12:39 PM PDT 24 3128803850 ps
T1191 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.104202484 Jun 23 08:08:23 PM PDT 24 Jun 23 08:13:53 PM PDT 24 3303891464 ps
T795 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2454990399 Jun 23 08:20:22 PM PDT 24 Jun 23 08:28:46 PM PDT 24 4317741858 ps
T314 /workspace/coverage/default/1.chip_plic_all_irqs_20.3399992839 Jun 23 08:01:21 PM PDT 24 Jun 23 08:14:20 PM PDT 24 4994739000 ps
T1192 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1563890342 Jun 23 07:54:12 PM PDT 24 Jun 23 10:55:20 PM PDT 24 65358885363 ps
T134 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.340116475 Jun 23 08:00:41 PM PDT 24 Jun 23 08:09:53 PM PDT 24 4859277510 ps
T1193 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1813524217 Jun 23 08:01:06 PM PDT 24 Jun 23 08:32:34 PM PDT 24 8536112200 ps
T1194 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2567384865 Jun 23 07:53:30 PM PDT 24 Jun 23 08:13:50 PM PDT 24 8618145900 ps
T1195 /workspace/coverage/default/1.chip_sw_edn_kat.2726092639 Jun 23 07:58:59 PM PDT 24 Jun 23 08:10:33 PM PDT 24 3670477368 ps
T293 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.324374027 Jun 23 08:03:31 PM PDT 24 Jun 23 08:09:43 PM PDT 24 3099907624 ps
T843 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3735822133 Jun 23 08:24:01 PM PDT 24 Jun 23 08:33:09 PM PDT 24 4866910416 ps
T1196 /workspace/coverage/default/2.chip_sw_hmac_multistream.3760771446 Jun 23 08:11:05 PM PDT 24 Jun 23 08:33:57 PM PDT 24 7173195868 ps
T845 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1528152401 Jun 23 08:25:01 PM PDT 24 Jun 23 08:34:05 PM PDT 24 4963450854 ps
T1197 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1567244621 Jun 23 08:18:03 PM PDT 24 Jun 23 08:27:14 PM PDT 24 3969103186 ps
T1198 /workspace/coverage/default/1.chip_sw_hmac_oneshot.876763250 Jun 23 08:00:17 PM PDT 24 Jun 23 08:06:14 PM PDT 24 3409556116 ps
T1199 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1588080640 Jun 23 08:17:06 PM PDT 24 Jun 23 08:24:18 PM PDT 24 4136991336 ps
T1200 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3750255446 Jun 23 08:07:01 PM PDT 24 Jun 23 08:21:26 PM PDT 24 5743998072 ps
T782 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1767097501 Jun 23 08:24:21 PM PDT 24 Jun 23 08:32:09 PM PDT 24 3521006346 ps
T294 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1597996427 Jun 23 08:14:19 PM PDT 24 Jun 23 08:17:27 PM PDT 24 2589802247 ps
T325 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2525730847 Jun 23 07:55:41 PM PDT 24 Jun 23 08:08:20 PM PDT 24 4969031256 ps
T783 /workspace/coverage/default/81.chip_sw_all_escalation_resets.445084569 Jun 23 08:25:42 PM PDT 24 Jun 23 08:36:11 PM PDT 24 5818139418 ps
T712 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.773043579 Jun 23 08:24:35 PM PDT 24 Jun 23 08:31:14 PM PDT 24 3377809238 ps
T283 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3894325098 Jun 23 07:59:24 PM PDT 24 Jun 23 08:07:54 PM PDT 24 3259532248 ps
T1201 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2777742748 Jun 23 08:12:29 PM PDT 24 Jun 23 08:26:01 PM PDT 24 7535671144 ps
T1202 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2379066226 Jun 23 08:15:00 PM PDT 24 Jun 23 08:34:55 PM PDT 24 5567678490 ps
T1203 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3904525168 Jun 23 08:15:23 PM PDT 24 Jun 23 08:20:43 PM PDT 24 3558453023 ps
T135 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1850274688 Jun 23 08:03:37 PM PDT 24 Jun 23 08:37:47 PM PDT 24 16925351388 ps
T1204 /workspace/coverage/default/1.rom_e2e_static_critical.1296616080 Jun 23 08:08:46 PM PDT 24 Jun 23 09:11:09 PM PDT 24 16570077400 ps
T802 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3166031192 Jun 23 08:24:06 PM PDT 24 Jun 23 08:31:18 PM PDT 24 4085024120 ps
T76 /workspace/coverage/default/2.chip_jtag_csr_rw.1782161070 Jun 23 08:06:06 PM PDT 24 Jun 23 08:13:00 PM PDT 24 3881436150 ps
T1205 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1163453324 Jun 23 07:58:05 PM PDT 24 Jun 23 08:10:27 PM PDT 24 5900352444 ps
T1206 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1895373363 Jun 23 08:08:46 PM PDT 24 Jun 23 08:56:06 PM PDT 24 21269963302 ps
T1207 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.961350072 Jun 23 07:58:37 PM PDT 24 Jun 23 08:06:14 PM PDT 24 3513513460 ps
T1208 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2797322139 Jun 23 08:04:53 PM PDT 24 Jun 23 08:35:15 PM PDT 24 10413427087 ps
T1209 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1954933142 Jun 23 08:09:49 PM PDT 24 Jun 23 09:09:52 PM PDT 24 15322136592 ps
T7 /workspace/coverage/default/1.chip_jtag_csr_rw.1814489329 Jun 23 07:55:21 PM PDT 24 Jun 23 08:41:40 PM PDT 24 22417668988 ps
T403 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1938487833 Jun 23 08:11:54 PM PDT 24 Jun 23 08:21:00 PM PDT 24 3883650620 ps
T404 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.989699059 Jun 23 08:17:17 PM PDT 24 Jun 23 08:25:42 PM PDT 24 6693395005 ps
T405 /workspace/coverage/default/2.chip_sw_edn_kat.876606184 Jun 23 08:10:14 PM PDT 24 Jun 23 08:21:14 PM PDT 24 3700900060 ps
T251 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2235546184 Jun 23 07:58:40 PM PDT 24 Jun 23 08:07:28 PM PDT 24 4229815000 ps
T406 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4292225072 Jun 23 08:19:15 PM PDT 24 Jun 23 08:28:49 PM PDT 24 3843348834 ps
T407 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1271417590 Jun 23 08:26:56 PM PDT 24 Jun 23 08:36:53 PM PDT 24 5795625264 ps
T408 /workspace/coverage/default/2.chip_sw_aes_idle.3176298232 Jun 23 08:09:06 PM PDT 24 Jun 23 08:12:29 PM PDT 24 2560793420 ps
T409 /workspace/coverage/default/0.chip_sw_pattgen_ios.1972312358 Jun 23 07:48:28 PM PDT 24 Jun 23 07:54:15 PM PDT 24 3279147516 ps
T410 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.4228262201 Jun 23 07:58:27 PM PDT 24 Jun 23 08:13:05 PM PDT 24 10989355597 ps
T1210 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1268628359 Jun 23 07:49:36 PM PDT 24 Jun 23 08:00:39 PM PDT 24 7339073628 ps
T1211 /workspace/coverage/default/76.chip_sw_all_escalation_resets.689082409 Jun 23 08:24:09 PM PDT 24 Jun 23 08:32:42 PM PDT 24 4742053056 ps
T824 /workspace/coverage/default/14.chip_sw_all_escalation_resets.1425428898 Jun 23 08:19:19 PM PDT 24 Jun 23 08:29:21 PM PDT 24 6212143516 ps
T1212 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3421460725 Jun 23 08:19:28 PM PDT 24 Jun 23 08:27:25 PM PDT 24 6767115341 ps
T786 /workspace/coverage/default/63.chip_sw_all_escalation_resets.2194073749 Jun 23 08:24:05 PM PDT 24 Jun 23 08:33:14 PM PDT 24 5083196456 ps
T796 /workspace/coverage/default/13.chip_sw_all_escalation_resets.2343250863 Jun 23 08:18:48 PM PDT 24 Jun 23 08:29:21 PM PDT 24 5121214048 ps
T80 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.382401612 Jun 23 08:09:50 PM PDT 24 Jun 23 08:14:51 PM PDT 24 2870969409 ps
T1213 /workspace/coverage/default/1.chip_sw_otbn_smoketest.1613708064 Jun 23 08:05:10 PM PDT 24 Jun 23 08:23:30 PM PDT 24 5106768892 ps
T1214 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1401790133 Jun 23 07:51:46 PM PDT 24 Jun 23 08:08:45 PM PDT 24 5267263420 ps
T1215 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3039588061 Jun 23 08:08:17 PM PDT 24 Jun 23 08:16:10 PM PDT 24 4357866108 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%